| 1 | /* $Id: IEMAll-armv8.cpp 108791 2025-03-28 21:58:31Z vboxsync $ */
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| 2 | /** @file
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| 3 | * IEM - Interpreted Execution Manager - ARMv8 target, miscellaneous.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2011-2024 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 |
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| 29 | /*********************************************************************************************************************************
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| 30 | * Header Files *
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| 31 | *********************************************************************************************************************************/
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| 32 | #define LOG_GROUP LOG_GROUP_IEM
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| 33 | #define VMCPU_INCL_CPUM_GST_CTX
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| 34 | #include <VBox/vmm/iem.h>
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| 35 | #include <VBox/vmm/cpum.h>
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| 36 | #include <VBox/vmm/dbgf.h>
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| 37 | #include "IEMInternal.h"
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| 38 | #include <VBox/vmm/vmcc.h>
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| 39 | #include <VBox/log.h>
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| 40 | #include <iprt/assert.h>
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| 41 | #include <iprt/armv8.h>
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| 42 |
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| 43 |
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| 44 |
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| 45 | /**
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| 46 | * Slow iemCalcExecDbgFlags() code path.
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| 47 | */
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| 48 | uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu)
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| 49 | {
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| 50 | uint32_t fExec = 0;
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| 51 |
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| 52 | #if 0 /** @todo ARM hardware breakpoints/watchpoints. */
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| 53 | /*
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| 54 | * Helper for invalidate the data TLB for breakpoint addresses.
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| 55 | *
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| 56 | * This is to make sure any access to the page will always trigger a TLB
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| 57 | * load for as long as the breakpoint is enabled.
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| 58 | */
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| 59 | #ifdef IEM_WITH_DATA_TLB
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| 60 | # define INVALID_TLB_ENTRY_FOR_BP(a_uValue) do { \
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| 61 | RTGCPTR uTagNoRev = (a_uValue); \
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| 62 | uTagNoRev = IEMTLB_CALC_TAG_NO_REV(pVCpu, uTagNoRev); \
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| 63 | /** @todo do large page accounting */ \
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| 64 | uintptr_t const idxEven = IEMTLB_TAG_TO_EVEN_INDEX(uTagNoRev); \
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| 65 | if (pVCpu->iem.s.DataTlb.aEntries[idxEven].uTag == (uTagNoRev | pVCpu->iem.s.DataTlb.uTlbRevision)) \
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| 66 | pVCpu->iem.s.DataTlb.aEntries[idxEven].uTag = 0; \
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| 67 | if (pVCpu->iem.s.DataTlb.aEntries[idxEven + 1].uTag == (uTagNoRev | pVCpu->iem.s.DataTlb.uTlbRevisionGlobal)) \
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| 68 | pVCpu->iem.s.DataTlb.aEntries[idxEven + 1].uTag = 0; \
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| 69 | } while (0)
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| 70 | #else
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| 71 | # define INVALID_TLB_ENTRY_FOR_BP(a_uValue) do { } while (0)
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| 72 | #endif
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| 73 |
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| 74 | /*
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| 75 | * Process guest breakpoints.
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| 76 | */
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| 77 | #define PROCESS_ONE_BP(a_fDr7, a_iBp, a_uValue) do { \
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| 78 | if (a_fDr7 & X86_DR7_L_G(a_iBp)) \
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| 79 | { \
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| 80 | switch (X86_DR7_GET_RW(a_fDr7, a_iBp)) \
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| 81 | { \
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| 82 | case X86_DR7_RW_EO: \
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| 83 | fExec |= IEM_F_PENDING_BRK_INSTR; \
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| 84 | break; \
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| 85 | case X86_DR7_RW_WO: \
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| 86 | case X86_DR7_RW_RW: \
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| 87 | fExec |= IEM_F_PENDING_BRK_DATA; \
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| 88 | INVALID_TLB_ENTRY_FOR_BP(a_uValue); \
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| 89 | break; \
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| 90 | case X86_DR7_RW_IO: \
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| 91 | fExec |= IEM_F_PENDING_BRK_X86_IO; \
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| 92 | break; \
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| 93 | } \
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| 94 | } \
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| 95 | } while (0)
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| 96 |
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| 97 | uint32_t const fGstDr7 = (uint32_t)pVCpu->cpum.GstCtx.dr[7];
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| 98 | if (fGstDr7 & X86_DR7_ENABLED_MASK)
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| 99 | {
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| 100 | /** @todo extract more details here to simplify matching later. */
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| 101 | #ifdef IEM_WITH_DATA_TLB
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| 102 | IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
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| 103 | #endif
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| 104 | PROCESS_ONE_BP(fGstDr7, 0, pVCpu->cpum.GstCtx.dr[0]);
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| 105 | PROCESS_ONE_BP(fGstDr7, 1, pVCpu->cpum.GstCtx.dr[1]);
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| 106 | PROCESS_ONE_BP(fGstDr7, 2, pVCpu->cpum.GstCtx.dr[2]);
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| 107 | PROCESS_ONE_BP(fGstDr7, 3, pVCpu->cpum.GstCtx.dr[3]);
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| 108 | }
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| 109 |
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| 110 | /*
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| 111 | * Process hypervisor breakpoints.
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| 112 | */
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| 113 | PVMCC const pVM = pVCpu->CTX_SUFF(pVM);
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| 114 | uint32_t const fHyperDr7 = DBGFBpGetDR7(pVM);
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| 115 | if (fHyperDr7 & X86_DR7_ENABLED_MASK)
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| 116 | {
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| 117 | /** @todo extract more details here to simplify matching later. */
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| 118 | PROCESS_ONE_BP(fHyperDr7, 0, DBGFBpGetDR0(pVM));
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| 119 | PROCESS_ONE_BP(fHyperDr7, 1, DBGFBpGetDR1(pVM));
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| 120 | PROCESS_ONE_BP(fHyperDr7, 2, DBGFBpGetDR2(pVM));
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| 121 | PROCESS_ONE_BP(fHyperDr7, 3, DBGFBpGetDR3(pVM));
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| 122 | }
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| 123 | #else
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| 124 | RT_NOREF(pVCpu);
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| 125 | #endif
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| 126 |
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| 127 | return fExec;
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| 128 | }
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| 129 |
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