/* * Autogenerated by $Id: IEMAllInstrA64Impl.h 108958 2025-04-12 00:16:40Z vboxsync $ * from the open source v9Ap6-A specs, build 406 (5e0a212688c6bd7aee92394b6f5e491b4d0fee1d) * dated Sun Dec 15 22:18:44 2024 UTC. * * Do not edit! */ /* * Copyright (C) 2025 Oracle and/or its affiliates. * * This file is part of VirtualBox base platform packages, as * available from https://www.virtualbox.org. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation, in version 3 of the * License. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, see . * * SPDX-License-Identifier: GPL-3.0-only */ /* * * Instruction Set & Groups: addsub_carry / dpreg / A64 * */ /* ADC , , (ffe0fc00/1a000000) */ //#define IEM_INSTR_IMPL_A64__ADC_32_addsub_carry(Rd, Rn, Rm) /* ADCS , , (ffe0fc00/3a000000) */ //#define IEM_INSTR_IMPL_A64__ADCS_32_addsub_carry(Rd, Rn, Rm) /* SBC , , (ffe0fc00/5a000000) */ //#define IEM_INSTR_IMPL_A64__SBC_32_addsub_carry(Rd, Rn, Rm) /* SBCS , , (ffe0fc00/7a000000) */ //#define IEM_INSTR_IMPL_A64__SBCS_32_addsub_carry(Rd, Rn, Rm) /* ADC , , (ffe0fc00/9a000000) */ //#define IEM_INSTR_IMPL_A64__ADC_64_addsub_carry(Rd, Rn, Rm) /* ADCS , , (ffe0fc00/ba000000) */ //#define IEM_INSTR_IMPL_A64__ADCS_64_addsub_carry(Rd, Rn, Rm) /* SBC , , (ffe0fc00/da000000) */ //#define IEM_INSTR_IMPL_A64__SBC_64_addsub_carry(Rd, Rn, Rm) /* SBCS , , (ffe0fc00/fa000000) */ //#define IEM_INSTR_IMPL_A64__SBCS_64_addsub_carry(Rd, Rn, Rm) /* * * Instruction Set & Groups: addsub_ext / dpreg / A64 * */ /* ADD , , {, { #}} (ffe00000/0b200000) */ //#define IEM_INSTR_IMPL_A64__ADD_32_addsub_ext(Rd, Rn, imm3, option, Rm) /* ADDS , , {, { #}} (ffe00000/2b200000) */ //#define IEM_INSTR_IMPL_A64__ADDS_32S_addsub_ext(Rd, Rn, imm3, option, Rm) /* SUB , , {, { #}} (ffe00000/4b200000) */ //#define IEM_INSTR_IMPL_A64__SUB_32_addsub_ext(Rd, Rn, imm3, option, Rm) /* SUBS , , {, { #}} (ffe00000/6b200000) */ //#define IEM_INSTR_IMPL_A64__SUBS_32S_addsub_ext(Rd, Rn, imm3, option, Rm) /* ADD , , {, { #}} (ffe00000/8b200000) */ //#define IEM_INSTR_IMPL_A64__ADD_64_addsub_ext(Rd, Rn, imm3, option, Rm) /* ADDS , , {, { #}} (ffe00000/ab200000) */ //#define IEM_INSTR_IMPL_A64__ADDS_64S_addsub_ext(Rd, Rn, imm3, option, Rm) /* SUB , , {, { #}} (ffe00000/cb200000) */ //#define IEM_INSTR_IMPL_A64__SUB_64_addsub_ext(Rd, Rn, imm3, option, Rm) /* SUBS , , {, { #}} (ffe00000/eb200000) */ //#define IEM_INSTR_IMPL_A64__SUBS_64S_addsub_ext(Rd, Rn, imm3, option, Rm) /* * * Instruction Set & Groups: addsub_imm / dpimm / A64 * */ /* ADD , , #{, } (ff800000/11000000) */ //#define IEM_INSTR_IMPL_A64__ADD_32_addsub_imm(Rd, Rn, imm12, sh) /* ADDS , , #{, } (ff800000/31000000) */ //#define IEM_INSTR_IMPL_A64__ADDS_32S_addsub_imm(Rd, Rn, imm12, sh) /* SUB , , #{, } (ff800000/51000000) */ //#define IEM_INSTR_IMPL_A64__SUB_32_addsub_imm(Rd, Rn, imm12, sh) /* SUBS , , #{, } (ff800000/71000000) */ //#define IEM_INSTR_IMPL_A64__SUBS_32S_addsub_imm(Rd, Rn, imm12, sh) /* ADD , , #{, } (ff800000/91000000) */ //#define IEM_INSTR_IMPL_A64__ADD_64_addsub_imm(Rd, Rn, imm12, sh) /* ADDS , , #{, } (ff800000/b1000000) */ //#define IEM_INSTR_IMPL_A64__ADDS_64S_addsub_imm(Rd, Rn, imm12, sh) /* SUB , , #{, } (ff800000/d1000000) */ //#define IEM_INSTR_IMPL_A64__SUB_64_addsub_imm(Rd, Rn, imm12, sh) /* SUBS , , #{, } (ff800000/f1000000) */ //#define IEM_INSTR_IMPL_A64__SUBS_64S_addsub_imm(Rd, Rn, imm12, sh) /* * * Instruction Set & Groups: addsub_immtags / dpimm / A64 * */ /* ADDG , , #, # (ffc0c000/91800000) */ //#define IEM_INSTR_IMPL_A64__ADDG_64_addsub_immtags(Rd, Rn, imm4, imm6) /* SUBG , , #, # (ffc0c000/d1800000) */ //#define IEM_INSTR_IMPL_A64__SUBG_64_addsub_immtags(Rd, Rn, imm4, imm6) /* * * Instruction Set & Groups: addsub_pt / dpreg / A64 * */ /* ADDPT , , {, LSL #} (ffe0e000/9a002000) */ //#define IEM_INSTR_IMPL_A64__ADDPT_64_addsub_pt(Rd, Rn, imm3, Rm) /* SUBPT , , {, LSL #} (ffe0e000/da002000) */ //#define IEM_INSTR_IMPL_A64__SUBPT_64_addsub_pt(Rd, Rn, imm3, Rm) /* * * Instruction Set & Groups: addsub_shift / dpreg / A64 * */ /* ADD , , {, #} (ff200000/0b000000) */ //#define IEM_INSTR_IMPL_A64__ADD_32_addsub_shift(Rd, Rn, imm6, Rm, shift) /* ADDS , , {, #} (ff200000/2b000000) */ //#define IEM_INSTR_IMPL_A64__ADDS_32_addsub_shift(Rd, Rn, imm6, Rm, shift) /* SUB , , {, #} (ff200000/4b000000) */ //#define IEM_INSTR_IMPL_A64__SUB_32_addsub_shift(Rd, Rn, imm6, Rm, shift) /* SUBS , , {, #} (ff200000/6b000000) */ //#define IEM_INSTR_IMPL_A64__SUBS_32_addsub_shift(Rd, Rn, imm6, Rm, shift) /* ADD , , {, #} (ff200000/8b000000) */ //#define IEM_INSTR_IMPL_A64__ADD_64_addsub_shift(Rd, Rn, imm6, Rm, shift) /* ADDS , , {, #} (ff200000/ab000000) */ //#define IEM_INSTR_IMPL_A64__ADDS_64_addsub_shift(Rd, Rn, imm6, Rm, shift) /* SUB , , {, #} (ff200000/cb000000) */ //#define IEM_INSTR_IMPL_A64__SUB_64_addsub_shift(Rd, Rn, imm6, Rm, shift) /* SUBS , , {, #} (ff200000/eb000000) */ //#define IEM_INSTR_IMPL_A64__SUBS_64_addsub_shift(Rd, Rn, imm6, Rm, shift) /* * * Instruction Set & Groups: asimdall / simd_dp / A64 * */ /* SADDLV , . (bf3ffc00/0e303800) */ //#define IEM_INSTR_IMPL_A64__SADDLV_asimdall_only(Rd, Rn, size, Q) /* SMAXV , . (bf3ffc00/0e30a800) */ //#define IEM_INSTR_IMPL_A64__SMAXV_asimdall_only(Rd, Rn, op, size, Q) /* SMINV , . (bf3ffc00/0e31a800) */ //#define IEM_INSTR_IMPL_A64__SMINV_asimdall_only(Rd, Rn, op, size, Q) /* ADDV , . (bf3ffc00/0e31b800) */ //#define IEM_INSTR_IMPL_A64__ADDV_asimdall_only(Rd, Rn, size, Q) /* FMAXNMV , . (bffffc00/0e30c800) */ //#define IEM_INSTR_IMPL_A64__FMAXNMV_asimdall_only_H(Rd, Rn, o1, Q) /* FMAXV , . (bffffc00/0e30f800) */ //#define IEM_INSTR_IMPL_A64__FMAXV_asimdall_only_H(Rd, Rn, o1, Q) /* FMINNMV , . (bffffc00/0eb0c800) */ //#define IEM_INSTR_IMPL_A64__FMINNMV_asimdall_only_H(Rd, Rn, o1, Q) /* FMINV , . (bffffc00/0eb0f800) */ //#define IEM_INSTR_IMPL_A64__FMINV_asimdall_only_H(Rd, Rn, o1, Q) /* UADDLV , . (bf3ffc00/2e303800) */ //#define IEM_INSTR_IMPL_A64__UADDLV_asimdall_only(Rd, Rn, size, Q) /* UMAXV , . (bf3ffc00/2e30a800) */ //#define IEM_INSTR_IMPL_A64__UMAXV_asimdall_only(Rd, Rn, op, size, Q) /* UMINV , . (bf3ffc00/2e31a800) */ //#define IEM_INSTR_IMPL_A64__UMINV_asimdall_only(Rd, Rn, op, size, Q) /* FMAXNMV S, .4S (fffffc00/6e30c800) */ //#define IEM_INSTR_IMPL_A64__FMAXNMV_asimdall_only_SD(Rd, Rn, sz, o1, Q) /* FMAXV S, .4S (fffffc00/6e30f800) */ //#define IEM_INSTR_IMPL_A64__FMAXV_asimdall_only_SD(Rd, Rn, sz, o1, Q) /* FMINNMV S, .4S (fffffc00/6eb0c800) */ //#define IEM_INSTR_IMPL_A64__FMINNMV_asimdall_only_SD(Rd, Rn, sz, o1, Q) /* FMINV S, .4S (fffffc00/6eb0f800) */ //#define IEM_INSTR_IMPL_A64__FMINV_asimdall_only_SD(Rd, Rn, sz, o1, Q) /* * * Instruction Set & Groups: asimddiff / simd_dp / A64 * */ /* SADDL2 ., ., . (bf20fc00/0e200000) */ //#define IEM_INSTR_IMPL_A64__SADDL_asimddiff_L(Rd, Rn, o1, Rm, size, Q) /* SADDW2 ., ., . (bf20fc00/0e201000) */ //#define IEM_INSTR_IMPL_A64__SADDW_asimddiff_W(Rd, Rn, o1, Rm, size, Q) /* SSUBL2 ., ., . (bf20fc00/0e202000) */ //#define IEM_INSTR_IMPL_A64__SSUBL_asimddiff_L(Rd, Rn, o1, Rm, size, Q) /* SSUBW2 ., ., . (bf20fc00/0e203000) */ //#define IEM_INSTR_IMPL_A64__SSUBW_asimddiff_W(Rd, Rn, o1, Rm, size, Q) /* ADDHN2 ., ., . (bf20fc00/0e204000) */ //#define IEM_INSTR_IMPL_A64__ADDHN_asimddiff_N(Rd, Rn, o1, Rm, size, Q) /* SABAL2 ., ., . (bf20fc00/0e205000) */ //#define IEM_INSTR_IMPL_A64__SABAL_asimddiff_L(Rd, Rn, op, Rm, size, Q) /* SUBHN2 ., ., . (bf20fc00/0e206000) */ //#define IEM_INSTR_IMPL_A64__SUBHN_asimddiff_N(Rd, Rn, o1, Rm, size, Q) /* SABDL2 ., ., . (bf20fc00/0e207000) */ //#define IEM_INSTR_IMPL_A64__SABDL_asimddiff_L(Rd, Rn, op, Rm, size, Q) /* SMLAL2 ., ., . (bf20fc00/0e208000) */ //#define IEM_INSTR_IMPL_A64__SMLAL_asimddiff_L(Rd, Rn, o1, Rm, size, Q) /* SQDMLAL2 ., ., . (bf20fc00/0e209000) */ //#define IEM_INSTR_IMPL_A64__SQDMLAL_asimddiff_L(Rd, Rn, o1, Rm, size, Q) /* SMLSL2 ., ., . (bf20fc00/0e20a000) */ //#define IEM_INSTR_IMPL_A64__SMLSL_asimddiff_L(Rd, Rn, o1, Rm, size, Q) /* SQDMLSL2 ., ., . (bf20fc00/0e20b000) */ //#define IEM_INSTR_IMPL_A64__SQDMLSL_asimddiff_L(Rd, Rn, o1, Rm, size, Q) /* SMULL2 ., ., . (bf20fc00/0e20c000) */ //#define IEM_INSTR_IMPL_A64__SMULL_asimddiff_L(Rd, Rn, Rm, size, Q) /* SQDMULL2 ., ., . (bf20fc00/0e20d000) */ //#define IEM_INSTR_IMPL_A64__SQDMULL_asimddiff_L(Rd, Rn, Rm, size, Q) /* PMULL2 ., ., . (bf20fc00/0e20e000) */ //#define IEM_INSTR_IMPL_A64__PMULL_asimddiff_L(Rd, Rn, Rm, size, Q) /* UADDL2 ., ., . (bf20fc00/2e200000) */ //#define IEM_INSTR_IMPL_A64__UADDL_asimddiff_L(Rd, Rn, o1, Rm, size, Q) /* UADDW2 ., ., . (bf20fc00/2e201000) */ //#define IEM_INSTR_IMPL_A64__UADDW_asimddiff_W(Rd, Rn, o1, Rm, size, Q) /* USUBL2 ., ., . (bf20fc00/2e202000) */ //#define IEM_INSTR_IMPL_A64__USUBL_asimddiff_L(Rd, Rn, o1, Rm, size, Q) /* USUBW2 ., ., . (bf20fc00/2e203000) */ //#define IEM_INSTR_IMPL_A64__USUBW_asimddiff_W(Rd, Rn, o1, Rm, size, Q) /* RADDHN2 ., ., . (bf20fc00/2e204000) */ //#define IEM_INSTR_IMPL_A64__RADDHN_asimddiff_N(Rd, Rn, o1, Rm, size, Q) /* UABAL2 ., ., . (bf20fc00/2e205000) */ //#define IEM_INSTR_IMPL_A64__UABAL_asimddiff_L(Rd, Rn, op, Rm, size, Q) /* RSUBHN2 ., ., . (bf20fc00/2e206000) */ //#define IEM_INSTR_IMPL_A64__RSUBHN_asimddiff_N(Rd, Rn, o1, Rm, size, Q) /* UABDL2 ., ., . (bf20fc00/2e207000) */ //#define IEM_INSTR_IMPL_A64__UABDL_asimddiff_L(Rd, Rn, op, Rm, size, Q) /* UMLAL2 ., ., . (bf20fc00/2e208000) */ //#define IEM_INSTR_IMPL_A64__UMLAL_asimddiff_L(Rd, Rn, o1, Rm, size, Q) /* UMLSL2 ., ., . (bf20fc00/2e20a000) */ //#define IEM_INSTR_IMPL_A64__UMLSL_asimddiff_L(Rd, Rn, o1, Rm, size, Q) /* UMULL2 ., ., . (bf20fc00/2e20c000) */ //#define IEM_INSTR_IMPL_A64__UMULL_asimddiff_L(Rd, Rn, Rm, size, Q) /* * * Instruction Set & Groups: asimdelem / simd_dp / A64 * */ /* SMLAL2 ., ., .[] (bf00f400/0f002000) */ //#define IEM_INSTR_IMPL_A64__SMLAL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q) /* SQDMLAL2 ., ., .[] (bf00f400/0f003000) */ //#define IEM_INSTR_IMPL_A64__SQDMLAL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q) /* SMLSL2 ., ., .[] (bf00f400/0f006000) */ //#define IEM_INSTR_IMPL_A64__SMLSL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q) /* SQDMLSL2 ., ., .[] (bf00f400/0f007000) */ //#define IEM_INSTR_IMPL_A64__SQDMLSL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q) /* MUL ., ., .[] (bf00f400/0f008000) */ //#define IEM_INSTR_IMPL_A64__MUL_asimdelem_R(Rd, Rn, H, Rm, M, L, size, Q) /* SMULL2 ., ., .[] (bf00f400/0f00a000) */ //#define IEM_INSTR_IMPL_A64__SMULL_asimdelem_L(Rd, Rn, H, Rm, M, L, size, Q) /* SQDMULL2 ., ., .[] (bf00f400/0f00b000) */ //#define IEM_INSTR_IMPL_A64__SQDMULL_asimdelem_L(Rd, Rn, H, Rm, M, L, size, Q) /* SQDMULH ., ., .[] (bf00f400/0f00c000) */ //#define IEM_INSTR_IMPL_A64__SQDMULH_asimdelem_R(Rd, Rn, H, op, Rm, M, L, size, Q) /* SQRDMULH ., ., .[] (bf00f400/0f00d000) */ //#define IEM_INSTR_IMPL_A64__SQRDMULH_asimdelem_R(Rd, Rn, H, op, Rm, M, L, size, Q) /* SDOT ., ., .4B[] (bf00f400/0f00e000) */ //#define IEM_INSTR_IMPL_A64__SDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, size, Q) /* FDOT ., ., .4B[] (bfc0f400/0f000000) */ //#define IEM_INSTR_IMPL_A64__FDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, Q) /* FMLA ., ., .H[] (bfc0f400/0f001000) */ //#define IEM_INSTR_IMPL_A64__FMLA_asimdelem_RH_H(Rd, Rn, H, o2, Rm, M, L, Q) /* FMLS ., ., .H[] (bfc0f400/0f005000) */ //#define IEM_INSTR_IMPL_A64__FMLS_asimdelem_RH_H(Rd, Rn, H, o2, Rm, M, L, Q) /* FMUL ., ., .H[] (bfc0f400/0f009000) */ //#define IEM_INSTR_IMPL_A64__FMUL_asimdelem_RH_H(Rd, Rn, H, Rm, M, L, Q) /* SUDOT ., ., .4B[] (bfc0f400/0f00f000) */ //#define IEM_INSTR_IMPL_A64__SUDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, US, Q) /* FDOT ., ., .2B[] (bfc0f400/0f400000) */ //#define IEM_INSTR_IMPL_A64__FDOT_asimdelem_G(Rd, Rn, H, Rm, M, L, Q) /* BFDOT ., ., .2H[] (bfc0f400/0f40f000) */ //#define IEM_INSTR_IMPL_A64__BFDOT_asimdelem_E(Rd, Rn, H, Rm, M, L, Q) /* FMLA ., ., .[] (bf80f400/0f801000) */ //#define IEM_INSTR_IMPL_A64__FMLA_asimdelem_R_SD(Rd, Rn, H, o2, Rm, M, L, sz, Q) /* FMLS ., ., .[] (bf80f400/0f805000) */ //#define IEM_INSTR_IMPL_A64__FMLS_asimdelem_R_SD(Rd, Rn, H, o2, Rm, M, L, sz, Q) /* FMUL ., ., .[] (bf80f400/0f809000) */ //#define IEM_INSTR_IMPL_A64__FMUL_asimdelem_R_SD(Rd, Rn, H, Rm, M, L, sz, Q) /* FMLAL ., ., .H[] (bfc0f400/0f800000) */ //#define IEM_INSTR_IMPL_A64__FMLAL_asimdelem_LH(Rd, Rn, H, S, Rm, M, L, sz, Q) /* FMLSL ., ., .H[] (bfc0f400/0f804000) */ //#define IEM_INSTR_IMPL_A64__FMLSL_asimdelem_LH(Rd, Rn, H, S, Rm, M, L, sz, Q) /* USDOT ., ., .4B[] (bfc0f400/0f80f000) */ //#define IEM_INSTR_IMPL_A64__USDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, US, Q) /* BFMLAL .4S, .8H, .H[] (bfc0f400/0fc0f000) */ //#define IEM_INSTR_IMPL_A64__BFMLAL_asimdelem_F(Rd, Rn, H, Rm, M, L, Q) /* MLA ., ., .[] (bf00f400/2f000000) */ //#define IEM_INSTR_IMPL_A64__MLA_asimdelem_R(Rd, Rn, H, o2, Rm, M, L, size, Q) /* UMLAL2 ., ., .[] (bf00f400/2f002000) */ //#define IEM_INSTR_IMPL_A64__UMLAL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q) /* MLS ., ., .[] (bf00f400/2f004000) */ //#define IEM_INSTR_IMPL_A64__MLS_asimdelem_R(Rd, Rn, H, o2, Rm, M, L, size, Q) /* UMLSL2 ., ., .[] (bf00f400/2f006000) */ //#define IEM_INSTR_IMPL_A64__UMLSL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q) /* UMULL2 ., ., .[] (bf00f400/2f00a000) */ //#define IEM_INSTR_IMPL_A64__UMULL_asimdelem_L(Rd, Rn, H, Rm, M, L, size, Q) /* SQRDMLAH ., ., .[] (bf00f400/2f00d000) */ //#define IEM_INSTR_IMPL_A64__SQRDMLAH_asimdelem_R(Rd, Rn, H, S, Rm, M, L, size, Q) /* UDOT ., ., .4B[] (bf00f400/2f00e000) */ //#define IEM_INSTR_IMPL_A64__UDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, size, Q) /* SQRDMLSH ., ., .[] (bf00f400/2f00f000) */ //#define IEM_INSTR_IMPL_A64__SQRDMLSH_asimdelem_R(Rd, Rn, H, S, Rm, M, L, size, Q) /* FMULX ., ., .H[] (bfc0f400/2f009000) */ //#define IEM_INSTR_IMPL_A64__FMULX_asimdelem_RH_H(Rd, Rn, H, Rm, M, L, Q) /* FCMLA ., ., .[], # (bf009400/2f001000) */ //#define IEM_INSTR_IMPL_A64__FCMLA_advsimd_elt(Rd, Rn, H, rot, Rm, M, L, size, Q) /* FMULX ., ., .[] (bf80f400/2f809000) */ //#define IEM_INSTR_IMPL_A64__FMULX_asimdelem_R_SD(Rd, Rn, H, Rm, M, L, sz, Q) /* FMLAL2 ., ., .H[] (bfc0f400/2f808000) */ //#define IEM_INSTR_IMPL_A64__FMLAL2_asimdelem_LH(Rd, Rn, H, S, Rm, M, L, sz, Q) /* FMLSL2 ., ., .H[] (bfc0f400/2f80c000) */ //#define IEM_INSTR_IMPL_A64__FMLSL2_asimdelem_LH(Rd, Rn, H, S, Rm, M, L, sz, Q) /* FMLALB .8H, .16B, .B[] (ffc0f400/0fc00000) */ //#define IEM_INSTR_IMPL_A64__FMLALB_asimdelem_H(Rd, Rn, H, Rm, M, L) /* FMLALLBB .4S, .16B, .B[] (ffc0f400/2f008000) */ //#define IEM_INSTR_IMPL_A64__FMLALLBB_asimdelem_J(Rd, Rn, H, Rm, M, L) /* FMLALLBT .4S, .16B, .B[] (ffc0f400/2f408000) */ //#define IEM_INSTR_IMPL_A64__FMLALLBT_asimdelem_J(Rd, Rn, H, Rm, M, L) /* FMLALT .8H, .16B, .B[] (ffc0f400/4fc00000) */ //#define IEM_INSTR_IMPL_A64__FMLALT_asimdelem_H(Rd, Rn, H, Rm, M, L) /* FMLALLTB .4S, .16B, .B[] (ffc0f400/6f008000) */ //#define IEM_INSTR_IMPL_A64__FMLALLTB_asimdelem_J(Rd, Rn, H, Rm, M, L) /* FMLALLTT .4S, .16B, .B[] (ffc0f400/6f408000) */ //#define IEM_INSTR_IMPL_A64__FMLALLTT_asimdelem_J(Rd, Rn, H, Rm, M, L) /* * * Instruction Set & Groups: asimdext / simd_dp / A64 * */ /* EXT ., ., ., # (bfe08400/2e000000) */ //#define IEM_INSTR_IMPL_A64__EXT_asimdext_only(Rd, Rn, imm4, Rm, Q) /* * * Instruction Set & Groups: asimdimm / simd_dp / A64 * */ /* MOVI ., #{, LSL #} (bff89c00/0f000400) */ //#define IEM_INSTR_IMPL_A64__MOVI_asimdimm_L_sl(Rd, h, g, f, e, d, cmode, c, b, a, Q) /* ORR ., #{, LSL #} (bff89c00/0f001400) */ //#define IEM_INSTR_IMPL_A64__ORR_asimdimm_L_sl(Rd, h, g, f, e, d, cmode, c, b, a, Q) /* MOVI ., #{, LSL #} (bff8dc00/0f008400) */ //#define IEM_INSTR_IMPL_A64__MOVI_asimdimm_L_hl(Rd, h, g, f, e, d, cmode, c, b, a, Q) /* ORR ., #{, LSL #} (bff8dc00/0f009400) */ //#define IEM_INSTR_IMPL_A64__ORR_asimdimm_L_hl(Rd, h, g, f, e, d, cmode, c, b, a, Q) /* MOVI ., #, MSL # (bff8ec00/0f00c400) */ //#define IEM_INSTR_IMPL_A64__MOVI_asimdimm_M_sm(Rd, h, g, f, e, d, cmode, c, b, a, Q) /* MOVI ., #{, LSL #0} (bff8fc00/0f00e400) */ //#define IEM_INSTR_IMPL_A64__MOVI_asimdimm_N_b(Rd, h, g, f, e, d, c, b, a, Q) /* FMOV ., # (bff8fc00/0f00f400) */ //#define IEM_INSTR_IMPL_A64__FMOV_asimdimm_S_s(Rd, h, g, f, e, d, c, b, a, Q) /* FMOV ., # (bff8fc00/0f00fc00) */ //#define IEM_INSTR_IMPL_A64__FMOV_asimdimm_H_h(Rd, h, g, f, e, d, c, b, a, Q) /* MVNI ., #{, LSL #} (bff89c00/2f000400) */ //#define IEM_INSTR_IMPL_A64__MVNI_asimdimm_L_sl(Rd, h, g, f, e, d, cmode, c, b, a, Q) /* BIC ., #{, LSL #} (bff89c00/2f001400) */ //#define IEM_INSTR_IMPL_A64__BIC_asimdimm_L_sl(Rd, h, g, f, e, d, cmode, c, b, a, Q) /* MVNI ., #{, LSL #} (bff8dc00/2f008400) */ //#define IEM_INSTR_IMPL_A64__MVNI_asimdimm_L_hl(Rd, h, g, f, e, d, cmode, c, b, a, Q) /* BIC ., #{, LSL #} (bff8dc00/2f009400) */ //#define IEM_INSTR_IMPL_A64__BIC_asimdimm_L_hl(Rd, h, g, f, e, d, cmode, c, b, a, Q) /* MVNI ., #, MSL # (bff8ec00/2f00c400) */ //#define IEM_INSTR_IMPL_A64__MVNI_asimdimm_M_sm(Rd, h, g, f, e, d, cmode, c, b, a, Q) /* MOVI
, # (fff8fc00/2f00e400) */ //#define IEM_INSTR_IMPL_A64__MOVI_asimdimm_D_ds(Rd, h, g, f, e, d, c, b, a) /* MOVI .2D, # (fff8fc00/6f00e400) */ //#define IEM_INSTR_IMPL_A64__MOVI_asimdimm_D2_d(Rd, h, g, f, e, d, c, b, a) /* FMOV .2D, # (fff8fc00/6f00f400) */ //#define IEM_INSTR_IMPL_A64__FMOV_asimdimm_D2_d(Rd, h, g, f, e, d, c, b, a) /* * * Instruction Set & Groups: asimdins / simd_dp / A64 * */ /* DUP ., .[] (bfe0fc00/0e000400) */ //#define IEM_INSTR_IMPL_A64__DUP_asimdins_DV_v(Rd, Rn, imm5, Q) /* DUP ., (bfe0fc00/0e000c00) */ //#define IEM_INSTR_IMPL_A64__DUP_asimdins_DR_r(Rd, Rn, imm5, Q) /* SMOV , .[] (ffe0fc00/0e002c00) */ //#define IEM_INSTR_IMPL_A64__SMOV_asimdins_W_w(Rd, Rn, imm5) /* UMOV , .[] (ffe0fc00/0e003c00) */ //#define IEM_INSTR_IMPL_A64__UMOV_asimdins_W_w(Rd, Rn, imm5) /* INS .[], (ffe0fc00/4e001c00) */ //#define IEM_INSTR_IMPL_A64__INS_asimdins_IR_r(Rd, Rn, imm5) /* SMOV , .[] (ffe0fc00/4e002c00) */ //#define IEM_INSTR_IMPL_A64__SMOV_asimdins_X_x(Rd, Rn, imm5) /* UMOV , .D[] (ffeffc00/4e083c00) */ //#define IEM_INSTR_IMPL_A64__UMOV_asimdins_X_x(Rd, Rn, imm5) /* INS .[], .[] (ffe08400/6e000400) */ //#define IEM_INSTR_IMPL_A64__INS_asimdins_IV_v(Rd, Rn, imm4, imm5) /* * * Instruction Set & Groups: asimdmisc / simd_dp / A64 * */ /* REV64 ., . (bf3ffc00/0e200800) */ //#define IEM_INSTR_IMPL_A64__REV64_asimdmisc_R(Rd, Rn, o0, size, Q) /* REV16 ., . (bf3ffc00/0e201800) */ //#define IEM_INSTR_IMPL_A64__REV16_asimdmisc_R(Rd, Rn, o0, size, Q) /* SADDLP ., . (bf3ffc00/0e202800) */ //#define IEM_INSTR_IMPL_A64__SADDLP_asimdmisc_P(Rd, Rn, op, size, Q) /* SUQADD ., . (bf3ffc00/0e203800) */ //#define IEM_INSTR_IMPL_A64__SUQADD_asimdmisc_R(Rd, Rn, size, Q) /* CLS ., . (bf3ffc00/0e204800) */ //#define IEM_INSTR_IMPL_A64__CLS_asimdmisc_R(Rd, Rn, size, Q) /* CNT ., . (bf3ffc00/0e205800) */ //#define IEM_INSTR_IMPL_A64__CNT_asimdmisc_R(Rd, Rn, size, Q) /* SADALP ., . (bf3ffc00/0e206800) */ //#define IEM_INSTR_IMPL_A64__SADALP_asimdmisc_P(Rd, Rn, op, size, Q) /* SQABS ., . (bf3ffc00/0e207800) */ //#define IEM_INSTR_IMPL_A64__SQABS_asimdmisc_R(Rd, Rn, size, Q) /* CMGT ., ., #0 (bf3ffc00/0e208800) */ //#define IEM_INSTR_IMPL_A64__CMGT_asimdmisc_Z(Rd, Rn, op, size, Q) /* CMEQ ., ., #0 (bf3ffc00/0e209800) */ //#define IEM_INSTR_IMPL_A64__CMEQ_asimdmisc_Z(Rd, Rn, op, size, Q) /* CMLT ., ., #0 (bf3ffc00/0e20a800) */ //#define IEM_INSTR_IMPL_A64__CMLT_asimdmisc_Z(Rd, Rn, size, Q) /* ABS ., . (bf3ffc00/0e20b800) */ //#define IEM_INSTR_IMPL_A64__ABS_asimdmisc_R(Rd, Rn, size, Q) /* XTN2 ., . (bf3ffc00/0e212800) */ //#define IEM_INSTR_IMPL_A64__XTN_asimdmisc_N(Rd, Rn, size, Q) /* SQXTN2 ., . (bf3ffc00/0e214800) */ //#define IEM_INSTR_IMPL_A64__SQXTN_asimdmisc_N(Rd, Rn, size, Q) /* FCVTN2 ., . (bfbffc00/0e216800) */ //#define IEM_INSTR_IMPL_A64__FCVTN_asimdmisc_N(Rd, Rn, sz, Q) /* FCVTL2 ., . (bfbffc00/0e217800) */ //#define IEM_INSTR_IMPL_A64__FCVTL_asimdmisc_L(Rd, Rn, sz, Q) /* FRINTN ., . (bfbffc00/0e218800) */ //#define IEM_INSTR_IMPL_A64__FRINTN_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FRINTM ., . (bfbffc00/0e219800) */ //#define IEM_INSTR_IMPL_A64__FRINTM_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FCVTNS ., . (bfbffc00/0e21a800) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FCVTMS ., . (bfbffc00/0e21b800) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FCVTAS ., . (bfbffc00/0e21c800) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_asimdmisc_R(Rd, Rn, sz, Q) /* SCVTF ., . (bfbffc00/0e21d800) */ //#define IEM_INSTR_IMPL_A64__SCVTF_asimdmisc_R(Rd, Rn, sz, Q) /* FRINT32Z ., . (bfbffc00/0e21e800) */ //#define IEM_INSTR_IMPL_A64__FRINT32Z_asimdmisc_R(Rd, Rn, op, sz, Q) /* FRINT64Z ., . (bfbffc00/0e21f800) */ //#define IEM_INSTR_IMPL_A64__FRINT64Z_asimdmisc_R(Rd, Rn, op, sz, Q) /* FCMGT ., ., #0.0 (bfbffc00/0ea0c800) */ //#define IEM_INSTR_IMPL_A64__FCMGT_asimdmisc_FZ(Rd, Rn, op, sz, Q) /* FCMEQ ., ., #0.0 (bfbffc00/0ea0d800) */ //#define IEM_INSTR_IMPL_A64__FCMEQ_asimdmisc_FZ(Rd, Rn, op, sz, Q) /* FCMLT ., ., #0.0 (bfbffc00/0ea0e800) */ //#define IEM_INSTR_IMPL_A64__FCMLT_asimdmisc_FZ(Rd, Rn, sz, Q) /* FABS ., . (bfbffc00/0ea0f800) */ //#define IEM_INSTR_IMPL_A64__FABS_asimdmisc_R(Rd, Rn, sz, Q) /* FRINTP ., . (bfbffc00/0ea18800) */ //#define IEM_INSTR_IMPL_A64__FRINTP_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FRINTZ ., . (bfbffc00/0ea19800) */ //#define IEM_INSTR_IMPL_A64__FRINTZ_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FCVTPS ., . (bfbffc00/0ea1a800) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FCVTZS ., . (bfbffc00/0ea1b800) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* URECPE ., . (bfbffc00/0ea1c800) */ //#define IEM_INSTR_IMPL_A64__URECPE_asimdmisc_R(Rd, Rn, sz, Q) /* FRECPE ., . (bfbffc00/0ea1d800) */ //#define IEM_INSTR_IMPL_A64__FRECPE_asimdmisc_R(Rd, Rn, sz, Q) /* BFCVTN2 ., .4S (bffffc00/0ea16800) */ //#define IEM_INSTR_IMPL_A64__BFCVTN_asimdmisc_4S(Rd, Rn, Q) /* REV32 ., . (bf3ffc00/2e200800) */ //#define IEM_INSTR_IMPL_A64__REV32_asimdmisc_R(Rd, Rn, o0, size, Q) /* UADDLP ., . (bf3ffc00/2e202800) */ //#define IEM_INSTR_IMPL_A64__UADDLP_asimdmisc_P(Rd, Rn, op, size, Q) /* USQADD ., . (bf3ffc00/2e203800) */ //#define IEM_INSTR_IMPL_A64__USQADD_asimdmisc_R(Rd, Rn, size, Q) /* CLZ ., . (bf3ffc00/2e204800) */ //#define IEM_INSTR_IMPL_A64__CLZ_asimdmisc_R(Rd, Rn, size, Q) /* UADALP ., . (bf3ffc00/2e206800) */ //#define IEM_INSTR_IMPL_A64__UADALP_asimdmisc_P(Rd, Rn, op, size, Q) /* SQNEG ., . (bf3ffc00/2e207800) */ //#define IEM_INSTR_IMPL_A64__SQNEG_asimdmisc_R(Rd, Rn, size, Q) /* CMGE ., ., #0 (bf3ffc00/2e208800) */ //#define IEM_INSTR_IMPL_A64__CMGE_asimdmisc_Z(Rd, Rn, op, size, Q) /* CMLE ., ., #0 (bf3ffc00/2e209800) */ //#define IEM_INSTR_IMPL_A64__CMLE_asimdmisc_Z(Rd, Rn, op, size, Q) /* NEG ., . (bf3ffc00/2e20b800) */ //#define IEM_INSTR_IMPL_A64__NEG_asimdmisc_R(Rd, Rn, size, Q) /* SQXTUN2 ., . (bf3ffc00/2e212800) */ //#define IEM_INSTR_IMPL_A64__SQXTUN_asimdmisc_N(Rd, Rn, size, Q) /* SHLL2 ., ., # (bf3ffc00/2e213800) */ //#define IEM_INSTR_IMPL_A64__SHLL_asimdmisc_S(Rd, Rn, size, Q) /* UQXTN2 ., . (bf3ffc00/2e214800) */ //#define IEM_INSTR_IMPL_A64__UQXTN_asimdmisc_N(Rd, Rn, size, Q) /* FCVTXN2 ., .2D (bffffc00/2e616800) */ //#define IEM_INSTR_IMPL_A64__FCVTXN_asimdmisc_N(Rd, Rn, Q) /* FRINTA ., . (bfbffc00/2e218800) */ //#define IEM_INSTR_IMPL_A64__FRINTA_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FRINTX ., . (bfbffc00/2e219800) */ //#define IEM_INSTR_IMPL_A64__FRINTX_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FCVTNU ., . (bfbffc00/2e21a800) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FCVTMU ., . (bfbffc00/2e21b800) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FCVTAU ., . (bfbffc00/2e21c800) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_asimdmisc_R(Rd, Rn, sz, Q) /* UCVTF ., . (bfbffc00/2e21d800) */ //#define IEM_INSTR_IMPL_A64__UCVTF_asimdmisc_R(Rd, Rn, sz, Q) /* FRINT32X ., . (bfbffc00/2e21e800) */ //#define IEM_INSTR_IMPL_A64__FRINT32X_asimdmisc_R(Rd, Rn, op, sz, Q) /* FRINT64X ., . (bfbffc00/2e21f800) */ //#define IEM_INSTR_IMPL_A64__FRINT64X_asimdmisc_R(Rd, Rn, op, sz, Q) /* NOT ., . (bffffc00/2e205800) */ //#define IEM_INSTR_IMPL_A64__NOT_asimdmisc_R(Rd, Rn, Q) /* F1CVTL2 .8H, . (bffffc00/2e217800) */ //#define IEM_INSTR_IMPL_A64__F1CVTL_asimdmisc_V(Rd, Rn, Q) /* RBIT ., . (bffffc00/2e605800) */ //#define IEM_INSTR_IMPL_A64__RBIT_asimdmisc_R(Rd, Rn, Q) /* F2CVTL2 .8H, . (bffffc00/2e617800) */ //#define IEM_INSTR_IMPL_A64__F2CVTL_asimdmisc_V(Rd, Rn, Q) /* FCMGE ., ., #0.0 (bfbffc00/2ea0c800) */ //#define IEM_INSTR_IMPL_A64__FCMGE_asimdmisc_FZ(Rd, Rn, op, sz, Q) /* FCMLE ., ., #0.0 (bfbffc00/2ea0d800) */ //#define IEM_INSTR_IMPL_A64__FCMLE_asimdmisc_FZ(Rd, Rn, op, sz, Q) /* FNEG ., . (bfbffc00/2ea0f800) */ //#define IEM_INSTR_IMPL_A64__FNEG_asimdmisc_R(Rd, Rn, sz, Q) /* FRINTI ., . (bfbffc00/2ea19800) */ //#define IEM_INSTR_IMPL_A64__FRINTI_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FCVTPU ., . (bfbffc00/2ea1a800) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* FCVTZU ., . (bfbffc00/2ea1b800) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_asimdmisc_R(Rd, Rn, o1, sz, o2, Q) /* URSQRTE ., . (bfbffc00/2ea1c800) */ //#define IEM_INSTR_IMPL_A64__URSQRTE_asimdmisc_R(Rd, Rn, sz, Q) /* FRSQRTE ., . (bfbffc00/2ea1d800) */ //#define IEM_INSTR_IMPL_A64__FRSQRTE_asimdmisc_R(Rd, Rn, sz, Q) /* FSQRT ., . (bfbffc00/2ea1f800) */ //#define IEM_INSTR_IMPL_A64__FSQRT_asimdmisc_R(Rd, Rn, sz, Q) /* BF1CVTL2 .8H, . (bffffc00/2ea17800) */ //#define IEM_INSTR_IMPL_A64__BF1CVTL_asimdmisc_V(Rd, Rn, Q) /* BF2CVTL2 .8H, . (bffffc00/2ee17800) */ //#define IEM_INSTR_IMPL_A64__BF2CVTL_asimdmisc_V(Rd, Rn, Q) /* * * Instruction Set & Groups: asimdmiscfp16 / simd_dp / A64 * */ /* FRINTN ., . (bffffc00/0e798800) */ //#define IEM_INSTR_IMPL_A64__FRINTN_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FRINTM ., . (bffffc00/0e799800) */ //#define IEM_INSTR_IMPL_A64__FRINTM_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FCVTNS ., . (bffffc00/0e79a800) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FCVTMS ., . (bffffc00/0e79b800) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FCVTAS ., . (bffffc00/0e79c800) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_asimdmiscfp16_R(Rd, Rn, Q) /* SCVTF ., . (bffffc00/0e79d800) */ //#define IEM_INSTR_IMPL_A64__SCVTF_asimdmiscfp16_R(Rd, Rn, Q) /* FCMGT ., ., #0.0 (bffffc00/0ef8c800) */ //#define IEM_INSTR_IMPL_A64__FCMGT_asimdmiscfp16_FZ(Rd, Rn, op, Q) /* FCMEQ ., ., #0.0 (bffffc00/0ef8d800) */ //#define IEM_INSTR_IMPL_A64__FCMEQ_asimdmiscfp16_FZ(Rd, Rn, op, Q) /* FCMLT ., ., #0.0 (bffffc00/0ef8e800) */ //#define IEM_INSTR_IMPL_A64__FCMLT_asimdmiscfp16_FZ(Rd, Rn, Q) /* FABS ., . (bffffc00/0ef8f800) */ //#define IEM_INSTR_IMPL_A64__FABS_asimdmiscfp16_R(Rd, Rn, Q) /* FRINTP ., . (bffffc00/0ef98800) */ //#define IEM_INSTR_IMPL_A64__FRINTP_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FRINTZ ., . (bffffc00/0ef99800) */ //#define IEM_INSTR_IMPL_A64__FRINTZ_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FCVTPS ., . (bffffc00/0ef9a800) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FCVTZS ., . (bffffc00/0ef9b800) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FRECPE ., . (bffffc00/0ef9d800) */ //#define IEM_INSTR_IMPL_A64__FRECPE_asimdmiscfp16_R(Rd, Rn, Q) /* FRINTA ., . (bffffc00/2e798800) */ //#define IEM_INSTR_IMPL_A64__FRINTA_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FRINTX ., . (bffffc00/2e799800) */ //#define IEM_INSTR_IMPL_A64__FRINTX_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FCVTNU ., . (bffffc00/2e79a800) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FCVTMU ., . (bffffc00/2e79b800) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FCVTAU ., . (bffffc00/2e79c800) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_asimdmiscfp16_R(Rd, Rn, Q) /* UCVTF ., . (bffffc00/2e79d800) */ //#define IEM_INSTR_IMPL_A64__UCVTF_asimdmiscfp16_R(Rd, Rn, Q) /* FCMGE ., ., #0.0 (bffffc00/2ef8c800) */ //#define IEM_INSTR_IMPL_A64__FCMGE_asimdmiscfp16_FZ(Rd, Rn, op, Q) /* FCMLE ., ., #0.0 (bffffc00/2ef8d800) */ //#define IEM_INSTR_IMPL_A64__FCMLE_asimdmiscfp16_FZ(Rd, Rn, op, Q) /* FNEG ., . (bffffc00/2ef8f800) */ //#define IEM_INSTR_IMPL_A64__FNEG_asimdmiscfp16_R(Rd, Rn, Q) /* FRINTI ., . (bffffc00/2ef99800) */ //#define IEM_INSTR_IMPL_A64__FRINTI_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FCVTPU ., . (bffffc00/2ef9a800) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FCVTZU ., . (bffffc00/2ef9b800) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_asimdmiscfp16_R(Rd, Rn, o1, o2, Q) /* FRSQRTE ., . (bffffc00/2ef9d800) */ //#define IEM_INSTR_IMPL_A64__FRSQRTE_asimdmiscfp16_R(Rd, Rn, Q) /* FSQRT ., . (bffffc00/2ef9f800) */ //#define IEM_INSTR_IMPL_A64__FSQRT_asimdmiscfp16_R(Rd, Rn, Q) /* * * Instruction Set & Groups: asimdperm / simd_dp / A64 * */ /* UZP1 ., ., . (bf20fc00/0e001800) */ //#define IEM_INSTR_IMPL_A64__UZP1_asimdperm_only(Rd, Rn, op, Rm, size, Q) /* TRN1 ., ., . (bf20fc00/0e002800) */ //#define IEM_INSTR_IMPL_A64__TRN1_asimdperm_only(Rd, Rn, op, Rm, size, Q) /* ZIP1 ., ., . (bf20fc00/0e003800) */ //#define IEM_INSTR_IMPL_A64__ZIP1_asimdperm_only(Rd, Rn, op, Rm, size, Q) /* UZP2 ., ., . (bf20fc00/0e005800) */ //#define IEM_INSTR_IMPL_A64__UZP2_asimdperm_only(Rd, Rn, op, Rm, size, Q) /* TRN2 ., ., . (bf20fc00/0e006800) */ //#define IEM_INSTR_IMPL_A64__TRN2_asimdperm_only(Rd, Rn, op, Rm, size, Q) /* ZIP2 ., ., . (bf20fc00/0e007800) */ //#define IEM_INSTR_IMPL_A64__ZIP2_asimdperm_only(Rd, Rn, op, Rm, size, Q) /* * * Instruction Set & Groups: asimdsame / simd_dp / A64 * */ /* SHADD ., ., . (bf20fc00/0e200400) */ //#define IEM_INSTR_IMPL_A64__SHADD_asimdsame_only(Rd, Rn, Rm, size, Q) /* SQADD ., ., . (bf20fc00/0e200c00) */ //#define IEM_INSTR_IMPL_A64__SQADD_asimdsame_only(Rd, Rn, Rm, size, Q) /* SRHADD ., ., . (bf20fc00/0e201400) */ //#define IEM_INSTR_IMPL_A64__SRHADD_asimdsame_only(Rd, Rn, Rm, size, Q) /* SHSUB ., ., . (bf20fc00/0e202400) */ //#define IEM_INSTR_IMPL_A64__SHSUB_asimdsame_only(Rd, Rn, Rm, size, Q) /* SQSUB ., ., . (bf20fc00/0e202c00) */ //#define IEM_INSTR_IMPL_A64__SQSUB_asimdsame_only(Rd, Rn, Rm, size, Q) /* CMGT ., ., . (bf20fc00/0e203400) */ //#define IEM_INSTR_IMPL_A64__CMGT_asimdsame_only(Rd, Rn, eq, Rm, size, Q) /* CMGE ., ., . (bf20fc00/0e203c00) */ //#define IEM_INSTR_IMPL_A64__CMGE_asimdsame_only(Rd, Rn, eq, Rm, size, Q) /* SSHL ., ., . (bf20fc00/0e204400) */ //#define IEM_INSTR_IMPL_A64__SSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q) /* SQSHL ., ., . (bf20fc00/0e204c00) */ //#define IEM_INSTR_IMPL_A64__SQSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q) /* SRSHL ., ., . (bf20fc00/0e205400) */ //#define IEM_INSTR_IMPL_A64__SRSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q) /* SQRSHL ., ., . (bf20fc00/0e205c00) */ //#define IEM_INSTR_IMPL_A64__SQRSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q) /* SMAX ., ., . (bf20fc00/0e206400) */ //#define IEM_INSTR_IMPL_A64__SMAX_asimdsame_only(Rd, Rn, o1, Rm, size, Q) /* SMIN ., ., . (bf20fc00/0e206c00) */ //#define IEM_INSTR_IMPL_A64__SMIN_asimdsame_only(Rd, Rn, o1, Rm, size, Q) /* SABD ., ., . (bf20fc00/0e207400) */ //#define IEM_INSTR_IMPL_A64__SABD_asimdsame_only(Rd, Rn, ac, Rm, size, Q) /* SABA ., ., . (bf20fc00/0e207c00) */ //#define IEM_INSTR_IMPL_A64__SABA_asimdsame_only(Rd, Rn, ac, Rm, size, Q) /* ADD ., ., . (bf20fc00/0e208400) */ //#define IEM_INSTR_IMPL_A64__ADD_asimdsame_only(Rd, Rn, Rm, size, Q) /* CMTST ., ., . (bf20fc00/0e208c00) */ //#define IEM_INSTR_IMPL_A64__CMTST_asimdsame_only(Rd, Rn, Rm, size, Q) /* MLA ., ., . (bf20fc00/0e209400) */ //#define IEM_INSTR_IMPL_A64__MLA_asimdsame_only(Rd, Rn, Rm, size, Q) /* MUL ., ., . (bf20fc00/0e209c00) */ //#define IEM_INSTR_IMPL_A64__MUL_asimdsame_only(Rd, Rn, Rm, size, Q) /* SMAXP ., ., . (bf20fc00/0e20a400) */ //#define IEM_INSTR_IMPL_A64__SMAXP_asimdsame_only(Rd, Rn, o1, Rm, size, Q) /* SMINP ., ., . (bf20fc00/0e20ac00) */ //#define IEM_INSTR_IMPL_A64__SMINP_asimdsame_only(Rd, Rn, o1, Rm, size, Q) /* SQDMULH ., ., . (bf20fc00/0e20b400) */ //#define IEM_INSTR_IMPL_A64__SQDMULH_asimdsame_only(Rd, Rn, Rm, size, Q) /* ADDP ., ., . (bf20fc00/0e20bc00) */ //#define IEM_INSTR_IMPL_A64__ADDP_asimdsame_only(Rd, Rn, Rm, size, Q) /* FMAXNM ., ., . (bfa0fc00/0e20c400) */ //#define IEM_INSTR_IMPL_A64__FMAXNM_asimdsame_only(Rd, Rn, Rm, sz, o1, Q) /* FMLA ., ., . (bfa0fc00/0e20cc00) */ //#define IEM_INSTR_IMPL_A64__FMLA_asimdsame_only(Rd, Rn, Rm, sz, op, Q) /* FADD ., ., . (bfa0fc00/0e20d400) */ //#define IEM_INSTR_IMPL_A64__FADD_asimdsame_only(Rd, Rn, Rm, sz, Q) /* FMULX ., ., . (bfa0fc00/0e20dc00) */ //#define IEM_INSTR_IMPL_A64__FMULX_asimdsame_only(Rd, Rn, Rm, sz, Q) /* FCMEQ ., ., . (bfa0fc00/0e20e400) */ //#define IEM_INSTR_IMPL_A64__FCMEQ_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q) /* FMAX ., ., . (bfa0fc00/0e20f400) */ //#define IEM_INSTR_IMPL_A64__FMAX_asimdsame_only(Rd, Rn, Rm, sz, o1, Q) /* FRECPS ., ., . (bfa0fc00/0e20fc00) */ //#define IEM_INSTR_IMPL_A64__FRECPS_asimdsame_only(Rd, Rn, Rm, sz, Q) /* AND ., ., . (bfe0fc00/0e201c00) */ //#define IEM_INSTR_IMPL_A64__AND_asimdsame_only(Rd, Rn, Rm, Q) /* FMLAL ., ., . (bfe0fc00/0e20ec00) */ //#define IEM_INSTR_IMPL_A64__FMLAL_asimdsame_F(Rd, Rn, Rm, sz, S, Q) /* BIC ., ., . (bfe0fc00/0e601c00) */ //#define IEM_INSTR_IMPL_A64__BIC_asimdsame_only(Rd, Rn, Rm, Q) /* FMINNM ., ., . (bfa0fc00/0ea0c400) */ //#define IEM_INSTR_IMPL_A64__FMINNM_asimdsame_only(Rd, Rn, Rm, sz, o1, Q) /* FMLS ., ., . (bfa0fc00/0ea0cc00) */ //#define IEM_INSTR_IMPL_A64__FMLS_asimdsame_only(Rd, Rn, Rm, sz, op, Q) /* FSUB ., ., . (bfa0fc00/0ea0d400) */ //#define IEM_INSTR_IMPL_A64__FSUB_asimdsame_only(Rd, Rn, Rm, sz, Q) /* FAMAX ., ., . (bf20fc00/0e20dc00) */ //#define IEM_INSTR_IMPL_A64__FAMAX_asimdsame_only(Rd, Rn, Rm, size, Q) /* FMIN ., ., . (bfa0fc00/0ea0f400) */ //#define IEM_INSTR_IMPL_A64__FMIN_asimdsame_only(Rd, Rn, Rm, sz, o1, Q) /* FRSQRTS ., ., . (bfa0fc00/0ea0fc00) */ //#define IEM_INSTR_IMPL_A64__FRSQRTS_asimdsame_only(Rd, Rn, Rm, sz, Q) /* ORR ., ., . (bfe0fc00/0ea01c00) */ //#define IEM_INSTR_IMPL_A64__ORR_asimdsame_only(Rd, Rn, Rm, Q) /* FMLSL ., ., . (bfe0fc00/0ea0ec00) */ //#define IEM_INSTR_IMPL_A64__FMLSL_asimdsame_F(Rd, Rn, Rm, sz, S, Q) /* ORN ., ., . (bfe0fc00/0ee01c00) */ //#define IEM_INSTR_IMPL_A64__ORN_asimdsame_only(Rd, Rn, Rm, Q) /* UHADD ., ., . (bf20fc00/2e200400) */ //#define IEM_INSTR_IMPL_A64__UHADD_asimdsame_only(Rd, Rn, Rm, size, Q) /* UQADD ., ., . (bf20fc00/2e200c00) */ //#define IEM_INSTR_IMPL_A64__UQADD_asimdsame_only(Rd, Rn, Rm, size, Q) /* URHADD ., ., . (bf20fc00/2e201400) */ //#define IEM_INSTR_IMPL_A64__URHADD_asimdsame_only(Rd, Rn, Rm, size, Q) /* UHSUB ., ., . (bf20fc00/2e202400) */ //#define IEM_INSTR_IMPL_A64__UHSUB_asimdsame_only(Rd, Rn, Rm, size, Q) /* UQSUB ., ., . (bf20fc00/2e202c00) */ //#define IEM_INSTR_IMPL_A64__UQSUB_asimdsame_only(Rd, Rn, Rm, size, Q) /* CMHI ., ., . (bf20fc00/2e203400) */ //#define IEM_INSTR_IMPL_A64__CMHI_asimdsame_only(Rd, Rn, eq, Rm, size, Q) /* CMHS ., ., . (bf20fc00/2e203c00) */ //#define IEM_INSTR_IMPL_A64__CMHS_asimdsame_only(Rd, Rn, eq, Rm, size, Q) /* USHL ., ., . (bf20fc00/2e204400) */ //#define IEM_INSTR_IMPL_A64__USHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q) /* UQSHL ., ., . (bf20fc00/2e204c00) */ //#define IEM_INSTR_IMPL_A64__UQSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q) /* URSHL ., ., . (bf20fc00/2e205400) */ //#define IEM_INSTR_IMPL_A64__URSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q) /* UQRSHL ., ., . (bf20fc00/2e205c00) */ //#define IEM_INSTR_IMPL_A64__UQRSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q) /* UMAX ., ., . (bf20fc00/2e206400) */ //#define IEM_INSTR_IMPL_A64__UMAX_asimdsame_only(Rd, Rn, o1, Rm, size, Q) /* UMIN ., ., . (bf20fc00/2e206c00) */ //#define IEM_INSTR_IMPL_A64__UMIN_asimdsame_only(Rd, Rn, o1, Rm, size, Q) /* UABD ., ., . (bf20fc00/2e207400) */ //#define IEM_INSTR_IMPL_A64__UABD_asimdsame_only(Rd, Rn, ac, Rm, size, Q) /* UABA ., ., . (bf20fc00/2e207c00) */ //#define IEM_INSTR_IMPL_A64__UABA_asimdsame_only(Rd, Rn, ac, Rm, size, Q) /* SUB ., ., . (bf20fc00/2e208400) */ //#define IEM_INSTR_IMPL_A64__SUB_asimdsame_only(Rd, Rn, Rm, size, Q) /* CMEQ ., ., . (bf20fc00/2e208c00) */ //#define IEM_INSTR_IMPL_A64__CMEQ_asimdsame_only(Rd, Rn, Rm, size, Q) /* MLS ., ., . (bf20fc00/2e209400) */ //#define IEM_INSTR_IMPL_A64__MLS_asimdsame_only(Rd, Rn, Rm, size, Q) /* PMUL ., ., . (bf20fc00/2e209c00) */ //#define IEM_INSTR_IMPL_A64__PMUL_asimdsame_only(Rd, Rn, Rm, size, Q) /* UMAXP ., ., . (bf20fc00/2e20a400) */ //#define IEM_INSTR_IMPL_A64__UMAXP_asimdsame_only(Rd, Rn, o1, Rm, size, Q) /* UMINP ., ., . (bf20fc00/2e20ac00) */ //#define IEM_INSTR_IMPL_A64__UMINP_asimdsame_only(Rd, Rn, o1, Rm, size, Q) /* SQRDMULH ., ., . (bf20fc00/2e20b400) */ //#define IEM_INSTR_IMPL_A64__SQRDMULH_asimdsame_only(Rd, Rn, Rm, size, Q) /* FMAXNMP ., ., . (bfa0fc00/2e20c400) */ //#define IEM_INSTR_IMPL_A64__FMAXNMP_asimdsame_only(Rd, Rn, Rm, sz, o1, Q) /* FADDP ., ., . (bfa0fc00/2e20d400) */ //#define IEM_INSTR_IMPL_A64__FADDP_asimdsame_only(Rd, Rn, Rm, sz, Q) /* FMUL ., ., . (bfa0fc00/2e20dc00) */ //#define IEM_INSTR_IMPL_A64__FMUL_asimdsame_only(Rd, Rn, Rm, sz, Q) /* FCMGE ., ., . (bfa0fc00/2e20e400) */ //#define IEM_INSTR_IMPL_A64__FCMGE_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q) /* FACGE ., ., . (bfa0fc00/2e20ec00) */ //#define IEM_INSTR_IMPL_A64__FACGE_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q) /* FMAXP ., ., . (bfa0fc00/2e20f400) */ //#define IEM_INSTR_IMPL_A64__FMAXP_asimdsame_only(Rd, Rn, Rm, sz, o1, Q) /* FDIV ., ., . (bfa0fc00/2e20fc00) */ //#define IEM_INSTR_IMPL_A64__FDIV_asimdsame_only(Rd, Rn, Rm, sz, Q) /* EOR ., ., . (bfe0fc00/2e201c00) */ //#define IEM_INSTR_IMPL_A64__EOR_asimdsame_only(Rd, Rn, Rm, opc2, Q) /* FMLAL2 ., ., . (bfe0fc00/2e20cc00) */ //#define IEM_INSTR_IMPL_A64__FMLAL2_asimdsame_F(Rd, Rn, Rm, sz, S, Q) /* BSL ., ., . (bfe0fc00/2e601c00) */ //#define IEM_INSTR_IMPL_A64__BSL_asimdsame_only(Rd, Rn, Rm, opc2, Q) /* FMINNMP ., ., . (bfa0fc00/2ea0c400) */ //#define IEM_INSTR_IMPL_A64__FMINNMP_asimdsame_only(Rd, Rn, Rm, sz, o1, Q) /* FABD ., ., . (bfa0fc00/2ea0d400) */ //#define IEM_INSTR_IMPL_A64__FABD_asimdsame_only(Rd, Rn, Rm, sz, Q) /* FAMIN ., ., . (bf20fc00/2e20dc00) */ //#define IEM_INSTR_IMPL_A64__FAMIN_asimdsame_only(Rd, Rn, Rm, size, Q) /* FCMGT ., ., . (bfa0fc00/2ea0e400) */ //#define IEM_INSTR_IMPL_A64__FCMGT_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q) /* FACGT ., ., . (bfa0fc00/2ea0ec00) */ //#define IEM_INSTR_IMPL_A64__FACGT_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q) /* FMINP ., ., . (bfa0fc00/2ea0f400) */ //#define IEM_INSTR_IMPL_A64__FMINP_asimdsame_only(Rd, Rn, Rm, sz, o1, Q) /* FSCALE ., ., . (bf20fc00/2e20fc00) */ //#define IEM_INSTR_IMPL_A64__FSCALE_asimdsame_only(Rd, Rn, Rm, size, Q) /* BIT ., ., . (bfe0fc00/2ea01c00) */ //#define IEM_INSTR_IMPL_A64__BIT_asimdsame_only(Rd, Rn, Rm, opc2, Q) /* FMLSL2 ., ., . (bfe0fc00/2ea0cc00) */ //#define IEM_INSTR_IMPL_A64__FMLSL2_asimdsame_F(Rd, Rn, Rm, sz, S, Q) /* BIF ., ., . (bfe0fc00/2ee01c00) */ //#define IEM_INSTR_IMPL_A64__BIF_asimdsame_only(Rd, Rn, Rm, opc2, Q) /* * * Instruction Set & Groups: asimdsame2 / simd_dp / A64 * */ /* SDOT ., ., . (bf20fc00/0e009400) */ //#define IEM_INSTR_IMPL_A64__SDOT_asimdsame2_D(Rd, Rn, Rm, size, Q) /* FCVTN2 ., .4S, .4S (bfe0fc00/0e00f400) */ //#define IEM_INSTR_IMPL_A64__FCVTN_asimdsame2_H(Rd, Rn, Rm, Q) /* FDOT ., ., . (bfe0fc00/0e00fc00) */ //#define IEM_INSTR_IMPL_A64__FDOT_asimdsame2_DD(Rd, Rn, Rm, Q) /* FCVTN ., ., . (bfe0fc00/0e40f400) */ //#define IEM_INSTR_IMPL_A64__FCVTN_asimdsame2_D(Rd, Rn, Rm, Q) /* FDOT ., ., . (bfe0fc00/0e40fc00) */ //#define IEM_INSTR_IMPL_A64__FDOT_asimdsame2_D(Rd, Rn, Rm, Q) /* USDOT ., ., . (bfe0fc00/0e809c00) */ //#define IEM_INSTR_IMPL_A64__USDOT_asimdsame2_D(Rd, Rn, Rm, Q) /* SQRDMLAH ., ., . (bf20fc00/2e008400) */ //#define IEM_INSTR_IMPL_A64__SQRDMLAH_asimdsame2_only(Rd, Rn, S, Rm, size, Q) /* SQRDMLSH ., ., . (bf20fc00/2e008c00) */ //#define IEM_INSTR_IMPL_A64__SQRDMLSH_asimdsame2_only(Rd, Rn, S, Rm, size, Q) /* UDOT ., ., . (bf20fc00/2e009400) */ //#define IEM_INSTR_IMPL_A64__UDOT_asimdsame2_D(Rd, Rn, Rm, size, Q) /* FCMLA ., ., ., # (bf20e400/2e00c400) */ //#define IEM_INSTR_IMPL_A64__FCMLA_asimdsame2_C(Rd, Rn, rot, Rm, size, Q) /* FCADD ., ., ., # (bf20ec00/2e00e400) */ //#define IEM_INSTR_IMPL_A64__FCADD_asimdsame2_C(Rd, Rn, rot, Rm, size, Q) /* BFDOT ., ., . (bfe0fc00/2e40fc00) */ //#define IEM_INSTR_IMPL_A64__BFDOT_asimdsame2_D(Rd, Rn, Rm, Q) /* BFMLAL .4S, .8H, .8H (bfe0fc00/2ec0fc00) */ //#define IEM_INSTR_IMPL_A64__BFMLAL_asimdsame2_F(Rd, Rn, Rm, Q) /* FMLALLBB .4S, .16B, .16B (ffe0fc00/0e00c400) */ //#define IEM_INSTR_IMPL_A64__FMLALLBB_asimdsame2_G(Rd, Rn, Rm) /* FMLALLBT .4S, .16B, .16B (ffe0fc00/0e40c400) */ //#define IEM_INSTR_IMPL_A64__FMLALLBT_asimdsame2_G(Rd, Rn, Rm) /* FMLALB .8H, .16B, .16B (ffe0fc00/0ec0fc00) */ //#define IEM_INSTR_IMPL_A64__FMLALB_asimdsame2_J(Rd, Rn, Rm) /* FMLALLTB .4S, .16B, .16B (ffe0fc00/4e00c400) */ //#define IEM_INSTR_IMPL_A64__FMLALLTB_asimdsame2_G(Rd, Rn, Rm) /* FMLALLTT .4S, .16B, .16B (ffe0fc00/4e40c400) */ //#define IEM_INSTR_IMPL_A64__FMLALLTT_asimdsame2_G(Rd, Rn, Rm) /* SMMLA .4S, .16B, .16B (ffe0fc00/4e80a400) */ //#define IEM_INSTR_IMPL_A64__SMMLA_asimdsame2_G(Rd, Rn, B, Rm) /* USMMLA .4S, .16B, .16B (ffe0fc00/4e80ac00) */ //#define IEM_INSTR_IMPL_A64__USMMLA_asimdsame2_G(Rd, Rn, B, Rm) /* FMLALT .8H, .16B, .16B (ffe0fc00/4ec0fc00) */ //#define IEM_INSTR_IMPL_A64__FMLALT_asimdsame2_J(Rd, Rn, Rm) /* FMMLA .8H, .16B, .16B (ffe0fc00/6e00ec00) */ //#define IEM_INSTR_IMPL_A64__FMMLA_asimd_FP8FP16(Rd, Rn, Rm) /* BFMMLA .4S, .8H, .8H (ffe0fc00/6e40ec00) */ //#define IEM_INSTR_IMPL_A64__BFMMLA_asimdsame2_E(Rd, Rn, Rm) /* FMMLA .4S, .16B, .16B (ffe0fc00/6e80ec00) */ //#define IEM_INSTR_IMPL_A64__FMMLA_asimd_FP8FP32(Rd, Rn, Rm) /* UMMLA .4S, .16B, .16B (ffe0fc00/6e80a400) */ //#define IEM_INSTR_IMPL_A64__UMMLA_asimdsame2_G(Rd, Rn, B, Rm) /* * * Instruction Set & Groups: asimdsamefp16 / simd_dp / A64 * */ /* FMAXNM ., ., . (bfe0fc00/0e400400) */ //#define IEM_INSTR_IMPL_A64__FMAXNM_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FMLA ., ., . (bfe0fc00/0e400c00) */ //#define IEM_INSTR_IMPL_A64__FMLA_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FADD ., ., . (bfe0fc00/0e401400) */ //#define IEM_INSTR_IMPL_A64__FADD_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FMULX ., ., . (bfe0fc00/0e401c00) */ //#define IEM_INSTR_IMPL_A64__FMULX_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FCMEQ ., ., . (bfe0fc00/0e402400) */ //#define IEM_INSTR_IMPL_A64__FCMEQ_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q) /* FMAX ., ., . (bfe0fc00/0e403400) */ //#define IEM_INSTR_IMPL_A64__FMAX_asimdsamefp16_only(Rd, Rn, Rm, o1, Q) /* FRECPS ., ., . (bfe0fc00/0e403c00) */ //#define IEM_INSTR_IMPL_A64__FRECPS_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FMINNM ., ., . (bfe0fc00/0ec00400) */ //#define IEM_INSTR_IMPL_A64__FMINNM_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FMLS ., ., . (bfe0fc00/0ec00c00) */ //#define IEM_INSTR_IMPL_A64__FMLS_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FSUB ., ., . (bfe0fc00/0ec01400) */ //#define IEM_INSTR_IMPL_A64__FSUB_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FAMAX ., ., . (bfe0fc00/0ec01c00) */ //#define IEM_INSTR_IMPL_A64__FAMAX_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FMIN ., ., . (bfe0fc00/0ec03400) */ //#define IEM_INSTR_IMPL_A64__FMIN_asimdsamefp16_only(Rd, Rn, Rm, o1, Q) /* FRSQRTS ., ., . (bfe0fc00/0ec03c00) */ //#define IEM_INSTR_IMPL_A64__FRSQRTS_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FMAXNMP ., ., . (bfe0fc00/2e400400) */ //#define IEM_INSTR_IMPL_A64__FMAXNMP_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FADDP ., ., . (bfe0fc00/2e401400) */ //#define IEM_INSTR_IMPL_A64__FADDP_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FMUL ., ., . (bfe0fc00/2e401c00) */ //#define IEM_INSTR_IMPL_A64__FMUL_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FCMGE ., ., . (bfe0fc00/2e402400) */ //#define IEM_INSTR_IMPL_A64__FCMGE_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q) /* FACGE ., ., . (bfe0fc00/2e402c00) */ //#define IEM_INSTR_IMPL_A64__FACGE_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q) /* FMAXP ., ., . (bfe0fc00/2e403400) */ //#define IEM_INSTR_IMPL_A64__FMAXP_asimdsamefp16_only(Rd, Rn, Rm, o1, Q) /* FDIV ., ., . (bfe0fc00/2e403c00) */ //#define IEM_INSTR_IMPL_A64__FDIV_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FMINNMP ., ., . (bfe0fc00/2ec00400) */ //#define IEM_INSTR_IMPL_A64__FMINNMP_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FABD ., ., . (bfe0fc00/2ec01400) */ //#define IEM_INSTR_IMPL_A64__FABD_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FAMIN ., ., . (bfe0fc00/2ec01c00) */ //#define IEM_INSTR_IMPL_A64__FAMIN_asimdsamefp16_only(Rd, Rn, Rm, Q) /* FCMGT ., ., . (bfe0fc00/2ec02400) */ //#define IEM_INSTR_IMPL_A64__FCMGT_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q) /* FACGT ., ., . (bfe0fc00/2ec02c00) */ //#define IEM_INSTR_IMPL_A64__FACGT_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q) /* FMINP ., ., . (bfe0fc00/2ec03400) */ //#define IEM_INSTR_IMPL_A64__FMINP_asimdsamefp16_only(Rd, Rn, Rm, o1, Q) /* FSCALE ., ., . (bfe0fc00/2ec03c00) */ //#define IEM_INSTR_IMPL_A64__FSCALE_asimdsamefp16_only(Rd, Rn, Rm, Q) /* * * Instruction Set & Groups: asimdshf / simd_dp / A64 * */ /* SSHR ., ., # (bf80fc00/0f000400) */ //#define IEM_INSTR_IMPL_A64__SSHR_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q) /* SSRA ., ., # (bf80fc00/0f001400) */ //#define IEM_INSTR_IMPL_A64__SSRA_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q) /* SRSHR ., ., # (bf80fc00/0f002400) */ //#define IEM_INSTR_IMPL_A64__SRSHR_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q) /* SRSRA ., ., # (bf80fc00/0f003400) */ //#define IEM_INSTR_IMPL_A64__SRSRA_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q) /* SHL ., ., # (bf80fc00/0f005400) */ //#define IEM_INSTR_IMPL_A64__SHL_asimdshf_R(Rd, Rn, immb, immh, Q) /* SQSHL ., ., # (bf80fc00/0f007400) */ //#define IEM_INSTR_IMPL_A64__SQSHL_asimdshf_R(Rd, Rn, op, immb, immh, Q) /* SHRN2 ., ., # (bf80fc00/0f008400) */ //#define IEM_INSTR_IMPL_A64__SHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q) /* RSHRN2 ., ., # (bf80fc00/0f008c00) */ //#define IEM_INSTR_IMPL_A64__RSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q) /* SQSHRN2 ., ., # (bf80fc00/0f009400) */ //#define IEM_INSTR_IMPL_A64__SQSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q) /* SQRSHRN2 ., ., # (bf80fc00/0f009c00) */ //#define IEM_INSTR_IMPL_A64__SQRSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q) /* SSHLL2 ., ., # (bf80fc00/0f00a400) */ //#define IEM_INSTR_IMPL_A64__SSHLL_asimdshf_L(Rd, Rn, immb, immh, Q) /* SCVTF ., ., # (bf80fc00/0f00e400) */ //#define IEM_INSTR_IMPL_A64__SCVTF_asimdshf_C(Rd, Rn, immb, immh, Q) /* FCVTZS ., ., # (bf80fc00/0f00fc00) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_asimdshf_C(Rd, Rn, immb, immh, Q) /* USHR ., ., # (bf80fc00/2f000400) */ //#define IEM_INSTR_IMPL_A64__USHR_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q) /* USRA ., ., # (bf80fc00/2f001400) */ //#define IEM_INSTR_IMPL_A64__USRA_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q) /* URSHR ., ., # (bf80fc00/2f002400) */ //#define IEM_INSTR_IMPL_A64__URSHR_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q) /* URSRA ., ., # (bf80fc00/2f003400) */ //#define IEM_INSTR_IMPL_A64__URSRA_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q) /* SRI ., ., # (bf80fc00/2f004400) */ //#define IEM_INSTR_IMPL_A64__SRI_asimdshf_R(Rd, Rn, immb, immh, Q) /* SLI ., ., # (bf80fc00/2f005400) */ //#define IEM_INSTR_IMPL_A64__SLI_asimdshf_R(Rd, Rn, immb, immh, Q) /* SQSHLU ., ., # (bf80fc00/2f006400) */ //#define IEM_INSTR_IMPL_A64__SQSHLU_asimdshf_R(Rd, Rn, op, immb, immh, Q) /* UQSHL ., ., # (bf80fc00/2f007400) */ //#define IEM_INSTR_IMPL_A64__UQSHL_asimdshf_R(Rd, Rn, op, immb, immh, Q) /* SQSHRUN2 ., ., # (bf80fc00/2f008400) */ //#define IEM_INSTR_IMPL_A64__SQSHRUN_asimdshf_N(Rd, Rn, op, immb, immh, Q) /* SQRSHRUN2 ., ., # (bf80fc00/2f008c00) */ //#define IEM_INSTR_IMPL_A64__SQRSHRUN_asimdshf_N(Rd, Rn, op, immb, immh, Q) /* UQSHRN2 ., ., # (bf80fc00/2f009400) */ //#define IEM_INSTR_IMPL_A64__UQSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q) /* UQRSHRN2 ., ., # (bf80fc00/2f009c00) */ //#define IEM_INSTR_IMPL_A64__UQRSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q) /* USHLL2 ., ., # (bf80fc00/2f00a400) */ //#define IEM_INSTR_IMPL_A64__USHLL_asimdshf_L(Rd, Rn, immb, immh, Q) /* UCVTF ., ., # (bf80fc00/2f00e400) */ //#define IEM_INSTR_IMPL_A64__UCVTF_asimdshf_C(Rd, Rn, immb, immh, Q) /* FCVTZU ., ., # (bf80fc00/2f00fc00) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_asimdshf_C(Rd, Rn, immb, immh, Q) /* * * Instruction Set & Groups: asimdtbl / simd_dp / A64 * */ /* TBL ., { .16B }, . (bfe0fc00/0e000000) */ //#define IEM_INSTR_IMPL_A64__TBL_asimdtbl_L1_1(Rd, Rn, Rm, Q) /* TBX ., { .16B }, . (bfe0fc00/0e001000) */ //#define IEM_INSTR_IMPL_A64__TBX_asimdtbl_L1_1(Rd, Rn, Rm, Q) /* TBL ., { .16B, .16B }, . (bfe0fc00/0e002000) */ //#define IEM_INSTR_IMPL_A64__TBL_asimdtbl_L2_2(Rd, Rn, Rm, Q) /* TBX ., { .16B, .16B }, . (bfe0fc00/0e003000) */ //#define IEM_INSTR_IMPL_A64__TBX_asimdtbl_L2_2(Rd, Rn, Rm, Q) /* TBL ., { .16B, .16B, .16B }, . (bfe0fc00/0e004000) */ //#define IEM_INSTR_IMPL_A64__TBL_asimdtbl_L3_3(Rd, Rn, Rm, Q) /* TBX ., { .16B, .16B, .16B }, . (bfe0fc00/0e005000) */ //#define IEM_INSTR_IMPL_A64__TBX_asimdtbl_L3_3(Rd, Rn, Rm, Q) /* TBL ., { .16B, .16B, .16B, .16B }, . (bfe0fc00/0e006000) */ //#define IEM_INSTR_IMPL_A64__TBL_asimdtbl_L4_4(Rd, Rn, Rm, Q) /* TBX ., { .16B, .16B, .16B, .16B }, . (bfe0fc00/0e007000) */ //#define IEM_INSTR_IMPL_A64__TBX_asimdtbl_L4_4(Rd, Rn, Rm, Q) /* LUTI4 .8H, { .8H, .8H }, [] (ffe09c00/4e401000) */ //#define IEM_INSTR_IMPL_A64__LUTI4_asimdtbl_L7(Rd, Rn, len, Rm) /* LUTI4 .16B, { .16B }, [] (ffe0bc00/4e402000) */ //#define IEM_INSTR_IMPL_A64__LUTI4_asimdtbl_L5(Rd, Rn, len, Rm) /* LUTI2 .16B, { .16B }, [] (ffe09c00/4e801000) */ //#define IEM_INSTR_IMPL_A64__LUTI2_asimdtbl_L5(Rd, Rn, len, Rm) /* LUTI2 .8H, { .8H }, [] (ffe08c00/4ec00000) */ //#define IEM_INSTR_IMPL_A64__LUTI2_asimdtbl_L6(Rd, Rn, op, len, Rm) /* * * Instruction Set & Groups: asisddiff / simd_dp / A64 * */ /* SQDMLAL , , (ff20fc00/5e209000) */ //#define IEM_INSTR_IMPL_A64__SQDMLAL_asisddiff_only(Rd, Rn, o1, Rm, size) /* SQDMLSL , , (ff20fc00/5e20b000) */ //#define IEM_INSTR_IMPL_A64__SQDMLSL_asisddiff_only(Rd, Rn, o1, Rm, size) /* SQDMULL , , (ff20fc00/5e20d000) */ //#define IEM_INSTR_IMPL_A64__SQDMULL_asisddiff_only(Rd, Rn, Rm, size) /* * * Instruction Set & Groups: asisdelem / simd_dp / A64 * */ /* SQDMLAL , , .[] (ff00f400/5f003000) */ //#define IEM_INSTR_IMPL_A64__SQDMLAL_asisdelem_L(Rd, Rn, H, o2, Rm, M, L, size) /* SQDMLSL , , .[] (ff00f400/5f007000) */ //#define IEM_INSTR_IMPL_A64__SQDMLSL_asisdelem_L(Rd, Rn, H, o2, Rm, M, L, size) /* SQDMULL , , .[] (ff00f400/5f00b000) */ //#define IEM_INSTR_IMPL_A64__SQDMULL_asisdelem_L(Rd, Rn, H, Rm, M, L, size) /* SQDMULH , , .[] (ff00f400/5f00c000) */ //#define IEM_INSTR_IMPL_A64__SQDMULH_asisdelem_R(Rd, Rn, H, op, Rm, M, L, size) /* SQRDMULH , , .[] (ff00f400/5f00d000) */ //#define IEM_INSTR_IMPL_A64__SQRDMULH_asisdelem_R(Rd, Rn, H, op, Rm, M, L, size) /* FMLA , , .H[] (ffc0f400/5f001000) */ //#define IEM_INSTR_IMPL_A64__FMLA_asisdelem_RH_H(Rd, Rn, H, o2, Rm, M, L) /* FMLS , , .H[] (ffc0f400/5f005000) */ //#define IEM_INSTR_IMPL_A64__FMLS_asisdelem_RH_H(Rd, Rn, H, o2, Rm, M, L) /* FMUL , , .H[] (ffc0f400/5f009000) */ //#define IEM_INSTR_IMPL_A64__FMUL_asisdelem_RH_H(Rd, Rn, H, Rm, M, L) /* FMLA , , .[] (ff80f400/5f801000) */ //#define IEM_INSTR_IMPL_A64__FMLA_asisdelem_R_SD(Rd, Rn, H, o2, Rm, M, L, sz) /* FMLS , , .[] (ff80f400/5f805000) */ //#define IEM_INSTR_IMPL_A64__FMLS_asisdelem_R_SD(Rd, Rn, H, o2, Rm, M, L, sz) /* FMUL , , .[] (ff80f400/5f809000) */ //#define IEM_INSTR_IMPL_A64__FMUL_asisdelem_R_SD(Rd, Rn, H, Rm, M, L, sz) /* SQRDMLAH , , .[] (ff00f400/7f00d000) */ //#define IEM_INSTR_IMPL_A64__SQRDMLAH_asisdelem_R(Rd, Rn, H, S, Rm, M, L, size) /* SQRDMLSH , , .[] (ff00f400/7f00f000) */ //#define IEM_INSTR_IMPL_A64__SQRDMLSH_asisdelem_R(Rd, Rn, H, S, Rm, M, L, size) /* FMULX , , .H[] (ffc0f400/7f009000) */ //#define IEM_INSTR_IMPL_A64__FMULX_asisdelem_RH_H(Rd, Rn, H, Rm, M, L) /* FMULX , , .[] (ff80f400/7f809000) */ //#define IEM_INSTR_IMPL_A64__FMULX_asisdelem_R_SD(Rd, Rn, H, Rm, M, L, sz) /* * * Instruction Set & Groups: asisdlse / ldst / A64 * */ /* ST4 { ., ., ., . }, [] (bffff000/0c000000) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlse_R4(Rt, Rn, size, Q) /* ST1 { ., ., ., . }, [] (bffff000/0c002000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlse_R4_4v(Rt, Rn, size, Q) /* ST3 { ., ., . }, [] (bffff000/0c004000) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlse_R3(Rt, Rn, size, Q) /* ST1 { ., ., . }, [] (bffff000/0c006000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlse_R3_3v(Rt, Rn, size, Q) /* ST1 { . }, [] (bffff000/0c007000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlse_R1_1v(Rt, Rn, size, Q) /* ST2 { ., . }, [] (bffff000/0c008000) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlse_R2(Rt, Rn, size, Q) /* ST1 { ., . }, [] (bffff000/0c00a000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlse_R2_2v(Rt, Rn, size, Q) /* LD4 { ., ., ., . }, [] (bffff000/0c400000) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlse_R4(Rt, Rn, size, Q) /* LD1 { ., ., ., . }, [] (bffff000/0c402000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlse_R4_4v(Rt, Rn, size, Q) /* LD3 { ., ., . }, [] (bffff000/0c404000) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlse_R3(Rt, Rn, size, Q) /* LD1 { ., ., . }, [] (bffff000/0c406000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlse_R3_3v(Rt, Rn, size, Q) /* LD1 { . }, [] (bffff000/0c407000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlse_R1_1v(Rt, Rn, size, Q) /* LD2 { ., . }, [] (bffff000/0c408000) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlse_R2(Rt, Rn, size, Q) /* LD1 { ., . }, [] (bffff000/0c40a000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlse_R2_2v(Rt, Rn, size, Q) /* * * Instruction Set & Groups: asisdlsep / ldst / A64 * */ /* ST4 { ., ., ., . }, [], (bfe0f000/0c800000) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlsep_R4_r(Rt, Rn, size, Rm, Q) /* ST1 { ., ., ., . }, [], (bfe0f000/0c802000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_R4_r4(Rt, Rn, size, Rm, Q) /* ST3 { ., ., . }, [], (bfe0f000/0c804000) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlsep_R3_r(Rt, Rn, size, Rm, Q) /* ST1 { ., ., . }, [], (bfe0f000/0c806000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_R3_r3(Rt, Rn, size, Rm, Q) /* ST1 { . }, [], (bfe0f000/0c807000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_R1_r1(Rt, Rn, size, Rm, Q) /* ST2 { ., . }, [], (bfe0f000/0c808000) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlsep_R2_r(Rt, Rn, size, Rm, Q) /* ST1 { ., . }, [], (bfe0f000/0c80a000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_R2_r2(Rt, Rn, size, Rm, Q) /* ST4 { ., ., ., . }, [], (bffff000/0c9f0000) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlsep_I4_i(Rt, Rn, size, Q) /* ST1 { ., ., ., . }, [], (bffff000/0c9f2000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_I4_i4(Rt, Rn, size, Q) /* ST3 { ., ., . }, [], (bffff000/0c9f4000) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlsep_I3_i(Rt, Rn, size, Q) /* ST1 { ., ., . }, [], (bffff000/0c9f6000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_I3_i3(Rt, Rn, size, Q) /* ST1 { . }, [], (bffff000/0c9f7000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_I1_i1(Rt, Rn, size, Q) /* ST2 { ., . }, [], (bffff000/0c9f8000) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlsep_I2_i(Rt, Rn, size, Q) /* ST1 { ., . }, [], (bffff000/0c9fa000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_I2_i2(Rt, Rn, size, Q) /* LD4 { ., ., ., . }, [], (bfe0f000/0cc00000) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlsep_R4_r(Rt, Rn, size, Rm, Q) /* LD1 { ., ., ., . }, [], (bfe0f000/0cc02000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_R4_r4(Rt, Rn, size, Rm, Q) /* LD3 { ., ., . }, [], (bfe0f000/0cc04000) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlsep_R3_r(Rt, Rn, size, Rm, Q) /* LD1 { ., ., . }, [], (bfe0f000/0cc06000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_R3_r3(Rt, Rn, size, Rm, Q) /* LD1 { . }, [], (bfe0f000/0cc07000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_R1_r1(Rt, Rn, size, Rm, Q) /* LD2 { ., . }, [], (bfe0f000/0cc08000) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlsep_R2_r(Rt, Rn, size, Rm, Q) /* LD1 { ., . }, [], (bfe0f000/0cc0a000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_R2_r2(Rt, Rn, size, Rm, Q) /* LD4 { ., ., ., . }, [], (bffff000/0cdf0000) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlsep_I4_i(Rt, Rn, size, Q) /* LD1 { ., ., ., . }, [], (bffff000/0cdf2000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_I4_i4(Rt, Rn, size, Q) /* LD3 { ., ., . }, [], (bffff000/0cdf4000) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlsep_I3_i(Rt, Rn, size, Q) /* LD1 { ., ., . }, [], (bffff000/0cdf6000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_I3_i3(Rt, Rn, size, Q) /* LD1 { . }, [], (bffff000/0cdf7000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_I1_i1(Rt, Rn, size, Q) /* LD2 { ., . }, [], (bffff000/0cdf8000) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlsep_I2_i(Rt, Rn, size, Q) /* LD1 { ., . }, [], (bffff000/0cdfa000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_I2_i2(Rt, Rn, size, Q) /* * * Instruction Set & Groups: asisdlso / ldst / A64 * */ /* ST1 { .B }[], [] (bfffe000/0d000000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlso_B1_1b(Rt, Rn, size, S, Q) /* ST3 { .B, .B, .B }[], [] (bfffe000/0d002000) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlso_B3_3b(Rt, Rn, size, S, Q) /* ST1 { .H }[], [] (bfffe400/0d004000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlso_H1_1h(Rt, Rn, size, S, Q) /* ST3 { .H, .H, .H }[], [] (bfffe400/0d006000) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlso_H3_3h(Rt, Rn, size, S, Q) /* ST1 { .S }[], [] (bfffec00/0d008000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlso_S1_1s(Rt, Rn, S, Q) /* ST1 { .D }[], [] (bffffc00/0d008400) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlso_D1_1d(Rt, Rn, Q) /* ST3 { .S, .S, .S }[], [] (bfffec00/0d00a000) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlso_S3_3s(Rt, Rn, S, Q) /* ST3 { .D, .D, .D }[], [] (bffffc00/0d00a400) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlso_D3_3d(Rt, Rn, Q) /* STL1 { .D }[], [] (bffffc00/0d018400) */ //#define IEM_INSTR_IMPL_A64__STL1_asisdlso_D1(Rt, Rn, Q) /* ST2 { .B, .B }[], [] (bfffe000/0d200000) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlso_B2_2b(Rt, Rn, size, S, Q) /* ST4 { .B, .B, .B, .B }[], [] (bfffe000/0d202000) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlso_B4_4b(Rt, Rn, size, S, Q) /* ST2 { .H, .H }[], [] (bfffe400/0d204000) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlso_H2_2h(Rt, Rn, size, S, Q) /* ST4 { .H, .H, .H, .H }[], [] (bfffe400/0d206000) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlso_H4_4h(Rt, Rn, size, S, Q) /* ST2 { .S, .S }[], [] (bfffec00/0d208000) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlso_S2_2s(Rt, Rn, S, Q) /* ST2 { .D, .D }[], [] (bffffc00/0d208400) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlso_D2_2d(Rt, Rn, Q) /* ST4 { .S, .S, .S, .S }[], [] (bfffec00/0d20a000) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlso_S4_4s(Rt, Rn, S, Q) /* ST4 { .D, .D, .D, .D }[], [] (bffffc00/0d20a400) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlso_D4_4d(Rt, Rn, Q) /* LD1 { .B }[], [] (bfffe000/0d400000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlso_B1_1b(Rt, Rn, size, S, Q) /* LD3 { .B, .B, .B }[], [] (bfffe000/0d402000) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlso_B3_3b(Rt, Rn, size, S, Q) /* LD1 { .H }[], [] (bfffe400/0d404000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlso_H1_1h(Rt, Rn, size, S, Q) /* LD3 { .H, .H, .H }[], [] (bfffe400/0d406000) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlso_H3_3h(Rt, Rn, size, S, Q) /* LD1 { .S }[], [] (bfffec00/0d408000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlso_S1_1s(Rt, Rn, S, Q) /* LD1 { .D }[], [] (bffffc00/0d408400) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlso_D1_1d(Rt, Rn, Q) /* LD3 { .S, .S, .S }[], [] (bfffec00/0d40a000) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlso_S3_3s(Rt, Rn, S, Q) /* LD3 { .D, .D, .D }[], [] (bffffc00/0d40a400) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlso_D3_3d(Rt, Rn, Q) /* LD1R { . }, [] (bffff000/0d40c000) */ //#define IEM_INSTR_IMPL_A64__LD1R_asisdlso_R1(Rt, Rn, size, Q) /* LD3R { ., ., . }, [] (bffff000/0d40e000) */ //#define IEM_INSTR_IMPL_A64__LD3R_asisdlso_R3(Rt, Rn, size, Q) /* LDAP1 { .D }[], [] (bffffc00/0d418400) */ //#define IEM_INSTR_IMPL_A64__LDAP1_asisdlso_D1(Rt, Rn, Q) /* LD2 { .B, .B }[], [] (bfffe000/0d600000) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlso_B2_2b(Rt, Rn, size, S, Q) /* LD4 { .B, .B, .B, .B }[], [] (bfffe000/0d602000) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlso_B4_4b(Rt, Rn, size, S, Q) /* LD2 { .H, .H }[], [] (bfffe400/0d604000) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlso_H2_2h(Rt, Rn, size, S, Q) /* LD4 { .H, .H, .H, .H }[], [] (bfffe400/0d606000) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlso_H4_4h(Rt, Rn, size, S, Q) /* LD2 { .S, .S }[], [] (bfffec00/0d608000) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlso_S2_2s(Rt, Rn, S, Q) /* LD2 { .D, .D }[], [] (bffffc00/0d608400) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlso_D2_2d(Rt, Rn, Q) /* LD4 { .S, .S, .S, .S }[], [] (bfffec00/0d60a000) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlso_S4_4s(Rt, Rn, S, Q) /* LD4 { .D, .D, .D, .D }[], [] (bffffc00/0d60a400) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlso_D4_4d(Rt, Rn, Q) /* LD2R { ., . }, [] (bffff000/0d60c000) */ //#define IEM_INSTR_IMPL_A64__LD2R_asisdlso_R2(Rt, Rn, size, Q) /* LD4R { ., ., ., . }, [] (bffff000/0d60e000) */ //#define IEM_INSTR_IMPL_A64__LD4R_asisdlso_R4(Rt, Rn, size, Q) /* * * Instruction Set & Groups: asisdlsop / ldst / A64 * */ /* ST1 { .B }[], [], (bfe0e000/0d800000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_BX1_r1b(Rt, Rn, size, S, Rm, Q) /* ST3 { .B, .B, .B }[], [], (bfe0e000/0d802000) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_BX3_r3b(Rt, Rn, size, S, Rm, Q) /* ST1 { .H }[], [], (bfe0e400/0d804000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_HX1_r1h(Rt, Rn, size, S, Rm, Q) /* ST3 { .H, .H, .H }[], [], (bfe0e400/0d806000) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_HX3_r3h(Rt, Rn, size, S, Rm, Q) /* ST1 { .S }[], [], (bfe0ec00/0d808000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_SX1_r1s(Rt, Rn, S, Rm, Q) /* ST1 { .D }[], [], (bfe0fc00/0d808400) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_DX1_r1d(Rt, Rn, Rm, Q) /* ST3 { .S, .S, .S }[], [], (bfe0ec00/0d80a000) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_SX3_r3s(Rt, Rn, S, Rm, Q) /* ST3 { .D, .D, .D }[], [], (bfe0fc00/0d80a400) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_DX3_r3d(Rt, Rn, Rm, Q) /* ST1 { .B }[], [], #1 (bfffe000/0d9f0000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_B1_i1b(Rt, Rn, size, S, Q) /* ST3 { .B, .B, .B }[], [], #3 (bfffe000/0d9f2000) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_B3_i3b(Rt, Rn, size, S, Q) /* ST1 { .H }[], [], #2 (bfffe400/0d9f4000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_H1_i1h(Rt, Rn, size, S, Q) /* ST3 { .H, .H, .H }[], [], #6 (bfffe400/0d9f6000) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_H3_i3h(Rt, Rn, size, S, Q) /* ST1 { .S }[], [], #4 (bfffec00/0d9f8000) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_S1_i1s(Rt, Rn, S, Q) /* ST1 { .D }[], [], #8 (bffffc00/0d9f8400) */ //#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_D1_i1d(Rt, Rn, Q) /* ST3 { .S, .S, .S }[], [], #12 (bfffec00/0d9fa000) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_S3_i3s(Rt, Rn, S, Q) /* ST3 { .D, .D, .D }[], [], #24 (bffffc00/0d9fa400) */ //#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_D3_i3d(Rt, Rn, Q) /* ST2 { .B, .B }[], [], (bfe0e000/0da00000) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_BX2_r2b(Rt, Rn, size, S, Rm, Q) /* ST4 { .B, .B, .B, .B }[], [], (bfe0e000/0da02000) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_BX4_r4b(Rt, Rn, size, S, Rm, Q) /* ST2 { .H, .H }[], [], (bfe0e400/0da04000) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_HX2_r2h(Rt, Rn, size, S, Rm, Q) /* ST4 { .H, .H, .H, .H }[], [], (bfe0e400/0da06000) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_HX4_r4h(Rt, Rn, size, S, Rm, Q) /* ST2 { .S, .S }[], [], (bfe0ec00/0da08000) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_SX2_r2s(Rt, Rn, S, Rm, Q) /* ST2 { .D, .D }[], [], (bfe0fc00/0da08400) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_DX2_r2d(Rt, Rn, Rm, Q) /* ST4 { .S, .S, .S, .S }[], [], (bfe0ec00/0da0a000) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_SX4_r4s(Rt, Rn, S, Rm, Q) /* ST4 { .D, .D, .D, .D }[], [], (bfe0fc00/0da0a400) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_DX4_r4d(Rt, Rn, Rm, Q) /* ST2 { .B, .B }[], [], #2 (bfffe000/0dbf0000) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_B2_i2b(Rt, Rn, size, S, Q) /* ST4 { .B, .B, .B, .B }[], [], #4 (bfffe000/0dbf2000) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_B4_i4b(Rt, Rn, size, S, Q) /* ST2 { .H, .H }[], [], #4 (bfffe400/0dbf4000) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_H2_i2h(Rt, Rn, size, S, Q) /* ST4 { .H, .H, .H, .H }[], [], #8 (bfffe400/0dbf6000) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_H4_i4h(Rt, Rn, size, S, Q) /* ST2 { .S, .S }[], [], #8 (bfffec00/0dbf8000) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_S2_i2s(Rt, Rn, S, Q) /* ST2 { .D, .D }[], [], #16 (bffffc00/0dbf8400) */ //#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_D2_i2d(Rt, Rn, Q) /* ST4 { .S, .S, .S, .S }[], [], #16 (bfffec00/0dbfa000) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_S4_i4s(Rt, Rn, S, Q) /* ST4 { .D, .D, .D, .D }[], [], #32 (bffffc00/0dbfa400) */ //#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_D4_i4d(Rt, Rn, Q) /* LD1 { .B }[], [], (bfe0e000/0dc00000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_BX1_r1b(Rt, Rn, size, S, Rm, Q) /* LD3 { .B, .B, .B }[], [], (bfe0e000/0dc02000) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_BX3_r3b(Rt, Rn, size, S, Rm, Q) /* LD1 { .H }[], [], (bfe0e400/0dc04000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_HX1_r1h(Rt, Rn, size, S, Rm, Q) /* LD3 { .H, .H, .H }[], [], (bfe0e400/0dc06000) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_HX3_r3h(Rt, Rn, size, S, Rm, Q) /* LD1 { .S }[], [], (bfe0ec00/0dc08000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_SX1_r1s(Rt, Rn, S, Rm, Q) /* LD1 { .D }[], [], (bfe0fc00/0dc08400) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_DX1_r1d(Rt, Rn, Rm, Q) /* LD3 { .S, .S, .S }[], [], (bfe0ec00/0dc0a000) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_SX3_r3s(Rt, Rn, S, Rm, Q) /* LD3 { .D, .D, .D }[], [], (bfe0fc00/0dc0a400) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_DX3_r3d(Rt, Rn, Rm, Q) /* LD1R { . }, [], (bfe0f000/0dc0c000) */ //#define IEM_INSTR_IMPL_A64__LD1R_asisdlsop_RX1_r(Rt, Rn, size, Rm, Q) /* LD3R { ., ., . }, [], (bfe0f000/0dc0e000) */ //#define IEM_INSTR_IMPL_A64__LD3R_asisdlsop_RX3_r(Rt, Rn, size, Rm, Q) /* LD1 { .B }[], [], #1 (bfffe000/0ddf0000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_B1_i1b(Rt, Rn, size, S, Q) /* LD3 { .B, .B, .B }[], [], #3 (bfffe000/0ddf2000) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_B3_i3b(Rt, Rn, size, S, Q) /* LD1 { .H }[], [], #2 (bfffe400/0ddf4000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_H1_i1h(Rt, Rn, size, S, Q) /* LD3 { .H, .H, .H }[], [], #6 (bfffe400/0ddf6000) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_H3_i3h(Rt, Rn, size, S, Q) /* LD1 { .S }[], [], #4 (bfffec00/0ddf8000) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_S1_i1s(Rt, Rn, S, Q) /* LD1 { .D }[], [], #8 (bffffc00/0ddf8400) */ //#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_D1_i1d(Rt, Rn, Q) /* LD3 { .S, .S, .S }[], [], #12 (bfffec00/0ddfa000) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_S3_i3s(Rt, Rn, S, Q) /* LD3 { .D, .D, .D }[], [], #24 (bffffc00/0ddfa400) */ //#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_D3_i3d(Rt, Rn, Q) /* LD1R { . }, [], (bffff000/0ddfc000) */ //#define IEM_INSTR_IMPL_A64__LD1R_asisdlsop_R1_i(Rt, Rn, size, Q) /* LD3R { ., ., . }, [], (bffff000/0ddfe000) */ //#define IEM_INSTR_IMPL_A64__LD3R_asisdlsop_R3_i(Rt, Rn, size, Q) /* LD2 { .B, .B }[], [], (bfe0e000/0de00000) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_BX2_r2b(Rt, Rn, size, S, Rm, Q) /* LD4 { .B, .B, .B, .B }[], [], (bfe0e000/0de02000) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_BX4_r4b(Rt, Rn, size, S, Rm, Q) /* LD2 { .H, .H }[], [], (bfe0e400/0de04000) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_HX2_r2h(Rt, Rn, size, S, Rm, Q) /* LD4 { .H, .H, .H, .H }[], [], (bfe0e400/0de06000) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_HX4_r4h(Rt, Rn, size, S, Rm, Q) /* LD2 { .S, .S }[], [], (bfe0ec00/0de08000) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_SX2_r2s(Rt, Rn, S, Rm, Q) /* LD2 { .D, .D }[], [], (bfe0fc00/0de08400) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_DX2_r2d(Rt, Rn, Rm, Q) /* LD4 { .S, .S, .S, .S }[], [], (bfe0ec00/0de0a000) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_SX4_r4s(Rt, Rn, S, Rm, Q) /* LD4 { .D, .D, .D, .D }[], [], (bfe0fc00/0de0a400) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_DX4_r4d(Rt, Rn, Rm, Q) /* LD2R { ., . }, [], (bfe0f000/0de0c000) */ //#define IEM_INSTR_IMPL_A64__LD2R_asisdlsop_RX2_r(Rt, Rn, size, Rm, Q) /* LD4R { ., ., ., . }, [], (bfe0f000/0de0e000) */ //#define IEM_INSTR_IMPL_A64__LD4R_asisdlsop_RX4_r(Rt, Rn, size, Rm, Q) /* LD2 { .B, .B }[], [], #2 (bfffe000/0dff0000) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_B2_i2b(Rt, Rn, size, S, Q) /* LD4 { .B, .B, .B, .B }[], [], #4 (bfffe000/0dff2000) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_B4_i4b(Rt, Rn, size, S, Q) /* LD2 { .H, .H }[], [], #4 (bfffe400/0dff4000) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_H2_i2h(Rt, Rn, size, S, Q) /* LD4 { .H, .H, .H, .H }[], [], #8 (bfffe400/0dff6000) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_H4_i4h(Rt, Rn, size, S, Q) /* LD2 { .S, .S }[], [], #8 (bfffec00/0dff8000) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_S2_i2s(Rt, Rn, S, Q) /* LD2 { .D, .D }[], [], #16 (bffffc00/0dff8400) */ //#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_D2_i2d(Rt, Rn, Q) /* LD4 { .S, .S, .S, .S }[], [], #16 (bfffec00/0dffa000) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_S4_i4s(Rt, Rn, S, Q) /* LD4 { .D, .D, .D, .D }[], [], #32 (bffffc00/0dffa400) */ //#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_D4_i4d(Rt, Rn, Q) /* LD2R { ., . }, [], (bffff000/0dffc000) */ //#define IEM_INSTR_IMPL_A64__LD2R_asisdlsop_R2_i(Rt, Rn, size, Q) /* LD4R { ., ., ., . }, [], (bffff000/0dffe000) */ //#define IEM_INSTR_IMPL_A64__LD4R_asisdlsop_R4_i(Rt, Rn, size, Q) /* * * Instruction Set & Groups: asisdmisc / simd_dp / A64 * */ /* SUQADD , (ff3ffc00/5e203800) */ //#define IEM_INSTR_IMPL_A64__SUQADD_asisdmisc_R(Rd, Rn, size) /* SQABS , (ff3ffc00/5e207800) */ //#define IEM_INSTR_IMPL_A64__SQABS_asisdmisc_R(Rd, Rn, size) /* CMGT D, D, #0 (fffffc00/5ee08800) */ //#define IEM_INSTR_IMPL_A64__CMGT_asisdmisc_Z(Rd, Rn, op) /* CMEQ D, D, #0 (fffffc00/5ee09800) */ //#define IEM_INSTR_IMPL_A64__CMEQ_asisdmisc_Z(Rd, Rn, op) /* CMLT D, D, #0 (fffffc00/5ee0a800) */ //#define IEM_INSTR_IMPL_A64__CMLT_asisdmisc_Z(Rd, Rn) /* ABS D, D (fffffc00/5ee0b800) */ //#define IEM_INSTR_IMPL_A64__ABS_asisdmisc_R(Rd, Rn) /* SQXTN , (ff3ffc00/5e214800) */ //#define IEM_INSTR_IMPL_A64__SQXTN_asisdmisc_N(Rd, Rn, size) /* FCVTNS , (ffbffc00/5e21a800) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_asisdmisc_R(Rd, Rn, o1, sz, o2) /* FCVTMS , (ffbffc00/5e21b800) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_asisdmisc_R(Rd, Rn, o1, sz, o2) /* FCVTAS , (ffbffc00/5e21c800) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_asisdmisc_R(Rd, Rn, sz) /* SCVTF , (ffbffc00/5e21d800) */ //#define IEM_INSTR_IMPL_A64__SCVTF_asisdmisc_R(Rd, Rn, sz) /* FCMGT , , #0.0 (ffbffc00/5ea0c800) */ //#define IEM_INSTR_IMPL_A64__FCMGT_asisdmisc_FZ(Rd, Rn, op, sz) /* FCMEQ , , #0.0 (ffbffc00/5ea0d800) */ //#define IEM_INSTR_IMPL_A64__FCMEQ_asisdmisc_FZ(Rd, Rn, op, sz) /* FCMLT , , #0.0 (ffbffc00/5ea0e800) */ //#define IEM_INSTR_IMPL_A64__FCMLT_asisdmisc_FZ(Rd, Rn, sz) /* FCVTPS , (ffbffc00/5ea1a800) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_asisdmisc_R(Rd, Rn, o1, sz, o2) /* FCVTZS , (ffbffc00/5ea1b800) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_asisdmisc_R(Rd, Rn, o1, sz, o2) /* FRECPE , (ffbffc00/5ea1d800) */ //#define IEM_INSTR_IMPL_A64__FRECPE_asisdmisc_R(Rd, Rn, sz) /* FRECPX , (ffbffc00/5ea1f800) */ //#define IEM_INSTR_IMPL_A64__FRECPX_asisdmisc_R(Rd, Rn, sz) /* USQADD , (ff3ffc00/7e203800) */ //#define IEM_INSTR_IMPL_A64__USQADD_asisdmisc_R(Rd, Rn, size) /* SQNEG , (ff3ffc00/7e207800) */ //#define IEM_INSTR_IMPL_A64__SQNEG_asisdmisc_R(Rd, Rn, size) /* CMGE D, D, #0 (fffffc00/7ee08800) */ //#define IEM_INSTR_IMPL_A64__CMGE_asisdmisc_Z(Rd, Rn, op) /* CMLE D, D, #0 (fffffc00/7ee09800) */ //#define IEM_INSTR_IMPL_A64__CMLE_asisdmisc_Z(Rd, Rn, op) /* NEG D, D (fffffc00/7ee0b800) */ //#define IEM_INSTR_IMPL_A64__NEG_asisdmisc_R(Rd, Rn) /* SQXTUN , (ff3ffc00/7e212800) */ //#define IEM_INSTR_IMPL_A64__SQXTUN_asisdmisc_N(Rd, Rn, size) /* UQXTN , (ff3ffc00/7e214800) */ //#define IEM_INSTR_IMPL_A64__UQXTN_asisdmisc_N(Rd, Rn, size) /* FCVTXN S, D (fffffc00/7e616800) */ //#define IEM_INSTR_IMPL_A64__FCVTXN_asisdmisc_N(Rd, Rn) /* FCVTNU , (ffbffc00/7e21a800) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_asisdmisc_R(Rd, Rn, o1, sz, o2) /* FCVTMU , (ffbffc00/7e21b800) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_asisdmisc_R(Rd, Rn, o1, sz, o2) /* FCVTAU , (ffbffc00/7e21c800) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_asisdmisc_R(Rd, Rn, sz) /* UCVTF , (ffbffc00/7e21d800) */ //#define IEM_INSTR_IMPL_A64__UCVTF_asisdmisc_R(Rd, Rn, sz) /* FCMGE , , #0.0 (ffbffc00/7ea0c800) */ //#define IEM_INSTR_IMPL_A64__FCMGE_asisdmisc_FZ(Rd, Rn, op, sz) /* FCMLE , , #0.0 (ffbffc00/7ea0d800) */ //#define IEM_INSTR_IMPL_A64__FCMLE_asisdmisc_FZ(Rd, Rn, op, sz) /* FCVTPU , (ffbffc00/7ea1a800) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_asisdmisc_R(Rd, Rn, o1, sz, o2) /* FCVTZU , (ffbffc00/7ea1b800) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_asisdmisc_R(Rd, Rn, o1, sz, o2) /* FRSQRTE , (ffbffc00/7ea1d800) */ //#define IEM_INSTR_IMPL_A64__FRSQRTE_asisdmisc_R(Rd, Rn, sz) /* * * Instruction Set & Groups: asisdmiscfp16 / simd_dp / A64 * */ /* FCVTNS , (fffffc00/5e79a800) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_asisdmiscfp16_R(Rd, Rn, o1, o2) /* FCVTMS , (fffffc00/5e79b800) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_asisdmiscfp16_R(Rd, Rn, o1, o2) /* FCVTAS , (fffffc00/5e79c800) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_asisdmiscfp16_R(Rd, Rn) /* SCVTF , (fffffc00/5e79d800) */ //#define IEM_INSTR_IMPL_A64__SCVTF_asisdmiscfp16_R(Rd, Rn) /* FCMGT , , #0.0 (fffffc00/5ef8c800) */ //#define IEM_INSTR_IMPL_A64__FCMGT_asisdmiscfp16_FZ(Rd, Rn, op) /* FCMEQ , , #0.0 (fffffc00/5ef8d800) */ //#define IEM_INSTR_IMPL_A64__FCMEQ_asisdmiscfp16_FZ(Rd, Rn, op) /* FCMLT , , #0.0 (fffffc00/5ef8e800) */ //#define IEM_INSTR_IMPL_A64__FCMLT_asisdmiscfp16_FZ(Rd, Rn) /* FCVTPS , (fffffc00/5ef9a800) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_asisdmiscfp16_R(Rd, Rn, o1, o2) /* FCVTZS , (fffffc00/5ef9b800) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_asisdmiscfp16_R(Rd, Rn, o1, o2) /* FRECPE , (fffffc00/5ef9d800) */ //#define IEM_INSTR_IMPL_A64__FRECPE_asisdmiscfp16_R(Rd, Rn) /* FRECPX , (fffffc00/5ef9f800) */ //#define IEM_INSTR_IMPL_A64__FRECPX_asisdmiscfp16_R(Rd, Rn) /* FCVTNU , (fffffc00/7e79a800) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_asisdmiscfp16_R(Rd, Rn, o1, o2) /* FCVTMU , (fffffc00/7e79b800) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_asisdmiscfp16_R(Rd, Rn, o1, o2) /* FCVTAU , (fffffc00/7e79c800) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_asisdmiscfp16_R(Rd, Rn) /* UCVTF , (fffffc00/7e79d800) */ //#define IEM_INSTR_IMPL_A64__UCVTF_asisdmiscfp16_R(Rd, Rn) /* FCMGE , , #0.0 (fffffc00/7ef8c800) */ //#define IEM_INSTR_IMPL_A64__FCMGE_asisdmiscfp16_FZ(Rd, Rn, op) /* FCMLE , , #0.0 (fffffc00/7ef8d800) */ //#define IEM_INSTR_IMPL_A64__FCMLE_asisdmiscfp16_FZ(Rd, Rn, op) /* FCVTPU , (fffffc00/7ef9a800) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_asisdmiscfp16_R(Rd, Rn, o1, o2) /* FCVTZU , (fffffc00/7ef9b800) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_asisdmiscfp16_R(Rd, Rn, o1, o2) /* FRSQRTE , (fffffc00/7ef9d800) */ //#define IEM_INSTR_IMPL_A64__FRSQRTE_asisdmiscfp16_R(Rd, Rn) /* * * Instruction Set & Groups: asisdone / simd_dp / A64 * */ /* DUP , .[] (ffe0fc00/5e000400) */ //#define IEM_INSTR_IMPL_A64__DUP_asisdone_only(Rd, Rn, imm5) /* * * Instruction Set & Groups: asisdpair / simd_dp / A64 * */ /* ADDP D, .2D (fffffc00/5ef1b800) */ //#define IEM_INSTR_IMPL_A64__ADDP_asisdpair_only(Rd, Rn) /* FMAXNMP H, .2H (fffffc00/5e30c800) */ //#define IEM_INSTR_IMPL_A64__FMAXNMP_asisdpair_only_H(Rd, Rn, sz, o1) /* FADDP H, .2H (fffffc00/5e30d800) */ //#define IEM_INSTR_IMPL_A64__FADDP_asisdpair_only_H(Rd, Rn, sz) /* FMAXP H, .2H (fffffc00/5e30f800) */ //#define IEM_INSTR_IMPL_A64__FMAXP_asisdpair_only_H(Rd, Rn, sz, o1) /* FMINNMP H, .2H (fffffc00/5eb0c800) */ //#define IEM_INSTR_IMPL_A64__FMINNMP_asisdpair_only_H(Rd, Rn, sz, o1) /* FMINP H, .2H (fffffc00/5eb0f800) */ //#define IEM_INSTR_IMPL_A64__FMINP_asisdpair_only_H(Rd, Rn, sz, o1) /* FMAXNMP , . (ffbffc00/7e30c800) */ //#define IEM_INSTR_IMPL_A64__FMAXNMP_asisdpair_only_SD(Rd, Rn, sz, o1) /* FADDP , . (ffbffc00/7e30d800) */ //#define IEM_INSTR_IMPL_A64__FADDP_asisdpair_only_SD(Rd, Rn, sz) /* FMAXP , . (ffbffc00/7e30f800) */ //#define IEM_INSTR_IMPL_A64__FMAXP_asisdpair_only_SD(Rd, Rn, sz, o1) /* FMINNMP , . (ffbffc00/7eb0c800) */ //#define IEM_INSTR_IMPL_A64__FMINNMP_asisdpair_only_SD(Rd, Rn, sz, o1) /* FMINP , . (ffbffc00/7eb0f800) */ //#define IEM_INSTR_IMPL_A64__FMINP_asisdpair_only_SD(Rd, Rn, sz, o1) /* * * Instruction Set & Groups: asisdsame / simd_dp / A64 * */ /* SQADD , , (ff20fc00/5e200c00) */ //#define IEM_INSTR_IMPL_A64__SQADD_asisdsame_only(Rd, Rn, Rm, size) /* SQSUB , , (ff20fc00/5e202c00) */ //#define IEM_INSTR_IMPL_A64__SQSUB_asisdsame_only(Rd, Rn, Rm, size) /* CMGT D, D, D (ffe0fc00/5ee03400) */ //#define IEM_INSTR_IMPL_A64__CMGT_asisdsame_only(Rd, Rn, eq, Rm) /* CMGE D, D, D (ffe0fc00/5ee03c00) */ //#define IEM_INSTR_IMPL_A64__CMGE_asisdsame_only(Rd, Rn, eq, Rm) /* SSHL D, D, D (ffe0fc00/5ee04400) */ //#define IEM_INSTR_IMPL_A64__SSHL_asisdsame_only(Rd, Rn, S, R, Rm) /* SQSHL , , (ff20fc00/5e204c00) */ //#define IEM_INSTR_IMPL_A64__SQSHL_asisdsame_only(Rd, Rn, S, R, Rm, size) /* SRSHL D, D, D (ffe0fc00/5ee05400) */ //#define IEM_INSTR_IMPL_A64__SRSHL_asisdsame_only(Rd, Rn, S, R, Rm) /* SQRSHL , , (ff20fc00/5e205c00) */ //#define IEM_INSTR_IMPL_A64__SQRSHL_asisdsame_only(Rd, Rn, S, R, Rm, size) /* ADD D, D, D (ffe0fc00/5ee08400) */ //#define IEM_INSTR_IMPL_A64__ADD_asisdsame_only(Rd, Rn, Rm) /* CMTST D, D, D (ffe0fc00/5ee08c00) */ //#define IEM_INSTR_IMPL_A64__CMTST_asisdsame_only(Rd, Rn, Rm) /* SQDMULH , , (ff20fc00/5e20b400) */ //#define IEM_INSTR_IMPL_A64__SQDMULH_asisdsame_only(Rd, Rn, Rm, size) /* FMULX , , (ffa0fc00/5e20dc00) */ //#define IEM_INSTR_IMPL_A64__FMULX_asisdsame_only(Rd, Rn, Rm, sz) /* FCMEQ , , (ffa0fc00/5e20e400) */ //#define IEM_INSTR_IMPL_A64__FCMEQ_asisdsame_only(Rd, Rn, ac, Rm, sz, E) /* FRECPS , , (ffa0fc00/5e20fc00) */ //#define IEM_INSTR_IMPL_A64__FRECPS_asisdsame_only(Rd, Rn, Rm, sz) /* FRSQRTS , , (ffa0fc00/5ea0fc00) */ //#define IEM_INSTR_IMPL_A64__FRSQRTS_asisdsame_only(Rd, Rn, Rm, sz) /* UQADD , , (ff20fc00/7e200c00) */ //#define IEM_INSTR_IMPL_A64__UQADD_asisdsame_only(Rd, Rn, Rm, size) /* UQSUB , , (ff20fc00/7e202c00) */ //#define IEM_INSTR_IMPL_A64__UQSUB_asisdsame_only(Rd, Rn, Rm, size) /* CMHI D, D, D (ffe0fc00/7ee03400) */ //#define IEM_INSTR_IMPL_A64__CMHI_asisdsame_only(Rd, Rn, eq, Rm) /* CMHS D, D, D (ffe0fc00/7ee03c00) */ //#define IEM_INSTR_IMPL_A64__CMHS_asisdsame_only(Rd, Rn, eq, Rm) /* USHL D, D, D (ffe0fc00/7ee04400) */ //#define IEM_INSTR_IMPL_A64__USHL_asisdsame_only(Rd, Rn, S, R, Rm) /* UQSHL , , (ff20fc00/7e204c00) */ //#define IEM_INSTR_IMPL_A64__UQSHL_asisdsame_only(Rd, Rn, S, R, Rm, size) /* URSHL D, D, D (ffe0fc00/7ee05400) */ //#define IEM_INSTR_IMPL_A64__URSHL_asisdsame_only(Rd, Rn, S, R, Rm) /* UQRSHL , , (ff20fc00/7e205c00) */ //#define IEM_INSTR_IMPL_A64__UQRSHL_asisdsame_only(Rd, Rn, S, R, Rm, size) /* SUB D, D, D (ffe0fc00/7ee08400) */ //#define IEM_INSTR_IMPL_A64__SUB_asisdsame_only(Rd, Rn, Rm) /* CMEQ D, D, D (ffe0fc00/7ee08c00) */ //#define IEM_INSTR_IMPL_A64__CMEQ_asisdsame_only(Rd, Rn, Rm) /* SQRDMULH , , (ff20fc00/7e20b400) */ //#define IEM_INSTR_IMPL_A64__SQRDMULH_asisdsame_only(Rd, Rn, Rm, size) /* FCMGE , , (ffa0fc00/7e20e400) */ //#define IEM_INSTR_IMPL_A64__FCMGE_asisdsame_only(Rd, Rn, ac, Rm, sz, E) /* FACGE , , (ffa0fc00/7e20ec00) */ //#define IEM_INSTR_IMPL_A64__FACGE_asisdsame_only(Rd, Rn, ac, Rm, sz, E) /* FABD , , (ffa0fc00/7ea0d400) */ //#define IEM_INSTR_IMPL_A64__FABD_asisdsame_only(Rd, Rn, Rm, sz) /* FCMGT , , (ffa0fc00/7ea0e400) */ //#define IEM_INSTR_IMPL_A64__FCMGT_asisdsame_only(Rd, Rn, ac, Rm, sz, E) /* FACGT , , (ffa0fc00/7ea0ec00) */ //#define IEM_INSTR_IMPL_A64__FACGT_asisdsame_only(Rd, Rn, ac, Rm, sz, E) /* * * Instruction Set & Groups: asisdsame2 / simd_dp / A64 * */ /* SQRDMLAH , , (ff20fc00/7e008400) */ //#define IEM_INSTR_IMPL_A64__SQRDMLAH_asisdsame2_only(Rd, Rn, S, Rm, size) /* SQRDMLSH , , (ff20fc00/7e008c00) */ //#define IEM_INSTR_IMPL_A64__SQRDMLSH_asisdsame2_only(Rd, Rn, S, Rm, size) /* * * Instruction Set & Groups: asisdsamefp16 / simd_dp / A64 * */ /* FMULX , , (ffe0fc00/5e401c00) */ //#define IEM_INSTR_IMPL_A64__FMULX_asisdsamefp16_only(Rd, Rn, Rm) /* FCMEQ , , (ffe0fc00/5e402400) */ //#define IEM_INSTR_IMPL_A64__FCMEQ_asisdsamefp16_only(Rd, Rn, ac, Rm, E) /* FRECPS , , (ffe0fc00/5e403c00) */ //#define IEM_INSTR_IMPL_A64__FRECPS_asisdsamefp16_only(Rd, Rn, Rm) /* FRSQRTS , , (ffe0fc00/5ec03c00) */ //#define IEM_INSTR_IMPL_A64__FRSQRTS_asisdsamefp16_only(Rd, Rn, Rm) /* FCMGE , , (ffe0fc00/7e402400) */ //#define IEM_INSTR_IMPL_A64__FCMGE_asisdsamefp16_only(Rd, Rn, ac, Rm, E) /* FACGE , , (ffe0fc00/7e402c00) */ //#define IEM_INSTR_IMPL_A64__FACGE_asisdsamefp16_only(Rd, Rn, ac, Rm, E) /* FABD , , (ffe0fc00/7ec01400) */ //#define IEM_INSTR_IMPL_A64__FABD_asisdsamefp16_only(Rd, Rn, Rm) /* FCMGT , , (ffe0fc00/7ec02400) */ //#define IEM_INSTR_IMPL_A64__FCMGT_asisdsamefp16_only(Rd, Rn, ac, Rm, E) /* FACGT , , (ffe0fc00/7ec02c00) */ //#define IEM_INSTR_IMPL_A64__FACGT_asisdsamefp16_only(Rd, Rn, ac, Rm, E) /* * * Instruction Set & Groups: asisdshf / simd_dp / A64 * */ /* SSHR D, D, # (ff80fc00/5f000400) */ //#define IEM_INSTR_IMPL_A64__SSHR_asisdshf_R(Rd, Rn, o0, o1, immb, immh) /* SSRA D, D, # (ff80fc00/5f001400) */ //#define IEM_INSTR_IMPL_A64__SSRA_asisdshf_R(Rd, Rn, o0, o1, immb, immh) /* SRSHR D, D, # (ff80fc00/5f002400) */ //#define IEM_INSTR_IMPL_A64__SRSHR_asisdshf_R(Rd, Rn, o0, o1, immb, immh) /* SRSRA D, D, # (ff80fc00/5f003400) */ //#define IEM_INSTR_IMPL_A64__SRSRA_asisdshf_R(Rd, Rn, o0, o1, immb, immh) /* SHL D, D, # (ff80fc00/5f005400) */ //#define IEM_INSTR_IMPL_A64__SHL_asisdshf_R(Rd, Rn, immb, immh) /* SQSHL , , # (ff80fc00/5f007400) */ //#define IEM_INSTR_IMPL_A64__SQSHL_asisdshf_R(Rd, Rn, op, immb, immh) /* SQSHRN , , # (ff80fc00/5f009400) */ //#define IEM_INSTR_IMPL_A64__SQSHRN_asisdshf_N(Rd, Rn, op, immb, immh) /* SQRSHRN , , # (ff80fc00/5f009c00) */ //#define IEM_INSTR_IMPL_A64__SQRSHRN_asisdshf_N(Rd, Rn, op, immb, immh) /* SCVTF , , # (ff80fc00/5f00e400) */ //#define IEM_INSTR_IMPL_A64__SCVTF_asisdshf_C(Rd, Rn, immb, immh) /* FCVTZS , , # (ff80fc00/5f00fc00) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_asisdshf_C(Rd, Rn, immb, immh) /* USHR D, D, # (ff80fc00/7f000400) */ //#define IEM_INSTR_IMPL_A64__USHR_asisdshf_R(Rd, Rn, o0, o1, immb, immh) /* USRA D, D, # (ff80fc00/7f001400) */ //#define IEM_INSTR_IMPL_A64__USRA_asisdshf_R(Rd, Rn, o0, o1, immb, immh) /* URSHR D, D, # (ff80fc00/7f002400) */ //#define IEM_INSTR_IMPL_A64__URSHR_asisdshf_R(Rd, Rn, o0, o1, immb, immh) /* URSRA D, D, # (ff80fc00/7f003400) */ //#define IEM_INSTR_IMPL_A64__URSRA_asisdshf_R(Rd, Rn, o0, o1, immb, immh) /* SRI D, D, # (ff80fc00/7f004400) */ //#define IEM_INSTR_IMPL_A64__SRI_asisdshf_R(Rd, Rn, immb, immh) /* SLI D, D, # (ff80fc00/7f005400) */ //#define IEM_INSTR_IMPL_A64__SLI_asisdshf_R(Rd, Rn, immb, immh) /* SQSHLU , , # (ff80fc00/7f006400) */ //#define IEM_INSTR_IMPL_A64__SQSHLU_asisdshf_R(Rd, Rn, op, immb, immh) /* UQSHL , , # (ff80fc00/7f007400) */ //#define IEM_INSTR_IMPL_A64__UQSHL_asisdshf_R(Rd, Rn, op, immb, immh) /* SQSHRUN , , # (ff80fc00/7f008400) */ //#define IEM_INSTR_IMPL_A64__SQSHRUN_asisdshf_N(Rd, Rn, op, immb, immh) /* SQRSHRUN , , # (ff80fc00/7f008c00) */ //#define IEM_INSTR_IMPL_A64__SQRSHRUN_asisdshf_N(Rd, Rn, op, immb, immh) /* UQSHRN , , # (ff80fc00/7f009400) */ //#define IEM_INSTR_IMPL_A64__UQSHRN_asisdshf_N(Rd, Rn, op, immb, immh) /* UQRSHRN , , # (ff80fc00/7f009c00) */ //#define IEM_INSTR_IMPL_A64__UQRSHRN_asisdshf_N(Rd, Rn, op, immb, immh) /* UCVTF , , # (ff80fc00/7f00e400) */ //#define IEM_INSTR_IMPL_A64__UCVTF_asisdshf_C(Rd, Rn, immb, immh) /* FCVTZU , , # (ff80fc00/7f00fc00) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_asisdshf_C(Rd, Rn, immb, immh) /* * * Instruction Set & Groups: barriers / control / A64 * */ /* CLREX{ #} (fffff0ff/d503305f) */ //#define IEM_INSTR_IMPL_A64__CLREX_BN_barriers(CRm) /* DSB {
, , # (ffff0000/1e420000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_D32_float2fix(Rd, Rn, scale) /* UCVTF
, , # (ffff0000/1e430000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_D32_float2fix(Rd, Rn, scale) /* FCVTZS , , # (ffff0000/1e580000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_32D_float2fix(Rd, Rn, scale) /* FCVTZU , , # (ffff0000/1e590000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_32D_float2fix(Rd, Rn, scale) /* SCVTF , , # (ffff0000/1ec20000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_H32_float2fix(Rd, Rn, scale) /* UCVTF , , # (ffff0000/1ec30000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_H32_float2fix(Rd, Rn, scale) /* FCVTZS , , # (ffff0000/1ed80000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_32H_float2fix(Rd, Rn, scale) /* FCVTZU , , # (ffff0000/1ed90000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_32H_float2fix(Rd, Rn, scale) /* SCVTF , , # (ffff0000/9e020000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_S64_float2fix(Rd, Rn, scale) /* UCVTF , , # (ffff0000/9e030000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_S64_float2fix(Rd, Rn, scale) /* FCVTZS , , # (ffff0000/9e180000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_64S_float2fix(Rd, Rn, scale) /* FCVTZU , , # (ffff0000/9e190000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_64S_float2fix(Rd, Rn, scale) /* SCVTF
, , # (ffff0000/9e420000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_D64_float2fix(Rd, Rn, scale) /* UCVTF
, , # (ffff0000/9e430000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_D64_float2fix(Rd, Rn, scale) /* FCVTZS , , # (ffff0000/9e580000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_64D_float2fix(Rd, Rn, scale) /* FCVTZU , , # (ffff0000/9e590000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_64D_float2fix(Rd, Rn, scale) /* SCVTF , , # (ffff0000/9ec20000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_H64_float2fix(Rd, Rn, scale) /* UCVTF , , # (ffff0000/9ec30000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_H64_float2fix(Rd, Rn, scale) /* FCVTZS , , # (ffff0000/9ed80000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_64H_float2fix(Rd, Rn, scale) /* FCVTZU , , # (ffff0000/9ed90000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_64H_float2fix(Rd, Rn, scale) /* * * Instruction Set & Groups: float2int / simd_dp / A64 * */ /* FCVTNS , (fffffc00/1e200000) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_32S_float2int(Rd, Rn) /* FCVTNU , (fffffc00/1e210000) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_32S_float2int(Rd, Rn) /* SCVTF , (fffffc00/1e220000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_S32_float2int(Rd, Rn) /* UCVTF , (fffffc00/1e230000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_S32_float2int(Rd, Rn) /* FCVTAS , (fffffc00/1e240000) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_32S_float2int(Rd, Rn) /* FCVTAU , (fffffc00/1e250000) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_32S_float2int(Rd, Rn) /* FMOV , (fffffc00/1e260000) */ //#define IEM_INSTR_IMPL_A64__FMOV_32S_float2int(Rd, Rn) /* FMOV , (fffffc00/1e270000) */ //#define IEM_INSTR_IMPL_A64__FMOV_S32_float2int(Rd, Rn) /* FCVTPS , (fffffc00/1e280000) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_32S_float2int(Rd, Rn) /* FCVTPU , (fffffc00/1e290000) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_32S_float2int(Rd, Rn) /* FCVTMS , (fffffc00/1e300000) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_32S_float2int(Rd, Rn) /* FCVTMU , (fffffc00/1e310000) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_32S_float2int(Rd, Rn) /* FCVTZS , (fffffc00/1e380000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_32S_float2int(Rd, Rn) /* FCVTZU , (fffffc00/1e390000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_32S_float2int(Rd, Rn) /* FCVTNS , (fffffc00/1e600000) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_32D_float2int(Rd, Rn) /* FCVTNU , (fffffc00/1e610000) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_32D_float2int(Rd, Rn) /* SCVTF
, (fffffc00/1e620000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_D32_float2int(Rd, Rn) /* UCVTF
, (fffffc00/1e630000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_D32_float2int(Rd, Rn) /* FCVTAS , (fffffc00/1e640000) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_32D_float2int(Rd, Rn) /* FCVTAU , (fffffc00/1e650000) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_32D_float2int(Rd, Rn) /* FCVTPS , (fffffc00/1e680000) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_32D_float2int(Rd, Rn) /* FCVTPU , (fffffc00/1e690000) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_32D_float2int(Rd, Rn) /* FCVTMS , (fffffc00/1e700000) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_32D_float2int(Rd, Rn) /* FCVTMU , (fffffc00/1e710000) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_32D_float2int(Rd, Rn) /* FCVTZS , (fffffc00/1e780000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_32D_float2int(Rd, Rn) /* FCVTZU , (fffffc00/1e790000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_32D_float2int(Rd, Rn) /* FJCVTZS , (fffffc00/1e7e0000) */ //#define IEM_INSTR_IMPL_A64__FJCVTZS_32D_float2int(Rd, Rn) /* FCVTNS , (fffffc00/1ee00000) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_32H_float2int(Rd, Rn) /* FCVTNU , (fffffc00/1ee10000) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_32H_float2int(Rd, Rn) /* SCVTF , (fffffc00/1ee20000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_H32_float2int(Rd, Rn) /* UCVTF , (fffffc00/1ee30000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_H32_float2int(Rd, Rn) /* FCVTAS , (fffffc00/1ee40000) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_32H_float2int(Rd, Rn) /* FCVTAU , (fffffc00/1ee50000) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_32H_float2int(Rd, Rn) /* FMOV , (fffffc00/1ee60000) */ //#define IEM_INSTR_IMPL_A64__FMOV_32H_float2int(Rd, Rn) /* FMOV , (fffffc00/1ee70000) */ //#define IEM_INSTR_IMPL_A64__FMOV_H32_float2int(Rd, Rn) /* FCVTPS , (fffffc00/1ee80000) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_32H_float2int(Rd, Rn) /* FCVTPU , (fffffc00/1ee90000) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_32H_float2int(Rd, Rn) /* FCVTMS , (fffffc00/1ef00000) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_32H_float2int(Rd, Rn) /* FCVTMU , (fffffc00/1ef10000) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_32H_float2int(Rd, Rn) /* FCVTZS , (fffffc00/1ef80000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_32H_float2int(Rd, Rn) /* FCVTZU , (fffffc00/1ef90000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_32H_float2int(Rd, Rn) /* FCVTNS , (fffffc00/9e200000) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_64S_float2int(Rd, Rn) /* FCVTNU , (fffffc00/9e210000) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_64S_float2int(Rd, Rn) /* SCVTF , (fffffc00/9e220000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_S64_float2int(Rd, Rn) /* UCVTF , (fffffc00/9e230000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_S64_float2int(Rd, Rn) /* FCVTAS , (fffffc00/9e240000) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_64S_float2int(Rd, Rn) /* FCVTAU , (fffffc00/9e250000) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_64S_float2int(Rd, Rn) /* FCVTPS , (fffffc00/9e280000) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_64S_float2int(Rd, Rn) /* FCVTPU , (fffffc00/9e290000) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_64S_float2int(Rd, Rn) /* FCVTMS , (fffffc00/9e300000) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_64S_float2int(Rd, Rn) /* FCVTMU , (fffffc00/9e310000) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_64S_float2int(Rd, Rn) /* FCVTZS , (fffffc00/9e380000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_64S_float2int(Rd, Rn) /* FCVTZU , (fffffc00/9e390000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_64S_float2int(Rd, Rn) /* FCVTNS , (fffffc00/9e600000) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_64D_float2int(Rd, Rn) /* FCVTNU , (fffffc00/9e610000) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_64D_float2int(Rd, Rn) /* SCVTF
, (fffffc00/9e620000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_D64_float2int(Rd, Rn) /* UCVTF
, (fffffc00/9e630000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_D64_float2int(Rd, Rn) /* FCVTAS , (fffffc00/9e640000) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_64D_float2int(Rd, Rn) /* FCVTAU , (fffffc00/9e650000) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_64D_float2int(Rd, Rn) /* FMOV , (fffffc00/9e660000) */ //#define IEM_INSTR_IMPL_A64__FMOV_64D_float2int(Rd, Rn) /* FMOV
, (fffffc00/9e670000) */ //#define IEM_INSTR_IMPL_A64__FMOV_D64_float2int(Rd, Rn) /* FCVTPS , (fffffc00/9e680000) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_64D_float2int(Rd, Rn) /* FCVTPU , (fffffc00/9e690000) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_64D_float2int(Rd, Rn) /* FCVTMS , (fffffc00/9e700000) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_64D_float2int(Rd, Rn) /* FCVTMU , (fffffc00/9e710000) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_64D_float2int(Rd, Rn) /* FCVTZS , (fffffc00/9e780000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_64D_float2int(Rd, Rn) /* FCVTZU , (fffffc00/9e790000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_64D_float2int(Rd, Rn) /* FMOV , .D[1] (fffffc00/9eae0000) */ //#define IEM_INSTR_IMPL_A64__FMOV_64VX_float2int(Rd, Rn) /* FMOV .D[1], (fffffc00/9eaf0000) */ //#define IEM_INSTR_IMPL_A64__FMOV_V64I_float2int(Rd, Rn) /* FCVTNS , (fffffc00/9ee00000) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_64H_float2int(Rd, Rn) /* FCVTNU , (fffffc00/9ee10000) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_64H_float2int(Rd, Rn) /* SCVTF , (fffffc00/9ee20000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_H64_float2int(Rd, Rn) /* UCVTF , (fffffc00/9ee30000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_H64_float2int(Rd, Rn) /* FCVTAS , (fffffc00/9ee40000) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_64H_float2int(Rd, Rn) /* FCVTAU , (fffffc00/9ee50000) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_64H_float2int(Rd, Rn) /* FMOV , (fffffc00/9ee60000) */ //#define IEM_INSTR_IMPL_A64__FMOV_64H_float2int(Rd, Rn) /* FMOV , (fffffc00/9ee70000) */ //#define IEM_INSTR_IMPL_A64__FMOV_H64_float2int(Rd, Rn) /* FCVTPS , (fffffc00/9ee80000) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_64H_float2int(Rd, Rn) /* FCVTPU , (fffffc00/9ee90000) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_64H_float2int(Rd, Rn) /* FCVTMS , (fffffc00/9ef00000) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_64H_float2int(Rd, Rn) /* FCVTMU , (fffffc00/9ef10000) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_64H_float2int(Rd, Rn) /* FCVTZS , (fffffc00/9ef80000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_64H_float2int(Rd, Rn) /* FCVTZU , (fffffc00/9ef90000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_64H_float2int(Rd, Rn) /* FCVTNS , (fffffc00/1e6a0000) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_sisd_32D(Rd, Rn) /* FCVTAS , (fffffc00/1e7a0000) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_sisd_32D(Rd, Rn) /* FCVTPS , (fffffc00/1e720000) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_sisd_32D(Rd, Rn) /* FCVTMS , (fffffc00/1e740000) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_sisd_32D(Rd, Rn) /* FCVTZS , (fffffc00/1e760000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_sisd_32D(Rd, Rn) /* SCVTF
, (fffffc00/1e7c0000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_sisd_32D(Rd, Rn) /* FCVTNU , (fffffc00/1e6b0000) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_sisd_32D(Rd, Rn) /* FCVTAU , (fffffc00/1e7b0000) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_sisd_32D(Rd, Rn) /* FCVTPU , (fffffc00/1e730000) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_sisd_32D(Rd, Rn) /* FCVTMU , (fffffc00/1e750000) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_sisd_32D(Rd, Rn) /* FCVTZU , (fffffc00/1e770000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_sisd_32D(Rd, Rn) /* UCVTF
, (fffffc00/1e7d0000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_sisd_32D(Rd, Rn) /* FCVTNS , (fffffc00/1eea0000) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_sisd_32H(Rd, Rn) /* FCVTAS , (fffffc00/1efa0000) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_sisd_32H(Rd, Rn) /* FCVTPS , (fffffc00/1ef20000) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_sisd_32H(Rd, Rn) /* FCVTMS , (fffffc00/1ef40000) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_sisd_32H(Rd, Rn) /* FCVTZS , (fffffc00/1ef60000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_sisd_32H(Rd, Rn) /* SCVTF , (fffffc00/1efc0000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_sisd_32H(Rd, Rn) /* FCVTNU , (fffffc00/1eeb0000) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_sisd_32H(Rd, Rn) /* FCVTAU , (fffffc00/1efb0000) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_sisd_32H(Rd, Rn) /* FCVTPU , (fffffc00/1ef30000) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_sisd_32H(Rd, Rn) /* FCVTMU , (fffffc00/1ef50000) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_sisd_32H(Rd, Rn) /* FCVTZU , (fffffc00/1ef70000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_sisd_32H(Rd, Rn) /* UCVTF , (fffffc00/1efd0000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_sisd_32H(Rd, Rn) /* FCVTNS
, (fffffc00/9eea0000) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_sisd_64H(Rd, Rn) /* FCVTAS
, (fffffc00/9efa0000) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_sisd_64H(Rd, Rn) /* FCVTPS
, (fffffc00/9ef20000) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_sisd_64H(Rd, Rn) /* FCVTMS
, (fffffc00/9ef40000) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_sisd_64H(Rd, Rn) /* FCVTZS
, (fffffc00/9ef60000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_sisd_64H(Rd, Rn) /* SCVTF , (fffffc00/9efc0000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_sisd_64H(Rd, Rn) /* FCVTNU
, (fffffc00/9eeb0000) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_sisd_64H(Rd, Rn) /* FCVTAU
, (fffffc00/9efb0000) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_sisd_64H(Rd, Rn) /* FCVTPU
, (fffffc00/9ef30000) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_sisd_64H(Rd, Rn) /* FCVTMU
, (fffffc00/9ef50000) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_sisd_64H(Rd, Rn) /* FCVTZU
, (fffffc00/9ef70000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_sisd_64H(Rd, Rn) /* UCVTF , (fffffc00/9efd0000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_sisd_64H(Rd, Rn) /* FCVTNS
, (fffffc00/9e2a0000) */ //#define IEM_INSTR_IMPL_A64__FCVTNS_sisd_64S(Rd, Rn) /* FCVTAS
, (fffffc00/9e3a0000) */ //#define IEM_INSTR_IMPL_A64__FCVTAS_sisd_64S(Rd, Rn) /* FCVTPS
, (fffffc00/9e320000) */ //#define IEM_INSTR_IMPL_A64__FCVTPS_sisd_64S(Rd, Rn) /* FCVTMS
, (fffffc00/9e340000) */ //#define IEM_INSTR_IMPL_A64__FCVTMS_sisd_64S(Rd, Rn) /* FCVTZS
, (fffffc00/9e360000) */ //#define IEM_INSTR_IMPL_A64__FCVTZS_sisd_64S(Rd, Rn) /* SCVTF , (fffffc00/9e3c0000) */ //#define IEM_INSTR_IMPL_A64__SCVTF_sisd_64S(Rd, Rn) /* FCVTNU
, (fffffc00/9e2b0000) */ //#define IEM_INSTR_IMPL_A64__FCVTNU_sisd_64S(Rd, Rn) /* FCVTAU
, (fffffc00/9e3b0000) */ //#define IEM_INSTR_IMPL_A64__FCVTAU_sisd_64S(Rd, Rn) /* FCVTPU
, (fffffc00/9e330000) */ //#define IEM_INSTR_IMPL_A64__FCVTPU_sisd_64S(Rd, Rn) /* FCVTMU
, (fffffc00/9e350000) */ //#define IEM_INSTR_IMPL_A64__FCVTMU_sisd_64S(Rd, Rn) /* FCVTZU
, (fffffc00/9e370000) */ //#define IEM_INSTR_IMPL_A64__FCVTZU_sisd_64S(Rd, Rn) /* UCVTF , (fffffc00/9e3d0000) */ //#define IEM_INSTR_IMPL_A64__UCVTF_sisd_64S(Rd, Rn) /* * * Instruction Set & Groups: floatccmp / simd_dp / A64 * */ /* FCCMP , , #, (ffe00c10/1e200400) */ //#define IEM_INSTR_IMPL_A64__FCCMP_S_floatccmp(nzcv, Rn, cond, Rm) /* FCCMPE , , #, (ffe00c10/1e200410) */ //#define IEM_INSTR_IMPL_A64__FCCMPE_S_floatccmp(nzcv, Rn, cond, Rm) /* FCCMP , , #, (ffe00c10/1e600400) */ //#define IEM_INSTR_IMPL_A64__FCCMP_D_floatccmp(nzcv, Rn, cond, Rm) /* FCCMPE , , #, (ffe00c10/1e600410) */ //#define IEM_INSTR_IMPL_A64__FCCMPE_D_floatccmp(nzcv, Rn, cond, Rm) /* FCCMP , , #, (ffe00c10/1ee00400) */ //#define IEM_INSTR_IMPL_A64__FCCMP_H_floatccmp(nzcv, Rn, cond, Rm) /* FCCMPE , , #, (ffe00c10/1ee00410) */ //#define IEM_INSTR_IMPL_A64__FCCMPE_H_floatccmp(nzcv, Rn, cond, Rm) /* * * Instruction Set & Groups: floatcmp / simd_dp / A64 * */ /* FCMP , (ffe0fc1f/1e202000) */ //#define IEM_INSTR_IMPL_A64__FCMP_S_floatcmp(opc, Rn, Rm) /* FCMP , #0.0 (fffffc1f/1e202008) */ //#define IEM_INSTR_IMPL_A64__FCMP_SZ_floatcmp(opc, Rn) /* FCMPE , (ffe0fc1f/1e202010) */ //#define IEM_INSTR_IMPL_A64__FCMPE_S_floatcmp(opc, Rn, Rm) /* FCMPE , #0.0 (fffffc1f/1e202018) */ //#define IEM_INSTR_IMPL_A64__FCMPE_SZ_floatcmp(opc, Rn) /* FCMP , (ffe0fc1f/1e602000) */ //#define IEM_INSTR_IMPL_A64__FCMP_D_floatcmp(opc, Rn, Rm) /* FCMP , #0.0 (fffffc1f/1e602008) */ //#define IEM_INSTR_IMPL_A64__FCMP_DZ_floatcmp(opc, Rn) /* FCMPE , (ffe0fc1f/1e602010) */ //#define IEM_INSTR_IMPL_A64__FCMPE_D_floatcmp(opc, Rn, Rm) /* FCMPE , #0.0 (fffffc1f/1e602018) */ //#define IEM_INSTR_IMPL_A64__FCMPE_DZ_floatcmp(opc, Rn) /* FCMP , (ffe0fc1f/1ee02000) */ //#define IEM_INSTR_IMPL_A64__FCMP_H_floatcmp(opc, Rn, Rm) /* FCMP , #0.0 (fffffc1f/1ee02008) */ //#define IEM_INSTR_IMPL_A64__FCMP_HZ_floatcmp(opc, Rn) /* FCMPE , (ffe0fc1f/1ee02010) */ //#define IEM_INSTR_IMPL_A64__FCMPE_H_floatcmp(opc, Rn, Rm) /* FCMPE , #0.0 (fffffc1f/1ee02018) */ //#define IEM_INSTR_IMPL_A64__FCMPE_HZ_floatcmp(opc, Rn) /* * * Instruction Set & Groups: floatdp1 / simd_dp / A64 * */ /* FMOV , (fffffc00/1e204000) */ //#define IEM_INSTR_IMPL_A64__FMOV_S_floatdp1(Rd, Rn, opc) /* FABS , (fffffc00/1e20c000) */ //#define IEM_INSTR_IMPL_A64__FABS_S_floatdp1(Rd, Rn, opc) /* FNEG , (fffffc00/1e214000) */ //#define IEM_INSTR_IMPL_A64__FNEG_S_floatdp1(Rd, Rn, opc) /* FSQRT , (fffffc00/1e21c000) */ //#define IEM_INSTR_IMPL_A64__FSQRT_S_floatdp1(Rd, Rn, opc) /* FCVT
, (fffffc00/1e22c000) */ //#define IEM_INSTR_IMPL_A64__FCVT_DS_floatdp1(Rd, Rn, opc) /* FCVT , (fffffc00/1e23c000) */ //#define IEM_INSTR_IMPL_A64__FCVT_HS_floatdp1(Rd, Rn, opc) /* FRINTN , (fffffc00/1e244000) */ //#define IEM_INSTR_IMPL_A64__FRINTN_S_floatdp1(Rd, Rn, rmode) /* FRINTP , (fffffc00/1e24c000) */ //#define IEM_INSTR_IMPL_A64__FRINTP_S_floatdp1(Rd, Rn, rmode) /* FRINTM , (fffffc00/1e254000) */ //#define IEM_INSTR_IMPL_A64__FRINTM_S_floatdp1(Rd, Rn, rmode) /* FRINTZ , (fffffc00/1e25c000) */ //#define IEM_INSTR_IMPL_A64__FRINTZ_S_floatdp1(Rd, Rn, rmode) /* FRINTA , (fffffc00/1e264000) */ //#define IEM_INSTR_IMPL_A64__FRINTA_S_floatdp1(Rd, Rn, rmode) /* FRINTX , (fffffc00/1e274000) */ //#define IEM_INSTR_IMPL_A64__FRINTX_S_floatdp1(Rd, Rn, rmode) /* FRINTI , (fffffc00/1e27c000) */ //#define IEM_INSTR_IMPL_A64__FRINTI_S_floatdp1(Rd, Rn, rmode) /* FRINT32Z , (fffffc00/1e284000) */ //#define IEM_INSTR_IMPL_A64__FRINT32Z_S_floatdp1(Rd, Rn, op) /* FRINT32X , (fffffc00/1e28c000) */ //#define IEM_INSTR_IMPL_A64__FRINT32X_S_floatdp1(Rd, Rn, op) /* FRINT64Z , (fffffc00/1e294000) */ //#define IEM_INSTR_IMPL_A64__FRINT64Z_S_floatdp1(Rd, Rn, op) /* FRINT64X , (fffffc00/1e29c000) */ //#define IEM_INSTR_IMPL_A64__FRINT64X_S_floatdp1(Rd, Rn, op) /* FMOV
, (fffffc00/1e604000) */ //#define IEM_INSTR_IMPL_A64__FMOV_D_floatdp1(Rd, Rn, opc) /* FABS
, (fffffc00/1e60c000) */ //#define IEM_INSTR_IMPL_A64__FABS_D_floatdp1(Rd, Rn, opc) /* FNEG
, (fffffc00/1e614000) */ //#define IEM_INSTR_IMPL_A64__FNEG_D_floatdp1(Rd, Rn, opc) /* FSQRT
, (fffffc00/1e61c000) */ //#define IEM_INSTR_IMPL_A64__FSQRT_D_floatdp1(Rd, Rn, opc) /* FCVT , (fffffc00/1e624000) */ //#define IEM_INSTR_IMPL_A64__FCVT_SD_floatdp1(Rd, Rn, opc) /* BFCVT , (fffffc00/1e634000) */ //#define IEM_INSTR_IMPL_A64__BFCVT_BS_floatdp1(Rd, Rn) /* FCVT , (fffffc00/1e63c000) */ //#define IEM_INSTR_IMPL_A64__FCVT_HD_floatdp1(Rd, Rn, opc) /* FRINTN
, (fffffc00/1e644000) */ //#define IEM_INSTR_IMPL_A64__FRINTN_D_floatdp1(Rd, Rn, rmode) /* FRINTP
, (fffffc00/1e64c000) */ //#define IEM_INSTR_IMPL_A64__FRINTP_D_floatdp1(Rd, Rn, rmode) /* FRINTM
, (fffffc00/1e654000) */ //#define IEM_INSTR_IMPL_A64__FRINTM_D_floatdp1(Rd, Rn, rmode) /* FRINTZ
, (fffffc00/1e65c000) */ //#define IEM_INSTR_IMPL_A64__FRINTZ_D_floatdp1(Rd, Rn, rmode) /* FRINTA
, (fffffc00/1e664000) */ //#define IEM_INSTR_IMPL_A64__FRINTA_D_floatdp1(Rd, Rn, rmode) /* FRINTX
, (fffffc00/1e674000) */ //#define IEM_INSTR_IMPL_A64__FRINTX_D_floatdp1(Rd, Rn, rmode) /* FRINTI
, (fffffc00/1e67c000) */ //#define IEM_INSTR_IMPL_A64__FRINTI_D_floatdp1(Rd, Rn, rmode) /* FRINT32Z
, (fffffc00/1e684000) */ //#define IEM_INSTR_IMPL_A64__FRINT32Z_D_floatdp1(Rd, Rn, op) /* FRINT32X
, (fffffc00/1e68c000) */ //#define IEM_INSTR_IMPL_A64__FRINT32X_D_floatdp1(Rd, Rn, op) /* FRINT64Z
, (fffffc00/1e694000) */ //#define IEM_INSTR_IMPL_A64__FRINT64Z_D_floatdp1(Rd, Rn, op) /* FRINT64X
, (fffffc00/1e69c000) */ //#define IEM_INSTR_IMPL_A64__FRINT64X_D_floatdp1(Rd, Rn, op) /* FMOV , (fffffc00/1ee04000) */ //#define IEM_INSTR_IMPL_A64__FMOV_H_floatdp1(Rd, Rn, opc) /* FABS , (fffffc00/1ee0c000) */ //#define IEM_INSTR_IMPL_A64__FABS_H_floatdp1(Rd, Rn, opc) /* FNEG , (fffffc00/1ee14000) */ //#define IEM_INSTR_IMPL_A64__FNEG_H_floatdp1(Rd, Rn, opc) /* FSQRT , (fffffc00/1ee1c000) */ //#define IEM_INSTR_IMPL_A64__FSQRT_H_floatdp1(Rd, Rn, opc) /* FCVT , (fffffc00/1ee24000) */ //#define IEM_INSTR_IMPL_A64__FCVT_SH_floatdp1(Rd, Rn, opc) /* FCVT
, (fffffc00/1ee2c000) */ //#define IEM_INSTR_IMPL_A64__FCVT_DH_floatdp1(Rd, Rn, opc) /* FRINTN , (fffffc00/1ee44000) */ //#define IEM_INSTR_IMPL_A64__FRINTN_H_floatdp1(Rd, Rn, rmode) /* FRINTP , (fffffc00/1ee4c000) */ //#define IEM_INSTR_IMPL_A64__FRINTP_H_floatdp1(Rd, Rn, rmode) /* FRINTM , (fffffc00/1ee54000) */ //#define IEM_INSTR_IMPL_A64__FRINTM_H_floatdp1(Rd, Rn, rmode) /* FRINTZ , (fffffc00/1ee5c000) */ //#define IEM_INSTR_IMPL_A64__FRINTZ_H_floatdp1(Rd, Rn, rmode) /* FRINTA , (fffffc00/1ee64000) */ //#define IEM_INSTR_IMPL_A64__FRINTA_H_floatdp1(Rd, Rn, rmode) /* FRINTX , (fffffc00/1ee74000) */ //#define IEM_INSTR_IMPL_A64__FRINTX_H_floatdp1(Rd, Rn, rmode) /* FRINTI , (fffffc00/1ee7c000) */ //#define IEM_INSTR_IMPL_A64__FRINTI_H_floatdp1(Rd, Rn, rmode) /* * * Instruction Set & Groups: floatdp2 / simd_dp / A64 * */ /* FMUL , , (ffe0fc00/1e200800) */ //#define IEM_INSTR_IMPL_A64__FMUL_S_floatdp2(Rd, Rn, op, Rm) /* FDIV , , (ffe0fc00/1e201800) */ //#define IEM_INSTR_IMPL_A64__FDIV_S_floatdp2(Rd, Rn, Rm) /* FADD , , (ffe0fc00/1e202800) */ //#define IEM_INSTR_IMPL_A64__FADD_S_floatdp2(Rd, Rn, op, Rm) /* FSUB , , (ffe0fc00/1e203800) */ //#define IEM_INSTR_IMPL_A64__FSUB_S_floatdp2(Rd, Rn, op, Rm) /* FMAX , , (ffe0fc00/1e204800) */ //#define IEM_INSTR_IMPL_A64__FMAX_S_floatdp2(Rd, Rn, op, Rm) /* FMIN , , (ffe0fc00/1e205800) */ //#define IEM_INSTR_IMPL_A64__FMIN_S_floatdp2(Rd, Rn, op, Rm) /* FMAXNM , , (ffe0fc00/1e206800) */ //#define IEM_INSTR_IMPL_A64__FMAXNM_S_floatdp2(Rd, Rn, op, Rm) /* FMINNM , , (ffe0fc00/1e207800) */ //#define IEM_INSTR_IMPL_A64__FMINNM_S_floatdp2(Rd, Rn, op, Rm) /* FNMUL , , (ffe0fc00/1e208800) */ //#define IEM_INSTR_IMPL_A64__FNMUL_S_floatdp2(Rd, Rn, op, Rm) /* FMUL
, , (ffe0fc00/1e600800) */ //#define IEM_INSTR_IMPL_A64__FMUL_D_floatdp2(Rd, Rn, op, Rm) /* FDIV
, , (ffe0fc00/1e601800) */ //#define IEM_INSTR_IMPL_A64__FDIV_D_floatdp2(Rd, Rn, Rm) /* FADD
, , (ffe0fc00/1e602800) */ //#define IEM_INSTR_IMPL_A64__FADD_D_floatdp2(Rd, Rn, op, Rm) /* FSUB
, , (ffe0fc00/1e603800) */ //#define IEM_INSTR_IMPL_A64__FSUB_D_floatdp2(Rd, Rn, op, Rm) /* FMAX
, , (ffe0fc00/1e604800) */ //#define IEM_INSTR_IMPL_A64__FMAX_D_floatdp2(Rd, Rn, op, Rm) /* FMIN
, , (ffe0fc00/1e605800) */ //#define IEM_INSTR_IMPL_A64__FMIN_D_floatdp2(Rd, Rn, op, Rm) /* FMAXNM
, , (ffe0fc00/1e606800) */ //#define IEM_INSTR_IMPL_A64__FMAXNM_D_floatdp2(Rd, Rn, op, Rm) /* FMINNM
, , (ffe0fc00/1e607800) */ //#define IEM_INSTR_IMPL_A64__FMINNM_D_floatdp2(Rd, Rn, op, Rm) /* FNMUL
, , (ffe0fc00/1e608800) */ //#define IEM_INSTR_IMPL_A64__FNMUL_D_floatdp2(Rd, Rn, op, Rm) /* FMUL , , (ffe0fc00/1ee00800) */ //#define IEM_INSTR_IMPL_A64__FMUL_H_floatdp2(Rd, Rn, op, Rm) /* FDIV , , (ffe0fc00/1ee01800) */ //#define IEM_INSTR_IMPL_A64__FDIV_H_floatdp2(Rd, Rn, Rm) /* FADD , , (ffe0fc00/1ee02800) */ //#define IEM_INSTR_IMPL_A64__FADD_H_floatdp2(Rd, Rn, op, Rm) /* FSUB , , (ffe0fc00/1ee03800) */ //#define IEM_INSTR_IMPL_A64__FSUB_H_floatdp2(Rd, Rn, op, Rm) /* FMAX , , (ffe0fc00/1ee04800) */ //#define IEM_INSTR_IMPL_A64__FMAX_H_floatdp2(Rd, Rn, op, Rm) /* FMIN , , (ffe0fc00/1ee05800) */ //#define IEM_INSTR_IMPL_A64__FMIN_H_floatdp2(Rd, Rn, op, Rm) /* FMAXNM , , (ffe0fc00/1ee06800) */ //#define IEM_INSTR_IMPL_A64__FMAXNM_H_floatdp2(Rd, Rn, op, Rm) /* FMINNM , , (ffe0fc00/1ee07800) */ //#define IEM_INSTR_IMPL_A64__FMINNM_H_floatdp2(Rd, Rn, op, Rm) /* FNMUL , , (ffe0fc00/1ee08800) */ //#define IEM_INSTR_IMPL_A64__FNMUL_H_floatdp2(Rd, Rn, op, Rm) /* * * Instruction Set & Groups: floatdp3 / simd_dp / A64 * */ /* FMADD , , , (ffe08000/1f000000) */ //#define IEM_INSTR_IMPL_A64__FMADD_S_floatdp3(Rd, Rn, Ra, Rm) /* FMSUB , , , (ffe08000/1f008000) */ //#define IEM_INSTR_IMPL_A64__FMSUB_S_floatdp3(Rd, Rn, Ra, Rm) /* FNMADD , , , (ffe08000/1f200000) */ //#define IEM_INSTR_IMPL_A64__FNMADD_S_floatdp3(Rd, Rn, Ra, Rm) /* FNMSUB , , , (ffe08000/1f208000) */ //#define IEM_INSTR_IMPL_A64__FNMSUB_S_floatdp3(Rd, Rn, Ra, Rm) /* FMADD
, , , (ffe08000/1f400000) */ //#define IEM_INSTR_IMPL_A64__FMADD_D_floatdp3(Rd, Rn, Ra, Rm) /* FMSUB
, , , (ffe08000/1f408000) */ //#define IEM_INSTR_IMPL_A64__FMSUB_D_floatdp3(Rd, Rn, Ra, Rm) /* FNMADD
, , , (ffe08000/1f600000) */ //#define IEM_INSTR_IMPL_A64__FNMADD_D_floatdp3(Rd, Rn, Ra, Rm) /* FNMSUB
, , , (ffe08000/1f608000) */ //#define IEM_INSTR_IMPL_A64__FNMSUB_D_floatdp3(Rd, Rn, Ra, Rm) /* FMADD , , , (ffe08000/1fc00000) */ //#define IEM_INSTR_IMPL_A64__FMADD_H_floatdp3(Rd, Rn, Ra, Rm) /* FMSUB , , , (ffe08000/1fc08000) */ //#define IEM_INSTR_IMPL_A64__FMSUB_H_floatdp3(Rd, Rn, Ra, Rm) /* FNMADD , , , (ffe08000/1fe00000) */ //#define IEM_INSTR_IMPL_A64__FNMADD_H_floatdp3(Rd, Rn, Ra, Rm) /* FNMSUB , , , (ffe08000/1fe08000) */ //#define IEM_INSTR_IMPL_A64__FNMSUB_H_floatdp3(Rd, Rn, Ra, Rm) /* * * Instruction Set & Groups: floatimm / simd_dp / A64 * */ /* FMOV , # (ffe01fe0/1e201000) */ //#define IEM_INSTR_IMPL_A64__FMOV_S_floatimm(Rd, imm8) /* FMOV
, # (ffe01fe0/1e601000) */ //#define IEM_INSTR_IMPL_A64__FMOV_D_floatimm(Rd, imm8) /* FMOV , # (ffe01fe0/1ee01000) */ //#define IEM_INSTR_IMPL_A64__FMOV_H_floatimm(Rd, imm8) /* * * Instruction Set & Groups: floatsel / simd_dp / A64 * */ /* FCSEL , , , (ffe00c00/1e200c00) */ //#define IEM_INSTR_IMPL_A64__FCSEL_S_floatsel(Rd, Rn, cond, Rm) /* FCSEL
, , , (ffe00c00/1e600c00) */ //#define IEM_INSTR_IMPL_A64__FCSEL_D_floatsel(Rd, Rn, cond, Rm) /* FCSEL , , , (ffe00c00/1ee00c00) */ //#define IEM_INSTR_IMPL_A64__FCSEL_H_floatsel(Rd, Rn, cond, Rm) /* * * Instruction Set & Groups: hints / control / A64 * */ /* HINT # (fffff01f/d503201f) */ //#define IEM_INSTR_IMPL_A64__HINT_HM_hints(op2, CRm) /* NOP (ffffffff/d503201f) */ //#define IEM_INSTR_IMPL_A64__NOP_HI_hints() /* YIELD (ffffffff/d503203f) */ //#define IEM_INSTR_IMPL_A64__YIELD_HI_hints() /* WFE (ffffffff/d503205f) */ //#define IEM_INSTR_IMPL_A64__WFE_HI_hints() /* WFI (ffffffff/d503207f) */ //#define IEM_INSTR_IMPL_A64__WFI_HI_hints() /* SEV (ffffffff/d503209f) */ //#define IEM_INSTR_IMPL_A64__SEV_HI_hints() /* SEVL (ffffffff/d50320bf) */ //#define IEM_INSTR_IMPL_A64__SEVL_HI_hints() /* DGH (ffffffff/d50320df) */ //#define IEM_INSTR_IMPL_A64__DGH_HI_hints() /* XPACLRI (ffffffff/d50320ff) */ //#define IEM_INSTR_IMPL_A64__XPACLRI_HI_hints() /* PACIA1716 (ffffffff/d503211f) */ //#define IEM_INSTR_IMPL_A64__PACIA1716_HI_hints() /* PACIB1716 (ffffffff/d503215f) */ //#define IEM_INSTR_IMPL_A64__PACIB1716_HI_hints() /* AUTIA1716 (ffffffff/d503219f) */ //#define IEM_INSTR_IMPL_A64__AUTIA1716_HI_hints() /* AUTIB1716 (ffffffff/d50321df) */ //#define IEM_INSTR_IMPL_A64__AUTIB1716_HI_hints() /* ESB (ffffffff/d503221f) */ //#define IEM_INSTR_IMPL_A64__ESB_HI_hints() /* PSB CSYNC (ffffffff/d503223f) */ //#define IEM_INSTR_IMPL_A64__PSB_HC_hints() /* TSB CSYNC (ffffffff/d503225f) */ //#define IEM_INSTR_IMPL_A64__TSB_HC_hints() /* GCSB DSYNC (ffffffff/d503227f) */ //#define IEM_INSTR_IMPL_A64__GCSB_HD_hints() /* CSDB (ffffffff/d503229f) */ //#define IEM_INSTR_IMPL_A64__CSDB_HI_hints() /* CLRBHB (ffffffff/d50322df) */ //#define IEM_INSTR_IMPL_A64__CLRBHB_HI_hints() /* PACIAZ (ffffffff/d503231f) */ //#define IEM_INSTR_IMPL_A64__PACIAZ_HI_hints() /* PACIASP (ffffffff/d503233f) */ //#define IEM_INSTR_IMPL_A64__PACIASP_HI_hints() /* PACIBZ (ffffffff/d503235f) */ //#define IEM_INSTR_IMPL_A64__PACIBZ_HI_hints() /* PACIBSP (ffffffff/d503237f) */ //#define IEM_INSTR_IMPL_A64__PACIBSP_HI_hints() /* AUTIAZ (ffffffff/d503239f) */ //#define IEM_INSTR_IMPL_A64__AUTIAZ_HI_hints() /* AUTIASP (ffffffff/d50323bf) */ //#define IEM_INSTR_IMPL_A64__AUTIASP_HI_hints() /* AUTIBZ (ffffffff/d50323df) */ //#define IEM_INSTR_IMPL_A64__AUTIBZ_HI_hints() /* AUTIBSP (ffffffff/d50323ff) */ //#define IEM_INSTR_IMPL_A64__AUTIBSP_HI_hints() /* BTI{ } (ffffff1f/d503241f) */ //#define IEM_INSTR_IMPL_A64__BTI_HB_hints(op2) /* PACM (ffffffff/d50324ff) */ //#define IEM_INSTR_IMPL_A64__PACM_HI_hints() /* CHKFEAT X16 (ffffffff/d503251f) */ //#define IEM_INSTR_IMPL_A64__CHKFEAT_HF_hints() /* STSHH (ffffff1f/d503261f) */ //#define IEM_INSTR_IMPL_A64__STSHH_HI_hints(op2) /* * * Instruction Set & Groups: ldapstl_simd / ldst / A64 * */ /* STLUR , [{, #}] (ffe00c00/1d000800) */ //#define IEM_INSTR_IMPL_A64__STLUR_B_ldapstl_simd(Rt, Rn, imm9) /* LDAPUR , [{, #}] (ffe00c00/1d400800) */ //#define IEM_INSTR_IMPL_A64__LDAPUR_B_ldapstl_simd(Rt, Rn, imm9) /* STLUR , [{, #}] (ffe00c00/1d800800) */ //#define IEM_INSTR_IMPL_A64__STLUR_Q_ldapstl_simd(Rt, Rn, imm9) /* LDAPUR , [{, #}] (ffe00c00/1dc00800) */ //#define IEM_INSTR_IMPL_A64__LDAPUR_Q_ldapstl_simd(Rt, Rn, imm9) /* STLUR , [{, #}] (ffe00c00/5d000800) */ //#define IEM_INSTR_IMPL_A64__STLUR_H_ldapstl_simd(Rt, Rn, imm9) /* LDAPUR , [{, #}] (ffe00c00/5d400800) */ //#define IEM_INSTR_IMPL_A64__LDAPUR_H_ldapstl_simd(Rt, Rn, imm9) /* STLUR , [{, #}] (ffe00c00/9d000800) */ //#define IEM_INSTR_IMPL_A64__STLUR_S_ldapstl_simd(Rt, Rn, imm9) /* LDAPUR , [{, #}] (ffe00c00/9d400800) */ //#define IEM_INSTR_IMPL_A64__LDAPUR_S_ldapstl_simd(Rt, Rn, imm9) /* STLUR
, [{, #}] (ffe00c00/dd000800) */ //#define IEM_INSTR_IMPL_A64__STLUR_D_ldapstl_simd(Rt, Rn, imm9) /* LDAPUR
, [{, #}] (ffe00c00/dd400800) */ //#define IEM_INSTR_IMPL_A64__LDAPUR_D_ldapstl_simd(Rt, Rn, imm9) /* * * Instruction Set & Groups: ldapstl_unscaled / ldst / A64 * */ /* STLURB , [{, #}] (ffe00c00/19000000) */ //#define IEM_INSTR_IMPL_A64__STLURB_32_ldapstl_unscaled(Rt, Rn, imm9) /* LDAPURB , [{, #}] (ffe00c00/19400000) */ //#define IEM_INSTR_IMPL_A64__LDAPURB_32_ldapstl_unscaled(Rt, Rn, imm9) /* LDAPURSB , [{, #}] (ffe00c00/19800000) */ //#define IEM_INSTR_IMPL_A64__LDAPURSB_64_ldapstl_unscaled(Rt, Rn, imm9) /* LDAPURSB , [{, #}] (ffe00c00/19c00000) */ //#define IEM_INSTR_IMPL_A64__LDAPURSB_32_ldapstl_unscaled(Rt, Rn, imm9) /* STLURH , [{, #}] (ffe00c00/59000000) */ //#define IEM_INSTR_IMPL_A64__STLURH_32_ldapstl_unscaled(Rt, Rn, imm9) /* LDAPURH , [{, #}] (ffe00c00/59400000) */ //#define IEM_INSTR_IMPL_A64__LDAPURH_32_ldapstl_unscaled(Rt, Rn, imm9) /* LDAPURSH , [{, #}] (ffe00c00/59800000) */ //#define IEM_INSTR_IMPL_A64__LDAPURSH_64_ldapstl_unscaled(Rt, Rn, imm9) /* LDAPURSH , [{, #}] (ffe00c00/59c00000) */ //#define IEM_INSTR_IMPL_A64__LDAPURSH_32_ldapstl_unscaled(Rt, Rn, imm9) /* STLUR , [{, #}] (ffe00c00/99000000) */ //#define IEM_INSTR_IMPL_A64__STLUR_32_ldapstl_unscaled(Rt, Rn, imm9) /* LDAPUR , [{, #}] (ffe00c00/99400000) */ //#define IEM_INSTR_IMPL_A64__LDAPUR_32_ldapstl_unscaled(Rt, Rn, imm9) /* LDAPURSW , [{, #}] (ffe00c00/99800000) */ //#define IEM_INSTR_IMPL_A64__LDAPURSW_64_ldapstl_unscaled(Rt, Rn, imm9) /* STLUR , [{, #}] (ffe00c00/d9000000) */ //#define IEM_INSTR_IMPL_A64__STLUR_64_ldapstl_unscaled(Rt, Rn, imm9) /* LDAPUR , [{, #}] (ffe00c00/d9400000) */ //#define IEM_INSTR_IMPL_A64__LDAPUR_64_ldapstl_unscaled(Rt, Rn, imm9) /* * * Instruction Set & Groups: ldapstl_writeback / ldst / A64 * */ /* STLR , [, #-4]! (fffffc00/99800800) */ //#define IEM_INSTR_IMPL_A64__STLR_32S_ldapstl_writeback(Rt, Rn) /* LDAPR , [], #4 (fffffc00/99c00800) */ //#define IEM_INSTR_IMPL_A64__LDAPR_32L_ldapstl_writeback(Rt, Rn) /* STLR , [, #-8]! (fffffc00/d9800800) */ //#define IEM_INSTR_IMPL_A64__STLR_64S_ldapstl_writeback(Rt, Rn) /* LDAPR , [], #8 (fffffc00/d9c00800) */ //#define IEM_INSTR_IMPL_A64__LDAPR_64L_ldapstl_writeback(Rt, Rn) /* * * Instruction Set & Groups: ldiappstilp / ldst / A64 * */ /* STILP , , [, #-8]! (ffe0fc00/99000800) */ //#define IEM_INSTR_IMPL_A64__STILP_32SE_ldiappstilp(Rt, Rn, Rt2) /* STILP , , [] (ffe0fc00/99001800) */ //#define IEM_INSTR_IMPL_A64__STILP_32S_ldiappstilp(Rt, Rn, Rt2) /* LDIAPP , , [], #8 (ffe0fc00/99400800) */ //#define IEM_INSTR_IMPL_A64__LDIAPP_32LE_ldiappstilp(Rt, Rn, Rt2) /* LDIAPP , , [] (ffe0fc00/99401800) */ //#define IEM_INSTR_IMPL_A64__LDIAPP_32L_ldiappstilp(Rt, Rn, Rt2) /* STILP , , [, #-16]! (ffe0fc00/d9000800) */ //#define IEM_INSTR_IMPL_A64__STILP_64SS_ldiappstilp(Rt, Rn, Rt2) /* STILP , , [] (ffe0fc00/d9001800) */ //#define IEM_INSTR_IMPL_A64__STILP_64S_ldiappstilp(Rt, Rn, Rt2) /* LDIAPP , , [], #16 (ffe0fc00/d9400800) */ //#define IEM_INSTR_IMPL_A64__LDIAPP_64LS_ldiappstilp(Rt, Rn, Rt2) /* LDIAPP , , [] (ffe0fc00/d9401800) */ //#define IEM_INSTR_IMPL_A64__LDIAPP_64L_ldiappstilp(Rt, Rn, Rt2) /* * * Instruction Set & Groups: ldst_gcs / ldst / A64 * */ /* GCSSTR , [] (fffffc00/d91f0c00) */ //#define IEM_INSTR_IMPL_A64__GCSSTR_64_ldst_gcs(Rt, Rn) /* GCSSTTR , [] (fffffc00/d91f1c00) */ //#define IEM_INSTR_IMPL_A64__GCSSTTR_64_ldst_gcs(Rt, Rn) /* * * Instruction Set & Groups: ldst_immpost / ldst / A64 * */ /* STRB , [], # (ffe00c00/38000400) */ //#define IEM_INSTR_IMPL_A64__STRB_32_ldst_immpost(Rt, Rn, imm9) /* LDRB , [], # (ffe00c00/38400400) */ //#define IEM_INSTR_IMPL_A64__LDRB_32_ldst_immpost(Rt, Rn, imm9) /* LDRSB , [], # (ffe00c00/38800400) */ //#define IEM_INSTR_IMPL_A64__LDRSB_64_ldst_immpost(Rt, Rn, imm9) /* LDRSB , [], # (ffe00c00/38c00400) */ //#define IEM_INSTR_IMPL_A64__LDRSB_32_ldst_immpost(Rt, Rn, imm9) /* STR , [], # (ffe00c00/3c000400) */ //#define IEM_INSTR_IMPL_A64__STR_B_ldst_immpost(Rt, Rn, imm9) /* LDR , [], # (ffe00c00/3c400400) */ //#define IEM_INSTR_IMPL_A64__LDR_B_ldst_immpost(Rt, Rn, imm9) /* STR , [], # (ffe00c00/3c800400) */ //#define IEM_INSTR_IMPL_A64__STR_Q_ldst_immpost(Rt, Rn, imm9) /* LDR , [], # (ffe00c00/3cc00400) */ //#define IEM_INSTR_IMPL_A64__LDR_Q_ldst_immpost(Rt, Rn, imm9) /* STRH , [], # (ffe00c00/78000400) */ //#define IEM_INSTR_IMPL_A64__STRH_32_ldst_immpost(Rt, Rn, imm9) /* LDRH , [], # (ffe00c00/78400400) */ //#define IEM_INSTR_IMPL_A64__LDRH_32_ldst_immpost(Rt, Rn, imm9) /* LDRSH , [], # (ffe00c00/78800400) */ //#define IEM_INSTR_IMPL_A64__LDRSH_64_ldst_immpost(Rt, Rn, imm9) /* LDRSH , [], # (ffe00c00/78c00400) */ //#define IEM_INSTR_IMPL_A64__LDRSH_32_ldst_immpost(Rt, Rn, imm9) /* STR , [], # (ffe00c00/7c000400) */ //#define IEM_INSTR_IMPL_A64__STR_H_ldst_immpost(Rt, Rn, imm9) /* LDR , [], # (ffe00c00/7c400400) */ //#define IEM_INSTR_IMPL_A64__LDR_H_ldst_immpost(Rt, Rn, imm9) /* STR , [], # (ffe00c00/b8000400) */ //#define IEM_INSTR_IMPL_A64__STR_32_ldst_immpost(Rt, Rn, imm9) /* LDR , [], # (ffe00c00/b8400400) */ //#define IEM_INSTR_IMPL_A64__LDR_32_ldst_immpost(Rt, Rn, imm9) /* LDRSW , [], # (ffe00c00/b8800400) */ //#define IEM_INSTR_IMPL_A64__LDRSW_64_ldst_immpost(Rt, Rn, imm9) /* STR , [], # (ffe00c00/bc000400) */ //#define IEM_INSTR_IMPL_A64__STR_S_ldst_immpost(Rt, Rn, imm9) /* LDR , [], # (ffe00c00/bc400400) */ //#define IEM_INSTR_IMPL_A64__LDR_S_ldst_immpost(Rt, Rn, imm9) /* STR , [], # (ffe00c00/f8000400) */ //#define IEM_INSTR_IMPL_A64__STR_64_ldst_immpost(Rt, Rn, imm9) /* LDR , [], # (ffe00c00/f8400400) */ //#define IEM_INSTR_IMPL_A64__LDR_64_ldst_immpost(Rt, Rn, imm9) /* STR
, [], # (ffe00c00/fc000400) */ //#define IEM_INSTR_IMPL_A64__STR_D_ldst_immpost(Rt, Rn, imm9) /* LDR
, [], # (ffe00c00/fc400400) */ //#define IEM_INSTR_IMPL_A64__LDR_D_ldst_immpost(Rt, Rn, imm9) /* * * Instruction Set & Groups: ldst_immpre / ldst / A64 * */ /* STRB , [, #]! (ffe00c00/38000c00) */ //#define IEM_INSTR_IMPL_A64__STRB_32_ldst_immpre(Rt, Rn, imm9) /* LDRB , [, #]! (ffe00c00/38400c00) */ //#define IEM_INSTR_IMPL_A64__LDRB_32_ldst_immpre(Rt, Rn, imm9) /* LDRSB , [, #]! (ffe00c00/38800c00) */ //#define IEM_INSTR_IMPL_A64__LDRSB_64_ldst_immpre(Rt, Rn, imm9) /* LDRSB , [, #]! (ffe00c00/38c00c00) */ //#define IEM_INSTR_IMPL_A64__LDRSB_32_ldst_immpre(Rt, Rn, imm9) /* STR , [, #]! (ffe00c00/3c000c00) */ //#define IEM_INSTR_IMPL_A64__STR_B_ldst_immpre(Rt, Rn, imm9) /* LDR , [, #]! (ffe00c00/3c400c00) */ //#define IEM_INSTR_IMPL_A64__LDR_B_ldst_immpre(Rt, Rn, imm9) /* STR , [, #]! (ffe00c00/3c800c00) */ //#define IEM_INSTR_IMPL_A64__STR_Q_ldst_immpre(Rt, Rn, imm9) /* LDR , [, #]! (ffe00c00/3cc00c00) */ //#define IEM_INSTR_IMPL_A64__LDR_Q_ldst_immpre(Rt, Rn, imm9) /* STRH , [, #]! (ffe00c00/78000c00) */ //#define IEM_INSTR_IMPL_A64__STRH_32_ldst_immpre(Rt, Rn, imm9) /* LDRH , [, #]! (ffe00c00/78400c00) */ //#define IEM_INSTR_IMPL_A64__LDRH_32_ldst_immpre(Rt, Rn, imm9) /* LDRSH , [, #]! (ffe00c00/78800c00) */ //#define IEM_INSTR_IMPL_A64__LDRSH_64_ldst_immpre(Rt, Rn, imm9) /* LDRSH , [, #]! (ffe00c00/78c00c00) */ //#define IEM_INSTR_IMPL_A64__LDRSH_32_ldst_immpre(Rt, Rn, imm9) /* STR , [, #]! (ffe00c00/7c000c00) */ //#define IEM_INSTR_IMPL_A64__STR_H_ldst_immpre(Rt, Rn, imm9) /* LDR , [, #]! (ffe00c00/7c400c00) */ //#define IEM_INSTR_IMPL_A64__LDR_H_ldst_immpre(Rt, Rn, imm9) /* STR , [, #]! (ffe00c00/b8000c00) */ //#define IEM_INSTR_IMPL_A64__STR_32_ldst_immpre(Rt, Rn, imm9) /* LDR , [, #]! (ffe00c00/b8400c00) */ //#define IEM_INSTR_IMPL_A64__LDR_32_ldst_immpre(Rt, Rn, imm9) /* LDRSW , [, #]! (ffe00c00/b8800c00) */ //#define IEM_INSTR_IMPL_A64__LDRSW_64_ldst_immpre(Rt, Rn, imm9) /* STR , [, #]! (ffe00c00/bc000c00) */ //#define IEM_INSTR_IMPL_A64__STR_S_ldst_immpre(Rt, Rn, imm9) /* LDR , [, #]! (ffe00c00/bc400c00) */ //#define IEM_INSTR_IMPL_A64__LDR_S_ldst_immpre(Rt, Rn, imm9) /* STR , [, #]! (ffe00c00/f8000c00) */ //#define IEM_INSTR_IMPL_A64__STR_64_ldst_immpre(Rt, Rn, imm9) /* LDR , [, #]! (ffe00c00/f8400c00) */ //#define IEM_INSTR_IMPL_A64__LDR_64_ldst_immpre(Rt, Rn, imm9) /* STR
, [, #]! (ffe00c00/fc000c00) */ //#define IEM_INSTR_IMPL_A64__STR_D_ldst_immpre(Rt, Rn, imm9) /* LDR
, [, #]! (ffe00c00/fc400c00) */ //#define IEM_INSTR_IMPL_A64__LDR_D_ldst_immpre(Rt, Rn, imm9) /* * * Instruction Set & Groups: ldst_pac / ldst / A64 * */ /* LDRAA , [{, #}] (ffa00c00/f8200400) */ //#define IEM_INSTR_IMPL_A64__LDRAA_64_ldst_pac(Rt, Rn, imm9, S) /* LDRAA , [{, #}]! (ffa00c00/f8200c00) */ //#define IEM_INSTR_IMPL_A64__LDRAA_64W_ldst_pac(Rt, Rn, imm9, S) /* LDRAB , [{, #}] (ffa00c00/f8a00400) */ //#define IEM_INSTR_IMPL_A64__LDRAB_64_ldst_pac(Rt, Rn, imm9, S) /* LDRAB , [{, #}]! (ffa00c00/f8a00c00) */ //#define IEM_INSTR_IMPL_A64__LDRAB_64W_ldst_pac(Rt, Rn, imm9, S) /* * * Instruction Set & Groups: ldst_pos / ldst / A64 * */ /* STRB , [{, #}] (ffc00000/39000000) */ //#define IEM_INSTR_IMPL_A64__STRB_32_ldst_pos(Rt, Rn, imm12) /* LDRB , [{, #}] (ffc00000/39400000) */ //#define IEM_INSTR_IMPL_A64__LDRB_32_ldst_pos(Rt, Rn, imm12) /* LDRSB , [{, #}] (ffc00000/39800000) */ //#define IEM_INSTR_IMPL_A64__LDRSB_64_ldst_pos(Rt, Rn, imm12) /* LDRSB , [{, #}] (ffc00000/39c00000) */ //#define IEM_INSTR_IMPL_A64__LDRSB_32_ldst_pos(Rt, Rn, imm12) /* STR , [{, #}] (ffc00000/3d000000) */ //#define IEM_INSTR_IMPL_A64__STR_B_ldst_pos(Rt, Rn, imm12) /* LDR , [{, #}] (ffc00000/3d400000) */ //#define IEM_INSTR_IMPL_A64__LDR_B_ldst_pos(Rt, Rn, imm12) /* STR , [{, #}] (ffc00000/3d800000) */ //#define IEM_INSTR_IMPL_A64__STR_Q_ldst_pos(Rt, Rn, imm12) /* LDR , [{, #}] (ffc00000/3dc00000) */ //#define IEM_INSTR_IMPL_A64__LDR_Q_ldst_pos(Rt, Rn, imm12) /* STRH , [{, #}] (ffc00000/79000000) */ //#define IEM_INSTR_IMPL_A64__STRH_32_ldst_pos(Rt, Rn, imm12) /* LDRH , [{, #}] (ffc00000/79400000) */ //#define IEM_INSTR_IMPL_A64__LDRH_32_ldst_pos(Rt, Rn, imm12) /* LDRSH , [{, #}] (ffc00000/79800000) */ //#define IEM_INSTR_IMPL_A64__LDRSH_64_ldst_pos(Rt, Rn, imm12) /* LDRSH , [{, #}] (ffc00000/79c00000) */ //#define IEM_INSTR_IMPL_A64__LDRSH_32_ldst_pos(Rt, Rn, imm12) /* STR , [{, #}] (ffc00000/7d000000) */ //#define IEM_INSTR_IMPL_A64__STR_H_ldst_pos(Rt, Rn, imm12) /* LDR , [{, #}] (ffc00000/7d400000) */ //#define IEM_INSTR_IMPL_A64__LDR_H_ldst_pos(Rt, Rn, imm12) /* STR , [{, #}] (ffc00000/b9000000) */ //#define IEM_INSTR_IMPL_A64__STR_32_ldst_pos(Rt, Rn, imm12) /* LDR , [{, #}] (ffc00000/b9400000) */ //#define IEM_INSTR_IMPL_A64__LDR_32_ldst_pos(Rt, Rn, imm12) /* LDRSW , [{, #}] (ffc00000/b9800000) */ //#define IEM_INSTR_IMPL_A64__LDRSW_64_ldst_pos(Rt, Rn, imm12) /* STR , [{, #}] (ffc00000/bd000000) */ //#define IEM_INSTR_IMPL_A64__STR_S_ldst_pos(Rt, Rn, imm12) /* LDR , [{, #}] (ffc00000/bd400000) */ //#define IEM_INSTR_IMPL_A64__LDR_S_ldst_pos(Rt, Rn, imm12) /* STR , [{, #}] (ffc00000/f9000000) */ //#define IEM_INSTR_IMPL_A64__STR_64_ldst_pos(Rt, Rn, imm12) /* LDR , [{, #}] (ffc00000/f9400000) */ //#define IEM_INSTR_IMPL_A64__LDR_64_ldst_pos(Rt, Rn, imm12) /* PRFM { | #}, [{, #}] (ffc00000/f9800000) */ //#define IEM_INSTR_IMPL_A64__PRFM_P_ldst_pos(Rt, Rn, imm12) /* STR
, [{, #}] (ffc00000/fd000000) */ //#define IEM_INSTR_IMPL_A64__STR_D_ldst_pos(Rt, Rn, imm12) /* LDR
, [{, #}] (ffc00000/fd400000) */ //#define IEM_INSTR_IMPL_A64__LDR_D_ldst_pos(Rt, Rn, imm12) /* * * Instruction Set & Groups: ldst_regoff / ldst / A64 * */ /* STRB , [, { | }, { }] (ffe00c00/38200800) */ //#define IEM_INSTR_IMPL_A64__STRB_32B_ldst_regoff(Rt, Rn, S, option, Rm) /* STRB , [, {, LSL }] (ffe0ec00/38206800) */ //#define IEM_INSTR_IMPL_A64__STRB_32BL_ldst_regoff(Rt, Rn, S, Rm) /* LDRB , [, { | }, { }] (ffe00c00/38600800) */ //#define IEM_INSTR_IMPL_A64__LDRB_32B_ldst_regoff(Rt, Rn, S, option, Rm) /* LDRB , [, {, LSL }] (ffe0ec00/38606800) */ //#define IEM_INSTR_IMPL_A64__LDRB_32BL_ldst_regoff(Rt, Rn, S, Rm) /* LDRSB , [, { | }, { }] (ffe00c00/38a00800) */ //#define IEM_INSTR_IMPL_A64__LDRSB_64B_ldst_regoff(Rt, Rn, S, option, Rm) /* LDRSB , [, {, LSL }] (ffe0ec00/38a06800) */ //#define IEM_INSTR_IMPL_A64__LDRSB_64BL_ldst_regoff(Rt, Rn, S, Rm) /* LDRSB , [, { | }, { }] (ffe00c00/38e00800) */ //#define IEM_INSTR_IMPL_A64__LDRSB_32B_ldst_regoff(Rt, Rn, S, option, Rm) /* LDRSB , [, {, LSL }] (ffe0ec00/38e06800) */ //#define IEM_INSTR_IMPL_A64__LDRSB_32BL_ldst_regoff(Rt, Rn, S, Rm) /* STR , [, { | }, { }] (ffe00c00/3c200800) */ //#define IEM_INSTR_IMPL_A64__STR_B_ldst_regoff(Rt, Rn, S, option, Rm) /* STR , [, {, LSL }] (ffe0ec00/3c206800) */ //#define IEM_INSTR_IMPL_A64__STR_BL_ldst_regoff(Rt, Rn, S, Rm) /* LDR , [, { | }, { }] (ffe00c00/3c600800) */ //#define IEM_INSTR_IMPL_A64__LDR_B_ldst_regoff(Rt, Rn, S, option, Rm) /* LDR , [, {, LSL }] (ffe0ec00/3c606800) */ //#define IEM_INSTR_IMPL_A64__LDR_BL_ldst_regoff(Rt, Rn, S, Rm) /* STR , [, { | }{, { }}] (ffe00c00/3ca00800) */ //#define IEM_INSTR_IMPL_A64__STR_Q_ldst_regoff(Rt, Rn, S, option, Rm) /* LDR , [, { | }{, { }}] (ffe00c00/3ce00800) */ //#define IEM_INSTR_IMPL_A64__LDR_Q_ldst_regoff(Rt, Rn, S, option, Rm) /* STRH , [, { | }{, { }}] (ffe00c00/78200800) */ //#define IEM_INSTR_IMPL_A64__STRH_32_ldst_regoff(Rt, Rn, S, option, Rm) /* LDRH , [, { | }{, { }}] (ffe00c00/78600800) */ //#define IEM_INSTR_IMPL_A64__LDRH_32_ldst_regoff(Rt, Rn, S, option, Rm) /* LDRSH , [, { | }{, { }}] (ffe00c00/78a00800) */ //#define IEM_INSTR_IMPL_A64__LDRSH_64_ldst_regoff(Rt, Rn, S, option, Rm) /* LDRSH , [, { | }{, { }}] (ffe00c00/78e00800) */ //#define IEM_INSTR_IMPL_A64__LDRSH_32_ldst_regoff(Rt, Rn, S, option, Rm) /* STR , [, { | }{, { }}] (ffe00c00/7c200800) */ //#define IEM_INSTR_IMPL_A64__STR_H_ldst_regoff(Rt, Rn, S, option, Rm) /* LDR , [, { | }{, { }}] (ffe00c00/7c600800) */ //#define IEM_INSTR_IMPL_A64__LDR_H_ldst_regoff(Rt, Rn, S, option, Rm) /* STR , [, { | }{, { }}] (ffe00c00/b8200800) */ //#define IEM_INSTR_IMPL_A64__STR_32_ldst_regoff(Rt, Rn, S, option, Rm) /* LDR , [, { | }{, { }}] (ffe00c00/b8600800) */ //#define IEM_INSTR_IMPL_A64__LDR_32_ldst_regoff(Rt, Rn, S, option, Rm) /* LDRSW , [, { | }{, { }}] (ffe00c00/b8a00800) */ //#define IEM_INSTR_IMPL_A64__LDRSW_64_ldst_regoff(Rt, Rn, S, option, Rm) /* STR , [, { | }{, { }}] (ffe00c00/bc200800) */ //#define IEM_INSTR_IMPL_A64__STR_S_ldst_regoff(Rt, Rn, S, option, Rm) /* LDR , [, { | }{, { }}] (ffe00c00/bc600800) */ //#define IEM_INSTR_IMPL_A64__LDR_S_ldst_regoff(Rt, Rn, S, option, Rm) /* STR , [, { | }{, { }}] (ffe00c00/f8200800) */ //#define IEM_INSTR_IMPL_A64__STR_64_ldst_regoff(Rt, Rn, S, option, Rm) /* LDR , [, { | }{, { }}] (ffe00c00/f8600800) */ //#define IEM_INSTR_IMPL_A64__LDR_64_ldst_regoff(Rt, Rn, S, option, Rm) /* PRFM { | #}, [, { | }{, { }}] (ffe00c00/f8a00800) */ //#define IEM_INSTR_IMPL_A64__PRFM_P_ldst_regoff(Rt, Rn, S, option, Rm) /* RPRFM { | #}, , [] (ffe00c00/f8a00800) */ //#define IEM_INSTR_IMPL_A64__RPRFM_R_ldst_regoff(Rt, Rn, S, option, Rm) /* STR
, [, { | }{, { }}] (ffe00c00/fc200800) */ //#define IEM_INSTR_IMPL_A64__STR_D_ldst_regoff(Rt, Rn, S, option, Rm) /* LDR
, [, { | }{, { }}] (ffe00c00/fc600800) */ //#define IEM_INSTR_IMPL_A64__LDR_D_ldst_regoff(Rt, Rn, S, option, Rm) /* * * Instruction Set & Groups: ldst_unpriv / ldst / A64 * */ /* STTRB , [{, #}] (ffe00c00/38000800) */ //#define IEM_INSTR_IMPL_A64__STTRB_32_ldst_unpriv(Rt, Rn, imm9) /* LDTRB , [{, #}] (ffe00c00/38400800) */ //#define IEM_INSTR_IMPL_A64__LDTRB_32_ldst_unpriv(Rt, Rn, imm9) /* LDTRSB , [{, #}] (ffe00c00/38800800) */ //#define IEM_INSTR_IMPL_A64__LDTRSB_64_ldst_unpriv(Rt, Rn, imm9) /* LDTRSB , [{, #}] (ffe00c00/38c00800) */ //#define IEM_INSTR_IMPL_A64__LDTRSB_32_ldst_unpriv(Rt, Rn, imm9) /* STTRH , [{, #}] (ffe00c00/78000800) */ //#define IEM_INSTR_IMPL_A64__STTRH_32_ldst_unpriv(Rt, Rn, imm9) /* LDTRH , [{, #}] (ffe00c00/78400800) */ //#define IEM_INSTR_IMPL_A64__LDTRH_32_ldst_unpriv(Rt, Rn, imm9) /* LDTRSH , [{, #}] (ffe00c00/78800800) */ //#define IEM_INSTR_IMPL_A64__LDTRSH_64_ldst_unpriv(Rt, Rn, imm9) /* LDTRSH , [{, #}] (ffe00c00/78c00800) */ //#define IEM_INSTR_IMPL_A64__LDTRSH_32_ldst_unpriv(Rt, Rn, imm9) /* STTR , [{, #}] (ffe00c00/b8000800) */ //#define IEM_INSTR_IMPL_A64__STTR_32_ldst_unpriv(Rt, Rn, imm9) /* LDTR , [{, #}] (ffe00c00/b8400800) */ //#define IEM_INSTR_IMPL_A64__LDTR_32_ldst_unpriv(Rt, Rn, imm9) /* LDTRSW , [{, #}] (ffe00c00/b8800800) */ //#define IEM_INSTR_IMPL_A64__LDTRSW_64_ldst_unpriv(Rt, Rn, imm9) /* STTR , [{, #}] (ffe00c00/f8000800) */ //#define IEM_INSTR_IMPL_A64__STTR_64_ldst_unpriv(Rt, Rn, imm9) /* LDTR , [{, #}] (ffe00c00/f8400800) */ //#define IEM_INSTR_IMPL_A64__LDTR_64_ldst_unpriv(Rt, Rn, imm9) /* * * Instruction Set & Groups: ldst_unscaled / ldst / A64 * */ /* STURB , [{, #}] (ffe00c00/38000000) */ //#define IEM_INSTR_IMPL_A64__STURB_32_ldst_unscaled(Rt, Rn, imm9) /* LDURB , [{, #}] (ffe00c00/38400000) */ //#define IEM_INSTR_IMPL_A64__LDURB_32_ldst_unscaled(Rt, Rn, imm9) /* LDURSB , [{, #}] (ffe00c00/38800000) */ //#define IEM_INSTR_IMPL_A64__LDURSB_64_ldst_unscaled(Rt, Rn, imm9) /* LDURSB , [{, #}] (ffe00c00/38c00000) */ //#define IEM_INSTR_IMPL_A64__LDURSB_32_ldst_unscaled(Rt, Rn, imm9) /* STUR , [{, #}] (ffe00c00/3c000000) */ //#define IEM_INSTR_IMPL_A64__STUR_B_ldst_unscaled(Rt, Rn, imm9) /* LDUR , [{, #}] (ffe00c00/3c400000) */ //#define IEM_INSTR_IMPL_A64__LDUR_B_ldst_unscaled(Rt, Rn, imm9) /* STUR , [{, #}] (ffe00c00/3c800000) */ //#define IEM_INSTR_IMPL_A64__STUR_Q_ldst_unscaled(Rt, Rn, imm9) /* LDUR , [{, #}] (ffe00c00/3cc00000) */ //#define IEM_INSTR_IMPL_A64__LDUR_Q_ldst_unscaled(Rt, Rn, imm9) /* STURH , [{, #}] (ffe00c00/78000000) */ //#define IEM_INSTR_IMPL_A64__STURH_32_ldst_unscaled(Rt, Rn, imm9) /* LDURH , [{, #}] (ffe00c00/78400000) */ //#define IEM_INSTR_IMPL_A64__LDURH_32_ldst_unscaled(Rt, Rn, imm9) /* LDURSH , [{, #}] (ffe00c00/78800000) */ //#define IEM_INSTR_IMPL_A64__LDURSH_64_ldst_unscaled(Rt, Rn, imm9) /* LDURSH , [{, #}] (ffe00c00/78c00000) */ //#define IEM_INSTR_IMPL_A64__LDURSH_32_ldst_unscaled(Rt, Rn, imm9) /* STUR , [{, #}] (ffe00c00/7c000000) */ //#define IEM_INSTR_IMPL_A64__STUR_H_ldst_unscaled(Rt, Rn, imm9) /* LDUR , [{, #}] (ffe00c00/7c400000) */ //#define IEM_INSTR_IMPL_A64__LDUR_H_ldst_unscaled(Rt, Rn, imm9) /* STUR , [{, #}] (ffe00c00/b8000000) */ //#define IEM_INSTR_IMPL_A64__STUR_32_ldst_unscaled(Rt, Rn, imm9) /* LDUR , [{, #}] (ffe00c00/b8400000) */ //#define IEM_INSTR_IMPL_A64__LDUR_32_ldst_unscaled(Rt, Rn, imm9) /* LDURSW , [{, #}] (ffe00c00/b8800000) */ //#define IEM_INSTR_IMPL_A64__LDURSW_64_ldst_unscaled(Rt, Rn, imm9) /* STUR , [{, #}] (ffe00c00/bc000000) */ //#define IEM_INSTR_IMPL_A64__STUR_S_ldst_unscaled(Rt, Rn, imm9) /* LDUR , [{, #}] (ffe00c00/bc400000) */ //#define IEM_INSTR_IMPL_A64__LDUR_S_ldst_unscaled(Rt, Rn, imm9) /* STUR , [{, #}] (ffe00c00/f8000000) */ //#define IEM_INSTR_IMPL_A64__STUR_64_ldst_unscaled(Rt, Rn, imm9) /* LDUR , [{, #}] (ffe00c00/f8400000) */ //#define IEM_INSTR_IMPL_A64__LDUR_64_ldst_unscaled(Rt, Rn, imm9) /* PRFUM { | #}, [{, #}] (ffe00c00/f8800000) */ //#define IEM_INSTR_IMPL_A64__PRFUM_P_ldst_unscaled(Rt, Rn, imm9) /* STUR
, [{, #}] (ffe00c00/fc000000) */ //#define IEM_INSTR_IMPL_A64__STUR_D_ldst_unscaled(Rt, Rn, imm9) /* LDUR
, [{, #}] (ffe00c00/fc400000) */ //#define IEM_INSTR_IMPL_A64__LDUR_D_ldst_unscaled(Rt, Rn, imm9) /* * * Instruction Set & Groups: ldstexclp / ldst / A64 * */ /* STXP , , , [{, #0}] (ffe08000/88200000) */ //#define IEM_INSTR_IMPL_A64__STXP_SP32_ldstexclp(Rt, Rn, Rt2, Rs) /* STLXP , , , [{, #0}] (ffe08000/88208000) */ //#define IEM_INSTR_IMPL_A64__STLXP_SP32_ldstexclp(Rt, Rn, Rt2, Rs) /* LDXP , , [{, #0}] (ffff8000/887f0000) */ //#define IEM_INSTR_IMPL_A64__LDXP_LP32_ldstexclp(Rt, Rn, Rt2) /* LDAXP , , [{, #0}] (ffff8000/887f8000) */ //#define IEM_INSTR_IMPL_A64__LDAXP_LP32_ldstexclp(Rt, Rn, Rt2) /* STXP , , , [{, #0}] (ffe08000/c8200000) */ //#define IEM_INSTR_IMPL_A64__STXP_SP64_ldstexclp(Rt, Rn, Rt2, Rs) /* STLXP , , , [{, #0}] (ffe08000/c8208000) */ //#define IEM_INSTR_IMPL_A64__STLXP_SP64_ldstexclp(Rt, Rn, Rt2, Rs) /* LDXP , , [{, #0}] (ffff8000/c87f0000) */ //#define IEM_INSTR_IMPL_A64__LDXP_LP64_ldstexclp(Rt, Rn, Rt2) /* LDAXP , , [{, #0}] (ffff8000/c87f8000) */ //#define IEM_INSTR_IMPL_A64__LDAXP_LP64_ldstexclp(Rt, Rn, Rt2) /* * * Instruction Set & Groups: ldstexclr / ldst / A64 * */ /* STXRB , , [{, #0}] (ffe0fc00/08007c00) */ //#define IEM_INSTR_IMPL_A64__STXRB_SR32_ldstexclr(Rt, Rn, Rs) /* STLXRB , , [{, #0}] (ffe0fc00/0800fc00) */ //#define IEM_INSTR_IMPL_A64__STLXRB_SR32_ldstexclr(Rt, Rn, Rs) /* LDXRB , [{, #0}] (fffffc00/085f7c00) */ //#define IEM_INSTR_IMPL_A64__LDXRB_LR32_ldstexclr(Rt, Rn) /* LDAXRB , [{, #0}] (fffffc00/085ffc00) */ //#define IEM_INSTR_IMPL_A64__LDAXRB_LR32_ldstexclr(Rt, Rn) /* STXRH , , [{, #0}] (ffe0fc00/48007c00) */ //#define IEM_INSTR_IMPL_A64__STXRH_SR32_ldstexclr(Rt, Rn, Rs) /* STLXRH , , [{, #0}] (ffe0fc00/4800fc00) */ //#define IEM_INSTR_IMPL_A64__STLXRH_SR32_ldstexclr(Rt, Rn, Rs) /* LDXRH , [{, #0}] (fffffc00/485f7c00) */ //#define IEM_INSTR_IMPL_A64__LDXRH_LR32_ldstexclr(Rt, Rn) /* LDAXRH , [{, #0}] (fffffc00/485ffc00) */ //#define IEM_INSTR_IMPL_A64__LDAXRH_LR32_ldstexclr(Rt, Rn) /* STXR , , [{, #0}] (ffe0fc00/88007c00) */ //#define IEM_INSTR_IMPL_A64__STXR_SR32_ldstexclr(Rt, Rn, Rs) /* STLXR , , [{, #0}] (ffe0fc00/8800fc00) */ //#define IEM_INSTR_IMPL_A64__STLXR_SR32_ldstexclr(Rt, Rn, Rs) /* LDXR , [{, #0}] (fffffc00/885f7c00) */ //#define IEM_INSTR_IMPL_A64__LDXR_LR32_ldstexclr(Rt, Rn) /* LDAXR , [{, #0}] (fffffc00/885ffc00) */ //#define IEM_INSTR_IMPL_A64__LDAXR_LR32_ldstexclr(Rt, Rn) /* STXR , , [{, #0}] (ffe0fc00/c8007c00) */ //#define IEM_INSTR_IMPL_A64__STXR_SR64_ldstexclr(Rt, Rn, Rs) /* STLXR , , [{, #0}] (ffe0fc00/c800fc00) */ //#define IEM_INSTR_IMPL_A64__STLXR_SR64_ldstexclr(Rt, Rn, Rs) /* LDXR , [{, #0}] (fffffc00/c85f7c00) */ //#define IEM_INSTR_IMPL_A64__LDXR_LR64_ldstexclr(Rt, Rn) /* LDAXR , [{, #0}] (fffffc00/c85ffc00) */ //#define IEM_INSTR_IMPL_A64__LDAXR_LR64_ldstexclr(Rt, Rn) /* * * Instruction Set & Groups: ldstexclr_unpriv / ldst / A64 * */ /* STTXR , , [{, #0}] (ffe0fc00/89007c00) */ //#define IEM_INSTR_IMPL_A64__STTXR_SR32_ldstexclr_unpriv(Rt, Rn, Rs) /* STLTXR , , [{, #0}] (ffe0fc00/8900fc00) */ //#define IEM_INSTR_IMPL_A64__STLTXR_SR32_ldstexclr_unpriv(Rt, Rn, Rs) /* LDTXR , [{, #0}] (fffffc00/895f7c00) */ //#define IEM_INSTR_IMPL_A64__LDTXR_LR32_ldstexclr_unpriv(Rt, Rn) /* LDATXR , [{, #0}] (fffffc00/895ffc00) */ //#define IEM_INSTR_IMPL_A64__LDATXR_LR32_ldstexclr_unpriv(Rt, Rn) /* STTXR , , [{, #0}] (ffe0fc00/c9007c00) */ //#define IEM_INSTR_IMPL_A64__STTXR_SR64_ldstexclr_unpriv(Rt, Rn, Rs) /* STLTXR , , [{, #0}] (ffe0fc00/c900fc00) */ //#define IEM_INSTR_IMPL_A64__STLTXR_SR64_ldstexclr_unpriv(Rt, Rn, Rs) /* LDTXR , [{, #0}] (fffffc00/c95f7c00) */ //#define IEM_INSTR_IMPL_A64__LDTXR_LR64_ldstexclr_unpriv(Rt, Rn) /* LDATXR , [{, #0}] (fffffc00/c95ffc00) */ //#define IEM_INSTR_IMPL_A64__LDATXR_LR64_ldstexclr_unpriv(Rt, Rn) /* * * Instruction Set & Groups: ldstnapair_offs / ldst / A64 * */ /* STNP , , [{, #}] (ffc00000/28000000) */ //#define IEM_INSTR_IMPL_A64__STNP_32_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* LDNP , , [{, #}] (ffc00000/28400000) */ //#define IEM_INSTR_IMPL_A64__LDNP_32_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* STNP , , [{, #}] (ffc00000/2c000000) */ //#define IEM_INSTR_IMPL_A64__STNP_S_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* LDNP , , [{, #}] (ffc00000/2c400000) */ //#define IEM_INSTR_IMPL_A64__LDNP_S_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* STNP , , [{, #}] (ffc00000/6c000000) */ //#define IEM_INSTR_IMPL_A64__STNP_D_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* LDNP , , [{, #}] (ffc00000/6c400000) */ //#define IEM_INSTR_IMPL_A64__LDNP_D_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* STNP , , [{, #}] (ffc00000/a8000000) */ //#define IEM_INSTR_IMPL_A64__STNP_64_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* LDNP , , [{, #}] (ffc00000/a8400000) */ //#define IEM_INSTR_IMPL_A64__LDNP_64_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* STNP , , [{, #}] (ffc00000/ac000000) */ //#define IEM_INSTR_IMPL_A64__STNP_Q_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* LDNP , , [{, #}] (ffc00000/ac400000) */ //#define IEM_INSTR_IMPL_A64__LDNP_Q_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* STTNP , , [{, #}] (ffc00000/e8000000) */ //#define IEM_INSTR_IMPL_A64__STTNP_64_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* LDTNP , , [{, #}] (ffc00000/e8400000) */ //#define IEM_INSTR_IMPL_A64__LDTNP_64_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* STTNP , , [{, #}] (ffc00000/ec000000) */ //#define IEM_INSTR_IMPL_A64__STTNP_Q_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* LDTNP , , [{, #}] (ffc00000/ec400000) */ //#define IEM_INSTR_IMPL_A64__LDTNP_Q_ldstnapair_offs(Rt, Rn, Rt2, imm7) /* * * Instruction Set & Groups: ldstord / ldst / A64 * */ /* STLLRB , [{, #0}] (fffffc00/089f7c00) */ //#define IEM_INSTR_IMPL_A64__STLLRB_SL32_ldstord(Rt, Rn) /* STLRB , [{, #0}] (fffffc00/089ffc00) */ //#define IEM_INSTR_IMPL_A64__STLRB_SL32_ldstord(Rt, Rn) /* LDLARB , [{, #0}] (fffffc00/08df7c00) */ //#define IEM_INSTR_IMPL_A64__LDLARB_LR32_ldstord(Rt, Rn) /* LDARB , [{, #0}] (fffffc00/08dffc00) */ //#define IEM_INSTR_IMPL_A64__LDARB_LR32_ldstord(Rt, Rn) /* STLLRH , [{, #0}] (fffffc00/489f7c00) */ //#define IEM_INSTR_IMPL_A64__STLLRH_SL32_ldstord(Rt, Rn) /* STLRH , [{, #0}] (fffffc00/489ffc00) */ //#define IEM_INSTR_IMPL_A64__STLRH_SL32_ldstord(Rt, Rn) /* LDLARH , [{, #0}] (fffffc00/48df7c00) */ //#define IEM_INSTR_IMPL_A64__LDLARH_LR32_ldstord(Rt, Rn) /* LDARH , [{, #0}] (fffffc00/48dffc00) */ //#define IEM_INSTR_IMPL_A64__LDARH_LR32_ldstord(Rt, Rn) /* STLLR , [{, #0}] (fffffc00/889f7c00) */ //#define IEM_INSTR_IMPL_A64__STLLR_SL32_ldstord(Rt, Rn) /* STLR , [{, #0}] (fffffc00/889ffc00) */ //#define IEM_INSTR_IMPL_A64__STLR_SL32_ldstord(Rt, Rn) /* LDLAR , [{, #0}] (fffffc00/88df7c00) */ //#define IEM_INSTR_IMPL_A64__LDLAR_LR32_ldstord(Rt, Rn) /* LDAR , [{, #0}] (fffffc00/88dffc00) */ //#define IEM_INSTR_IMPL_A64__LDAR_LR32_ldstord(Rt, Rn) /* STLLR , [{, #0}] (fffffc00/c89f7c00) */ //#define IEM_INSTR_IMPL_A64__STLLR_SL64_ldstord(Rt, Rn) /* STLR , [{, #0}] (fffffc00/c89ffc00) */ //#define IEM_INSTR_IMPL_A64__STLR_SL64_ldstord(Rt, Rn) /* LDLAR , [{, #0}] (fffffc00/c8df7c00) */ //#define IEM_INSTR_IMPL_A64__LDLAR_LR64_ldstord(Rt, Rn) /* LDAR , [{, #0}] (fffffc00/c8dffc00) */ //#define IEM_INSTR_IMPL_A64__LDAR_LR64_ldstord(Rt, Rn) /* * * Instruction Set & Groups: ldstpair_off / ldst / A64 * */ /* STP , , [{, #}] (ffc00000/29000000) */ //#define IEM_INSTR_IMPL_A64__STP_32_ldstpair_off(Rt, Rn, Rt2, imm7) /* LDP , , [{, #}] (ffc00000/29400000) */ //#define IEM_INSTR_IMPL_A64__LDP_32_ldstpair_off(Rt, Rn, Rt2, imm7) /* STP , , [{, #}] (ffc00000/2d000000) */ //#define IEM_INSTR_IMPL_A64__STP_S_ldstpair_off(Rt, Rn, Rt2, imm7) /* LDP , , [{, #}] (ffc00000/2d400000) */ //#define IEM_INSTR_IMPL_A64__LDP_S_ldstpair_off(Rt, Rn, Rt2, imm7) /* STGP , , [{, #}] (ffc00000/69000000) */ //#define IEM_INSTR_IMPL_A64__STGP_64_ldstpair_off(Rt, Rn, Rt2, simm7) /* LDPSW , , [{, #}] (ffc00000/69400000) */ //#define IEM_INSTR_IMPL_A64__LDPSW_64_ldstpair_off(Rt, Rn, Rt2, imm7) /* STP , , [{, #}] (ffc00000/6d000000) */ //#define IEM_INSTR_IMPL_A64__STP_D_ldstpair_off(Rt, Rn, Rt2, imm7) /* LDP , , [{, #}] (ffc00000/6d400000) */ //#define IEM_INSTR_IMPL_A64__LDP_D_ldstpair_off(Rt, Rn, Rt2, imm7) /* STP , , [{, #}] (ffc00000/a9000000) */ //#define IEM_INSTR_IMPL_A64__STP_64_ldstpair_off(Rt, Rn, Rt2, imm7) /* LDP , , [{, #}] (ffc00000/a9400000) */ //#define IEM_INSTR_IMPL_A64__LDP_64_ldstpair_off(Rt, Rn, Rt2, imm7) /* STP , , [{, #}] (ffc00000/ad000000) */ //#define IEM_INSTR_IMPL_A64__STP_Q_ldstpair_off(Rt, Rn, Rt2, imm7) /* LDP , , [{, #}] (ffc00000/ad400000) */ //#define IEM_INSTR_IMPL_A64__LDP_Q_ldstpair_off(Rt, Rn, Rt2, imm7) /* STTP , , [{, #}] (ffc00000/e9000000) */ //#define IEM_INSTR_IMPL_A64__STTP_64_ldstpair_off(Rt, Rn, Rt2, imm7) /* LDTP , , [{, #}] (ffc00000/e9400000) */ //#define IEM_INSTR_IMPL_A64__LDTP_64_ldstpair_off(Rt, Rn, Rt2, imm7) /* STTP , , [{, #}] (ffc00000/ed000000) */ //#define IEM_INSTR_IMPL_A64__STTP_Q_ldstpair_off(Rt, Rn, Rt2, imm7) /* LDTP , , [{, #}] (ffc00000/ed400000) */ //#define IEM_INSTR_IMPL_A64__LDTP_Q_ldstpair_off(Rt, Rn, Rt2, imm7) /* * * Instruction Set & Groups: ldstpair_post / ldst / A64 * */ /* STP , , [], # (ffc00000/28800000) */ //#define IEM_INSTR_IMPL_A64__STP_32_ldstpair_post(Rt, Rn, Rt2, imm7) /* LDP , , [], # (ffc00000/28c00000) */ //#define IEM_INSTR_IMPL_A64__LDP_32_ldstpair_post(Rt, Rn, Rt2, imm7) /* STP , , [], # (ffc00000/2c800000) */ //#define IEM_INSTR_IMPL_A64__STP_S_ldstpair_post(Rt, Rn, Rt2, imm7) /* LDP , , [], # (ffc00000/2cc00000) */ //#define IEM_INSTR_IMPL_A64__LDP_S_ldstpair_post(Rt, Rn, Rt2, imm7) /* STGP , , [], # (ffc00000/68800000) */ //#define IEM_INSTR_IMPL_A64__STGP_64_ldstpair_post(Rt, Rn, Rt2, simm7) /* LDPSW , , [], # (ffc00000/68c00000) */ //#define IEM_INSTR_IMPL_A64__LDPSW_64_ldstpair_post(Rt, Rn, Rt2, imm7) /* STP , , [], # (ffc00000/6c800000) */ //#define IEM_INSTR_IMPL_A64__STP_D_ldstpair_post(Rt, Rn, Rt2, imm7) /* LDP , , [], # (ffc00000/6cc00000) */ //#define IEM_INSTR_IMPL_A64__LDP_D_ldstpair_post(Rt, Rn, Rt2, imm7) /* STP , , [], # (ffc00000/a8800000) */ //#define IEM_INSTR_IMPL_A64__STP_64_ldstpair_post(Rt, Rn, Rt2, imm7) /* LDP , , [], # (ffc00000/a8c00000) */ //#define IEM_INSTR_IMPL_A64__LDP_64_ldstpair_post(Rt, Rn, Rt2, imm7) /* STP , , [], # (ffc00000/ac800000) */ //#define IEM_INSTR_IMPL_A64__STP_Q_ldstpair_post(Rt, Rn, Rt2, imm7) /* LDP , , [], # (ffc00000/acc00000) */ //#define IEM_INSTR_IMPL_A64__LDP_Q_ldstpair_post(Rt, Rn, Rt2, imm7) /* STTP , , [], # (ffc00000/e8800000) */ //#define IEM_INSTR_IMPL_A64__STTP_64_ldstpair_post(Rt, Rn, Rt2, imm7) /* LDTP , , [], # (ffc00000/e8c00000) */ //#define IEM_INSTR_IMPL_A64__LDTP_64_ldstpair_post(Rt, Rn, Rt2, imm7) /* STTP , , [], # (ffc00000/ec800000) */ //#define IEM_INSTR_IMPL_A64__STTP_Q_ldstpair_post(Rt, Rn, Rt2, imm7) /* LDTP , , [], # (ffc00000/ecc00000) */ //#define IEM_INSTR_IMPL_A64__LDTP_Q_ldstpair_post(Rt, Rn, Rt2, imm7) /* * * Instruction Set & Groups: ldstpair_pre / ldst / A64 * */ /* STP , , [, #]! (ffc00000/29800000) */ //#define IEM_INSTR_IMPL_A64__STP_32_ldstpair_pre(Rt, Rn, Rt2, imm7) /* LDP , , [, #]! (ffc00000/29c00000) */ //#define IEM_INSTR_IMPL_A64__LDP_32_ldstpair_pre(Rt, Rn, Rt2, imm7) /* STP , , [, #]! (ffc00000/2d800000) */ //#define IEM_INSTR_IMPL_A64__STP_S_ldstpair_pre(Rt, Rn, Rt2, imm7) /* LDP , , [, #]! (ffc00000/2dc00000) */ //#define IEM_INSTR_IMPL_A64__LDP_S_ldstpair_pre(Rt, Rn, Rt2, imm7) /* STGP , , [, #]! (ffc00000/69800000) */ //#define IEM_INSTR_IMPL_A64__STGP_64_ldstpair_pre(Rt, Rn, Rt2, simm7) /* LDPSW , , [, #]! (ffc00000/69c00000) */ //#define IEM_INSTR_IMPL_A64__LDPSW_64_ldstpair_pre(Rt, Rn, Rt2, imm7) /* STP , , [, #]! (ffc00000/6d800000) */ //#define IEM_INSTR_IMPL_A64__STP_D_ldstpair_pre(Rt, Rn, Rt2, imm7) /* LDP , , [, #]! (ffc00000/6dc00000) */ //#define IEM_INSTR_IMPL_A64__LDP_D_ldstpair_pre(Rt, Rn, Rt2, imm7) /* STP , , [, #]! (ffc00000/a9800000) */ //#define IEM_INSTR_IMPL_A64__STP_64_ldstpair_pre(Rt, Rn, Rt2, imm7) /* LDP , , [, #]! (ffc00000/a9c00000) */ //#define IEM_INSTR_IMPL_A64__LDP_64_ldstpair_pre(Rt, Rn, Rt2, imm7) /* STP , , [, #]! (ffc00000/ad800000) */ //#define IEM_INSTR_IMPL_A64__STP_Q_ldstpair_pre(Rt, Rn, Rt2, imm7) /* LDP , , [, #]! (ffc00000/adc00000) */ //#define IEM_INSTR_IMPL_A64__LDP_Q_ldstpair_pre(Rt, Rn, Rt2, imm7) /* STTP , , [, #]! (ffc00000/e9800000) */ //#define IEM_INSTR_IMPL_A64__STTP_64_ldstpair_pre(Rt, Rn, Rt2, imm7) /* LDTP , , [, #]! (ffc00000/e9c00000) */ //#define IEM_INSTR_IMPL_A64__LDTP_64_ldstpair_pre(Rt, Rn, Rt2, imm7) /* STTP , , [, #]! (ffc00000/ed800000) */ //#define IEM_INSTR_IMPL_A64__STTP_Q_ldstpair_pre(Rt, Rn, Rt2, imm7) /* LDTP , , [, #]! (ffc00000/edc00000) */ //#define IEM_INSTR_IMPL_A64__LDTP_Q_ldstpair_pre(Rt, Rn, Rt2, imm7) /* * * Instruction Set & Groups: ldsttags / ldst / A64 * */ /* STG , [], # (ffe00c00/d9200400) */ //#define IEM_INSTR_IMPL_A64__STG_64Spost_ldsttags(Rt, Rn, imm9) /* STG , [{, #}] (ffe00c00/d9200800) */ //#define IEM_INSTR_IMPL_A64__STG_64Soffset_ldsttags(Rt, Rn, imm9) /* STG , [, #]! (ffe00c00/d9200c00) */ //#define IEM_INSTR_IMPL_A64__STG_64Spre_ldsttags(Rt, Rn, imm9) /* STZGM , [] (fffffc00/d9200000) */ //#define IEM_INSTR_IMPL_A64__STZGM_64bulk_ldsttags(Rt, Rn) /* LDG , [{, #}] (ffe00c00/d9600000) */ //#define IEM_INSTR_IMPL_A64__LDG_64Loffset_ldsttags(Rt, Rn, imm9) /* STZG , [], # (ffe00c00/d9600400) */ //#define IEM_INSTR_IMPL_A64__STZG_64Spost_ldsttags(Rt, Rn, imm9) /* STZG , [{, #}] (ffe00c00/d9600800) */ //#define IEM_INSTR_IMPL_A64__STZG_64Soffset_ldsttags(Rt, Rn, imm9) /* STZG , [, #]! (ffe00c00/d9600c00) */ //#define IEM_INSTR_IMPL_A64__STZG_64Spre_ldsttags(Rt, Rn, imm9) /* ST2G , [], # (ffe00c00/d9a00400) */ //#define IEM_INSTR_IMPL_A64__ST2G_64Spost_ldsttags(Rt, Rn, imm9) /* ST2G , [{, #}] (ffe00c00/d9a00800) */ //#define IEM_INSTR_IMPL_A64__ST2G_64Soffset_ldsttags(Rt, Rn, imm9) /* ST2G , [, #]! (ffe00c00/d9a00c00) */ //#define IEM_INSTR_IMPL_A64__ST2G_64Spre_ldsttags(Rt, Rn, imm9) /* STGM , [] (fffffc00/d9a00000) */ //#define IEM_INSTR_IMPL_A64__STGM_64bulk_ldsttags(Rt, Rn) /* STZ2G , [], # (ffe00c00/d9e00400) */ //#define IEM_INSTR_IMPL_A64__STZ2G_64Spost_ldsttags(Rt, Rn, imm9) /* STZ2G , [{, #}] (ffe00c00/d9e00800) */ //#define IEM_INSTR_IMPL_A64__STZ2G_64Soffset_ldsttags(Rt, Rn, imm9) /* STZ2G , [, #]! (ffe00c00/d9e00c00) */ //#define IEM_INSTR_IMPL_A64__STZ2G_64Spre_ldsttags(Rt, Rn, imm9) /* LDGM , [] (fffffc00/d9e00000) */ //#define IEM_INSTR_IMPL_A64__LDGM_64bulk_ldsttags(Rt, Rn) /* * * Instruction Set & Groups: loadlit / ldst / A64 * */ /* LDR ,
,
, [] (ffe0fc00/fc200000) */ //#define IEM_INSTR_IMPL_A64__LDFADD_64(Rt, Rn, Rs) /* LDFMAX ,
, [] (ffe0fc00/fc204000) */ //#define IEM_INSTR_IMPL_A64__LDFMAX_64(Rt, Rn, Rs) /* LDFMIN ,
, [] (ffe0fc00/fc205000) */ //#define IEM_INSTR_IMPL_A64__LDFMIN_64(Rt, Rn, Rs) /* LDFMAXNM ,
, [] (ffe0fc00/fc206000) */ //#define IEM_INSTR_IMPL_A64__LDFMAXNM_64(Rt, Rn, Rs) /* LDFMINNM ,
, [] (ffe0fc00/fc207000) */ //#define IEM_INSTR_IMPL_A64__LDFMINNM_64(Rt, Rn, Rs) /* STFADD , [] (ffe0fc1f/fc20801f) */ //#define IEM_INSTR_IMPL_A64__STFADD_64(Rn, Rs) /* STFMAX , [] (ffe0fc1f/fc20c01f) */ //#define IEM_INSTR_IMPL_A64__STFMAX_64(Rn, Rs) /* STFMIN , [] (ffe0fc1f/fc20d01f) */ //#define IEM_INSTR_IMPL_A64__STFMIN_64(Rn, Rs) /* STFMAXNM , [] (ffe0fc1f/fc20e01f) */ //#define IEM_INSTR_IMPL_A64__STFMAXNM_64(Rn, Rs) /* STFMINNM , [] (ffe0fc1f/fc20f01f) */ //#define IEM_INSTR_IMPL_A64__STFMINNM_64(Rn, Rs) /* STFADDL , [] (ffe0fc1f/fc60801f) */ //#define IEM_INSTR_IMPL_A64__STFADDL_64(Rn, Rs) /* STFMAXL , [] (ffe0fc1f/fc60c01f) */ //#define IEM_INSTR_IMPL_A64__STFMAXL_64(Rn, Rs) /* STFMINL , [] (ffe0fc1f/fc60d01f) */ //#define IEM_INSTR_IMPL_A64__STFMINL_64(Rn, Rs) /* STFMAXNML , [] (ffe0fc1f/fc60e01f) */ //#define IEM_INSTR_IMPL_A64__STFMAXNML_64(Rn, Rs) /* STFMINNML , [] (ffe0fc1f/fc60f01f) */ //#define IEM_INSTR_IMPL_A64__STFMINNML_64(Rn, Rs) /* LDFADDL ,
, [] (ffe0fc00/fc600000) */ //#define IEM_INSTR_IMPL_A64__LDFADDL_64(Rt, Rn, Rs) /* LDFMAXL ,
, [] (ffe0fc00/fc604000) */ //#define IEM_INSTR_IMPL_A64__LDFMAXL_64(Rt, Rn, Rs) /* LDFMINL ,
, [] (ffe0fc00/fc605000) */ //#define IEM_INSTR_IMPL_A64__LDFMINL_64(Rt, Rn, Rs) /* LDFMAXNML ,
, [] (ffe0fc00/fc606000) */ //#define IEM_INSTR_IMPL_A64__LDFMAXNML_64(Rt, Rn, Rs) /* LDFMINNML ,
, [] (ffe0fc00/fc607000) */ //#define IEM_INSTR_IMPL_A64__LDFMINNML_64(Rt, Rn, Rs) /* LDFADDA ,
, [] (ffe0fc00/fca00000) */ //#define IEM_INSTR_IMPL_A64__LDFADDA_64(Rt, Rn, Rs) /* LDFMAXA ,
, [] (ffe0fc00/fca04000) */ //#define IEM_INSTR_IMPL_A64__LDFMAXA_64(Rt, Rn, Rs) /* LDFMINA ,
, [] (ffe0fc00/fca05000) */ //#define IEM_INSTR_IMPL_A64__LDFMINA_64(Rt, Rn, Rs) /* LDFMAXNMA ,
, [] (ffe0fc00/fca06000) */ //#define IEM_INSTR_IMPL_A64__LDFMAXNMA_64(Rt, Rn, Rs) /* LDFMINNMA ,
, [] (ffe0fc00/fca07000) */ //#define IEM_INSTR_IMPL_A64__LDFMINNMA_64(Rt, Rn, Rs) /* LDFADDAL ,
, [] (ffe0fc00/fce00000) */ //#define IEM_INSTR_IMPL_A64__LDFADDAL_64(Rt, Rn, Rs) /* LDFMAXAL ,
, [] (ffe0fc00/fce04000) */ //#define IEM_INSTR_IMPL_A64__LDFMAXAL_64(Rt, Rn, Rs) /* LDFMINAL ,
, [] (ffe0fc00/fce05000) */ //#define IEM_INSTR_IMPL_A64__LDFMINAL_64(Rt, Rn, Rs) /* LDFMAXNMAL ,
, [] (ffe0fc00/fce06000) */ //#define IEM_INSTR_IMPL_A64__LDFMAXNMAL_64(Rt, Rn, Rs) /* LDFMINNMAL ,
, [] (ffe0fc00/fce07000) */ //#define IEM_INSTR_IMPL_A64__LDFMINNMAL_64(Rt, Rn, Rs) /* * * Instruction Set & Groups: memop_128 / ldst / A64 * */ /* LDCLRP , , [] (ffe0fc00/19201000) */ //#define IEM_INSTR_IMPL_A64__LDCLRP_128_memop_128(Rt, Rn, Rt2) /* LDSETP , , [] (ffe0fc00/19203000) */ //#define IEM_INSTR_IMPL_A64__LDSETP_128_memop_128(Rt, Rn, Rt2) /* SWPP , , [] (ffe0fc00/19208000) */ //#define IEM_INSTR_IMPL_A64__SWPP_128_memop_128(Rt, Rn, Rt2) /* RCWCLRP , , [] (ffe0fc00/19209000) */ //#define IEM_INSTR_IMPL_A64__RCWCLRP_128_memop_128(Rt, Rn, Rt2) /* RCWSWPP , , [] (ffe0fc00/1920a000) */ //#define IEM_INSTR_IMPL_A64__RCWSWPP_128_memop_128(Rt, Rn, Rt2) /* RCWSETP , , [] (ffe0fc00/1920b000) */ //#define IEM_INSTR_IMPL_A64__RCWSETP_128_memop_128(Rt, Rn, Rt2) /* LDCLRPL , , [] (ffe0fc00/19601000) */ //#define IEM_INSTR_IMPL_A64__LDCLRPL_128_memop_128(Rt, Rn, Rt2) /* LDSETPL , , [] (ffe0fc00/19603000) */ //#define IEM_INSTR_IMPL_A64__LDSETPL_128_memop_128(Rt, Rn, Rt2) /* SWPPL , , [] (ffe0fc00/19608000) */ //#define IEM_INSTR_IMPL_A64__SWPPL_128_memop_128(Rt, Rn, Rt2) /* RCWCLRPL , , [] (ffe0fc00/19609000) */ //#define IEM_INSTR_IMPL_A64__RCWCLRPL_128_memop_128(Rt, Rn, Rt2) /* RCWSWPPL , , [] (ffe0fc00/1960a000) */ //#define IEM_INSTR_IMPL_A64__RCWSWPPL_128_memop_128(Rt, Rn, Rt2) /* RCWSETPL , , [] (ffe0fc00/1960b000) */ //#define IEM_INSTR_IMPL_A64__RCWSETPL_128_memop_128(Rt, Rn, Rt2) /* LDCLRPA , , [] (ffe0fc00/19a01000) */ //#define IEM_INSTR_IMPL_A64__LDCLRPA_128_memop_128(Rt, Rn, Rt2) /* LDSETPA , , [] (ffe0fc00/19a03000) */ //#define IEM_INSTR_IMPL_A64__LDSETPA_128_memop_128(Rt, Rn, Rt2) /* SWPPA , , [] (ffe0fc00/19a08000) */ //#define IEM_INSTR_IMPL_A64__SWPPA_128_memop_128(Rt, Rn, Rt2) /* RCWCLRPA , , [] (ffe0fc00/19a09000) */ //#define IEM_INSTR_IMPL_A64__RCWCLRPA_128_memop_128(Rt, Rn, Rt2) /* RCWSWPPA , , [] (ffe0fc00/19a0a000) */ //#define IEM_INSTR_IMPL_A64__RCWSWPPA_128_memop_128(Rt, Rn, Rt2) /* RCWSETPA , , [] (ffe0fc00/19a0b000) */ //#define IEM_INSTR_IMPL_A64__RCWSETPA_128_memop_128(Rt, Rn, Rt2) /* LDCLRPAL , , [] (ffe0fc00/19e01000) */ //#define IEM_INSTR_IMPL_A64__LDCLRPAL_128_memop_128(Rt, Rn, Rt2) /* LDSETPAL , , [] (ffe0fc00/19e03000) */ //#define IEM_INSTR_IMPL_A64__LDSETPAL_128_memop_128(Rt, Rn, Rt2) /* SWPPAL , , [] (ffe0fc00/19e08000) */ //#define IEM_INSTR_IMPL_A64__SWPPAL_128_memop_128(Rt, Rn, Rt2) /* RCWCLRPAL , , [] (ffe0fc00/19e09000) */ //#define IEM_INSTR_IMPL_A64__RCWCLRPAL_128_memop_128(Rt, Rn, Rt2) /* RCWSWPPAL , , [] (ffe0fc00/19e0a000) */ //#define IEM_INSTR_IMPL_A64__RCWSWPPAL_128_memop_128(Rt, Rn, Rt2) /* RCWSETPAL , , [] (ffe0fc00/19e0b000) */ //#define IEM_INSTR_IMPL_A64__RCWSETPAL_128_memop_128(Rt, Rn, Rt2) /* RCWSCLRP , , [] (ffe0fc00/59209000) */ //#define IEM_INSTR_IMPL_A64__RCWSCLRP_128_memop_128(Rt, Rn, Rt2) /* RCWSSWPP , , [] (ffe0fc00/5920a000) */ //#define IEM_INSTR_IMPL_A64__RCWSSWPP_128_memop_128(Rt, Rn, Rt2) /* RCWSSETP , , [] (ffe0fc00/5920b000) */ //#define IEM_INSTR_IMPL_A64__RCWSSETP_128_memop_128(Rt, Rn, Rt2) /* RCWSCLRPL , , [] (ffe0fc00/59609000) */ //#define IEM_INSTR_IMPL_A64__RCWSCLRPL_128_memop_128(Rt, Rn, Rt2) /* RCWSSWPPL , , [] (ffe0fc00/5960a000) */ //#define IEM_INSTR_IMPL_A64__RCWSSWPPL_128_memop_128(Rt, Rn, Rt2) /* RCWSSETPL , , [] (ffe0fc00/5960b000) */ //#define IEM_INSTR_IMPL_A64__RCWSSETPL_128_memop_128(Rt, Rn, Rt2) /* RCWSCLRPA , , [] (ffe0fc00/59a09000) */ //#define IEM_INSTR_IMPL_A64__RCWSCLRPA_128_memop_128(Rt, Rn, Rt2) /* RCWSSWPPA , , [] (ffe0fc00/59a0a000) */ //#define IEM_INSTR_IMPL_A64__RCWSSWPPA_128_memop_128(Rt, Rn, Rt2) /* RCWSSETPA , , [] (ffe0fc00/59a0b000) */ //#define IEM_INSTR_IMPL_A64__RCWSSETPA_128_memop_128(Rt, Rn, Rt2) /* RCWSCLRPAL , , [] (ffe0fc00/59e09000) */ //#define IEM_INSTR_IMPL_A64__RCWSCLRPAL_128_memop_128(Rt, Rn, Rt2) /* RCWSSWPPAL , , [] (ffe0fc00/59e0a000) */ //#define IEM_INSTR_IMPL_A64__RCWSSWPPAL_128_memop_128(Rt, Rn, Rt2) /* RCWSSETPAL , , [] (ffe0fc00/59e0b000) */ //#define IEM_INSTR_IMPL_A64__RCWSSETPAL_128_memop_128(Rt, Rn, Rt2) /* * * Instruction Set & Groups: memop_unpriv / ldst / A64 * */ /* LDTADD , , [] (ffe0fc00/19200400) */ //#define IEM_INSTR_IMPL_A64__LDTADD_32_memop_unpriv(Rt, Rn, Rs) /* LDTCLR , , [] (ffe0fc00/19201400) */ //#define IEM_INSTR_IMPL_A64__LDTCLR_32_memop_unpriv(Rt, Rn, Rs) /* LDTSET , , [] (ffe0fc00/19203400) */ //#define IEM_INSTR_IMPL_A64__LDTSET_32_memop_unpriv(Rt, Rn, Rs) /* SWPT , , [] (ffe0fc00/19208400) */ //#define IEM_INSTR_IMPL_A64__SWPT_32_memop_unpriv(Rt, Rn, Rs) /* LDTADDL , , [] (ffe0fc00/19600400) */ //#define IEM_INSTR_IMPL_A64__LDTADDL_32_memop_unpriv(Rt, Rn, Rs) /* LDTCLRL , , [] (ffe0fc00/19601400) */ //#define IEM_INSTR_IMPL_A64__LDTCLRL_32_memop_unpriv(Rt, Rn, Rs) /* LDTSETL , , [] (ffe0fc00/19603400) */ //#define IEM_INSTR_IMPL_A64__LDTSETL_32_memop_unpriv(Rt, Rn, Rs) /* SWPTL , , [] (ffe0fc00/19608400) */ //#define IEM_INSTR_IMPL_A64__SWPTL_32_memop_unpriv(Rt, Rn, Rs) /* LDTADDA , , [] (ffe0fc00/19a00400) */ //#define IEM_INSTR_IMPL_A64__LDTADDA_32_memop_unpriv(Rt, Rn, Rs) /* LDTCLRA , , [] (ffe0fc00/19a01400) */ //#define IEM_INSTR_IMPL_A64__LDTCLRA_32_memop_unpriv(Rt, Rn, Rs) /* LDTSETA , , [] (ffe0fc00/19a03400) */ //#define IEM_INSTR_IMPL_A64__LDTSETA_32_memop_unpriv(Rt, Rn, Rs) /* SWPTA , , [] (ffe0fc00/19a08400) */ //#define IEM_INSTR_IMPL_A64__SWPTA_32_memop_unpriv(Rt, Rn, Rs) /* LDTADDAL , , [] (ffe0fc00/19e00400) */ //#define IEM_INSTR_IMPL_A64__LDTADDAL_32_memop_unpriv(Rt, Rn, Rs) /* LDTCLRAL , , [] (ffe0fc00/19e01400) */ //#define IEM_INSTR_IMPL_A64__LDTCLRAL_32_memop_unpriv(Rt, Rn, Rs) /* LDTSETAL , , [] (ffe0fc00/19e03400) */ //#define IEM_INSTR_IMPL_A64__LDTSETAL_32_memop_unpriv(Rt, Rn, Rs) /* SWPTAL , , [] (ffe0fc00/19e08400) */ //#define IEM_INSTR_IMPL_A64__SWPTAL_32_memop_unpriv(Rt, Rn, Rs) /* LDTADD , , [] (ffe0fc00/59200400) */ //#define IEM_INSTR_IMPL_A64__LDTADD_64_memop_unpriv(Rt, Rn, Rs) /* LDTCLR , , [] (ffe0fc00/59201400) */ //#define IEM_INSTR_IMPL_A64__LDTCLR_64_memop_unpriv(Rt, Rn, Rs) /* LDTSET , , [] (ffe0fc00/59203400) */ //#define IEM_INSTR_IMPL_A64__LDTSET_64_memop_unpriv(Rt, Rn, Rs) /* SWPT , , [] (ffe0fc00/59208400) */ //#define IEM_INSTR_IMPL_A64__SWPT_64_memop_unpriv(Rt, Rn, Rs) /* LDTADDL , , [] (ffe0fc00/59600400) */ //#define IEM_INSTR_IMPL_A64__LDTADDL_64_memop_unpriv(Rt, Rn, Rs) /* LDTCLRL , , [] (ffe0fc00/59601400) */ //#define IEM_INSTR_IMPL_A64__LDTCLRL_64_memop_unpriv(Rt, Rn, Rs) /* LDTSETL , , [] (ffe0fc00/59603400) */ //#define IEM_INSTR_IMPL_A64__LDTSETL_64_memop_unpriv(Rt, Rn, Rs) /* SWPTL , , [] (ffe0fc00/59608400) */ //#define IEM_INSTR_IMPL_A64__SWPTL_64_memop_unpriv(Rt, Rn, Rs) /* LDTADDA , , [] (ffe0fc00/59a00400) */ //#define IEM_INSTR_IMPL_A64__LDTADDA_64_memop_unpriv(Rt, Rn, Rs) /* LDTCLRA , , [] (ffe0fc00/59a01400) */ //#define IEM_INSTR_IMPL_A64__LDTCLRA_64_memop_unpriv(Rt, Rn, Rs) /* LDTSETA , , [] (ffe0fc00/59a03400) */ //#define IEM_INSTR_IMPL_A64__LDTSETA_64_memop_unpriv(Rt, Rn, Rs) /* SWPTA , , [] (ffe0fc00/59a08400) */ //#define IEM_INSTR_IMPL_A64__SWPTA_64_memop_unpriv(Rt, Rn, Rs) /* LDTADDAL , , [] (ffe0fc00/59e00400) */ //#define IEM_INSTR_IMPL_A64__LDTADDAL_64_memop_unpriv(Rt, Rn, Rs) /* LDTCLRAL , , [] (ffe0fc00/59e01400) */ //#define IEM_INSTR_IMPL_A64__LDTCLRAL_64_memop_unpriv(Rt, Rn, Rs) /* LDTSETAL , , [] (ffe0fc00/59e03400) */ //#define IEM_INSTR_IMPL_A64__LDTSETAL_64_memop_unpriv(Rt, Rn, Rs) /* SWPTAL , , [] (ffe0fc00/59e08400) */ //#define IEM_INSTR_IMPL_A64__SWPTAL_64_memop_unpriv(Rt, Rn, Rs) /* * * Instruction Set & Groups: minmax_imm / dpimm / A64 * */ /* SMAX , , # (fffc0000/11c00000) */ //#define IEM_INSTR_IMPL_A64__SMAX_32_minmax_imm(Rd, Rn, imm8) /* UMAX , , # (fffc0000/11c40000) */ //#define IEM_INSTR_IMPL_A64__UMAX_32U_minmax_imm(Rd, Rn, imm8) /* SMIN , , # (fffc0000/11c80000) */ //#define IEM_INSTR_IMPL_A64__SMIN_32_minmax_imm(Rd, Rn, imm8) /* UMIN , , # (fffc0000/11cc0000) */ //#define IEM_INSTR_IMPL_A64__UMIN_32U_minmax_imm(Rd, Rn, imm8) /* SMAX , , # (fffc0000/91c00000) */ //#define IEM_INSTR_IMPL_A64__SMAX_64_minmax_imm(Rd, Rn, imm8) /* UMAX , , # (fffc0000/91c40000) */ //#define IEM_INSTR_IMPL_A64__UMAX_64U_minmax_imm(Rd, Rn, imm8) /* SMIN , , # (fffc0000/91c80000) */ //#define IEM_INSTR_IMPL_A64__SMIN_64_minmax_imm(Rd, Rn, imm8) /* UMIN , , # (fffc0000/91cc0000) */ //#define IEM_INSTR_IMPL_A64__UMIN_64U_minmax_imm(Rd, Rn, imm8) /* * * Instruction Set & Groups: miscbranch / control / A64 * */ /* RETAASPPC
, , . (ff3fe000/04002000) */ //#define IEM_INSTR_IMPL_A64__saddv_r_p_z(Vd, Zn, Pg, size) /* UADDV
, , . (ff3fe000/04012000) */ //#define IEM_INSTR_IMPL_A64__uaddv_r_p_z(Vd, Zn, Pg, size) /* * * Instruction Set & Groups: sve_int_reduce_0q / sve_int_pred_red / sve / A64 * */ /* ADDQV ., , . (ff3fe000/04052000) */ //#define IEM_INSTR_IMPL_A64__addqv_z_p_z(Vd, Zn, Pg, size) /* * * Instruction Set & Groups: sve_int_reduce_1 / sve_int_pred_red / sve / A64 * */ /* SMAXV , , . (ff3fe000/04082000) */ //#define IEM_INSTR_IMPL_A64__smaxv_r_p_z(Vd, Zn, Pg, U, size) /* SMINV , , . (ff3fe000/040a2000) */ //#define IEM_INSTR_IMPL_A64__sminv_r_p_z(Vd, Zn, Pg, U, size) /* UMAXV , , . (ff3fe000/04092000) */ //#define IEM_INSTR_IMPL_A64__umaxv_r_p_z(Vd, Zn, Pg, U, size) /* UMINV , , . (ff3fe000/040b2000) */ //#define IEM_INSTR_IMPL_A64__uminv_r_p_z(Vd, Zn, Pg, U, size) /* * * Instruction Set & Groups: sve_int_reduce_1q / sve_int_pred_red / sve / A64 * */ /* SMAXQV ., , . (ff3fe000/040c2000) */ //#define IEM_INSTR_IMPL_A64__smaxqv_z_p_z(Vd, Zn, Pg, U, size) /* SMINQV ., , . (ff3fe000/040e2000) */ //#define IEM_INSTR_IMPL_A64__sminqv_z_p_z(Vd, Zn, Pg, U, size) /* UMAXQV ., , . (ff3fe000/040d2000) */ //#define IEM_INSTR_IMPL_A64__umaxqv_z_p_z(Vd, Zn, Pg, U, size) /* UMINQV ., , . (ff3fe000/040f2000) */ //#define IEM_INSTR_IMPL_A64__uminqv_z_p_z(Vd, Zn, Pg, U, size) /* * * Instruction Set & Groups: sve_int_reduce_2 / sve_int_pred_red / sve / A64 * */ /* ORV , , . (ff3fe000/04182000) */ //#define IEM_INSTR_IMPL_A64__orv_r_p_z(Vd, Zn, Pg, size) /* EORV , , . (ff3fe000/04192000) */ //#define IEM_INSTR_IMPL_A64__eorv_r_p_z(Vd, Zn, Pg, size) /* ANDV , , . (ff3fe000/041a2000) */ //#define IEM_INSTR_IMPL_A64__andv_r_p_z(Vd, Zn, Pg, size) /* * * Instruction Set & Groups: sve_int_reduce_2q / sve_int_pred_red / sve / A64 * */ /* ORQV ., , . (ff3fe000/041c2000) */ //#define IEM_INSTR_IMPL_A64__orqv_z_p_z(Vd, Zn, Pg, size) /* EORQV ., , . (ff3fe000/041d2000) */ //#define IEM_INSTR_IMPL_A64__eorqv_z_p_z(Vd, Zn, Pg, size) /* ANDQV ., , . (ff3fe000/041e2000) */ //#define IEM_INSTR_IMPL_A64__andqv_z_p_z(Vd, Zn, Pg, size) /* * * Instruction Set & Groups: sve_int_rotate_imm / sve_int_unpred_logical / sve / A64 * */ /* XAR ., ., ., # (ff20fc00/04203400) */ //#define IEM_INSTR_IMPL_A64__xar_z_zzi(Zdn, Zm, imm3, tszl, tszh) /* * * Instruction Set & Groups: sve_int_scmp_vi / sve_cmpsimm / sve / A64 * */ /* CMPGE ., /Z, ., # (ff20e010/25000000) */ //#define IEM_INSTR_IMPL_A64__cmpge_p_p_zi(Pd, ne, Zn, Pg, lt, imm5, size) /* CMPEQ ., /Z, ., # (ff20e010/25008000) */ //#define IEM_INSTR_IMPL_A64__cmpeq_p_p_zi(Pd, ne, Zn, Pg, imm5, size) /* CMPLT ., /Z, ., # (ff20e010/25002000) */ //#define IEM_INSTR_IMPL_A64__cmplt_p_p_zi(Pd, ne, Zn, Pg, lt, imm5, size) /* CMPGT ., /Z, ., # (ff20e010/25000010) */ //#define IEM_INSTR_IMPL_A64__cmpgt_p_p_zi(Pd, ne, Zn, Pg, lt, imm5, size) /* CMPNE ., /Z, ., # (ff20e010/25008010) */ //#define IEM_INSTR_IMPL_A64__cmpne_p_p_zi(Pd, ne, Zn, Pg, imm5, size) /* CMPLE ., /Z, ., # (ff20e010/25002010) */ //#define IEM_INSTR_IMPL_A64__cmple_p_p_zi(Pd, ne, Zn, Pg, lt, imm5, size) /* * * Instruction Set & Groups: sve_int_sel_vvv / sve_int_select / sve / A64 * */ /* SEL ., , ., . (ff20c000/0520c000) */ //#define IEM_INSTR_IMPL_A64__sel_z_p_zz(Zd, Zn, Pv, Zm, size) /* * * Instruction Set & Groups: sve_int_setffr / sve_pred_wrffr / sve / A64 * */ /* SETFFR (ffffffff/252c9000) */ //#define IEM_INSTR_IMPL_A64__setffr_f() /* * * Instruction Set & Groups: sve_int_sqdmulh / sve_int_unpred_arit_b / sve / A64 * */ /* SQDMULH ., ., . (ff20fc00/04207000) */ //#define IEM_INSTR_IMPL_A64__sqdmulh_z_zz(Zd, Zn, Zm, size) /* SQRDMULH ., ., . (ff20fc00/04207400) */ //#define IEM_INSTR_IMPL_A64__sqrdmulh_z_zz(Zd, Zn, Zm, size) /* * * Instruction Set & Groups: sve_int_tern_log / sve_int_unpred_logical / sve / A64 * */ /* EOR3 .D, .D, .D, .D (ffe0fc00/04203800) */ //#define IEM_INSTR_IMPL_A64__eor3_z_zzz(Zdn, Zk, Zm) /* BCAX .D, .D, .D, .D (ffe0fc00/04603800) */ //#define IEM_INSTR_IMPL_A64__bcax_z_zzz(Zdn, Zk, Zm) /* BSL .D, .D, .D, .D (ffe0fc00/04203c00) */ //#define IEM_INSTR_IMPL_A64__bsl_z_zzz(Zdn, Zk, Zm) /* BSL1N .D, .D, .D, .D (ffe0fc00/04603c00) */ //#define IEM_INSTR_IMPL_A64__bsl1n_z_zzz(Zdn, Zk, Zm) /* BSL2N .D, .D, .D, .D (ffe0fc00/04a03c00) */ //#define IEM_INSTR_IMPL_A64__bsl2n_z_zzz(Zdn, Zk, Zm) /* NBSL .D, .D, .D, .D (ffe0fc00/04e03c00) */ //#define IEM_INSTR_IMPL_A64__nbsl_z_zzz(Zdn, Zk, Zm) /* * * Instruction Set & Groups: sve_int_ucmp_vi / sve_cmpuimm / sve / A64 * */ /* CMPHS ., /Z, ., # (ff202010/24200000) */ //#define IEM_INSTR_IMPL_A64__cmphs_p_p_zi(Pd, ne, Zn, Pg, lt, imm7, size) /* CMPHI ., /Z, ., # (ff202010/24200010) */ //#define IEM_INSTR_IMPL_A64__cmphi_p_p_zi(Pd, ne, Zn, Pg, lt, imm7, size) /* CMPLO ., /Z, ., # (ff202010/24202000) */ //#define IEM_INSTR_IMPL_A64__cmplo_p_p_zi(Pd, ne, Zn, Pg, lt, imm7, size) /* CMPLS ., /Z, ., # (ff202010/24202010) */ //#define IEM_INSTR_IMPL_A64__cmpls_p_p_zi(Pd, ne, Zn, Pg, lt, imm7, size) /* * * Instruction Set & Groups: sve_int_un_pred_arit_0 / sve_int_pred_un / sve / A64 * */ /* ABS ., /M, . (ff3fe000/0416a000) */ //#define IEM_INSTR_IMPL_A64__abs_z_p_z_m(Zd, Zn, Pg, size) /* ABS ., /Z, . (ff3fe000/0406a000) */ //#define IEM_INSTR_IMPL_A64__abs_z_p_z_z(Zd, Zn, Pg, size) /* NEG ., /M, . (ff3fe000/0417a000) */ //#define IEM_INSTR_IMPL_A64__neg_z_p_z_m(Zd, Zn, Pg, size) /* NEG ., /Z, . (ff3fe000/0407a000) */ //#define IEM_INSTR_IMPL_A64__neg_z_p_z_z(Zd, Zn, Pg, size) /* SXTW .D, /M, .D (ff3fe000/0414a000) */ //#define IEM_INSTR_IMPL_A64__sxtw_z_p_z_m(Zd, Zn, Pg, U, size) /* SXTW .D, /Z, .D (ff3fe000/0404a000) */ //#define IEM_INSTR_IMPL_A64__sxtw_z_p_z_z(Zd, Zn, Pg, U, size) /* SXTH ., /M, . (ff3fe000/0412a000) */ //#define IEM_INSTR_IMPL_A64__sxth_z_p_z_m(Zd, Zn, Pg, U, size) /* SXTH ., /Z, . (ff3fe000/0402a000) */ //#define IEM_INSTR_IMPL_A64__sxth_z_p_z_z(Zd, Zn, Pg, U, size) /* SXTB ., /M, . (ff3fe000/0410a000) */ //#define IEM_INSTR_IMPL_A64__sxtb_z_p_z_m(Zd, Zn, Pg, U, size) /* SXTB ., /Z, . (ff3fe000/0400a000) */ //#define IEM_INSTR_IMPL_A64__sxtb_z_p_z_z(Zd, Zn, Pg, U, size) /* UXTW .D, /M, .D (ff3fe000/0415a000) */ //#define IEM_INSTR_IMPL_A64__uxtw_z_p_z_m(Zd, Zn, Pg, U, size) /* UXTW .D, /Z, .D (ff3fe000/0405a000) */ //#define IEM_INSTR_IMPL_A64__uxtw_z_p_z_z(Zd, Zn, Pg, U, size) /* UXTH ., /M, . (ff3fe000/0413a000) */ //#define IEM_INSTR_IMPL_A64__uxth_z_p_z_m(Zd, Zn, Pg, U, size) /* UXTH ., /Z, . (ff3fe000/0403a000) */ //#define IEM_INSTR_IMPL_A64__uxth_z_p_z_z(Zd, Zn, Pg, U, size) /* UXTB ., /M, . (ff3fe000/0411a000) */ //#define IEM_INSTR_IMPL_A64__uxtb_z_p_z_m(Zd, Zn, Pg, U, size) /* UXTB ., /Z, . (ff3fe000/0401a000) */ //#define IEM_INSTR_IMPL_A64__uxtb_z_p_z_z(Zd, Zn, Pg, U, size) /* * * Instruction Set & Groups: sve_int_un_pred_arit_1 / sve_int_pred_un / sve / A64 * */ /* CLS ., /M, . (ff3fe000/0418a000) */ //#define IEM_INSTR_IMPL_A64__cls_z_p_z_m(Zd, Zn, Pg, size) /* CLS ., /Z, . (ff3fe000/0408a000) */ //#define IEM_INSTR_IMPL_A64__cls_z_p_z_z(Zd, Zn, Pg, size) /* CLZ ., /M, . (ff3fe000/0419a000) */ //#define IEM_INSTR_IMPL_A64__clz_z_p_z_m(Zd, Zn, Pg, size) /* CLZ ., /Z, . (ff3fe000/0409a000) */ //#define IEM_INSTR_IMPL_A64__clz_z_p_z_z(Zd, Zn, Pg, size) /* CNT ., /M, . (ff3fe000/041aa000) */ //#define IEM_INSTR_IMPL_A64__cnt_z_p_z_m(Zd, Zn, Pg, size) /* CNT ., /Z, . (ff3fe000/040aa000) */ //#define IEM_INSTR_IMPL_A64__cnt_z_p_z_z(Zd, Zn, Pg, size) /* CNOT ., /M, . (ff3fe000/041ba000) */ //#define IEM_INSTR_IMPL_A64__cnot_z_p_z_m(Zd, Zn, Pg, size) /* CNOT ., /Z, . (ff3fe000/040ba000) */ //#define IEM_INSTR_IMPL_A64__cnot_z_p_z_z(Zd, Zn, Pg, size) /* FABS ., /M, . (ff3fe000/041ca000) */ //#define IEM_INSTR_IMPL_A64__fabs_z_p_z_m(Zd, Zn, Pg, size) /* FABS ., /Z, . (ff3fe000/040ca000) */ //#define IEM_INSTR_IMPL_A64__fabs_z_p_z_z(Zd, Zn, Pg, size) /* FNEG ., /M, . (ff3fe000/041da000) */ //#define IEM_INSTR_IMPL_A64__fneg_z_p_z_m(Zd, Zn, Pg, size) /* FNEG ., /Z, . (ff3fe000/040da000) */ //#define IEM_INSTR_IMPL_A64__fneg_z_p_z_z(Zd, Zn, Pg, size) /* NOT ., /M, . (ff3fe000/041ea000) */ //#define IEM_INSTR_IMPL_A64__not_z_p_z_m(Zd, Zn, Pg, size) /* NOT ., /Z, . (ff3fe000/040ea000) */ //#define IEM_INSTR_IMPL_A64__not_z_p_z_z(Zd, Zn, Pg, size) /* * * Instruction Set & Groups: sve_int_while_rr / sve_cmpgpr / sve / A64 * */ /* WHILEGE ., , (ff20ec10/25200000) */ //#define IEM_INSTR_IMPL_A64__whilege_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size) /* WHILEHS ., , (ff20ec10/25200800) */ //#define IEM_INSTR_IMPL_A64__whilehs_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size) /* WHILEGT ., , (ff20ec10/25200010) */ //#define IEM_INSTR_IMPL_A64__whilegt_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size) /* WHILEHI ., , (ff20ec10/25200810) */ //#define IEM_INSTR_IMPL_A64__whilehi_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size) /* WHILELT ., , (ff20ec10/25200400) */ //#define IEM_INSTR_IMPL_A64__whilelt_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size) /* WHILELO ., , (ff20ec10/25200c00) */ //#define IEM_INSTR_IMPL_A64__whilelo_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size) /* WHILELE ., , (ff20ec10/25200410) */ //#define IEM_INSTR_IMPL_A64__whilele_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size) /* WHILELS ., , (ff20ec10/25200c10) */ //#define IEM_INSTR_IMPL_A64__whilels_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size) /* * * Instruction Set & Groups: sve_int_while_rr_pair / sve_while_pn / sve / A64 * */ /* WHILEGE { ., . }, , (ff20fc11/25205010) */ //#define IEM_INSTR_IMPL_A64__whilege_pp_rr(eq, Pd, Rn, lt, Rm, size) /* WHILEHS { ., . }, , (ff20fc11/25205810) */ //#define IEM_INSTR_IMPL_A64__whilehs_pp_rr(eq, Pd, Rn, lt, Rm, size) /* WHILEGT { ., . }, , (ff20fc11/25205011) */ //#define IEM_INSTR_IMPL_A64__whilegt_pp_rr(eq, Pd, Rn, lt, Rm, size) /* WHILEHI { ., . }, , (ff20fc11/25205811) */ //#define IEM_INSTR_IMPL_A64__whilehi_pp_rr(eq, Pd, Rn, lt, Rm, size) /* WHILELT { ., . }, , (ff20fc11/25205410) */ //#define IEM_INSTR_IMPL_A64__whilelt_pp_rr(eq, Pd, Rn, lt, Rm, size) /* WHILELO { ., . }, , (ff20fc11/25205c10) */ //#define IEM_INSTR_IMPL_A64__whilelo_pp_rr(eq, Pd, Rn, lt, Rm, size) /* WHILELE { ., . }, , (ff20fc11/25205411) */ //#define IEM_INSTR_IMPL_A64__whilele_pp_rr(eq, Pd, Rn, lt, Rm, size) /* WHILELS { ., . }, , (ff20fc11/25205c11) */ //#define IEM_INSTR_IMPL_A64__whilels_pp_rr(eq, Pd, Rn, lt, Rm, size) /* * * Instruction Set & Groups: sve_int_while_rr_pn / sve_while_pn / sve / A64 * */ /* WHILEGE ., , , (ff20dc18/25204010) */ //#define IEM_INSTR_IMPL_A64__whilege_pn_rr(PNd, eq, Rn, lt, vl, Rm, size) /* WHILEHS ., , , (ff20dc18/25204810) */ //#define IEM_INSTR_IMPL_A64__whilehs_pn_rr(PNd, eq, Rn, lt, vl, Rm, size) /* WHILEGT ., , , (ff20dc18/25204018) */ //#define IEM_INSTR_IMPL_A64__whilegt_pn_rr(PNd, eq, Rn, lt, vl, Rm, size) /* WHILEHI ., , , (ff20dc18/25204818) */ //#define IEM_INSTR_IMPL_A64__whilehi_pn_rr(PNd, eq, Rn, lt, vl, Rm, size) /* WHILELT ., , , (ff20dc18/25204410) */ //#define IEM_INSTR_IMPL_A64__whilelt_pn_rr(PNd, eq, Rn, lt, vl, Rm, size) /* WHILELO ., , , (ff20dc18/25204c10) */ //#define IEM_INSTR_IMPL_A64__whilelo_pn_rr(PNd, eq, Rn, lt, vl, Rm, size) /* WHILELE ., , , (ff20dc18/25204418) */ //#define IEM_INSTR_IMPL_A64__whilele_pn_rr(PNd, eq, Rn, lt, vl, Rm, size) /* WHILELS ., , , (ff20dc18/25204c18) */ //#define IEM_INSTR_IMPL_A64__whilels_pn_rr(PNd, eq, Rn, lt, vl, Rm, size) /* * * Instruction Set & Groups: sve_int_whilenc / sve_cmpgpr / sve / A64 * */ /* WHILEWR ., , (ff20fc10/25203000) */ //#define IEM_INSTR_IMPL_A64__whilewr_p_rr(Pd, Rn, Rm, size) /* WHILERW ., , (ff20fc10/25203010) */ //#define IEM_INSTR_IMPL_A64__whilerw_p_rr(Pd, Rn, Rm, size) /* * * Instruction Set & Groups: sve_int_wrffr / sve_pred_wrffr / sve / A64 * */ /* WRFFR .B (fffffe1f/25289000) */ //#define IEM_INSTR_IMPL_A64__wrffr_f_p(Pn) /* * * Instruction Set & Groups: sve_intx_aba / sve_intx_acc / sve / A64 * */ /* SABA ., ., . (ff20fc00/4500f800) */ //#define IEM_INSTR_IMPL_A64__saba_z_zzz(Zda, Zn, U, Zm, size) /* UABA ., ., . (ff20fc00/4500fc00) */ //#define IEM_INSTR_IMPL_A64__uaba_z_zzz(Zda, Zn, U, Zm, size) /* * * Instruction Set & Groups: sve_intx_aba_long / sve_intx_acc / sve / A64 * */ /* SABALB ., ., . (ff20fc00/4500c000) */ //#define IEM_INSTR_IMPL_A64__sabalb_z_zzz(Zda, Zn, T, U, Zm, size) /* SABALT ., ., . (ff20fc00/4500c400) */ //#define IEM_INSTR_IMPL_A64__sabalt_z_zzz(Zda, Zn, T, U, Zm, size) /* UABALB ., ., . (ff20fc00/4500c800) */ //#define IEM_INSTR_IMPL_A64__uabalb_z_zzz(Zda, Zn, T, U, Zm, size) /* UABALT ., ., . (ff20fc00/4500cc00) */ //#define IEM_INSTR_IMPL_A64__uabalt_z_zzz(Zda, Zn, T, U, Zm, size) /* * * Instruction Set & Groups: sve_intx_accumulate_long_pairs / sve_intx_predicated / sve / A64 * */ /* SADALP ., /M, . (ff3fe000/4404a000) */ //#define IEM_INSTR_IMPL_A64__sadalp_z_p_z(Zda, Zn, Pg, U, size) /* UADALP ., /M, . (ff3fe000/4405a000) */ //#define IEM_INSTR_IMPL_A64__uadalp_z_p_z(Zda, Zn, Pg, U, size) /* * * Instruction Set & Groups: sve_intx_adc_long / sve_intx_acc / sve / A64 * */ /* ADCLB ., ., . (ffa0fc00/4500d000) */ //#define IEM_INSTR_IMPL_A64__adclb_z_zzz(Zda, Zn, T, Zm, sz) /* SBCLB ., ., . (ffa0fc00/4580d000) */ //#define IEM_INSTR_IMPL_A64__sbclb_z_zzz(Zda, Zn, T, Zm, sz) /* ADCLT ., ., . (ffa0fc00/4500d400) */ //#define IEM_INSTR_IMPL_A64__adclt_z_zzz(Zda, Zn, T, Zm, sz) /* SBCLT ., ., . (ffa0fc00/4580d400) */ //#define IEM_INSTR_IMPL_A64__sbclt_z_zzz(Zda, Zn, T, Zm, sz) /* * * Instruction Set & Groups: sve_intx_arith_binary_pairs / sve_intx_predicated / sve / A64 * */ /* ADDP ., /M, ., . (ff3fe000/4411a000) */ //#define IEM_INSTR_IMPL_A64__addp_z_p_zz(Zdn, Zm, Pg, size) /* SMAXP ., /M, ., . (ff3fe000/4414a000) */ //#define IEM_INSTR_IMPL_A64__smaxp_z_p_zz(Zdn, Zm, Pg, U, size) /* SMINP ., /M, ., . (ff3fe000/4416a000) */ //#define IEM_INSTR_IMPL_A64__sminp_z_p_zz(Zdn, Zm, Pg, U, size) /* UMAXP ., /M, ., . (ff3fe000/4415a000) */ //#define IEM_INSTR_IMPL_A64__umaxp_z_p_zz(Zdn, Zm, Pg, U, size) /* UMINP ., /M, ., . (ff3fe000/4417a000) */ //#define IEM_INSTR_IMPL_A64__uminp_z_p_zz(Zdn, Zm, Pg, U, size) /* * * Instruction Set & Groups: sve_intx_arith_narrow / sve_intx_narrowing / sve / A64 * */ /* ADDHNB ., ., . (ff20fc00/45206000) */ //#define IEM_INSTR_IMPL_A64__addhnb_z_zz(Zd, Zn, T, Zm, size) /* RADDHNB ., ., . (ff20fc00/45206800) */ //#define IEM_INSTR_IMPL_A64__raddhnb_z_zz(Zd, Zn, T, Zm, size) /* SUBHNB ., ., . (ff20fc00/45207000) */ //#define IEM_INSTR_IMPL_A64__subhnb_z_zz(Zd, Zn, T, Zm, size) /* RSUBHNB ., ., . (ff20fc00/45207800) */ //#define IEM_INSTR_IMPL_A64__rsubhnb_z_zz(Zd, Zn, T, Zm, size) /* ADDHNT ., ., . (ff20fc00/45206400) */ //#define IEM_INSTR_IMPL_A64__addhnt_z_zz(Zd, Zn, T, Zm, size) /* RADDHNT ., ., . (ff20fc00/45206c00) */ //#define IEM_INSTR_IMPL_A64__raddhnt_z_zz(Zd, Zn, T, Zm, size) /* SUBHNT ., ., . (ff20fc00/45207400) */ //#define IEM_INSTR_IMPL_A64__subhnt_z_zz(Zd, Zn, T, Zm, size) /* RSUBHNT ., ., . (ff20fc00/45207c00) */ //#define IEM_INSTR_IMPL_A64__rsubhnt_z_zz(Zd, Zn, T, Zm, size) /* * * Instruction Set & Groups: sve_intx_bin_pred_shift_sat_round / sve_intx_predicated / sve / A64 * */ /* SRSHL ., /M, ., . (ff3fe000/44028000) */ //#define IEM_INSTR_IMPL_A64__srshl_z_p_zz(Zdn, Zm, Pg, U, size) /* SRSHLR ., /M, ., . (ff3fe000/44068000) */ //#define IEM_INSTR_IMPL_A64__srshlr_z_p_zz(Zdn, Zm, Pg, U, size) /* SQSHL ., /M, ., . (ff3fe000/44088000) */ //#define IEM_INSTR_IMPL_A64__sqshl_z_p_zz(Zdn, Zm, Pg, U, size) /* SQRSHL ., /M, ., . (ff3fe000/440a8000) */ //#define IEM_INSTR_IMPL_A64__sqrshl_z_p_zz(Zdn, Zm, Pg, U, size) /* SQSHLR ., /M, ., . (ff3fe000/440c8000) */ //#define IEM_INSTR_IMPL_A64__sqshlr_z_p_zz(Zdn, Zm, Pg, U, size) /* SQRSHLR ., /M, ., . (ff3fe000/440e8000) */ //#define IEM_INSTR_IMPL_A64__sqrshlr_z_p_zz(Zdn, Zm, Pg, U, size) /* URSHL ., /M, ., . (ff3fe000/44038000) */ //#define IEM_INSTR_IMPL_A64__urshl_z_p_zz(Zdn, Zm, Pg, U, size) /* URSHLR ., /M, ., . (ff3fe000/44078000) */ //#define IEM_INSTR_IMPL_A64__urshlr_z_p_zz(Zdn, Zm, Pg, U, size) /* UQSHL ., /M, ., . (ff3fe000/44098000) */ //#define IEM_INSTR_IMPL_A64__uqshl_z_p_zz(Zdn, Zm, Pg, U, size) /* UQRSHL ., /M, ., . (ff3fe000/440b8000) */ //#define IEM_INSTR_IMPL_A64__uqrshl_z_p_zz(Zdn, Zm, Pg, U, size) /* UQSHLR ., /M, ., . (ff3fe000/440d8000) */ //#define IEM_INSTR_IMPL_A64__uqshlr_z_p_zz(Zdn, Zm, Pg, U, size) /* UQRSHLR ., /M, ., . (ff3fe000/440f8000) */ //#define IEM_INSTR_IMPL_A64__uqrshlr_z_p_zz(Zdn, Zm, Pg, U, size) /* * * Instruction Set & Groups: sve_intx_cadd / sve_intx_acc / sve / A64 * */ /* CADD ., ., ., (ff3ff800/4500d800) */ //#define IEM_INSTR_IMPL_A64__cadd_z_zz(Zdn, Zm, rot, size) /* SQCADD ., ., ., (ff3ff800/4501d800) */ //#define IEM_INSTR_IMPL_A64__sqcadd_z_zz(Zdn, Zm, rot, size) /* * * Instruction Set & Groups: sve_intx_cdot / sve_intx_muladd_unpred / sve / A64 * */ /* CDOT ., ., ., (ff20f000/44001000) */ //#define IEM_INSTR_IMPL_A64__cdot_z_zzz(Zda, Zn, rot, Zm, size) /* * * Instruction Set & Groups: sve_intx_cdot_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* CDOT .S, .B, .B[], (ffe0f000/44a04000) */ //#define IEM_INSTR_IMPL_A64__cdot_z_zzzi_s(Zda, Zn, rot, Zm, i2) /* CDOT .D, .H, .H[], (ffe0f000/44e04000) */ //#define IEM_INSTR_IMPL_A64__cdot_z_zzzi_d(Zda, Zn, rot, Zm, i1) /* * * Instruction Set & Groups: sve_intx_clamp_lvl2 / sve_intx_clamp / sve / A64 * */ /* SCLAMP ., ., . (ff20fc00/4400c000) */ //#define IEM_INSTR_IMPL_A64__sclamp_z_zz(Zd, Zn, Zm, size) /* UCLAMP ., ., . (ff20fc00/4400c400) */ //#define IEM_INSTR_IMPL_A64__uclamp_z_zz(Zd, Zn, Zm, size) /* * * Instruction Set & Groups: sve_intx_clong / sve_intx_constructive / sve / A64 * */ /* SADDLBT ., ., . (ff20fc00/45008000) */ //#define IEM_INSTR_IMPL_A64__saddlbt_z_zz(Zd, Zn, Zm, size) /* SSUBLBT ., ., . (ff20fc00/45008800) */ //#define IEM_INSTR_IMPL_A64__ssublbt_z_zz(Zd, Zn, Zm, size) /* SSUBLTB ., ., . (ff20fc00/45008c00) */ //#define IEM_INSTR_IMPL_A64__ssubltb_z_zz(Zd, Zn, Zm, size) /* * * Instruction Set & Groups: sve_intx_cmla / sve_intx_muladd_unpred / sve / A64 * */ /* CMLA ., ., ., (ff20f000/44002000) */ //#define IEM_INSTR_IMPL_A64__cmla_z_zzz(Zda, Zn, rot, Zm, size) /* SQRDCMLAH ., ., ., (ff20f000/44003000) */ //#define IEM_INSTR_IMPL_A64__sqrdcmlah_z_zzz(Zda, Zn, rot, Zm, size) /* * * Instruction Set & Groups: sve_intx_cmla_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* CMLA .H, .H, .H[], (ffe0f000/44a06000) */ //#define IEM_INSTR_IMPL_A64__cmla_z_zzzi_h(Zda, Zn, rot, Zm, i2) /* CMLA .S, .S, .S[], (ffe0f000/44e06000) */ //#define IEM_INSTR_IMPL_A64__cmla_z_zzzi_s(Zda, Zn, rot, Zm, i1) /* * * Instruction Set & Groups: sve_intx_cons_arith_long / sve_intx_cons_widening / sve / A64 * */ /* SADDLB ., ., . (ff20fc00/45000000) */ //#define IEM_INSTR_IMPL_A64__saddlb_z_zz(Zd, Zn, T, U, Zm, size) /* SSUBLB ., ., . (ff20fc00/45001000) */ //#define IEM_INSTR_IMPL_A64__ssublb_z_zz(Zd, Zn, T, U, Zm, size) /* SABDLB ., ., . (ff20fc00/45003000) */ //#define IEM_INSTR_IMPL_A64__sabdlb_z_zz(Zd, Zn, T, U, Zm, size) /* SADDLT ., ., . (ff20fc00/45000400) */ //#define IEM_INSTR_IMPL_A64__saddlt_z_zz(Zd, Zn, T, U, Zm, size) /* SSUBLT ., ., . (ff20fc00/45001400) */ //#define IEM_INSTR_IMPL_A64__ssublt_z_zz(Zd, Zn, T, U, Zm, size) /* SABDLT ., ., . (ff20fc00/45003400) */ //#define IEM_INSTR_IMPL_A64__sabdlt_z_zz(Zd, Zn, T, U, Zm, size) /* UADDLB ., ., . (ff20fc00/45000800) */ //#define IEM_INSTR_IMPL_A64__uaddlb_z_zz(Zd, Zn, T, U, Zm, size) /* USUBLB ., ., . (ff20fc00/45001800) */ //#define IEM_INSTR_IMPL_A64__usublb_z_zz(Zd, Zn, T, U, Zm, size) /* UABDLB ., ., . (ff20fc00/45003800) */ //#define IEM_INSTR_IMPL_A64__uabdlb_z_zz(Zd, Zn, T, U, Zm, size) /* UADDLT ., ., . (ff20fc00/45000c00) */ //#define IEM_INSTR_IMPL_A64__uaddlt_z_zz(Zd, Zn, T, U, Zm, size) /* USUBLT ., ., . (ff20fc00/45001c00) */ //#define IEM_INSTR_IMPL_A64__usublt_z_zz(Zd, Zn, T, U, Zm, size) /* UABDLT ., ., . (ff20fc00/45003c00) */ //#define IEM_INSTR_IMPL_A64__uabdlt_z_zz(Zd, Zn, T, U, Zm, size) /* * * Instruction Set & Groups: sve_intx_cons_arith_wide / sve_intx_cons_widening / sve / A64 * */ /* SADDWB ., ., . (ff20fc00/45004000) */ //#define IEM_INSTR_IMPL_A64__saddwb_z_zz(Zd, Zn, T, U, Zm, size) /* SSUBWB ., ., . (ff20fc00/45005000) */ //#define IEM_INSTR_IMPL_A64__ssubwb_z_zz(Zd, Zn, T, U, Zm, size) /* SADDWT ., ., . (ff20fc00/45004400) */ //#define IEM_INSTR_IMPL_A64__saddwt_z_zz(Zd, Zn, T, U, Zm, size) /* SSUBWT ., ., . (ff20fc00/45005400) */ //#define IEM_INSTR_IMPL_A64__ssubwt_z_zz(Zd, Zn, T, U, Zm, size) /* UADDWB ., ., . (ff20fc00/45004800) */ //#define IEM_INSTR_IMPL_A64__uaddwb_z_zz(Zd, Zn, T, U, Zm, size) /* USUBWB ., ., . (ff20fc00/45005800) */ //#define IEM_INSTR_IMPL_A64__usubwb_z_zz(Zd, Zn, T, U, Zm, size) /* UADDWT ., ., . (ff20fc00/45004c00) */ //#define IEM_INSTR_IMPL_A64__uaddwt_z_zz(Zd, Zn, T, U, Zm, size) /* USUBWT ., ., . (ff20fc00/45005c00) */ //#define IEM_INSTR_IMPL_A64__usubwt_z_zz(Zd, Zn, T, U, Zm, size) /* * * Instruction Set & Groups: sve_intx_cons_mul_long / sve_intx_cons_widening / sve / A64 * */ /* SQDMULLB ., ., . (ff20fc00/45006000) */ //#define IEM_INSTR_IMPL_A64__sqdmullb_z_zz(Zd, Zn, T, Zm, size) /* PMULLB .Q, .D, .D (ffe0fc00/45006800) */ //#define IEM_INSTR_IMPL_A64__pmullb_z_zz_q(Zd, Zn, T, Zm) /* PMULLB ., ., . (ff20fc00/45006800) */ //#define IEM_INSTR_IMPL_A64__pmullb_z_zz(Zd, Zn, T, Zm, size) /* SMULLB ., ., . (ff20fc00/45007000) */ //#define IEM_INSTR_IMPL_A64__smullb_z_zz(Zd, Zn, T, U, Zm, size) /* SQDMULLT ., ., . (ff20fc00/45006400) */ //#define IEM_INSTR_IMPL_A64__sqdmullt_z_zz(Zd, Zn, T, Zm, size) /* PMULLT .Q, .D, .D (ffe0fc00/45006c00) */ //#define IEM_INSTR_IMPL_A64__pmullt_z_zz_q(Zd, Zn, T, Zm) /* PMULLT ., ., . (ff20fc00/45006c00) */ //#define IEM_INSTR_IMPL_A64__pmullt_z_zz(Zd, Zn, T, Zm, size) /* SMULLT ., ., . (ff20fc00/45007400) */ //#define IEM_INSTR_IMPL_A64__smullt_z_zz(Zd, Zn, T, U, Zm, size) /* UMULLB ., ., . (ff20fc00/45007800) */ //#define IEM_INSTR_IMPL_A64__umullb_z_zz(Zd, Zn, T, U, Zm, size) /* UMULLT ., ., . (ff20fc00/45007c00) */ //#define IEM_INSTR_IMPL_A64__umullt_z_zz(Zd, Zn, T, U, Zm, size) /* * * Instruction Set & Groups: sve_intx_dot / sve_intx_muladd_unpred / sve / A64 * */ /* SDOT ., ., . (ffa0fc00/44800000) */ //#define IEM_INSTR_IMPL_A64__sdot_z_zzz(Zda, Zn, U, Zm, size) /* UDOT ., ., . (ffa0fc00/44800400) */ //#define IEM_INSTR_IMPL_A64__udot_z_zzz(Zda, Zn, U, Zm, size) /* * * Instruction Set & Groups: sve_intx_dot2_by_indexed_elem_lvl2 / sve_intx_dot2_by_indexed_elem / sve / A64 * */ /* SDOT .S, .H, .H[] (ffe0fc00/4480c800) */ //#define IEM_INSTR_IMPL_A64__sdot_z32_zzzi(Zda, Zn, U, Zm, i2) /* UDOT .S, .H, .H[] (ffe0fc00/4480cc00) */ //#define IEM_INSTR_IMPL_A64__udot_z32_zzzi(Zda, Zn, U, Zm, i2) /* * * Instruction Set & Groups: sve_intx_dot2_lvl2 / sve_intx_dot2 / sve / A64 * */ /* SDOT .S, .H, .H (ffe0fc00/4400c800) */ //#define IEM_INSTR_IMPL_A64__sdot_z32_zzz(Zda, Zn, U, Zm) /* UDOT .S, .H, .H (ffe0fc00/4400cc00) */ //#define IEM_INSTR_IMPL_A64__udot_z32_zzz(Zda, Zn, U, Zm) /* * * Instruction Set & Groups: sve_intx_dot_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* SDOT .S, .B, .B[] (ffe0fc00/44a00000) */ //#define IEM_INSTR_IMPL_A64__sdot_z_zzzi_s(Zda, Zn, U, Zm, i2) /* SDOT .D, .H, .H[] (ffe0fc00/44e00000) */ //#define IEM_INSTR_IMPL_A64__sdot_z_zzzi_d(Zda, Zn, U, Zm, i1) /* UDOT .S, .B, .B[] (ffe0fc00/44a00400) */ //#define IEM_INSTR_IMPL_A64__udot_z_zzzi_s(Zda, Zn, U, Zm, i2) /* UDOT .D, .H, .H[] (ffe0fc00/44e00400) */ //#define IEM_INSTR_IMPL_A64__udot_z_zzzi_d(Zda, Zn, U, Zm, i1) /* * * Instruction Set & Groups: sve_intx_eorx / sve_intx_constructive / sve / A64 * */ /* EORBT ., ., . (ff20fc00/45009000) */ //#define IEM_INSTR_IMPL_A64__eorbt_z_zz(Zd, Zn, Zm, size) /* EORTB ., ., . (ff20fc00/45009400) */ //#define IEM_INSTR_IMPL_A64__eortb_z_zz(Zd, Zn, Zm, size) /* * * Instruction Set & Groups: sve_intx_extract_narrow / sve_intx_narrowing / sve / A64 * */ /* SQXTNB ., . (ffa7fc00/45204000) */ //#define IEM_INSTR_IMPL_A64__sqxtnb_z_zz(Zd, Zn, T, U, tszl, tszh) /* SQXTUNB ., . (ffa7fc00/45205000) */ //#define IEM_INSTR_IMPL_A64__sqxtunb_z_zz(Zd, Zn, T, tszl, tszh) /* SQXTNT ., . (ffa7fc00/45204400) */ //#define IEM_INSTR_IMPL_A64__sqxtnt_z_zz(Zd, Zn, T, U, tszl, tszh) /* SQXTUNT ., . (ffa7fc00/45205400) */ //#define IEM_INSTR_IMPL_A64__sqxtunt_z_zz(Zd, Zn, T, tszl, tszh) /* UQXTNB ., . (ffa7fc00/45204800) */ //#define IEM_INSTR_IMPL_A64__uqxtnb_z_zz(Zd, Zn, T, U, tszl, tszh) /* UQXTNT ., . (ffa7fc00/45204c00) */ //#define IEM_INSTR_IMPL_A64__uqxtnt_z_zz(Zd, Zn, T, U, tszl, tszh) /* * * Instruction Set & Groups: sve_intx_histcnt_lvl2 / sve_intx_histcnt / sve / A64 * */ /* HISTCNT ., /Z, ., . (ff20e000/4520c000) */ //#define IEM_INSTR_IMPL_A64__histcnt_z_p_zz(Zd, Zn, Pg, Zm, size) /* * * Instruction Set & Groups: sve_intx_histseg / sve_intx_histseg_lut / sve / A64 * */ /* HISTSEG .B, .B, .B (ff20fc00/4520a000) */ //#define IEM_INSTR_IMPL_A64__histseg_z_zz(Zd, Zn, Zm, size) /* * * Instruction Set & Groups: sve_intx_lut2_16 / sve_intx_histseg_lut / sve / A64 * */ /* LUTI2 .H, { .H }, [] (ff20ec00/4520a800) */ //#define IEM_INSTR_IMPL_A64__luti2_z_zz_16(Zd, Zn, i3l, Zm, i3h) /* * * Instruction Set & Groups: sve_intx_lut2_8 / sve_intx_histseg_lut / sve / A64 * */ /* LUTI2 .B, { .B }, [] (ff20fc00/4520b000) */ //#define IEM_INSTR_IMPL_A64__luti2_z_zz_8(Zd, Zn, Zm, i2) /* * * Instruction Set & Groups: sve_intx_lut4_16 / sve_intx_histseg_lut / sve / A64 * */ /* LUTI4 .H, { .H, .H }, [] (ff20fc00/4520b400) */ //#define IEM_INSTR_IMPL_A64__luti4_z_zz_2x16(Zd, Zn, Zm, i2) /* LUTI4 .H, { .H }, [] (ff20fc00/4520bc00) */ //#define IEM_INSTR_IMPL_A64__luti4_z_zz_1x16(Zd, Zn, Zm, i2) /* * * Instruction Set & Groups: sve_intx_lut4_8 / sve_intx_histseg_lut / sve / A64 * */ /* LUTI4 .B, { .B }, [] (ff60fc00/4560a400) */ //#define IEM_INSTR_IMPL_A64__luti4_z_zz_8(Zd, Zn, Zm, i1) /* * * Instruction Set & Groups: sve_intx_match / sve_intx_string / sve / A64 * */ /* MATCH ., /Z, ., . (ff20e010/45208000) */ //#define IEM_INSTR_IMPL_A64__match_p_p_zz(Pd, Zn, Pg, Zm, size) /* NMATCH ., /Z, ., . (ff20e010/45208010) */ //#define IEM_INSTR_IMPL_A64__nmatch_p_p_zz(Pd, Zn, Pg, Zm, size) /* * * Instruction Set & Groups: sve_intx_mixed_dot / sve_intx_muladd_unpred / sve / A64 * */ /* USDOT .S, .B, .B (ffe0fc00/44807800) */ //#define IEM_INSTR_IMPL_A64__usdot_z_zzz_s(Zda, Zn, Zm) /* * * Instruction Set & Groups: sve_intx_mixed_dot_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* USDOT .S, .B, .B[] (ffe0fc00/44a01800) */ //#define IEM_INSTR_IMPL_A64__usdot_z_zzzi_s(Zda, Zn, U, Zm, i2) /* SUDOT .S, .B, .B[] (ffe0fc00/44a01c00) */ //#define IEM_INSTR_IMPL_A64__sudot_z_zzzi_s(Zda, Zn, U, Zm, i2) /* * * Instruction Set & Groups: sve_intx_mla_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* MLA .H, .H, .H[] (ffa0fc00/44200800) */ //#define IEM_INSTR_IMPL_A64__mla_z_zzzi_h(Zda, Zn, S, Zm, i3l, i3h) /* MLA .S, .S, .S[] (ffe0fc00/44a00800) */ //#define IEM_INSTR_IMPL_A64__mla_z_zzzi_s(Zda, Zn, S, Zm, i2) /* MLA .D, .D, .D[] (ffe0fc00/44e00800) */ //#define IEM_INSTR_IMPL_A64__mla_z_zzzi_d(Zda, Zn, S, Zm, i1) /* MLS .H, .H, .H[] (ffa0fc00/44200c00) */ //#define IEM_INSTR_IMPL_A64__mls_z_zzzi_h(Zda, Zn, S, Zm, i3l, i3h) /* MLS .S, .S, .S[] (ffe0fc00/44a00c00) */ //#define IEM_INSTR_IMPL_A64__mls_z_zzzi_s(Zda, Zn, S, Zm, i2) /* MLS .D, .D, .D[] (ffe0fc00/44e00c00) */ //#define IEM_INSTR_IMPL_A64__mls_z_zzzi_d(Zda, Zn, S, Zm, i1) /* * * Instruction Set & Groups: sve_intx_mla_long_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* SMLALB .S, .H, .H[] (ffe0f400/44a08000) */ //#define IEM_INSTR_IMPL_A64__smlalb_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h) /* SMLALB .D, .S, .S[] (ffe0f400/44e08000) */ //#define IEM_INSTR_IMPL_A64__smlalb_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h) /* SMLSLB .S, .H, .H[] (ffe0f400/44a0a000) */ //#define IEM_INSTR_IMPL_A64__smlslb_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h) /* SMLSLB .D, .S, .S[] (ffe0f400/44e0a000) */ //#define IEM_INSTR_IMPL_A64__smlslb_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h) /* SMLALT .S, .H, .H[] (ffe0f400/44a08400) */ //#define IEM_INSTR_IMPL_A64__smlalt_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h) /* SMLALT .D, .S, .S[] (ffe0f400/44e08400) */ //#define IEM_INSTR_IMPL_A64__smlalt_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h) /* SMLSLT .S, .H, .H[] (ffe0f400/44a0a400) */ //#define IEM_INSTR_IMPL_A64__smlslt_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h) /* SMLSLT .D, .S, .S[] (ffe0f400/44e0a400) */ //#define IEM_INSTR_IMPL_A64__smlslt_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h) /* UMLALB .S, .H, .H[] (ffe0f400/44a09000) */ //#define IEM_INSTR_IMPL_A64__umlalb_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h) /* UMLALB .D, .S, .S[] (ffe0f400/44e09000) */ //#define IEM_INSTR_IMPL_A64__umlalb_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h) /* UMLSLB .S, .H, .H[] (ffe0f400/44a0b000) */ //#define IEM_INSTR_IMPL_A64__umlslb_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h) /* UMLSLB .D, .S, .S[] (ffe0f400/44e0b000) */ //#define IEM_INSTR_IMPL_A64__umlslb_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h) /* UMLALT .S, .H, .H[] (ffe0f400/44a09400) */ //#define IEM_INSTR_IMPL_A64__umlalt_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h) /* UMLALT .D, .S, .S[] (ffe0f400/44e09400) */ //#define IEM_INSTR_IMPL_A64__umlalt_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h) /* UMLSLT .S, .H, .H[] (ffe0f400/44a0b400) */ //#define IEM_INSTR_IMPL_A64__umlslt_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h) /* UMLSLT .D, .S, .S[] (ffe0f400/44e0b400) */ //#define IEM_INSTR_IMPL_A64__umlslt_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h) /* * * Instruction Set & Groups: sve_intx_mlal_long / sve_intx_muladd_unpred / sve / A64 * */ /* SMLALB ., ., . (ff20fc00/44004000) */ //#define IEM_INSTR_IMPL_A64__smlalb_z_zzz(Zda, Zn, T, U, Zm, size) /* SMLSLB ., ., . (ff20fc00/44005000) */ //#define IEM_INSTR_IMPL_A64__smlslb_z_zzz(Zda, Zn, T, U, Zm, size) /* SMLALT ., ., . (ff20fc00/44004400) */ //#define IEM_INSTR_IMPL_A64__smlalt_z_zzz(Zda, Zn, T, U, Zm, size) /* SMLSLT ., ., . (ff20fc00/44005400) */ //#define IEM_INSTR_IMPL_A64__smlslt_z_zzz(Zda, Zn, T, U, Zm, size) /* UMLALB ., ., . (ff20fc00/44004800) */ //#define IEM_INSTR_IMPL_A64__umlalb_z_zzz(Zda, Zn, T, U, Zm, size) /* UMLSLB ., ., . (ff20fc00/44005800) */ //#define IEM_INSTR_IMPL_A64__umlslb_z_zzz(Zda, Zn, T, U, Zm, size) /* UMLALT ., ., . (ff20fc00/44004c00) */ //#define IEM_INSTR_IMPL_A64__umlalt_z_zzz(Zda, Zn, T, U, Zm, size) /* UMLSLT ., ., . (ff20fc00/44005c00) */ //#define IEM_INSTR_IMPL_A64__umlslt_z_zzz(Zda, Zn, T, U, Zm, size) /* * * Instruction Set & Groups: sve_intx_mmla / sve_intx_constructive / sve / A64 * */ /* SMMLA .S, .B, .B (ffe0fc00/45009800) */ //#define IEM_INSTR_IMPL_A64__smmla_z_zzz(Zda, Zn, Zm, uns) /* USMMLA .S, .B, .B (ffe0fc00/45809800) */ //#define IEM_INSTR_IMPL_A64__usmmla_z_zzz(Zda, Zn, Zm, uns) /* UMMLA .S, .B, .B (ffe0fc00/45c09800) */ //#define IEM_INSTR_IMPL_A64__ummla_z_zzz(Zda, Zn, Zm, uns) /* * * Instruction Set & Groups: sve_intx_mul_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* MUL .H, .H, .H[] (ffa0fc00/4420f800) */ //#define IEM_INSTR_IMPL_A64__mul_z_zzi_h(Zd, Zn, Zm, i3l, i3h) /* MUL .S, .S, .S[] (ffe0fc00/44a0f800) */ //#define IEM_INSTR_IMPL_A64__mul_z_zzi_s(Zd, Zn, Zm, i2) /* MUL .D, .D, .D[] (ffe0fc00/44e0f800) */ //#define IEM_INSTR_IMPL_A64__mul_z_zzi_d(Zd, Zn, Zm, i1) /* * * Instruction Set & Groups: sve_intx_mul_long_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* SMULLB .S, .H, .H[] (ffe0f400/44a0c000) */ //#define IEM_INSTR_IMPL_A64__smullb_z_zzi_s(Zd, Zn, T, i3l, U, Zm, i3h) /* SMULLB .D, .S, .S[] (ffe0f400/44e0c000) */ //#define IEM_INSTR_IMPL_A64__smullb_z_zzi_d(Zd, Zn, T, i2l, U, Zm, i2h) /* SMULLT .S, .H, .H[] (ffe0f400/44a0c400) */ //#define IEM_INSTR_IMPL_A64__smullt_z_zzi_s(Zd, Zn, T, i3l, U, Zm, i3h) /* SMULLT .D, .S, .S[] (ffe0f400/44e0c400) */ //#define IEM_INSTR_IMPL_A64__smullt_z_zzi_d(Zd, Zn, T, i2l, U, Zm, i2h) /* UMULLB .S, .H, .H[] (ffe0f400/44a0d000) */ //#define IEM_INSTR_IMPL_A64__umullb_z_zzi_s(Zd, Zn, T, i3l, U, Zm, i3h) /* UMULLB .D, .S, .S[] (ffe0f400/44e0d000) */ //#define IEM_INSTR_IMPL_A64__umullb_z_zzi_d(Zd, Zn, T, i2l, U, Zm, i2h) /* UMULLT .S, .H, .H[] (ffe0f400/44a0d400) */ //#define IEM_INSTR_IMPL_A64__umullt_z_zzi_s(Zd, Zn, T, i3l, U, Zm, i3h) /* UMULLT .D, .S, .S[] (ffe0f400/44e0d400) */ //#define IEM_INSTR_IMPL_A64__umullt_z_zzi_d(Zd, Zn, T, i2l, U, Zm, i2h) /* * * Instruction Set & Groups: sve_intx_multi_extract_narrow / sve_intx_narrowing / sve / A64 * */ /* SQCVTN .H, { .S-.S } (fffffc20/45314000) */ //#define IEM_INSTR_IMPL_A64__sqcvtn_z_mz2(Zd, Zn, U) /* SQCVTUN .H, { .S-.S } (fffffc20/45315000) */ //#define IEM_INSTR_IMPL_A64__sqcvtun_z_mz2(Zd, Zn) /* UQCVTN .H, { .S-.S } (fffffc20/45314800) */ //#define IEM_INSTR_IMPL_A64__uqcvtn_z_mz2(Zd, Zn, U) /* * * Instruction Set & Groups: sve_intx_multi_shift_narrow / sve_intx_narrowing / sve / A64 * */ /* SQRSHRN .H, { .S-.S }, # (fff0fc20/45b02800) */ //#define IEM_INSTR_IMPL_A64__sqrshrn_z_mz2(Zd, Zn, U, imm4) /* SQRSHRUN .H, { .S-.S }, # (fff0fc20/45b00800) */ //#define IEM_INSTR_IMPL_A64__sqrshrun_z_mz2(Zd, Zn, imm4) /* UQRSHRN .H, { .S-.S }, # (fff0fc20/45b03800) */ //#define IEM_INSTR_IMPL_A64__uqrshrn_z_mz2(Zd, Zn, U, imm4) /* * * Instruction Set & Groups: sve_intx_perm_bit / sve_intx_constructive / sve / A64 * */ /* BEXT ., ., . (ff20fc00/4500b000) */ //#define IEM_INSTR_IMPL_A64__bext_z_zz(Zd, Zn, Zm, size) /* BDEP ., ., . (ff20fc00/4500b400) */ //#define IEM_INSTR_IMPL_A64__bdep_z_zz(Zd, Zn, Zm, size) /* BGRP ., ., . (ff20fc00/4500b800) */ //#define IEM_INSTR_IMPL_A64__bgrp_z_zz(Zd, Zn, Zm, size) /* * * Instruction Set & Groups: sve_intx_perm_extract_i / sve_perm_extract / sve / A64 * */ /* EXT .B, { .B, .B }, # (ffe0e000/05600000) */ //#define IEM_INSTR_IMPL_A64__ext_z_zi_con(Zd, Zn, imm8l, imm8h) /* * * Instruction Set & Groups: sve_intx_perm_splice / sve_perm_pred / sve / A64 * */ /* SPLICE ., , { ., . } (ff3fe000/052d8000) */ //#define IEM_INSTR_IMPL_A64__splice_z_p_zz_con(Zd, Zn, Pv, size) /* * * Instruction Set & Groups: sve_intx_pred_arith_binary / sve_intx_predicated / sve / A64 * */ /* SHADD ., /M, ., . (ff3fe000/44108000) */ //#define IEM_INSTR_IMPL_A64__shadd_z_p_zz(Zdn, Zm, Pg, U, size) /* SHSUB ., /M, ., . (ff3fe000/44128000) */ //#define IEM_INSTR_IMPL_A64__shsub_z_p_zz(Zdn, Zm, Pg, U, size) /* SRHADD ., /M, ., . (ff3fe000/44148000) */ //#define IEM_INSTR_IMPL_A64__srhadd_z_p_zz(Zdn, Zm, Pg, U, size) /* SHSUBR ., /M, ., . (ff3fe000/44168000) */ //#define IEM_INSTR_IMPL_A64__shsubr_z_p_zz(Zdn, Zm, Pg, U, size) /* UHADD ., /M, ., . (ff3fe000/44118000) */ //#define IEM_INSTR_IMPL_A64__uhadd_z_p_zz(Zdn, Zm, Pg, U, size) /* UHSUB ., /M, ., . (ff3fe000/44138000) */ //#define IEM_INSTR_IMPL_A64__uhsub_z_p_zz(Zdn, Zm, Pg, U, size) /* URHADD ., /M, ., . (ff3fe000/44158000) */ //#define IEM_INSTR_IMPL_A64__urhadd_z_p_zz(Zdn, Zm, Pg, U, size) /* UHSUBR ., /M, ., . (ff3fe000/44178000) */ //#define IEM_INSTR_IMPL_A64__uhsubr_z_p_zz(Zdn, Zm, Pg, U, size) /* * * Instruction Set & Groups: sve_intx_pred_arith_binary_sat / sve_intx_predicated / sve / A64 * */ /* SQADD ., /M, ., . (ff3fe000/44188000) */ //#define IEM_INSTR_IMPL_A64__sqadd_z_p_zz(Zdn, Zm, Pg, U, size) /* SQSUB ., /M, ., . (ff3fe000/441a8000) */ //#define IEM_INSTR_IMPL_A64__sqsub_z_p_zz(Zdn, Zm, Pg, U, size) /* SUQADD ., /M, ., . (ff3fe000/441c8000) */ //#define IEM_INSTR_IMPL_A64__suqadd_z_p_zz(Zdn, Zm, Pg, size) /* USQADD ., /M, ., . (ff3fe000/441d8000) */ //#define IEM_INSTR_IMPL_A64__usqadd_z_p_zz(Zdn, Zm, Pg, size) /* SQSUBR ., /M, ., . (ff3fe000/441e8000) */ //#define IEM_INSTR_IMPL_A64__sqsubr_z_p_zz(Zdn, Zm, Pg, U, size) /* UQADD ., /M, ., . (ff3fe000/44198000) */ //#define IEM_INSTR_IMPL_A64__uqadd_z_p_zz(Zdn, Zm, Pg, U, size) /* UQSUB ., /M, ., . (ff3fe000/441b8000) */ //#define IEM_INSTR_IMPL_A64__uqsub_z_p_zz(Zdn, Zm, Pg, U, size) /* UQSUBR ., /M, ., . (ff3fe000/441f8000) */ //#define IEM_INSTR_IMPL_A64__uqsubr_z_p_zz(Zdn, Zm, Pg, U, size) /* * * Instruction Set & Groups: sve_intx_pred_arith_unary / sve_intx_predicated / sve / A64 * */ /* URECPE .S, /M, .S (ff3fe000/4400a000) */ //#define IEM_INSTR_IMPL_A64__urecpe_z_p_z_m(Zd, Zn, Pg, size) /* URECPE .S, /Z, .S (ff3fe000/4402a000) */ //#define IEM_INSTR_IMPL_A64__urecpe_z_p_z_z(Zd, Zn, Pg, size) /* URSQRTE .S, /M, .S (ff3fe000/4401a000) */ //#define IEM_INSTR_IMPL_A64__ursqrte_z_p_z_m(Zd, Zn, Pg, size) /* URSQRTE .S, /Z, .S (ff3fe000/4403a000) */ //#define IEM_INSTR_IMPL_A64__ursqrte_z_p_z_z(Zd, Zn, Pg, size) /* SQABS ., /M, . (ff3fe000/4408a000) */ //#define IEM_INSTR_IMPL_A64__sqabs_z_p_z_m(Zd, Zn, Pg, size) /* SQABS ., /Z, . (ff3fe000/440aa000) */ //#define IEM_INSTR_IMPL_A64__sqabs_z_p_z_z(Zd, Zn, Pg, size) /* SQNEG ., /M, . (ff3fe000/4409a000) */ //#define IEM_INSTR_IMPL_A64__sqneg_z_p_z_m(Zd, Zn, Pg, size) /* SQNEG ., /Z, . (ff3fe000/440ba000) */ //#define IEM_INSTR_IMPL_A64__sqneg_z_p_z_z(Zd, Zn, Pg, size) /* * * Instruction Set & Groups: sve_intx_qdmla_long_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* SQDMLALB .S, .H, .H[] (ffe0f400/44a02000) */ //#define IEM_INSTR_IMPL_A64__sqdmlalb_z_zzzi_s(Zda, Zn, T, i3l, S, Zm, i3h) /* SQDMLALB .D, .S, .S[] (ffe0f400/44e02000) */ //#define IEM_INSTR_IMPL_A64__sqdmlalb_z_zzzi_d(Zda, Zn, T, i2l, S, Zm, i2h) /* SQDMLSLB .S, .H, .H[] (ffe0f400/44a03000) */ //#define IEM_INSTR_IMPL_A64__sqdmlslb_z_zzzi_s(Zda, Zn, T, i3l, S, Zm, i3h) /* SQDMLSLB .D, .S, .S[] (ffe0f400/44e03000) */ //#define IEM_INSTR_IMPL_A64__sqdmlslb_z_zzzi_d(Zda, Zn, T, i2l, S, Zm, i2h) /* SQDMLALT .S, .H, .H[] (ffe0f400/44a02400) */ //#define IEM_INSTR_IMPL_A64__sqdmlalt_z_zzzi_s(Zda, Zn, T, i3l, S, Zm, i3h) /* SQDMLALT .D, .S, .S[] (ffe0f400/44e02400) */ //#define IEM_INSTR_IMPL_A64__sqdmlalt_z_zzzi_d(Zda, Zn, T, i2l, S, Zm, i2h) /* SQDMLSLT .S, .H, .H[] (ffe0f400/44a03400) */ //#define IEM_INSTR_IMPL_A64__sqdmlslt_z_zzzi_s(Zda, Zn, T, i3l, S, Zm, i3h) /* SQDMLSLT .D, .S, .S[] (ffe0f400/44e03400) */ //#define IEM_INSTR_IMPL_A64__sqdmlslt_z_zzzi_d(Zda, Zn, T, i2l, S, Zm, i2h) /* * * Instruction Set & Groups: sve_intx_qdmlal_long / sve_intx_muladd_unpred / sve / A64 * */ /* SQDMLALB ., ., . (ff20fc00/44006000) */ //#define IEM_INSTR_IMPL_A64__sqdmlalb_z_zzz(Zda, Zn, T, Zm, size) /* SQDMLSLB ., ., . (ff20fc00/44006800) */ //#define IEM_INSTR_IMPL_A64__sqdmlslb_z_zzz(Zda, Zn, T, Zm, size) /* SQDMLALT ., ., . (ff20fc00/44006400) */ //#define IEM_INSTR_IMPL_A64__sqdmlalt_z_zzz(Zda, Zn, T, Zm, size) /* SQDMLSLT ., ., . (ff20fc00/44006c00) */ //#define IEM_INSTR_IMPL_A64__sqdmlslt_z_zzz(Zda, Zn, T, Zm, size) /* * * Instruction Set & Groups: sve_intx_qdmlalbt / sve_intx_muladd_unpred / sve / A64 * */ /* SQDMLALBT ., ., . (ff20fc00/44000800) */ //#define IEM_INSTR_IMPL_A64__sqdmlalbt_z_zzz(Zda, Zn, Zm, size) /* SQDMLSLBT ., ., . (ff20fc00/44000c00) */ //#define IEM_INSTR_IMPL_A64__sqdmlslbt_z_zzz(Zda, Zn, Zm, size) /* * * Instruction Set & Groups: sve_intx_qdmul_long_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* SQDMULLB .S, .H, .H[] (ffe0f400/44a0e000) */ //#define IEM_INSTR_IMPL_A64__sqdmullb_z_zzi_s(Zd, Zn, T, i3l, Zm, i3h) /* SQDMULLB .D, .S, .S[] (ffe0f400/44e0e000) */ //#define IEM_INSTR_IMPL_A64__sqdmullb_z_zzi_d(Zd, Zn, T, i2l, Zm, i2h) /* SQDMULLT .S, .H, .H[] (ffe0f400/44a0e400) */ //#define IEM_INSTR_IMPL_A64__sqdmullt_z_zzi_s(Zd, Zn, T, i3l, Zm, i3h) /* SQDMULLT .D, .S, .S[] (ffe0f400/44e0e400) */ //#define IEM_INSTR_IMPL_A64__sqdmullt_z_zzi_d(Zd, Zn, T, i2l, Zm, i2h) /* * * Instruction Set & Groups: sve_intx_qdmulh_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* SQDMULH .H, .H, .H[] (ffa0fc00/4420f000) */ //#define IEM_INSTR_IMPL_A64__sqdmulh_z_zzi_h(Zd, Zn, Zm, i3l, i3h) /* SQDMULH .S, .S, .S[] (ffe0fc00/44a0f000) */ //#define IEM_INSTR_IMPL_A64__sqdmulh_z_zzi_s(Zd, Zn, Zm, i2) /* SQDMULH .D, .D, .D[] (ffe0fc00/44e0f000) */ //#define IEM_INSTR_IMPL_A64__sqdmulh_z_zzi_d(Zd, Zn, Zm, i1) /* SQRDMULH .H, .H, .H[] (ffa0fc00/4420f400) */ //#define IEM_INSTR_IMPL_A64__sqrdmulh_z_zzi_h(Zd, Zn, Zm, i3l, i3h) /* SQRDMULH .S, .S, .S[] (ffe0fc00/44a0f400) */ //#define IEM_INSTR_IMPL_A64__sqrdmulh_z_zzi_s(Zd, Zn, Zm, i2) /* SQRDMULH .D, .D, .D[] (ffe0fc00/44e0f400) */ //#define IEM_INSTR_IMPL_A64__sqrdmulh_z_zzi_d(Zd, Zn, Zm, i1) /* * * Instruction Set & Groups: sve_intx_qrdcmla_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* SQRDCMLAH .H, .H, .H[], (ffe0f000/44a07000) */ //#define IEM_INSTR_IMPL_A64__sqrdcmlah_z_zzzi_h(Zda, Zn, rot, Zm, i2) /* SQRDCMLAH .S, .S, .S[], (ffe0f000/44e07000) */ //#define IEM_INSTR_IMPL_A64__sqrdcmlah_z_zzzi_s(Zda, Zn, rot, Zm, i1) /* * * Instruction Set & Groups: sve_intx_qrdmlah / sve_intx_muladd_unpred / sve / A64 * */ /* SQRDMLAH ., ., . (ff20fc00/44007000) */ //#define IEM_INSTR_IMPL_A64__sqrdmlah_z_zzz(Zda, Zn, Zm, size) /* SQRDMLSH ., ., . (ff20fc00/44007400) */ //#define IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzz(Zda, Zn, Zm, size) /* * * Instruction Set & Groups: sve_intx_qrdmlah_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64 * */ /* SQRDMLAH .H, .H, .H[] (ffa0fc00/44201000) */ //#define IEM_INSTR_IMPL_A64__sqrdmlah_z_zzzi_h(Zda, Zn, S, Zm, i3l, i3h) /* SQRDMLAH .S, .S, .S[] (ffe0fc00/44a01000) */ //#define IEM_INSTR_IMPL_A64__sqrdmlah_z_zzzi_s(Zda, Zn, S, Zm, i2) /* SQRDMLAH .D, .D, .D[] (ffe0fc00/44e01000) */ //#define IEM_INSTR_IMPL_A64__sqrdmlah_z_zzzi_d(Zda, Zn, S, Zm, i1) /* SQRDMLSH .H, .H, .H[] (ffa0fc00/44201400) */ //#define IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzzi_h(Zda, Zn, S, Zm, i3l, i3h) /* SQRDMLSH .S, .S, .S[] (ffe0fc00/44a01400) */ //#define IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzzi_s(Zda, Zn, S, Zm, i2) /* SQRDMLSH .D, .D, .D[] (ffe0fc00/44e01400) */ //#define IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzzi_d(Zda, Zn, S, Zm, i1) /* * * Instruction Set & Groups: sve_intx_shift_insert / sve_intx_acc / sve / A64 * */ /* SRI ., ., # (ff20fc00/4500f000) */ //#define IEM_INSTR_IMPL_A64__sri_z_zzi(Zd, Zn, imm3, tszl, tszh) /* SLI ., ., # (ff20fc00/4500f400) */ //#define IEM_INSTR_IMPL_A64__sli_z_zzi(Zd, Zn, imm3, tszl, tszh) /* * * Instruction Set & Groups: sve_intx_shift_long / sve_intx_constructive / sve / A64 * */ /* SSHLLB ., ., # (ffa0fc00/4500a000) */ //#define IEM_INSTR_IMPL_A64__sshllb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh) /* SSHLLT ., ., # (ffa0fc00/4500a400) */ //#define IEM_INSTR_IMPL_A64__sshllt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh) /* USHLLB ., ., # (ffa0fc00/4500a800) */ //#define IEM_INSTR_IMPL_A64__ushllb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh) /* USHLLT ., ., # (ffa0fc00/4500ac00) */ //#define IEM_INSTR_IMPL_A64__ushllt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh) /* * * Instruction Set & Groups: sve_intx_shift_narrow / sve_intx_narrowing / sve / A64 * */ /* SQSHRUNB ., ., # (ffa0fc00/45200000) */ //#define IEM_INSTR_IMPL_A64__sqshrunb_z_zi(Zd, Zn, T, imm3, tszl, tszh) /* SQRSHRUNB ., ., # (ffa0fc00/45200800) */ //#define IEM_INSTR_IMPL_A64__sqrshrunb_z_zi(Zd, Zn, T, imm3, tszl, tszh) /* SHRNB ., ., # (ffa0fc00/45201000) */ //#define IEM_INSTR_IMPL_A64__shrnb_z_zi(Zd, Zn, T, imm3, tszl, tszh) /* RSHRNB ., ., # (ffa0fc00/45201800) */ //#define IEM_INSTR_IMPL_A64__rshrnb_z_zi(Zd, Zn, T, imm3, tszl, tszh) /* SQSHRNB ., ., # (ffa0fc00/45202000) */ //#define IEM_INSTR_IMPL_A64__sqshrnb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh) /* SQRSHRNB ., ., # (ffa0fc00/45202800) */ //#define IEM_INSTR_IMPL_A64__sqrshrnb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh) /* SQSHRUNT ., ., # (ffa0fc00/45200400) */ //#define IEM_INSTR_IMPL_A64__sqshrunt_z_zi(Zd, Zn, T, imm3, tszl, tszh) /* SQRSHRUNT ., ., # (ffa0fc00/45200c00) */ //#define IEM_INSTR_IMPL_A64__sqrshrunt_z_zi(Zd, Zn, T, imm3, tszl, tszh) /* SHRNT ., ., # (ffa0fc00/45201400) */ //#define IEM_INSTR_IMPL_A64__shrnt_z_zi(Zd, Zn, T, imm3, tszl, tszh) /* RSHRNT ., ., # (ffa0fc00/45201c00) */ //#define IEM_INSTR_IMPL_A64__rshrnt_z_zi(Zd, Zn, T, imm3, tszl, tszh) /* SQSHRNT ., ., # (ffa0fc00/45202400) */ //#define IEM_INSTR_IMPL_A64__sqshrnt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh) /* SQRSHRNT ., ., # (ffa0fc00/45202c00) */ //#define IEM_INSTR_IMPL_A64__sqrshrnt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh) /* UQSHRNB ., ., # (ffa0fc00/45203000) */ //#define IEM_INSTR_IMPL_A64__uqshrnb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh) /* UQRSHRNB ., ., # (ffa0fc00/45203800) */ //#define IEM_INSTR_IMPL_A64__uqrshrnb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh) /* UQSHRNT ., ., # (ffa0fc00/45203400) */ //#define IEM_INSTR_IMPL_A64__uqshrnt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh) /* UQRSHRNT ., ., # (ffa0fc00/45203c00) */ //#define IEM_INSTR_IMPL_A64__uqrshrnt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh) /* * * Instruction Set & Groups: sve_intx_sra / sve_intx_acc / sve / A64 * */ /* SSRA ., ., # (ff20fc00/4500e000) */ //#define IEM_INSTR_IMPL_A64__ssra_z_zi(Zda, Zn, U, imm3, tszl, tszh) /* SRSRA ., ., # (ff20fc00/4500e800) */ //#define IEM_INSTR_IMPL_A64__srsra_z_zi(Zda, Zn, U, imm3, tszl, tszh) /* USRA ., ., # (ff20fc00/4500e400) */ //#define IEM_INSTR_IMPL_A64__usra_z_zi(Zda, Zn, U, imm3, tszl, tszh) /* URSRA ., ., # (ff20fc00/4500ec00) */ //#define IEM_INSTR_IMPL_A64__ursra_z_zi(Zda, Zn, U, imm3, tszl, tszh) /* * * Instruction Set & Groups: sve_mem_32b_fill / sve_mem32 / sve / A64 * */ /* LDR , [{, #, MUL VL}] (ffc0e000/85804000) */ //#define IEM_INSTR_IMPL_A64__ldr_z_bi(Zt, Rn, imm9l, imm9h) /* * * Instruction Set & Groups: sve_mem_32b_gld_sv_a / sve_mem32 / sve / A64 * */ /* LD1SH { .S }, /Z, [, .S, #1] (ffa0e000/84a00000) */ //#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LD1H { .S }, /Z, [, .S, #1] (ffa0e000/84a04000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1SH { .S }, /Z, [, .S, #1] (ffa0e000/84a02000) */ //#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1H { .S }, /Z, [, .S, #1] (ffa0e000/84a06000) */ //#define IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs) /* * * Instruction Set & Groups: sve_mem_32b_gld_sv_b / sve_mem32 / sve / A64 * */ /* LD1W { .S }, /Z, [, .S, #2] (ffa0e000/85204000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, Zm, xs) /* LDFF1W { .S }, /Z, [, .S, #2] (ffa0e000/85206000) */ //#define IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, Zm, xs) /* * * Instruction Set & Groups: sve_mem_32b_gld_vi / sve_mem32 / sve / A64 * */ /* LD1SB { .S }, /Z, [.S{, #}] (ffe0e000/84208000) */ //#define IEM_INSTR_IMPL_A64__ld1sb_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5) /* LD1SH { .S }, /Z, [.S{, #}] (ffe0e000/84a08000) */ //#define IEM_INSTR_IMPL_A64__ld1sh_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5) /* LD1W { .S }, /Z, [.S{, #}] (ffe0e000/8520c000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_ai_s(Zt, Zn, Pg, ff, imm5) /* LD1B { .S }, /Z, [.S{, #}] (ffe0e000/8420c000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5) /* LD1H { .S }, /Z, [.S{, #}] (ffe0e000/84a0c000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5) /* LDFF1SB { .S }, /Z, [.S{, #}] (ffe0e000/8420a000) */ //#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5) /* LDFF1SH { .S }, /Z, [.S{, #}] (ffe0e000/84a0a000) */ //#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5) /* LDFF1W { .S }, /Z, [.S{, #}] (ffe0e000/8520e000) */ //#define IEM_INSTR_IMPL_A64__ldff1w_z_p_ai_s(Zt, Zn, Pg, ff, imm5) /* LDFF1B { .S }, /Z, [.S{, #}] (ffe0e000/8420e000) */ //#define IEM_INSTR_IMPL_A64__ldff1b_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5) /* LDFF1H { .S }, /Z, [.S{, #}] (ffe0e000/84a0e000) */ //#define IEM_INSTR_IMPL_A64__ldff1h_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5) /* * * Instruction Set & Groups: sve_mem_32b_gld_vs / sve_mem32 / sve / A64 * */ /* LD1SB { .S }, /Z, [, .S, ] (ffa0e000/84000000) */ //#define IEM_INSTR_IMPL_A64__ld1sb_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LD1SH { .S }, /Z, [, .S, ] (ffa0e000/84800000) */ //#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LD1W { .S }, /Z, [, .S, ] (ffa0e000/85004000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, Zm, xs) /* LD1B { .S }, /Z, [, .S, ] (ffa0e000/84004000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LD1H { .S }, /Z, [, .S, ] (ffa0e000/84804000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1SB { .S }, /Z, [, .S, ] (ffa0e000/84002000) */ //#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1SH { .S }, /Z, [, .S, ] (ffa0e000/84802000) */ //#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1W { .S }, /Z, [, .S, ] (ffa0e000/85006000) */ //#define IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, Zm, xs) /* LDFF1B { .S }, /Z, [, .S, ] (ffa0e000/84006000) */ //#define IEM_INSTR_IMPL_A64__ldff1b_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1H { .S }, /Z, [, .S, ] (ffa0e000/84806000) */ //#define IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* * * Instruction Set & Groups: sve_mem_32b_gldnt_vs / sve_mem32 / sve / A64 * */ /* LDNT1SB { .S }, /Z, [.S{, }] (ffe0e000/84008000) */ //#define IEM_INSTR_IMPL_A64__ldnt1sb_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, U, Rm) /* LDNT1SH { .S }, /Z, [.S{, }] (ffe0e000/84808000) */ //#define IEM_INSTR_IMPL_A64__ldnt1sh_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, U, Rm) /* LDNT1W { .S }, /Z, [.S{, }] (ffe0e000/8500a000) */ //#define IEM_INSTR_IMPL_A64__ldnt1w_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, Rm) /* LDNT1B { .S }, /Z, [.S{, }] (ffe0e000/8400a000) */ //#define IEM_INSTR_IMPL_A64__ldnt1b_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, U, Rm) /* LDNT1H { .S }, /Z, [.S{, }] (ffe0e000/8480a000) */ //#define IEM_INSTR_IMPL_A64__ldnt1h_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, U, Rm) /* * * Instruction Set & Groups: sve_mem_32b_pfill / sve_mem32 / sve / A64 * */ /* LDR , [{, #, MUL VL}] (ffc0e010/85800000) */ //#define IEM_INSTR_IMPL_A64__ldr_p_bi(Pt, Rn, imm9l, imm9h) /* * * Instruction Set & Groups: sve_mem_32b_prfm_sv / sve_mem32 / sve / A64 * */ /* PRFB , , [, .S, ] (ffa0e010/84200000) */ //#define IEM_INSTR_IMPL_A64__prfb_i_p_bz_s_x32_scaled(prfop, Rn, Pg, msz, Zm, xs) /* PRFH , , [, .S, #1] (ffa0e010/84202000) */ //#define IEM_INSTR_IMPL_A64__prfh_i_p_bz_s_x32_scaled(prfop, Rn, Pg, msz, Zm, xs) /* PRFW , , [, .S, #2] (ffa0e010/84204000) */ //#define IEM_INSTR_IMPL_A64__prfw_i_p_bz_s_x32_scaled(prfop, Rn, Pg, msz, Zm, xs) /* PRFD , , [, .S, #3] (ffa0e010/84206000) */ //#define IEM_INSTR_IMPL_A64__prfd_i_p_bz_s_x32_scaled(prfop, Rn, Pg, msz, Zm, xs) /* * * Instruction Set & Groups: sve_mem_32b_prfm_vi / sve_mem32 / sve / A64 * */ /* PRFB , , [.S{, #}] (ffe0e010/8400e000) */ //#define IEM_INSTR_IMPL_A64__prfb_i_p_ai_s(prfop, Zn, Pg, imm5) /* PRFH , , [.S{, #}] (ffe0e010/8480e000) */ //#define IEM_INSTR_IMPL_A64__prfh_i_p_ai_s(prfop, Zn, Pg, imm5) /* PRFW , , [.S{, #}] (ffe0e010/8500e000) */ //#define IEM_INSTR_IMPL_A64__prfw_i_p_ai_s(prfop, Zn, Pg, imm5) /* PRFD , , [.S{, #}] (ffe0e010/8580e000) */ //#define IEM_INSTR_IMPL_A64__prfd_i_p_ai_s(prfop, Zn, Pg, imm5) /* * * Instruction Set & Groups: sve_mem_64b_gld_sv / sve_mem64 / sve / A64 * */ /* LD1SH { .D }, /Z, [, .D, #1] (ffa0e000/c4a00000) */ //#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LD1SW { .D }, /Z, [, .D, #2] (ffa0e000/c5200000) */ //#define IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LD1D { .D }, /Z, [, .D, #3] (ffa0e000/c5a04000) */ //#define IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, Zm, xs) /* LD1H { .D }, /Z, [, .D, #1] (ffa0e000/c4a04000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LD1W { .D }, /Z, [, .D, #2] (ffa0e000/c5204000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1SH { .D }, /Z, [, .D, #1] (ffa0e000/c4a02000) */ //#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1SW { .D }, /Z, [, .D, #2] (ffa0e000/c5202000) */ //#define IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1D { .D }, /Z, [, .D, #3] (ffa0e000/c5a06000) */ //#define IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, Zm, xs) /* LDFF1H { .D }, /Z, [, .D, #1] (ffa0e000/c4a06000) */ //#define IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1W { .D }, /Z, [, .D, #2] (ffa0e000/c5206000) */ //#define IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs) /* * * Instruction Set & Groups: sve_mem_64b_gld_sv2 / sve_mem64 / sve / A64 * */ /* LD1SH { .D }, /Z, [, .D, LSL #1] (ffe0e000/c4e08000) */ //#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm) /* LD1SW { .D }, /Z, [, .D, LSL #2] (ffe0e000/c5608000) */ //#define IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm) /* LD1D { .D }, /Z, [, .D, LSL #3] (ffe0e000/c5e0c000) */ //#define IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, Zm) /* LD1H { .D }, /Z, [, .D, LSL #1] (ffe0e000/c4e0c000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm) /* LD1W { .D }, /Z, [, .D, LSL #2] (ffe0e000/c560c000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm) /* LDFF1SH { .D }, /Z, [, .D, LSL #1] (ffe0e000/c4e0a000) */ //#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm) /* LDFF1SW { .D }, /Z, [, .D, LSL #2] (ffe0e000/c560a000) */ //#define IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm) /* LDFF1D { .D }, /Z, [, .D, LSL #3] (ffe0e000/c5e0e000) */ //#define IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, Zm) /* LDFF1H { .D }, /Z, [, .D, LSL #1] (ffe0e000/c4e0e000) */ //#define IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm) /* LDFF1W { .D }, /Z, [, .D, LSL #2] (ffe0e000/c560e000) */ //#define IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm) /* * * Instruction Set & Groups: sve_mem_64b_gld_vi / sve_mem64 / sve / A64 * */ /* LD1SB { .D }, /Z, [.D{, #}] (ffe0e000/c4208000) */ //#define IEM_INSTR_IMPL_A64__ld1sb_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5) /* LD1SH { .D }, /Z, [.D{, #}] (ffe0e000/c4a08000) */ //#define IEM_INSTR_IMPL_A64__ld1sh_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5) /* LD1SW { .D }, /Z, [.D{, #}] (ffe0e000/c5208000) */ //#define IEM_INSTR_IMPL_A64__ld1sw_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5) /* LD1D { .D }, /Z, [.D{, #}] (ffe0e000/c5a0c000) */ //#define IEM_INSTR_IMPL_A64__ld1d_z_p_ai_d(Zt, Zn, Pg, ff, imm5) /* LD1B { .D }, /Z, [.D{, #}] (ffe0e000/c420c000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5) /* LD1H { .D }, /Z, [.D{, #}] (ffe0e000/c4a0c000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5) /* LD1W { .D }, /Z, [.D{, #}] (ffe0e000/c520c000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5) /* LDFF1SB { .D }, /Z, [.D{, #}] (ffe0e000/c420a000) */ //#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5) /* LDFF1SH { .D }, /Z, [.D{, #}] (ffe0e000/c4a0a000) */ //#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5) /* LDFF1SW { .D }, /Z, [.D{, #}] (ffe0e000/c520a000) */ //#define IEM_INSTR_IMPL_A64__ldff1sw_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5) /* LDFF1D { .D }, /Z, [.D{, #}] (ffe0e000/c5a0e000) */ //#define IEM_INSTR_IMPL_A64__ldff1d_z_p_ai_d(Zt, Zn, Pg, ff, imm5) /* LDFF1B { .D }, /Z, [.D{, #}] (ffe0e000/c420e000) */ //#define IEM_INSTR_IMPL_A64__ldff1b_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5) /* LDFF1H { .D }, /Z, [.D{, #}] (ffe0e000/c4a0e000) */ //#define IEM_INSTR_IMPL_A64__ldff1h_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5) /* LDFF1W { .D }, /Z, [.D{, #}] (ffe0e000/c520e000) */ //#define IEM_INSTR_IMPL_A64__ldff1w_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5) /* * * Instruction Set & Groups: sve_mem_64b_gld_vs / sve_mem64 / sve / A64 * */ /* LD1SB { .D }, /Z, [, .D, ] (ffa0e000/c4000000) */ //#define IEM_INSTR_IMPL_A64__ld1sb_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LD1SH { .D }, /Z, [, .D, ] (ffa0e000/c4800000) */ //#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LD1SW { .D }, /Z, [, .D, ] (ffa0e000/c5000000) */ //#define IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LD1D { .D }, /Z, [, .D, ] (ffa0e000/c5804000) */ //#define IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, Zm, xs) /* LD1B { .D }, /Z, [, .D, ] (ffa0e000/c4004000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LD1H { .D }, /Z, [, .D, ] (ffa0e000/c4804000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LD1W { .D }, /Z, [, .D, ] (ffa0e000/c5004000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1SB { .D }, /Z, [, .D, ] (ffa0e000/c4002000) */ //#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1SH { .D }, /Z, [, .D, ] (ffa0e000/c4802000) */ //#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1SW { .D }, /Z, [, .D, ] (ffa0e000/c5002000) */ //#define IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1D { .D }, /Z, [, .D, ] (ffa0e000/c5806000) */ //#define IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, Zm, xs) /* LDFF1B { .D }, /Z, [, .D, ] (ffa0e000/c4006000) */ //#define IEM_INSTR_IMPL_A64__ldff1b_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1H { .D }, /Z, [, .D, ] (ffa0e000/c4806000) */ //#define IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* LDFF1W { .D }, /Z, [, .D, ] (ffa0e000/c5006000) */ //#define IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs) /* * * Instruction Set & Groups: sve_mem_64b_gld_vs2 / sve_mem64 / sve / A64 * */ /* LD1SB { .D }, /Z, [, .D] (ffe0e000/c4408000) */ //#define IEM_INSTR_IMPL_A64__ld1sb_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm) /* LD1SH { .D }, /Z, [, .D] (ffe0e000/c4c08000) */ //#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm) /* LD1SW { .D }, /Z, [, .D] (ffe0e000/c5408000) */ //#define IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm) /* LD1D { .D }, /Z, [, .D] (ffe0e000/c5c0c000) */ //#define IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, Zm) /* LD1B { .D }, /Z, [, .D] (ffe0e000/c440c000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm) /* LD1H { .D }, /Z, [, .D] (ffe0e000/c4c0c000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm) /* LD1W { .D }, /Z, [, .D] (ffe0e000/c540c000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm) /* LDFF1SB { .D }, /Z, [, .D] (ffe0e000/c440a000) */ //#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm) /* LDFF1SH { .D }, /Z, [, .D] (ffe0e000/c4c0a000) */ //#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm) /* LDFF1SW { .D }, /Z, [, .D] (ffe0e000/c540a000) */ //#define IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm) /* LDFF1D { .D }, /Z, [, .D] (ffe0e000/c5c0e000) */ //#define IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, Zm) /* LDFF1B { .D }, /Z, [, .D] (ffe0e000/c440e000) */ //#define IEM_INSTR_IMPL_A64__ldff1b_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm) /* LDFF1H { .D }, /Z, [, .D] (ffe0e000/c4c0e000) */ //#define IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm) /* LDFF1W { .D }, /Z, [, .D] (ffe0e000/c540e000) */ //#define IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm) /* * * Instruction Set & Groups: sve_mem_64b_gldnt_vs / sve_mem64 / sve / A64 * */ /* LDNT1SB { .D }, /Z, [.D{, }] (ffe0e000/c4008000) */ //#define IEM_INSTR_IMPL_A64__ldnt1sb_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm) /* LDNT1SH { .D }, /Z, [.D{, }] (ffe0e000/c4808000) */ //#define IEM_INSTR_IMPL_A64__ldnt1sh_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm) /* LDNT1SW { .D }, /Z, [.D{, }] (ffe0e000/c5008000) */ //#define IEM_INSTR_IMPL_A64__ldnt1sw_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm) /* LDNT1D { .D }, /Z, [.D{, }] (ffe0e000/c580c000) */ //#define IEM_INSTR_IMPL_A64__ldnt1d_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm) /* LDNT1B { .D }, /Z, [.D{, }] (ffe0e000/c400c000) */ //#define IEM_INSTR_IMPL_A64__ldnt1b_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm) /* LDNT1H { .D }, /Z, [.D{, }] (ffe0e000/c480c000) */ //#define IEM_INSTR_IMPL_A64__ldnt1h_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm) /* LDNT1W { .D }, /Z, [.D{, }] (ffe0e000/c500c000) */ //#define IEM_INSTR_IMPL_A64__ldnt1w_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm) /* * * Instruction Set & Groups: sve_mem_64b_gldq_vs / sve_mem64 / sve / A64 * */ /* LD1Q { .Q }, /Z, [.D{, }] (ffe0e000/c400a000) */ //#define IEM_INSTR_IMPL_A64__ld1q_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm) /* * * Instruction Set & Groups: sve_mem_64b_prfm_sv / sve_mem64 / sve / A64 * */ /* PRFB , , [, .D, ] (ffa0e010/c4200000) */ //#define IEM_INSTR_IMPL_A64__prfb_i_p_bz_d_x32_scaled(prfop, Rn, Pg, msz, Zm, xs) /* PRFH , , [, .D, #1] (ffa0e010/c4202000) */ //#define IEM_INSTR_IMPL_A64__prfh_i_p_bz_d_x32_scaled(prfop, Rn, Pg, msz, Zm, xs) /* PRFW , , [, .D, #2] (ffa0e010/c4204000) */ //#define IEM_INSTR_IMPL_A64__prfw_i_p_bz_d_x32_scaled(prfop, Rn, Pg, msz, Zm, xs) /* PRFD , , [, .D, #3] (ffa0e010/c4206000) */ //#define IEM_INSTR_IMPL_A64__prfd_i_p_bz_d_x32_scaled(prfop, Rn, Pg, msz, Zm, xs) /* * * Instruction Set & Groups: sve_mem_64b_prfm_sv2 / sve_mem64 / sve / A64 * */ /* PRFB , , [, .D] (ffe0e010/c4608000) */ //#define IEM_INSTR_IMPL_A64__prfb_i_p_bz_d_64_scaled(prfop, Rn, Pg, msz, Zm) /* PRFH , , [, .D, LSL #1] (ffe0e010/c460a000) */ //#define IEM_INSTR_IMPL_A64__prfh_i_p_bz_d_64_scaled(prfop, Rn, Pg, msz, Zm) /* PRFW , , [, .D, LSL #2] (ffe0e010/c460c000) */ //#define IEM_INSTR_IMPL_A64__prfw_i_p_bz_d_64_scaled(prfop, Rn, Pg, msz, Zm) /* PRFD , , [, .D, LSL #3] (ffe0e010/c460e000) */ //#define IEM_INSTR_IMPL_A64__prfd_i_p_bz_d_64_scaled(prfop, Rn, Pg, msz, Zm) /* * * Instruction Set & Groups: sve_mem_64b_prfm_vi / sve_mem64 / sve / A64 * */ /* PRFB , , [.D{, #}] (ffe0e010/c400e000) */ //#define IEM_INSTR_IMPL_A64__prfb_i_p_ai_d(prfop, Zn, Pg, imm5) /* PRFH , , [.D{, #}] (ffe0e010/c480e000) */ //#define IEM_INSTR_IMPL_A64__prfh_i_p_ai_d(prfop, Zn, Pg, imm5) /* PRFW , , [.D{, #}] (ffe0e010/c500e000) */ //#define IEM_INSTR_IMPL_A64__prfw_i_p_ai_d(prfop, Zn, Pg, imm5) /* PRFD , , [.D{, #}] (ffe0e010/c580e000) */ //#define IEM_INSTR_IMPL_A64__prfd_i_p_ai_d(prfop, Zn, Pg, imm5) /* * * Instruction Set & Groups: sve_mem_cld_si / sve_memcld / sve / A64 * */ /* LD1B { .B }, /Z, [{, #, MUL VL}] (fff0e000/a400a000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u8(Zt, Rn, Pg, imm4, dtype) /* LD1B { .H }, /Z, [{, #, MUL VL}] (fff0e000/a420a000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u16(Zt, Rn, Pg, imm4, dtype) /* LD1B { .S }, /Z, [{, #, MUL VL}] (fff0e000/a440a000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype) /* LD1B { .D }, /Z, [{, #, MUL VL}] (fff0e000/a460a000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype) /* LD1SW { .D }, /Z, [{, #, MUL VL}] (fff0e000/a480a000) */ //#define IEM_INSTR_IMPL_A64__ld1sw_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype) /* LD1H { .H }, /Z, [{, #, MUL VL}] (fff0e000/a4a0a000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_bi_u16(Zt, Rn, Pg, imm4, dtype) /* LD1H { .S }, /Z, [{, #, MUL VL}] (fff0e000/a4c0a000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype) /* LD1H { .D }, /Z, [{, #, MUL VL}] (fff0e000/a4e0a000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype) /* LD1SH { .D }, /Z, [{, #, MUL VL}] (fff0e000/a500a000) */ //#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype) /* LD1SH { .S }, /Z, [{, #, MUL VL}] (fff0e000/a520a000) */ //#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bi_s32(Zt, Rn, Pg, imm4, dtype) /* LD1W { .S }, /Z, [{, #, MUL VL}] (fff0e000/a540a000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype) /* LD1W { .D }, /Z, [{, #, MUL VL}] (fff0e000/a560a000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype) /* LD1SB { .D }, /Z, [{, #, MUL VL}] (fff0e000/a580a000) */ //#define IEM_INSTR_IMPL_A64__ld1sb_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype) /* LD1SB { .S }, /Z, [{, #, MUL VL}] (fff0e000/a5a0a000) */ //#define IEM_INSTR_IMPL_A64__ld1sb_z_p_bi_s32(Zt, Rn, Pg, imm4, dtype) /* LD1SB { .H }, /Z, [{, #, MUL VL}] (fff0e000/a5c0a000) */ //#define IEM_INSTR_IMPL_A64__ld1sb_z_p_bi_s16(Zt, Rn, Pg, imm4, dtype) /* LD1D { .D }, /Z, [{, #, MUL VL}] (fff0e000/a5e0a000) */ //#define IEM_INSTR_IMPL_A64__ld1d_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype) /* * * Instruction Set & Groups: sve_mem_cld_si_q / sve_memcld / sve / A64 * */ /* LD1W { .Q }, /Z, [{, #, MUL VL}] (fff0e000/a5102000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_bi_u128(Zt, Rn, Pg, imm4) /* LD1D { .Q }, /Z, [{, #, MUL VL}] (fff0e000/a5902000) */ //#define IEM_INSTR_IMPL_A64__ld1d_z_p_bi_u128(Zt, Rn, Pg, imm4) /* * * Instruction Set & Groups: sve_mem_cld_ss / sve_memcld / sve / A64 * */ /* LD1B { .B }, /Z, [, ] (ffe0e000/a4004000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_br_u8(Zt, Rn, Pg, Rm, dtype) /* LD1B { .H }, /Z, [, ] (ffe0e000/a4204000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_br_u16(Zt, Rn, Pg, Rm, dtype) /* LD1B { .S }, /Z, [, ] (ffe0e000/a4404000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_br_u32(Zt, Rn, Pg, Rm, dtype) /* LD1B { .D }, /Z, [, ] (ffe0e000/a4604000) */ //#define IEM_INSTR_IMPL_A64__ld1b_z_p_br_u64(Zt, Rn, Pg, Rm, dtype) /* LD1SW { .D }, /Z, [, , LSL #2] (ffe0e000/a4804000) */ //#define IEM_INSTR_IMPL_A64__ld1sw_z_p_br_s64(Zt, Rn, Pg, Rm, dtype) /* LD1H { .H }, /Z, [, , LSL #1] (ffe0e000/a4a04000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_br_u16(Zt, Rn, Pg, Rm, dtype) /* LD1H { .S }, /Z, [, , LSL #1] (ffe0e000/a4c04000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_br_u32(Zt, Rn, Pg, Rm, dtype) /* LD1H { .D }, /Z, [, , LSL #1] (ffe0e000/a4e04000) */ //#define IEM_INSTR_IMPL_A64__ld1h_z_p_br_u64(Zt, Rn, Pg, Rm, dtype) /* LD1SH { .D }, /Z, [, , LSL #1] (ffe0e000/a5004000) */ //#define IEM_INSTR_IMPL_A64__ld1sh_z_p_br_s64(Zt, Rn, Pg, Rm, dtype) /* LD1SH { .S }, /Z, [, , LSL #1] (ffe0e000/a5204000) */ //#define IEM_INSTR_IMPL_A64__ld1sh_z_p_br_s32(Zt, Rn, Pg, Rm, dtype) /* LD1W { .S }, /Z, [, , LSL #2] (ffe0e000/a5404000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_br_u32(Zt, Rn, Pg, Rm, dtype) /* LD1W { .D }, /Z, [, , LSL #2] (ffe0e000/a5604000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_br_u64(Zt, Rn, Pg, Rm, dtype) /* LD1SB { .D }, /Z, [, ] (ffe0e000/a5804000) */ //#define IEM_INSTR_IMPL_A64__ld1sb_z_p_br_s64(Zt, Rn, Pg, Rm, dtype) /* LD1SB { .S }, /Z, [, ] (ffe0e000/a5a04000) */ //#define IEM_INSTR_IMPL_A64__ld1sb_z_p_br_s32(Zt, Rn, Pg, Rm, dtype) /* LD1SB { .H }, /Z, [, ] (ffe0e000/a5c04000) */ //#define IEM_INSTR_IMPL_A64__ld1sb_z_p_br_s16(Zt, Rn, Pg, Rm, dtype) /* LD1D { .D }, /Z, [, , LSL #3] (ffe0e000/a5e04000) */ //#define IEM_INSTR_IMPL_A64__ld1d_z_p_br_u64(Zt, Rn, Pg, Rm, dtype) /* * * Instruction Set & Groups: sve_mem_cld_ss_q / sve_memcld / sve / A64 * */ /* LD1W { .Q }, /Z, [, , LSL #2] (ffe0e000/a5008000) */ //#define IEM_INSTR_IMPL_A64__ld1w_z_p_br_u128(Zt, Rn, Pg, Rm) /* LD1D { .Q }, /Z, [, , LSL #3] (ffe0e000/a5808000) */ //#define IEM_INSTR_IMPL_A64__ld1d_z_p_br_u128(Zt, Rn, Pg, Rm) /* * * Instruction Set & Groups: sve_mem_cldff_ss / sve_memcld / sve / A64 * */ /* LDFF1B { .B }, /Z, [{, }] (ffe0e000/a4006000) */ //#define IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u8(Zt, Rn, Pg, Rm, dtype) /* LDFF1B { .H }, /Z, [{, }] (ffe0e000/a4206000) */ //#define IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u16(Zt, Rn, Pg, Rm, dtype) /* LDFF1B { .S }, /Z, [{, }] (ffe0e000/a4406000) */ //#define IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u32(Zt, Rn, Pg, Rm, dtype) /* LDFF1B { .D }, /Z, [{, }] (ffe0e000/a4606000) */ //#define IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u64(Zt, Rn, Pg, Rm, dtype) /* LDFF1SW { .D }, /Z, [{, , LSL #2}] (ffe0e000/a4806000) */ //#define IEM_INSTR_IMPL_A64__ldff1sw_z_p_br_s64(Zt, Rn, Pg, Rm, dtype) /* LDFF1H { .H }, /Z, [{, , LSL #1}] (ffe0e000/a4a06000) */ //#define IEM_INSTR_IMPL_A64__ldff1h_z_p_br_u16(Zt, Rn, Pg, Rm, dtype) /* LDFF1H { .S }, /Z, [{, , LSL #1}] (ffe0e000/a4c06000) */ //#define IEM_INSTR_IMPL_A64__ldff1h_z_p_br_u32(Zt, Rn, Pg, Rm, dtype) /* LDFF1H { .D }, /Z, [{, , LSL #1}] (ffe0e000/a4e06000) */ //#define IEM_INSTR_IMPL_A64__ldff1h_z_p_br_u64(Zt, Rn, Pg, Rm, dtype) /* LDFF1SH { .D }, /Z, [{, , LSL #1}] (ffe0e000/a5006000) */ //#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_br_s64(Zt, Rn, Pg, Rm, dtype) /* LDFF1SH { .S }, /Z, [{, , LSL #1}] (ffe0e000/a5206000) */ //#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_br_s32(Zt, Rn, Pg, Rm, dtype) /* LDFF1W { .S }, /Z, [{, , LSL #2}] (ffe0e000/a5406000) */ //#define IEM_INSTR_IMPL_A64__ldff1w_z_p_br_u32(Zt, Rn, Pg, Rm, dtype) /* LDFF1W { .D }, /Z, [{, , LSL #2}] (ffe0e000/a5606000) */ //#define IEM_INSTR_IMPL_A64__ldff1w_z_p_br_u64(Zt, Rn, Pg, Rm, dtype) /* LDFF1SB { .D }, /Z, [{, }] (ffe0e000/a5806000) */ //#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_br_s64(Zt, Rn, Pg, Rm, dtype) /* LDFF1SB { .S }, /Z, [{, }] (ffe0e000/a5a06000) */ //#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_br_s32(Zt, Rn, Pg, Rm, dtype) /* LDFF1SB { .H }, /Z, [{, }] (ffe0e000/a5c06000) */ //#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_br_s16(Zt, Rn, Pg, Rm, dtype) /* LDFF1D { .D }, /Z, [{, , LSL #3}] (ffe0e000/a5e06000) */ //#define IEM_INSTR_IMPL_A64__ldff1d_z_p_br_u64(Zt, Rn, Pg, Rm, dtype) /* * * Instruction Set & Groups: sve_mem_cldnf_si / sve_memcld / sve / A64 * */ /* LDNF1B { .B }, /Z, [{, #, MUL VL}] (fff0e000/a410a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u8(Zt, Rn, Pg, imm4, dtype) /* LDNF1B { .H }, /Z, [{, #, MUL VL}] (fff0e000/a430a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u16(Zt, Rn, Pg, imm4, dtype) /* LDNF1B { .S }, /Z, [{, #, MUL VL}] (fff0e000/a450a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype) /* LDNF1B { .D }, /Z, [{, #, MUL VL}] (fff0e000/a470a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype) /* LDNF1SW { .D }, /Z, [{, #, MUL VL}] (fff0e000/a490a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1sw_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype) /* LDNF1H { .H }, /Z, [{, #, MUL VL}] (fff0e000/a4b0a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1h_z_p_bi_u16(Zt, Rn, Pg, imm4, dtype) /* LDNF1H { .S }, /Z, [{, #, MUL VL}] (fff0e000/a4d0a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1h_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype) /* LDNF1H { .D }, /Z, [{, #, MUL VL}] (fff0e000/a4f0a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1h_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype) /* LDNF1SH { .D }, /Z, [{, #, MUL VL}] (fff0e000/a510a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1sh_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype) /* LDNF1SH { .S }, /Z, [{, #, MUL VL}] (fff0e000/a530a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1sh_z_p_bi_s32(Zt, Rn, Pg, imm4, dtype) /* LDNF1W { .S }, /Z, [{, #, MUL VL}] (fff0e000/a550a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1w_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype) /* LDNF1W { .D }, /Z, [{, #, MUL VL}] (fff0e000/a570a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1w_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype) /* LDNF1SB { .D }, /Z, [{, #, MUL VL}] (fff0e000/a590a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1sb_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype) /* LDNF1SB { .S }, /Z, [{, #, MUL VL}] (fff0e000/a5b0a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1sb_z_p_bi_s32(Zt, Rn, Pg, imm4, dtype) /* LDNF1SB { .H }, /Z, [{, #, MUL VL}] (fff0e000/a5d0a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1sb_z_p_bi_s16(Zt, Rn, Pg, imm4, dtype) /* LDNF1D { .D }, /Z, [{, #, MUL VL}] (fff0e000/a5f0a000) */ //#define IEM_INSTR_IMPL_A64__ldnf1d_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype) /* * * Instruction Set & Groups: sve_mem_cldnt_si / sve_memcld / sve / A64 * */ /* LDNT1B { .B }, /Z, [{, #, MUL VL}] (fff0e000/a400e000) */ //#define IEM_INSTR_IMPL_A64__ldnt1b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LDNT1H { .H }, /Z, [{, #, MUL VL}] (fff0e000/a480e000) */ //#define IEM_INSTR_IMPL_A64__ldnt1h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LDNT1W { .S }, /Z, [{, #, MUL VL}] (fff0e000/a500e000) */ //#define IEM_INSTR_IMPL_A64__ldnt1w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LDNT1D { .D }, /Z, [{, #, MUL VL}] (fff0e000/a580e000) */ //#define IEM_INSTR_IMPL_A64__ldnt1d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* * * Instruction Set & Groups: sve_mem_cldnt_ss / sve_memcld / sve / A64 * */ /* LDNT1B { .B }, /Z, [, ] (ffe0e000/a400c000) */ //#define IEM_INSTR_IMPL_A64__ldnt1b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LDNT1H { .H }, /Z, [, , LSL #1] (ffe0e000/a480c000) */ //#define IEM_INSTR_IMPL_A64__ldnt1h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LDNT1W { .S }, /Z, [, , LSL #2] (ffe0e000/a500c000) */ //#define IEM_INSTR_IMPL_A64__ldnt1w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LDNT1D { .D }, /Z, [, , LSL #3] (ffe0e000/a580c000) */ //#define IEM_INSTR_IMPL_A64__ldnt1d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* * * Instruction Set & Groups: sve_mem_cst_si / sve_memst_si / sve / A64 * */ /* ST1B { . }, , [{, #, MUL VL}] (ff90e000/e400e000) */ //#define IEM_INSTR_IMPL_A64__st1b_z_p_bi(Zt, Rn, Pg, imm4, size) /* ST1H { . }, , [{, #, MUL VL}] (ff90e000/e480e000) */ //#define IEM_INSTR_IMPL_A64__st1h_z_p_bi(Zt, Rn, Pg, imm4, size) /* ST1W { .Q }, , [{, #, MUL VL}] (fff0e000/e500e000) */ //#define IEM_INSTR_IMPL_A64__st1w_z_p_bi_u128(Zt, Rn, Pg, imm4) /* ST1W { . }, , [{, #, MUL VL}] (ffd0e000/e540e000) */ //#define IEM_INSTR_IMPL_A64__st1w_z_p_bi(Zt, Rn, Pg, imm4, sz) /* ST1D { .Q }, , [{, #, MUL VL}] (fff0e000/e5c0e000) */ //#define IEM_INSTR_IMPL_A64__st1d_z_p_bi_u128(Zt, Rn, Pg, imm4) /* ST1D { .D }, , [{, #, MUL VL}] (fff0e000/e5e0e000) */ //#define IEM_INSTR_IMPL_A64__st1d_z_p_bi(Zt, Rn, Pg, imm4) /* * * Instruction Set & Groups: sve_mem_cst_ss / sve_memst_cs / sve / A64 * */ /* ST1B { . }, , [, ] (ff80e000/e4004000) */ //#define IEM_INSTR_IMPL_A64__st1b_z_p_br(Zt, Rn, Pg, Rm, size) /* ST1H { . }, , [, , LSL #1] (ff80e000/e4804000) */ //#define IEM_INSTR_IMPL_A64__st1h_z_p_br(Zt, Rn, Pg, Rm, size) /* ST1W { .Q }, , [, , LSL #2] (ffe0e000/e5004000) */ //#define IEM_INSTR_IMPL_A64__st1w_z_p_br_u128(Zt, Rn, Pg, Rm) /* ST1W { . }, , [, , LSL #2] (ffc0e000/e5404000) */ //#define IEM_INSTR_IMPL_A64__st1w_z_p_br(Zt, Rn, Pg, Rm, sz) /* ST1D { .Q }, , [, , LSL #3] (ffe0e000/e5c04000) */ //#define IEM_INSTR_IMPL_A64__st1d_z_p_br_u128(Zt, Rn, Pg, Rm) /* ST1D { .D }, , [, , LSL #3] (ffe0e000/e5e04000) */ //#define IEM_INSTR_IMPL_A64__st1d_z_p_br(Zt, Rn, Pg, Rm) /* * * Instruction Set & Groups: sve_mem_cstnt_si / sve_memst_si / sve / A64 * */ /* STNT1B { .B }, , [{, #, MUL VL}] (fff0e000/e410e000) */ //#define IEM_INSTR_IMPL_A64__stnt1b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* STNT1H { .H }, , [{, #, MUL VL}] (fff0e000/e490e000) */ //#define IEM_INSTR_IMPL_A64__stnt1h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* STNT1W { .S }, , [{, #, MUL VL}] (fff0e000/e510e000) */ //#define IEM_INSTR_IMPL_A64__stnt1w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* STNT1D { .D }, , [{, #, MUL VL}] (fff0e000/e590e000) */ //#define IEM_INSTR_IMPL_A64__stnt1d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* * * Instruction Set & Groups: sve_mem_cstnt_ss / sve_memcst_nt / sve / A64 * */ /* STNT1B { .B }, , [, ] (ffe0e000/e4006000) */ //#define IEM_INSTR_IMPL_A64__stnt1b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* STNT1H { .H }, , [, , LSL #1] (ffe0e000/e4806000) */ //#define IEM_INSTR_IMPL_A64__stnt1h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* STNT1W { .S }, , [, , LSL #2] (ffe0e000/e5006000) */ //#define IEM_INSTR_IMPL_A64__stnt1w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* STNT1D { .D }, , [, , LSL #3] (ffe0e000/e5806000) */ //#define IEM_INSTR_IMPL_A64__stnt1d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* * * Instruction Set & Groups: sve_mem_eld_si / sve_memcld / sve / A64 * */ /* LD2B { .B, .B }, /Z, [{, #, MUL VL}] (fff0e000/a420e000) */ //#define IEM_INSTR_IMPL_A64__ld2b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LD3B { .B, .B, .B }, /Z, [{, #, MUL VL}] (fff0e000/a440e000) */ //#define IEM_INSTR_IMPL_A64__ld3b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LD4B { .B, .B, .B, .B }, /Z, [{, #, MUL VL}] (fff0e000/a460e000) */ //#define IEM_INSTR_IMPL_A64__ld4b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LD2H { .H, .H }, /Z, [{, #, MUL VL}] (fff0e000/a4a0e000) */ //#define IEM_INSTR_IMPL_A64__ld2h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LD3H { .H, .H, .H }, /Z, [{, #, MUL VL}] (fff0e000/a4c0e000) */ //#define IEM_INSTR_IMPL_A64__ld3h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LD4H { .H, .H, .H, .H }, /Z, [{, #, MUL VL}] (fff0e000/a4e0e000) */ //#define IEM_INSTR_IMPL_A64__ld4h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LD2W { .S, .S }, /Z, [{, #, MUL VL}] (fff0e000/a520e000) */ //#define IEM_INSTR_IMPL_A64__ld2w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LD3W { .S, .S, .S }, /Z, [{, #, MUL VL}] (fff0e000/a540e000) */ //#define IEM_INSTR_IMPL_A64__ld3w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LD4W { .S, .S, .S, .S }, /Z, [{, #, MUL VL}] (fff0e000/a560e000) */ //#define IEM_INSTR_IMPL_A64__ld4w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LD2D { .D, .D }, /Z, [{, #, MUL VL}] (fff0e000/a5a0e000) */ //#define IEM_INSTR_IMPL_A64__ld2d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LD3D { .D, .D, .D }, /Z, [{, #, MUL VL}] (fff0e000/a5c0e000) */ //#define IEM_INSTR_IMPL_A64__ld3d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* LD4D { .D, .D, .D, .D }, /Z, [{, #, MUL VL}] (fff0e000/a5e0e000) */ //#define IEM_INSTR_IMPL_A64__ld4d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* * * Instruction Set & Groups: sve_mem_eld_ss / sve_memcld / sve / A64 * */ /* LD2B { .B, .B }, /Z, [, ] (ffe0e000/a420c000) */ //#define IEM_INSTR_IMPL_A64__ld2b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LD3B { .B, .B, .B }, /Z, [, ] (ffe0e000/a440c000) */ //#define IEM_INSTR_IMPL_A64__ld3b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LD4B { .B, .B, .B, .B }, /Z, [, ] (ffe0e000/a460c000) */ //#define IEM_INSTR_IMPL_A64__ld4b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LD2H { .H, .H }, /Z, [, , LSL #1] (ffe0e000/a4a0c000) */ //#define IEM_INSTR_IMPL_A64__ld2h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LD3H { .H, .H, .H }, /Z, [, , LSL #1] (ffe0e000/a4c0c000) */ //#define IEM_INSTR_IMPL_A64__ld3h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LD4H { .H, .H, .H, .H }, /Z, [, , LSL #1] (ffe0e000/a4e0c000) */ //#define IEM_INSTR_IMPL_A64__ld4h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LD2W { .S, .S }, /Z, [, , LSL #2] (ffe0e000/a520c000) */ //#define IEM_INSTR_IMPL_A64__ld2w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LD3W { .S, .S, .S }, /Z, [, , LSL #2] (ffe0e000/a540c000) */ //#define IEM_INSTR_IMPL_A64__ld3w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LD4W { .S, .S, .S, .S }, /Z, [, , LSL #2] (ffe0e000/a560c000) */ //#define IEM_INSTR_IMPL_A64__ld4w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LD2D { .D, .D }, /Z, [, , LSL #3] (ffe0e000/a5a0c000) */ //#define IEM_INSTR_IMPL_A64__ld2d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LD3D { .D, .D, .D }, /Z, [, , LSL #3] (ffe0e000/a5c0c000) */ //#define IEM_INSTR_IMPL_A64__ld3d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* LD4D { .D, .D, .D, .D }, /Z, [, , LSL #3] (ffe0e000/a5e0c000) */ //#define IEM_INSTR_IMPL_A64__ld4d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* * * Instruction Set & Groups: sve_mem_eldq_si / sve_memcld / sve / A64 * */ /* LD2Q { .Q, .Q }, /Z, [{, #, MUL VL}] (fff0e000/a490e000) */ //#define IEM_INSTR_IMPL_A64__ld2q_z_p_bi_contiguous(Zt, Rn, Pg, imm4) /* LD3Q { .Q, .Q, .Q }, /Z, [{, #, MUL VL}] (fff0e000/a510e000) */ //#define IEM_INSTR_IMPL_A64__ld3q_z_p_bi_contiguous(Zt, Rn, Pg, imm4) /* LD4Q { .Q, .Q, .Q, .Q }, /Z, [{, #, MUL VL}] (fff0e000/a590e000) */ //#define IEM_INSTR_IMPL_A64__ld4q_z_p_bi_contiguous(Zt, Rn, Pg, imm4) /* * * Instruction Set & Groups: sve_mem_eldq_ss / sve_memcld / sve / A64 * */ /* LD2Q { .Q, .Q }, /Z, [, , LSL #4] (ffe0e000/a4a08000) */ //#define IEM_INSTR_IMPL_A64__ld2q_z_p_br_contiguous(Zt, Rn, Pg, Rm) /* LD3Q { .Q, .Q, .Q }, /Z, [, , LSL #4] (ffe0e000/a5208000) */ //#define IEM_INSTR_IMPL_A64__ld3q_z_p_br_contiguous(Zt, Rn, Pg, Rm) /* LD4Q { .Q, .Q, .Q, .Q }, /Z, [, , LSL #4] (ffe0e000/a5a08000) */ //#define IEM_INSTR_IMPL_A64__ld4q_z_p_br_contiguous(Zt, Rn, Pg, Rm) /* * * Instruction Set & Groups: sve_mem_est_si / sve_memst_si / sve / A64 * */ /* ST2B { .B, .B }, , [{, #, MUL VL}] (fff0e000/e430e000) */ //#define IEM_INSTR_IMPL_A64__st2b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* ST3B { .B, .B, .B }, , [{, #, MUL VL}] (fff0e000/e450e000) */ //#define IEM_INSTR_IMPL_A64__st3b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* ST4B { .B, .B, .B, .B }, , [{, #, MUL VL}] (fff0e000/e470e000) */ //#define IEM_INSTR_IMPL_A64__st4b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* ST2H { .H, .H }, , [{, #, MUL VL}] (fff0e000/e4b0e000) */ //#define IEM_INSTR_IMPL_A64__st2h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* ST3H { .H, .H, .H }, , [{, #, MUL VL}] (fff0e000/e4d0e000) */ //#define IEM_INSTR_IMPL_A64__st3h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* ST4H { .H, .H, .H, .H }, , [{, #, MUL VL}] (fff0e000/e4f0e000) */ //#define IEM_INSTR_IMPL_A64__st4h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* ST2W { .S, .S }, , [{, #, MUL VL}] (fff0e000/e530e000) */ //#define IEM_INSTR_IMPL_A64__st2w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* ST3W { .S, .S, .S }, , [{, #, MUL VL}] (fff0e000/e550e000) */ //#define IEM_INSTR_IMPL_A64__st3w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* ST4W { .S, .S, .S, .S }, , [{, #, MUL VL}] (fff0e000/e570e000) */ //#define IEM_INSTR_IMPL_A64__st4w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* ST2D { .D, .D }, , [{, #, MUL VL}] (fff0e000/e5b0e000) */ //#define IEM_INSTR_IMPL_A64__st2d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* ST3D { .D, .D, .D }, , [{, #, MUL VL}] (fff0e000/e5d0e000) */ //#define IEM_INSTR_IMPL_A64__st3d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* ST4D { .D, .D, .D, .D }, , [{, #, MUL VL}] (fff0e000/e5f0e000) */ //#define IEM_INSTR_IMPL_A64__st4d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz) /* * * Instruction Set & Groups: sve_mem_est_ss / sve_memcst_nt / sve / A64 * */ /* ST2B { .B, .B }, , [, ] (ffe0e000/e4206000) */ //#define IEM_INSTR_IMPL_A64__st2b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* ST3B { .B, .B, .B }, , [, ] (ffe0e000/e4406000) */ //#define IEM_INSTR_IMPL_A64__st3b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* ST4B { .B, .B, .B, .B }, , [, ] (ffe0e000/e4606000) */ //#define IEM_INSTR_IMPL_A64__st4b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* ST2H { .H, .H }, , [, , LSL #1] (ffe0e000/e4a06000) */ //#define IEM_INSTR_IMPL_A64__st2h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* ST3H { .H, .H, .H }, , [, , LSL #1] (ffe0e000/e4c06000) */ //#define IEM_INSTR_IMPL_A64__st3h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* ST4H { .H, .H, .H, .H }, , [, , LSL #1] (ffe0e000/e4e06000) */ //#define IEM_INSTR_IMPL_A64__st4h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* ST2W { .S, .S }, , [, , LSL #2] (ffe0e000/e5206000) */ //#define IEM_INSTR_IMPL_A64__st2w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* ST3W { .S, .S, .S }, , [, , LSL #2] (ffe0e000/e5406000) */ //#define IEM_INSTR_IMPL_A64__st3w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* ST4W { .S, .S, .S, .S }, , [, , LSL #2] (ffe0e000/e5606000) */ //#define IEM_INSTR_IMPL_A64__st4w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* ST2D { .D, .D }, , [, , LSL #3] (ffe0e000/e5a06000) */ //#define IEM_INSTR_IMPL_A64__st2d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* ST3D { .D, .D, .D }, , [, , LSL #3] (ffe0e000/e5c06000) */ //#define IEM_INSTR_IMPL_A64__st3d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* ST4D { .D, .D, .D, .D }, , [, , LSL #3] (ffe0e000/e5e06000) */ //#define IEM_INSTR_IMPL_A64__st4d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz) /* * * Instruction Set & Groups: sve_mem_estq_si / sve_memst_cs / sve / A64 * */ /* ST2Q { .Q, .Q }, , [{, #, MUL VL}] (fff0e000/e4400000) */ //#define IEM_INSTR_IMPL_A64__st2q_z_p_bi_contiguous(Zt, Rn, Pg, imm4) /* ST3Q { .Q, .Q, .Q }, , [{, #, MUL VL}] (fff0e000/e4800000) */ //#define IEM_INSTR_IMPL_A64__st3q_z_p_bi_contiguous(Zt, Rn, Pg, imm4) /* ST4Q { .Q, .Q, .Q, .Q }, , [{, #, MUL VL}] (fff0e000/e4c00000) */ //#define IEM_INSTR_IMPL_A64__st4q_z_p_bi_contiguous(Zt, Rn, Pg, imm4) /* * * Instruction Set & Groups: sve_mem_estq_ss / sve_memst_cs / sve / A64 * */ /* ST2Q { .Q, .Q }, , [, , LSL #4] (ffe0e000/e4600000) */ //#define IEM_INSTR_IMPL_A64__st2q_z_p_br_contiguous(Zt, Rn, Pg, Rm) /* ST3Q { .Q, .Q, .Q }, , [, , LSL #4] (ffe0e000/e4a00000) */ //#define IEM_INSTR_IMPL_A64__st3q_z_p_br_contiguous(Zt, Rn, Pg, Rm) /* ST4Q { .Q, .Q, .Q, .Q }, , [, , LSL #4] (ffe0e000/e4e00000) */ //#define IEM_INSTR_IMPL_A64__st4q_z_p_br_contiguous(Zt, Rn, Pg, Rm) /* * * Instruction Set & Groups: sve_mem_ld_dup / sve_mem32 / sve / A64 * */ /* LD1RB { .B }, /Z, [{, #}] (ffc0e000/84408000) */ //#define IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u8(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RB { .H }, /Z, [{, #}] (ffc0e000/8440a000) */ //#define IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u16(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RB { .S }, /Z, [{, #}] (ffc0e000/8440c000) */ //#define IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u32(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RB { .D }, /Z, [{, #}] (ffc0e000/8440e000) */ //#define IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u64(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RSW { .D }, /Z, [{, #}] (ffc0e000/84c08000) */ //#define IEM_INSTR_IMPL_A64__ld1rsw_z_p_bi_s64(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RH { .H }, /Z, [{, #}] (ffc0e000/84c0a000) */ //#define IEM_INSTR_IMPL_A64__ld1rh_z_p_bi_u16(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RH { .S }, /Z, [{, #}] (ffc0e000/84c0c000) */ //#define IEM_INSTR_IMPL_A64__ld1rh_z_p_bi_u32(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RH { .D }, /Z, [{, #}] (ffc0e000/84c0e000) */ //#define IEM_INSTR_IMPL_A64__ld1rh_z_p_bi_u64(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RSH { .D }, /Z, [{, #}] (ffc0e000/85408000) */ //#define IEM_INSTR_IMPL_A64__ld1rsh_z_p_bi_s64(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RSH { .S }, /Z, [{, #}] (ffc0e000/8540a000) */ //#define IEM_INSTR_IMPL_A64__ld1rsh_z_p_bi_s32(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RW { .S }, /Z, [{, #}] (ffc0e000/8540c000) */ //#define IEM_INSTR_IMPL_A64__ld1rw_z_p_bi_u32(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RW { .D }, /Z, [{, #}] (ffc0e000/8540e000) */ //#define IEM_INSTR_IMPL_A64__ld1rw_z_p_bi_u64(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RSB { .D }, /Z, [{, #}] (ffc0e000/85c08000) */ //#define IEM_INSTR_IMPL_A64__ld1rsb_z_p_bi_s64(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RSB { .S }, /Z, [{, #}] (ffc0e000/85c0a000) */ //#define IEM_INSTR_IMPL_A64__ld1rsb_z_p_bi_s32(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RSB { .H }, /Z, [{, #}] (ffc0e000/85c0c000) */ //#define IEM_INSTR_IMPL_A64__ld1rsb_z_p_bi_s16(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* LD1RD { .D }, /Z, [{, #}] (ffc0e000/85c0e000) */ //#define IEM_INSTR_IMPL_A64__ld1rd_z_p_bi_u64(Zt, Rn, Pg, dtypel, imm6, dtypeh) /* * * Instruction Set & Groups: sve_mem_ldqr_si / sve_memcld / sve / A64 * */ /* LD1RQB { .B }, /Z, [{, #}] (fff0e000/a4002000) */ //#define IEM_INSTR_IMPL_A64__ld1rqb_z_p_bi_u8(Zt, Rn, Pg, imm4, ssz, msz) /* LD1ROB { .B }, /Z, [{, #}] (fff0e000/a4202000) */ //#define IEM_INSTR_IMPL_A64__ld1rob_z_p_bi_u8(Zt, Rn, Pg, imm4, ssz, msz) /* LD1RQH { .H }, /Z, [{, #}] (fff0e000/a4802000) */ //#define IEM_INSTR_IMPL_A64__ld1rqh_z_p_bi_u16(Zt, Rn, Pg, imm4, ssz, msz) /* LD1ROH { .H }, /Z, [{, #}] (fff0e000/a4a02000) */ //#define IEM_INSTR_IMPL_A64__ld1roh_z_p_bi_u16(Zt, Rn, Pg, imm4, ssz, msz) /* LD1RQW { .S }, /Z, [{, #}] (fff0e000/a5002000) */ //#define IEM_INSTR_IMPL_A64__ld1rqw_z_p_bi_u32(Zt, Rn, Pg, imm4, ssz, msz) /* LD1ROW { .S }, /Z, [{, #}] (fff0e000/a5202000) */ //#define IEM_INSTR_IMPL_A64__ld1row_z_p_bi_u32(Zt, Rn, Pg, imm4, ssz, msz) /* LD1RQD { .D }, /Z, [{, #}] (fff0e000/a5802000) */ //#define IEM_INSTR_IMPL_A64__ld1rqd_z_p_bi_u64(Zt, Rn, Pg, imm4, ssz, msz) /* LD1ROD { .D }, /Z, [{, #}] (fff0e000/a5a02000) */ //#define IEM_INSTR_IMPL_A64__ld1rod_z_p_bi_u64(Zt, Rn, Pg, imm4, ssz, msz) /* * * Instruction Set & Groups: sve_mem_ldqr_ss / sve_memcld / sve / A64 * */ /* LD1RQB { .B }, /Z, [, ] (ffe0e000/a4000000) */ //#define IEM_INSTR_IMPL_A64__ld1rqb_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz) /* LD1ROB { .B }, /Z, [, ] (ffe0e000/a4200000) */ //#define IEM_INSTR_IMPL_A64__ld1rob_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz) /* LD1RQH { .H }, /Z, [, , LSL #1] (ffe0e000/a4800000) */ //#define IEM_INSTR_IMPL_A64__ld1rqh_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz) /* LD1ROH { .H }, /Z, [, , LSL #1] (ffe0e000/a4a00000) */ //#define IEM_INSTR_IMPL_A64__ld1roh_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz) /* LD1RQW { .S }, /Z, [, , LSL #2] (ffe0e000/a5000000) */ //#define IEM_INSTR_IMPL_A64__ld1rqw_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz) /* LD1ROW { .S }, /Z, [, , LSL #2] (ffe0e000/a5200000) */ //#define IEM_INSTR_IMPL_A64__ld1row_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz) /* LD1RQD { .D }, /Z, [, , LSL #3] (ffe0e000/a5800000) */ //#define IEM_INSTR_IMPL_A64__ld1rqd_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz) /* LD1ROD { .D }, /Z, [, , LSL #3] (ffe0e000/a5a00000) */ //#define IEM_INSTR_IMPL_A64__ld1rod_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz) /* * * Instruction Set & Groups: sve_mem_prfm_si / sve_mem32 / sve / A64 * */ /* PRFB , , [{, #, MUL VL}] (ffc0e010/85c00000) */ //#define IEM_INSTR_IMPL_A64__prfb_i_p_bi_s(prfop, Rn, Pg, imm6) /* PRFH , , [{, #, MUL VL}] (ffc0e010/85c02000) */ //#define IEM_INSTR_IMPL_A64__prfh_i_p_bi_s(prfop, Rn, Pg, imm6) /* PRFW , , [{, #, MUL VL}] (ffc0e010/85c04000) */ //#define IEM_INSTR_IMPL_A64__prfw_i_p_bi_s(prfop, Rn, Pg, imm6) /* PRFD , , [{, #, MUL VL}] (ffc0e010/85c06000) */ //#define IEM_INSTR_IMPL_A64__prfd_i_p_bi_s(prfop, Rn, Pg, imm6) /* * * Instruction Set & Groups: sve_mem_prfm_ss / sve_mem32 / sve / A64 * */ /* PRFB , , [, ] (ffe0e010/8400c000) */ //#define IEM_INSTR_IMPL_A64__prfb_i_p_br_s(prfop, Rn, Pg, Rm) /* PRFH , , [, , LSL #1] (ffe0e010/8480c000) */ //#define IEM_INSTR_IMPL_A64__prfh_i_p_br_s(prfop, Rn, Pg, Rm) /* PRFW , , [, , LSL #2] (ffe0e010/8500c000) */ //#define IEM_INSTR_IMPL_A64__prfw_i_p_br_s(prfop, Rn, Pg, Rm) /* PRFD , , [, , LSL #3] (ffe0e010/8580c000) */ //#define IEM_INSTR_IMPL_A64__prfd_i_p_br_s(prfop, Rn, Pg, Rm) /* * * Instruction Set & Groups: sve_mem_pspill / sve_memst_cs / sve / A64 * */ /* STR , [{, #, MUL VL}] (ffc0e010/e5800000) */ //#define IEM_INSTR_IMPL_A64__str_p_bi(Pt, Rn, imm9l, imm9h) /* * * Instruction Set & Groups: sve_mem_spill / sve_memst_cs / sve / A64 * */ /* STR , [{, #, MUL VL}] (ffc0e000/e5804000) */ //#define IEM_INSTR_IMPL_A64__str_z_bi(Zt, Rn, imm9l, imm9h) /* * * Instruction Set & Groups: sve_mem_sst_sv2 / sve_memst_ss2 / sve / A64 * */ /* ST1H { .D }, , [, .D, LSL #1] (ffe0e000/e4a0a000) */ //#define IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_64_scaled(Zt, Rn, Pg, Zm) /* ST1W { .D }, , [, .D, LSL #2] (ffe0e000/e520a000) */ //#define IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_64_scaled(Zt, Rn, Pg, Zm) /* ST1D { .D }, , [, .D, LSL #3] (ffe0e000/e5a0a000) */ //#define IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_64_scaled(Zt, Rn, Pg, Zm) /* * * Instruction Set & Groups: sve_mem_sst_sv_a / sve_memst_ss / sve / A64 * */ /* ST1H { .D }, , [, .D, #1] (ffe0a000/e4a08000) */ //#define IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_x32_scaled(Zt, Rn, Pg, xs, Zm) /* ST1W { .D }, , [, .D, #2] (ffe0a000/e5208000) */ //#define IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_x32_scaled(Zt, Rn, Pg, xs, Zm) /* ST1D { .D }, , [, .D, #3] (ffe0a000/e5a08000) */ //#define IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_x32_scaled(Zt, Rn, Pg, xs, Zm) /* * * Instruction Set & Groups: sve_mem_sst_sv_b / sve_memst_ss / sve / A64 * */ /* ST1H { .S }, , [, .S, #1] (ffe0a000/e4e08000) */ //#define IEM_INSTR_IMPL_A64__st1h_z_p_bz_s_x32_scaled(Zt, Rn, Pg, xs, Zm) /* ST1W { .S }, , [, .S, #2] (ffe0a000/e5608000) */ //#define IEM_INSTR_IMPL_A64__st1w_z_p_bz_s_x32_scaled(Zt, Rn, Pg, xs, Zm) /* * * Instruction Set & Groups: sve_mem_sst_vi_a / sve_memst_ss2 / sve / A64 * */ /* ST1B { .D }, , [.D{, #}] (ffe0e000/e440a000) */ //#define IEM_INSTR_IMPL_A64__st1b_z_p_ai_d(Zt, Zn, Pg, imm5) /* ST1H { .D }, , [.D{, #}] (ffe0e000/e4c0a000) */ //#define IEM_INSTR_IMPL_A64__st1h_z_p_ai_d(Zt, Zn, Pg, imm5) /* ST1W { .D }, , [.D{, #}] (ffe0e000/e540a000) */ //#define IEM_INSTR_IMPL_A64__st1w_z_p_ai_d(Zt, Zn, Pg, imm5) /* ST1D { .D }, , [.D{, #}] (ffe0e000/e5c0a000) */ //#define IEM_INSTR_IMPL_A64__st1d_z_p_ai_d(Zt, Zn, Pg, imm5) /* * * Instruction Set & Groups: sve_mem_sst_vi_b / sve_memst_ss2 / sve / A64 * */ /* ST1B { .S }, , [.S{, #}] (ffe0e000/e460a000) */ //#define IEM_INSTR_IMPL_A64__st1b_z_p_ai_s(Zt, Zn, Pg, imm5) /* ST1H { .S }, , [.S{, #}] (ffe0e000/e4e0a000) */ //#define IEM_INSTR_IMPL_A64__st1h_z_p_ai_s(Zt, Zn, Pg, imm5) /* ST1W { .S }, , [.S{, #}] (ffe0e000/e560a000) */ //#define IEM_INSTR_IMPL_A64__st1w_z_p_ai_s(Zt, Zn, Pg, imm5) /* * * Instruction Set & Groups: sve_mem_sst_vs2 / sve_memst_ss2 / sve / A64 * */ /* ST1B { .D }, , [, .D] (ffe0e000/e400a000) */ //#define IEM_INSTR_IMPL_A64__st1b_z_p_bz_d_64_unscaled(Zt, Rn, Pg, Zm) /* ST1H { .D }, , [, .D] (ffe0e000/e480a000) */ //#define IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_64_unscaled(Zt, Rn, Pg, Zm) /* ST1W { .D }, , [, .D] (ffe0e000/e500a000) */ //#define IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_64_unscaled(Zt, Rn, Pg, Zm) /* ST1D { .D }, , [, .D] (ffe0e000/e580a000) */ //#define IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_64_unscaled(Zt, Rn, Pg, Zm) /* * * Instruction Set & Groups: sve_mem_sst_vs_a / sve_memst_ss / sve / A64 * */ /* ST1B { .D }, , [, .D, ] (ffe0a000/e4008000) */ //#define IEM_INSTR_IMPL_A64__st1b_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, xs, Zm) /* ST1H { .D }, , [, .D, ] (ffe0a000/e4808000) */ //#define IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, xs, Zm) /* ST1W { .D }, , [, .D, ] (ffe0a000/e5008000) */ //#define IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, xs, Zm) /* ST1D { .D }, , [, .D, ] (ffe0a000/e5808000) */ //#define IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, xs, Zm) /* * * Instruction Set & Groups: sve_mem_sst_vs_b / sve_memst_ss / sve / A64 * */ /* ST1B { .S }, , [, .S, ] (ffe0a000/e4408000) */ //#define IEM_INSTR_IMPL_A64__st1b_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, xs, Zm) /* ST1H { .S }, , [, .S, ] (ffe0a000/e4c08000) */ //#define IEM_INSTR_IMPL_A64__st1h_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, xs, Zm) /* ST1W { .S }, , [, .S, ] (ffe0a000/e5408000) */ //#define IEM_INSTR_IMPL_A64__st1w_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, xs, Zm) /* * * Instruction Set & Groups: sve_mem_sstnt_32b_vs / sve_memsst_nt / sve / A64 * */ /* STNT1B { .S }, , [.S{, }] (ffe0e000/e4402000) */ //#define IEM_INSTR_IMPL_A64__stnt1b_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, Rm) /* STNT1H { .S }, , [.S{, }] (ffe0e000/e4c02000) */ //#define IEM_INSTR_IMPL_A64__stnt1h_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, Rm) /* STNT1W { .S }, , [.S{, }] (ffe0e000/e5402000) */ //#define IEM_INSTR_IMPL_A64__stnt1w_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, Rm) /* * * Instruction Set & Groups: sve_mem_sstnt_64b_vs / sve_memsst_nt / sve / A64 * */ /* STNT1B { .D }, , [.D{, }] (ffe0e000/e4002000) */ //#define IEM_INSTR_IMPL_A64__stnt1b_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm) /* STNT1H { .D }, , [.D{, }] (ffe0e000/e4802000) */ //#define IEM_INSTR_IMPL_A64__stnt1h_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm) /* STNT1W { .D }, , [.D{, }] (ffe0e000/e5002000) */ //#define IEM_INSTR_IMPL_A64__stnt1w_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm) /* STNT1D { .D }, , [.D{, }] (ffe0e000/e5802000) */ //#define IEM_INSTR_IMPL_A64__stnt1d_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm) /* * * Instruction Set & Groups: sve_mem_sstq_64b_vs / sve_memsst_nt / sve / A64 * */ /* ST1Q { .Q }, , [.D{, }] (ffe0e000/e4202000) */ //#define IEM_INSTR_IMPL_A64__st1q_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm) /* * * Instruction Set & Groups: sve_ptr_muladd_unpred_lvl2 / sve_ptr_muladd_unpred / sve / A64 * */ /* MLAPT .D, .D, .D (ffe0fc00/44c0d000) */ //#define IEM_INSTR_IMPL_A64__mlapt_z_zzz(Zda, Zn, Zm) /* MADPT .D, .D, .D (ffe0fc00/44c0d800) */ //#define IEM_INSTR_IMPL_A64__madpt_z_zzz(Zdn, Za, Zm) /* * * Instruction Set & Groups: syspairinstrs / control / A64 * */ /* SYSP #, , , #{, , } (fff80000/d5480000) */ //#define IEM_INSTR_IMPL_A64__SYSP_CR_syspairinstrs(Rt, op2, CRm, CRn, op1) /* * * Instruction Set & Groups: systeminstrs / control / A64 * */ /* SYS #, , , #{, } (fff80000/d5080000) */ //#define IEM_INSTR_IMPL_A64__SYS_CR_systeminstrs(Rt, op2, CRm, CRn, op1) /* SYSL , #, , , # (fff80000/d5280000) */ //#define IEM_INSTR_IMPL_A64__SYSL_RC_systeminstrs(Rt, op2, CRm, CRn, op1) /* * * Instruction Set & Groups: systeminstrswithreg / control / A64 * */ /* WFET (ffffffe0/d5031000) */ //#define IEM_INSTR_IMPL_A64__WFET_only_systeminstrswithreg(Rd) /* WFIT (ffffffe0/d5031020) */ //#define IEM_INSTR_IMPL_A64__WFIT_only_systeminstrswithreg(Rd) /* * * Instruction Set & Groups: systemmove / control / A64 * */ /* MSR { | S____}, (fff00000/d5100000) */ //#define IEM_INSTR_IMPL_A64__MSR_SR_systemmove(Rt, op2, CRm, CRn, op1, o0) /* MRS , { | S____} (fff00000/d5300000) */ //#define IEM_INSTR_IMPL_A64__MRS_RS_systemmove(Rt, op2, CRm, CRn, op1, o0) /* * * Instruction Set & Groups: systemmovepr / control / A64 * */ /* MSRR { | S____}, , (fff00000/d5500000) */ //#define IEM_INSTR_IMPL_A64__MSRR_SR_systemmovepr(Rt, op2, CRm, CRn, op1, o0) /* MRRS , , { | S____} (fff00000/d5700000) */ //#define IEM_INSTR_IMPL_A64__MRRS_RS_systemmovepr(Rt, op2, CRm, CRn, op1, o0) /* * * Instruction Set & Groups: systemresult / control / A64 * */ /* TSTART (ffffffe0/d5233060) */ //#define IEM_INSTR_IMPL_A64__TSTART_BR_systemresult(Rt) /* TTEST (ffffffe0/d5233160) */ //#define IEM_INSTR_IMPL_A64__TTEST_BR_systemresult(Rt) /* * * Instruction Set & Groups: testbranch / control / A64 * */ /* TBZ , #,