/*
 * Autogenerated by $Id: IEMAllIntprA64Tables-armv8.cpp 108958 2025-04-12 00:16:40Z vboxsync $
 * from the open source v9Ap6-A specs, build 406 (5e0a212688c6bd7aee92394b6f5e491b4d0fee1d)
 * dated Sun Dec 15 22:18:44 2024 UTC.
 *
 * Do not edit!
 */

/*
 * Copyright (C) 2025 Oracle and/or its affiliates.
 *
 * This file is part of VirtualBox base platform packages, as
 * available from https://www.virtualbox.org.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation, in version 3 of the
 * License.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <https://www.gnu.org/licenses>.
 *
 * SPDX-License-Identifier: GPL-3.0-only
 */


#define LOG_GROUP LOG_GROUP_IEM
#define VMCPU_INCL_CPUM_GST_CTX
#include "IEMInternal.h"
#include <VBox/vmm/vm.h>
#include "VBox/err.h"

#include "iprt/armv8.h"

#include "IEMMc.h"

#include "IEMAllIntprA64Tables-armv8.h"
#include "IEMAllInstrA64Impl.h"

/** Invalid instruction decoder function. */
FNIEMOP_DEF_1(iemDecodeA64_Invalid, uint32_t, uOpcode)
{
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ac02000: ABS  <Wd>, <Wn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ABS_32_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: ABS_32_dp_1src Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__ABS_32_dp_1src
        IEM_INSTR_IMPL_A64__ABS_32_dp_1src(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/dac02000: ABS  <Xd>, <Xn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ABS_64_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: ABS_64_dp_1src Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__ABS_64_dp_1src
        IEM_INSTR_IMPL_A64__ABS_64_dp_1src(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e20b800: ABS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ABS_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ABS_asimdmisc_R Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ABS_asimdmisc_R
        IEM_INSTR_IMPL_A64__ABS_asimdmisc_R(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ee0b800: ABS  D<d>, D<n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ABS_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ABS_asisdmisc_R Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__ABS_asisdmisc_R
        IEM_INSTR_IMPL_A64__ABS_asisdmisc_R(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3a000000: ADCS  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: addsub_carry, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADCS_32_addsub_carry, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: ADCS_32_addsub_carry Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__ADCS_32_addsub_carry
    IEM_INSTR_IMPL_A64__ADCS_32_addsub_carry(Rd, Rn, Rm);
#else
    RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/ba000000: ADCS  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: addsub_carry, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADCS_64_addsub_carry, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: ADCS_64_addsub_carry Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__ADCS_64_addsub_carry
    IEM_INSTR_IMPL_A64__ADCS_64_addsub_carry(Rd, Rn, Rm);
#else
    RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/1a000000: ADC  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: addsub_carry, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADC_32_addsub_carry, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: ADC_32_addsub_carry Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__ADC_32_addsub_carry
    IEM_INSTR_IMPL_A64__ADC_32_addsub_carry(Rd, Rn, Rm);
#else
    RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/9a000000: ADC  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: addsub_carry, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADC_64_addsub_carry, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: ADC_64_addsub_carry Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__ADC_64_addsub_carry
    IEM_INSTR_IMPL_A64__ADC_64_addsub_carry(Rd, Rn, Rm);
#else
    RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc0c000/91800000: ADDG  <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4>
   Instruction Set: A64  Groups: addsub_immtags, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_ADDG_64_addsub_immtags, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 10) & 0x0000000f;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: ADDG_64_addsub_immtags Rd=%#x Rn=%#x imm4=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm4, imm6));
#ifdef IEM_INSTR_IMPL_A64__ADDG_64_addsub_immtags
        IEM_INSTR_IMPL_A64__ADDG_64_addsub_immtags(Rd, Rn, imm4, imm6);
#else
        RT_NOREF(Rd, Rn, imm4, imm6, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e204000: ADDHN2  <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ADDHN_asimddiff_N, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e204000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ADDHN_asimddiff_N Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ADDHN_asimddiff_N
            IEM_INSTR_IMPL_A64__ADDHN_asimddiff_N(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/9a002000: ADDPT  <Xd|SP>, <Xn|SP>, <Xm>{, LSL #<amount>}
   Instruction Set: A64  Groups: addsub_pt, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADDPT_64_addsub_pt, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x9a002000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CPA*/)
        {
            LogFlow(("%018x/%010x: ADDPT_64_addsub_pt Rd=%#x Rn=%#x imm3=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm3, Rm));
#ifdef IEM_INSTR_IMPL_A64__ADDPT_64_addsub_pt
            IEM_INSTR_IMPL_A64__ADDPT_64_addsub_pt(Rd, Rn, imm3, Rm);
#else
            RT_NOREF(Rd, Rn, imm3, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e20bc00: ADDP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ADDP_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ADDP_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ADDP_asimdsame_only
        IEM_INSTR_IMPL_A64__ADDP_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ef1b800: ADDP  D<d>, <Vn>.2D
   Instruction Set: A64  Groups: asisdpair, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ADDP_asisdpair_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ADDP_asisdpair_only Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__ADDP_asisdpair_only
        IEM_INSTR_IMPL_A64__ADDP_asisdpair_only(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00000/2b200000: ADDS  <Wd>, <Wn|WSP>, <Wm>{, <extend>{ #<amount>}}
   Instruction Set: A64  Groups: addsub_ext, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADDS_32S_addsub_ext, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00000)) == UINT32_C(0x2b200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >> 10) & 0x00000007;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: ADDS_32S_addsub_ext Rd=%#x Rn=%#x imm3=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm3, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__ADDS_32S_addsub_ext
        IEM_INSTR_IMPL_A64__ADDS_32S_addsub_ext(Rd, Rn, imm3, option, Rm);
#else
        RT_NOREF(Rd, Rn, imm3, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff800000/31000000: ADDS  <Wd>, <Wn|WSP>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: addsub_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_ADDS_32S_addsub_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    uint32_t const sh         = (uOpcode >> 22) & 0x00000001;
    LogFlow(("%018x/%010x: ADDS_32S_addsub_imm Rd=%#x Rn=%#x imm12=%#x sh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm12, sh));
#ifdef IEM_INSTR_IMPL_A64__ADDS_32S_addsub_imm
    IEM_INSTR_IMPL_A64__ADDS_32S_addsub_imm(Rd, Rn, imm12, sh);
#else
    RT_NOREF(Rd, Rn, imm12, sh, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/2b000000: ADDS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: addsub_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADDS_32_addsub_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: ADDS_32_addsub_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__ADDS_32_addsub_shift
    IEM_INSTR_IMPL_A64__ADDS_32_addsub_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00000/ab200000: ADDS  <Xd>, <Xn|SP>, <R><m>{, <extend>{ #<amount>}}
   Instruction Set: A64  Groups: addsub_ext, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADDS_64S_addsub_ext, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00000)) == UINT32_C(0xab200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >> 10) & 0x00000007;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: ADDS_64S_addsub_ext Rd=%#x Rn=%#x imm3=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm3, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__ADDS_64S_addsub_ext
        IEM_INSTR_IMPL_A64__ADDS_64S_addsub_ext(Rd, Rn, imm3, option, Rm);
#else
        RT_NOREF(Rd, Rn, imm3, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff800000/b1000000: ADDS  <Xd>, <Xn|SP>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: addsub_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_ADDS_64S_addsub_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    uint32_t const sh         = (uOpcode >> 22) & 0x00000001;
    LogFlow(("%018x/%010x: ADDS_64S_addsub_imm Rd=%#x Rn=%#x imm12=%#x sh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm12, sh));
#ifdef IEM_INSTR_IMPL_A64__ADDS_64S_addsub_imm
    IEM_INSTR_IMPL_A64__ADDS_64S_addsub_imm(Rd, Rn, imm12, sh);
#else
    RT_NOREF(Rd, Rn, imm12, sh, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/ab000000: ADDS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: addsub_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADDS_64_addsub_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: ADDS_64_addsub_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__ADDS_64_addsub_shift
    IEM_INSTR_IMPL_A64__ADDS_64_addsub_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf3ffc00/0e31b800: ADDV  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ADDV_asimdall_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ADDV_asimdall_only Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ADDV_asimdall_only
        IEM_INSTR_IMPL_A64__ADDV_asimdall_only(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00000/0b200000: ADD  <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend>{ #<amount>}}
   Instruction Set: A64  Groups: addsub_ext, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADD_32_addsub_ext, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00000)) == UINT32_C(0x0b200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >> 10) & 0x00000007;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: ADD_32_addsub_ext Rd=%#x Rn=%#x imm3=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm3, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__ADD_32_addsub_ext
        IEM_INSTR_IMPL_A64__ADD_32_addsub_ext(Rd, Rn, imm3, option, Rm);
#else
        RT_NOREF(Rd, Rn, imm3, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff800000/11000000: ADD  <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: addsub_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_ADD_32_addsub_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    uint32_t const sh         = (uOpcode >> 22) & 0x00000001;
    LogFlow(("%018x/%010x: ADD_32_addsub_imm Rd=%#x Rn=%#x imm12=%#x sh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm12, sh));
#ifdef IEM_INSTR_IMPL_A64__ADD_32_addsub_imm
    IEM_INSTR_IMPL_A64__ADD_32_addsub_imm(Rd, Rn, imm12, sh);
#else
    RT_NOREF(Rd, Rn, imm12, sh, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/0b000000: ADD  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: addsub_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADD_32_addsub_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: ADD_32_addsub_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__ADD_32_addsub_shift
    IEM_INSTR_IMPL_A64__ADD_32_addsub_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00000/8b200000: ADD  <Xd|SP>, <Xn|SP>, <R><m>{, <extend>{ #<amount>}}
   Instruction Set: A64  Groups: addsub_ext, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADD_64_addsub_ext, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm3       = (uOpcode >> 10) & 0x00000007;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: ADD_64_addsub_ext Rd=%#x Rn=%#x imm3=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm3, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__ADD_64_addsub_ext
    IEM_INSTR_IMPL_A64__ADD_64_addsub_ext(Rd, Rn, imm3, option, Rm);
#else
    RT_NOREF(Rd, Rn, imm3, option, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff800000/91000000: ADD  <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: addsub_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_ADD_64_addsub_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    uint32_t const sh         = (uOpcode >> 22) & 0x00000001;
    LogFlow(("%018x/%010x: ADD_64_addsub_imm Rd=%#x Rn=%#x imm12=%#x sh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm12, sh));
#ifdef IEM_INSTR_IMPL_A64__ADD_64_addsub_imm
    IEM_INSTR_IMPL_A64__ADD_64_addsub_imm(Rd, Rn, imm12, sh);
#else
    RT_NOREF(Rd, Rn, imm12, sh, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/8b000000: ADD  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: addsub_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ADD_64_addsub_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: ADD_64_addsub_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__ADD_64_addsub_shift
    IEM_INSTR_IMPL_A64__ADD_64_addsub_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf20fc00/0e208400: ADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ADD_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ADD_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ADD_asimdsame_only
        IEM_INSTR_IMPL_A64__ADD_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5ee08400: ADD  D<d>, D<n>, D<m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ADD_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ADD_asisdsame_only Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__ADD_asisdsame_only
        IEM_INSTR_IMPL_A64__ADD_asisdsame_only(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 9f000000/90000000: ADRP  <Xd>, <label>
   Instruction Set: A64  Groups: pcreladdr, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_ADRP_only_pcreladdr, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const immhi      = (uOpcode >>  5) & 0x0007ffff;
    uint32_t const immlo      = (uOpcode >> 29) & 0x00000003;
    LogFlow(("%018x/%010x: ADRP_only_pcreladdr Rd=%#x immhi=%#x immlo=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, immhi, immlo));
#ifdef IEM_INSTR_IMPL_A64__ADRP_only_pcreladdr
    IEM_INSTR_IMPL_A64__ADRP_only_pcreladdr(Rd, immhi, immlo);
#else
    RT_NOREF(Rd, immhi, immlo, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* 9f000000/10000000: ADR  <Xd>, <label>
   Instruction Set: A64  Groups: pcreladdr, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_ADR_only_pcreladdr, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const immhi      = (uOpcode >>  5) & 0x0007ffff;
    uint32_t const immlo      = (uOpcode >> 29) & 0x00000003;
    LogFlow(("%018x/%010x: ADR_only_pcreladdr Rd=%#x immhi=%#x immlo=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, immhi, immlo));
#ifdef IEM_INSTR_IMPL_A64__ADR_only_pcreladdr
    IEM_INSTR_IMPL_A64__ADR_only_pcreladdr(Rd, immhi, immlo);
#else
    RT_NOREF(Rd, immhi, immlo, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/4e285800: AESD  <Vd>.16B, <Vn>.16B
   Instruction Set: A64  Groups: cryptoaes, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_AESD_B_cryptoaes, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x4e285800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const D          = (uOpcode >> 12) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAes /*FEAT_AES*/)
        {
            LogFlow(("%018x/%010x: AESD_B_cryptoaes Rd=%#x Rn=%#x D=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, D));
#ifdef IEM_INSTR_IMPL_A64__AESD_B_cryptoaes
            IEM_INSTR_IMPL_A64__AESD_B_cryptoaes(Rd, Rn, D);
#else
            RT_NOREF(Rd, Rn, D, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/4e284800: AESE  <Vd>.16B, <Vn>.16B
   Instruction Set: A64  Groups: cryptoaes, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_AESE_B_cryptoaes, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const D          = (uOpcode >> 12) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAes /*FEAT_AES*/)
    {
        LogFlow(("%018x/%010x: AESE_B_cryptoaes Rd=%#x Rn=%#x D=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, D));
#ifdef IEM_INSTR_IMPL_A64__AESE_B_cryptoaes
        IEM_INSTR_IMPL_A64__AESE_B_cryptoaes(Rd, Rn, D);
#else
        RT_NOREF(Rd, Rn, D, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/4e287800: AESIMC  <Vd>.16B, <Vn>.16B
   Instruction Set: A64  Groups: cryptoaes, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_AESIMC_B_cryptoaes, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const D          = (uOpcode >> 12) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAes /*FEAT_AES*/)
    {
        LogFlow(("%018x/%010x: AESIMC_B_cryptoaes Rd=%#x Rn=%#x D=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, D));
#ifdef IEM_INSTR_IMPL_A64__AESIMC_B_cryptoaes
        IEM_INSTR_IMPL_A64__AESIMC_B_cryptoaes(Rd, Rn, D);
#else
        RT_NOREF(Rd, Rn, D, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/4e286800: AESMC  <Vd>.16B, <Vn>.16B
   Instruction Set: A64  Groups: cryptoaes, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_AESMC_B_cryptoaes, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const D          = (uOpcode >> 12) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAes /*FEAT_AES*/)
    {
        LogFlow(("%018x/%010x: AESMC_B_cryptoaes Rd=%#x Rn=%#x D=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, D));
#ifdef IEM_INSTR_IMPL_A64__AESMC_B_cryptoaes
        IEM_INSTR_IMPL_A64__AESMC_B_cryptoaes(Rd, Rn, D);
#else
        RT_NOREF(Rd, Rn, D, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/72000000: ANDS  <Wd>, <Wn>, #<imm>
   Instruction Set: A64  Groups: log_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_ANDS_32S_log_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
    LogFlow(("%018x/%010x: ANDS_32S_log_imm Rd=%#x Rn=%#x imms=%#x immr=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr));
#ifdef IEM_INSTR_IMPL_A64__ANDS_32S_log_imm
    IEM_INSTR_IMPL_A64__ANDS_32S_log_imm(Rd, Rn, imms, immr);
#else
    RT_NOREF(Rd, Rn, imms, immr, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/6a000000: ANDS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ANDS_32_log_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: ANDS_32_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__ANDS_32_log_shift
    IEM_INSTR_IMPL_A64__ANDS_32_log_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff800000/f2000000: ANDS  <Xd>, <Xn>, #<imm>
   Instruction Set: A64  Groups: log_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_ANDS_64S_log_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const N          = (uOpcode >> 22) & 0x00000001;
    LogFlow(("%018x/%010x: ANDS_64S_log_imm Rd=%#x Rn=%#x imms=%#x immr=%#x N=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr, N));
#ifdef IEM_INSTR_IMPL_A64__ANDS_64S_log_imm
    IEM_INSTR_IMPL_A64__ANDS_64S_log_imm(Rd, Rn, imms, immr, N);
#else
    RT_NOREF(Rd, Rn, imms, immr, N, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/ea000000: ANDS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ANDS_64_log_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: ANDS_64_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__ANDS_64_log_shift
    IEM_INSTR_IMPL_A64__ANDS_64_log_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/12000000: AND  <Wd|WSP>, <Wn>, #<imm>
   Instruction Set: A64  Groups: log_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_AND_32_log_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
    LogFlow(("%018x/%010x: AND_32_log_imm Rd=%#x Rn=%#x imms=%#x immr=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr));
#ifdef IEM_INSTR_IMPL_A64__AND_32_log_imm
    IEM_INSTR_IMPL_A64__AND_32_log_imm(Rd, Rn, imms, immr);
#else
    RT_NOREF(Rd, Rn, imms, immr, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/0a000000: AND  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AND_32_log_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: AND_32_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__AND_32_log_shift
    IEM_INSTR_IMPL_A64__AND_32_log_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff800000/92000000: AND  <Xd|SP>, <Xn>, #<imm>
   Instruction Set: A64  Groups: log_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_AND_64_log_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const N          = (uOpcode >> 22) & 0x00000001;
    LogFlow(("%018x/%010x: AND_64_log_imm Rd=%#x Rn=%#x imms=%#x immr=%#x N=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr, N));
#ifdef IEM_INSTR_IMPL_A64__AND_64_log_imm
    IEM_INSTR_IMPL_A64__AND_64_log_imm(Rd, Rn, imms, immr, N);
#else
    RT_NOREF(Rd, Rn, imms, immr, N, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/8a000000: AND  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AND_64_log_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: AND_64_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__AND_64_log_shift
    IEM_INSTR_IMPL_A64__AND_64_log_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bfe0fc00/0e201c00: AND  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_AND_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: AND_asimdsame_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__AND_asimdsame_only
        IEM_INSTR_IMPL_A64__AND_asimdsame_only(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac02800: ASRV  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ASRV_32_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op2        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: ASRV_32_dp_2src Rd=%#x Rn=%#x op2=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op2, Rm));
#ifdef IEM_INSTR_IMPL_A64__ASRV_32_dp_2src
    IEM_INSTR_IMPL_A64__ASRV_32_dp_2src(Rd, Rn, op2, Rm);
#else
    RT_NOREF(Rd, Rn, op2, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/9ac02800: ASRV  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ASRV_64_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op2        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: ASRV_64_dp_2src Rd=%#x Rn=%#x op2=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op2, Rm));
#ifdef IEM_INSTR_IMPL_A64__ASRV_64_dp_2src
    IEM_INSTR_IMPL_A64__ASRV_64_dp_2src(Rd, Rn, op2, Rm);
#else
    RT_NOREF(Rd, Rn, op2, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/dac11800: AUTDA  <Xd>, <Xn|SP>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AUTDA_64P_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: AUTDA_64P_dp_1src Rd=%#x Rn=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Z));
#ifdef IEM_INSTR_IMPL_A64__AUTDA_64P_dp_1src
        IEM_INSTR_IMPL_A64__AUTDA_64P_dp_1src(Rd, Rn, Z);
#else
        RT_NOREF(Rd, Rn, Z, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/dac11c00: AUTDB  <Xd>, <Xn|SP>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AUTDB_64P_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: AUTDB_64P_dp_1src Rd=%#x Rn=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Z));
#ifdef IEM_INSTR_IMPL_A64__AUTDB_64P_dp_1src
        IEM_INSTR_IMPL_A64__AUTDB_64P_dp_1src(Rd, Rn, Z);
#else
        RT_NOREF(Rd, Rn, Z, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/dac13be0: AUTDZA  <Xd>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AUTDZA_64Z_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xdac13be0))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: AUTDZA_64Z_dp_1src Rd=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Z));
#ifdef IEM_INSTR_IMPL_A64__AUTDZA_64Z_dp_1src
            IEM_INSTR_IMPL_A64__AUTDZA_64Z_dp_1src(Rd, Z);
#else
            RT_NOREF(Rd, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/dac13fe0: AUTDZB  <Xd>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AUTDZB_64Z_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: AUTDZB_64Z_dp_1src Rd=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Z));
#ifdef IEM_INSTR_IMPL_A64__AUTDZB_64Z_dp_1src
        IEM_INSTR_IMPL_A64__AUTDZB_64Z_dp_1src(Rd, Z);
#else
        RT_NOREF(Rd, Z, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/dac1bbfe: AUTIA171615
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AUTIA171615_64LR_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xdac1bbfe))
    {
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
        {
            LogFlow(("%018x/%010x: AUTIA171615_64LR_dp_1src\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__AUTIA171615_64LR_dp_1src
            IEM_INSTR_IMPL_A64__AUTIA171615_64LR_dp_1src();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503219f: AUTIA1716
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_AUTIA1716_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503219f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: AUTIA1716_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__AUTIA1716_HI_hints
            IEM_INSTR_IMPL_A64__AUTIA1716_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/dac1901e: AUTIASPPCR  <Xn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AUTIASPPCR_64LRR_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0xdac1901e))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
        {
            LogFlow(("%018x/%010x: AUTIASPPCR_64LRR_dp_1src Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn));
#ifdef IEM_INSTR_IMPL_A64__AUTIASPPCR_64LRR_dp_1src
            IEM_INSTR_IMPL_A64__AUTIASPPCR_64LRR_dp_1src(Rn);
#else
            RT_NOREF(Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001f/f380001f: AUTIASPPC  <label>
   Instruction Set: A64  Groups: dp_1src_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_AUTIASPPC_only_dp_1src_imm, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0xf380001f))
    {
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
        {
            LogFlow(("%018x/%010x: AUTIASPPC_only_dp_1src_imm imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__AUTIASPPC_only_dp_1src_imm
            IEM_INSTR_IMPL_A64__AUTIASPPC_only_dp_1src_imm(imm16);
#else
            RT_NOREF(imm16, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d50323bf: AUTIASP
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_AUTIASP_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd50323bf))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: AUTIASP_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__AUTIASP_HI_hints
            IEM_INSTR_IMPL_A64__AUTIASP_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503239f: AUTIAZ
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_AUTIAZ_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503239f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: AUTIAZ_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__AUTIAZ_HI_hints
            IEM_INSTR_IMPL_A64__AUTIAZ_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/dac11000: AUTIA  <Xd>, <Xn|SP>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AUTIA_64P_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: AUTIA_64P_dp_1src Rd=%#x Rn=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Z));
#ifdef IEM_INSTR_IMPL_A64__AUTIA_64P_dp_1src
        IEM_INSTR_IMPL_A64__AUTIA_64P_dp_1src(Rd, Rn, Z);
#else
        RT_NOREF(Rd, Rn, Z, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/dac1bffe: AUTIB171615
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AUTIB171615_64LR_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xdac1bffe))
    {
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
        {
            LogFlow(("%018x/%010x: AUTIB171615_64LR_dp_1src\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__AUTIB171615_64LR_dp_1src
            IEM_INSTR_IMPL_A64__AUTIB171615_64LR_dp_1src();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d50321df: AUTIB1716
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_AUTIB1716_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd50321df))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: AUTIB1716_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__AUTIB1716_HI_hints
            IEM_INSTR_IMPL_A64__AUTIB1716_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/dac1941e: AUTIBSPPCR  <Xn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AUTIBSPPCR_64LRR_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0xdac1941e))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
        {
            LogFlow(("%018x/%010x: AUTIBSPPCR_64LRR_dp_1src Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn));
#ifdef IEM_INSTR_IMPL_A64__AUTIBSPPCR_64LRR_dp_1src
            IEM_INSTR_IMPL_A64__AUTIBSPPCR_64LRR_dp_1src(Rn);
#else
            RT_NOREF(Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001f/f3a0001f: AUTIBSPPC  <label>
   Instruction Set: A64  Groups: dp_1src_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_AUTIBSPPC_only_dp_1src_imm, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0xf3a0001f))
    {
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
        {
            LogFlow(("%018x/%010x: AUTIBSPPC_only_dp_1src_imm imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__AUTIBSPPC_only_dp_1src_imm
            IEM_INSTR_IMPL_A64__AUTIBSPPC_only_dp_1src_imm(imm16);
#else
            RT_NOREF(imm16, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d50323ff: AUTIBSP
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_AUTIBSP_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd50323ff))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: AUTIBSP_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__AUTIBSP_HI_hints
            IEM_INSTR_IMPL_A64__AUTIBSP_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d50323df: AUTIBZ
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_AUTIBZ_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd50323df))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: AUTIBZ_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__AUTIBZ_HI_hints
            IEM_INSTR_IMPL_A64__AUTIBZ_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/dac11400: AUTIB  <Xd>, <Xn|SP>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AUTIB_64P_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: AUTIB_64P_dp_1src Rd=%#x Rn=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Z));
#ifdef IEM_INSTR_IMPL_A64__AUTIB_64P_dp_1src
        IEM_INSTR_IMPL_A64__AUTIB_64P_dp_1src(Rd, Rn, Z);
#else
        RT_NOREF(Rd, Rn, Z, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/dac133e0: AUTIZA  <Xd>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AUTIZA_64Z_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xdac133e0))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: AUTIZA_64Z_dp_1src Rd=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Z));
#ifdef IEM_INSTR_IMPL_A64__AUTIZA_64Z_dp_1src
            IEM_INSTR_IMPL_A64__AUTIZA_64Z_dp_1src(Rd, Z);
#else
            RT_NOREF(Rd, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/dac137e0: AUTIZB  <Xd>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_AUTIZB_64Z_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xdac137e0))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: AUTIZB_64Z_dp_1src Rd=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Z));
#ifdef IEM_INSTR_IMPL_A64__AUTIZB_64Z_dp_1src
            IEM_INSTR_IMPL_A64__AUTIZB_64Z_dp_1src(Rd, Z);
#else
            RT_NOREF(Rd, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d500405f: AXFLAG
   Instruction Set: A64  Groups: pstate, control */
FNIEMOP_DEF_1(iemDecodeA64_AXFLAG_M_pstate, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd500405f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFlagM2 /*FEAT_FlagM2*/)
        {
            LogFlow(("%018x/%010x: AXFLAG_M_pstate\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__AXFLAG_M_pstate
            IEM_INSTR_IMPL_A64__AXFLAG_M_pstate();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/ce200000: BCAX  <Vd>.16B, <Vn>.16B, <Vm>.16B, <Va>.16B
   Instruction Set: A64  Groups: crypto4, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BCAX_VVV16_crypto4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0xce200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha3 /*FEAT_SHA3*/)
        {
            LogFlow(("%018x/%010x: BCAX_VVV16_crypto4 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__BCAX_VVV16_crypto4
            IEM_INSTR_IMPL_A64__BCAX_VVV16_crypto4(Rd, Rn, Ra, Rm);
#else
            RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff000010/54000010: BC.<cond>  <label>
   Instruction Set: A64  Groups: condbranch, control */
FNIEMOP_DEF_1(iemDecodeA64_BC_only_condbranch, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff000010)) == UINT32_C(0x54000010))
    {
        uint32_t const cond       = (uOpcode >>  0) & 0x0000000f;
        uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fHbc /*FEAT_HBC*/)
        {
            LogFlow(("%018x/%010x: BC_only_condbranch cond=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, cond, imm19));
#ifdef IEM_INSTR_IMPL_A64__BC_only_condbranch
            IEM_INSTR_IMPL_A64__BC_only_condbranch(cond, imm19);
#else
            RT_NOREF(cond, imm19, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2ea17800: BF1CVTL2  <Vd>.8H, <Vn>.<Ta>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BF1CVTL_asimdmisc_V, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2ea17800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
        {
            LogFlow(("%018x/%010x: BF1CVTL_asimdmisc_V Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__BF1CVTL_asimdmisc_V
            IEM_INSTR_IMPL_A64__BF1CVTL_asimdmisc_V(Rd, Rn, Q);
#else
            RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2ee17800: BF2CVTL2  <Vd>.8H, <Vn>.<Ta>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BF2CVTL_asimdmisc_V, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2ee17800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
        {
            LogFlow(("%018x/%010x: BF2CVTL_asimdmisc_V Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__BF2CVTL_asimdmisc_V
            IEM_INSTR_IMPL_A64__BF2CVTL_asimdmisc_V(Rd, Rn, Q);
#else
            RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0ea16800: BFCVTN2  <Vd>.<Ta>, <Vn>.4S
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BFCVTN_asimdmisc_4S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0ea16800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: BFCVTN_asimdmisc_4S Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__BFCVTN_asimdmisc_4S
            IEM_INSTR_IMPL_A64__BFCVTN_asimdmisc_4S(Rd, Rn, Q);
#else
            RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e634000: BFCVT  <Hd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BFCVT_BS_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e634000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: BFCVT_BS_floatdp1 Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__BFCVT_BS_floatdp1
            IEM_INSTR_IMPL_A64__BFCVT_BS_floatdp1(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/0f40f000: BFDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.2H[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BFDOT_asimdelem_E, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x0f40f000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: BFDOT_asimdelem_E Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, Q));
#ifdef IEM_INSTR_IMPL_A64__BFDOT_asimdelem_E
            IEM_INSTR_IMPL_A64__BFDOT_asimdelem_E(Rd, Rn, H, Rm, M, L, Q);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2e40fc00: BFDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BFDOT_asimdsame2_D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2e40fc00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: BFDOT_asimdsame2_D Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__BFDOT_asimdsame2_D
            IEM_INSTR_IMPL_A64__BFDOT_asimdsame2_D(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/0fc0f000: BFMLAL<bt>  <Vd>.4S, <Vn>.8H, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BFMLAL_asimdelem_F, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x0fc0f000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: BFMLAL_asimdelem_F Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, Q));
#ifdef IEM_INSTR_IMPL_A64__BFMLAL_asimdelem_F
            IEM_INSTR_IMPL_A64__BFMLAL_asimdelem_F(Rd, Rn, H, Rm, M, L, Q);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2ec0fc00: BFMLAL<bt>  <Vd>.4S, <Vn>.8H, <Vm>.8H
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BFMLAL_asimdsame2_F, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2ec0fc00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: BFMLAL_asimdsame2_F Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__BFMLAL_asimdsame2_F
            IEM_INSTR_IMPL_A64__BFMLAL_asimdsame2_F(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/6e40ec00: BFMMLA  <Vd>.4S, <Vn>.8H, <Vm>.8H
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BFMMLA_asimdsame2_E, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x6e40ec00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: BFMMLA_asimdsame2_E Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__BFMMLA_asimdsame2_E
            IEM_INSTR_IMPL_A64__BFMMLA_asimdsame2_E(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/33000000: BFM  <Wd>, <Wn>, #<immr>, #<imms>
   Instruction Set: A64  Groups: bitfield, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_BFM_32M_bitfield, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
    LogFlow(("%018x/%010x: BFM_32M_bitfield Rd=%#x Rn=%#x imms=%#x immr=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr));
#ifdef IEM_INSTR_IMPL_A64__BFM_32M_bitfield
    IEM_INSTR_IMPL_A64__BFM_32M_bitfield(Rd, Rn, imms, immr);
#else
    RT_NOREF(Rd, Rn, imms, immr, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/b3400000: BFM  <Xd>, <Xn>, #<immr>, #<imms>
   Instruction Set: A64  Groups: bitfield, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_BFM_64M_bitfield, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xb3400000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
        uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
        LogFlow(("%018x/%010x: BFM_64M_bitfield Rd=%#x Rn=%#x imms=%#x immr=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr));
#ifdef IEM_INSTR_IMPL_A64__BFM_64M_bitfield
        IEM_INSTR_IMPL_A64__BFM_64M_bitfield(Rd, Rn, imms, immr);
#else
        RT_NOREF(Rd, Rn, imms, immr, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff200000/6a200000: BICS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_BICS_32_log_shift, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff200000)) == UINT32_C(0x6a200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
        LogFlow(("%018x/%010x: BICS_32_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__BICS_32_log_shift
        IEM_INSTR_IMPL_A64__BICS_32_log_shift(Rd, Rn, imm6, Rm, shift);
#else
        RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff200000/ea200000: BICS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_BICS_64_log_shift, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff200000)) == UINT32_C(0xea200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
        LogFlow(("%018x/%010x: BICS_64_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__BICS_64_log_shift
        IEM_INSTR_IMPL_A64__BICS_64_log_shift(Rd, Rn, imm6, Rm, shift);
#else
        RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff200000/0a200000: BIC  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_BIC_32_log_shift, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff200000)) == UINT32_C(0x0a200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
        LogFlow(("%018x/%010x: BIC_32_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__BIC_32_log_shift
        IEM_INSTR_IMPL_A64__BIC_32_log_shift(Rd, Rn, imm6, Rm, shift);
#else
        RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff200000/8a200000: BIC  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_BIC_64_log_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: BIC_64_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__BIC_64_log_shift
    IEM_INSTR_IMPL_A64__BIC_64_log_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bff8dc00/2f009400: BIC  <Vd>.<T>, #<imm8>{, LSL #<amount>}
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BIC_asimdimm_L_hl, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const cmode      = (uOpcode >> 12) & 0x0000000f;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: BIC_asimdimm_L_hl Rd=%#x h=%u g=%u f=%u e=%u d=%u cmode=%#x c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, cmode, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__BIC_asimdimm_L_hl
        IEM_INSTR_IMPL_A64__BIC_asimdimm_L_hl(Rd, h, g, f, e, d, cmode, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, cmode, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bff89c00/2f001400: BIC  <Vd>.<T>, #<imm8>{, LSL #<amount>}
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BIC_asimdimm_L_sl, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const cmode      = (uOpcode >> 12) & 0x0000000f;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: BIC_asimdimm_L_sl Rd=%#x h=%u g=%u f=%u e=%u d=%u cmode=%#x c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, cmode, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__BIC_asimdimm_L_sl
        IEM_INSTR_IMPL_A64__BIC_asimdimm_L_sl(Rd, h, g, f, e, d, cmode, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, cmode, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e601c00: BIC  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BIC_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e601c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: BIC_asimdsame_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__BIC_asimdsame_only
            IEM_INSTR_IMPL_A64__BIC_asimdsame_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2ee01c00: BIF  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BIF_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2ee01c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const opc2       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: BIF_asimdsame_only Rd=%#x Rn=%#x Rm=%#x opc2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, opc2, Q));
#ifdef IEM_INSTR_IMPL_A64__BIF_asimdsame_only
            IEM_INSTR_IMPL_A64__BIF_asimdsame_only(Rd, Rn, Rm, opc2, Q);
#else
            RT_NOREF(Rd, Rn, Rm, opc2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2ea01c00: BIT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BIT_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2ea01c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const opc2       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: BIT_asimdsame_only Rd=%#x Rn=%#x Rm=%#x opc2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, opc2, Q));
#ifdef IEM_INSTR_IMPL_A64__BIT_asimdsame_only
            IEM_INSTR_IMPL_A64__BIT_asimdsame_only(Rd, Rn, Rm, opc2, Q);
#else
            RT_NOREF(Rd, Rn, Rm, opc2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/d63f081f: BLRAAZ  <Xn>
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_BLRAAZ_64_branch_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0xd63f081f))
    {
        uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const M          = (uOpcode >> 10) & 0x00000001;
        uint32_t const A          = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 21) & 0x00000003;
        uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: BLRAAZ_64_branch_reg Rm=%#x Rn=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, Rn, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__BLRAAZ_64_branch_reg
            IEM_INSTR_IMPL_A64__BLRAAZ_64_branch_reg(Rm, Rn, M, A, op, Z);
#else
            RT_NOREF(Rm, Rn, M, A, op, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/d73f0800: BLRAA  <Xn>, <Xm|SP>
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_BLRAA_64P_branch_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xd73f0800))
    {
        uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const M          = (uOpcode >> 10) & 0x00000001;
        uint32_t const A          = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 21) & 0x00000003;
        uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: BLRAA_64P_branch_reg Rm=%#x Rn=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, Rn, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__BLRAA_64P_branch_reg
            IEM_INSTR_IMPL_A64__BLRAA_64P_branch_reg(Rm, Rn, M, A, op, Z);
#else
            RT_NOREF(Rm, Rn, M, A, op, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/d63f0c1f: BLRABZ  <Xn>
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_BLRABZ_64_branch_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0xd63f0c1f))
    {
        uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const M          = (uOpcode >> 10) & 0x00000001;
        uint32_t const A          = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 21) & 0x00000003;
        uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: BLRABZ_64_branch_reg Rm=%#x Rn=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, Rn, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__BLRABZ_64_branch_reg
            IEM_INSTR_IMPL_A64__BLRABZ_64_branch_reg(Rm, Rn, M, A, op, Z);
#else
            RT_NOREF(Rm, Rn, M, A, op, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/d73f0c00: BLRAB  <Xn>, <Xm|SP>
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_BLRAB_64P_branch_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xd73f0c00))
    {
        uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const M          = (uOpcode >> 10) & 0x00000001;
        uint32_t const A          = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 21) & 0x00000003;
        uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: BLRAB_64P_branch_reg Rm=%#x Rn=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, Rn, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__BLRAB_64P_branch_reg
            IEM_INSTR_IMPL_A64__BLRAB_64P_branch_reg(Rm, Rn, M, A, op, Z);
#else
            RT_NOREF(Rm, Rn, M, A, op, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/d63f0000: BLR  <Xn>
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_BLR_64_branch_reg, uint32_t, uOpcode)
{
    uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const M          = (uOpcode >> 10) & 0x00000001;
    uint32_t const A          = (uOpcode >> 11) & 0x00000001;
    uint32_t const op         = (uOpcode >> 21) & 0x00000003;
    uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
    LogFlow(("%018x/%010x: BLR_64_branch_reg Rm=%#x Rn=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, Rn, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__BLR_64_branch_reg
    IEM_INSTR_IMPL_A64__BLR_64_branch_reg(Rm, Rn, M, A, op, Z);
#else
    RT_NOREF(Rm, Rn, M, A, op, Z, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fc000000/94000000: BL  <label>
   Instruction Set: A64  Groups: branch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_BL_only_branch_imm, uint32_t, uOpcode)
{
    uint32_t const imm26      = (uOpcode >>  0) & 0x03ffffff;
    LogFlow(("%018x/%010x: BL_only_branch_imm imm26=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm26));
#ifdef IEM_INSTR_IMPL_A64__BL_only_branch_imm
    IEM_INSTR_IMPL_A64__BL_only_branch_imm(imm26);
#else
    RT_NOREF(imm26, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc1f/d61f081f: BRAAZ  <Xn>
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_BRAAZ_64_branch_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0xd61f081f))
    {
        uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const M          = (uOpcode >> 10) & 0x00000001;
        uint32_t const A          = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 21) & 0x00000003;
        uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: BRAAZ_64_branch_reg Rm=%#x Rn=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, Rn, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__BRAAZ_64_branch_reg
            IEM_INSTR_IMPL_A64__BRAAZ_64_branch_reg(Rm, Rn, M, A, op, Z);
#else
            RT_NOREF(Rm, Rn, M, A, op, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/d71f0800: BRAA  <Xn>, <Xm|SP>
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_BRAA_64P_branch_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xd71f0800))
    {
        uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const M          = (uOpcode >> 10) & 0x00000001;
        uint32_t const A          = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 21) & 0x00000003;
        uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: BRAA_64P_branch_reg Rm=%#x Rn=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, Rn, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__BRAA_64P_branch_reg
            IEM_INSTR_IMPL_A64__BRAA_64P_branch_reg(Rm, Rn, M, A, op, Z);
#else
            RT_NOREF(Rm, Rn, M, A, op, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/d61f0c1f: BRABZ  <Xn>
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_BRABZ_64_branch_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0xd61f0c1f))
    {
        uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const M          = (uOpcode >> 10) & 0x00000001;
        uint32_t const A          = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 21) & 0x00000003;
        uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: BRABZ_64_branch_reg Rm=%#x Rn=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, Rn, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__BRABZ_64_branch_reg
            IEM_INSTR_IMPL_A64__BRABZ_64_branch_reg(Rm, Rn, M, A, op, Z);
#else
            RT_NOREF(Rm, Rn, M, A, op, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/d71f0c00: BRAB  <Xn>, <Xm|SP>
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_BRAB_64P_branch_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xd71f0c00))
    {
        uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const M          = (uOpcode >> 10) & 0x00000001;
        uint32_t const A          = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 21) & 0x00000003;
        uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: BRAB_64P_branch_reg Rm=%#x Rn=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, Rn, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__BRAB_64P_branch_reg
            IEM_INSTR_IMPL_A64__BRAB_64P_branch_reg(Rm, Rn, M, A, op, Z);
#else
            RT_NOREF(Rm, Rn, M, A, op, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001f/d4200000: BRK  #<imm>
   Instruction Set: A64  Groups: exception, control */
FNIEMOP_DEF_1(iemDecodeA64_BRK_EX_exception, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0xd4200000))
    {
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        LogFlow(("%018x/%010x: BRK_EX_exception imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__BRK_EX_exception
        IEM_INSTR_IMPL_A64__BRK_EX_exception(imm16);
#else
        RT_NOREF(imm16, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/d61f0000: BR  <Xn>
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_BR_64_branch_reg, uint32_t, uOpcode)
{
    uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const M          = (uOpcode >> 10) & 0x00000001;
    uint32_t const A          = (uOpcode >> 11) & 0x00000001;
    uint32_t const op         = (uOpcode >> 21) & 0x00000003;
    uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
    LogFlow(("%018x/%010x: BR_64_branch_reg Rm=%#x Rn=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, Rn, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__BR_64_branch_reg
    IEM_INSTR_IMPL_A64__BR_64_branch_reg(Rm, Rn, M, A, op, Z);
#else
    RT_NOREF(Rm, Rn, M, A, op, Z, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bfe0fc00/2e601c00: BSL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_BSL_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2e601c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const opc2       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: BSL_asimdsame_only Rd=%#x Rn=%#x Rm=%#x opc2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, opc2, Q));
#ifdef IEM_INSTR_IMPL_A64__BSL_asimdsame_only
            IEM_INSTR_IMPL_A64__BSL_asimdsame_only(Rd, Rn, Rm, opc2, Q);
#else
            RT_NOREF(Rd, Rn, Rm, opc2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffff1f/d503241f: BTI{  <targets>}
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_BTI_HB_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffff1f)) == UINT32_C(0xd503241f))
    {
        uint32_t const op2        = (uOpcode >>  5) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBti /*FEAT_BTI*/ && (op2 & 1) == 0)
        {
            LogFlow(("%018x/%010x: BTI_HB_hints op2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, op2));
#ifdef IEM_INSTR_IMPL_A64__BTI_HB_hints
            IEM_INSTR_IMPL_A64__BTI_HB_hints(op2);
#else
            RT_NOREF(op2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fc000000/14000000: B  <label>
   Instruction Set: A64  Groups: branch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_B_only_branch_imm, uint32_t, uOpcode)
{
    uint32_t const imm26      = (uOpcode >>  0) & 0x03ffffff;
    LogFlow(("%018x/%010x: B_only_branch_imm imm26=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm26));
#ifdef IEM_INSTR_IMPL_A64__B_only_branch_imm
    IEM_INSTR_IMPL_A64__B_only_branch_imm(imm26);
#else
    RT_NOREF(imm26, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff000010/54000000: B.<cond>  <label>
   Instruction Set: A64  Groups: condbranch, control */
FNIEMOP_DEF_1(iemDecodeA64_B_only_condbranch, uint32_t, uOpcode)
{
    uint32_t const cond       = (uOpcode >>  0) & 0x0000000f;
    uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
    LogFlow(("%018x/%010x: B_only_condbranch cond=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, cond, imm19));
#ifdef IEM_INSTR_IMPL_A64__B_only_condbranch
    IEM_INSTR_IMPL_A64__B_only_condbranch(cond, imm19);
#else
    RT_NOREF(cond, imm19, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/08e07c00: CASAB  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASAB_C32_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASAB_C32_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASAB_C32_comswap
        IEM_INSTR_IMPL_A64__CASAB_C32_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/48e07c00: CASAH  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASAH_C32_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASAH_C32_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASAH_C32_comswap
        IEM_INSTR_IMPL_A64__CASAH_C32_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/08e0fc00: CASALB  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASALB_C32_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASALB_C32_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASALB_C32_comswap
        IEM_INSTR_IMPL_A64__CASALB_C32_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/48e0fc00: CASALH  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASALH_C32_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASALH_C32_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASALH_C32_comswap
        IEM_INSTR_IMPL_A64__CASALH_C32_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/c9c0fc00: CASALT  <Xs>, <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASALT_C64_comswap_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xc9c0fc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: CASALT_C64_comswap_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASALT_C64_comswap_unpriv
            IEM_INSTR_IMPL_A64__CASALT_C64_comswap_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/88e0fc00: CASAL  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASAL_C32_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASAL_C32_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASAL_C32_comswap
        IEM_INSTR_IMPL_A64__CASAL_C32_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/c8e0fc00: CASAL  <Xs>, <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASAL_C64_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASAL_C64_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASAL_C64_comswap
        IEM_INSTR_IMPL_A64__CASAL_C64_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/c9c07c00: CASAT  <Xs>, <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASAT_C64_comswap_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: CASAT_C64_comswap_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASAT_C64_comswap_unpriv
        IEM_INSTR_IMPL_A64__CASAT_C64_comswap_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/88e07c00: CASA  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASA_C32_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASA_C32_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASA_C32_comswap
        IEM_INSTR_IMPL_A64__CASA_C32_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/c8e07c00: CASA  <Xs>, <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASA_C64_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASA_C64_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASA_C64_comswap
        IEM_INSTR_IMPL_A64__CASA_C64_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/08a07c00: CASB  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASB_C32_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASB_C32_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASB_C32_comswap
        IEM_INSTR_IMPL_A64__CASB_C32_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/48a07c00: CASH  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASH_C32_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASH_C32_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASH_C32_comswap
        IEM_INSTR_IMPL_A64__CASH_C32_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/08a0fc00: CASLB  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASLB_C32_comswap, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x08a0fc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: CASLB_C32_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASLB_C32_comswap
            IEM_INSTR_IMPL_A64__CASLB_C32_comswap(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/48a0fc00: CASLH  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASLH_C32_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASLH_C32_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASLH_C32_comswap
        IEM_INSTR_IMPL_A64__CASLH_C32_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/c980fc00: CASLT  <Xs>, <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASLT_C64_comswap_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: CASLT_C64_comswap_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASLT_C64_comswap_unpriv
        IEM_INSTR_IMPL_A64__CASLT_C64_comswap_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/88a0fc00: CASL  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASL_C32_comswap, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x88a0fc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: CASL_C32_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASL_C32_comswap
            IEM_INSTR_IMPL_A64__CASL_C32_comswap(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/c8a0fc00: CASL  <Xs>, <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASL_C64_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASL_C64_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASL_C64_comswap
        IEM_INSTR_IMPL_A64__CASL_C64_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/49c0fc00: CASPALT  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswappr_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASPALT_CP64_comswappr_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x49c0fc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: CASPALT_CP64_comswappr_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASPALT_CP64_comswappr_unpriv
            IEM_INSTR_IMPL_A64__CASPALT_CP64_comswappr_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/0860fc00: CASPAL  <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASPAL_CP32_comswappr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASPAL_CP32_comswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASPAL_CP32_comswappr
        IEM_INSTR_IMPL_A64__CASPAL_CP32_comswappr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4860fc00: CASPAL  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASPAL_CP64_comswappr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4860fc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: CASPAL_CP64_comswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASPAL_CP64_comswappr
            IEM_INSTR_IMPL_A64__CASPAL_CP64_comswappr(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/49c07c00: CASPAT  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswappr_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASPAT_CP64_comswappr_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: CASPAT_CP64_comswappr_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASPAT_CP64_comswappr_unpriv
        IEM_INSTR_IMPL_A64__CASPAT_CP64_comswappr_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/08607c00: CASPA  <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASPA_CP32_comswappr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x08607c00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: CASPA_CP32_comswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASPA_CP32_comswappr
            IEM_INSTR_IMPL_A64__CASPA_CP32_comswappr(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/48607c00: CASPA  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASPA_CP64_comswappr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x48607c00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: CASPA_CP64_comswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASPA_CP64_comswappr
            IEM_INSTR_IMPL_A64__CASPA_CP64_comswappr(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4980fc00: CASPLT  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswappr_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASPLT_CP64_comswappr_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: CASPLT_CP64_comswappr_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASPLT_CP64_comswappr_unpriv
        IEM_INSTR_IMPL_A64__CASPLT_CP64_comswappr_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/0820fc00: CASPL  <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASPL_CP32_comswappr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASPL_CP32_comswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASPL_CP32_comswappr
        IEM_INSTR_IMPL_A64__CASPL_CP32_comswappr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4820fc00: CASPL  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASPL_CP64_comswappr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASPL_CP64_comswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASPL_CP64_comswappr
        IEM_INSTR_IMPL_A64__CASPL_CP64_comswappr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/49807c00: CASPT  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswappr_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASPT_CP64_comswappr_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: CASPT_CP64_comswappr_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASPT_CP64_comswappr_unpriv
        IEM_INSTR_IMPL_A64__CASPT_CP64_comswappr_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/08207c00: CASP  <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASP_CP32_comswappr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASP_CP32_comswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASP_CP32_comswappr
        IEM_INSTR_IMPL_A64__CASP_CP32_comswappr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/48207c00: CASP  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CASP_CP64_comswappr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CASP_CP64_comswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CASP_CP64_comswappr
        IEM_INSTR_IMPL_A64__CASP_CP64_comswappr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/c9807c00: CAST  <Xs>, <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CAST_C64_comswap_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: CAST_C64_comswap_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CAST_C64_comswap_unpriv
        IEM_INSTR_IMPL_A64__CAST_C64_comswap_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/88a07c00: CAS  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CAS_C32_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CAS_C32_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CAS_C32_comswap
        IEM_INSTR_IMPL_A64__CAS_C32_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/c8a07c00: CAS  <Xs>, <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: comswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CAS_C64_comswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: CAS_C64_comswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__CAS_C64_comswap
        IEM_INSTR_IMPL_A64__CAS_C64_comswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74c08000: CBBEQ  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs2, control */
FNIEMOP_DEF_1(iemDecodeA64_CBBEQ_8_regs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
    {
        LogFlow(("%018x/%010x: CBBEQ_8_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBBEQ_8_regs
        IEM_INSTR_IMPL_A64__CBBEQ_8_regs(Rt, imm9, Rm);
#else
        RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74208000: CBBGE  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs2, control */
FNIEMOP_DEF_1(iemDecodeA64_CBBGE_8_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74208000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBBGE_8_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBBGE_8_regs
            IEM_INSTR_IMPL_A64__CBBGE_8_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74008000: CBBGT  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs2, control */
FNIEMOP_DEF_1(iemDecodeA64_CBBGT_8_regs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
    {
        LogFlow(("%018x/%010x: CBBGT_8_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBBGT_8_regs
        IEM_INSTR_IMPL_A64__CBBGT_8_regs(Rt, imm9, Rm);
#else
        RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74408000: CBBHI  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs2, control */
FNIEMOP_DEF_1(iemDecodeA64_CBBHI_8_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74408000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBBHI_8_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBBHI_8_regs
            IEM_INSTR_IMPL_A64__CBBHI_8_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74608000: CBBHS  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs2, control */
FNIEMOP_DEF_1(iemDecodeA64_CBBHS_8_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74608000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBBHS_8_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBBHS_8_regs
            IEM_INSTR_IMPL_A64__CBBHS_8_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74e08000: CBBNE  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs2, control */
FNIEMOP_DEF_1(iemDecodeA64_CBBNE_8_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74e08000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBBNE_8_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBBNE_8_regs
            IEM_INSTR_IMPL_A64__CBBNE_8_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe04000/75c00000: CBEQ  <Wt>, #<imm>, <label>
   Instruction Set: A64  Groups: compbranch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_CBEQ_32_imm, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe04000)) == UINT32_C(0x75c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBEQ_32_imm Rt=%#x imm9=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, imm6));
#ifdef IEM_INSTR_IMPL_A64__CBEQ_32_imm
            IEM_INSTR_IMPL_A64__CBEQ_32_imm(Rt, imm9, imm6);
#else
            RT_NOREF(Rt, imm9, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74c00000: CBEQ  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs, control */
FNIEMOP_DEF_1(iemDecodeA64_CBEQ_32_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBEQ_32_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBEQ_32_regs
            IEM_INSTR_IMPL_A64__CBEQ_32_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe04000/f5c00000: CBEQ  <Xt>, #<imm>, <label>
   Instruction Set: A64  Groups: compbranch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_CBEQ_64_imm, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe04000)) == UINT32_C(0xf5c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBEQ_64_imm Rt=%#x imm9=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, imm6));
#ifdef IEM_INSTR_IMPL_A64__CBEQ_64_imm
            IEM_INSTR_IMPL_A64__CBEQ_64_imm(Rt, imm9, imm6);
#else
            RT_NOREF(Rt, imm9, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/f4c00000: CBEQ  <Xt>, <Xm>, <label>
   Instruction Set: A64  Groups: compbranch_regs, control */
FNIEMOP_DEF_1(iemDecodeA64_CBEQ_64_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0xf4c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBEQ_64_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBEQ_64_regs
            IEM_INSTR_IMPL_A64__CBEQ_64_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74200000: CBGE  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs, control */
FNIEMOP_DEF_1(iemDecodeA64_CBGE_32_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74200000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBGE_32_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBGE_32_regs
            IEM_INSTR_IMPL_A64__CBGE_32_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/f4200000: CBGE  <Xt>, <Xm>, <label>
   Instruction Set: A64  Groups: compbranch_regs, control */
FNIEMOP_DEF_1(iemDecodeA64_CBGE_64_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0xf4200000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBGE_64_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBGE_64_regs
            IEM_INSTR_IMPL_A64__CBGE_64_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe04000/75000000: CBGT  <Wt>, #<imm>, <label>
   Instruction Set: A64  Groups: compbranch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_CBGT_32_imm, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
    uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
    {
        LogFlow(("%018x/%010x: CBGT_32_imm Rt=%#x imm9=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, imm6));
#ifdef IEM_INSTR_IMPL_A64__CBGT_32_imm
        IEM_INSTR_IMPL_A64__CBGT_32_imm(Rt, imm9, imm6);
#else
        RT_NOREF(Rt, imm9, imm6, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74000000: CBGT  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs, control */
FNIEMOP_DEF_1(iemDecodeA64_CBGT_32_regs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
    {
        LogFlow(("%018x/%010x: CBGT_32_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBGT_32_regs
        IEM_INSTR_IMPL_A64__CBGT_32_regs(Rt, imm9, Rm);
#else
        RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe04000/f5000000: CBGT  <Xt>, #<imm>, <label>
   Instruction Set: A64  Groups: compbranch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_CBGT_64_imm, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
    uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
    {
        LogFlow(("%018x/%010x: CBGT_64_imm Rt=%#x imm9=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, imm6));
#ifdef IEM_INSTR_IMPL_A64__CBGT_64_imm
        IEM_INSTR_IMPL_A64__CBGT_64_imm(Rt, imm9, imm6);
#else
        RT_NOREF(Rt, imm9, imm6, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/f4000000: CBGT  <Xt>, <Xm>, <label>
   Instruction Set: A64  Groups: compbranch_regs, control */
FNIEMOP_DEF_1(iemDecodeA64_CBGT_64_regs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
    {
        LogFlow(("%018x/%010x: CBGT_64_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBGT_64_regs
        IEM_INSTR_IMPL_A64__CBGT_64_regs(Rt, imm9, Rm);
#else
        RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74c0c000: CBHEQ  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs2, control */
FNIEMOP_DEF_1(iemDecodeA64_CBHEQ_16_regs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
    {
        LogFlow(("%018x/%010x: CBHEQ_16_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBHEQ_16_regs
        IEM_INSTR_IMPL_A64__CBHEQ_16_regs(Rt, imm9, Rm);
#else
        RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/7420c000: CBHGE  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs2, control */
FNIEMOP_DEF_1(iemDecodeA64_CBHGE_16_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x7420c000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBHGE_16_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBHGE_16_regs
            IEM_INSTR_IMPL_A64__CBHGE_16_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/7400c000: CBHGT  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs2, control */
FNIEMOP_DEF_1(iemDecodeA64_CBHGT_16_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x7400c000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBHGT_16_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBHGT_16_regs
            IEM_INSTR_IMPL_A64__CBHGT_16_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/7440c000: CBHHI  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs2, control */
FNIEMOP_DEF_1(iemDecodeA64_CBHHI_16_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x7440c000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBHHI_16_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBHHI_16_regs
            IEM_INSTR_IMPL_A64__CBHHI_16_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/7460c000: CBHHS  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs2, control */
FNIEMOP_DEF_1(iemDecodeA64_CBHHS_16_regs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
    {
        LogFlow(("%018x/%010x: CBHHS_16_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBHHS_16_regs
        IEM_INSTR_IMPL_A64__CBHHS_16_regs(Rt, imm9, Rm);
#else
        RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe04000/75400000: CBHI  <Wt>, #<imm>, <label>
   Instruction Set: A64  Groups: compbranch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_CBHI_32_imm, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe04000)) == UINT32_C(0x75400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBHI_32_imm Rt=%#x imm9=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, imm6));
#ifdef IEM_INSTR_IMPL_A64__CBHI_32_imm
            IEM_INSTR_IMPL_A64__CBHI_32_imm(Rt, imm9, imm6);
#else
            RT_NOREF(Rt, imm9, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74400000: CBHI  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs, control */
FNIEMOP_DEF_1(iemDecodeA64_CBHI_32_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBHI_32_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBHI_32_regs
            IEM_INSTR_IMPL_A64__CBHI_32_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe04000/f5400000: CBHI  <Xt>, #<imm>, <label>
   Instruction Set: A64  Groups: compbranch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_CBHI_64_imm, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe04000)) == UINT32_C(0xf5400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBHI_64_imm Rt=%#x imm9=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, imm6));
#ifdef IEM_INSTR_IMPL_A64__CBHI_64_imm
            IEM_INSTR_IMPL_A64__CBHI_64_imm(Rt, imm9, imm6);
#else
            RT_NOREF(Rt, imm9, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/f4400000: CBHI  <Xt>, <Xm>, <label>
   Instruction Set: A64  Groups: compbranch_regs, control */
FNIEMOP_DEF_1(iemDecodeA64_CBHI_64_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0xf4400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBHI_64_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBHI_64_regs
            IEM_INSTR_IMPL_A64__CBHI_64_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74e0c000: CBHNE  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs2, control */
FNIEMOP_DEF_1(iemDecodeA64_CBHNE_16_regs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
    {
        LogFlow(("%018x/%010x: CBHNE_16_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBHNE_16_regs
        IEM_INSTR_IMPL_A64__CBHNE_16_regs(Rt, imm9, Rm);
#else
        RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74600000: CBHS  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs, control */
FNIEMOP_DEF_1(iemDecodeA64_CBHS_32_regs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74600000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBHS_32_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBHS_32_regs
            IEM_INSTR_IMPL_A64__CBHS_32_regs(Rt, imm9, Rm);
#else
            RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/f4600000: CBHS  <Xt>, <Xm>, <label>
   Instruction Set: A64  Groups: compbranch_regs, control */
FNIEMOP_DEF_1(iemDecodeA64_CBHS_64_regs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
    {
        LogFlow(("%018x/%010x: CBHS_64_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBHS_64_regs
        IEM_INSTR_IMPL_A64__CBHS_64_regs(Rt, imm9, Rm);
#else
        RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe04000/75600000: CBLO  <Wt>, #<imm>, <label>
   Instruction Set: A64  Groups: compbranch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_CBLO_32_imm, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe04000)) == UINT32_C(0x75600000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBLO_32_imm Rt=%#x imm9=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, imm6));
#ifdef IEM_INSTR_IMPL_A64__CBLO_32_imm
            IEM_INSTR_IMPL_A64__CBLO_32_imm(Rt, imm9, imm6);
#else
            RT_NOREF(Rt, imm9, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe04000/f5600000: CBLO  <Xt>, #<imm>, <label>
   Instruction Set: A64  Groups: compbranch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_CBLO_64_imm, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe04000)) == UINT32_C(0xf5600000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBLO_64_imm Rt=%#x imm9=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, imm6));
#ifdef IEM_INSTR_IMPL_A64__CBLO_64_imm
            IEM_INSTR_IMPL_A64__CBLO_64_imm(Rt, imm9, imm6);
#else
            RT_NOREF(Rt, imm9, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe04000/75200000: CBLT  <Wt>, #<imm>, <label>
   Instruction Set: A64  Groups: compbranch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_CBLT_32_imm, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe04000)) == UINT32_C(0x75200000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBLT_32_imm Rt=%#x imm9=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, imm6));
#ifdef IEM_INSTR_IMPL_A64__CBLT_32_imm
            IEM_INSTR_IMPL_A64__CBLT_32_imm(Rt, imm9, imm6);
#else
            RT_NOREF(Rt, imm9, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe04000/f5200000: CBLT  <Xt>, #<imm>, <label>
   Instruction Set: A64  Groups: compbranch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_CBLT_64_imm, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe04000)) == UINT32_C(0xf5200000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBLT_64_imm Rt=%#x imm9=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, imm6));
#ifdef IEM_INSTR_IMPL_A64__CBLT_64_imm
            IEM_INSTR_IMPL_A64__CBLT_64_imm(Rt, imm9, imm6);
#else
            RT_NOREF(Rt, imm9, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe04000/75e00000: CBNE  <Wt>, #<imm>, <label>
   Instruction Set: A64  Groups: compbranch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_CBNE_32_imm, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe04000)) == UINT32_C(0x75e00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBNE_32_imm Rt=%#x imm9=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, imm6));
#ifdef IEM_INSTR_IMPL_A64__CBNE_32_imm
            IEM_INSTR_IMPL_A64__CBNE_32_imm(Rt, imm9, imm6);
#else
            RT_NOREF(Rt, imm9, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/74e00000: CBNE  <Wt>, <Wm>, <label>
   Instruction Set: A64  Groups: compbranch_regs, control */
FNIEMOP_DEF_1(iemDecodeA64_CBNE_32_regs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
    {
        LogFlow(("%018x/%010x: CBNE_32_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBNE_32_regs
        IEM_INSTR_IMPL_A64__CBNE_32_regs(Rt, imm9, Rm);
#else
        RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe04000/f5e00000: CBNE  <Xt>, #<imm>, <label>
   Instruction Set: A64  Groups: compbranch_imm, control */
FNIEMOP_DEF_1(iemDecodeA64_CBNE_64_imm, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe04000)) == UINT32_C(0xf5e00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
        uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
        {
            LogFlow(("%018x/%010x: CBNE_64_imm Rt=%#x imm9=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, imm6));
#ifdef IEM_INSTR_IMPL_A64__CBNE_64_imm
            IEM_INSTR_IMPL_A64__CBNE_64_imm(Rt, imm9, imm6);
#else
            RT_NOREF(Rt, imm9, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0c000/f4e00000: CBNE  <Xt>, <Xm>, <label>
   Instruction Set: A64  Groups: compbranch_regs, control */
FNIEMOP_DEF_1(iemDecodeA64_CBNE_64_regs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >>  5) & 0x000001ff;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CMPBR*/)
    {
        LogFlow(("%018x/%010x: CBNE_64_regs Rt=%#x imm9=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm9, Rm));
#ifdef IEM_INSTR_IMPL_A64__CBNE_64_regs
        IEM_INSTR_IMPL_A64__CBNE_64_regs(Rt, imm9, Rm);
#else
        RT_NOREF(Rt, imm9, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff000000/35000000: CBNZ  <Wt>, <label>
   Instruction Set: A64  Groups: compbranch, control */
FNIEMOP_DEF_1(iemDecodeA64_CBNZ_32_compbranch, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
    LogFlow(("%018x/%010x: CBNZ_32_compbranch Rt=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm19));
#ifdef IEM_INSTR_IMPL_A64__CBNZ_32_compbranch
    IEM_INSTR_IMPL_A64__CBNZ_32_compbranch(Rt, imm19);
#else
    RT_NOREF(Rt, imm19, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff000000/b5000000: CBNZ  <Xt>, <label>
   Instruction Set: A64  Groups: compbranch, control */
FNIEMOP_DEF_1(iemDecodeA64_CBNZ_64_compbranch, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
    LogFlow(("%018x/%010x: CBNZ_64_compbranch Rt=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm19));
#ifdef IEM_INSTR_IMPL_A64__CBNZ_64_compbranch
    IEM_INSTR_IMPL_A64__CBNZ_64_compbranch(Rt, imm19);
#else
    RT_NOREF(Rt, imm19, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff000000/34000000: CBZ  <Wt>, <label>
   Instruction Set: A64  Groups: compbranch, control */
FNIEMOP_DEF_1(iemDecodeA64_CBZ_32_compbranch, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
    LogFlow(("%018x/%010x: CBZ_32_compbranch Rt=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm19));
#ifdef IEM_INSTR_IMPL_A64__CBZ_32_compbranch
    IEM_INSTR_IMPL_A64__CBZ_32_compbranch(Rt, imm19);
#else
    RT_NOREF(Rt, imm19, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff000000/b4000000: CBZ  <Xt>, <label>
   Instruction Set: A64  Groups: compbranch, control */
FNIEMOP_DEF_1(iemDecodeA64_CBZ_64_compbranch, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
    LogFlow(("%018x/%010x: CBZ_64_compbranch Rt=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm19));
#ifdef IEM_INSTR_IMPL_A64__CBZ_64_compbranch
    IEM_INSTR_IMPL_A64__CBZ_64_compbranch(Rt, imm19);
#else
    RT_NOREF(Rt, imm19, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c10/3a400800: CCMN  <Wn>, #<imm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: condcmp_imm, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CCMN_32_condcmp_imm, uint32_t, uOpcode)
{
    uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: CCMN_32_condcmp_imm nzcv=%#x Rn=%#x cond=%#x imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, imm5));
#ifdef IEM_INSTR_IMPL_A64__CCMN_32_condcmp_imm
    IEM_INSTR_IMPL_A64__CCMN_32_condcmp_imm(nzcv, Rn, cond, imm5);
#else
    RT_NOREF(nzcv, Rn, cond, imm5, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c10/3a400000: CCMN  <Wn>, <Wm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: condcmp_reg, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CCMN_32_condcmp_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0x3a400000))
    {
        uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: CCMN_32_condcmp_reg nzcv=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__CCMN_32_condcmp_reg
        IEM_INSTR_IMPL_A64__CCMN_32_condcmp_reg(nzcv, Rn, cond, Rm);
#else
        RT_NOREF(nzcv, Rn, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c10/ba400800: CCMN  <Xn>, #<imm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: condcmp_imm, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CCMN_64_condcmp_imm, uint32_t, uOpcode)
{
    uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: CCMN_64_condcmp_imm nzcv=%#x Rn=%#x cond=%#x imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, imm5));
#ifdef IEM_INSTR_IMPL_A64__CCMN_64_condcmp_imm
    IEM_INSTR_IMPL_A64__CCMN_64_condcmp_imm(nzcv, Rn, cond, imm5);
#else
    RT_NOREF(nzcv, Rn, cond, imm5, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c10/ba400000: CCMN  <Xn>, <Xm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: condcmp_reg, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CCMN_64_condcmp_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0xba400000))
    {
        uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: CCMN_64_condcmp_reg nzcv=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__CCMN_64_condcmp_reg
        IEM_INSTR_IMPL_A64__CCMN_64_condcmp_reg(nzcv, Rn, cond, Rm);
#else
        RT_NOREF(nzcv, Rn, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c10/7a400800: CCMP  <Wn>, #<imm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: condcmp_imm, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CCMP_32_condcmp_imm, uint32_t, uOpcode)
{
    uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: CCMP_32_condcmp_imm nzcv=%#x Rn=%#x cond=%#x imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, imm5));
#ifdef IEM_INSTR_IMPL_A64__CCMP_32_condcmp_imm
    IEM_INSTR_IMPL_A64__CCMP_32_condcmp_imm(nzcv, Rn, cond, imm5);
#else
    RT_NOREF(nzcv, Rn, cond, imm5, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c10/7a400000: CCMP  <Wn>, <Wm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: condcmp_reg, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CCMP_32_condcmp_reg, uint32_t, uOpcode)
{
    uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: CCMP_32_condcmp_reg nzcv=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__CCMP_32_condcmp_reg
    IEM_INSTR_IMPL_A64__CCMP_32_condcmp_reg(nzcv, Rn, cond, Rm);
#else
    RT_NOREF(nzcv, Rn, cond, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c10/fa400800: CCMP  <Xn>, #<imm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: condcmp_imm, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CCMP_64_condcmp_imm, uint32_t, uOpcode)
{
    uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: CCMP_64_condcmp_imm nzcv=%#x Rn=%#x cond=%#x imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, imm5));
#ifdef IEM_INSTR_IMPL_A64__CCMP_64_condcmp_imm
    IEM_INSTR_IMPL_A64__CCMP_64_condcmp_imm(nzcv, Rn, cond, imm5);
#else
    RT_NOREF(nzcv, Rn, cond, imm5, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c10/fa400000: CCMP  <Xn>, <Xm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: condcmp_reg, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CCMP_64_condcmp_reg, uint32_t, uOpcode)
{
    uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: CCMP_64_condcmp_reg nzcv=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__CCMP_64_condcmp_reg
    IEM_INSTR_IMPL_A64__CCMP_64_condcmp_reg(nzcv, Rn, cond, Rm);
#else
    RT_NOREF(nzcv, Rn, cond, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffffffff/d500401f: CFINV
   Instruction Set: A64  Groups: pstate, control */
FNIEMOP_DEF_1(iemDecodeA64_CFINV_M_pstate, uint32_t, uOpcode)
{
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFlagM /*FEAT_FlagM*/)
    {
        LogFlow(("%018x/%010x: CFINV_M_pstate\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__CFINV_M_pstate
        IEM_INSTR_IMPL_A64__CFINV_M_pstate();
#else
        RT_NOREF(pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503251f: CHKFEAT  X16
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_CHKFEAT_HF_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503251f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fChk /*FEAT_CHK*/)
        {
            LogFlow(("%018x/%010x: CHKFEAT_HF_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__CHKFEAT_HF_hints
            IEM_INSTR_IMPL_A64__CHKFEAT_HF_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d50322df: CLRBHB
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_CLRBHB_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd50322df))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fClrBhb /*FEAT_CLRBHB*/)
        {
            LogFlow(("%018x/%010x: CLRBHB_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__CLRBHB_HI_hints
            IEM_INSTR_IMPL_A64__CLRBHB_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffff0ff/d503305f: CLREX{  #<imm>}
   Instruction Set: A64  Groups: barriers, control */
FNIEMOP_DEF_1(iemDecodeA64_CLREX_BN_barriers, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffff0ff)) == UINT32_C(0xd503305f))
    {
        uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
        LogFlow(("%018x/%010x: CLREX_BN_barriers CRm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, CRm));
#ifdef IEM_INSTR_IMPL_A64__CLREX_BN_barriers
        IEM_INSTR_IMPL_A64__CLREX_BN_barriers(CRm);
#else
        RT_NOREF(CRm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ac01400: CLS  <Wd>, <Wn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CLS_32_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 10) & 0x00000001;
    LogFlow(("%018x/%010x: CLS_32_dp_1src Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__CLS_32_dp_1src
    IEM_INSTR_IMPL_A64__CLS_32_dp_1src(Rd, Rn, op);
#else
    RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/dac01400: CLS  <Xd>, <Xn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CLS_64_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 10) & 0x00000001;
    LogFlow(("%018x/%010x: CLS_64_dp_1src Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__CLS_64_dp_1src
    IEM_INSTR_IMPL_A64__CLS_64_dp_1src(Rd, Rn, op);
#else
    RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf3ffc00/0e204800: CLS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CLS_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e204800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CLS_asimdmisc_R Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CLS_asimdmisc_R
            IEM_INSTR_IMPL_A64__CLS_asimdmisc_R(Rd, Rn, size, Q);
#else
            RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ac01000: CLZ  <Wd>, <Wn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CLZ_32_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 10) & 0x00000001;
    LogFlow(("%018x/%010x: CLZ_32_dp_1src Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__CLZ_32_dp_1src
    IEM_INSTR_IMPL_A64__CLZ_32_dp_1src(Rd, Rn, op);
#else
    RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/dac01000: CLZ  <Xd>, <Xn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CLZ_64_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 10) & 0x00000001;
    LogFlow(("%018x/%010x: CLZ_64_dp_1src Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__CLZ_64_dp_1src
    IEM_INSTR_IMPL_A64__CLZ_64_dp_1src(Rd, Rn, op);
#else
    RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf3ffc00/2e204800: CLZ  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CLZ_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: CLZ_asimdmisc_R Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CLZ_asimdmisc_R
        IEM_INSTR_IMPL_A64__CLZ_asimdmisc_R(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e209800: CMEQ  <Vd>.<T>, <Vn>.<T>, #0
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMEQ_asimdmisc_Z, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: CMEQ_asimdmisc_Z Rd=%#x Rn=%#x op=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CMEQ_asimdmisc_Z
        IEM_INSTR_IMPL_A64__CMEQ_asimdmisc_Z(Rd, Rn, op, size, Q);
#else
        RT_NOREF(Rd, Rn, op, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e208c00: CMEQ  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMEQ_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e208c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMEQ_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CMEQ_asimdsame_only
            IEM_INSTR_IMPL_A64__CMEQ_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ee09800: CMEQ  D<d>, D<n>, #0
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMEQ_asisdmisc_Z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ee09800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMEQ_asisdmisc_Z Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__CMEQ_asisdmisc_Z
            IEM_INSTR_IMPL_A64__CMEQ_asisdmisc_Z(Rd, Rn, op);
#else
            RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ee08c00: CMEQ  D<d>, D<n>, D<m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMEQ_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ee08c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMEQ_asisdsame_only Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__CMEQ_asisdsame_only
            IEM_INSTR_IMPL_A64__CMEQ_asisdsame_only(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e208800: CMGE  <Vd>.<T>, <Vn>.<T>, #0
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMGE_asimdmisc_Z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e208800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMGE_asimdmisc_Z Rd=%#x Rn=%#x op=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CMGE_asimdmisc_Z
            IEM_INSTR_IMPL_A64__CMGE_asimdmisc_Z(Rd, Rn, op, size, Q);
#else
            RT_NOREF(Rd, Rn, op, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e203c00: CMGE  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMGE_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const eq         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: CMGE_asimdsame_only Rd=%#x Rn=%#x eq=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, eq, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CMGE_asimdsame_only
        IEM_INSTR_IMPL_A64__CMGE_asimdsame_only(Rd, Rn, eq, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, eq, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7ee08800: CMGE  D<d>, D<n>, #0
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMGE_asisdmisc_Z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7ee08800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMGE_asisdmisc_Z Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__CMGE_asisdmisc_Z
            IEM_INSTR_IMPL_A64__CMGE_asisdmisc_Z(Rd, Rn, op);
#else
            RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5ee03c00: CMGE  D<d>, D<n>, D<m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMGE_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5ee03c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const eq         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMGE_asisdsame_only Rd=%#x Rn=%#x eq=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, eq, Rm));
#ifdef IEM_INSTR_IMPL_A64__CMGE_asisdsame_only
            IEM_INSTR_IMPL_A64__CMGE_asisdsame_only(Rd, Rn, eq, Rm);
#else
            RT_NOREF(Rd, Rn, eq, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e208800: CMGT  <Vd>.<T>, <Vn>.<T>, #0
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMGT_asimdmisc_Z, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: CMGT_asimdmisc_Z Rd=%#x Rn=%#x op=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CMGT_asimdmisc_Z
        IEM_INSTR_IMPL_A64__CMGT_asimdmisc_Z(Rd, Rn, op, size, Q);
#else
        RT_NOREF(Rd, Rn, op, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e203400: CMGT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMGT_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const eq         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: CMGT_asimdsame_only Rd=%#x Rn=%#x eq=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, eq, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CMGT_asimdsame_only
        IEM_INSTR_IMPL_A64__CMGT_asimdsame_only(Rd, Rn, eq, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, eq, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ee08800: CMGT  D<d>, D<n>, #0
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMGT_asisdmisc_Z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ee08800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMGT_asisdmisc_Z Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__CMGT_asisdmisc_Z
            IEM_INSTR_IMPL_A64__CMGT_asisdmisc_Z(Rd, Rn, op);
#else
            RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5ee03400: CMGT  D<d>, D<n>, D<m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMGT_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const eq         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: CMGT_asisdsame_only Rd=%#x Rn=%#x eq=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, eq, Rm));
#ifdef IEM_INSTR_IMPL_A64__CMGT_asisdsame_only
        IEM_INSTR_IMPL_A64__CMGT_asisdsame_only(Rd, Rn, eq, Rm);
#else
        RT_NOREF(Rd, Rn, eq, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e203400: CMHI  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMHI_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e203400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const eq         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMHI_asimdsame_only Rd=%#x Rn=%#x eq=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, eq, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CMHI_asimdsame_only
            IEM_INSTR_IMPL_A64__CMHI_asimdsame_only(Rd, Rn, eq, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, eq, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ee03400: CMHI  D<d>, D<n>, D<m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMHI_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ee03400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const eq         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMHI_asisdsame_only Rd=%#x Rn=%#x eq=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, eq, Rm));
#ifdef IEM_INSTR_IMPL_A64__CMHI_asisdsame_only
            IEM_INSTR_IMPL_A64__CMHI_asisdsame_only(Rd, Rn, eq, Rm);
#else
            RT_NOREF(Rd, Rn, eq, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e203c00: CMHS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMHS_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e203c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const eq         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMHS_asimdsame_only Rd=%#x Rn=%#x eq=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, eq, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CMHS_asimdsame_only
            IEM_INSTR_IMPL_A64__CMHS_asimdsame_only(Rd, Rn, eq, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, eq, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ee03c00: CMHS  D<d>, D<n>, D<m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMHS_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ee03c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const eq         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMHS_asisdsame_only Rd=%#x Rn=%#x eq=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, eq, Rm));
#ifdef IEM_INSTR_IMPL_A64__CMHS_asisdsame_only
            IEM_INSTR_IMPL_A64__CMHS_asisdsame_only(Rd, Rn, eq, Rm);
#else
            RT_NOREF(Rd, Rn, eq, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e209800: CMLE  <Vd>.<T>, <Vn>.<T>, #0
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMLE_asimdmisc_Z, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: CMLE_asimdmisc_Z Rd=%#x Rn=%#x op=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CMLE_asimdmisc_Z
        IEM_INSTR_IMPL_A64__CMLE_asimdmisc_Z(Rd, Rn, op, size, Q);
#else
        RT_NOREF(Rd, Rn, op, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7ee09800: CMLE  D<d>, D<n>, #0
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMLE_asisdmisc_Z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7ee09800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMLE_asisdmisc_Z Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__CMLE_asisdmisc_Z
            IEM_INSTR_IMPL_A64__CMLE_asisdmisc_Z(Rd, Rn, op);
#else
            RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e20a800: CMLT  <Vd>.<T>, <Vn>.<T>, #0
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMLT_asimdmisc_Z, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: CMLT_asimdmisc_Z Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CMLT_asimdmisc_Z
        IEM_INSTR_IMPL_A64__CMLT_asimdmisc_Z(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ee0a800: CMLT  D<d>, D<n>, #0
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMLT_asisdmisc_Z, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: CMLT_asisdmisc_Z Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__CMLT_asisdmisc_Z
        IEM_INSTR_IMPL_A64__CMLT_asisdmisc_Z(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e208c00: CMTST  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMTST_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: CMTST_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CMTST_asimdsame_only
        IEM_INSTR_IMPL_A64__CMTST_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5ee08c00: CMTST  D<d>, D<n>, D<m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CMTST_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5ee08c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: CMTST_asisdsame_only Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__CMTST_asisdsame_only
            IEM_INSTR_IMPL_A64__CMTST_asisdsame_only(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ac01c00: CNT  <Wd>, <Wn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CNT_32_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: CNT_32_dp_1src Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__CNT_32_dp_1src
        IEM_INSTR_IMPL_A64__CNT_32_dp_1src(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/dac01c00: CNT  <Xd>, <Xn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CNT_64_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: CNT_64_dp_1src Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__CNT_64_dp_1src
        IEM_INSTR_IMPL_A64__CNT_64_dp_1src(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e205800: CNT  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_CNT_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: CNT_asimdmisc_R Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__CNT_asimdmisc_R
        IEM_INSTR_IMPL_A64__CNT_asimdmisc_R(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d80c400: CPYEN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYEN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYEN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYEN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYEN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d808400: CPYERN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYERN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYERN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYERN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYERN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d80e400: CPYERTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYERTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYERTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYERTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYERTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d80a400: CPYERTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYERTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYERTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYERTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYERTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d806400: CPYERTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYERTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYERTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYERTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYERTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d802400: CPYERT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYERT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYERT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYERT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYERT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d80f400: CPYETN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYETN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYETN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYETN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYETN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d80b400: CPYETRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYETRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYETRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYETRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYETRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d807400: CPYETWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYETWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYETWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYETWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYETWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d803400: CPYET  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYET_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYET_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYET_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYET_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d804400: CPYEWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYEWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYEWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYEWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYEWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d80d400: CPYEWTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYEWTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYEWTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYEWTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYEWTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d809400: CPYEWTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYEWTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYEWTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYEWTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYEWTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d805400: CPYEWTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYEWTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYEWTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYEWTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYEWTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d801400: CPYEWT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYEWT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYEWT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYEWT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYEWT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d800400: CPYE  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYE_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYE_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYE_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYE_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1980c400: CPYFEN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFEN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFEN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFEN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFEN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19808400: CPYFERN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFERN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFERN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFERN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFERN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1980e400: CPYFERTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFERTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFERTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFERTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFERTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1980a400: CPYFERTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFERTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFERTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFERTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFERTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19806400: CPYFERTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFERTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFERTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFERTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFERTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19802400: CPYFERT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFERT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFERT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFERT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFERT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1980f400: CPYFETN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFETN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFETN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFETN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFETN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1980b400: CPYFETRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFETRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFETRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFETRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFETRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19807400: CPYFETWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFETWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFETWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFETWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFETWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19803400: CPYFET  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFET_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFET_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFET_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFET_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19804400: CPYFEWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFEWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFEWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFEWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFEWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1980d400: CPYFEWTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFEWTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFEWTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFEWTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFEWTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19809400: CPYFEWTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFEWTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFEWTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFEWTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFEWTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19805400: CPYFEWTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFEWTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFEWTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFEWTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFEWTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19801400: CPYFEWT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFEWT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFEWT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFEWT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFEWT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19800400: CPYFE  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFE_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFE_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFE_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFE_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1940c400: CPYFMN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19408400: CPYFMRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1940e400: CPYFMRTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMRTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMRTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMRTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMRTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1940a400: CPYFMRTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMRTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMRTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMRTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMRTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19406400: CPYFMRTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMRTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMRTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMRTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMRTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19402400: CPYFMRT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMRT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMRT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMRT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMRT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1940f400: CPYFMTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1940b400: CPYFMTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19407400: CPYFMTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19403400: CPYFMT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19404400: CPYFMWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1940d400: CPYFMWTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMWTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMWTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMWTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMWTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19409400: CPYFMWTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMWTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMWTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMWTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMWTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19405400: CPYFMWTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMWTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMWTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMWTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMWTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19401400: CPYFMWT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFMWT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFMWT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFMWT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFMWT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19400400: CPYFM  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFM_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFM_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFM_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFM_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1900c400: CPYFPN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19008400: CPYFPRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPRN_CPY_memcms, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19008400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
        {
            LogFlow(("%018x/%010x: CPYFPRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPRN_CPY_memcms
            IEM_INSTR_IMPL_A64__CPYFPRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
            RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1900e400: CPYFPRTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPRTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPRTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPRTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPRTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1900a400: CPYFPRTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPRTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPRTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPRTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPRTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19006400: CPYFPRTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPRTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPRTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPRTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPRTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19002400: CPYFPRT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPRT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPRT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPRT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPRT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1900f400: CPYFPTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1900b400: CPYFPTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19007400: CPYFPTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19003400: CPYFPT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19004400: CPYFPWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1900d400: CPYFPWTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPWTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPWTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPWTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPWTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19009400: CPYFPWTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPWTRN_CPY_memcms, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19009400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
        {
            LogFlow(("%018x/%010x: CPYFPWTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPWTRN_CPY_memcms
            IEM_INSTR_IMPL_A64__CPYFPWTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
            RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19005400: CPYFPWTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPWTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPWTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPWTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPWTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19001400: CPYFPWT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFPWT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYFPWT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFPWT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYFPWT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19000400: CPYFP  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYFP_CPY_memcms, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19000400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
        {
            LogFlow(("%018x/%010x: CPYFP_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYFP_CPY_memcms
            IEM_INSTR_IMPL_A64__CPYFP_CPY_memcms(Rd, Rn, Rs, sz);
#else
            RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d40c400: CPYMN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d408400: CPYMRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d40e400: CPYMRTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMRTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMRTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMRTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMRTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d40a400: CPYMRTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMRTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMRTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMRTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMRTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d406400: CPYMRTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMRTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMRTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMRTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMRTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d402400: CPYMRT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMRT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMRT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMRT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMRT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d40f400: CPYMTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d40b400: CPYMTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d407400: CPYMTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d403400: CPYMT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d404400: CPYMWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d40d400: CPYMWTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMWTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMWTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMWTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMWTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d409400: CPYMWTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMWTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMWTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMWTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMWTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d405400: CPYMWTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMWTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMWTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMWTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMWTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d401400: CPYMWT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYMWT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYMWT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYMWT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYMWT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d400400: CPYM  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYM_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYM_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYM_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYM_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d00c400: CPYPN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d008400: CPYPRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPRN_CPY_memcms, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d008400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
        {
            LogFlow(("%018x/%010x: CPYPRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPRN_CPY_memcms
            IEM_INSTR_IMPL_A64__CPYPRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
            RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d00e400: CPYPRTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPRTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPRTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPRTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPRTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d00a400: CPYPRTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPRTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPRTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPRTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPRTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d006400: CPYPRTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPRTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPRTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPRTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPRTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d002400: CPYPRT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPRT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPRT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPRT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPRT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d00f400: CPYPTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d00b400: CPYPTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPTRN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPTRN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d007400: CPYPTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d003400: CPYPT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d004400: CPYPWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d00d400: CPYPWTN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPWTN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPWTN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPWTN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPWTN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d009400: CPYPWTRN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPWTRN_CPY_memcms, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d009400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
        {
            LogFlow(("%018x/%010x: CPYPWTRN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPWTRN_CPY_memcms
            IEM_INSTR_IMPL_A64__CPYPWTRN_CPY_memcms(Rd, Rn, Rs, sz);
#else
            RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d005400: CPYPWTWN  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPWTWN_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPWTWN_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPWTWN_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPWTWN_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d001400: CPYPWT  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYPWT_CPY_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: CPYPWT_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYPWT_CPY_memcms
        IEM_INSTR_IMPL_A64__CPYPWT_CPY_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1d000400: CPYP  [<Xd>]!, [<Xs>]!, <Xn>!
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_CPYP_CPY_memcms, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d000400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
        {
            LogFlow(("%018x/%010x: CPYP_CPY_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__CPYP_CPY_memcms
            IEM_INSTR_IMPL_A64__CPYP_CPY_memcms(Rd, Rn, Rs, sz);
#else
            RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac04000: CRC32B  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CRC32B_32C_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac04000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 10) & 0x00000003;
        uint32_t const C          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCrc32 /*FEAT_CRC32*/)
        {
            LogFlow(("%018x/%010x: CRC32B_32C_dp_2src Rd=%#x Rn=%#x sz=%u C=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, C, Rm));
#ifdef IEM_INSTR_IMPL_A64__CRC32B_32C_dp_2src
            IEM_INSTR_IMPL_A64__CRC32B_32C_dp_2src(Rd, Rn, sz, C, Rm);
#else
            RT_NOREF(Rd, Rn, sz, C, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac05000: CRC32CB  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CRC32CB_32C_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac05000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 10) & 0x00000003;
        uint32_t const C          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCrc32 /*FEAT_CRC32*/)
        {
            LogFlow(("%018x/%010x: CRC32CB_32C_dp_2src Rd=%#x Rn=%#x sz=%u C=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, C, Rm));
#ifdef IEM_INSTR_IMPL_A64__CRC32CB_32C_dp_2src
            IEM_INSTR_IMPL_A64__CRC32CB_32C_dp_2src(Rd, Rn, sz, C, Rm);
#else
            RT_NOREF(Rd, Rn, sz, C, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac05400: CRC32CH  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CRC32CH_32C_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 10) & 0x00000003;
    uint32_t const C          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCrc32 /*FEAT_CRC32*/)
    {
        LogFlow(("%018x/%010x: CRC32CH_32C_dp_2src Rd=%#x Rn=%#x sz=%u C=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, C, Rm));
#ifdef IEM_INSTR_IMPL_A64__CRC32CH_32C_dp_2src
        IEM_INSTR_IMPL_A64__CRC32CH_32C_dp_2src(Rd, Rn, sz, C, Rm);
#else
        RT_NOREF(Rd, Rn, sz, C, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac05800: CRC32CW  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CRC32CW_32C_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac05800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 10) & 0x00000003;
        uint32_t const C          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCrc32 /*FEAT_CRC32*/)
        {
            LogFlow(("%018x/%010x: CRC32CW_32C_dp_2src Rd=%#x Rn=%#x sz=%u C=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, C, Rm));
#ifdef IEM_INSTR_IMPL_A64__CRC32CW_32C_dp_2src
            IEM_INSTR_IMPL_A64__CRC32CW_32C_dp_2src(Rd, Rn, sz, C, Rm);
#else
            RT_NOREF(Rd, Rn, sz, C, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9ac05c00: CRC32CX  <Wd>, <Wn>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CRC32CX_64C_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac05c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 10) & 0x00000003;
        uint32_t const C          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCrc32 /*FEAT_CRC32*/)
        {
            LogFlow(("%018x/%010x: CRC32CX_64C_dp_2src Rd=%#x Rn=%#x sz=%u C=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, C, Rm));
#ifdef IEM_INSTR_IMPL_A64__CRC32CX_64C_dp_2src
            IEM_INSTR_IMPL_A64__CRC32CX_64C_dp_2src(Rd, Rn, sz, C, Rm);
#else
            RT_NOREF(Rd, Rn, sz, C, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac04400: CRC32H  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CRC32H_32C_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 10) & 0x00000003;
    uint32_t const C          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCrc32 /*FEAT_CRC32*/)
    {
        LogFlow(("%018x/%010x: CRC32H_32C_dp_2src Rd=%#x Rn=%#x sz=%u C=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, C, Rm));
#ifdef IEM_INSTR_IMPL_A64__CRC32H_32C_dp_2src
        IEM_INSTR_IMPL_A64__CRC32H_32C_dp_2src(Rd, Rn, sz, C, Rm);
#else
        RT_NOREF(Rd, Rn, sz, C, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac04800: CRC32W  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CRC32W_32C_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac04800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 10) & 0x00000003;
        uint32_t const C          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCrc32 /*FEAT_CRC32*/)
        {
            LogFlow(("%018x/%010x: CRC32W_32C_dp_2src Rd=%#x Rn=%#x sz=%u C=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, C, Rm));
#ifdef IEM_INSTR_IMPL_A64__CRC32W_32C_dp_2src
            IEM_INSTR_IMPL_A64__CRC32W_32C_dp_2src(Rd, Rn, sz, C, Rm);
#else
            RT_NOREF(Rd, Rn, sz, C, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9ac04c00: CRC32X  <Wd>, <Wn>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CRC32X_64C_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac04c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 10) & 0x00000003;
        uint32_t const C          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCrc32 /*FEAT_CRC32*/)
        {
            LogFlow(("%018x/%010x: CRC32X_64C_dp_2src Rd=%#x Rn=%#x sz=%u C=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, C, Rm));
#ifdef IEM_INSTR_IMPL_A64__CRC32X_64C_dp_2src
            IEM_INSTR_IMPL_A64__CRC32X_64C_dp_2src(Rd, Rn, sz, C, Rm);
#else
            RT_NOREF(Rd, Rn, sz, C, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503229f: CSDB
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_CSDB_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503229f))
    {
        LogFlow(("%018x/%010x: CSDB_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__CSDB_HI_hints
        IEM_INSTR_IMPL_A64__CSDB_HI_hints();
#else
        RT_NOREF(pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/1a800000: CSEL  <Wd>, <Wn>, <Wm>, <cond>
   Instruction Set: A64  Groups: condsel, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CSEL_32_condsel, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x1a800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o2         = (uOpcode >> 10) & 0x00000001;
        uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: CSEL_32_condsel Rd=%#x Rn=%#x o2=%u cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o2, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__CSEL_32_condsel
        IEM_INSTR_IMPL_A64__CSEL_32_condsel(Rd, Rn, o2, cond, Rm);
#else
        RT_NOREF(Rd, Rn, o2, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/9a800000: CSEL  <Xd>, <Xn>, <Xm>, <cond>
   Instruction Set: A64  Groups: condsel, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CSEL_64_condsel, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x9a800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o2         = (uOpcode >> 10) & 0x00000001;
        uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: CSEL_64_condsel Rd=%#x Rn=%#x o2=%u cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o2, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__CSEL_64_condsel
        IEM_INSTR_IMPL_A64__CSEL_64_condsel(Rd, Rn, o2, cond, Rm);
#else
        RT_NOREF(Rd, Rn, o2, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/1a800400: CSINC  <Wd>, <Wn>, <Wm>, <cond>
   Instruction Set: A64  Groups: condsel, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CSINC_32_condsel, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o2         = (uOpcode >> 10) & 0x00000001;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: CSINC_32_condsel Rd=%#x Rn=%#x o2=%u cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o2, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__CSINC_32_condsel
    IEM_INSTR_IMPL_A64__CSINC_32_condsel(Rd, Rn, o2, cond, Rm);
#else
    RT_NOREF(Rd, Rn, o2, cond, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/9a800400: CSINC  <Xd>, <Xn>, <Xm>, <cond>
   Instruction Set: A64  Groups: condsel, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CSINC_64_condsel, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o2         = (uOpcode >> 10) & 0x00000001;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: CSINC_64_condsel Rd=%#x Rn=%#x o2=%u cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o2, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__CSINC_64_condsel
    IEM_INSTR_IMPL_A64__CSINC_64_condsel(Rd, Rn, o2, cond, Rm);
#else
    RT_NOREF(Rd, Rn, o2, cond, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/5a800000: CSINV  <Wd>, <Wn>, <Wm>, <cond>
   Instruction Set: A64  Groups: condsel, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CSINV_32_condsel, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x5a800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o2         = (uOpcode >> 10) & 0x00000001;
        uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: CSINV_32_condsel Rd=%#x Rn=%#x o2=%u cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o2, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__CSINV_32_condsel
        IEM_INSTR_IMPL_A64__CSINV_32_condsel(Rd, Rn, o2, cond, Rm);
#else
        RT_NOREF(Rd, Rn, o2, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/da800000: CSINV  <Xd>, <Xn>, <Xm>, <cond>
   Instruction Set: A64  Groups: condsel, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CSINV_64_condsel, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xda800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o2         = (uOpcode >> 10) & 0x00000001;
        uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: CSINV_64_condsel Rd=%#x Rn=%#x o2=%u cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o2, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__CSINV_64_condsel
        IEM_INSTR_IMPL_A64__CSINV_64_condsel(Rd, Rn, o2, cond, Rm);
#else
        RT_NOREF(Rd, Rn, o2, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/5a800400: CSNEG  <Wd>, <Wn>, <Wm>, <cond>
   Instruction Set: A64  Groups: condsel, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CSNEG_32_condsel, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x5a800400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o2         = (uOpcode >> 10) & 0x00000001;
        uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: CSNEG_32_condsel Rd=%#x Rn=%#x o2=%u cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o2, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__CSNEG_32_condsel
        IEM_INSTR_IMPL_A64__CSNEG_32_condsel(Rd, Rn, o2, cond, Rm);
#else
        RT_NOREF(Rd, Rn, o2, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/da800400: CSNEG  <Xd>, <Xn>, <Xm>, <cond>
   Instruction Set: A64  Groups: condsel, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CSNEG_64_condsel, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xda800400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o2         = (uOpcode >> 10) & 0x00000001;
        uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: CSNEG_64_condsel Rd=%#x Rn=%#x o2=%u cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o2, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__CSNEG_64_condsel
        IEM_INSTR_IMPL_A64__CSNEG_64_condsel(Rd, Rn, o2, cond, Rm);
#else
        RT_NOREF(Rd, Rn, o2, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ac01800: CTZ  <Wd>, <Wn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CTZ_32_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: CTZ_32_dp_1src Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__CTZ_32_dp_1src
        IEM_INSTR_IMPL_A64__CTZ_32_dp_1src(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/dac01800: CTZ  <Xd>, <Xn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_CTZ_64_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: CTZ_64_dp_1src Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__CTZ_64_dp_1src
        IEM_INSTR_IMPL_A64__CTZ_64_dp_1src(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001f/d4a00001: DCPS1{  #<imm>}
   Instruction Set: A64  Groups: exception, control */
FNIEMOP_DEF_1(iemDecodeA64_DCPS1_DC_exception, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0xd4a00001))
    {
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        LogFlow(("%018x/%010x: DCPS1_DC_exception imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__DCPS1_DC_exception
        IEM_INSTR_IMPL_A64__DCPS1_DC_exception(imm16);
#else
        RT_NOREF(imm16, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001f/d4a00002: DCPS2{  #<imm>}
   Instruction Set: A64  Groups: exception, control */
FNIEMOP_DEF_1(iemDecodeA64_DCPS2_DC_exception, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0xd4a00002))
    {
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        LogFlow(("%018x/%010x: DCPS2_DC_exception imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__DCPS2_DC_exception
        IEM_INSTR_IMPL_A64__DCPS2_DC_exception(imm16);
#else
        RT_NOREF(imm16, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001f/d4a00003: DCPS3{  #<imm>}
   Instruction Set: A64  Groups: exception, control */
FNIEMOP_DEF_1(iemDecodeA64_DCPS3_DC_exception, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0xd4a00003))
    {
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        LogFlow(("%018x/%010x: DCPS3_DC_exception imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__DCPS3_DC_exception
        IEM_INSTR_IMPL_A64__DCPS3_DC_exception(imm16);
#else
        RT_NOREF(imm16, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d50320df: DGH
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_DGH_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd50320df))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fDgh /*FEAT_DGH*/)
        {
            LogFlow(("%018x/%010x: DGH_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__DGH_HI_hints
            IEM_INSTR_IMPL_A64__DGH_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffff0ff/d50330bf: DMB  {<option> | #<imm>}
   Instruction Set: A64  Groups: barriers, control */
FNIEMOP_DEF_1(iemDecodeA64_DMB_BO_barriers, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffff0ff)) == UINT32_C(0xd50330bf))
    {
        uint32_t const opc        = (uOpcode >>  5) & 0x00000003;
        uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
        LogFlow(("%018x/%010x: DMB_BO_barriers opc=%u CRm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, CRm));
#ifdef IEM_INSTR_IMPL_A64__DMB_BO_barriers
        IEM_INSTR_IMPL_A64__DMB_BO_barriers(opc, CRm);
#else
        RT_NOREF(opc, CRm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d6bf03e0: DRPS
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_DRPS_64E_branch_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd6bf03e0))
    {
        LogFlow(("%018x/%010x: DRPS_64E_branch_reg\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__DRPS_64E_branch_reg
        IEM_INSTR_IMPL_A64__DRPS_64E_branch_reg();
#else
        RT_NOREF(pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffff0ff/d503309f: DSB  {<option> | #<imm>}
   Instruction Set: A64  Groups: barriers, control */
FNIEMOP_DEF_1(iemDecodeA64_DSB_BO_barriers, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffff0ff)) == UINT32_C(0xd503309f))
    {
        uint32_t const opc        = (uOpcode >>  5) & 0x00000003;
        uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
        LogFlow(("%018x/%010x: DSB_BO_barriers opc=%u CRm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, CRm));
#ifdef IEM_INSTR_IMPL_A64__DSB_BO_barriers
        IEM_INSTR_IMPL_A64__DSB_BO_barriers(opc, CRm);
#else
        RT_NOREF(opc, CRm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffff3ff/d503323f: DSB  <option>nXS
   Instruction Set: A64  Groups: barriers, control */
FNIEMOP_DEF_1(iemDecodeA64_DSB_BOn_barriers, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffff3ff)) == UINT32_C(0xd503323f))
    {
        uint32_t const imm2       = (uOpcode >> 10) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXs /*FEAT_XS*/)
        {
            LogFlow(("%018x/%010x: DSB_BOn_barriers imm2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm2));
#ifdef IEM_INSTR_IMPL_A64__DSB_BOn_barriers
            IEM_INSTR_IMPL_A64__DSB_BOn_barriers(imm2);
#else
            RT_NOREF(imm2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e000c00: DUP  <Vd>.<T>, <R><n>
   Instruction Set: A64  Groups: asimdins, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_DUP_asimdins_DR_r, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e000c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: DUP_asimdins_DR_r Rd=%#x Rn=%#x imm5=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm5, Q));
#ifdef IEM_INSTR_IMPL_A64__DUP_asimdins_DR_r
            IEM_INSTR_IMPL_A64__DUP_asimdins_DR_r(Rd, Rn, imm5, Q);
#else
            RT_NOREF(Rd, Rn, imm5, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e000400: DUP  <Vd>.<T>, <Vn>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdins, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_DUP_asimdins_DV_v, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e000400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: DUP_asimdins_DV_v Rd=%#x Rn=%#x imm5=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm5, Q));
#ifdef IEM_INSTR_IMPL_A64__DUP_asimdins_DV_v
            IEM_INSTR_IMPL_A64__DUP_asimdins_DV_v(Rd, Rn, imm5, Q);
#else
            RT_NOREF(Rd, Rn, imm5, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5e000400: DUP  <V><d>, <Vn>.<T>[<index>]
   Instruction Set: A64  Groups: asisdone, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_DUP_asisdone_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5e000400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: DUP_asisdone_only Rd=%#x Rn=%#x imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm5));
#ifdef IEM_INSTR_IMPL_A64__DUP_asisdone_only
            IEM_INSTR_IMPL_A64__DUP_asisdone_only(Rd, Rn, imm5);
#else
            RT_NOREF(Rd, Rn, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff200000/4a200000: EON  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_EON_32_log_shift, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff200000)) == UINT32_C(0x4a200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
        LogFlow(("%018x/%010x: EON_32_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__EON_32_log_shift
        IEM_INSTR_IMPL_A64__EON_32_log_shift(Rd, Rn, imm6, Rm, shift);
#else
        RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff200000/ca200000: EON  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_EON_64_log_shift, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff200000)) == UINT32_C(0xca200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
        LogFlow(("%018x/%010x: EON_64_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__EON_64_log_shift
        IEM_INSTR_IMPL_A64__EON_64_log_shift(Rd, Rn, imm6, Rm, shift);
#else
        RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/ce000000: EOR3  <Vd>.16B, <Vn>.16B, <Vm>.16B, <Va>.16B
   Instruction Set: A64  Groups: crypto4, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_EOR3_VVV16_crypto4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0xce000000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha3 /*FEAT_SHA3*/)
        {
            LogFlow(("%018x/%010x: EOR3_VVV16_crypto4 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__EOR3_VVV16_crypto4
            IEM_INSTR_IMPL_A64__EOR3_VVV16_crypto4(Rd, Rn, Ra, Rm);
#else
            RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/52000000: EOR  <Wd|WSP>, <Wn>, #<imm>
   Instruction Set: A64  Groups: log_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_EOR_32_log_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
    LogFlow(("%018x/%010x: EOR_32_log_imm Rd=%#x Rn=%#x imms=%#x immr=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr));
#ifdef IEM_INSTR_IMPL_A64__EOR_32_log_imm
    IEM_INSTR_IMPL_A64__EOR_32_log_imm(Rd, Rn, imms, immr);
#else
    RT_NOREF(Rd, Rn, imms, immr, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/4a000000: EOR  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_EOR_32_log_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: EOR_32_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__EOR_32_log_shift
    IEM_INSTR_IMPL_A64__EOR_32_log_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff800000/d2000000: EOR  <Xd|SP>, <Xn>, #<imm>
   Instruction Set: A64  Groups: log_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_EOR_64_log_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const N          = (uOpcode >> 22) & 0x00000001;
    LogFlow(("%018x/%010x: EOR_64_log_imm Rd=%#x Rn=%#x imms=%#x immr=%#x N=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr, N));
#ifdef IEM_INSTR_IMPL_A64__EOR_64_log_imm
    IEM_INSTR_IMPL_A64__EOR_64_log_imm(Rd, Rn, imms, immr, N);
#else
    RT_NOREF(Rd, Rn, imms, immr, N, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/ca000000: EOR  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_EOR_64_log_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: EOR_64_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__EOR_64_log_shift
    IEM_INSTR_IMPL_A64__EOR_64_log_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bfe0fc00/2e201c00: EOR  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_EOR_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2e201c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const opc2       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: EOR_asimdsame_only Rd=%#x Rn=%#x Rm=%#x opc2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, opc2, Q));
#ifdef IEM_INSTR_IMPL_A64__EOR_asimdsame_only
            IEM_INSTR_IMPL_A64__EOR_asimdsame_only(Rd, Rn, Rm, opc2, Q);
#else
            RT_NOREF(Rd, Rn, Rm, opc2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d69f0bff: ERETAA
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_ERETAA_64E_branch_reg, uint32_t, uOpcode)
{
    uint32_t const M          = (uOpcode >> 10) & 0x00000001;
    uint32_t const A          = (uOpcode >> 11) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: ERETAA_64E_branch_reg M=%u A=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, M, A));
#ifdef IEM_INSTR_IMPL_A64__ERETAA_64E_branch_reg
        IEM_INSTR_IMPL_A64__ERETAA_64E_branch_reg(M, A);
#else
        RT_NOREF(M, A, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d69f0fff: ERETAB
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_ERETAB_64E_branch_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd69f0fff))
    {
        uint32_t const M          = (uOpcode >> 10) & 0x00000001;
        uint32_t const A          = (uOpcode >> 11) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: ERETAB_64E_branch_reg M=%u A=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, M, A));
#ifdef IEM_INSTR_IMPL_A64__ERETAB_64E_branch_reg
            IEM_INSTR_IMPL_A64__ERETAB_64E_branch_reg(M, A);
#else
            RT_NOREF(M, A, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d69f03e0: ERET
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_ERET_64E_branch_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd69f03e0))
    {
        uint32_t const M          = (uOpcode >> 10) & 0x00000001;
        uint32_t const A          = (uOpcode >> 11) & 0x00000001;
        LogFlow(("%018x/%010x: ERET_64E_branch_reg M=%u A=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, M, A));
#ifdef IEM_INSTR_IMPL_A64__ERET_64E_branch_reg
        IEM_INSTR_IMPL_A64__ERET_64E_branch_reg(M, A);
#else
        RT_NOREF(M, A, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503221f: ESB
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_ESB_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503221f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRas /*FEAT_RAS*/)
        {
            LogFlow(("%018x/%010x: ESB_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__ESB_HI_hints
            IEM_INSTR_IMPL_A64__ESB_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/13800000: EXTR  <Wd>, <Wn>, <Wm>, #<lsb>
   Instruction Set: A64  Groups: extract, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_EXTR_32_extract, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x13800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (0x0 /*op21@29*/ != 3)
        {
            LogFlow(("%018x/%010x: EXTR_32_extract Rd=%#x Rn=%#x imms=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, Rm));
#ifdef IEM_INSTR_IMPL_A64__EXTR_32_extract
            IEM_INSTR_IMPL_A64__EXTR_32_extract(Rd, Rn, imms, Rm);
#else
            RT_NOREF(Rd, Rn, imms, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00000/93c00000: EXTR  <Xd>, <Xn>, <Xm>, #<lsb>
   Instruction Set: A64  Groups: extract, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_EXTR_64_extract, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (0x0 /*op21@29*/ != 3)
    {
        LogFlow(("%018x/%010x: EXTR_64_extract Rd=%#x Rn=%#x imms=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, Rm));
#ifdef IEM_INSTR_IMPL_A64__EXTR_64_extract
        IEM_INSTR_IMPL_A64__EXTR_64_extract(Rd, Rn, imms, Rm);
#else
        RT_NOREF(Rd, Rn, imms, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe08400/2e000000: EXT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>
   Instruction Set: A64  Groups: asimdext, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_EXT_asimdext_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 11) & 0x0000000f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: EXT_asimdext_only Rd=%#x Rn=%#x imm4=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm4, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__EXT_asimdext_only
        IEM_INSTR_IMPL_A64__EXT_asimdext_only(Rd, Rn, imm4, Rm, Q);
#else
        RT_NOREF(Rd, Rn, imm4, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2e217800: F1CVTL2  <Vd>.8H, <Vn>.<Ta>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_F1CVTL_asimdmisc_V, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: F1CVTL_asimdmisc_V Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__F1CVTL_asimdmisc_V
        IEM_INSTR_IMPL_A64__F1CVTL_asimdmisc_V(Rd, Rn, Q);
#else
        RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2e617800: F2CVTL2  <Vd>.8H, <Vn>.<Ta>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_F2CVTL_asimdmisc_V, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2e617800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
        {
            LogFlow(("%018x/%010x: F2CVTL_asimdmisc_V Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__F2CVTL_asimdmisc_V
            IEM_INSTR_IMPL_A64__F2CVTL_asimdmisc_V(Rd, Rn, Q);
#else
            RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/2ea0d400: FABD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FABD_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x2ea0d400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FABD_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FABD_asimdsame_only
            IEM_INSTR_IMPL_A64__FABD_asimdsame_only(Rd, Rn, Rm, sz, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2ec01400: FABD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FABD_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2ec01400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FABD_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FABD_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FABD_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/7ea0d400: FABD  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FABD_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x7ea0d400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FABD_asisdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz));
#ifdef IEM_INSTR_IMPL_A64__FABD_asisdsame_only
            IEM_INSTR_IMPL_A64__FABD_asisdsame_only(Rd, Rn, Rm, sz);
#else
            RT_NOREF(Rd, Rn, Rm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ec01400: FABD  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: asisdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FABD_asisdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ec01400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FABD_asisdsamefp16_only Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FABD_asisdsamefp16_only
            IEM_INSTR_IMPL_A64__FABD_asisdsamefp16_only(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e60c000: FABS  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FABS_D_floatdp1, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FABS_D_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FABS_D_floatdp1
        IEM_INSTR_IMPL_A64__FABS_D_floatdp1(Rd, Rn, opc);
#else
        RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee0c000: FABS  <Hd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FABS_H_floatdp1, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FABS_H_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FABS_H_floatdp1
        IEM_INSTR_IMPL_A64__FABS_H_floatdp1(Rd, Rn, opc);
#else
        RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e20c000: FABS  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FABS_S_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e20c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FABS_S_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FABS_S_floatdp1
            IEM_INSTR_IMPL_A64__FABS_S_floatdp1(Rd, Rn, opc);
#else
            RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0ea0f800: FABS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FABS_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FABS_asimdmisc_R Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FABS_asimdmisc_R
        IEM_INSTR_IMPL_A64__FABS_asimdmisc_R(Rd, Rn, sz, Q);
#else
        RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0ef8f800: FABS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FABS_asimdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FABS_asimdmiscfp16_R Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__FABS_asimdmiscfp16_R
        IEM_INSTR_IMPL_A64__FABS_asimdmiscfp16_R(Rd, Rn, Q);
#else
        RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/2e20ec00: FACGE  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FACGE_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x2e20ec00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FACGE_asimdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x sz=%u E=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, sz, E, Q));
#ifdef IEM_INSTR_IMPL_A64__FACGE_asimdsame_only
            IEM_INSTR_IMPL_A64__FACGE_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q);
#else
            RT_NOREF(Rd, Rn, ac, Rm, sz, E, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2e402c00: FACGE  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FACGE_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2e402c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FACGE_asimdsamefp16_only Rd=%#x Rn=%#x ac=%u Rm=%#x E=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, E, Q));
#ifdef IEM_INSTR_IMPL_A64__FACGE_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FACGE_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q);
#else
            RT_NOREF(Rd, Rn, ac, Rm, E, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/7e20ec00: FACGE  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FACGE_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x7e20ec00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FACGE_asisdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x sz=%u E=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, sz, E));
#ifdef IEM_INSTR_IMPL_A64__FACGE_asisdsame_only
            IEM_INSTR_IMPL_A64__FACGE_asisdsame_only(Rd, Rn, ac, Rm, sz, E);
#else
            RT_NOREF(Rd, Rn, ac, Rm, sz, E, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7e402c00: FACGE  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: asisdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FACGE_asisdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7e402c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FACGE_asisdsamefp16_only Rd=%#x Rn=%#x ac=%u Rm=%#x E=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, E));
#ifdef IEM_INSTR_IMPL_A64__FACGE_asisdsamefp16_only
            IEM_INSTR_IMPL_A64__FACGE_asisdsamefp16_only(Rd, Rn, ac, Rm, E);
#else
            RT_NOREF(Rd, Rn, ac, Rm, E, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/2ea0ec00: FACGT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FACGT_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x2ea0ec00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FACGT_asimdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x sz=%u E=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, sz, E, Q));
#ifdef IEM_INSTR_IMPL_A64__FACGT_asimdsame_only
            IEM_INSTR_IMPL_A64__FACGT_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q);
#else
            RT_NOREF(Rd, Rn, ac, Rm, sz, E, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2ec02c00: FACGT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FACGT_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2ec02c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FACGT_asimdsamefp16_only Rd=%#x Rn=%#x ac=%u Rm=%#x E=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, E, Q));
#ifdef IEM_INSTR_IMPL_A64__FACGT_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FACGT_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q);
#else
            RT_NOREF(Rd, Rn, ac, Rm, E, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/7ea0ec00: FACGT  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FACGT_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x7ea0ec00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FACGT_asisdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x sz=%u E=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, sz, E));
#ifdef IEM_INSTR_IMPL_A64__FACGT_asisdsame_only
            IEM_INSTR_IMPL_A64__FACGT_asisdsame_only(Rd, Rn, ac, Rm, sz, E);
#else
            RT_NOREF(Rd, Rn, ac, Rm, sz, E, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ec02c00: FACGT  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: asisdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FACGT_asisdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ec02c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FACGT_asisdsamefp16_only Rd=%#x Rn=%#x ac=%u Rm=%#x E=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, E));
#ifdef IEM_INSTR_IMPL_A64__FACGT_asisdsamefp16_only
            IEM_INSTR_IMPL_A64__FACGT_asisdsamefp16_only(Rd, Rn, ac, Rm, E);
#else
            RT_NOREF(Rd, Rn, ac, Rm, E, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/2e20d400: FADDP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FADDP_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x2e20d400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FADDP_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FADDP_asimdsame_only
            IEM_INSTR_IMPL_A64__FADDP_asimdsame_only(Rd, Rn, Rm, sz, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2e401400: FADDP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FADDP_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2e401400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FADDP_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FADDP_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FADDP_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5e30d800: FADDP  H<d>, <Vn>.2H
   Instruction Set: A64  Groups: asisdpair, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FADDP_asisdpair_only_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FADDP_asisdpair_only_H Rd=%#x Rn=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz));
#ifdef IEM_INSTR_IMPL_A64__FADDP_asisdpair_only_H
        IEM_INSTR_IMPL_A64__FADDP_asisdpair_only_H(Rd, Rn, sz);
#else
        RT_NOREF(Rd, Rn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7e30d800: FADDP  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asisdpair, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FADDP_asisdpair_only_SD, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FADDP_asisdpair_only_SD Rd=%#x Rn=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz));
#ifdef IEM_INSTR_IMPL_A64__FADDP_asisdpair_only_SD
        IEM_INSTR_IMPL_A64__FADDP_asisdpair_only_SD(Rd, Rn, sz);
#else
        RT_NOREF(Rd, Rn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e602800: FADD  <Dd>, <Dn>, <Dm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FADD_D_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e602800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FADD_D_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FADD_D_floatdp2
            IEM_INSTR_IMPL_A64__FADD_D_floatdp2(Rd, Rn, op, Rm);
#else
            RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ee02800: FADD  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FADD_H_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ee02800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FADD_H_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FADD_H_floatdp2
            IEM_INSTR_IMPL_A64__FADD_H_floatdp2(Rd, Rn, op, Rm);
#else
            RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e202800: FADD  <Sd>, <Sn>, <Sm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FADD_S_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FADD_S_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FADD_S_floatdp2
        IEM_INSTR_IMPL_A64__FADD_S_floatdp2(Rd, Rn, op, Rm);
#else
        RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/0e20d400: FADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FADD_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x0e20d400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FADD_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FADD_asimdsame_only
            IEM_INSTR_IMPL_A64__FADD_asimdsame_only(Rd, Rn, Rm, sz, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e401400: FADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FADD_asimdsamefp16_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FADD_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FADD_asimdsamefp16_only
        IEM_INSTR_IMPL_A64__FADD_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e20dc00: FAMAX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FAMAX_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FAMINMAX*/ && (size & 2) == 2)
    {
        LogFlow(("%018x/%010x: FAMAX_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__FAMAX_asimdsame_only
        IEM_INSTR_IMPL_A64__FAMAX_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0ec01c00: FAMAX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FAMAX_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0ec01c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FAMINMAX*/)
        {
            LogFlow(("%018x/%010x: FAMAX_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FAMAX_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FAMAX_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e20dc00: FAMIN  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FAMIN_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FAMINMAX*/ && (size & 2) == 2)
    {
        LogFlow(("%018x/%010x: FAMIN_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__FAMIN_asimdsame_only
        IEM_INSTR_IMPL_A64__FAMIN_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2ec01c00: FAMIN  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FAMIN_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2ec01c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FAMINMAX*/)
        {
            LogFlow(("%018x/%010x: FAMIN_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FAMIN_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FAMIN_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20ec00/2e00e400: FCADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate>
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCADD_asimdsame2_C, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const rot        = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFcma /*FEAT_FCMA*/)
    {
        LogFlow(("%018x/%010x: FCADD_asimdsame2_C Rd=%#x Rn=%#x rot=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rot, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__FCADD_asimdsame2_C
        IEM_INSTR_IMPL_A64__FCADD_asimdsame2_C(Rd, Rn, rot, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, rot, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c10/1e600410: FCCMPE  <Dn>, <Dm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: floatccmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCCMPE_D_floatccmp, uint32_t, uOpcode)
{
    uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FCCMPE_D_floatccmp nzcv=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCCMPE_D_floatccmp
        IEM_INSTR_IMPL_A64__FCCMPE_D_floatccmp(nzcv, Rn, cond, Rm);
#else
        RT_NOREF(nzcv, Rn, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c10/1ee00410: FCCMPE  <Hn>, <Hm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: floatccmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCCMPE_H_floatccmp, uint32_t, uOpcode)
{
    uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCCMPE_H_floatccmp nzcv=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCCMPE_H_floatccmp
        IEM_INSTR_IMPL_A64__FCCMPE_H_floatccmp(nzcv, Rn, cond, Rm);
#else
        RT_NOREF(nzcv, Rn, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c10/1e200410: FCCMPE  <Sn>, <Sm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: floatccmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCCMPE_S_floatccmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0x1e200410))
    {
        uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCCMPE_S_floatccmp nzcv=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCCMPE_S_floatccmp
            IEM_INSTR_IMPL_A64__FCCMPE_S_floatccmp(nzcv, Rn, cond, Rm);
#else
            RT_NOREF(nzcv, Rn, cond, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c10/1e600400: FCCMP  <Dn>, <Dm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: floatccmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCCMP_D_floatccmp, uint32_t, uOpcode)
{
    uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FCCMP_D_floatccmp nzcv=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCCMP_D_floatccmp
        IEM_INSTR_IMPL_A64__FCCMP_D_floatccmp(nzcv, Rn, cond, Rm);
#else
        RT_NOREF(nzcv, Rn, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c10/1ee00400: FCCMP  <Hn>, <Hm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: floatccmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCCMP_H_floatccmp, uint32_t, uOpcode)
{
    uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCCMP_H_floatccmp nzcv=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCCMP_H_floatccmp
        IEM_INSTR_IMPL_A64__FCCMP_H_floatccmp(nzcv, Rn, cond, Rm);
#else
        RT_NOREF(nzcv, Rn, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c10/1e200400: FCCMP  <Sn>, <Sm>, #<nzcv>, <cond>
   Instruction Set: A64  Groups: floatccmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCCMP_S_floatccmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0x1e200400))
    {
        uint32_t const nzcv       = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCCMP_S_floatccmp nzcv=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, nzcv, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCCMP_S_floatccmp
            IEM_INSTR_IMPL_A64__FCCMP_S_floatccmp(nzcv, Rn, cond, Rm);
#else
            RT_NOREF(nzcv, Rn, cond, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0ea0d800: FCMEQ  <Vd>.<T>, <Vn>.<T>, #0.0
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMEQ_asimdmisc_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCMEQ_asimdmisc_FZ Rd=%#x Rn=%#x op=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMEQ_asimdmisc_FZ
        IEM_INSTR_IMPL_A64__FCMEQ_asimdmisc_FZ(Rd, Rn, op, sz, Q);
#else
        RT_NOREF(Rd, Rn, op, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0ef8d800: FCMEQ  <Vd>.<T>, <Vn>.<T>, #0.0
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMEQ_asimdmiscfp16_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCMEQ_asimdmiscfp16_FZ Rd=%#x Rn=%#x op=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMEQ_asimdmiscfp16_FZ
        IEM_INSTR_IMPL_A64__FCMEQ_asimdmiscfp16_FZ(Rd, Rn, op, Q);
#else
        RT_NOREF(Rd, Rn, op, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/0e20e400: FCMEQ  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMEQ_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const E          = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCMEQ_asimdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x sz=%u E=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, sz, E, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMEQ_asimdsame_only
        IEM_INSTR_IMPL_A64__FCMEQ_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q);
#else
        RT_NOREF(Rd, Rn, ac, Rm, sz, E, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e402400: FCMEQ  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMEQ_asimdsamefp16_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const E          = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCMEQ_asimdsamefp16_only Rd=%#x Rn=%#x ac=%u Rm=%#x E=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, E, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMEQ_asimdsamefp16_only
        IEM_INSTR_IMPL_A64__FCMEQ_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q);
#else
        RT_NOREF(Rd, Rn, ac, Rm, E, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/5ea0d800: FCMEQ  <V><d>, <V><n>, #0.0
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMEQ_asisdmisc_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCMEQ_asisdmisc_FZ Rd=%#x Rn=%#x op=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, sz));
#ifdef IEM_INSTR_IMPL_A64__FCMEQ_asisdmisc_FZ
        IEM_INSTR_IMPL_A64__FCMEQ_asisdmisc_FZ(Rd, Rn, op, sz);
#else
        RT_NOREF(Rd, Rn, op, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ef8d800: FCMEQ  <Hd>, <Hn>, #0.0
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMEQ_asisdmiscfp16_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCMEQ_asisdmiscfp16_FZ Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__FCMEQ_asisdmiscfp16_FZ
        IEM_INSTR_IMPL_A64__FCMEQ_asisdmiscfp16_FZ(Rd, Rn, op);
#else
        RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/5e20e400: FCMEQ  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMEQ_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x5e20e400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCMEQ_asisdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x sz=%u E=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, sz, E));
#ifdef IEM_INSTR_IMPL_A64__FCMEQ_asisdsame_only
            IEM_INSTR_IMPL_A64__FCMEQ_asisdsame_only(Rd, Rn, ac, Rm, sz, E);
#else
            RT_NOREF(Rd, Rn, ac, Rm, sz, E, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5e402400: FCMEQ  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: asisdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMEQ_asisdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5e402400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMEQ_asisdsamefp16_only Rd=%#x Rn=%#x ac=%u Rm=%#x E=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, E));
#ifdef IEM_INSTR_IMPL_A64__FCMEQ_asisdsamefp16_only
            IEM_INSTR_IMPL_A64__FCMEQ_asisdsamefp16_only(Rd, Rn, ac, Rm, E);
#else
            RT_NOREF(Rd, Rn, ac, Rm, E, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2ea0c800: FCMGE  <Vd>.<T>, <Vn>.<T>, #0.0
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGE_asimdmisc_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCMGE_asimdmisc_FZ Rd=%#x Rn=%#x op=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMGE_asimdmisc_FZ
        IEM_INSTR_IMPL_A64__FCMGE_asimdmisc_FZ(Rd, Rn, op, sz, Q);
#else
        RT_NOREF(Rd, Rn, op, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2ef8c800: FCMGE  <Vd>.<T>, <Vn>.<T>, #0.0
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGE_asimdmiscfp16_FZ, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2ef8c800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMGE_asimdmiscfp16_FZ Rd=%#x Rn=%#x op=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMGE_asimdmiscfp16_FZ
            IEM_INSTR_IMPL_A64__FCMGE_asimdmiscfp16_FZ(Rd, Rn, op, Q);
#else
            RT_NOREF(Rd, Rn, op, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/2e20e400: FCMGE  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGE_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x2e20e400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCMGE_asimdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x sz=%u E=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, sz, E, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMGE_asimdsame_only
            IEM_INSTR_IMPL_A64__FCMGE_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q);
#else
            RT_NOREF(Rd, Rn, ac, Rm, sz, E, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2e402400: FCMGE  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGE_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2e402400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMGE_asimdsamefp16_only Rd=%#x Rn=%#x ac=%u Rm=%#x E=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, E, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMGE_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FCMGE_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q);
#else
            RT_NOREF(Rd, Rn, ac, Rm, E, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7ea0c800: FCMGE  <V><d>, <V><n>, #0.0
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGE_asisdmisc_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCMGE_asisdmisc_FZ Rd=%#x Rn=%#x op=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, sz));
#ifdef IEM_INSTR_IMPL_A64__FCMGE_asisdmisc_FZ
        IEM_INSTR_IMPL_A64__FCMGE_asisdmisc_FZ(Rd, Rn, op, sz);
#else
        RT_NOREF(Rd, Rn, op, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7ef8c800: FCMGE  <Hd>, <Hn>, #0.0
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGE_asisdmiscfp16_FZ, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7ef8c800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMGE_asisdmiscfp16_FZ Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__FCMGE_asisdmiscfp16_FZ
            IEM_INSTR_IMPL_A64__FCMGE_asisdmiscfp16_FZ(Rd, Rn, op);
#else
            RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/7e20e400: FCMGE  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGE_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const E          = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCMGE_asisdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x sz=%u E=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, sz, E));
#ifdef IEM_INSTR_IMPL_A64__FCMGE_asisdsame_only
        IEM_INSTR_IMPL_A64__FCMGE_asisdsame_only(Rd, Rn, ac, Rm, sz, E);
#else
        RT_NOREF(Rd, Rn, ac, Rm, sz, E, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7e402400: FCMGE  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: asisdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGE_asisdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7e402400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMGE_asisdsamefp16_only Rd=%#x Rn=%#x ac=%u Rm=%#x E=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, E));
#ifdef IEM_INSTR_IMPL_A64__FCMGE_asisdsamefp16_only
            IEM_INSTR_IMPL_A64__FCMGE_asisdsamefp16_only(Rd, Rn, ac, Rm, E);
#else
            RT_NOREF(Rd, Rn, ac, Rm, E, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0ea0c800: FCMGT  <Vd>.<T>, <Vn>.<T>, #0.0
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGT_asimdmisc_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCMGT_asimdmisc_FZ Rd=%#x Rn=%#x op=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMGT_asimdmisc_FZ
        IEM_INSTR_IMPL_A64__FCMGT_asimdmisc_FZ(Rd, Rn, op, sz, Q);
#else
        RT_NOREF(Rd, Rn, op, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0ef8c800: FCMGT  <Vd>.<T>, <Vn>.<T>, #0.0
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGT_asimdmiscfp16_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCMGT_asimdmiscfp16_FZ Rd=%#x Rn=%#x op=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMGT_asimdmiscfp16_FZ
        IEM_INSTR_IMPL_A64__FCMGT_asimdmiscfp16_FZ(Rd, Rn, op, Q);
#else
        RT_NOREF(Rd, Rn, op, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/2ea0e400: FCMGT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGT_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x2ea0e400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCMGT_asimdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x sz=%u E=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, sz, E, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMGT_asimdsame_only
            IEM_INSTR_IMPL_A64__FCMGT_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q);
#else
            RT_NOREF(Rd, Rn, ac, Rm, sz, E, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2ec02400: FCMGT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGT_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2ec02400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMGT_asimdsamefp16_only Rd=%#x Rn=%#x ac=%u Rm=%#x E=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, E, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMGT_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FCMGT_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q);
#else
            RT_NOREF(Rd, Rn, ac, Rm, E, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/5ea0c800: FCMGT  <V><d>, <V><n>, #0.0
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGT_asisdmisc_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCMGT_asisdmisc_FZ Rd=%#x Rn=%#x op=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, sz));
#ifdef IEM_INSTR_IMPL_A64__FCMGT_asisdmisc_FZ
        IEM_INSTR_IMPL_A64__FCMGT_asisdmisc_FZ(Rd, Rn, op, sz);
#else
        RT_NOREF(Rd, Rn, op, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ef8c800: FCMGT  <Hd>, <Hn>, #0.0
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGT_asisdmiscfp16_FZ, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ef8c800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMGT_asisdmiscfp16_FZ Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__FCMGT_asisdmiscfp16_FZ
            IEM_INSTR_IMPL_A64__FCMGT_asisdmiscfp16_FZ(Rd, Rn, op);
#else
            RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/7ea0e400: FCMGT  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGT_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const E          = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCMGT_asisdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x sz=%u E=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, sz, E));
#ifdef IEM_INSTR_IMPL_A64__FCMGT_asisdsame_only
        IEM_INSTR_IMPL_A64__FCMGT_asisdsame_only(Rd, Rn, ac, Rm, sz, E);
#else
        RT_NOREF(Rd, Rn, ac, Rm, sz, E, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ec02400: FCMGT  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: asisdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMGT_asisdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ec02400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const E          = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMGT_asisdsamefp16_only Rd=%#x Rn=%#x ac=%u Rm=%#x E=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, E));
#ifdef IEM_INSTR_IMPL_A64__FCMGT_asisdsamefp16_only
            IEM_INSTR_IMPL_A64__FCMGT_asisdsamefp16_only(Rd, Rn, ac, Rm, E);
#else
            RT_NOREF(Rd, Rn, ac, Rm, E, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf009400/2f001000: FCMLA  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>], #<rotate>
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMLA_advsimd_elt, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf009400)) == UINT32_C(0x2f001000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const rot        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFcma /*FEAT_FCMA*/)
        {
            LogFlow(("%018x/%010x: FCMLA_advsimd_elt Rd=%#x Rn=%#x H=%u rot=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, rot, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMLA_advsimd_elt
            IEM_INSTR_IMPL_A64__FCMLA_advsimd_elt(Rd, Rn, H, rot, Rm, M, L, size, Q);
#else
            RT_NOREF(Rd, Rn, H, rot, Rm, M, L, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20e400/2e00c400: FCMLA  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate>
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMLA_asimdsame2_C, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const rot        = (uOpcode >> 11) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFcma /*FEAT_FCMA*/)
    {
        LogFlow(("%018x/%010x: FCMLA_asimdsame2_C Rd=%#x Rn=%#x rot=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rot, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMLA_asimdsame2_C
        IEM_INSTR_IMPL_A64__FCMLA_asimdsame2_C(Rd, Rn, rot, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, rot, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2ea0d800: FCMLE  <Vd>.<T>, <Vn>.<T>, #0.0
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMLE_asimdmisc_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCMLE_asimdmisc_FZ Rd=%#x Rn=%#x op=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMLE_asimdmisc_FZ
        IEM_INSTR_IMPL_A64__FCMLE_asimdmisc_FZ(Rd, Rn, op, sz, Q);
#else
        RT_NOREF(Rd, Rn, op, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2ef8d800: FCMLE  <Vd>.<T>, <Vn>.<T>, #0.0
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMLE_asimdmiscfp16_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCMLE_asimdmiscfp16_FZ Rd=%#x Rn=%#x op=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMLE_asimdmiscfp16_FZ
        IEM_INSTR_IMPL_A64__FCMLE_asimdmiscfp16_FZ(Rd, Rn, op, Q);
#else
        RT_NOREF(Rd, Rn, op, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7ea0d800: FCMLE  <V><d>, <V><n>, #0.0
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMLE_asisdmisc_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCMLE_asisdmisc_FZ Rd=%#x Rn=%#x op=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, sz));
#ifdef IEM_INSTR_IMPL_A64__FCMLE_asisdmisc_FZ
        IEM_INSTR_IMPL_A64__FCMLE_asisdmisc_FZ(Rd, Rn, op, sz);
#else
        RT_NOREF(Rd, Rn, op, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7ef8d800: FCMLE  <Hd>, <Hn>, #0.0
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMLE_asisdmiscfp16_FZ, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCMLE_asisdmiscfp16_FZ Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__FCMLE_asisdmiscfp16_FZ
        IEM_INSTR_IMPL_A64__FCMLE_asisdmiscfp16_FZ(Rd, Rn, op);
#else
        RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0ea0e800: FCMLT  <Vd>.<T>, <Vn>.<T>, #0.0
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMLT_asimdmisc_FZ, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0ea0e800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCMLT_asimdmisc_FZ Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMLT_asimdmisc_FZ
            IEM_INSTR_IMPL_A64__FCMLT_asimdmisc_FZ(Rd, Rn, sz, Q);
#else
            RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0ef8e800: FCMLT  <Vd>.<T>, <Vn>.<T>, #0.0
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMLT_asimdmiscfp16_FZ, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0ef8e800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMLT_asimdmiscfp16_FZ Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__FCMLT_asimdmiscfp16_FZ
            IEM_INSTR_IMPL_A64__FCMLT_asimdmiscfp16_FZ(Rd, Rn, Q);
#else
            RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/5ea0e800: FCMLT  <V><d>, <V><n>, #0.0
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMLT_asisdmisc_FZ, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x5ea0e800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCMLT_asisdmisc_FZ Rd=%#x Rn=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz));
#ifdef IEM_INSTR_IMPL_A64__FCMLT_asisdmisc_FZ
            IEM_INSTR_IMPL_A64__FCMLT_asisdmisc_FZ(Rd, Rn, sz);
#else
            RT_NOREF(Rd, Rn, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ef8e800: FCMLT  <Hd>, <Hn>, #0.0
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMLT_asisdmiscfp16_FZ, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ef8e800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMLT_asisdmiscfp16_FZ Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCMLT_asisdmiscfp16_FZ
            IEM_INSTR_IMPL_A64__FCMLT_asisdmiscfp16_FZ(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/1e602018: FCMPE  <Dn>, #0.0
   Instruction Set: A64  Groups: floatcmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMPE_DZ_floatcmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0x1e602018))
    {
        uint32_t const opc        = (uOpcode >>  3) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCMPE_DZ_floatcmp opc=%u Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCMPE_DZ_floatcmp
            IEM_INSTR_IMPL_A64__FCMPE_DZ_floatcmp(opc, Rn);
#else
            RT_NOREF(opc, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/1e602010: FCMPE  <Dn>, <Dm>
   Instruction Set: A64  Groups: floatcmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMPE_D_floatcmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x1e602010))
    {
        uint32_t const opc        = (uOpcode >>  3) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCMPE_D_floatcmp opc=%u Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCMPE_D_floatcmp
            IEM_INSTR_IMPL_A64__FCMPE_D_floatcmp(opc, Rn, Rm);
#else
            RT_NOREF(opc, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/1ee02018: FCMPE  <Hn>, #0.0
   Instruction Set: A64  Groups: floatcmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMPE_HZ_floatcmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0x1ee02018))
    {
        uint32_t const opc        = (uOpcode >>  3) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMPE_HZ_floatcmp opc=%u Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCMPE_HZ_floatcmp
            IEM_INSTR_IMPL_A64__FCMPE_HZ_floatcmp(opc, Rn);
#else
            RT_NOREF(opc, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/1ee02010: FCMPE  <Hn>, <Hm>
   Instruction Set: A64  Groups: floatcmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMPE_H_floatcmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x1ee02010))
    {
        uint32_t const opc        = (uOpcode >>  3) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMPE_H_floatcmp opc=%u Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCMPE_H_floatcmp
            IEM_INSTR_IMPL_A64__FCMPE_H_floatcmp(opc, Rn, Rm);
#else
            RT_NOREF(opc, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/1e202018: FCMPE  <Sn>, #0.0
   Instruction Set: A64  Groups: floatcmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMPE_SZ_floatcmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0x1e202018))
    {
        uint32_t const opc        = (uOpcode >>  3) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCMPE_SZ_floatcmp opc=%u Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCMPE_SZ_floatcmp
            IEM_INSTR_IMPL_A64__FCMPE_SZ_floatcmp(opc, Rn);
#else
            RT_NOREF(opc, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/1e202010: FCMPE  <Sn>, <Sm>
   Instruction Set: A64  Groups: floatcmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMPE_S_floatcmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x1e202010))
    {
        uint32_t const opc        = (uOpcode >>  3) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCMPE_S_floatcmp opc=%u Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCMPE_S_floatcmp
            IEM_INSTR_IMPL_A64__FCMPE_S_floatcmp(opc, Rn, Rm);
#else
            RT_NOREF(opc, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/1e602008: FCMP  <Dn>, #0.0
   Instruction Set: A64  Groups: floatcmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMP_DZ_floatcmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0x1e602008))
    {
        uint32_t const opc        = (uOpcode >>  3) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCMP_DZ_floatcmp opc=%u Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCMP_DZ_floatcmp
            IEM_INSTR_IMPL_A64__FCMP_DZ_floatcmp(opc, Rn);
#else
            RT_NOREF(opc, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/1e602000: FCMP  <Dn>, <Dm>
   Instruction Set: A64  Groups: floatcmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMP_D_floatcmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x1e602000))
    {
        uint32_t const opc        = (uOpcode >>  3) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCMP_D_floatcmp opc=%u Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCMP_D_floatcmp
            IEM_INSTR_IMPL_A64__FCMP_D_floatcmp(opc, Rn, Rm);
#else
            RT_NOREF(opc, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/1ee02008: FCMP  <Hn>, #0.0
   Instruction Set: A64  Groups: floatcmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMP_HZ_floatcmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0x1ee02008))
    {
        uint32_t const opc        = (uOpcode >>  3) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMP_HZ_floatcmp opc=%u Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCMP_HZ_floatcmp
            IEM_INSTR_IMPL_A64__FCMP_HZ_floatcmp(opc, Rn);
#else
            RT_NOREF(opc, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/1ee02000: FCMP  <Hn>, <Hm>
   Instruction Set: A64  Groups: floatcmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMP_H_floatcmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x1ee02000))
    {
        uint32_t const opc        = (uOpcode >>  3) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCMP_H_floatcmp opc=%u Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCMP_H_floatcmp
            IEM_INSTR_IMPL_A64__FCMP_H_floatcmp(opc, Rn, Rm);
#else
            RT_NOREF(opc, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/1e202008: FCMP  <Sn>, #0.0
   Instruction Set: A64  Groups: floatcmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMP_SZ_floatcmp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0x1e202008))
    {
        uint32_t const opc        = (uOpcode >>  3) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCMP_SZ_floatcmp opc=%u Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCMP_SZ_floatcmp
            IEM_INSTR_IMPL_A64__FCMP_SZ_floatcmp(opc, Rn);
#else
            RT_NOREF(opc, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/1e202000: FCMP  <Sn>, <Sm>
   Instruction Set: A64  Groups: floatcmp, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCMP_S_floatcmp, uint32_t, uOpcode)
{
    uint32_t const opc        = (uOpcode >>  3) & 0x00000003;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FCMP_S_floatcmp opc=%u Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCMP_S_floatcmp
        IEM_INSTR_IMPL_A64__FCMP_S_floatcmp(opc, Rn, Rm);
#else
        RT_NOREF(opc, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/1e600c00: FCSEL  <Dd>, <Dn>, <Dm>, <cond>
   Instruction Set: A64  Groups: floatsel, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCSEL_D_floatsel, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FCSEL_D_floatsel Rd=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCSEL_D_floatsel
        IEM_INSTR_IMPL_A64__FCSEL_D_floatsel(Rd, Rn, cond, Rm);
#else
        RT_NOREF(Rd, Rn, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/1ee00c00: FCSEL  <Hd>, <Hn>, <Hm>, <cond>
   Instruction Set: A64  Groups: floatsel, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCSEL_H_floatsel, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCSEL_H_floatsel Rd=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCSEL_H_floatsel
        IEM_INSTR_IMPL_A64__FCSEL_H_floatsel(Rd, Rn, cond, Rm);
#else
        RT_NOREF(Rd, Rn, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/1e200c00: FCSEL  <Sd>, <Sn>, <Sm>, <cond>
   Instruction Set: A64  Groups: floatsel, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCSEL_S_floatsel, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const cond       = (uOpcode >> 12) & 0x0000000f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FCSEL_S_floatsel Rd=%#x Rn=%#x cond=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, cond, Rm));
#ifdef IEM_INSTR_IMPL_A64__FCSEL_S_floatsel
        IEM_INSTR_IMPL_A64__FCSEL_S_floatsel(Rd, Rn, cond, Rm);
#else
        RT_NOREF(Rd, Rn, cond, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e640000: FCVTAS  <Wd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_32D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e640000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTAS_32D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_32D_float2int
            IEM_INSTR_IMPL_A64__FCVTAS_32D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee40000: FCVTAS  <Wd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_32H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee40000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTAS_32H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_32H_float2int
            IEM_INSTR_IMPL_A64__FCVTAS_32H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e240000: FCVTAS  <Wd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_32S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e240000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTAS_32S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_32S_float2int
            IEM_INSTR_IMPL_A64__FCVTAS_32S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e640000: FCVTAS  <Xd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_64D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e640000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTAS_64D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_64D_float2int
            IEM_INSTR_IMPL_A64__FCVTAS_64D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ee40000: FCVTAS  <Xd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_64H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ee40000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTAS_64H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_64H_float2int
            IEM_INSTR_IMPL_A64__FCVTAS_64H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e240000: FCVTAS  <Xd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_64S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e240000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTAS_64S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_64S_float2int
            IEM_INSTR_IMPL_A64__FCVTAS_64S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0e21c800: FCVTAS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTAS_asimdmisc_R Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_asimdmisc_R
        IEM_INSTR_IMPL_A64__FCVTAS_asimdmisc_R(Rd, Rn, sz, Q);
#else
        RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0e79c800: FCVTAS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_asimdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCVTAS_asimdmiscfp16_R Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_asimdmiscfp16_R
        IEM_INSTR_IMPL_A64__FCVTAS_asimdmiscfp16_R(Rd, Rn, Q);
#else
        RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/5e21c800: FCVTAS  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTAS_asisdmisc_R Rd=%#x Rn=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_asisdmisc_R
        IEM_INSTR_IMPL_A64__FCVTAS_asisdmisc_R(Rd, Rn, sz);
#else
        RT_NOREF(Rd, Rn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5e79c800: FCVTAS  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_asisdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCVTAS_asisdmiscfp16_R Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_asisdmiscfp16_R
        IEM_INSTR_IMPL_A64__FCVTAS_asisdmiscfp16_R(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e7a0000: FCVTAS  <Sd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_sisd_32D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e7a0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTAS_sisd_32D Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_sisd_32D
            IEM_INSTR_IMPL_A64__FCVTAS_sisd_32D(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1efa0000: FCVTAS  <Sd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_sisd_32H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1efa0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTAS_sisd_32H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_sisd_32H
            IEM_INSTR_IMPL_A64__FCVTAS_sisd_32H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9efa0000: FCVTAS  <Dd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_sisd_64H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9efa0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTAS_sisd_64H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_sisd_64H
            IEM_INSTR_IMPL_A64__FCVTAS_sisd_64H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e3a0000: FCVTAS  <Dd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAS_sisd_64S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e3a0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTAS_sisd_64S Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAS_sisd_64S
            IEM_INSTR_IMPL_A64__FCVTAS_sisd_64S(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e650000: FCVTAU  <Wd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_32D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e650000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_32D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_32D_float2int
            IEM_INSTR_IMPL_A64__FCVTAU_32D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee50000: FCVTAU  <Wd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_32H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee50000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_32H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_32H_float2int
            IEM_INSTR_IMPL_A64__FCVTAU_32H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e250000: FCVTAU  <Wd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_32S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e250000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_32S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_32S_float2int
            IEM_INSTR_IMPL_A64__FCVTAU_32S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e650000: FCVTAU  <Xd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_64D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e650000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_64D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_64D_float2int
            IEM_INSTR_IMPL_A64__FCVTAU_64D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ee50000: FCVTAU  <Xd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_64H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ee50000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_64H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_64H_float2int
            IEM_INSTR_IMPL_A64__FCVTAU_64H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e250000: FCVTAU  <Xd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_64S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e250000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_64S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_64S_float2int
            IEM_INSTR_IMPL_A64__FCVTAU_64S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2e21c800: FCVTAU  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2e21c800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_asimdmisc_R Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_asimdmisc_R
            IEM_INSTR_IMPL_A64__FCVTAU_asimdmisc_R(Rd, Rn, sz, Q);
#else
            RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2e79c800: FCVTAU  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2e79c800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_asimdmiscfp16_R Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTAU_asimdmiscfp16_R(Rd, Rn, Q);
#else
            RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7e21c800: FCVTAU  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTAU_asisdmisc_R Rd=%#x Rn=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_asisdmisc_R
        IEM_INSTR_IMPL_A64__FCVTAU_asisdmisc_R(Rd, Rn, sz);
#else
        RT_NOREF(Rd, Rn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7e79c800: FCVTAU  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_asisdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7e79c800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_asisdmiscfp16_R Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_asisdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTAU_asisdmiscfp16_R(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e7b0000: FCVTAU  <Sd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_sisd_32D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e7b0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_sisd_32D Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_sisd_32D
            IEM_INSTR_IMPL_A64__FCVTAU_sisd_32D(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1efb0000: FCVTAU  <Sd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_sisd_32H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1efb0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_sisd_32H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_sisd_32H
            IEM_INSTR_IMPL_A64__FCVTAU_sisd_32H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9efb0000: FCVTAU  <Dd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_sisd_64H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9efb0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_sisd_64H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_sisd_64H
            IEM_INSTR_IMPL_A64__FCVTAU_sisd_64H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e3b0000: FCVTAU  <Dd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTAU_sisd_64S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e3b0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTAU_sisd_64S Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTAU_sisd_64S
            IEM_INSTR_IMPL_A64__FCVTAU_sisd_64S(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0e217800: FCVTL2  <Vd>.<Ta>, <Vn>.<Tb>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTL_asimdmisc_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTL_asimdmisc_L Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTL_asimdmisc_L
        IEM_INSTR_IMPL_A64__FCVTL_asimdmisc_L(Rd, Rn, sz, Q);
#else
        RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e700000: FCVTMS  <Wd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_32D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e700000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTMS_32D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_32D_float2int
            IEM_INSTR_IMPL_A64__FCVTMS_32D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ef00000: FCVTMS  <Wd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_32H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ef00000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTMS_32H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_32H_float2int
            IEM_INSTR_IMPL_A64__FCVTMS_32H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e300000: FCVTMS  <Wd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_32S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e300000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTMS_32S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_32S_float2int
            IEM_INSTR_IMPL_A64__FCVTMS_32S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e700000: FCVTMS  <Xd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_64D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e700000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTMS_64D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_64D_float2int
            IEM_INSTR_IMPL_A64__FCVTMS_64D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ef00000: FCVTMS  <Xd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_64H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ef00000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTMS_64H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_64H_float2int
            IEM_INSTR_IMPL_A64__FCVTMS_64H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e300000: FCVTMS  <Xd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_64S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e300000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTMS_64S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_64S_float2int
            IEM_INSTR_IMPL_A64__FCVTMS_64S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0e21b800: FCVTMS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTMS_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_asimdmisc_R
        IEM_INSTR_IMPL_A64__FCVTMS_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
        RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0e79b800: FCVTMS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0e79b800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTMS_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTMS_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/5e21b800: FCVTMS  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTMS_asisdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_asisdmisc_R
        IEM_INSTR_IMPL_A64__FCVTMS_asisdmisc_R(Rd, Rn, o1, sz, o2);
#else
        RT_NOREF(Rd, Rn, o1, sz, o2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5e79b800: FCVTMS  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_asisdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5e79b800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTMS_asisdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_asisdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTMS_asisdmiscfp16_R(Rd, Rn, o1, o2);
#else
            RT_NOREF(Rd, Rn, o1, o2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e740000: FCVTMS  <Sd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_sisd_32D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e740000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTMS_sisd_32D Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_sisd_32D
            IEM_INSTR_IMPL_A64__FCVTMS_sisd_32D(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ef40000: FCVTMS  <Sd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_sisd_32H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ef40000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTMS_sisd_32H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_sisd_32H
            IEM_INSTR_IMPL_A64__FCVTMS_sisd_32H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ef40000: FCVTMS  <Dd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_sisd_64H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ef40000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTMS_sisd_64H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_sisd_64H
            IEM_INSTR_IMPL_A64__FCVTMS_sisd_64H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e340000: FCVTMS  <Dd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMS_sisd_64S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e340000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTMS_sisd_64S Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMS_sisd_64S
            IEM_INSTR_IMPL_A64__FCVTMS_sisd_64S(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e710000: FCVTMU  <Wd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_32D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e710000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTMU_32D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_32D_float2int
            IEM_INSTR_IMPL_A64__FCVTMU_32D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ef10000: FCVTMU  <Wd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_32H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ef10000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTMU_32H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_32H_float2int
            IEM_INSTR_IMPL_A64__FCVTMU_32H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e310000: FCVTMU  <Wd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_32S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e310000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTMU_32S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_32S_float2int
            IEM_INSTR_IMPL_A64__FCVTMU_32S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e710000: FCVTMU  <Xd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_64D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e710000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTMU_64D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_64D_float2int
            IEM_INSTR_IMPL_A64__FCVTMU_64D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ef10000: FCVTMU  <Xd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_64H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ef10000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTMU_64H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_64H_float2int
            IEM_INSTR_IMPL_A64__FCVTMU_64H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e310000: FCVTMU  <Xd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_64S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e310000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTMU_64S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_64S_float2int
            IEM_INSTR_IMPL_A64__FCVTMU_64S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2e21b800: FCVTMU  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTMU_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_asimdmisc_R
        IEM_INSTR_IMPL_A64__FCVTMU_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
        RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2e79b800: FCVTMU  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2e79b800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTMU_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTMU_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7e21b800: FCVTMU  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTMU_asisdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_asisdmisc_R
        IEM_INSTR_IMPL_A64__FCVTMU_asisdmisc_R(Rd, Rn, o1, sz, o2);
#else
        RT_NOREF(Rd, Rn, o1, sz, o2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7e79b800: FCVTMU  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_asisdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7e79b800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTMU_asisdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_asisdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTMU_asisdmiscfp16_R(Rd, Rn, o1, o2);
#else
            RT_NOREF(Rd, Rn, o1, o2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e750000: FCVTMU  <Sd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_sisd_32D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e750000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTMU_sisd_32D Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_sisd_32D
            IEM_INSTR_IMPL_A64__FCVTMU_sisd_32D(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ef50000: FCVTMU  <Sd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_sisd_32H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ef50000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTMU_sisd_32H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_sisd_32H
            IEM_INSTR_IMPL_A64__FCVTMU_sisd_32H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ef50000: FCVTMU  <Dd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_sisd_64H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ef50000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTMU_sisd_64H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_sisd_64H
            IEM_INSTR_IMPL_A64__FCVTMU_sisd_64H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e350000: FCVTMU  <Dd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTMU_sisd_64S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e350000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTMU_sisd_64S Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTMU_sisd_64S
            IEM_INSTR_IMPL_A64__FCVTMU_sisd_64S(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e600000: FCVTNS  <Wd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_32D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e600000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTNS_32D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_32D_float2int
            IEM_INSTR_IMPL_A64__FCVTNS_32D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee00000: FCVTNS  <Wd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_32H_float2int, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCVTNS_32H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_32H_float2int
        IEM_INSTR_IMPL_A64__FCVTNS_32H_float2int(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e200000: FCVTNS  <Wd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_32S_float2int, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FCVTNS_32S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_32S_float2int
        IEM_INSTR_IMPL_A64__FCVTNS_32S_float2int(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e600000: FCVTNS  <Xd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_64D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e600000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTNS_64D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_64D_float2int
            IEM_INSTR_IMPL_A64__FCVTNS_64D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ee00000: FCVTNS  <Xd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_64H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ee00000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTNS_64H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_64H_float2int
            IEM_INSTR_IMPL_A64__FCVTNS_64H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e200000: FCVTNS  <Xd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_64S_float2int, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FCVTNS_64S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_64S_float2int
        IEM_INSTR_IMPL_A64__FCVTNS_64S_float2int(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0e21a800: FCVTNS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTNS_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_asimdmisc_R
        IEM_INSTR_IMPL_A64__FCVTNS_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
        RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0e79a800: FCVTNS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0e79a800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTNS_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTNS_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/5e21a800: FCVTNS  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTNS_asisdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_asisdmisc_R
        IEM_INSTR_IMPL_A64__FCVTNS_asisdmisc_R(Rd, Rn, o1, sz, o2);
#else
        RT_NOREF(Rd, Rn, o1, sz, o2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5e79a800: FCVTNS  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_asisdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5e79a800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTNS_asisdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_asisdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTNS_asisdmiscfp16_R(Rd, Rn, o1, o2);
#else
            RT_NOREF(Rd, Rn, o1, o2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e6a0000: FCVTNS  <Sd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_sisd_32D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e6a0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTNS_sisd_32D Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_sisd_32D
            IEM_INSTR_IMPL_A64__FCVTNS_sisd_32D(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1eea0000: FCVTNS  <Sd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_sisd_32H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1eea0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTNS_sisd_32H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_sisd_32H
            IEM_INSTR_IMPL_A64__FCVTNS_sisd_32H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9eea0000: FCVTNS  <Dd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_sisd_64H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9eea0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTNS_sisd_64H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_sisd_64H
            IEM_INSTR_IMPL_A64__FCVTNS_sisd_64H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e2a0000: FCVTNS  <Dd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNS_sisd_64S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e2a0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTNS_sisd_64S Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNS_sisd_64S
            IEM_INSTR_IMPL_A64__FCVTNS_sisd_64S(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e610000: FCVTNU  <Wd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_32D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e610000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTNU_32D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_32D_float2int
            IEM_INSTR_IMPL_A64__FCVTNU_32D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee10000: FCVTNU  <Wd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_32H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee10000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTNU_32H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_32H_float2int
            IEM_INSTR_IMPL_A64__FCVTNU_32H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e210000: FCVTNU  <Wd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_32S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e210000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTNU_32S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_32S_float2int
            IEM_INSTR_IMPL_A64__FCVTNU_32S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e610000: FCVTNU  <Xd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_64D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e610000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTNU_64D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_64D_float2int
            IEM_INSTR_IMPL_A64__FCVTNU_64D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ee10000: FCVTNU  <Xd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_64H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ee10000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTNU_64H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_64H_float2int
            IEM_INSTR_IMPL_A64__FCVTNU_64H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e210000: FCVTNU  <Xd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_64S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e210000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTNU_64S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_64S_float2int
            IEM_INSTR_IMPL_A64__FCVTNU_64S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2e21a800: FCVTNU  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTNU_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_asimdmisc_R
        IEM_INSTR_IMPL_A64__FCVTNU_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
        RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2e79a800: FCVTNU  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2e79a800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTNU_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTNU_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7e21a800: FCVTNU  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTNU_asisdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_asisdmisc_R
        IEM_INSTR_IMPL_A64__FCVTNU_asisdmisc_R(Rd, Rn, o1, sz, o2);
#else
        RT_NOREF(Rd, Rn, o1, sz, o2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7e79a800: FCVTNU  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_asisdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7e79a800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTNU_asisdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_asisdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTNU_asisdmiscfp16_R(Rd, Rn, o1, o2);
#else
            RT_NOREF(Rd, Rn, o1, o2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e6b0000: FCVTNU  <Sd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_sisd_32D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e6b0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTNU_sisd_32D Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_sisd_32D
            IEM_INSTR_IMPL_A64__FCVTNU_sisd_32D(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1eeb0000: FCVTNU  <Sd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_sisd_32H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1eeb0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTNU_sisd_32H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_sisd_32H
            IEM_INSTR_IMPL_A64__FCVTNU_sisd_32H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9eeb0000: FCVTNU  <Dd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_sisd_64H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9eeb0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTNU_sisd_64H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_sisd_64H
            IEM_INSTR_IMPL_A64__FCVTNU_sisd_64H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e2b0000: FCVTNU  <Dd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTNU_sisd_64S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e2b0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTNU_sisd_64S Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTNU_sisd_64S
            IEM_INSTR_IMPL_A64__FCVTNU_sisd_64S(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0e216800: FCVTN2  <Vd>.<Tb>, <Vn>.<Ta>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTN_asimdmisc_N, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0e216800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCVTN_asimdmisc_N Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTN_asimdmisc_N
            IEM_INSTR_IMPL_A64__FCVTN_asimdmisc_N(Rd, Rn, sz, Q);
#else
            RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e40f400: FCVTN  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTN_asimdsame2_D, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: FCVTN_asimdsame2_D Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTN_asimdsame2_D
        IEM_INSTR_IMPL_A64__FCVTN_asimdsame2_D(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e00f400: FCVTN2  <Vd>.<Ta>, <Vn>.4S, <Vm>.4S
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTN_asimdsame2_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: FCVTN_asimdsame2_H Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTN_asimdsame2_H
        IEM_INSTR_IMPL_A64__FCVTN_asimdsame2_H(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e680000: FCVTPS  <Wd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_32D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e680000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_32D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_32D_float2int
            IEM_INSTR_IMPL_A64__FCVTPS_32D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee80000: FCVTPS  <Wd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_32H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee80000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_32H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_32H_float2int
            IEM_INSTR_IMPL_A64__FCVTPS_32H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e280000: FCVTPS  <Wd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_32S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e280000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_32S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_32S_float2int
            IEM_INSTR_IMPL_A64__FCVTPS_32S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e680000: FCVTPS  <Xd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_64D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e680000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_64D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_64D_float2int
            IEM_INSTR_IMPL_A64__FCVTPS_64D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ee80000: FCVTPS  <Xd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_64H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ee80000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_64H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_64H_float2int
            IEM_INSTR_IMPL_A64__FCVTPS_64H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e280000: FCVTPS  <Xd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_64S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e280000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_64S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_64S_float2int
            IEM_INSTR_IMPL_A64__FCVTPS_64S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0ea1a800: FCVTPS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0ea1a800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_asimdmisc_R
            IEM_INSTR_IMPL_A64__FCVTPS_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0ef9a800: FCVTPS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0ef9a800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTPS_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/5ea1a800: FCVTPS  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_asisdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x5ea1a800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_asisdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_asisdmisc_R
            IEM_INSTR_IMPL_A64__FCVTPS_asisdmisc_R(Rd, Rn, o1, sz, o2);
#else
            RT_NOREF(Rd, Rn, o1, sz, o2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ef9a800: FCVTPS  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_asisdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCVTPS_asisdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_asisdmiscfp16_R
        IEM_INSTR_IMPL_A64__FCVTPS_asisdmiscfp16_R(Rd, Rn, o1, o2);
#else
        RT_NOREF(Rd, Rn, o1, o2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e720000: FCVTPS  <Sd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_sisd_32D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e720000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_sisd_32D Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_sisd_32D
            IEM_INSTR_IMPL_A64__FCVTPS_sisd_32D(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ef20000: FCVTPS  <Sd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_sisd_32H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ef20000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_sisd_32H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_sisd_32H
            IEM_INSTR_IMPL_A64__FCVTPS_sisd_32H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ef20000: FCVTPS  <Dd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_sisd_64H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ef20000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_sisd_64H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_sisd_64H
            IEM_INSTR_IMPL_A64__FCVTPS_sisd_64H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e320000: FCVTPS  <Dd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPS_sisd_64S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e320000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTPS_sisd_64S Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPS_sisd_64S
            IEM_INSTR_IMPL_A64__FCVTPS_sisd_64S(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e690000: FCVTPU  <Wd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_32D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e690000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_32D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_32D_float2int
            IEM_INSTR_IMPL_A64__FCVTPU_32D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee90000: FCVTPU  <Wd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_32H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee90000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_32H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_32H_float2int
            IEM_INSTR_IMPL_A64__FCVTPU_32H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e290000: FCVTPU  <Wd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_32S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e290000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_32S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_32S_float2int
            IEM_INSTR_IMPL_A64__FCVTPU_32S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e690000: FCVTPU  <Xd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_64D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e690000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_64D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_64D_float2int
            IEM_INSTR_IMPL_A64__FCVTPU_64D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ee90000: FCVTPU  <Xd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_64H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ee90000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_64H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_64H_float2int
            IEM_INSTR_IMPL_A64__FCVTPU_64H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e290000: FCVTPU  <Xd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_64S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e290000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_64S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_64S_float2int
            IEM_INSTR_IMPL_A64__FCVTPU_64S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2ea1a800: FCVTPU  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2ea1a800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_asimdmisc_R
            IEM_INSTR_IMPL_A64__FCVTPU_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2ef9a800: FCVTPU  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2ef9a800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTPU_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7ea1a800: FCVTPU  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_asisdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7ea1a800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_asisdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_asisdmisc_R
            IEM_INSTR_IMPL_A64__FCVTPU_asisdmisc_R(Rd, Rn, o1, sz, o2);
#else
            RT_NOREF(Rd, Rn, o1, sz, o2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7ef9a800: FCVTPU  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_asisdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7ef9a800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_asisdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_asisdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTPU_asisdmiscfp16_R(Rd, Rn, o1, o2);
#else
            RT_NOREF(Rd, Rn, o1, o2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e730000: FCVTPU  <Sd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_sisd_32D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e730000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_sisd_32D Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_sisd_32D
            IEM_INSTR_IMPL_A64__FCVTPU_sisd_32D(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ef30000: FCVTPU  <Sd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_sisd_32H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ef30000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_sisd_32H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_sisd_32H
            IEM_INSTR_IMPL_A64__FCVTPU_sisd_32H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ef30000: FCVTPU  <Dd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_sisd_64H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ef30000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_sisd_64H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_sisd_64H
            IEM_INSTR_IMPL_A64__FCVTPU_sisd_64H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e330000: FCVTPU  <Dd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTPU_sisd_64S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e330000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTPU_sisd_64S Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTPU_sisd_64S
            IEM_INSTR_IMPL_A64__FCVTPU_sisd_64S(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2e616800: FCVTXN2  <Vd>.<Tb>, <Vn>.2D
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTXN_asimdmisc_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FCVTXN_asimdmisc_N Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTXN_asimdmisc_N
        IEM_INSTR_IMPL_A64__FCVTXN_asimdmisc_N(Rd, Rn, Q);
#else
        RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7e616800: FCVTXN  S<d>, D<n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTXN_asisdmisc_N, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7e616800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCVTXN_asisdmisc_N Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTXN_asisdmisc_N
            IEM_INSTR_IMPL_A64__FCVTXN_asisdmisc_N(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/1e580000: FCVTZS  <Wd>, <Dn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_32D_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x1e580000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_32D_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_32D_float2fix
            IEM_INSTR_IMPL_A64__FCVTZS_32D_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e780000: FCVTZS  <Wd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_32D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e780000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_32D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_32D_float2int
            IEM_INSTR_IMPL_A64__FCVTZS_32D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/1ed80000: FCVTZS  <Wd>, <Hn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_32H_float2fix, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCVTZS_32H_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_32H_float2fix
        IEM_INSTR_IMPL_A64__FCVTZS_32H_float2fix(Rd, Rn, scale);
#else
        RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ef80000: FCVTZS  <Wd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_32H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ef80000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_32H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_32H_float2int
            IEM_INSTR_IMPL_A64__FCVTZS_32H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/1e180000: FCVTZS  <Wd>, <Sn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_32S_float2fix, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FCVTZS_32S_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_32S_float2fix
        IEM_INSTR_IMPL_A64__FCVTZS_32S_float2fix(Rd, Rn, scale);
#else
        RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e380000: FCVTZS  <Wd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_32S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e380000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_32S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_32S_float2int
            IEM_INSTR_IMPL_A64__FCVTZS_32S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/9e580000: FCVTZS  <Xd>, <Dn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_64D_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x9e580000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_64D_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_64D_float2fix
            IEM_INSTR_IMPL_A64__FCVTZS_64D_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e780000: FCVTZS  <Xd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_64D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e780000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_64D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_64D_float2int
            IEM_INSTR_IMPL_A64__FCVTZS_64D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/9ed80000: FCVTZS  <Xd>, <Hn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_64H_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x9ed80000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_64H_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_64H_float2fix
            IEM_INSTR_IMPL_A64__FCVTZS_64H_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ef80000: FCVTZS  <Xd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_64H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ef80000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_64H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_64H_float2int
            IEM_INSTR_IMPL_A64__FCVTZS_64H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/9e180000: FCVTZS  <Xd>, <Sn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_64S_float2fix, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FCVTZS_64S_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_64S_float2fix
        IEM_INSTR_IMPL_A64__FCVTZS_64S_float2fix(Rd, Rn, scale);
#else
        RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e380000: FCVTZS  <Xd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_64S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e380000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_64S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_64S_float2int
            IEM_INSTR_IMPL_A64__FCVTZS_64S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0ea1b800: FCVTZS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0ea1b800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_asimdmisc_R
            IEM_INSTR_IMPL_A64__FCVTZS_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0ef9b800: FCVTZS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0ef9b800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTZS_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f00fc00: FCVTZS  <Vd>.<T>, <Vn>.<T>, #<fbits>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_asimdshf_C, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: FCVTZS_asimdshf_C Rd=%#x Rn=%#x immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_asimdshf_C
        IEM_INSTR_IMPL_A64__FCVTZS_asimdshf_C(Rd, Rn, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/5ea1b800: FCVTZS  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_asisdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x5ea1b800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_asisdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_asisdmisc_R
            IEM_INSTR_IMPL_A64__FCVTZS_asisdmisc_R(Rd, Rn, o1, sz, o2);
#else
            RT_NOREF(Rd, Rn, o1, sz, o2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ef9b800: FCVTZS  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_asisdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCVTZS_asisdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_asisdmiscfp16_R
        IEM_INSTR_IMPL_A64__FCVTZS_asisdmiscfp16_R(Rd, Rn, o1, o2);
#else
        RT_NOREF(Rd, Rn, o1, o2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/5f00fc00: FCVTZS  <V><d>, <V><n>, #<fbits>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_asisdshf_C, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x5f00fc00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
        {
            LogFlow(("%018x/%010x: FCVTZS_asisdshf_C Rd=%#x Rn=%#x immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_asisdshf_C
            IEM_INSTR_IMPL_A64__FCVTZS_asisdshf_C(Rd, Rn, immb, immh);
#else
            RT_NOREF(Rd, Rn, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e760000: FCVTZS  <Sd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_sisd_32D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e760000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_sisd_32D Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_sisd_32D
            IEM_INSTR_IMPL_A64__FCVTZS_sisd_32D(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ef60000: FCVTZS  <Sd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_sisd_32H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ef60000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_sisd_32H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_sisd_32H
            IEM_INSTR_IMPL_A64__FCVTZS_sisd_32H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ef60000: FCVTZS  <Dd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_sisd_64H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ef60000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_sisd_64H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_sisd_64H
            IEM_INSTR_IMPL_A64__FCVTZS_sisd_64H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e360000: FCVTZS  <Dd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZS_sisd_64S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e360000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTZS_sisd_64S Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZS_sisd_64S
            IEM_INSTR_IMPL_A64__FCVTZS_sisd_64S(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/1e590000: FCVTZU  <Wd>, <Dn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_32D_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x1e590000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_32D_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_32D_float2fix
            IEM_INSTR_IMPL_A64__FCVTZU_32D_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e790000: FCVTZU  <Wd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_32D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e790000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_32D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_32D_float2int
            IEM_INSTR_IMPL_A64__FCVTZU_32D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/1ed90000: FCVTZU  <Wd>, <Hn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_32H_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x1ed90000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_32H_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_32H_float2fix
            IEM_INSTR_IMPL_A64__FCVTZU_32H_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ef90000: FCVTZU  <Wd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_32H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ef90000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_32H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_32H_float2int
            IEM_INSTR_IMPL_A64__FCVTZU_32H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/1e190000: FCVTZU  <Wd>, <Sn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_32S_float2fix, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FCVTZU_32S_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_32S_float2fix
        IEM_INSTR_IMPL_A64__FCVTZU_32S_float2fix(Rd, Rn, scale);
#else
        RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e390000: FCVTZU  <Wd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_32S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e390000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_32S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_32S_float2int
            IEM_INSTR_IMPL_A64__FCVTZU_32S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/9e590000: FCVTZU  <Xd>, <Dn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_64D_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x9e590000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_64D_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_64D_float2fix
            IEM_INSTR_IMPL_A64__FCVTZU_64D_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e790000: FCVTZU  <Xd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_64D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e790000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_64D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_64D_float2int
            IEM_INSTR_IMPL_A64__FCVTZU_64D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/9ed90000: FCVTZU  <Xd>, <Hn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_64H_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x9ed90000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_64H_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_64H_float2fix
            IEM_INSTR_IMPL_A64__FCVTZU_64H_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ef90000: FCVTZU  <Xd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_64H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ef90000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_64H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_64H_float2int
            IEM_INSTR_IMPL_A64__FCVTZU_64H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/9e190000: FCVTZU  <Xd>, <Sn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_64S_float2fix, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FCVTZU_64S_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_64S_float2fix
        IEM_INSTR_IMPL_A64__FCVTZU_64S_float2fix(Rd, Rn, scale);
#else
        RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e390000: FCVTZU  <Xd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_64S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e390000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_64S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_64S_float2int
            IEM_INSTR_IMPL_A64__FCVTZU_64S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2ea1b800: FCVTZU  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2ea1b800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_asimdmisc_R
            IEM_INSTR_IMPL_A64__FCVTZU_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2ef9b800: FCVTZU  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2ef9b800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FCVTZU_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f00fc00: FCVTZU  <Vd>.<T>, <Vn>.<T>, #<fbits>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_asimdshf_C, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f00fc00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
        {
            LogFlow(("%018x/%010x: FCVTZU_asimdshf_C Rd=%#x Rn=%#x immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_asimdshf_C
            IEM_INSTR_IMPL_A64__FCVTZU_asimdshf_C(Rd, Rn, immb, immh, Q);
#else
            RT_NOREF(Rd, Rn, immb, immh, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7ea1b800: FCVTZU  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_asisdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7ea1b800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_asisdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_asisdmisc_R
            IEM_INSTR_IMPL_A64__FCVTZU_asisdmisc_R(Rd, Rn, o1, sz, o2);
#else
            RT_NOREF(Rd, Rn, o1, sz, o2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7ef9b800: FCVTZU  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_asisdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FCVTZU_asisdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_asisdmiscfp16_R
        IEM_INSTR_IMPL_A64__FCVTZU_asisdmiscfp16_R(Rd, Rn, o1, o2);
#else
        RT_NOREF(Rd, Rn, o1, o2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f00fc00: FCVTZU  <V><d>, <V><n>, #<fbits>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_asisdshf_C, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f00fc00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
        {
            LogFlow(("%018x/%010x: FCVTZU_asisdshf_C Rd=%#x Rn=%#x immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_asisdshf_C
            IEM_INSTR_IMPL_A64__FCVTZU_asisdshf_C(Rd, Rn, immb, immh);
#else
            RT_NOREF(Rd, Rn, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e770000: FCVTZU  <Sd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_sisd_32D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e770000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_sisd_32D Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_sisd_32D
            IEM_INSTR_IMPL_A64__FCVTZU_sisd_32D(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ef70000: FCVTZU  <Sd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_sisd_32H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ef70000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_sisd_32H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_sisd_32H
            IEM_INSTR_IMPL_A64__FCVTZU_sisd_32H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ef70000: FCVTZU  <Dd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_sisd_64H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ef70000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_sisd_64H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_sisd_64H
            IEM_INSTR_IMPL_A64__FCVTZU_sisd_64H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e370000: FCVTZU  <Dd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVTZU_sisd_64S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e370000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: FCVTZU_sisd_64S Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FCVTZU_sisd_64S
            IEM_INSTR_IMPL_A64__FCVTZU_sisd_64S(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee2c000: FCVT  <Dd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVT_DH_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee2c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVT_DH_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FCVT_DH_floatdp1
            IEM_INSTR_IMPL_A64__FCVT_DH_floatdp1(Rd, Rn, opc);
#else
            RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e22c000: FCVT  <Dd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVT_DS_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e22c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVT_DS_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FCVT_DS_floatdp1
            IEM_INSTR_IMPL_A64__FCVT_DS_floatdp1(Rd, Rn, opc);
#else
            RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e63c000: FCVT  <Hd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVT_HD_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e63c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVT_HD_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FCVT_HD_floatdp1
            IEM_INSTR_IMPL_A64__FCVT_HD_floatdp1(Rd, Rn, opc);
#else
            RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e23c000: FCVT  <Hd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVT_HS_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e23c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVT_HS_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FCVT_HS_floatdp1
            IEM_INSTR_IMPL_A64__FCVT_HS_floatdp1(Rd, Rn, opc);
#else
            RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e624000: FCVT  <Sd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVT_SD_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e624000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVT_SD_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FCVT_SD_floatdp1
            IEM_INSTR_IMPL_A64__FCVT_SD_floatdp1(Rd, Rn, opc);
#else
            RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee24000: FCVT  <Sd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FCVT_SH_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee24000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FCVT_SH_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FCVT_SH_floatdp1
            IEM_INSTR_IMPL_A64__FCVT_SH_floatdp1(Rd, Rn, opc);
#else
            RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e601800: FDIV  <Dd>, <Dn>, <Dm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FDIV_D_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e601800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FDIV_D_floatdp2 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FDIV_D_floatdp2
            IEM_INSTR_IMPL_A64__FDIV_D_floatdp2(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ee01800: FDIV  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FDIV_H_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ee01800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FDIV_H_floatdp2 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FDIV_H_floatdp2
            IEM_INSTR_IMPL_A64__FDIV_H_floatdp2(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e201800: FDIV  <Sd>, <Sn>, <Sm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FDIV_S_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FDIV_S_floatdp2 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FDIV_S_floatdp2
        IEM_INSTR_IMPL_A64__FDIV_S_floatdp2(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/2e20fc00: FDIV  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FDIV_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FDIV_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FDIV_asimdsame_only
        IEM_INSTR_IMPL_A64__FDIV_asimdsame_only(Rd, Rn, Rm, sz, Q);
#else
        RT_NOREF(Rd, Rn, Rm, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2e403c00: FDIV  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FDIV_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2e403c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FDIV_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FDIV_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FDIV_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/0f000000: FDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FDOT_asimdelem_D, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8DOT4*/)
    {
        LogFlow(("%018x/%010x: FDOT_asimdelem_D Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, Q));
#ifdef IEM_INSTR_IMPL_A64__FDOT_asimdelem_D
        IEM_INSTR_IMPL_A64__FDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, Q);
#else
        RT_NOREF(Rd, Rn, H, Rm, M, L, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/0f400000: FDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.2B[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FDOT_asimdelem_G, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8DOT2*/)
    {
        LogFlow(("%018x/%010x: FDOT_asimdelem_G Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, Q));
#ifdef IEM_INSTR_IMPL_A64__FDOT_asimdelem_G
        IEM_INSTR_IMPL_A64__FDOT_asimdelem_G(Rd, Rn, H, Rm, M, L, Q);
#else
        RT_NOREF(Rd, Rn, H, Rm, M, L, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e40fc00: FDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FDOT_asimdsame2_D, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8DOT2*/)
    {
        LogFlow(("%018x/%010x: FDOT_asimdsame2_D Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FDOT_asimdsame2_D
        IEM_INSTR_IMPL_A64__FDOT_asimdsame2_D(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e00fc00: FDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FDOT_asimdsame2_DD, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e00fc00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8DOT4*/)
        {
            LogFlow(("%018x/%010x: FDOT_asimdsame2_DD Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FDOT_asimdsame2_DD
            IEM_INSTR_IMPL_A64__FDOT_asimdsame2_DD(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e7e0000: FJCVTZS  <Wd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FJCVTZS_32D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e7e0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fJscvt /*FEAT_JSCVT*/)
        {
            LogFlow(("%018x/%010x: FJCVTZS_32D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FJCVTZS_32D_float2int
            IEM_INSTR_IMPL_A64__FJCVTZS_32D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1f400000: FMADD  <Dd>, <Dn>, <Dm>, <Da>
   Instruction Set: A64  Groups: floatdp3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMADD_D_floatdp3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMADD_D_floatdp3 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMADD_D_floatdp3
        IEM_INSTR_IMPL_A64__FMADD_D_floatdp3(Rd, Rn, Ra, Rm);
#else
        RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1fc00000: FMADD  <Hd>, <Hn>, <Hm>, <Ha>
   Instruction Set: A64  Groups: floatdp3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMADD_H_floatdp3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMADD_H_floatdp3 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMADD_H_floatdp3
        IEM_INSTR_IMPL_A64__FMADD_H_floatdp3(Rd, Rn, Ra, Rm);
#else
        RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1f000000: FMADD  <Sd>, <Sn>, <Sm>, <Sa>
   Instruction Set: A64  Groups: floatdp3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMADD_S_floatdp3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMADD_S_floatdp3 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMADD_S_floatdp3
        IEM_INSTR_IMPL_A64__FMADD_S_floatdp3(Rd, Rn, Ra, Rm);
#else
        RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/2e20c400: FMAXNMP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXNMP_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x2e20c400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMAXNMP_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMAXNMP_asimdsame_only
            IEM_INSTR_IMPL_A64__FMAXNMP_asimdsame_only(Rd, Rn, Rm, sz, o1, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, o1, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2e400400: FMAXNMP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXNMP_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2e400400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMAXNMP_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FMAXNMP_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FMAXNMP_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5e30c800: FMAXNMP  H<d>, <Vn>.2H
   Instruction Set: A64  Groups: asisdpair, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXNMP_asisdpair_only_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMAXNMP_asisdpair_only_H Rd=%#x Rn=%#x sz=%u o1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, o1));
#ifdef IEM_INSTR_IMPL_A64__FMAXNMP_asisdpair_only_H
        IEM_INSTR_IMPL_A64__FMAXNMP_asisdpair_only_H(Rd, Rn, sz, o1);
#else
        RT_NOREF(Rd, Rn, sz, o1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7e30c800: FMAXNMP  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asisdpair, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXNMP_asisdpair_only_SD, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMAXNMP_asisdpair_only_SD Rd=%#x Rn=%#x sz=%u o1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, o1));
#ifdef IEM_INSTR_IMPL_A64__FMAXNMP_asisdpair_only_SD
        IEM_INSTR_IMPL_A64__FMAXNMP_asisdpair_only_SD(Rd, Rn, sz, o1);
#else
        RT_NOREF(Rd, Rn, sz, o1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0e30c800: FMAXNMV  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXNMV_asimdall_only_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMAXNMV_asimdall_only_H Rd=%#x Rn=%#x o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMAXNMV_asimdall_only_H
        IEM_INSTR_IMPL_A64__FMAXNMV_asimdall_only_H(Rd, Rn, o1, Q);
#else
        RT_NOREF(Rd, Rn, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/6e30c800: FMAXNMV  S<d>, <Vn>.4S
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXNMV_asimdall_only_SD, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMAXNMV_asimdall_only_SD Rd=%#x Rn=%#x sz=%u o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMAXNMV_asimdall_only_SD
        IEM_INSTR_IMPL_A64__FMAXNMV_asimdall_only_SD(Rd, Rn, sz, o1, Q);
#else
        RT_NOREF(Rd, Rn, sz, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e606800: FMAXNM  <Dd>, <Dn>, <Dm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXNM_D_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e606800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FMAXNM_D_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMAXNM_D_floatdp2
            IEM_INSTR_IMPL_A64__FMAXNM_D_floatdp2(Rd, Rn, op, Rm);
#else
            RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ee06800: FMAXNM  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXNM_H_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ee06800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMAXNM_H_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMAXNM_H_floatdp2
            IEM_INSTR_IMPL_A64__FMAXNM_H_floatdp2(Rd, Rn, op, Rm);
#else
            RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e206800: FMAXNM  <Sd>, <Sn>, <Sm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXNM_S_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e206800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FMAXNM_S_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMAXNM_S_floatdp2
            IEM_INSTR_IMPL_A64__FMAXNM_S_floatdp2(Rd, Rn, op, Rm);
#else
            RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/0e20c400: FMAXNM  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXNM_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x0e20c400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMAXNM_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMAXNM_asimdsame_only
            IEM_INSTR_IMPL_A64__FMAXNM_asimdsame_only(Rd, Rn, Rm, sz, o1, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, o1, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e400400: FMAXNM  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXNM_asimdsamefp16_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMAXNM_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FMAXNM_asimdsamefp16_only
        IEM_INSTR_IMPL_A64__FMAXNM_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/2e20f400: FMAXP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXP_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x2e20f400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMAXP_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMAXP_asimdsame_only
            IEM_INSTR_IMPL_A64__FMAXP_asimdsame_only(Rd, Rn, Rm, sz, o1, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, o1, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2e403400: FMAXP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXP_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2e403400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMAXP_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMAXP_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FMAXP_asimdsamefp16_only(Rd, Rn, Rm, o1, Q);
#else
            RT_NOREF(Rd, Rn, Rm, o1, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5e30f800: FMAXP  H<d>, <Vn>.2H
   Instruction Set: A64  Groups: asisdpair, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXP_asisdpair_only_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMAXP_asisdpair_only_H Rd=%#x Rn=%#x sz=%u o1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, o1));
#ifdef IEM_INSTR_IMPL_A64__FMAXP_asisdpair_only_H
        IEM_INSTR_IMPL_A64__FMAXP_asisdpair_only_H(Rd, Rn, sz, o1);
#else
        RT_NOREF(Rd, Rn, sz, o1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7e30f800: FMAXP  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asisdpair, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXP_asisdpair_only_SD, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMAXP_asisdpair_only_SD Rd=%#x Rn=%#x sz=%u o1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, o1));
#ifdef IEM_INSTR_IMPL_A64__FMAXP_asisdpair_only_SD
        IEM_INSTR_IMPL_A64__FMAXP_asisdpair_only_SD(Rd, Rn, sz, o1);
#else
        RT_NOREF(Rd, Rn, sz, o1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0e30f800: FMAXV  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXV_asimdall_only_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMAXV_asimdall_only_H Rd=%#x Rn=%#x o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMAXV_asimdall_only_H
        IEM_INSTR_IMPL_A64__FMAXV_asimdall_only_H(Rd, Rn, o1, Q);
#else
        RT_NOREF(Rd, Rn, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/6e30f800: FMAXV  S<d>, <Vn>.4S
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAXV_asimdall_only_SD, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMAXV_asimdall_only_SD Rd=%#x Rn=%#x sz=%u o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMAXV_asimdall_only_SD
        IEM_INSTR_IMPL_A64__FMAXV_asimdall_only_SD(Rd, Rn, sz, o1, Q);
#else
        RT_NOREF(Rd, Rn, sz, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e604800: FMAX  <Dd>, <Dn>, <Dm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAX_D_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e604800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FMAX_D_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMAX_D_floatdp2
            IEM_INSTR_IMPL_A64__FMAX_D_floatdp2(Rd, Rn, op, Rm);
#else
            RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ee04800: FMAX  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAX_H_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ee04800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMAX_H_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMAX_H_floatdp2
            IEM_INSTR_IMPL_A64__FMAX_H_floatdp2(Rd, Rn, op, Rm);
#else
            RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e204800: FMAX  <Sd>, <Sn>, <Sm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAX_S_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e204800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FMAX_S_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMAX_S_floatdp2
            IEM_INSTR_IMPL_A64__FMAX_S_floatdp2(Rd, Rn, op, Rm);
#else
            RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/0e20f400: FMAX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAX_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMAX_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMAX_asimdsame_only
        IEM_INSTR_IMPL_A64__FMAX_asimdsame_only(Rd, Rn, Rm, sz, o1, Q);
#else
        RT_NOREF(Rd, Rn, Rm, sz, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e403400: FMAX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMAX_asimdsamefp16_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMAX_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMAX_asimdsamefp16_only
        IEM_INSTR_IMPL_A64__FMAX_asimdsamefp16_only(Rd, Rn, Rm, o1, Q);
#else
        RT_NOREF(Rd, Rn, Rm, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/2ea0c400: FMINNMP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINNMP_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x2ea0c400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMINNMP_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMINNMP_asimdsame_only
            IEM_INSTR_IMPL_A64__FMINNMP_asimdsame_only(Rd, Rn, Rm, sz, o1, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, o1, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2ec00400: FMINNMP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINNMP_asimdsamefp16_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMINNMP_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FMINNMP_asimdsamefp16_only
        IEM_INSTR_IMPL_A64__FMINNMP_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5eb0c800: FMINNMP  H<d>, <Vn>.2H
   Instruction Set: A64  Groups: asisdpair, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINNMP_asisdpair_only_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMINNMP_asisdpair_only_H Rd=%#x Rn=%#x sz=%u o1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, o1));
#ifdef IEM_INSTR_IMPL_A64__FMINNMP_asisdpair_only_H
        IEM_INSTR_IMPL_A64__FMINNMP_asisdpair_only_H(Rd, Rn, sz, o1);
#else
        RT_NOREF(Rd, Rn, sz, o1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7eb0c800: FMINNMP  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asisdpair, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINNMP_asisdpair_only_SD, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMINNMP_asisdpair_only_SD Rd=%#x Rn=%#x sz=%u o1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, o1));
#ifdef IEM_INSTR_IMPL_A64__FMINNMP_asisdpair_only_SD
        IEM_INSTR_IMPL_A64__FMINNMP_asisdpair_only_SD(Rd, Rn, sz, o1);
#else
        RT_NOREF(Rd, Rn, sz, o1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0eb0c800: FMINNMV  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINNMV_asimdall_only_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMINNMV_asimdall_only_H Rd=%#x Rn=%#x o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMINNMV_asimdall_only_H
        IEM_INSTR_IMPL_A64__FMINNMV_asimdall_only_H(Rd, Rn, o1, Q);
#else
        RT_NOREF(Rd, Rn, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/6eb0c800: FMINNMV  S<d>, <Vn>.4S
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINNMV_asimdall_only_SD, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMINNMV_asimdall_only_SD Rd=%#x Rn=%#x sz=%u o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMINNMV_asimdall_only_SD
        IEM_INSTR_IMPL_A64__FMINNMV_asimdall_only_SD(Rd, Rn, sz, o1, Q);
#else
        RT_NOREF(Rd, Rn, sz, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e607800: FMINNM  <Dd>, <Dn>, <Dm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINNM_D_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e607800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FMINNM_D_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMINNM_D_floatdp2
            IEM_INSTR_IMPL_A64__FMINNM_D_floatdp2(Rd, Rn, op, Rm);
#else
            RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ee07800: FMINNM  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINNM_H_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ee07800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMINNM_H_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMINNM_H_floatdp2
            IEM_INSTR_IMPL_A64__FMINNM_H_floatdp2(Rd, Rn, op, Rm);
#else
            RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e207800: FMINNM  <Sd>, <Sn>, <Sm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINNM_S_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMINNM_S_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMINNM_S_floatdp2
        IEM_INSTR_IMPL_A64__FMINNM_S_floatdp2(Rd, Rn, op, Rm);
#else
        RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/0ea0c400: FMINNM  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINNM_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMINNM_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMINNM_asimdsame_only
        IEM_INSTR_IMPL_A64__FMINNM_asimdsame_only(Rd, Rn, Rm, sz, o1, Q);
#else
        RT_NOREF(Rd, Rn, Rm, sz, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0ec00400: FMINNM  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINNM_asimdsamefp16_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMINNM_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FMINNM_asimdsamefp16_only
        IEM_INSTR_IMPL_A64__FMINNM_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/2ea0f400: FMINP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINP_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x2ea0f400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMINP_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMINP_asimdsame_only
            IEM_INSTR_IMPL_A64__FMINP_asimdsame_only(Rd, Rn, Rm, sz, o1, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, o1, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2ec03400: FMINP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINP_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2ec03400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMINP_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMINP_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FMINP_asimdsamefp16_only(Rd, Rn, Rm, o1, Q);
#else
            RT_NOREF(Rd, Rn, Rm, o1, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5eb0f800: FMINP  H<d>, <Vn>.2H
   Instruction Set: A64  Groups: asisdpair, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINP_asisdpair_only_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMINP_asisdpair_only_H Rd=%#x Rn=%#x sz=%u o1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, o1));
#ifdef IEM_INSTR_IMPL_A64__FMINP_asisdpair_only_H
        IEM_INSTR_IMPL_A64__FMINP_asisdpair_only_H(Rd, Rn, sz, o1);
#else
        RT_NOREF(Rd, Rn, sz, o1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7eb0f800: FMINP  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asisdpair, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINP_asisdpair_only_SD, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMINP_asisdpair_only_SD Rd=%#x Rn=%#x sz=%u o1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, o1));
#ifdef IEM_INSTR_IMPL_A64__FMINP_asisdpair_only_SD
        IEM_INSTR_IMPL_A64__FMINP_asisdpair_only_SD(Rd, Rn, sz, o1);
#else
        RT_NOREF(Rd, Rn, sz, o1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0eb0f800: FMINV  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINV_asimdall_only_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMINV_asimdall_only_H Rd=%#x Rn=%#x o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMINV_asimdall_only_H
        IEM_INSTR_IMPL_A64__FMINV_asimdall_only_H(Rd, Rn, o1, Q);
#else
        RT_NOREF(Rd, Rn, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/6eb0f800: FMINV  S<d>, <Vn>.4S
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMINV_asimdall_only_SD, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMINV_asimdall_only_SD Rd=%#x Rn=%#x sz=%u o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMINV_asimdall_only_SD
        IEM_INSTR_IMPL_A64__FMINV_asimdall_only_SD(Rd, Rn, sz, o1, Q);
#else
        RT_NOREF(Rd, Rn, sz, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e605800: FMIN  <Dd>, <Dn>, <Dm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMIN_D_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMIN_D_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMIN_D_floatdp2
        IEM_INSTR_IMPL_A64__FMIN_D_floatdp2(Rd, Rn, op, Rm);
#else
        RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ee05800: FMIN  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMIN_H_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ee05800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMIN_H_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMIN_H_floatdp2
            IEM_INSTR_IMPL_A64__FMIN_H_floatdp2(Rd, Rn, op, Rm);
#else
            RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e205800: FMIN  <Sd>, <Sn>, <Sm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMIN_S_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMIN_S_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMIN_S_floatdp2
        IEM_INSTR_IMPL_A64__FMIN_S_floatdp2(Rd, Rn, op, Rm);
#else
        RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/0ea0f400: FMIN  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMIN_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMIN_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMIN_asimdsame_only
        IEM_INSTR_IMPL_A64__FMIN_asimdsame_only(Rd, Rn, Rm, sz, o1, Q);
#else
        RT_NOREF(Rd, Rn, Rm, sz, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0ec03400: FMIN  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMIN_asimdsamefp16_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMIN_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x o1=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, o1, Q));
#ifdef IEM_INSTR_IMPL_A64__FMIN_asimdsamefp16_only
        IEM_INSTR_IMPL_A64__FMIN_asimdsamefp16_only(Rd, Rn, Rm, o1, Q);
#else
        RT_NOREF(Rd, Rn, Rm, o1, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/2f808000: FMLAL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLAL2_asimdelem_LH, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const S          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFhm /*FEAT_FHM*/)
    {
        LogFlow(("%018x/%010x: FMLAL2_asimdelem_LH Rd=%#x Rn=%#x H=%u S=%u Rm=%#x M=%u L=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, S, Rm, M, L, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLAL2_asimdelem_LH
        IEM_INSTR_IMPL_A64__FMLAL2_asimdelem_LH(Rd, Rn, H, S, Rm, M, L, sz, Q);
#else
        RT_NOREF(Rd, Rn, H, S, Rm, M, L, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2e20cc00: FMLAL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLAL2_asimdsame_F, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2e20cc00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const S          = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFhm /*FEAT_FHM*/)
        {
            LogFlow(("%018x/%010x: FMLAL2_asimdsame_F Rd=%#x Rn=%#x Rm=%#x sz=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, S, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLAL2_asimdsame_F
            IEM_INSTR_IMPL_A64__FMLAL2_asimdsame_F(Rd, Rn, Rm, sz, S, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0f400/0fc00000: FMLALB  <Vd>.8H, <Vn>.16B, <Vm>.B[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLALB_asimdelem_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/)
    {
        LogFlow(("%018x/%010x: FMLALB_asimdelem_H Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L));
#ifdef IEM_INSTR_IMPL_A64__FMLALB_asimdelem_H
        IEM_INSTR_IMPL_A64__FMLALB_asimdelem_H(Rd, Rn, H, Rm, M, L);
#else
        RT_NOREF(Rd, Rn, H, Rm, M, L, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/0ec0fc00: FMLALB  <Vd>.8H, <Vn>.16B, <Vm>.16B
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLALB_asimdsame2_J, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/)
    {
        LogFlow(("%018x/%010x: FMLALB_asimdsame2_J Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMLALB_asimdsame2_J
        IEM_INSTR_IMPL_A64__FMLALB_asimdsame2_J(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0f400/2f008000: FMLALLBB  <Vd>.4S, <Vn>.16B, <Vm>.B[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLALLBB_asimdelem_J, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0f400)) == UINT32_C(0x2f008000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: FMLALLBB_asimdelem_J Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L));
#ifdef IEM_INSTR_IMPL_A64__FMLALLBB_asimdelem_J
            IEM_INSTR_IMPL_A64__FMLALLBB_asimdelem_J(Rd, Rn, H, Rm, M, L);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/0e00c400: FMLALLBB  <Vd>.4S, <Vn>.16B, <Vm>.16B
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLALLBB_asimdsame2_G, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/)
    {
        LogFlow(("%018x/%010x: FMLALLBB_asimdsame2_G Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMLALLBB_asimdsame2_G
        IEM_INSTR_IMPL_A64__FMLALLBB_asimdsame2_G(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0f400/2f408000: FMLALLBT  <Vd>.4S, <Vn>.16B, <Vm>.B[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLALLBT_asimdelem_J, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0f400)) == UINT32_C(0x2f408000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: FMLALLBT_asimdelem_J Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L));
#ifdef IEM_INSTR_IMPL_A64__FMLALLBT_asimdelem_J
            IEM_INSTR_IMPL_A64__FMLALLBT_asimdelem_J(Rd, Rn, H, Rm, M, L);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/0e40c400: FMLALLBT  <Vd>.4S, <Vn>.16B, <Vm>.16B
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLALLBT_asimdsame2_G, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/)
    {
        LogFlow(("%018x/%010x: FMLALLBT_asimdsame2_G Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMLALLBT_asimdsame2_G
        IEM_INSTR_IMPL_A64__FMLALLBT_asimdsame2_G(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0f400/6f008000: FMLALLTB  <Vd>.4S, <Vn>.16B, <Vm>.B[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLALLTB_asimdelem_J, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/)
    {
        LogFlow(("%018x/%010x: FMLALLTB_asimdelem_J Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L));
#ifdef IEM_INSTR_IMPL_A64__FMLALLTB_asimdelem_J
        IEM_INSTR_IMPL_A64__FMLALLTB_asimdelem_J(Rd, Rn, H, Rm, M, L);
#else
        RT_NOREF(Rd, Rn, H, Rm, M, L, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4e00c400: FMLALLTB  <Vd>.4S, <Vn>.16B, <Vm>.16B
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLALLTB_asimdsame2_G, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/)
    {
        LogFlow(("%018x/%010x: FMLALLTB_asimdsame2_G Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMLALLTB_asimdsame2_G
        IEM_INSTR_IMPL_A64__FMLALLTB_asimdsame2_G(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0f400/6f408000: FMLALLTT  <Vd>.4S, <Vn>.16B, <Vm>.B[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLALLTT_asimdelem_J, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0f400)) == UINT32_C(0x6f408000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: FMLALLTT_asimdelem_J Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L));
#ifdef IEM_INSTR_IMPL_A64__FMLALLTT_asimdelem_J
            IEM_INSTR_IMPL_A64__FMLALLTT_asimdelem_J(Rd, Rn, H, Rm, M, L);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4e40c400: FMLALLTT  <Vd>.4S, <Vn>.16B, <Vm>.16B
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLALLTT_asimdsame2_G, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4e40c400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: FMLALLTT_asimdsame2_G Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMLALLTT_asimdsame2_G
            IEM_INSTR_IMPL_A64__FMLALLTT_asimdsame2_G(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0f400/4fc00000: FMLALT  <Vd>.8H, <Vn>.16B, <Vm>.B[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLALT_asimdelem_H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0f400)) == UINT32_C(0x4fc00000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: FMLALT_asimdelem_H Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L));
#ifdef IEM_INSTR_IMPL_A64__FMLALT_asimdelem_H
            IEM_INSTR_IMPL_A64__FMLALT_asimdelem_H(Rd, Rn, H, Rm, M, L);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4ec0fc00: FMLALT  <Vd>.8H, <Vn>.16B, <Vm>.16B
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLALT_asimdsame2_J, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4ec0fc00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: FMLALT_asimdsame2_J Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMLALT_asimdsame2_J
            IEM_INSTR_IMPL_A64__FMLALT_asimdsame2_J(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/0f800000: FMLAL  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLAL_asimdelem_LH, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x0f800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const S          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFhm /*FEAT_FHM*/)
        {
            LogFlow(("%018x/%010x: FMLAL_asimdelem_LH Rd=%#x Rn=%#x H=%u S=%u Rm=%#x M=%u L=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, S, Rm, M, L, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLAL_asimdelem_LH
            IEM_INSTR_IMPL_A64__FMLAL_asimdelem_LH(Rd, Rn, H, S, Rm, M, L, sz, Q);
#else
            RT_NOREF(Rd, Rn, H, S, Rm, M, L, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e20ec00: FMLAL  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLAL_asimdsame_F, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e20ec00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const S          = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFhm /*FEAT_FHM*/)
        {
            LogFlow(("%018x/%010x: FMLAL_asimdsame_F Rd=%#x Rn=%#x Rm=%#x sz=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, S, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLAL_asimdsame_F
            IEM_INSTR_IMPL_A64__FMLAL_asimdsame_F(Rd, Rn, Rm, sz, S, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/0f001000: FMLA  <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLA_asimdelem_RH_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMLA_asimdelem_RH_H Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLA_asimdelem_RH_H
        IEM_INSTR_IMPL_A64__FMLA_asimdelem_RH_H(Rd, Rn, H, o2, Rm, M, L, Q);
#else
        RT_NOREF(Rd, Rn, H, o2, Rm, M, L, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80f400/0f801000: FMLA  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLA_asimdelem_R_SD, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80f400)) == UINT32_C(0x0f801000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMLA_asimdelem_R_SD Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLA_asimdelem_R_SD
            IEM_INSTR_IMPL_A64__FMLA_asimdelem_R_SD(Rd, Rn, H, o2, Rm, M, L, sz, Q);
#else
            RT_NOREF(Rd, Rn, H, o2, Rm, M, L, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/0e20cc00: FMLA  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLA_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x0e20cc00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const op         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMLA_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u op=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, op, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLA_asimdsame_only
            IEM_INSTR_IMPL_A64__FMLA_asimdsame_only(Rd, Rn, Rm, sz, op, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, op, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e400c00: FMLA  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLA_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e400c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMLA_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLA_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FMLA_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0f400/5f001000: FMLA  <Hd>, <Hn>, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLA_asisdelem_RH_H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0f400)) == UINT32_C(0x5f001000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMLA_asisdelem_RH_H Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L));
#ifdef IEM_INSTR_IMPL_A64__FMLA_asisdelem_RH_H
            IEM_INSTR_IMPL_A64__FMLA_asisdelem_RH_H(Rd, Rn, H, o2, Rm, M, L);
#else
            RT_NOREF(Rd, Rn, H, o2, Rm, M, L, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80f400/5f801000: FMLA  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLA_asisdelem_R_SD, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80f400)) == UINT32_C(0x5f801000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMLA_asisdelem_R_SD Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, sz));
#ifdef IEM_INSTR_IMPL_A64__FMLA_asisdelem_R_SD
            IEM_INSTR_IMPL_A64__FMLA_asisdelem_R_SD(Rd, Rn, H, o2, Rm, M, L, sz);
#else
            RT_NOREF(Rd, Rn, H, o2, Rm, M, L, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/2f80c000: FMLSL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLSL2_asimdelem_LH, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const S          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFhm /*FEAT_FHM*/)
    {
        LogFlow(("%018x/%010x: FMLSL2_asimdelem_LH Rd=%#x Rn=%#x H=%u S=%u Rm=%#x M=%u L=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, S, Rm, M, L, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLSL2_asimdelem_LH
        IEM_INSTR_IMPL_A64__FMLSL2_asimdelem_LH(Rd, Rn, H, S, Rm, M, L, sz, Q);
#else
        RT_NOREF(Rd, Rn, H, S, Rm, M, L, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2ea0cc00: FMLSL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLSL2_asimdsame_F, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2ea0cc00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const S          = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFhm /*FEAT_FHM*/)
        {
            LogFlow(("%018x/%010x: FMLSL2_asimdsame_F Rd=%#x Rn=%#x Rm=%#x sz=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, S, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLSL2_asimdsame_F
            IEM_INSTR_IMPL_A64__FMLSL2_asimdsame_F(Rd, Rn, Rm, sz, S, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/0f804000: FMLSL  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLSL_asimdelem_LH, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x0f804000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const S          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFhm /*FEAT_FHM*/)
        {
            LogFlow(("%018x/%010x: FMLSL_asimdelem_LH Rd=%#x Rn=%#x H=%u S=%u Rm=%#x M=%u L=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, S, Rm, M, L, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLSL_asimdelem_LH
            IEM_INSTR_IMPL_A64__FMLSL_asimdelem_LH(Rd, Rn, H, S, Rm, M, L, sz, Q);
#else
            RT_NOREF(Rd, Rn, H, S, Rm, M, L, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0ea0ec00: FMLSL  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLSL_asimdsame_F, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0ea0ec00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const S          = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFhm /*FEAT_FHM*/)
        {
            LogFlow(("%018x/%010x: FMLSL_asimdsame_F Rd=%#x Rn=%#x Rm=%#x sz=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, S, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLSL_asimdsame_F
            IEM_INSTR_IMPL_A64__FMLSL_asimdsame_F(Rd, Rn, Rm, sz, S, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/0f005000: FMLS  <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLS_asimdelem_RH_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMLS_asimdelem_RH_H Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLS_asimdelem_RH_H
        IEM_INSTR_IMPL_A64__FMLS_asimdelem_RH_H(Rd, Rn, H, o2, Rm, M, L, Q);
#else
        RT_NOREF(Rd, Rn, H, o2, Rm, M, L, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80f400/0f805000: FMLS  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLS_asimdelem_R_SD, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80f400)) == UINT32_C(0x0f805000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMLS_asimdelem_R_SD Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLS_asimdelem_R_SD
            IEM_INSTR_IMPL_A64__FMLS_asimdelem_R_SD(Rd, Rn, H, o2, Rm, M, L, sz, Q);
#else
            RT_NOREF(Rd, Rn, H, o2, Rm, M, L, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/0ea0cc00: FMLS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLS_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const op         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMLS_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u op=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, op, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLS_asimdsame_only
        IEM_INSTR_IMPL_A64__FMLS_asimdsame_only(Rd, Rn, Rm, sz, op, Q);
#else
        RT_NOREF(Rd, Rn, Rm, sz, op, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0ec00c00: FMLS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLS_asimdsamefp16_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMLS_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FMLS_asimdsamefp16_only
        IEM_INSTR_IMPL_A64__FMLS_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0f400/5f005000: FMLS  <Hd>, <Hn>, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLS_asisdelem_RH_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMLS_asisdelem_RH_H Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L));
#ifdef IEM_INSTR_IMPL_A64__FMLS_asisdelem_RH_H
        IEM_INSTR_IMPL_A64__FMLS_asisdelem_RH_H(Rd, Rn, H, o2, Rm, M, L);
#else
        RT_NOREF(Rd, Rn, H, o2, Rm, M, L, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80f400/5f805000: FMLS  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMLS_asisdelem_R_SD, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80f400)) == UINT32_C(0x5f805000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMLS_asisdelem_R_SD Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, sz));
#ifdef IEM_INSTR_IMPL_A64__FMLS_asisdelem_R_SD
            IEM_INSTR_IMPL_A64__FMLS_asisdelem_R_SD(Rd, Rn, H, o2, Rm, M, L, sz);
#else
            RT_NOREF(Rd, Rn, H, o2, Rm, M, L, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/6e00ec00: FMMLA  <Vd>.8H, <Vn>.16B, <Vm>.16B
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMMLA_asimd_FP8FP16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x6e00ec00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_F8F16MM*/)
        {
            LogFlow(("%018x/%010x: FMMLA_asimd_FP8FP16 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMMLA_asimd_FP8FP16
            IEM_INSTR_IMPL_A64__FMMLA_asimd_FP8FP16(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/6e80ec00: FMMLA  <Vd>.4S, <Vn>.16B, <Vm>.16B
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMMLA_asimd_FP8FP32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x6e80ec00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_F8F32MM*/)
        {
            LogFlow(("%018x/%010x: FMMLA_asimd_FP8FP32 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMMLA_asimd_FP8FP32
            IEM_INSTR_IMPL_A64__FMMLA_asimd_FP8FP32(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee60000: FMOV  <Wd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_32H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee60000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMOV_32H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FMOV_32H_float2int
            IEM_INSTR_IMPL_A64__FMOV_32H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e260000: FMOV  <Wd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_32S_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e260000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FMOV_32S_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FMOV_32S_float2int
            IEM_INSTR_IMPL_A64__FMOV_32S_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e660000: FMOV  <Xd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_64D_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e660000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FMOV_64D_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FMOV_64D_float2int
            IEM_INSTR_IMPL_A64__FMOV_64D_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ee60000: FMOV  <Xd>, <Hn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_64H_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ee60000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMOV_64H_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FMOV_64H_float2int
            IEM_INSTR_IMPL_A64__FMOV_64H_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9eae0000: FMOV  <Xd>, <Vn>.D[1]
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_64VX_float2int, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMOV_64VX_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FMOV_64VX_float2int
        IEM_INSTR_IMPL_A64__FMOV_64VX_float2int(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e670000: FMOV  <Dd>, <Xn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_D64_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e670000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FMOV_D64_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FMOV_D64_float2int
            IEM_INSTR_IMPL_A64__FMOV_D64_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e604000: FMOV  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_D_floatdp1, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMOV_D_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FMOV_D_floatdp1
        IEM_INSTR_IMPL_A64__FMOV_D_floatdp1(Rd, Rn, opc);
#else
        RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe01fe0/1e601000: FMOV  <Dd>, #<imm>
   Instruction Set: A64  Groups: floatimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_D_floatimm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm8       = (uOpcode >> 13) & 0x000000ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMOV_D_floatimm Rd=%#x imm8=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm8));
#ifdef IEM_INSTR_IMPL_A64__FMOV_D_floatimm
        IEM_INSTR_IMPL_A64__FMOV_D_floatimm(Rd, imm8);
#else
        RT_NOREF(Rd, imm8, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee70000: FMOV  <Hd>, <Wn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_H32_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee70000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMOV_H32_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FMOV_H32_float2int
            IEM_INSTR_IMPL_A64__FMOV_H32_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ee70000: FMOV  <Hd>, <Xn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_H64_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ee70000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMOV_H64_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FMOV_H64_float2int
            IEM_INSTR_IMPL_A64__FMOV_H64_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee04000: FMOV  <Hd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_H_floatdp1, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMOV_H_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FMOV_H_floatdp1
        IEM_INSTR_IMPL_A64__FMOV_H_floatdp1(Rd, Rn, opc);
#else
        RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe01fe0/1ee01000: FMOV  <Hd>, #<imm>
   Instruction Set: A64  Groups: floatimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_H_floatimm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm8       = (uOpcode >> 13) & 0x000000ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMOV_H_floatimm Rd=%#x imm8=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm8));
#ifdef IEM_INSTR_IMPL_A64__FMOV_H_floatimm
        IEM_INSTR_IMPL_A64__FMOV_H_floatimm(Rd, imm8);
#else
        RT_NOREF(Rd, imm8, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e270000: FMOV  <Sd>, <Wn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_S32_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e270000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FMOV_S32_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FMOV_S32_float2int
            IEM_INSTR_IMPL_A64__FMOV_S32_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e204000: FMOV  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_S_floatdp1, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMOV_S_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FMOV_S_floatdp1
        IEM_INSTR_IMPL_A64__FMOV_S_floatdp1(Rd, Rn, opc);
#else
        RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe01fe0/1e201000: FMOV  <Sd>, #<imm>
   Instruction Set: A64  Groups: floatimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_S_floatimm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm8       = (uOpcode >> 13) & 0x000000ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMOV_S_floatimm Rd=%#x imm8=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm8));
#ifdef IEM_INSTR_IMPL_A64__FMOV_S_floatimm
        IEM_INSTR_IMPL_A64__FMOV_S_floatimm(Rd, imm8);
#else
        RT_NOREF(Rd, imm8, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9eaf0000: FMOV  <Vd>.D[1], <Xn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_V64I_float2int, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMOV_V64I_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FMOV_V64I_float2int
        IEM_INSTR_IMPL_A64__FMOV_V64I_float2int(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff8fc00/6f00f400: FMOV  <Vd>.2D, #<imm>
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_asimdimm_D2_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff8fc00)) == UINT32_C(0x6f00f400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const h          = (uOpcode >>  5) & 0x00000001;
        uint32_t const g          = (uOpcode >>  6) & 0x00000001;
        uint32_t const f          = (uOpcode >>  7) & 0x00000001;
        uint32_t const e          = (uOpcode >>  8) & 0x00000001;
        uint32_t const d          = (uOpcode >>  9) & 0x00000001;
        uint32_t const c          = (uOpcode >> 16) & 0x00000001;
        uint32_t const b          = (uOpcode >> 17) & 0x00000001;
        uint32_t const a          = (uOpcode >> 18) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMOV_asimdimm_D2_d Rd=%#x h=%u g=%u f=%u e=%u d=%u c=%u b=%u a=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, c, b, a));
#ifdef IEM_INSTR_IMPL_A64__FMOV_asimdimm_D2_d
            IEM_INSTR_IMPL_A64__FMOV_asimdimm_D2_d(Rd, h, g, f, e, d, c, b, a);
#else
            RT_NOREF(Rd, h, g, f, e, d, c, b, a, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bff8fc00/0f00fc00: FMOV  <Vd>.<T>, #<imm>
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_asimdimm_H_h, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMOV_asimdimm_H_h Rd=%#x h=%u g=%u f=%u e=%u d=%u c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__FMOV_asimdimm_H_h
        IEM_INSTR_IMPL_A64__FMOV_asimdimm_H_h(Rd, h, g, f, e, d, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bff8fc00/0f00f400: FMOV  <Vd>.<T>, #<imm>
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMOV_asimdimm_S_s, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMOV_asimdimm_S_s Rd=%#x h=%u g=%u f=%u e=%u d=%u c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__FMOV_asimdimm_S_s
        IEM_INSTR_IMPL_A64__FMOV_asimdimm_S_s(Rd, h, g, f, e, d, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1f408000: FMSUB  <Dd>, <Dn>, <Dm>, <Da>
   Instruction Set: A64  Groups: floatdp3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMSUB_D_floatdp3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMSUB_D_floatdp3 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMSUB_D_floatdp3
        IEM_INSTR_IMPL_A64__FMSUB_D_floatdp3(Rd, Rn, Ra, Rm);
#else
        RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1fc08000: FMSUB  <Hd>, <Hn>, <Hm>, <Ha>
   Instruction Set: A64  Groups: floatdp3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMSUB_H_floatdp3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x1fc08000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMSUB_H_floatdp3 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMSUB_H_floatdp3
            IEM_INSTR_IMPL_A64__FMSUB_H_floatdp3(Rd, Rn, Ra, Rm);
#else
            RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1f008000: FMSUB  <Sd>, <Sn>, <Sm>, <Sa>
   Instruction Set: A64  Groups: floatdp3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMSUB_S_floatdp3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMSUB_S_floatdp3 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMSUB_S_floatdp3
        IEM_INSTR_IMPL_A64__FMSUB_S_floatdp3(Rd, Rn, Ra, Rm);
#else
        RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/2f009000: FMULX  <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMULX_asimdelem_RH_H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x2f009000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMULX_asimdelem_RH_H Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, Q));
#ifdef IEM_INSTR_IMPL_A64__FMULX_asimdelem_RH_H
            IEM_INSTR_IMPL_A64__FMULX_asimdelem_RH_H(Rd, Rn, H, Rm, M, L, Q);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80f400/2f809000: FMULX  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMULX_asimdelem_R_SD, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80f400)) == UINT32_C(0x2f809000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMULX_asimdelem_R_SD Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FMULX_asimdelem_R_SD
            IEM_INSTR_IMPL_A64__FMULX_asimdelem_R_SD(Rd, Rn, H, Rm, M, L, sz, Q);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/0e20dc00: FMULX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMULX_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMULX_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FMULX_asimdsame_only
        IEM_INSTR_IMPL_A64__FMULX_asimdsame_only(Rd, Rn, Rm, sz, Q);
#else
        RT_NOREF(Rd, Rn, Rm, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e401c00: FMULX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMULX_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e401c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMULX_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FMULX_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FMULX_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0f400/7f009000: FMULX  <Hd>, <Hn>, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMULX_asisdelem_RH_H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0f400)) == UINT32_C(0x7f009000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMULX_asisdelem_RH_H Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L));
#ifdef IEM_INSTR_IMPL_A64__FMULX_asisdelem_RH_H
            IEM_INSTR_IMPL_A64__FMULX_asisdelem_RH_H(Rd, Rn, H, Rm, M, L);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80f400/7f809000: FMULX  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMULX_asisdelem_R_SD, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80f400)) == UINT32_C(0x7f809000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMULX_asisdelem_R_SD Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, sz));
#ifdef IEM_INSTR_IMPL_A64__FMULX_asisdelem_R_SD
            IEM_INSTR_IMPL_A64__FMULX_asisdelem_R_SD(Rd, Rn, H, Rm, M, L, sz);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/5e20dc00: FMULX  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMULX_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMULX_asisdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz));
#ifdef IEM_INSTR_IMPL_A64__FMULX_asisdsame_only
        IEM_INSTR_IMPL_A64__FMULX_asisdsame_only(Rd, Rn, Rm, sz);
#else
        RT_NOREF(Rd, Rn, Rm, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5e401c00: FMULX  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: asisdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMULX_asisdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5e401c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMULX_asisdsamefp16_only Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMULX_asisdsamefp16_only
            IEM_INSTR_IMPL_A64__FMULX_asisdsamefp16_only(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e600800: FMUL  <Dd>, <Dn>, <Dm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMUL_D_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 15) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMUL_D_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMUL_D_floatdp2
        IEM_INSTR_IMPL_A64__FMUL_D_floatdp2(Rd, Rn, op, Rm);
#else
        RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ee00800: FMUL  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMUL_H_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 15) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMUL_H_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMUL_H_floatdp2
        IEM_INSTR_IMPL_A64__FMUL_H_floatdp2(Rd, Rn, op, Rm);
#else
        RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e200800: FMUL  <Sd>, <Sn>, <Sm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMUL_S_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 15) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FMUL_S_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FMUL_S_floatdp2
        IEM_INSTR_IMPL_A64__FMUL_S_floatdp2(Rd, Rn, op, Rm);
#else
        RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/0f009000: FMUL  <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMUL_asimdelem_RH_H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x0f009000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMUL_asimdelem_RH_H Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, Q));
#ifdef IEM_INSTR_IMPL_A64__FMUL_asimdelem_RH_H
            IEM_INSTR_IMPL_A64__FMUL_asimdelem_RH_H(Rd, Rn, H, Rm, M, L, Q);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80f400/0f809000: FMUL  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMUL_asimdelem_R_SD, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80f400)) == UINT32_C(0x0f809000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FMUL_asimdelem_R_SD Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FMUL_asimdelem_R_SD
            IEM_INSTR_IMPL_A64__FMUL_asimdelem_R_SD(Rd, Rn, H, Rm, M, L, sz, Q);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/2e20dc00: FMUL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMUL_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMUL_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FMUL_asimdsame_only
        IEM_INSTR_IMPL_A64__FMUL_asimdsame_only(Rd, Rn, Rm, sz, Q);
#else
        RT_NOREF(Rd, Rn, Rm, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2e401c00: FMUL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMUL_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2e401c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FMUL_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FMUL_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FMUL_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0f400/5f009000: FMUL  <Hd>, <Hn>, <Vm>.H[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMUL_asisdelem_RH_H, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FMUL_asisdelem_RH_H Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L));
#ifdef IEM_INSTR_IMPL_A64__FMUL_asisdelem_RH_H
        IEM_INSTR_IMPL_A64__FMUL_asisdelem_RH_H(Rd, Rn, H, Rm, M, L);
#else
        RT_NOREF(Rd, Rn, H, Rm, M, L, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80f400/5f809000: FMUL  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FMUL_asisdelem_R_SD, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FMUL_asisdelem_R_SD Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, sz));
#ifdef IEM_INSTR_IMPL_A64__FMUL_asisdelem_R_SD
        IEM_INSTR_IMPL_A64__FMUL_asisdelem_R_SD(Rd, Rn, H, Rm, M, L, sz);
#else
        RT_NOREF(Rd, Rn, H, Rm, M, L, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e614000: FNEG  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNEG_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e614000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FNEG_D_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FNEG_D_floatdp1
            IEM_INSTR_IMPL_A64__FNEG_D_floatdp1(Rd, Rn, opc);
#else
            RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee14000: FNEG  <Hd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNEG_H_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee14000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FNEG_H_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FNEG_H_floatdp1
            IEM_INSTR_IMPL_A64__FNEG_H_floatdp1(Rd, Rn, opc);
#else
            RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e214000: FNEG  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNEG_S_floatdp1, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FNEG_S_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FNEG_S_floatdp1
        IEM_INSTR_IMPL_A64__FNEG_S_floatdp1(Rd, Rn, opc);
#else
        RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2ea0f800: FNEG  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNEG_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FNEG_asimdmisc_R Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FNEG_asimdmisc_R
        IEM_INSTR_IMPL_A64__FNEG_asimdmisc_R(Rd, Rn, sz, Q);
#else
        RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2ef8f800: FNEG  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNEG_asimdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FNEG_asimdmiscfp16_R Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__FNEG_asimdmiscfp16_R
        IEM_INSTR_IMPL_A64__FNEG_asimdmiscfp16_R(Rd, Rn, Q);
#else
        RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1f600000: FNMADD  <Dd>, <Dn>, <Dm>, <Da>
   Instruction Set: A64  Groups: floatdp3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNMADD_D_floatdp3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FNMADD_D_floatdp3 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__FNMADD_D_floatdp3
        IEM_INSTR_IMPL_A64__FNMADD_D_floatdp3(Rd, Rn, Ra, Rm);
#else
        RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1fe00000: FNMADD  <Hd>, <Hn>, <Hm>, <Ha>
   Instruction Set: A64  Groups: floatdp3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNMADD_H_floatdp3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FNMADD_H_floatdp3 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__FNMADD_H_floatdp3
        IEM_INSTR_IMPL_A64__FNMADD_H_floatdp3(Rd, Rn, Ra, Rm);
#else
        RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1f200000: FNMADD  <Sd>, <Sn>, <Sm>, <Sa>
   Instruction Set: A64  Groups: floatdp3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNMADD_S_floatdp3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x1f200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FNMADD_S_floatdp3 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__FNMADD_S_floatdp3
            IEM_INSTR_IMPL_A64__FNMADD_S_floatdp3(Rd, Rn, Ra, Rm);
#else
            RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1f608000: FNMSUB  <Dd>, <Dn>, <Dm>, <Da>
   Instruction Set: A64  Groups: floatdp3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNMSUB_D_floatdp3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x1f608000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FNMSUB_D_floatdp3 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__FNMSUB_D_floatdp3
            IEM_INSTR_IMPL_A64__FNMSUB_D_floatdp3(Rd, Rn, Ra, Rm);
#else
            RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1fe08000: FNMSUB  <Hd>, <Hn>, <Hm>, <Ha>
   Instruction Set: A64  Groups: floatdp3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNMSUB_H_floatdp3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FNMSUB_H_floatdp3 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__FNMSUB_H_floatdp3
        IEM_INSTR_IMPL_A64__FNMSUB_H_floatdp3(Rd, Rn, Ra, Rm);
#else
        RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1f208000: FNMSUB  <Sd>, <Sn>, <Sm>, <Sa>
   Instruction Set: A64  Groups: floatdp3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNMSUB_S_floatdp3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x1f208000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FNMSUB_S_floatdp3 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__FNMSUB_S_floatdp3
            IEM_INSTR_IMPL_A64__FNMSUB_S_floatdp3(Rd, Rn, Ra, Rm);
#else
            RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e608800: FNMUL  <Dd>, <Dn>, <Dm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNMUL_D_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 15) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FNMUL_D_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FNMUL_D_floatdp2
        IEM_INSTR_IMPL_A64__FNMUL_D_floatdp2(Rd, Rn, op, Rm);
#else
        RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ee08800: FNMUL  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNMUL_H_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 15) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FNMUL_H_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FNMUL_H_floatdp2
        IEM_INSTR_IMPL_A64__FNMUL_H_floatdp2(Rd, Rn, op, Rm);
#else
        RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e208800: FNMUL  <Sd>, <Sn>, <Sm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FNMUL_S_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 15) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FNMUL_S_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FNMUL_S_floatdp2
        IEM_INSTR_IMPL_A64__FNMUL_S_floatdp2(Rd, Rn, op, Rm);
#else
        RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0ea1d800: FRECPE  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRECPE_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FRECPE_asimdmisc_R Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FRECPE_asimdmisc_R
        IEM_INSTR_IMPL_A64__FRECPE_asimdmisc_R(Rd, Rn, sz, Q);
#else
        RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0ef9d800: FRECPE  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRECPE_asimdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FRECPE_asimdmiscfp16_R Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__FRECPE_asimdmiscfp16_R
        IEM_INSTR_IMPL_A64__FRECPE_asimdmiscfp16_R(Rd, Rn, Q);
#else
        RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/5ea1d800: FRECPE  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRECPE_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FRECPE_asisdmisc_R Rd=%#x Rn=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz));
#ifdef IEM_INSTR_IMPL_A64__FRECPE_asisdmisc_R
        IEM_INSTR_IMPL_A64__FRECPE_asisdmisc_R(Rd, Rn, sz);
#else
        RT_NOREF(Rd, Rn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ef9d800: FRECPE  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRECPE_asisdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FRECPE_asisdmiscfp16_R Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FRECPE_asisdmiscfp16_R
        IEM_INSTR_IMPL_A64__FRECPE_asisdmiscfp16_R(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/0e20fc00: FRECPS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRECPS_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FRECPS_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FRECPS_asimdsame_only
        IEM_INSTR_IMPL_A64__FRECPS_asimdsame_only(Rd, Rn, Rm, sz, Q);
#else
        RT_NOREF(Rd, Rn, Rm, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e403c00: FRECPS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRECPS_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e403c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRECPS_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FRECPS_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FRECPS_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/5e20fc00: FRECPS  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRECPS_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FRECPS_asisdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz));
#ifdef IEM_INSTR_IMPL_A64__FRECPS_asisdsame_only
        IEM_INSTR_IMPL_A64__FRECPS_asisdsame_only(Rd, Rn, Rm, sz);
#else
        RT_NOREF(Rd, Rn, Rm, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5e403c00: FRECPS  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: asisdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRECPS_asisdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5e403c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRECPS_asisdsamefp16_only Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FRECPS_asisdsamefp16_only
            IEM_INSTR_IMPL_A64__FRECPS_asisdsamefp16_only(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/5ea1f800: FRECPX  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRECPX_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FRECPX_asisdmisc_R Rd=%#x Rn=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz));
#ifdef IEM_INSTR_IMPL_A64__FRECPX_asisdmisc_R
        IEM_INSTR_IMPL_A64__FRECPX_asisdmisc_R(Rd, Rn, sz);
#else
        RT_NOREF(Rd, Rn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ef9f800: FRECPX  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRECPX_asisdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FRECPX_asisdmiscfp16_R Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FRECPX_asisdmiscfp16_R
        IEM_INSTR_IMPL_A64__FRECPX_asisdmiscfp16_R(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e68c000: FRINT32X  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINT32X_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e68c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFrintts /*FEAT_FRINTTS*/)
        {
            LogFlow(("%018x/%010x: FRINT32X_D_floatdp1 Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__FRINT32X_D_floatdp1
            IEM_INSTR_IMPL_A64__FRINT32X_D_floatdp1(Rd, Rn, op);
#else
            RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e28c000: FRINT32X  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINT32X_S_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e28c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFrintts /*FEAT_FRINTTS*/)
        {
            LogFlow(("%018x/%010x: FRINT32X_S_floatdp1 Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__FRINT32X_S_floatdp1
            IEM_INSTR_IMPL_A64__FRINT32X_S_floatdp1(Rd, Rn, op);
#else
            RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2e21e800: FRINT32X  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINT32X_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2e21e800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFrintts /*FEAT_FRINTTS*/)
        {
            LogFlow(("%018x/%010x: FRINT32X_asimdmisc_R Rd=%#x Rn=%#x op=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINT32X_asimdmisc_R
            IEM_INSTR_IMPL_A64__FRINT32X_asimdmisc_R(Rd, Rn, op, sz, Q);
#else
            RT_NOREF(Rd, Rn, op, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e684000: FRINT32Z  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINT32Z_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e684000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFrintts /*FEAT_FRINTTS*/)
        {
            LogFlow(("%018x/%010x: FRINT32Z_D_floatdp1 Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__FRINT32Z_D_floatdp1
            IEM_INSTR_IMPL_A64__FRINT32Z_D_floatdp1(Rd, Rn, op);
#else
            RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e284000: FRINT32Z  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINT32Z_S_floatdp1, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 15) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFrintts /*FEAT_FRINTTS*/)
    {
        LogFlow(("%018x/%010x: FRINT32Z_S_floatdp1 Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__FRINT32Z_S_floatdp1
        IEM_INSTR_IMPL_A64__FRINT32Z_S_floatdp1(Rd, Rn, op);
#else
        RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0e21e800: FRINT32Z  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINT32Z_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0e21e800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFrintts /*FEAT_FRINTTS*/)
        {
            LogFlow(("%018x/%010x: FRINT32Z_asimdmisc_R Rd=%#x Rn=%#x op=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINT32Z_asimdmisc_R
            IEM_INSTR_IMPL_A64__FRINT32Z_asimdmisc_R(Rd, Rn, op, sz, Q);
#else
            RT_NOREF(Rd, Rn, op, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e69c000: FRINT64X  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINT64X_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e69c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFrintts /*FEAT_FRINTTS*/)
        {
            LogFlow(("%018x/%010x: FRINT64X_D_floatdp1 Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__FRINT64X_D_floatdp1
            IEM_INSTR_IMPL_A64__FRINT64X_D_floatdp1(Rd, Rn, op);
#else
            RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e29c000: FRINT64X  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINT64X_S_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e29c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFrintts /*FEAT_FRINTTS*/)
        {
            LogFlow(("%018x/%010x: FRINT64X_S_floatdp1 Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__FRINT64X_S_floatdp1
            IEM_INSTR_IMPL_A64__FRINT64X_S_floatdp1(Rd, Rn, op);
#else
            RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2e21f800: FRINT64X  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINT64X_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2e21f800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFrintts /*FEAT_FRINTTS*/)
        {
            LogFlow(("%018x/%010x: FRINT64X_asimdmisc_R Rd=%#x Rn=%#x op=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINT64X_asimdmisc_R
            IEM_INSTR_IMPL_A64__FRINT64X_asimdmisc_R(Rd, Rn, op, sz, Q);
#else
            RT_NOREF(Rd, Rn, op, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e694000: FRINT64Z  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINT64Z_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e694000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFrintts /*FEAT_FRINTTS*/)
        {
            LogFlow(("%018x/%010x: FRINT64Z_D_floatdp1 Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__FRINT64Z_D_floatdp1
            IEM_INSTR_IMPL_A64__FRINT64Z_D_floatdp1(Rd, Rn, op);
#else
            RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e294000: FRINT64Z  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINT64Z_S_floatdp1, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 15) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFrintts /*FEAT_FRINTTS*/)
    {
        LogFlow(("%018x/%010x: FRINT64Z_S_floatdp1 Rd=%#x Rn=%#x op=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op));
#ifdef IEM_INSTR_IMPL_A64__FRINT64Z_S_floatdp1
        IEM_INSTR_IMPL_A64__FRINT64Z_S_floatdp1(Rd, Rn, op);
#else
        RT_NOREF(Rd, Rn, op, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0e21f800: FRINT64Z  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINT64Z_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFrintts /*FEAT_FRINTTS*/)
    {
        LogFlow(("%018x/%010x: FRINT64Z_asimdmisc_R Rd=%#x Rn=%#x op=%u sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINT64Z_asimdmisc_R
        IEM_INSTR_IMPL_A64__FRINT64Z_asimdmisc_R(Rd, Rn, op, sz, Q);
#else
        RT_NOREF(Rd, Rn, op, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e664000: FRINTA  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTA_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e664000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTA_D_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTA_D_floatdp1
            IEM_INSTR_IMPL_A64__FRINTA_D_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee64000: FRINTA  <Hd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTA_H_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee64000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRINTA_H_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTA_H_floatdp1
            IEM_INSTR_IMPL_A64__FRINTA_H_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e264000: FRINTA  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTA_S_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e264000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTA_S_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTA_S_floatdp1
            IEM_INSTR_IMPL_A64__FRINTA_S_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2e218800: FRINTA  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTA_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2e218800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FRINTA_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTA_asimdmisc_R
            IEM_INSTR_IMPL_A64__FRINTA_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2e798800: FRINTA  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTA_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2e798800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRINTA_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTA_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FRINTA_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e67c000: FRINTI  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTI_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e67c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTI_D_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTI_D_floatdp1
            IEM_INSTR_IMPL_A64__FRINTI_D_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee7c000: FRINTI  <Hd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTI_H_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee7c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRINTI_H_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTI_H_floatdp1
            IEM_INSTR_IMPL_A64__FRINTI_H_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e27c000: FRINTI  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTI_S_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e27c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTI_S_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTI_S_floatdp1
            IEM_INSTR_IMPL_A64__FRINTI_S_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2ea19800: FRINTI  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTI_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2ea19800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FRINTI_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTI_asimdmisc_R
            IEM_INSTR_IMPL_A64__FRINTI_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2ef99800: FRINTI  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTI_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2ef99800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRINTI_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTI_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FRINTI_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e654000: FRINTM  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTM_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e654000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTM_D_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTM_D_floatdp1
            IEM_INSTR_IMPL_A64__FRINTM_D_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee54000: FRINTM  <Hd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTM_H_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee54000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRINTM_H_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTM_H_floatdp1
            IEM_INSTR_IMPL_A64__FRINTM_H_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e254000: FRINTM  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTM_S_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e254000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTM_S_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTM_S_floatdp1
            IEM_INSTR_IMPL_A64__FRINTM_S_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0e219800: FRINTM  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTM_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FRINTM_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTM_asimdmisc_R
        IEM_INSTR_IMPL_A64__FRINTM_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
        RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0e799800: FRINTM  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTM_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0e799800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRINTM_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTM_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FRINTM_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e644000: FRINTN  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTN_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e644000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTN_D_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTN_D_floatdp1
            IEM_INSTR_IMPL_A64__FRINTN_D_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee44000: FRINTN  <Hd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTN_H_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee44000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRINTN_H_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTN_H_floatdp1
            IEM_INSTR_IMPL_A64__FRINTN_H_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e244000: FRINTN  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTN_S_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e244000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTN_S_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTN_S_floatdp1
            IEM_INSTR_IMPL_A64__FRINTN_S_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0e218800: FRINTN  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTN_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FRINTN_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTN_asimdmisc_R
        IEM_INSTR_IMPL_A64__FRINTN_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
        RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0e798800: FRINTN  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTN_asimdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FRINTN_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTN_asimdmiscfp16_R
        IEM_INSTR_IMPL_A64__FRINTN_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
        RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e64c000: FRINTP  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTP_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e64c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTP_D_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTP_D_floatdp1
            IEM_INSTR_IMPL_A64__FRINTP_D_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee4c000: FRINTP  <Hd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTP_H_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee4c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRINTP_H_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTP_H_floatdp1
            IEM_INSTR_IMPL_A64__FRINTP_H_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e24c000: FRINTP  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTP_S_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e24c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTP_S_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTP_S_floatdp1
            IEM_INSTR_IMPL_A64__FRINTP_S_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0ea18800: FRINTP  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTP_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0ea18800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FRINTP_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTP_asimdmisc_R
            IEM_INSTR_IMPL_A64__FRINTP_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0ef98800: FRINTP  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTP_asimdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FRINTP_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTP_asimdmiscfp16_R
        IEM_INSTR_IMPL_A64__FRINTP_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
        RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e674000: FRINTX  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTX_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e674000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTX_D_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTX_D_floatdp1
            IEM_INSTR_IMPL_A64__FRINTX_D_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee74000: FRINTX  <Hd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTX_H_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee74000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRINTX_H_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTX_H_floatdp1
            IEM_INSTR_IMPL_A64__FRINTX_H_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e274000: FRINTX  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTX_S_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e274000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTX_S_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTX_S_floatdp1
            IEM_INSTR_IMPL_A64__FRINTX_S_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2e219800: FRINTX  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTX_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FRINTX_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTX_asimdmisc_R
        IEM_INSTR_IMPL_A64__FRINTX_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
        RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2e799800: FRINTX  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTX_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2e799800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRINTX_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTX_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FRINTX_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e65c000: FRINTZ  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTZ_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e65c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTZ_D_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTZ_D_floatdp1
            IEM_INSTR_IMPL_A64__FRINTZ_D_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee5c000: FRINTZ  <Hd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTZ_H_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee5c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRINTZ_H_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTZ_H_floatdp1
            IEM_INSTR_IMPL_A64__FRINTZ_H_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e25c000: FRINTZ  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTZ_S_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e25c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rmode      = (uOpcode >> 15) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FRINTZ_S_floatdp1 Rd=%#x Rn=%#x rmode=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, rmode));
#ifdef IEM_INSTR_IMPL_A64__FRINTZ_S_floatdp1
            IEM_INSTR_IMPL_A64__FRINTZ_S_floatdp1(Rd, Rn, rmode);
#else
            RT_NOREF(Rd, Rn, rmode, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0ea19800: FRINTZ  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTZ_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0ea19800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FRINTZ_asimdmisc_R Rd=%#x Rn=%#x o1=%u sz=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, sz, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTZ_asimdmisc_R
            IEM_INSTR_IMPL_A64__FRINTZ_asimdmisc_R(Rd, Rn, o1, sz, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, sz, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0ef99800: FRINTZ  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRINTZ_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0ef99800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRINTZ_asimdmiscfp16_R Rd=%#x Rn=%#x o1=%u o2=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, o2, Q));
#ifdef IEM_INSTR_IMPL_A64__FRINTZ_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__FRINTZ_asimdmiscfp16_R(Rd, Rn, o1, o2, Q);
#else
            RT_NOREF(Rd, Rn, o1, o2, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2ea1d800: FRSQRTE  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRSQRTE_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FRSQRTE_asimdmisc_R Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FRSQRTE_asimdmisc_R
        IEM_INSTR_IMPL_A64__FRSQRTE_asimdmisc_R(Rd, Rn, sz, Q);
#else
        RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2ef9d800: FRSQRTE  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRSQRTE_asimdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FRSQRTE_asimdmiscfp16_R Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__FRSQRTE_asimdmiscfp16_R
        IEM_INSTR_IMPL_A64__FRSQRTE_asimdmiscfp16_R(Rd, Rn, Q);
#else
        RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7ea1d800: FRSQRTE  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRSQRTE_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FRSQRTE_asisdmisc_R Rd=%#x Rn=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz));
#ifdef IEM_INSTR_IMPL_A64__FRSQRTE_asisdmisc_R
        IEM_INSTR_IMPL_A64__FRSQRTE_asisdmisc_R(Rd, Rn, sz);
#else
        RT_NOREF(Rd, Rn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7ef9d800: FRSQRTE  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRSQRTE_asisdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FRSQRTE_asisdmiscfp16_R Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__FRSQRTE_asisdmiscfp16_R
        IEM_INSTR_IMPL_A64__FRSQRTE_asisdmiscfp16_R(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/0ea0fc00: FRSQRTS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRSQRTS_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x0ea0fc00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FRSQRTS_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FRSQRTS_asimdsame_only
            IEM_INSTR_IMPL_A64__FRSQRTS_asimdsame_only(Rd, Rn, Rm, sz, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0ec03c00: FRSQRTS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRSQRTS_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0ec03c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FRSQRTS_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FRSQRTS_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FRSQRTS_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/5ea0fc00: FRSQRTS  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRSQRTS_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FRSQRTS_asisdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz));
#ifdef IEM_INSTR_IMPL_A64__FRSQRTS_asisdsame_only
        IEM_INSTR_IMPL_A64__FRSQRTS_asisdsame_only(Rd, Rn, Rm, sz);
#else
        RT_NOREF(Rd, Rn, Rm, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5ec03c00: FRSQRTS  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: asisdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FRSQRTS_asisdsamefp16_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FRSQRTS_asisdsamefp16_only Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__FRSQRTS_asisdsamefp16_only
        IEM_INSTR_IMPL_A64__FRSQRTS_asisdsamefp16_only(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e20fc00: FSCALE  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FSCALE_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/ && (size & 2) == 2)
    {
        LogFlow(("%018x/%010x: FSCALE_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__FSCALE_asimdsame_only
        IEM_INSTR_IMPL_A64__FSCALE_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/2ec03c00: FSCALE  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FSCALE_asimdsamefp16_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2ec03c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
        {
            LogFlow(("%018x/%010x: FSCALE_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FSCALE_asimdsamefp16_only
            IEM_INSTR_IMPL_A64__FSCALE_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e61c000: FSQRT  <Dd>, <Dn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FSQRT_D_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e61c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FSQRT_D_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FSQRT_D_floatdp1
            IEM_INSTR_IMPL_A64__FSQRT_D_floatdp1(Rd, Rn, opc);
#else
            RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee1c000: FSQRT  <Hd>, <Hn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FSQRT_H_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee1c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FSQRT_H_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FSQRT_H_floatdp1
            IEM_INSTR_IMPL_A64__FSQRT_H_floatdp1(Rd, Rn, opc);
#else
            RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e21c000: FSQRT  <Sd>, <Sn>
   Instruction Set: A64  Groups: floatdp1, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FSQRT_S_floatdp1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e21c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 15) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: FSQRT_S_floatdp1 Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__FSQRT_S_floatdp1
            IEM_INSTR_IMPL_A64__FSQRT_S_floatdp1(Rd, Rn, opc);
#else
            RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2ea1f800: FSQRT  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FSQRT_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: FSQRT_asimdmisc_R Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FSQRT_asimdmisc_R
        IEM_INSTR_IMPL_A64__FSQRT_asimdmisc_R(Rd, Rn, sz, Q);
#else
        RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2ef9f800: FSQRT  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FSQRT_asimdmiscfp16_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FSQRT_asimdmiscfp16_R Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__FSQRT_asimdmiscfp16_R
        IEM_INSTR_IMPL_A64__FSQRT_asimdmiscfp16_R(Rd, Rn, Q);
#else
        RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e603800: FSUB  <Dd>, <Dn>, <Dm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FSUB_D_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FSUB_D_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FSUB_D_floatdp2
        IEM_INSTR_IMPL_A64__FSUB_D_floatdp2(Rd, Rn, op, Rm);
#else
        RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ee03800: FSUB  <Hd>, <Hn>, <Hm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FSUB_H_floatdp2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ee03800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: FSUB_H_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FSUB_H_floatdp2
            IEM_INSTR_IMPL_A64__FSUB_H_floatdp2(Rd, Rn, op, Rm);
#else
            RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1e203800: FSUB  <Sd>, <Sn>, <Sm>
   Instruction Set: A64  Groups: floatdp2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FSUB_S_floatdp2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: FSUB_S_floatdp2 Rd=%#x Rn=%#x op=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm));
#ifdef IEM_INSTR_IMPL_A64__FSUB_S_floatdp2
        IEM_INSTR_IMPL_A64__FSUB_S_floatdp2(Rd, Rn, op, Rm);
#else
        RT_NOREF(Rd, Rn, op, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfa0fc00/0ea0d400: FSUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FSUB_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x0ea0d400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: FSUB_asimdsame_only Rd=%#x Rn=%#x Rm=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__FSUB_asimdsame_only
            IEM_INSTR_IMPL_A64__FSUB_asimdsame_only(Rd, Rn, Rm, sz, Q);
#else
            RT_NOREF(Rd, Rn, Rm, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0ec01400: FSUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsamefp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_FSUB_asimdsamefp16_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
    {
        LogFlow(("%018x/%010x: FSUB_asimdsamefp16_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__FSUB_asimdsamefp16_only
        IEM_INSTR_IMPL_A64__FSUB_asimdsamefp16_only(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503227f: GCSB  DSYNC
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_GCSB_HD_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503227f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fGcs /*FEAT_GCS*/)
        {
            LogFlow(("%018x/%010x: GCSB_HD_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__GCSB_HD_hints
            IEM_INSTR_IMPL_A64__GCSB_HD_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/d91f0c00: GCSSTR  <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: ldst_gcs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_GCSSTR_64_ldst_gcs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xd91f0c00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fGcs /*FEAT_GCS*/)
        {
            LogFlow(("%018x/%010x: GCSSTR_64_ldst_gcs Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__GCSSTR_64_ldst_gcs
            IEM_INSTR_IMPL_A64__GCSSTR_64_ldst_gcs(Rt, Rn);
#else
            RT_NOREF(Rt, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/d91f1c00: GCSSTTR  <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: ldst_gcs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_GCSSTTR_64_ldst_gcs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fGcs /*FEAT_GCS*/)
    {
        LogFlow(("%018x/%010x: GCSSTTR_64_ldst_gcs Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__GCSSTTR_64_ldst_gcs
        IEM_INSTR_IMPL_A64__GCSSTTR_64_ldst_gcs(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9ac01400: GMI  <Xd>, <Xn|SP>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_GMI_64G_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: GMI_64G_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__GMI_64G_dp_2src
        IEM_INSTR_IMPL_A64__GMI_64G_dp_2src(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffff01f/d503201f: HINT  #<imm>
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_HINT_HM_hints, uint32_t, uOpcode)
{
    uint32_t const op2        = (uOpcode >>  5) & 0x00000007;
    uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
    LogFlow(("%018x/%010x: HINT_HM_hints op2=%u CRm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, op2, CRm));
#ifdef IEM_INSTR_IMPL_A64__HINT_HM_hints
    IEM_INSTR_IMPL_A64__HINT_HM_hints(op2, CRm);
#else
    RT_NOREF(op2, CRm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0001f/d4400000: HLT  #<imm>
   Instruction Set: A64  Groups: exception, control */
FNIEMOP_DEF_1(iemDecodeA64_HLT_EX_exception, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0xd4400000))
    {
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        LogFlow(("%018x/%010x: HLT_EX_exception imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__HLT_EX_exception
        IEM_INSTR_IMPL_A64__HLT_EX_exception(imm16);
#else
        RT_NOREF(imm16, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001f/d4000002: HVC  #<imm>
   Instruction Set: A64  Groups: exception, control */
FNIEMOP_DEF_1(iemDecodeA64_HVC_EX_exception, uint32_t, uOpcode)
{
    uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
    LogFlow(("%018x/%010x: HVC_EX_exception imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__HVC_EX_exception
    IEM_INSTR_IMPL_A64__HVC_EX_exception(imm16);
#else
    RT_NOREF(imm16, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/4e001c00: INS  <Vd>.<Ts>[<index>], <R><n>
   Instruction Set: A64  Groups: asimdins, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_INS_asimdins_IR_r, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: INS_asimdins_IR_r Rd=%#x Rn=%#x imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm5));
#ifdef IEM_INSTR_IMPL_A64__INS_asimdins_IR_r
        IEM_INSTR_IMPL_A64__INS_asimdins_IR_r(Rd, Rn, imm5);
#else
        RT_NOREF(Rd, Rn, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08400/6e000400: INS  <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]
   Instruction Set: A64  Groups: asimdins, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_INS_asimdins_IV_v, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08400)) == UINT32_C(0x6e000400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm4       = (uOpcode >> 11) & 0x0000000f;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: INS_asimdins_IV_v Rd=%#x Rn=%#x imm4=%#x imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm4, imm5));
#ifdef IEM_INSTR_IMPL_A64__INS_asimdins_IV_v
            IEM_INSTR_IMPL_A64__INS_asimdins_IV_v(Rd, Rn, imm4, imm5);
#else
            RT_NOREF(Rd, Rn, imm4, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9ac01000: IRG  <Xd|SP>, <Xn|SP>{, <Xm>}
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_IRG_64I_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac01000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
        {
            LogFlow(("%018x/%010x: IRG_64I_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__IRG_64I_dp_2src
            IEM_INSTR_IMPL_A64__IRG_64I_dp_2src(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffff0ff/d50330df: ISB{  <option> |   #<imm>}
   Instruction Set: A64  Groups: barriers, control */
FNIEMOP_DEF_1(iemDecodeA64_ISB_BI_barriers, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffff0ff)) == UINT32_C(0xd50330df))
    {
        uint32_t const opc        = (uOpcode >>  5) & 0x00000003;
        uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
        LogFlow(("%018x/%010x: ISB_BI_barriers opc=%u CRm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc, CRm));
#ifdef IEM_INSTR_IMPL_A64__ISB_BI_barriers
        IEM_INSTR_IMPL_A64__ISB_BI_barriers(opc, CRm);
#else
        RT_NOREF(opc, CRm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0d40c000: LD1R  { <Vt>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1R_asisdlso_R1, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD1R_asisdlso_R1 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1R_asisdlso_R1
        IEM_INSTR_IMPL_A64__LD1R_asisdlso_R1(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0ddfc000: LD1R  { <Vt>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1R_asisdlsop_R1_i, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD1R_asisdlsop_R1_i Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1R_asisdlsop_R1_i
        IEM_INSTR_IMPL_A64__LD1R_asisdlsop_R1_i(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0dc0c000: LD1R  { <Vt>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1R_asisdlsop_RX1_r, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD1R_asisdlsop_RX1_r Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1R_asisdlsop_RX1_r
        IEM_INSTR_IMPL_A64__LD1R_asisdlsop_RX1_r(Rt, Rn, size, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c407000: LD1  { <Vt>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlse_R1_1v, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c407000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD1_asisdlse_R1_1v Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlse_R1_1v
            IEM_INSTR_IMPL_A64__LD1_asisdlse_R1_1v(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c40a000: LD1  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlse_R2_2v, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD1_asisdlse_R2_2v Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlse_R2_2v
        IEM_INSTR_IMPL_A64__LD1_asisdlse_R2_2v(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c406000: LD1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlse_R3_3v, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD1_asisdlse_R3_3v Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlse_R3_3v
        IEM_INSTR_IMPL_A64__LD1_asisdlse_R3_3v(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c402000: LD1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlse_R4_4v, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD1_asisdlse_R4_4v Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlse_R4_4v
        IEM_INSTR_IMPL_A64__LD1_asisdlse_R4_4v(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0cdf7000: LD1  { <Vt>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsep_I1_i1, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD1_asisdlsep_I1_i1 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsep_I1_i1
        IEM_INSTR_IMPL_A64__LD1_asisdlsep_I1_i1(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0cdfa000: LD1  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsep_I2_i2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0cdfa000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD1_asisdlsep_I2_i2 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsep_I2_i2
            IEM_INSTR_IMPL_A64__LD1_asisdlsep_I2_i2(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0cdf6000: LD1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsep_I3_i3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0cdf6000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD1_asisdlsep_I3_i3 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsep_I3_i3
            IEM_INSTR_IMPL_A64__LD1_asisdlsep_I3_i3(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0cdf2000: LD1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsep_I4_i4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0cdf2000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD1_asisdlsep_I4_i4 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsep_I4_i4
            IEM_INSTR_IMPL_A64__LD1_asisdlsep_I4_i4(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0cc07000: LD1  { <Vt>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsep_R1_r1, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD1_asisdlsep_R1_r1 Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsep_R1_r1
        IEM_INSTR_IMPL_A64__LD1_asisdlsep_R1_r1(Rt, Rn, size, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0cc0a000: LD1  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsep_R2_r2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0cc0a000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: LD1_asisdlsep_R2_r2 Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsep_R2_r2
            IEM_INSTR_IMPL_A64__LD1_asisdlsep_R2_r2(Rt, Rn, size, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0cc06000: LD1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsep_R3_r3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0cc06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: LD1_asisdlsep_R3_r3 Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsep_R3_r3
            IEM_INSTR_IMPL_A64__LD1_asisdlsep_R3_r3(Rt, Rn, size, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0cc02000: LD1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsep_R4_r4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0cc02000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: LD1_asisdlsep_R4_r4 Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsep_R4_r4
            IEM_INSTR_IMPL_A64__LD1_asisdlsep_R4_r4(Rt, Rn, size, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0d400000: LD1  { <Vt>.B }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlso_B1_1b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0d400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD1_asisdlso_B1_1b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlso_B1_1b
            IEM_INSTR_IMPL_A64__LD1_asisdlso_B1_1b(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0d408400: LD1  { <Vt>.D }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlso_D1_1d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD1_asisdlso_D1_1d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlso_D1_1d
        IEM_INSTR_IMPL_A64__LD1_asisdlso_D1_1d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0d404000: LD1  { <Vt>.H }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlso_H1_1h, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD1_asisdlso_H1_1h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlso_H1_1h
        IEM_INSTR_IMPL_A64__LD1_asisdlso_H1_1h(Rt, Rn, size, S, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0d408000: LD1  { <Vt>.S }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlso_S1_1s, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD1_asisdlso_S1_1s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlso_S1_1s
        IEM_INSTR_IMPL_A64__LD1_asisdlso_S1_1s(Rt, Rn, S, Q);
#else
        RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0ddf0000: LD1  { <Vt>.B }[<index>], [<Xn|SP>], #1
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsop_B1_i1b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0ddf0000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD1_asisdlsop_B1_i1b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsop_B1_i1b
            IEM_INSTR_IMPL_A64__LD1_asisdlsop_B1_i1b(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e000/0dc00000: LD1  { <Vt>.B }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsop_BX1_r1b, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD1_asisdlsop_BX1_r1b Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsop_BX1_r1b
        IEM_INSTR_IMPL_A64__LD1_asisdlsop_BX1_r1b(Rt, Rn, size, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0ddf8400: LD1  { <Vt>.D }[<index>], [<Xn|SP>], #8
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsop_D1_i1d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD1_asisdlsop_D1_i1d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsop_D1_i1d
        IEM_INSTR_IMPL_A64__LD1_asisdlsop_D1_i1d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0dc08400: LD1  { <Vt>.D }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsop_DX1_r1d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD1_asisdlsop_DX1_r1d Rt=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsop_DX1_r1d
        IEM_INSTR_IMPL_A64__LD1_asisdlsop_DX1_r1d(Rt, Rn, Rm, Q);
#else
        RT_NOREF(Rt, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0ddf4000: LD1  { <Vt>.H }[<index>], [<Xn|SP>], #2
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsop_H1_i1h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0ddf4000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD1_asisdlsop_H1_i1h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsop_H1_i1h
            IEM_INSTR_IMPL_A64__LD1_asisdlsop_H1_i1h(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e400/0dc04000: LD1  { <Vt>.H }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsop_HX1_r1h, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD1_asisdlsop_HX1_r1h Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsop_HX1_r1h
        IEM_INSTR_IMPL_A64__LD1_asisdlsop_HX1_r1h(Rt, Rn, size, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0ddf8000: LD1  { <Vt>.S }[<index>], [<Xn|SP>], #4
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsop_S1_i1s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0ddf8000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD1_asisdlsop_S1_i1s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsop_S1_i1s
            IEM_INSTR_IMPL_A64__LD1_asisdlsop_S1_i1s(Rt, Rn, S, Q);
#else
            RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0ec00/0dc08000: LD1  { <Vt>.S }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD1_asisdlsop_SX1_r1s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0ec00)) == UINT32_C(0x0dc08000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: LD1_asisdlsop_SX1_r1s Rt=%#x Rn=%#x S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD1_asisdlsop_SX1_r1s
            IEM_INSTR_IMPL_A64__LD1_asisdlsop_SX1_r1s(Rt, Rn, S, Rm, Q);
#else
            RT_NOREF(Rt, Rn, S, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0d60c000: LD2R  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2R_asisdlso_R2, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD2R_asisdlso_R2 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2R_asisdlso_R2
        IEM_INSTR_IMPL_A64__LD2R_asisdlso_R2(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0dffc000: LD2R  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2R_asisdlsop_R2_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0dffc000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD2R_asisdlsop_R2_i Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2R_asisdlsop_R2_i
            IEM_INSTR_IMPL_A64__LD2R_asisdlsop_R2_i(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0de0c000: LD2R  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2R_asisdlsop_RX2_r, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD2R_asisdlsop_RX2_r Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2R_asisdlsop_RX2_r
        IEM_INSTR_IMPL_A64__LD2R_asisdlsop_RX2_r(Rt, Rn, size, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c408000: LD2  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlse_R2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c408000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD2_asisdlse_R2 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlse_R2
            IEM_INSTR_IMPL_A64__LD2_asisdlse_R2(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0cdf8000: LD2  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlsep_I2_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0cdf8000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD2_asisdlsep_I2_i Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlsep_I2_i
            IEM_INSTR_IMPL_A64__LD2_asisdlsep_I2_i(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0cc08000: LD2  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlsep_R2_r, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0cc08000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: LD2_asisdlsep_R2_r Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlsep_R2_r
            IEM_INSTR_IMPL_A64__LD2_asisdlsep_R2_r(Rt, Rn, size, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0d600000: LD2  { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlso_B2_2b, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD2_asisdlso_B2_2b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlso_B2_2b
        IEM_INSTR_IMPL_A64__LD2_asisdlso_B2_2b(Rt, Rn, size, S, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0d608400: LD2  { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlso_D2_2d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD2_asisdlso_D2_2d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlso_D2_2d
        IEM_INSTR_IMPL_A64__LD2_asisdlso_D2_2d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0d604000: LD2  { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlso_H2_2h, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD2_asisdlso_H2_2h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlso_H2_2h
        IEM_INSTR_IMPL_A64__LD2_asisdlso_H2_2h(Rt, Rn, size, S, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0d608000: LD2  { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlso_S2_2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0d608000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD2_asisdlso_S2_2s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlso_S2_2s
            IEM_INSTR_IMPL_A64__LD2_asisdlso_S2_2s(Rt, Rn, S, Q);
#else
            RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0dff0000: LD2  { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], #2
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlsop_B2_i2b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0dff0000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD2_asisdlsop_B2_i2b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlsop_B2_i2b
            IEM_INSTR_IMPL_A64__LD2_asisdlsop_B2_i2b(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e000/0de00000: LD2  { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlsop_BX2_r2b, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD2_asisdlsop_BX2_r2b Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlsop_BX2_r2b
        IEM_INSTR_IMPL_A64__LD2_asisdlsop_BX2_r2b(Rt, Rn, size, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0dff8400: LD2  { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], #16
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlsop_D2_i2d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD2_asisdlsop_D2_i2d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlsop_D2_i2d
        IEM_INSTR_IMPL_A64__LD2_asisdlsop_D2_i2d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0de08400: LD2  { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlsop_DX2_r2d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD2_asisdlsop_DX2_r2d Rt=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlsop_DX2_r2d
        IEM_INSTR_IMPL_A64__LD2_asisdlsop_DX2_r2d(Rt, Rn, Rm, Q);
#else
        RT_NOREF(Rt, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0dff4000: LD2  { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], #4
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlsop_H2_i2h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0dff4000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD2_asisdlsop_H2_i2h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlsop_H2_i2h
            IEM_INSTR_IMPL_A64__LD2_asisdlsop_H2_i2h(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e400/0de04000: LD2  { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlsop_HX2_r2h, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD2_asisdlsop_HX2_r2h Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlsop_HX2_r2h
        IEM_INSTR_IMPL_A64__LD2_asisdlsop_HX2_r2h(Rt, Rn, size, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0dff8000: LD2  { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], #8
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlsop_S2_i2s, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD2_asisdlsop_S2_i2s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlsop_S2_i2s
        IEM_INSTR_IMPL_A64__LD2_asisdlsop_S2_i2s(Rt, Rn, S, Q);
#else
        RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0ec00/0de08000: LD2  { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD2_asisdlsop_SX2_r2s, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD2_asisdlsop_SX2_r2s Rt=%#x Rn=%#x S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD2_asisdlsop_SX2_r2s
        IEM_INSTR_IMPL_A64__LD2_asisdlsop_SX2_r2s(Rt, Rn, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0d40e000: LD3R  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3R_asisdlso_R3, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD3R_asisdlso_R3 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3R_asisdlso_R3
        IEM_INSTR_IMPL_A64__LD3R_asisdlso_R3(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0ddfe000: LD3R  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3R_asisdlsop_R3_i, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD3R_asisdlsop_R3_i Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3R_asisdlsop_R3_i
        IEM_INSTR_IMPL_A64__LD3R_asisdlsop_R3_i(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0dc0e000: LD3R  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3R_asisdlsop_RX3_r, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD3R_asisdlsop_RX3_r Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3R_asisdlsop_RX3_r
        IEM_INSTR_IMPL_A64__LD3R_asisdlsop_RX3_r(Rt, Rn, size, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c404000: LD3  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlse_R3, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD3_asisdlse_R3 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlse_R3
        IEM_INSTR_IMPL_A64__LD3_asisdlse_R3(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0cdf4000: LD3  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlsep_I3_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0cdf4000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD3_asisdlsep_I3_i Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlsep_I3_i
            IEM_INSTR_IMPL_A64__LD3_asisdlsep_I3_i(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0cc04000: LD3  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlsep_R3_r, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0cc04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: LD3_asisdlsep_R3_r Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlsep_R3_r
            IEM_INSTR_IMPL_A64__LD3_asisdlsep_R3_r(Rt, Rn, size, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0d402000: LD3  { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlso_B3_3b, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD3_asisdlso_B3_3b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlso_B3_3b
        IEM_INSTR_IMPL_A64__LD3_asisdlso_B3_3b(Rt, Rn, size, S, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0d40a400: LD3  { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlso_D3_3d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD3_asisdlso_D3_3d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlso_D3_3d
        IEM_INSTR_IMPL_A64__LD3_asisdlso_D3_3d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0d406000: LD3  { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlso_H3_3h, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD3_asisdlso_H3_3h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlso_H3_3h
        IEM_INSTR_IMPL_A64__LD3_asisdlso_H3_3h(Rt, Rn, size, S, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0d40a000: LD3  { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlso_S3_3s, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD3_asisdlso_S3_3s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlso_S3_3s
        IEM_INSTR_IMPL_A64__LD3_asisdlso_S3_3s(Rt, Rn, S, Q);
#else
        RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0ddf2000: LD3  { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], #3
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlsop_B3_i3b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0ddf2000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD3_asisdlsop_B3_i3b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlsop_B3_i3b
            IEM_INSTR_IMPL_A64__LD3_asisdlsop_B3_i3b(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e000/0dc02000: LD3  { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlsop_BX3_r3b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e000)) == UINT32_C(0x0dc02000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: LD3_asisdlsop_BX3_r3b Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlsop_BX3_r3b
            IEM_INSTR_IMPL_A64__LD3_asisdlsop_BX3_r3b(Rt, Rn, size, S, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0ddfa400: LD3  { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], #24
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlsop_D3_i3d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD3_asisdlsop_D3_i3d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlsop_D3_i3d
        IEM_INSTR_IMPL_A64__LD3_asisdlsop_D3_i3d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0dc0a400: LD3  { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlsop_DX3_r3d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD3_asisdlsop_DX3_r3d Rt=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlsop_DX3_r3d
        IEM_INSTR_IMPL_A64__LD3_asisdlsop_DX3_r3d(Rt, Rn, Rm, Q);
#else
        RT_NOREF(Rt, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0ddf6000: LD3  { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], #6
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlsop_H3_i3h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0ddf6000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD3_asisdlsop_H3_i3h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlsop_H3_i3h
            IEM_INSTR_IMPL_A64__LD3_asisdlsop_H3_i3h(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e400/0dc06000: LD3  { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlsop_HX3_r3h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e400)) == UINT32_C(0x0dc06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: LD3_asisdlsop_HX3_r3h Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlsop_HX3_r3h
            IEM_INSTR_IMPL_A64__LD3_asisdlsop_HX3_r3h(Rt, Rn, size, S, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0ddfa000: LD3  { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], #12
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlsop_S3_i3s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0ddfa000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD3_asisdlsop_S3_i3s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlsop_S3_i3s
            IEM_INSTR_IMPL_A64__LD3_asisdlsop_S3_i3s(Rt, Rn, S, Q);
#else
            RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0ec00/0dc0a000: LD3  { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD3_asisdlsop_SX3_r3s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0ec00)) == UINT32_C(0x0dc0a000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: LD3_asisdlsop_SX3_r3s Rt=%#x Rn=%#x S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD3_asisdlsop_SX3_r3s
            IEM_INSTR_IMPL_A64__LD3_asisdlsop_SX3_r3s(Rt, Rn, S, Rm, Q);
#else
            RT_NOREF(Rt, Rn, S, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0d60e000: LD4R  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4R_asisdlso_R4, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD4R_asisdlso_R4 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4R_asisdlso_R4
        IEM_INSTR_IMPL_A64__LD4R_asisdlso_R4(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0dffe000: LD4R  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4R_asisdlsop_R4_i, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD4R_asisdlsop_R4_i Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4R_asisdlsop_R4_i
        IEM_INSTR_IMPL_A64__LD4R_asisdlsop_R4_i(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0de0e000: LD4R  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4R_asisdlsop_RX4_r, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD4R_asisdlsop_RX4_r Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4R_asisdlsop_RX4_r
        IEM_INSTR_IMPL_A64__LD4R_asisdlsop_RX4_r(Rt, Rn, size, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c400000: LD4  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlse_R4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD4_asisdlse_R4 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlse_R4
            IEM_INSTR_IMPL_A64__LD4_asisdlse_R4(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0cdf0000: LD4  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlsep_I4_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0cdf0000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD4_asisdlsep_I4_i Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlsep_I4_i
            IEM_INSTR_IMPL_A64__LD4_asisdlsep_I4_i(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0cc00000: LD4  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlsep_R4_r, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD4_asisdlsep_R4_r Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlsep_R4_r
        IEM_INSTR_IMPL_A64__LD4_asisdlsep_R4_r(Rt, Rn, size, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0d602000: LD4  { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlso_B4_4b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0d602000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD4_asisdlso_B4_4b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlso_B4_4b
            IEM_INSTR_IMPL_A64__LD4_asisdlso_B4_4b(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0d60a400: LD4  { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlso_D4_4d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0d60a400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD4_asisdlso_D4_4d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlso_D4_4d
            IEM_INSTR_IMPL_A64__LD4_asisdlso_D4_4d(Rt, Rn, Q);
#else
            RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0d606000: LD4  { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlso_H4_4h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0d606000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: LD4_asisdlso_H4_4h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlso_H4_4h
            IEM_INSTR_IMPL_A64__LD4_asisdlso_H4_4h(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0d60a000: LD4  { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlso_S4_4s, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD4_asisdlso_S4_4s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlso_S4_4s
        IEM_INSTR_IMPL_A64__LD4_asisdlso_S4_4s(Rt, Rn, S, Q);
#else
        RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0dff2000: LD4  { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlsop_B4_i4b, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD4_asisdlsop_B4_i4b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlsop_B4_i4b
        IEM_INSTR_IMPL_A64__LD4_asisdlsop_B4_i4b(Rt, Rn, size, S, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e000/0de02000: LD4  { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlsop_BX4_r4b, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD4_asisdlsop_BX4_r4b Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlsop_BX4_r4b
        IEM_INSTR_IMPL_A64__LD4_asisdlsop_BX4_r4b(Rt, Rn, size, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0dffa400: LD4  { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlsop_D4_i4d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD4_asisdlsop_D4_i4d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlsop_D4_i4d
        IEM_INSTR_IMPL_A64__LD4_asisdlsop_D4_i4d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0de0a400: LD4  { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlsop_DX4_r4d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD4_asisdlsop_DX4_r4d Rt=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlsop_DX4_r4d
        IEM_INSTR_IMPL_A64__LD4_asisdlsop_DX4_r4d(Rt, Rn, Rm, Q);
#else
        RT_NOREF(Rt, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0dff6000: LD4  { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlsop_H4_i4h, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD4_asisdlsop_H4_i4h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlsop_H4_i4h
        IEM_INSTR_IMPL_A64__LD4_asisdlsop_H4_i4h(Rt, Rn, size, S, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e400/0de06000: LD4  { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlsop_HX4_r4h, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD4_asisdlsop_HX4_r4h Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlsop_HX4_r4h
        IEM_INSTR_IMPL_A64__LD4_asisdlsop_HX4_r4h(Rt, Rn, size, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0dffa000: LD4  { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlsop_S4_i4s, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: LD4_asisdlsop_S4_i4s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlsop_S4_i4s
        IEM_INSTR_IMPL_A64__LD4_asisdlsop_S4_i4s(Rt, Rn, S, Q);
#else
        RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0ec00/0de0a000: LD4  { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD4_asisdlsop_SX4_r4s, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: LD4_asisdlsop_SX4_r4s Rt=%#x Rn=%#x S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__LD4_asisdlsop_SX4_r4s
        IEM_INSTR_IMPL_A64__LD4_asisdlsop_SX4_r4s(Rt, Rn, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/f83fd000: LD64B  <Xt>, [<Xn|SP>{ , #0}]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LD64B_64L_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLs64 /*FEAT_LS64*/)
    {
        LogFlow(("%018x/%010x: LD64B_64L_memop Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LD64B_64L_memop
        IEM_INSTR_IMPL_A64__LD64B_64L_memop(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38a00000: LDADDAB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDAB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38a00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDADDAB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDAB_32_memop
            IEM_INSTR_IMPL_A64__LDADDAB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78a00000: LDADDAH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDAH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78a00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDADDAH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDAH_32_memop
            IEM_INSTR_IMPL_A64__LDADDAH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38e00000: LDADDALB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDALB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDADDALB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDALB_32_memop
        IEM_INSTR_IMPL_A64__LDADDALB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78e00000: LDADDALH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDALH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78e00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDADDALH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDALH_32_memop
            IEM_INSTR_IMPL_A64__LDADDALH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8e00000: LDADDAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDAL_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDADDAL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDAL_32_memop
        IEM_INSTR_IMPL_A64__LDADDAL_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8e00000: LDADDAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDAL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8e00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDADDAL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDAL_64_memop
            IEM_INSTR_IMPL_A64__LDADDAL_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8a00000: LDADDA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDA_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8a00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDADDA_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDA_32_memop
            IEM_INSTR_IMPL_A64__LDADDA_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8a00000: LDADDA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDA_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8a00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDADDA_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDA_64_memop
            IEM_INSTR_IMPL_A64__LDADDA_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38200000: LDADDB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDADDB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDB_32_memop
        IEM_INSTR_IMPL_A64__LDADDB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78200000: LDADDH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78200000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDADDH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDH_32_memop
            IEM_INSTR_IMPL_A64__LDADDH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38600000: LDADDLB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDLB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38600000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDADDLB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDLB_32_memop
            IEM_INSTR_IMPL_A64__LDADDLB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78600000: LDADDLH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDLH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78600000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDADDLH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDLH_32_memop
            IEM_INSTR_IMPL_A64__LDADDLH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8600000: LDADDL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDL_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8600000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDADDL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDL_32_memop
            IEM_INSTR_IMPL_A64__LDADDL_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8600000: LDADDL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADDL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8600000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDADDL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADDL_64_memop
            IEM_INSTR_IMPL_A64__LDADDL_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8200000: LDADD  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADD_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDADD_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADD_32_memop
        IEM_INSTR_IMPL_A64__LDADD_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8200000: LDADD  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDADD_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8200000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDADD_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDADD_64_memop
            IEM_INSTR_IMPL_A64__LDADD_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0d418400: LDAP1  { <Vt>.D }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAP1_asisdlso_D1, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: LDAP1_asisdlso_D1 Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__LDAP1_asisdlso_D1
        IEM_INSTR_IMPL_A64__LDAP1_asisdlso_D1(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/38bfc000: LDAPRB  <Wt>, [<Xn|SP>{ , #0}]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPRB_32L_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc /*FEAT_LRCPC*/)
    {
        LogFlow(("%018x/%010x: LDAPRB_32L_memop Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDAPRB_32L_memop
        IEM_INSTR_IMPL_A64__LDAPRB_32L_memop(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/78bfc000: LDAPRH  <Wt>, [<Xn|SP>{ , #0}]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPRH_32L_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc /*FEAT_LRCPC*/)
    {
        LogFlow(("%018x/%010x: LDAPRH_32L_memop Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDAPRH_32L_memop
        IEM_INSTR_IMPL_A64__LDAPRH_32L_memop(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/99c00800: LDAPR  <Wt>, [<Xn|SP>], #4
   Instruction Set: A64  Groups: ldapstl_writeback, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPR_32L_ldapstl_writeback, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: LDAPR_32L_ldapstl_writeback Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDAPR_32L_ldapstl_writeback
        IEM_INSTR_IMPL_A64__LDAPR_32L_ldapstl_writeback(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/b8bfc000: LDAPR  <Wt>, [<Xn|SP>{ , #0}]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPR_32L_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc /*FEAT_LRCPC*/)
    {
        LogFlow(("%018x/%010x: LDAPR_32L_memop Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDAPR_32L_memop
        IEM_INSTR_IMPL_A64__LDAPR_32L_memop(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/d9c00800: LDAPR  <Xt>, [<Xn|SP>], #8
   Instruction Set: A64  Groups: ldapstl_writeback, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPR_64L_ldapstl_writeback, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xd9c00800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
        {
            LogFlow(("%018x/%010x: LDAPR_64L_ldapstl_writeback Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDAPR_64L_ldapstl_writeback
            IEM_INSTR_IMPL_A64__LDAPR_64L_ldapstl_writeback(Rt, Rn);
#else
            RT_NOREF(Rt, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/f8bfc000: LDAPR  <Xt>, [<Xn|SP>{ , #0}]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPR_64L_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc /*FEAT_LRCPC*/)
    {
        LogFlow(("%018x/%010x: LDAPR_64L_memop Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDAPR_64L_memop
        IEM_INSTR_IMPL_A64__LDAPR_64L_memop(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/19400000: LDAPURB  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPURB_32_ldapstl_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
    {
        LogFlow(("%018x/%010x: LDAPURB_32_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPURB_32_ldapstl_unscaled
        IEM_INSTR_IMPL_A64__LDAPURB_32_ldapstl_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/59400000: LDAPURH  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPURH_32_ldapstl_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
    {
        LogFlow(("%018x/%010x: LDAPURH_32_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPURH_32_ldapstl_unscaled
        IEM_INSTR_IMPL_A64__LDAPURH_32_ldapstl_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/19c00000: LDAPURSB  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPURSB_32_ldapstl_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
    {
        LogFlow(("%018x/%010x: LDAPURSB_32_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPURSB_32_ldapstl_unscaled
        IEM_INSTR_IMPL_A64__LDAPURSB_32_ldapstl_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/19800000: LDAPURSB  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPURSB_64_ldapstl_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x19800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
        {
            LogFlow(("%018x/%010x: LDAPURSB_64_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPURSB_64_ldapstl_unscaled
            IEM_INSTR_IMPL_A64__LDAPURSB_64_ldapstl_unscaled(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/59c00000: LDAPURSH  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPURSH_32_ldapstl_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x59c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
        {
            LogFlow(("%018x/%010x: LDAPURSH_32_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPURSH_32_ldapstl_unscaled
            IEM_INSTR_IMPL_A64__LDAPURSH_32_ldapstl_unscaled(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/59800000: LDAPURSH  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPURSH_64_ldapstl_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x59800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
        {
            LogFlow(("%018x/%010x: LDAPURSH_64_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPURSH_64_ldapstl_unscaled
            IEM_INSTR_IMPL_A64__LDAPURSH_64_ldapstl_unscaled(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/99800000: LDAPURSW  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPURSW_64_ldapstl_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x99800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
        {
            LogFlow(("%018x/%010x: LDAPURSW_64_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPURSW_64_ldapstl_unscaled
            IEM_INSTR_IMPL_A64__LDAPURSW_64_ldapstl_unscaled(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/99400000: LDAPUR  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPUR_32_ldapstl_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
    {
        LogFlow(("%018x/%010x: LDAPUR_32_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPUR_32_ldapstl_unscaled
        IEM_INSTR_IMPL_A64__LDAPUR_32_ldapstl_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9400000: LDAPUR  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPUR_64_ldapstl_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
    {
        LogFlow(("%018x/%010x: LDAPUR_64_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPUR_64_ldapstl_unscaled
        IEM_INSTR_IMPL_A64__LDAPUR_64_ldapstl_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/1d400800: LDAPUR  <Bt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_simd, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPUR_B_ldapstl_simd, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: LDAPUR_B_ldapstl_simd Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPUR_B_ldapstl_simd
        IEM_INSTR_IMPL_A64__LDAPUR_B_ldapstl_simd(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/dd400800: LDAPUR  <Dt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_simd, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPUR_D_ldapstl_simd, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xdd400800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
        {
            LogFlow(("%018x/%010x: LDAPUR_D_ldapstl_simd Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPUR_D_ldapstl_simd
            IEM_INSTR_IMPL_A64__LDAPUR_D_ldapstl_simd(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/5d400800: LDAPUR  <Ht>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_simd, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPUR_H_ldapstl_simd, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x5d400800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
        {
            LogFlow(("%018x/%010x: LDAPUR_H_ldapstl_simd Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPUR_H_ldapstl_simd
            IEM_INSTR_IMPL_A64__LDAPUR_H_ldapstl_simd(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/1dc00800: LDAPUR  <Qt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_simd, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPUR_Q_ldapstl_simd, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: LDAPUR_Q_ldapstl_simd Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPUR_Q_ldapstl_simd
        IEM_INSTR_IMPL_A64__LDAPUR_Q_ldapstl_simd(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/9d400800: LDAPUR  <St>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_simd, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAPUR_S_ldapstl_simd, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: LDAPUR_S_ldapstl_simd Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDAPUR_S_ldapstl_simd
        IEM_INSTR_IMPL_A64__LDAPUR_S_ldapstl_simd(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/08dffc00: LDARB  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDARB_LR32_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: LDARB_LR32_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDARB_LR32_ldstord
    IEM_INSTR_IMPL_A64__LDARB_LR32_ldstord(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/48dffc00: LDARH  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDARH_LR32_ldstord, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x48dffc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        LogFlow(("%018x/%010x: LDARH_LR32_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDARH_LR32_ldstord
        IEM_INSTR_IMPL_A64__LDARH_LR32_ldstord(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/88dffc00: LDAR  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAR_LR32_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: LDAR_LR32_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDAR_LR32_ldstord
    IEM_INSTR_IMPL_A64__LDAR_LR32_ldstord(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/c8dffc00: LDAR  <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAR_LR64_ldstord, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xc8dffc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        LogFlow(("%018x/%010x: LDAR_LR64_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDAR_LR64_ldstord
        IEM_INSTR_IMPL_A64__LDAR_LR64_ldstord(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/895ffc00: LDATXR  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDATXR_LR32_ldstexclr_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDATXR_LR32_ldstexclr_unpriv Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDATXR_LR32_ldstexclr_unpriv
        IEM_INSTR_IMPL_A64__LDATXR_LR32_ldstexclr_unpriv(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/c95ffc00: LDATXR  <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDATXR_LR64_ldstexclr_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDATXR_LR64_ldstexclr_unpriv Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDATXR_LR64_ldstexclr_unpriv
        IEM_INSTR_IMPL_A64__LDATXR_LR64_ldstexclr_unpriv(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff8000/887f8000: LDAXP  <Wt1>, <Wt2>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAXP_LP32_ldstexclp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff8000)) == UINT32_C(0x887f8000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        LogFlow(("%018x/%010x: LDAXP_LP32_ldstexclp Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDAXP_LP32_ldstexclp
        IEM_INSTR_IMPL_A64__LDAXP_LP32_ldstexclp(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff8000/c87f8000: LDAXP  <Xt1>, <Xt2>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAXP_LP64_ldstexclp, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    LogFlow(("%018x/%010x: LDAXP_LP64_ldstexclp Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDAXP_LP64_ldstexclp
    IEM_INSTR_IMPL_A64__LDAXP_LP64_ldstexclp(Rt, Rn, Rt2);
#else
    RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/085ffc00: LDAXRB  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAXRB_LR32_ldstexclr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: LDAXRB_LR32_ldstexclr Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDAXRB_LR32_ldstexclr
    IEM_INSTR_IMPL_A64__LDAXRB_LR32_ldstexclr(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/485ffc00: LDAXRH  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAXRH_LR32_ldstexclr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: LDAXRH_LR32_ldstexclr Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDAXRH_LR32_ldstexclr
    IEM_INSTR_IMPL_A64__LDAXRH_LR32_ldstexclr(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/885ffc00: LDAXR  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAXR_LR32_ldstexclr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: LDAXR_LR32_ldstexclr Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDAXR_LR32_ldstexclr
    IEM_INSTR_IMPL_A64__LDAXR_LR32_ldstexclr(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/c85ffc00: LDAXR  <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDAXR_LR64_ldstexclr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: LDAXR_LR64_ldstexclr Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDAXR_LR64_ldstexclr
    IEM_INSTR_IMPL_A64__LDAXR_LR64_ldstexclr(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/3ce00000: LDBFADDAL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFADDAL_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDBFADDAL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFADDAL_16
        IEM_INSTR_IMPL_A64__LDBFADDAL_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3ca00000: LDBFADDA  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFADDA_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3ca00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDBFADDA_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFADDA_16
            IEM_INSTR_IMPL_A64__LDBFADDA_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3c600000: LDBFADDL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFADDL_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3c600000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDBFADDL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFADDL_16
            IEM_INSTR_IMPL_A64__LDBFADDL_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3c200000: LDBFADD  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFADD_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDBFADD_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFADD_16
        IEM_INSTR_IMPL_A64__LDBFADD_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3ce04000: LDBFMAXAL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMAXAL_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3ce04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDBFMAXAL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMAXAL_16
            IEM_INSTR_IMPL_A64__LDBFMAXAL_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3ca04000: LDBFMAXA  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMAXA_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3ca04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDBFMAXA_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMAXA_16
            IEM_INSTR_IMPL_A64__LDBFMAXA_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3c604000: LDBFMAXL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMAXL_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3c604000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDBFMAXL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMAXL_16
            IEM_INSTR_IMPL_A64__LDBFMAXL_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3ce06000: LDBFMAXNMAL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMAXNMAL_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3ce06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDBFMAXNMAL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMAXNMAL_16
            IEM_INSTR_IMPL_A64__LDBFMAXNMAL_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3ca06000: LDBFMAXNMA  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMAXNMA_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3ca06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDBFMAXNMA_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMAXNMA_16
            IEM_INSTR_IMPL_A64__LDBFMAXNMA_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3c606000: LDBFMAXNML  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMAXNML_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3c606000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDBFMAXNML_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMAXNML_16
            IEM_INSTR_IMPL_A64__LDBFMAXNML_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3c206000: LDBFMAXNM  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMAXNM_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDBFMAXNM_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMAXNM_16
        IEM_INSTR_IMPL_A64__LDBFMAXNM_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3c204000: LDBFMAX  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMAX_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDBFMAX_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMAX_16
        IEM_INSTR_IMPL_A64__LDBFMAX_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3ce05000: LDBFMINAL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMINAL_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDBFMINAL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMINAL_16
        IEM_INSTR_IMPL_A64__LDBFMINAL_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3ca05000: LDBFMINA  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMINA_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDBFMINA_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMINA_16
        IEM_INSTR_IMPL_A64__LDBFMINA_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3c605000: LDBFMINL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMINL_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDBFMINL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMINL_16
        IEM_INSTR_IMPL_A64__LDBFMINL_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3ce07000: LDBFMINNMAL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMINNMAL_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDBFMINNMAL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMINNMAL_16
        IEM_INSTR_IMPL_A64__LDBFMINNMAL_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3ca07000: LDBFMINNMA  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMINNMA_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDBFMINNMA_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMINNMA_16
        IEM_INSTR_IMPL_A64__LDBFMINNMA_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3c607000: LDBFMINNML  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMINNML_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDBFMINNML_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMINNML_16
        IEM_INSTR_IMPL_A64__LDBFMINNML_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3c207000: LDBFMINNM  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMINNM_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3c207000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDBFMINNM_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMINNM_16
            IEM_INSTR_IMPL_A64__LDBFMINNM_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3c205000: LDBFMIN  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDBFMIN_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3c205000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDBFMIN_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDBFMIN_16
            IEM_INSTR_IMPL_A64__LDBFMIN_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38a01000: LDCLRAB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRAB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRAB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRAB_32_memop
        IEM_INSTR_IMPL_A64__LDCLRAB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78a01000: LDCLRAH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRAH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRAH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRAH_32_memop
        IEM_INSTR_IMPL_A64__LDCLRAH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38e01000: LDCLRALB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRALB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRALB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRALB_32_memop
        IEM_INSTR_IMPL_A64__LDCLRALB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78e01000: LDCLRALH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRALH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRALH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRALH_32_memop
        IEM_INSTR_IMPL_A64__LDCLRALH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8e01000: LDCLRAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRAL_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRAL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRAL_32_memop
        IEM_INSTR_IMPL_A64__LDCLRAL_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8e01000: LDCLRAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRAL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRAL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRAL_64_memop
        IEM_INSTR_IMPL_A64__LDCLRAL_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8a01000: LDCLRA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRA_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRA_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRA_32_memop
        IEM_INSTR_IMPL_A64__LDCLRA_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8a01000: LDCLRA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRA_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRA_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRA_64_memop
        IEM_INSTR_IMPL_A64__LDCLRA_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38201000: LDCLRB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRB_32_memop
        IEM_INSTR_IMPL_A64__LDCLRB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78201000: LDCLRH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRH_32_memop
        IEM_INSTR_IMPL_A64__LDCLRH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38601000: LDCLRLB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRLB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRLB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRLB_32_memop
        IEM_INSTR_IMPL_A64__LDCLRLB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78601000: LDCLRLH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRLH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRLH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRLH_32_memop
        IEM_INSTR_IMPL_A64__LDCLRLH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8601000: LDCLRL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRL_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRL_32_memop
        IEM_INSTR_IMPL_A64__LDCLRL_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8601000: LDCLRL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLRL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLRL_64_memop
        IEM_INSTR_IMPL_A64__LDCLRL_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19e01000: LDCLRPAL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRPAL_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse128 /*FEAT_LSE128*/)
    {
        LogFlow(("%018x/%010x: LDCLRPAL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDCLRPAL_128_memop_128
        IEM_INSTR_IMPL_A64__LDCLRPAL_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19a01000: LDCLRPA  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRPA_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19a01000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse128 /*FEAT_LSE128*/)
        {
            LogFlow(("%018x/%010x: LDCLRPA_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDCLRPA_128_memop_128
            IEM_INSTR_IMPL_A64__LDCLRPA_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19601000: LDCLRPL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRPL_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse128 /*FEAT_LSE128*/)
    {
        LogFlow(("%018x/%010x: LDCLRPL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDCLRPL_128_memop_128
        IEM_INSTR_IMPL_A64__LDCLRPL_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19201000: LDCLRP  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLRP_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse128 /*FEAT_LSE128*/)
    {
        LogFlow(("%018x/%010x: LDCLRP_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDCLRP_128_memop_128
        IEM_INSTR_IMPL_A64__LDCLRP_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8201000: LDCLR  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLR_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLR_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLR_32_memop
        IEM_INSTR_IMPL_A64__LDCLR_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8201000: LDCLR  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDCLR_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDCLR_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDCLR_64_memop
        IEM_INSTR_IMPL_A64__LDCLR_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38a02000: LDEORAB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORAB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38a02000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDEORAB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORAB_32_memop
            IEM_INSTR_IMPL_A64__LDEORAB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78a02000: LDEORAH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORAH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDEORAH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORAH_32_memop
        IEM_INSTR_IMPL_A64__LDEORAH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38e02000: LDEORALB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORALB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDEORALB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORALB_32_memop
        IEM_INSTR_IMPL_A64__LDEORALB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78e02000: LDEORALH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORALH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDEORALH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORALH_32_memop
        IEM_INSTR_IMPL_A64__LDEORALH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8e02000: LDEORAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORAL_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDEORAL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORAL_32_memop
        IEM_INSTR_IMPL_A64__LDEORAL_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8e02000: LDEORAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORAL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDEORAL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORAL_64_memop
        IEM_INSTR_IMPL_A64__LDEORAL_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8a02000: LDEORA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORA_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDEORA_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORA_32_memop
        IEM_INSTR_IMPL_A64__LDEORA_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8a02000: LDEORA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORA_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDEORA_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORA_64_memop
        IEM_INSTR_IMPL_A64__LDEORA_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38202000: LDEORB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38202000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDEORB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORB_32_memop
            IEM_INSTR_IMPL_A64__LDEORB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78202000: LDEORH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78202000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDEORH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORH_32_memop
            IEM_INSTR_IMPL_A64__LDEORH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38602000: LDEORLB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORLB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38602000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDEORLB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORLB_32_memop
            IEM_INSTR_IMPL_A64__LDEORLB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78602000: LDEORLH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORLH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDEORLH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORLH_32_memop
        IEM_INSTR_IMPL_A64__LDEORLH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8602000: LDEORL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORL_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8602000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDEORL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORL_32_memop
            IEM_INSTR_IMPL_A64__LDEORL_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8602000: LDEORL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEORL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDEORL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEORL_64_memop
        IEM_INSTR_IMPL_A64__LDEORL_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8202000: LDEOR  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEOR_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8202000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDEOR_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEOR_32_memop
            IEM_INSTR_IMPL_A64__LDEOR_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8202000: LDEOR  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDEOR_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8202000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDEOR_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDEOR_64_memop
            IEM_INSTR_IMPL_A64__LDEOR_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ce00000: LDFADDAL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFADDAL_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ce00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFADDAL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFADDAL_16
            IEM_INSTR_IMPL_A64__LDFADDAL_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bce00000: LDFADDAL  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFADDAL_32, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFADDAL_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFADDAL_32
        IEM_INSTR_IMPL_A64__LDFADDAL_32(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fce00000: LDFADDAL  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFADDAL_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfce00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFADDAL_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFADDAL_64
            IEM_INSTR_IMPL_A64__LDFADDAL_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ca00000: LDFADDA  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFADDA_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ca00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFADDA_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFADDA_16
            IEM_INSTR_IMPL_A64__LDFADDA_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bca00000: LDFADDA  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFADDA_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbca00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFADDA_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFADDA_32
            IEM_INSTR_IMPL_A64__LDFADDA_32(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fca00000: LDFADDA  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFADDA_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfca00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFADDA_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFADDA_64
            IEM_INSTR_IMPL_A64__LDFADDA_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7c600000: LDFADDL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFADDL_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7c600000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFADDL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFADDL_16
            IEM_INSTR_IMPL_A64__LDFADDL_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bc600000: LDFADDL  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFADDL_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbc600000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFADDL_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFADDL_32
            IEM_INSTR_IMPL_A64__LDFADDL_32(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fc600000: LDFADDL  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFADDL_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfc600000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFADDL_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFADDL_64
            IEM_INSTR_IMPL_A64__LDFADDL_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7c200000: LDFADD  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFADD_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7c200000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFADD_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFADD_16
            IEM_INSTR_IMPL_A64__LDFADD_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bc200000: LDFADD  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFADD_32, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFADD_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFADD_32
        IEM_INSTR_IMPL_A64__LDFADD_32(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fc200000: LDFADD  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFADD_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfc200000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFADD_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFADD_64
            IEM_INSTR_IMPL_A64__LDFADD_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ce04000: LDFMAXAL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXAL_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ce04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXAL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXAL_16
            IEM_INSTR_IMPL_A64__LDFMAXAL_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bce04000: LDFMAXAL  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXAL_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbce04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXAL_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXAL_32
            IEM_INSTR_IMPL_A64__LDFMAXAL_32(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fce04000: LDFMAXAL  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXAL_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfce04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXAL_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXAL_64
            IEM_INSTR_IMPL_A64__LDFMAXAL_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ca04000: LDFMAXA  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXA_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ca04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXA_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXA_16
            IEM_INSTR_IMPL_A64__LDFMAXA_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bca04000: LDFMAXA  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXA_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbca04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXA_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXA_32
            IEM_INSTR_IMPL_A64__LDFMAXA_32(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fca04000: LDFMAXA  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXA_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfca04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXA_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXA_64
            IEM_INSTR_IMPL_A64__LDFMAXA_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7c604000: LDFMAXL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXL_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7c604000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXL_16
            IEM_INSTR_IMPL_A64__LDFMAXL_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bc604000: LDFMAXL  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXL_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbc604000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXL_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXL_32
            IEM_INSTR_IMPL_A64__LDFMAXL_32(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fc604000: LDFMAXL  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXL_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfc604000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXL_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXL_64
            IEM_INSTR_IMPL_A64__LDFMAXL_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ce06000: LDFMAXNMAL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXNMAL_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ce06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXNMAL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXNMAL_16
            IEM_INSTR_IMPL_A64__LDFMAXNMAL_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bce06000: LDFMAXNMAL  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXNMAL_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbce06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXNMAL_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXNMAL_32
            IEM_INSTR_IMPL_A64__LDFMAXNMAL_32(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fce06000: LDFMAXNMAL  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXNMAL_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfce06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXNMAL_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXNMAL_64
            IEM_INSTR_IMPL_A64__LDFMAXNMAL_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ca06000: LDFMAXNMA  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXNMA_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ca06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXNMA_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXNMA_16
            IEM_INSTR_IMPL_A64__LDFMAXNMA_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bca06000: LDFMAXNMA  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXNMA_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbca06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXNMA_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXNMA_32
            IEM_INSTR_IMPL_A64__LDFMAXNMA_32(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fca06000: LDFMAXNMA  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXNMA_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfca06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXNMA_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXNMA_64
            IEM_INSTR_IMPL_A64__LDFMAXNMA_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7c606000: LDFMAXNML  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXNML_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7c606000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXNML_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXNML_16
            IEM_INSTR_IMPL_A64__LDFMAXNML_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bc606000: LDFMAXNML  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXNML_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbc606000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXNML_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXNML_32
            IEM_INSTR_IMPL_A64__LDFMAXNML_32(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fc606000: LDFMAXNML  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXNML_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfc606000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXNML_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXNML_64
            IEM_INSTR_IMPL_A64__LDFMAXNML_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7c206000: LDFMAXNM  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXNM_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7c206000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXNM_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXNM_16
            IEM_INSTR_IMPL_A64__LDFMAXNM_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bc206000: LDFMAXNM  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXNM_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbc206000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXNM_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXNM_32
            IEM_INSTR_IMPL_A64__LDFMAXNM_32(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fc206000: LDFMAXNM  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAXNM_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfc206000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAXNM_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAXNM_64
            IEM_INSTR_IMPL_A64__LDFMAXNM_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7c204000: LDFMAX  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAX_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7c204000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAX_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAX_16
            IEM_INSTR_IMPL_A64__LDFMAX_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bc204000: LDFMAX  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAX_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbc204000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAX_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAX_32
            IEM_INSTR_IMPL_A64__LDFMAX_32(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fc204000: LDFMAX  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMAX_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfc204000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMAX_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMAX_64
            IEM_INSTR_IMPL_A64__LDFMAX_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ce05000: LDFMINAL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINAL_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINAL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINAL_16
        IEM_INSTR_IMPL_A64__LDFMINAL_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bce05000: LDFMINAL  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINAL_32, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINAL_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINAL_32
        IEM_INSTR_IMPL_A64__LDFMINAL_32(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fce05000: LDFMINAL  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINAL_64, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINAL_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINAL_64
        IEM_INSTR_IMPL_A64__LDFMINAL_64(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ca05000: LDFMINA  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINA_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ca05000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMINA_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINA_16
            IEM_INSTR_IMPL_A64__LDFMINA_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bca05000: LDFMINA  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINA_32, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINA_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINA_32
        IEM_INSTR_IMPL_A64__LDFMINA_32(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fca05000: LDFMINA  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINA_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfca05000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMINA_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINA_64
            IEM_INSTR_IMPL_A64__LDFMINA_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7c605000: LDFMINL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINL_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINL_16
        IEM_INSTR_IMPL_A64__LDFMINL_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bc605000: LDFMINL  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINL_32, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINL_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINL_32
        IEM_INSTR_IMPL_A64__LDFMINL_32(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fc605000: LDFMINL  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINL_64, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINL_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINL_64
        IEM_INSTR_IMPL_A64__LDFMINL_64(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ce07000: LDFMINNMAL  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINNMAL_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINNMAL_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINNMAL_16
        IEM_INSTR_IMPL_A64__LDFMINNMAL_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bce07000: LDFMINNMAL  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINNMAL_32, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINNMAL_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINNMAL_32
        IEM_INSTR_IMPL_A64__LDFMINNMAL_32(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fce07000: LDFMINNMAL  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINNMAL_64, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINNMAL_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINNMAL_64
        IEM_INSTR_IMPL_A64__LDFMINNMAL_64(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ca07000: LDFMINNMA  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINNMA_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINNMA_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINNMA_16
        IEM_INSTR_IMPL_A64__LDFMINNMA_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bca07000: LDFMINNMA  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINNMA_32, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINNMA_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINNMA_32
        IEM_INSTR_IMPL_A64__LDFMINNMA_32(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fca07000: LDFMINNMA  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINNMA_64, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINNMA_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINNMA_64
        IEM_INSTR_IMPL_A64__LDFMINNMA_64(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7c607000: LDFMINNML  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINNML_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINNML_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINNML_16
        IEM_INSTR_IMPL_A64__LDFMINNML_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bc607000: LDFMINNML  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINNML_32, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINNML_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINNML_32
        IEM_INSTR_IMPL_A64__LDFMINNML_32(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fc607000: LDFMINNML  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINNML_64, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINNML_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINNML_64
        IEM_INSTR_IMPL_A64__LDFMINNML_64(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7c207000: LDFMINNM  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINNM_16, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINNM_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINNM_16
        IEM_INSTR_IMPL_A64__LDFMINNM_16(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bc207000: LDFMINNM  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINNM_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbc207000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMINNM_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINNM_32
            IEM_INSTR_IMPL_A64__LDFMINNM_32(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fc207000: LDFMINNM  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMINNM_64, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: LDFMINNM_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMINNM_64
        IEM_INSTR_IMPL_A64__LDFMINNM_64(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7c205000: LDFMIN  <Hs>, <Ht>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMIN_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7c205000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMIN_16 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMIN_16
            IEM_INSTR_IMPL_A64__LDFMIN_16(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bc205000: LDFMIN  <Ss>, <St>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMIN_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbc205000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMIN_32 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMIN_32
            IEM_INSTR_IMPL_A64__LDFMIN_32(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/fc205000: LDFMIN  <Ds>, <Dt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDFMIN_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfc205000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: LDFMIN_64 Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDFMIN_64
            IEM_INSTR_IMPL_A64__LDFMIN_64(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/d9e00000: LDGM  <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDGM_64bulk_ldsttags, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte2 /*FEAT_MTE2*/)
    {
        LogFlow(("%018x/%010x: LDGM_64bulk_ldsttags Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDGM_64bulk_ldsttags
        IEM_INSTR_IMPL_A64__LDGM_64bulk_ldsttags(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9600000: LDG  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDG_64Loffset_ldsttags, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: LDG_64Loffset_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDG_64Loffset_ldsttags
        IEM_INSTR_IMPL_A64__LDG_64Loffset_ldsttags(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/99400800: LDIAPP  <Wt1>, <Wt2>, [<Xn|SP>], #8
   Instruction Set: A64  Groups: ldiappstilp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDIAPP_32LE_ldiappstilp, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: LDIAPP_32LE_ldiappstilp Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDIAPP_32LE_ldiappstilp
        IEM_INSTR_IMPL_A64__LDIAPP_32LE_ldiappstilp(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/99401800: LDIAPP  <Wt1>, <Wt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: ldiappstilp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDIAPP_32L_ldiappstilp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x99401800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
        {
            LogFlow(("%018x/%010x: LDIAPP_32L_ldiappstilp Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDIAPP_32L_ldiappstilp
            IEM_INSTR_IMPL_A64__LDIAPP_32L_ldiappstilp(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/d9400800: LDIAPP  <Xt1>, <Xt2>, [<Xn|SP>], #16
   Instruction Set: A64  Groups: ldiappstilp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDIAPP_64LS_ldiappstilp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xd9400800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
        {
            LogFlow(("%018x/%010x: LDIAPP_64LS_ldiappstilp Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDIAPP_64LS_ldiappstilp
            IEM_INSTR_IMPL_A64__LDIAPP_64LS_ldiappstilp(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/d9401800: LDIAPP  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: ldiappstilp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDIAPP_64L_ldiappstilp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xd9401800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
        {
            LogFlow(("%018x/%010x: LDIAPP_64L_ldiappstilp Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDIAPP_64L_ldiappstilp
            IEM_INSTR_IMPL_A64__LDIAPP_64L_ldiappstilp(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/08df7c00: LDLARB  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDLARB_LR32_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLor /*FEAT_LOR*/)
    {
        LogFlow(("%018x/%010x: LDLARB_LR32_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDLARB_LR32_ldstord
        IEM_INSTR_IMPL_A64__LDLARB_LR32_ldstord(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/48df7c00: LDLARH  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDLARH_LR32_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLor /*FEAT_LOR*/)
    {
        LogFlow(("%018x/%010x: LDLARH_LR32_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDLARH_LR32_ldstord
        IEM_INSTR_IMPL_A64__LDLARH_LR32_ldstord(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/88df7c00: LDLAR  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDLAR_LR32_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLor /*FEAT_LOR*/)
    {
        LogFlow(("%018x/%010x: LDLAR_LR32_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDLAR_LR32_ldstord
        IEM_INSTR_IMPL_A64__LDLAR_LR32_ldstord(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/c8df7c00: LDLAR  <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDLAR_LR64_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLor /*FEAT_LOR*/)
    {
        LogFlow(("%018x/%010x: LDLAR_LR64_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDLAR_LR64_ldstord
        IEM_INSTR_IMPL_A64__LDLAR_LR64_ldstord(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/28400000: LDNP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDNP_32_ldstnapair_offs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x28400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: LDNP_32_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDNP_32_ldstnapair_offs
        IEM_INSTR_IMPL_A64__LDNP_32_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/a8400000: LDNP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDNP_64_ldstnapair_offs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    LogFlow(("%018x/%010x: LDNP_64_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDNP_64_ldstnapair_offs
    IEM_INSTR_IMPL_A64__LDNP_64_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
    RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/6c400000: LDNP  <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDNP_D_ldstnapair_offs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x6c400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDNP_D_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDNP_D_ldstnapair_offs
            IEM_INSTR_IMPL_A64__LDNP_D_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ac400000: LDNP  <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDNP_Q_ldstnapair_offs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xac400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDNP_Q_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDNP_Q_ldstnapair_offs
            IEM_INSTR_IMPL_A64__LDNP_Q_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/2c400000: LDNP  <St1>, <St2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDNP_S_ldstnapair_offs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x2c400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDNP_S_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDNP_S_ldstnapair_offs
            IEM_INSTR_IMPL_A64__LDNP_S_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/69400000: LDPSW  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDPSW_64_ldstpair_off, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x69400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: LDPSW_64_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDPSW_64_ldstpair_off
        IEM_INSTR_IMPL_A64__LDPSW_64_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/68c00000: LDPSW  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDPSW_64_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x68c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: LDPSW_64_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDPSW_64_ldstpair_post
        IEM_INSTR_IMPL_A64__LDPSW_64_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/69c00000: LDPSW  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDPSW_64_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x69c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: LDPSW_64_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDPSW_64_ldstpair_pre
        IEM_INSTR_IMPL_A64__LDPSW_64_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/29400000: LDP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_32_ldstpair_off, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x29400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: LDP_32_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_32_ldstpair_off
        IEM_INSTR_IMPL_A64__LDP_32_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/28c00000: LDP  <Wt1>, <Wt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_32_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x28c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: LDP_32_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_32_ldstpair_post
        IEM_INSTR_IMPL_A64__LDP_32_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/29c00000: LDP  <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_32_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x29c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: LDP_32_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_32_ldstpair_pre
        IEM_INSTR_IMPL_A64__LDP_32_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/a9400000: LDP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_64_ldstpair_off, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    LogFlow(("%018x/%010x: LDP_64_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_64_ldstpair_off
    IEM_INSTR_IMPL_A64__LDP_64_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
    RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/a8c00000: LDP  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_64_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xa8c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: LDP_64_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_64_ldstpair_post
        IEM_INSTR_IMPL_A64__LDP_64_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/a9c00000: LDP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_64_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xa9c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: LDP_64_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_64_ldstpair_pre
        IEM_INSTR_IMPL_A64__LDP_64_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/6d400000: LDP  <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_D_ldstpair_off, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x6d400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDP_D_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_D_ldstpair_off
            IEM_INSTR_IMPL_A64__LDP_D_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/6cc00000: LDP  <Dt1>, <Dt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_D_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x6cc00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDP_D_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_D_ldstpair_post
            IEM_INSTR_IMPL_A64__LDP_D_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/6dc00000: LDP  <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_D_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x6dc00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDP_D_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_D_ldstpair_pre
            IEM_INSTR_IMPL_A64__LDP_D_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ad400000: LDP  <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_Q_ldstpair_off, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xad400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDP_Q_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_Q_ldstpair_off
            IEM_INSTR_IMPL_A64__LDP_Q_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/acc00000: LDP  <Qt1>, <Qt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_Q_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xacc00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDP_Q_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_Q_ldstpair_post
            IEM_INSTR_IMPL_A64__LDP_Q_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/adc00000: LDP  <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_Q_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xadc00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDP_Q_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_Q_ldstpair_pre
            IEM_INSTR_IMPL_A64__LDP_Q_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/2d400000: LDP  <St1>, <St2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_S_ldstpair_off, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x2d400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDP_S_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_S_ldstpair_off
            IEM_INSTR_IMPL_A64__LDP_S_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/2cc00000: LDP  <St1>, <St2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_S_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x2cc00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDP_S_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_S_ldstpair_post
            IEM_INSTR_IMPL_A64__LDP_S_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/2dc00000: LDP  <St1>, <St2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDP_S_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x2dc00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDP_S_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDP_S_ldstpair_pre
            IEM_INSTR_IMPL_A64__LDP_S_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa00c00/f8200c00: LDRAA  <Xt>, [<Xn|SP>{, #<simm>}]!
   Instruction Set: A64  Groups: ldst_pac, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRAA_64W_ldst_pac, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    uint32_t const S          = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: LDRAA_64W_ldst_pac Rt=%#x Rn=%#x imm9=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9, S));
#ifdef IEM_INSTR_IMPL_A64__LDRAA_64W_ldst_pac
        IEM_INSTR_IMPL_A64__LDRAA_64W_ldst_pac(Rt, Rn, imm9, S);
#else
        RT_NOREF(Rt, Rn, imm9, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa00c00/f8200400: LDRAA  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_pac, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRAA_64_ldst_pac, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    uint32_t const S          = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: LDRAA_64_ldst_pac Rt=%#x Rn=%#x imm9=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9, S));
#ifdef IEM_INSTR_IMPL_A64__LDRAA_64_ldst_pac
        IEM_INSTR_IMPL_A64__LDRAA_64_ldst_pac(Rt, Rn, imm9, S);
#else
        RT_NOREF(Rt, Rn, imm9, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa00c00/f8a00c00: LDRAB  <Xt>, [<Xn|SP>{, #<simm>}]!
   Instruction Set: A64  Groups: ldst_pac, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRAB_64W_ldst_pac, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa00c00)) == UINT32_C(0xf8a00c00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: LDRAB_64W_ldst_pac Rt=%#x Rn=%#x imm9=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9, S));
#ifdef IEM_INSTR_IMPL_A64__LDRAB_64W_ldst_pac
            IEM_INSTR_IMPL_A64__LDRAB_64W_ldst_pac(Rt, Rn, imm9, S);
#else
            RT_NOREF(Rt, Rn, imm9, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa00c00/f8a00400: LDRAB  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_pac, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRAB_64_ldst_pac, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    uint32_t const S          = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: LDRAB_64_ldst_pac Rt=%#x Rn=%#x imm9=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9, S));
#ifdef IEM_INSTR_IMPL_A64__LDRAB_64_ldst_pac
        IEM_INSTR_IMPL_A64__LDRAB_64_ldst_pac(Rt, Rn, imm9, S);
#else
        RT_NOREF(Rt, Rn, imm9, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0ec00/38606800: LDRB  <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRB_32BL_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: LDRB_32BL_ldst_regoff Rt=%#x Rn=%#x S=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDRB_32BL_ldst_regoff
    IEM_INSTR_IMPL_A64__LDRB_32BL_ldst_regoff(Rt, Rn, S, Rm);
#else
    RT_NOREF(Rt, Rn, S, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/38600800: LDRB  <Wt>, [<Xn|SP>, {<Wm> | <Xm>}, <extend>{ <amount>}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRB_32B_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (option != 3)
    {
        LogFlow(("%018x/%010x: LDRB_32B_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDRB_32B_ldst_regoff
        IEM_INSTR_IMPL_A64__LDRB_32B_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38400400: LDRB  <Wt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRB_32_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38400400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDRB_32_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRB_32_ldst_immpost
        IEM_INSTR_IMPL_A64__LDRB_32_ldst_immpost(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38400c00: LDRB  <Wt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRB_32_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDRB_32_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRB_32_ldst_immpre
    IEM_INSTR_IMPL_A64__LDRB_32_ldst_immpre(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/39400000: LDRB  <Wt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRB_32_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x39400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        LogFlow(("%018x/%010x: LDRB_32_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDRB_32_ldst_pos
        IEM_INSTR_IMPL_A64__LDRB_32_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78400400: LDRH  <Wt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRH_32_ldst_immpost, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDRH_32_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRH_32_ldst_immpost
    IEM_INSTR_IMPL_A64__LDRH_32_ldst_immpost(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/78400c00: LDRH  <Wt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRH_32_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDRH_32_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRH_32_ldst_immpre
    IEM_INSTR_IMPL_A64__LDRH_32_ldst_immpre(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/79400000: LDRH  <Wt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRH_32_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x79400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        LogFlow(("%018x/%010x: LDRH_32_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDRH_32_ldst_pos
        IEM_INSTR_IMPL_A64__LDRH_32_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78600800: LDRH  <Wt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRH_32_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: LDRH_32_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDRH_32_ldst_regoff
    IEM_INSTR_IMPL_A64__LDRH_32_ldst_regoff(Rt, Rn, S, option, Rm);
#else
    RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0ec00/38e06800: LDRSB  <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSB_32BL_ldst_regoff, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0ec00)) == UINT32_C(0x38e06800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: LDRSB_32BL_ldst_regoff Rt=%#x Rn=%#x S=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDRSB_32BL_ldst_regoff
        IEM_INSTR_IMPL_A64__LDRSB_32BL_ldst_regoff(Rt, Rn, S, Rm);
#else
        RT_NOREF(Rt, Rn, S, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38e00800: LDRSB  <Wt>, [<Xn|SP>, {<Wm> | <Xm>}, <extend>{ <amount>}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSB_32B_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (option != 3)
    {
        LogFlow(("%018x/%010x: LDRSB_32B_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDRSB_32B_ldst_regoff
        IEM_INSTR_IMPL_A64__LDRSB_32B_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38c00400: LDRSB  <Wt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSB_32_ldst_immpost, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDRSB_32_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRSB_32_ldst_immpost
    IEM_INSTR_IMPL_A64__LDRSB_32_ldst_immpost(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/38c00c00: LDRSB  <Wt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSB_32_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDRSB_32_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRSB_32_ldst_immpre
    IEM_INSTR_IMPL_A64__LDRSB_32_ldst_immpre(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/39c00000: LDRSB  <Wt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSB_32_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x39c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        LogFlow(("%018x/%010x: LDRSB_32_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDRSB_32_ldst_pos
        IEM_INSTR_IMPL_A64__LDRSB_32_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0ec00/38a06800: LDRSB  <Xt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSB_64BL_ldst_regoff, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0ec00)) == UINT32_C(0x38a06800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: LDRSB_64BL_ldst_regoff Rt=%#x Rn=%#x S=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDRSB_64BL_ldst_regoff
        IEM_INSTR_IMPL_A64__LDRSB_64BL_ldst_regoff(Rt, Rn, S, Rm);
#else
        RT_NOREF(Rt, Rn, S, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38a00800: LDRSB  <Xt>, [<Xn|SP>, {<Wm> | <Xm>}, <extend>{ <amount>}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSB_64B_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (option != 3)
    {
        LogFlow(("%018x/%010x: LDRSB_64B_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDRSB_64B_ldst_regoff
        IEM_INSTR_IMPL_A64__LDRSB_64B_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38800400: LDRSB  <Xt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSB_64_ldst_immpost, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDRSB_64_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRSB_64_ldst_immpost
    IEM_INSTR_IMPL_A64__LDRSB_64_ldst_immpost(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/38800c00: LDRSB  <Xt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSB_64_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDRSB_64_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRSB_64_ldst_immpre
    IEM_INSTR_IMPL_A64__LDRSB_64_ldst_immpre(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/39800000: LDRSB  <Xt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSB_64_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x39800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        LogFlow(("%018x/%010x: LDRSB_64_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDRSB_64_ldst_pos
        IEM_INSTR_IMPL_A64__LDRSB_64_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78c00400: LDRSH  <Wt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSH_32_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78c00400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDRSH_32_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRSH_32_ldst_immpost
        IEM_INSTR_IMPL_A64__LDRSH_32_ldst_immpost(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78c00c00: LDRSH  <Wt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSH_32_ldst_immpre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78c00c00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDRSH_32_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRSH_32_ldst_immpre
        IEM_INSTR_IMPL_A64__LDRSH_32_ldst_immpre(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/79c00000: LDRSH  <Wt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSH_32_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x79c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        LogFlow(("%018x/%010x: LDRSH_32_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDRSH_32_ldst_pos
        IEM_INSTR_IMPL_A64__LDRSH_32_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78e00800: LDRSH  <Wt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSH_32_ldst_regoff, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78e00800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: LDRSH_32_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDRSH_32_ldst_regoff
        IEM_INSTR_IMPL_A64__LDRSH_32_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78800400: LDRSH  <Xt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSH_64_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78800400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDRSH_64_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRSH_64_ldst_immpost
        IEM_INSTR_IMPL_A64__LDRSH_64_ldst_immpost(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78800c00: LDRSH  <Xt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSH_64_ldst_immpre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78800c00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDRSH_64_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRSH_64_ldst_immpre
        IEM_INSTR_IMPL_A64__LDRSH_64_ldst_immpre(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/79800000: LDRSH  <Xt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSH_64_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x79800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        LogFlow(("%018x/%010x: LDRSH_64_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDRSH_64_ldst_pos
        IEM_INSTR_IMPL_A64__LDRSH_64_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78a00800: LDRSH  <Xt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSH_64_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: LDRSH_64_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDRSH_64_ldst_regoff
    IEM_INSTR_IMPL_A64__LDRSH_64_ldst_regoff(Rt, Rn, S, option, Rm);
#else
    RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/b8800400: LDRSW  <Xt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSW_64_ldst_immpost, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDRSW_64_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRSW_64_ldst_immpost
    IEM_INSTR_IMPL_A64__LDRSW_64_ldst_immpost(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/b8800c00: LDRSW  <Xt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSW_64_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDRSW_64_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDRSW_64_ldst_immpre
    IEM_INSTR_IMPL_A64__LDRSW_64_ldst_immpre(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/b9800000: LDRSW  <Xt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSW_64_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xb9800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        LogFlow(("%018x/%010x: LDRSW_64_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDRSW_64_ldst_pos
        IEM_INSTR_IMPL_A64__LDRSW_64_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/b8a00800: LDRSW  <Xt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSW_64_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: LDRSW_64_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDRSW_64_ldst_regoff
    IEM_INSTR_IMPL_A64__LDRSW_64_ldst_regoff(Rt, Rn, S, option, Rm);
#else
    RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff000000/98000000: LDRSW  <Xt>, <label>
   Instruction Set: A64  Groups: loadlit, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDRSW_64_loadlit, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
    LogFlow(("%018x/%010x: LDRSW_64_loadlit Rt=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm19));
#ifdef IEM_INSTR_IMPL_A64__LDRSW_64_loadlit
    IEM_INSTR_IMPL_A64__LDRSW_64_loadlit(Rt, imm19);
#else
    RT_NOREF(Rt, imm19, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/b8400400: LDR  <Wt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_32_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8400400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDR_32_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_32_ldst_immpost
        IEM_INSTR_IMPL_A64__LDR_32_ldst_immpost(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/b8400c00: LDR  <Wt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_32_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDR_32_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_32_ldst_immpre
    IEM_INSTR_IMPL_A64__LDR_32_ldst_immpre(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/b9400000: LDR  <Wt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_32_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xb9400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        LogFlow(("%018x/%010x: LDR_32_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDR_32_ldst_pos
        IEM_INSTR_IMPL_A64__LDR_32_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/b8600800: LDR  <Wt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_32_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: LDR_32_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDR_32_ldst_regoff
    IEM_INSTR_IMPL_A64__LDR_32_ldst_regoff(Rt, Rn, S, option, Rm);
#else
    RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff000000/18000000: LDR  <Wt>, <label>
   Instruction Set: A64  Groups: loadlit, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_32_loadlit, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
    LogFlow(("%018x/%010x: LDR_32_loadlit Rt=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm19));
#ifdef IEM_INSTR_IMPL_A64__LDR_32_loadlit
    IEM_INSTR_IMPL_A64__LDR_32_loadlit(Rt, imm19);
#else
    RT_NOREF(Rt, imm19, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/f8400400: LDR  <Xt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_64_ldst_immpost, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDR_64_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_64_ldst_immpost
    IEM_INSTR_IMPL_A64__LDR_64_ldst_immpost(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/f8400c00: LDR  <Xt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_64_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDR_64_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_64_ldst_immpre
    IEM_INSTR_IMPL_A64__LDR_64_ldst_immpre(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/f9400000: LDR  <Xt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_64_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xf9400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        LogFlow(("%018x/%010x: LDR_64_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDR_64_ldst_pos
        IEM_INSTR_IMPL_A64__LDR_64_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/f8600800: LDR  <Xt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_64_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: LDR_64_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDR_64_ldst_regoff
    IEM_INSTR_IMPL_A64__LDR_64_ldst_regoff(Rt, Rn, S, option, Rm);
#else
    RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff000000/58000000: LDR  <Xt>, <label>
   Instruction Set: A64  Groups: loadlit, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_64_loadlit, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
    LogFlow(("%018x/%010x: LDR_64_loadlit Rt=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm19));
#ifdef IEM_INSTR_IMPL_A64__LDR_64_loadlit
    IEM_INSTR_IMPL_A64__LDR_64_loadlit(Rt, imm19);
#else
    RT_NOREF(Rt, imm19, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0ec00/3c606800: LDR  <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_BL_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_BL_ldst_regoff Rt=%#x Rn=%#x S=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDR_BL_ldst_regoff
        IEM_INSTR_IMPL_A64__LDR_BL_ldst_regoff(Rt, Rn, S, Rm);
#else
        RT_NOREF(Rt, Rn, S, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3c400400: LDR  <Bt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_B_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3c400400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDR_B_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_B_ldst_immpost
            IEM_INSTR_IMPL_A64__LDR_B_ldst_immpost(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3c400c00: LDR  <Bt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_B_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_B_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_B_ldst_immpre
        IEM_INSTR_IMPL_A64__LDR_B_ldst_immpre(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/3d400000: LDR  <Bt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_B_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x3d400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDR_B_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDR_B_ldst_pos
            IEM_INSTR_IMPL_A64__LDR_B_ldst_pos(Rt, Rn, imm12);
#else
            RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3c600800: LDR  <Bt>, [<Xn|SP>, {<Wm> | <Xm>}, <extend>{ <amount>}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_B_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && option != 3)
    {
        LogFlow(("%018x/%010x: LDR_B_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDR_B_ldst_regoff
        IEM_INSTR_IMPL_A64__LDR_B_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/fc400400: LDR  <Dt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_D_ldst_immpost, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_D_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_D_ldst_immpost
        IEM_INSTR_IMPL_A64__LDR_D_ldst_immpost(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/fc400c00: LDR  <Dt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_D_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_D_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_D_ldst_immpre
        IEM_INSTR_IMPL_A64__LDR_D_ldst_immpre(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/fd400000: LDR  <Dt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_D_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xfd400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDR_D_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDR_D_ldst_pos
            IEM_INSTR_IMPL_A64__LDR_D_ldst_pos(Rt, Rn, imm12);
#else
            RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/fc600800: LDR  <Dt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_D_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_D_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDR_D_ldst_regoff
        IEM_INSTR_IMPL_A64__LDR_D_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff000000/5c000000: LDR  <Dt>, <label>
   Instruction Set: A64  Groups: loadlit, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_D_loadlit, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_D_loadlit Rt=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm19));
#ifdef IEM_INSTR_IMPL_A64__LDR_D_loadlit
        IEM_INSTR_IMPL_A64__LDR_D_loadlit(Rt, imm19);
#else
        RT_NOREF(Rt, imm19, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/7c400400: LDR  <Ht>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_H_ldst_immpost, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_H_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_H_ldst_immpost
        IEM_INSTR_IMPL_A64__LDR_H_ldst_immpost(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/7c400c00: LDR  <Ht>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_H_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_H_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_H_ldst_immpre
        IEM_INSTR_IMPL_A64__LDR_H_ldst_immpre(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/7d400000: LDR  <Ht>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_H_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x7d400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDR_H_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDR_H_ldst_pos
            IEM_INSTR_IMPL_A64__LDR_H_ldst_pos(Rt, Rn, imm12);
#else
            RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/7c600800: LDR  <Ht>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_H_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_H_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDR_H_ldst_regoff
        IEM_INSTR_IMPL_A64__LDR_H_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3cc00400: LDR  <Qt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_Q_ldst_immpost, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_Q_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_Q_ldst_immpost
        IEM_INSTR_IMPL_A64__LDR_Q_ldst_immpost(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3cc00c00: LDR  <Qt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_Q_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_Q_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_Q_ldst_immpre
        IEM_INSTR_IMPL_A64__LDR_Q_ldst_immpre(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/3dc00000: LDR  <Qt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_Q_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x3dc00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDR_Q_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDR_Q_ldst_pos
            IEM_INSTR_IMPL_A64__LDR_Q_ldst_pos(Rt, Rn, imm12);
#else
            RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3ce00800: LDR  <Qt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_Q_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_Q_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDR_Q_ldst_regoff
        IEM_INSTR_IMPL_A64__LDR_Q_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff000000/9c000000: LDR  <Qt>, <label>
   Instruction Set: A64  Groups: loadlit, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_Q_loadlit, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_Q_loadlit Rt=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm19));
#ifdef IEM_INSTR_IMPL_A64__LDR_Q_loadlit
        IEM_INSTR_IMPL_A64__LDR_Q_loadlit(Rt, imm19);
#else
        RT_NOREF(Rt, imm19, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/bc400400: LDR  <St>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_S_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xbc400400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDR_S_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_S_ldst_immpost
            IEM_INSTR_IMPL_A64__LDR_S_ldst_immpost(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/bc400c00: LDR  <St>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_S_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_S_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDR_S_ldst_immpre
        IEM_INSTR_IMPL_A64__LDR_S_ldst_immpre(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/bd400000: LDR  <St>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_S_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xbd400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDR_S_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__LDR_S_ldst_pos
            IEM_INSTR_IMPL_A64__LDR_S_ldst_pos(Rt, Rn, imm12);
#else
            RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/bc600800: LDR  <St>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_S_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_S_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__LDR_S_ldst_regoff
        IEM_INSTR_IMPL_A64__LDR_S_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff000000/1c000000: LDR  <St>, <label>
   Instruction Set: A64  Groups: loadlit, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDR_S_loadlit, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: LDR_S_loadlit Rt=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm19));
#ifdef IEM_INSTR_IMPL_A64__LDR_S_loadlit
        IEM_INSTR_IMPL_A64__LDR_S_loadlit(Rt, imm19);
#else
        RT_NOREF(Rt, imm19, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38a03000: LDSETAB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETAB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETAB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETAB_32_memop
        IEM_INSTR_IMPL_A64__LDSETAB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78a03000: LDSETAH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETAH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETAH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETAH_32_memop
        IEM_INSTR_IMPL_A64__LDSETAH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38e03000: LDSETALB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETALB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETALB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETALB_32_memop
        IEM_INSTR_IMPL_A64__LDSETALB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78e03000: LDSETALH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETALH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETALH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETALH_32_memop
        IEM_INSTR_IMPL_A64__LDSETALH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8e03000: LDSETAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETAL_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETAL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETAL_32_memop
        IEM_INSTR_IMPL_A64__LDSETAL_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8e03000: LDSETAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETAL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETAL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETAL_64_memop
        IEM_INSTR_IMPL_A64__LDSETAL_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8a03000: LDSETA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETA_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETA_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETA_32_memop
        IEM_INSTR_IMPL_A64__LDSETA_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8a03000: LDSETA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETA_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETA_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETA_64_memop
        IEM_INSTR_IMPL_A64__LDSETA_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38203000: LDSETB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38203000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSETB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETB_32_memop
            IEM_INSTR_IMPL_A64__LDSETB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78203000: LDSETH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETH_32_memop
        IEM_INSTR_IMPL_A64__LDSETH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38603000: LDSETLB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETLB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETLB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETLB_32_memop
        IEM_INSTR_IMPL_A64__LDSETLB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78603000: LDSETLH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETLH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETLH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETLH_32_memop
        IEM_INSTR_IMPL_A64__LDSETLH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8603000: LDSETL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETL_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETL_32_memop
        IEM_INSTR_IMPL_A64__LDSETL_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8603000: LDSETL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSETL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSETL_64_memop
        IEM_INSTR_IMPL_A64__LDSETL_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19e03000: LDSETPAL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETPAL_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse128 /*FEAT_LSE128*/)
    {
        LogFlow(("%018x/%010x: LDSETPAL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDSETPAL_128_memop_128
        IEM_INSTR_IMPL_A64__LDSETPAL_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19a03000: LDSETPA  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETPA_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse128 /*FEAT_LSE128*/)
    {
        LogFlow(("%018x/%010x: LDSETPA_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDSETPA_128_memop_128
        IEM_INSTR_IMPL_A64__LDSETPA_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19603000: LDSETPL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETPL_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse128 /*FEAT_LSE128*/)
    {
        LogFlow(("%018x/%010x: LDSETPL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDSETPL_128_memop_128
        IEM_INSTR_IMPL_A64__LDSETPL_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19203000: LDSETP  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSETP_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse128 /*FEAT_LSE128*/)
    {
        LogFlow(("%018x/%010x: LDSETP_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDSETP_128_memop_128
        IEM_INSTR_IMPL_A64__LDSETP_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8203000: LDSET  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSET_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8203000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSET_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSET_32_memop
            IEM_INSTR_IMPL_A64__LDSET_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8203000: LDSET  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSET_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSET_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSET_64_memop
        IEM_INSTR_IMPL_A64__LDSET_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38a04000: LDSMAXAB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXAB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38a04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXAB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXAB_32_memop
            IEM_INSTR_IMPL_A64__LDSMAXAB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78a04000: LDSMAXAH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXAH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78a04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXAH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXAH_32_memop
            IEM_INSTR_IMPL_A64__LDSMAXAH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38e04000: LDSMAXALB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXALB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38e04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXALB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXALB_32_memop
            IEM_INSTR_IMPL_A64__LDSMAXALB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78e04000: LDSMAXALH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXALH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78e04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXALH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXALH_32_memop
            IEM_INSTR_IMPL_A64__LDSMAXALH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8e04000: LDSMAXAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXAL_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8e04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXAL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXAL_32_memop
            IEM_INSTR_IMPL_A64__LDSMAXAL_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8e04000: LDSMAXAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXAL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8e04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXAL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXAL_64_memop
            IEM_INSTR_IMPL_A64__LDSMAXAL_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8a04000: LDSMAXA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXA_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8a04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXA_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXA_32_memop
            IEM_INSTR_IMPL_A64__LDSMAXA_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8a04000: LDSMAXA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXA_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8a04000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXA_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXA_64_memop
            IEM_INSTR_IMPL_A64__LDSMAXA_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38204000: LDSMAXB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38204000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXB_32_memop
            IEM_INSTR_IMPL_A64__LDSMAXB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78204000: LDSMAXH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78204000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXH_32_memop
            IEM_INSTR_IMPL_A64__LDSMAXH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38604000: LDSMAXLB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXLB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38604000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXLB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXLB_32_memop
            IEM_INSTR_IMPL_A64__LDSMAXLB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78604000: LDSMAXLH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXLH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78604000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXLH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXLH_32_memop
            IEM_INSTR_IMPL_A64__LDSMAXLH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8604000: LDSMAXL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXL_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8604000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXL_32_memop
            IEM_INSTR_IMPL_A64__LDSMAXL_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8604000: LDSMAXL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAXL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8604000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAXL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAXL_64_memop
            IEM_INSTR_IMPL_A64__LDSMAXL_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8204000: LDSMAX  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAX_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8204000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAX_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAX_32_memop
            IEM_INSTR_IMPL_A64__LDSMAX_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8204000: LDSMAX  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMAX_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8204000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMAX_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMAX_64_memop
            IEM_INSTR_IMPL_A64__LDSMAX_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38a05000: LDSMINAB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINAB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSMINAB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINAB_32_memop
        IEM_INSTR_IMPL_A64__LDSMINAB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78a05000: LDSMINAH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINAH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78a05000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMINAH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINAH_32_memop
            IEM_INSTR_IMPL_A64__LDSMINAH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38e05000: LDSMINALB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINALB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSMINALB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINALB_32_memop
        IEM_INSTR_IMPL_A64__LDSMINALB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78e05000: LDSMINALH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINALH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSMINALH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINALH_32_memop
        IEM_INSTR_IMPL_A64__LDSMINALH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8e05000: LDSMINAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINAL_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSMINAL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINAL_32_memop
        IEM_INSTR_IMPL_A64__LDSMINAL_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8e05000: LDSMINAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINAL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSMINAL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINAL_64_memop
        IEM_INSTR_IMPL_A64__LDSMINAL_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8a05000: LDSMINA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINA_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSMINA_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINA_32_memop
        IEM_INSTR_IMPL_A64__LDSMINA_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8a05000: LDSMINA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINA_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8a05000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMINA_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINA_64_memop
            IEM_INSTR_IMPL_A64__LDSMINA_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38205000: LDSMINB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38205000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMINB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINB_32_memop
            IEM_INSTR_IMPL_A64__LDSMINB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78205000: LDSMINH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78205000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMINH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINH_32_memop
            IEM_INSTR_IMPL_A64__LDSMINH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38605000: LDSMINLB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINLB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSMINLB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINLB_32_memop
        IEM_INSTR_IMPL_A64__LDSMINLB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78605000: LDSMINLH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINLH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSMINLH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINLH_32_memop
        IEM_INSTR_IMPL_A64__LDSMINLH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8605000: LDSMINL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINL_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSMINL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINL_32_memop
        IEM_INSTR_IMPL_A64__LDSMINL_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8605000: LDSMINL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMINL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDSMINL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMINL_64_memop
        IEM_INSTR_IMPL_A64__LDSMINL_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8205000: LDSMIN  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMIN_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8205000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMIN_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMIN_32_memop
            IEM_INSTR_IMPL_A64__LDSMIN_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8205000: LDSMIN  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDSMIN_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8205000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDSMIN_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDSMIN_64_memop
            IEM_INSTR_IMPL_A64__LDSMIN_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19e00400: LDTADDAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTADDAL_32_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTADDAL_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTADDAL_32_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTADDAL_32_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59e00400: LDTADDAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTADDAL_64_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTADDAL_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTADDAL_64_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTADDAL_64_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19a00400: LDTADDA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTADDA_32_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTADDA_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTADDA_32_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTADDA_32_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59a00400: LDTADDA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTADDA_64_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTADDA_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTADDA_64_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTADDA_64_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19600400: LDTADDL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTADDL_32_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTADDL_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTADDL_32_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTADDL_32_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59600400: LDTADDL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTADDL_64_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTADDL_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTADDL_64_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTADDL_64_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19200400: LDTADD  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTADD_32_memop_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19200400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTADD_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTADD_32_memop_unpriv
            IEM_INSTR_IMPL_A64__LDTADD_32_memop_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59200400: LDTADD  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTADD_64_memop_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59200400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTADD_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTADD_64_memop_unpriv
            IEM_INSTR_IMPL_A64__LDTADD_64_memop_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19e01400: LDTCLRAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTCLRAL_32_memop_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19e01400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTCLRAL_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTCLRAL_32_memop_unpriv
            IEM_INSTR_IMPL_A64__LDTCLRAL_32_memop_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59e01400: LDTCLRAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTCLRAL_64_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTCLRAL_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTCLRAL_64_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTCLRAL_64_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19a01400: LDTCLRA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTCLRA_32_memop_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19a01400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTCLRA_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTCLRA_32_memop_unpriv
            IEM_INSTR_IMPL_A64__LDTCLRA_32_memop_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59a01400: LDTCLRA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTCLRA_64_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTCLRA_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTCLRA_64_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTCLRA_64_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19601400: LDTCLRL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTCLRL_32_memop_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19601400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTCLRL_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTCLRL_32_memop_unpriv
            IEM_INSTR_IMPL_A64__LDTCLRL_32_memop_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59601400: LDTCLRL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTCLRL_64_memop_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59601400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTCLRL_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTCLRL_64_memop_unpriv
            IEM_INSTR_IMPL_A64__LDTCLRL_64_memop_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19201400: LDTCLR  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTCLR_32_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTCLR_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTCLR_32_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTCLR_32_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59201400: LDTCLR  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTCLR_64_memop_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59201400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTCLR_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTCLR_64_memop_unpriv
            IEM_INSTR_IMPL_A64__LDTCLR_64_memop_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/e8400000: LDTNP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTNP_64_ldstnapair_offs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xe8400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTNP_64_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDTNP_64_ldstnapair_offs
            IEM_INSTR_IMPL_A64__LDTNP_64_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ec400000: LDTNP  <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTNP_Q_ldstnapair_offs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xec400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTNP_Q_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDTNP_Q_ldstnapair_offs
            IEM_INSTR_IMPL_A64__LDTNP_Q_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/e9400000: LDTP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTP_64_ldstpair_off, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xe9400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTP_64_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDTP_64_ldstpair_off
            IEM_INSTR_IMPL_A64__LDTP_64_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/e8c00000: LDTP  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTP_64_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xe8c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTP_64_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDTP_64_ldstpair_post
            IEM_INSTR_IMPL_A64__LDTP_64_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/e9c00000: LDTP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTP_64_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xe9c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTP_64_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDTP_64_ldstpair_pre
            IEM_INSTR_IMPL_A64__LDTP_64_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ed400000: LDTP  <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTP_Q_ldstpair_off, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xed400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTP_Q_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDTP_Q_ldstpair_off
            IEM_INSTR_IMPL_A64__LDTP_Q_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ecc00000: LDTP  <Qt1>, <Qt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTP_Q_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xecc00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTP_Q_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDTP_Q_ldstpair_post
            IEM_INSTR_IMPL_A64__LDTP_Q_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/edc00000: LDTP  <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTP_Q_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xedc00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTP_Q_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__LDTP_Q_ldstpair_pre
            IEM_INSTR_IMPL_A64__LDTP_Q_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38400800: LDTRB  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTRB_32_ldst_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDTRB_32_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDTRB_32_ldst_unpriv
    IEM_INSTR_IMPL_A64__LDTRB_32_ldst_unpriv(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/78400800: LDTRH  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTRH_32_ldst_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDTRH_32_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDTRH_32_ldst_unpriv
    IEM_INSTR_IMPL_A64__LDTRH_32_ldst_unpriv(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/38c00800: LDTRSB  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTRSB_32_ldst_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38c00800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDTRSB_32_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDTRSB_32_ldst_unpriv
        IEM_INSTR_IMPL_A64__LDTRSB_32_ldst_unpriv(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38800800: LDTRSB  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTRSB_64_ldst_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDTRSB_64_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDTRSB_64_ldst_unpriv
    IEM_INSTR_IMPL_A64__LDTRSB_64_ldst_unpriv(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/78c00800: LDTRSH  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTRSH_32_ldst_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78c00800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDTRSH_32_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDTRSH_32_ldst_unpriv
        IEM_INSTR_IMPL_A64__LDTRSH_32_ldst_unpriv(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78800800: LDTRSH  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTRSH_64_ldst_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78800800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDTRSH_64_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDTRSH_64_ldst_unpriv
        IEM_INSTR_IMPL_A64__LDTRSH_64_ldst_unpriv(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/b8800800: LDTRSW  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTRSW_64_ldst_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDTRSW_64_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDTRSW_64_ldst_unpriv
    IEM_INSTR_IMPL_A64__LDTRSW_64_ldst_unpriv(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/b8400800: LDTR  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTR_32_ldst_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDTR_32_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDTR_32_ldst_unpriv
    IEM_INSTR_IMPL_A64__LDTR_32_ldst_unpriv(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/f8400800: LDTR  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTR_64_ldst_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDTR_64_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDTR_64_ldst_unpriv
    IEM_INSTR_IMPL_A64__LDTR_64_ldst_unpriv(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/19e03400: LDTSETAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTSETAL_32_memop_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19e03400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTSETAL_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTSETAL_32_memop_unpriv
            IEM_INSTR_IMPL_A64__LDTSETAL_32_memop_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59e03400: LDTSETAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTSETAL_64_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTSETAL_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTSETAL_64_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTSETAL_64_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19a03400: LDTSETA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTSETA_32_memop_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19a03400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTSETA_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTSETA_32_memop_unpriv
            IEM_INSTR_IMPL_A64__LDTSETA_32_memop_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59a03400: LDTSETA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTSETA_64_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTSETA_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTSETA_64_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTSETA_64_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19603400: LDTSETL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTSETL_32_memop_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19603400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTSETL_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTSETL_32_memop_unpriv
            IEM_INSTR_IMPL_A64__LDTSETL_32_memop_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59603400: LDTSETL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTSETL_64_memop_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59603400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: LDTSETL_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTSETL_64_memop_unpriv
            IEM_INSTR_IMPL_A64__LDTSETL_64_memop_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19203400: LDTSET  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTSET_32_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTSET_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTSET_32_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTSET_32_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59203400: LDTSET  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTSET_64_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTSET_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDTSET_64_memop_unpriv
        IEM_INSTR_IMPL_A64__LDTSET_64_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/895f7c00: LDTXR  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTXR_LR32_ldstexclr_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTXR_LR32_ldstexclr_unpriv Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDTXR_LR32_ldstexclr_unpriv
        IEM_INSTR_IMPL_A64__LDTXR_LR32_ldstexclr_unpriv(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/c95f7c00: LDTXR  <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDTXR_LR64_ldstexclr_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: LDTXR_LR64_ldstexclr_unpriv Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDTXR_LR64_ldstexclr_unpriv
        IEM_INSTR_IMPL_A64__LDTXR_LR64_ldstexclr_unpriv(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38a06000: LDUMAXAB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXAB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38a06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXAB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXAB_32_memop
            IEM_INSTR_IMPL_A64__LDUMAXAB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78a06000: LDUMAXAH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXAH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78a06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXAH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXAH_32_memop
            IEM_INSTR_IMPL_A64__LDUMAXAH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38e06000: LDUMAXALB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXALB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38e06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXALB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXALB_32_memop
            IEM_INSTR_IMPL_A64__LDUMAXALB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78e06000: LDUMAXALH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXALH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78e06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXALH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXALH_32_memop
            IEM_INSTR_IMPL_A64__LDUMAXALH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8e06000: LDUMAXAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXAL_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8e06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXAL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXAL_32_memop
            IEM_INSTR_IMPL_A64__LDUMAXAL_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8e06000: LDUMAXAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXAL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8e06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXAL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXAL_64_memop
            IEM_INSTR_IMPL_A64__LDUMAXAL_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8a06000: LDUMAXA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXA_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8a06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXA_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXA_32_memop
            IEM_INSTR_IMPL_A64__LDUMAXA_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8a06000: LDUMAXA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXA_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8a06000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXA_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXA_64_memop
            IEM_INSTR_IMPL_A64__LDUMAXA_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38206000: LDUMAXB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38206000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXB_32_memop
            IEM_INSTR_IMPL_A64__LDUMAXB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78206000: LDUMAXH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78206000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXH_32_memop
            IEM_INSTR_IMPL_A64__LDUMAXH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38606000: LDUMAXLB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXLB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38606000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXLB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXLB_32_memop
            IEM_INSTR_IMPL_A64__LDUMAXLB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78606000: LDUMAXLH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXLH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78606000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXLH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXLH_32_memop
            IEM_INSTR_IMPL_A64__LDUMAXLH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8606000: LDUMAXL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXL_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8606000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXL_32_memop
            IEM_INSTR_IMPL_A64__LDUMAXL_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8606000: LDUMAXL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAXL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8606000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAXL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAXL_64_memop
            IEM_INSTR_IMPL_A64__LDUMAXL_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8206000: LDUMAX  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAX_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8206000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAX_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAX_32_memop
            IEM_INSTR_IMPL_A64__LDUMAX_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8206000: LDUMAX  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMAX_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8206000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMAX_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMAX_64_memop
            IEM_INSTR_IMPL_A64__LDUMAX_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38a07000: LDUMINAB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINAB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINAB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINAB_32_memop
        IEM_INSTR_IMPL_A64__LDUMINAB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78a07000: LDUMINAH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINAH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINAH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINAH_32_memop
        IEM_INSTR_IMPL_A64__LDUMINAH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38e07000: LDUMINALB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINALB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINALB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINALB_32_memop
        IEM_INSTR_IMPL_A64__LDUMINALB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78e07000: LDUMINALH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINALH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINALH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINALH_32_memop
        IEM_INSTR_IMPL_A64__LDUMINALH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8e07000: LDUMINAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINAL_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINAL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINAL_32_memop
        IEM_INSTR_IMPL_A64__LDUMINAL_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8e07000: LDUMINAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINAL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINAL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINAL_64_memop
        IEM_INSTR_IMPL_A64__LDUMINAL_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8a07000: LDUMINA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINA_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINA_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINA_32_memop
        IEM_INSTR_IMPL_A64__LDUMINA_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8a07000: LDUMINA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINA_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINA_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINA_64_memop
        IEM_INSTR_IMPL_A64__LDUMINA_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38207000: LDUMINB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38207000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMINB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINB_32_memop
            IEM_INSTR_IMPL_A64__LDUMINB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78207000: LDUMINH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINH_32_memop
        IEM_INSTR_IMPL_A64__LDUMINH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38607000: LDUMINLB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINLB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINLB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINLB_32_memop
        IEM_INSTR_IMPL_A64__LDUMINLB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78607000: LDUMINLH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINLH_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINLH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINLH_32_memop
        IEM_INSTR_IMPL_A64__LDUMINLH_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8607000: LDUMINL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINL_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINL_32_memop
        IEM_INSTR_IMPL_A64__LDUMINL_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8607000: LDUMINL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMINL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMINL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMINL_64_memop
        IEM_INSTR_IMPL_A64__LDUMINL_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8207000: LDUMIN  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMIN_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8207000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: LDUMIN_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMIN_32_memop
            IEM_INSTR_IMPL_A64__LDUMIN_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8207000: LDUMIN  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUMIN_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: LDUMIN_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__LDUMIN_64_memop
        IEM_INSTR_IMPL_A64__LDUMIN_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38400000: LDURB  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDURB_32_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDURB_32_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDURB_32_ldst_unscaled
        IEM_INSTR_IMPL_A64__LDURB_32_ldst_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78400000: LDURH  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDURH_32_ldst_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDURH_32_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDURH_32_ldst_unscaled
    IEM_INSTR_IMPL_A64__LDURH_32_ldst_unscaled(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/38c00000: LDURSB  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDURSB_32_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDURSB_32_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDURSB_32_ldst_unscaled
        IEM_INSTR_IMPL_A64__LDURSB_32_ldst_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38800000: LDURSB  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDURSB_64_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDURSB_64_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDURSB_64_ldst_unscaled
        IEM_INSTR_IMPL_A64__LDURSB_64_ldst_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78c00000: LDURSH  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDURSH_32_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78c00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDURSH_32_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDURSH_32_ldst_unscaled
        IEM_INSTR_IMPL_A64__LDURSH_32_ldst_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78800000: LDURSH  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDURSH_64_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDURSH_64_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDURSH_64_ldst_unscaled
        IEM_INSTR_IMPL_A64__LDURSH_64_ldst_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/b8800000: LDURSW  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDURSW_64_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDURSW_64_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDURSW_64_ldst_unscaled
        IEM_INSTR_IMPL_A64__LDURSW_64_ldst_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/b8400000: LDUR  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUR_32_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: LDUR_32_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDUR_32_ldst_unscaled
        IEM_INSTR_IMPL_A64__LDUR_32_ldst_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/f8400000: LDUR  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUR_64_ldst_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: LDUR_64_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDUR_64_ldst_unscaled
    IEM_INSTR_IMPL_A64__LDUR_64_ldst_unscaled(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/3c400000: LDUR  <Bt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUR_B_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3c400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDUR_B_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDUR_B_ldst_unscaled
            IEM_INSTR_IMPL_A64__LDUR_B_ldst_unscaled(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/fc400000: LDUR  <Dt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUR_D_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xfc400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDUR_D_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDUR_D_ldst_unscaled
            IEM_INSTR_IMPL_A64__LDUR_D_ldst_unscaled(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/7c400000: LDUR  <Ht>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUR_H_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x7c400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDUR_H_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDUR_H_ldst_unscaled
            IEM_INSTR_IMPL_A64__LDUR_H_ldst_unscaled(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3cc00000: LDUR  <Qt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUR_Q_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3cc00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDUR_Q_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDUR_Q_ldst_unscaled
            IEM_INSTR_IMPL_A64__LDUR_Q_ldst_unscaled(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/bc400000: LDUR  <St>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDUR_S_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xbc400000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: LDUR_S_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__LDUR_S_ldst_unscaled
            IEM_INSTR_IMPL_A64__LDUR_S_ldst_unscaled(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff8000/887f0000: LDXP  <Wt1>, <Wt2>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDXP_LP32_ldstexclp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff8000)) == UINT32_C(0x887f0000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        LogFlow(("%018x/%010x: LDXP_LP32_ldstexclp Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDXP_LP32_ldstexclp
        IEM_INSTR_IMPL_A64__LDXP_LP32_ldstexclp(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff8000/c87f0000: LDXP  <Xt1>, <Xt2>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDXP_LP64_ldstexclp, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    LogFlow(("%018x/%010x: LDXP_LP64_ldstexclp Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__LDXP_LP64_ldstexclp
    IEM_INSTR_IMPL_A64__LDXP_LP64_ldstexclp(Rt, Rn, Rt2);
#else
    RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/085f7c00: LDXRB  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDXRB_LR32_ldstexclr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: LDXRB_LR32_ldstexclr Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDXRB_LR32_ldstexclr
    IEM_INSTR_IMPL_A64__LDXRB_LR32_ldstexclr(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/485f7c00: LDXRH  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDXRH_LR32_ldstexclr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: LDXRH_LR32_ldstexclr Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDXRH_LR32_ldstexclr
    IEM_INSTR_IMPL_A64__LDXRH_LR32_ldstexclr(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/885f7c00: LDXR  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDXR_LR32_ldstexclr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: LDXR_LR32_ldstexclr Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDXR_LR32_ldstexclr
    IEM_INSTR_IMPL_A64__LDXR_LR32_ldstexclr(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/c85f7c00: LDXR  <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_LDXR_LR64_ldstexclr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: LDXR_LR64_ldstexclr Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__LDXR_LR64_ldstexclr
    IEM_INSTR_IMPL_A64__LDXR_LR64_ldstexclr(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/1ac02000: LSLV  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_LSLV_32_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac02000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op2        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: LSLV_32_dp_2src Rd=%#x Rn=%#x op2=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op2, Rm));
#ifdef IEM_INSTR_IMPL_A64__LSLV_32_dp_2src
        IEM_INSTR_IMPL_A64__LSLV_32_dp_2src(Rd, Rn, op2, Rm);
#else
        RT_NOREF(Rd, Rn, op2, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9ac02000: LSLV  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_LSLV_64_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac02000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op2        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: LSLV_64_dp_2src Rd=%#x Rn=%#x op2=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op2, Rm));
#ifdef IEM_INSTR_IMPL_A64__LSLV_64_dp_2src
        IEM_INSTR_IMPL_A64__LSLV_64_dp_2src(Rd, Rn, op2, Rm);
#else
        RT_NOREF(Rd, Rn, op2, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac02400: LSRV  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_LSRV_32_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op2        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: LSRV_32_dp_2src Rd=%#x Rn=%#x op2=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op2, Rm));
#ifdef IEM_INSTR_IMPL_A64__LSRV_32_dp_2src
    IEM_INSTR_IMPL_A64__LSRV_32_dp_2src(Rd, Rn, op2, Rm);
#else
    RT_NOREF(Rd, Rn, op2, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/9ac02400: LSRV  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_LSRV_64_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op2        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: LSRV_64_dp_2src Rd=%#x Rn=%#x op2=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op2, Rm));
#ifdef IEM_INSTR_IMPL_A64__LSRV_64_dp_2src
    IEM_INSTR_IMPL_A64__LSRV_64_dp_2src(Rd, Rn, op2, Rm);
#else
    RT_NOREF(Rd, Rn, op2, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe09c00/4e801000: LUTI2  <Vd>.16B, { <Vn>.16B }, <Vm>[<index>]
   Instruction Set: A64  Groups: asimdtbl, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_LUTI2_asimdtbl_L5, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe09c00)) == UINT32_C(0x4e801000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const len        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LUT*/)
        {
            LogFlow(("%018x/%010x: LUTI2_asimdtbl_L5 Rd=%#x Rn=%#x len=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, len, Rm));
#ifdef IEM_INSTR_IMPL_A64__LUTI2_asimdtbl_L5
            IEM_INSTR_IMPL_A64__LUTI2_asimdtbl_L5(Rd, Rn, len, Rm);
#else
            RT_NOREF(Rd, Rn, len, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08c00/4ec00000: LUTI2  <Vd>.8H, { <Vn>.8H }, <Vm>[<index>]
   Instruction Set: A64  Groups: asimdtbl, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_LUTI2_asimdtbl_L6, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08c00)) == UINT32_C(0x4ec00000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const len        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LUT*/)
        {
            LogFlow(("%018x/%010x: LUTI2_asimdtbl_L6 Rd=%#x Rn=%#x op=%u len=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, len, Rm));
#ifdef IEM_INSTR_IMPL_A64__LUTI2_asimdtbl_L6
            IEM_INSTR_IMPL_A64__LUTI2_asimdtbl_L6(Rd, Rn, op, len, Rm);
#else
            RT_NOREF(Rd, Rn, op, len, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0bc00/4e402000: LUTI4  <Vd>.16B, { <Vn>.16B }, <Vm>[<index>]
   Instruction Set: A64  Groups: asimdtbl, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_LUTI4_asimdtbl_L5, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0bc00)) == UINT32_C(0x4e402000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const len        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LUT*/)
        {
            LogFlow(("%018x/%010x: LUTI4_asimdtbl_L5 Rd=%#x Rn=%#x len=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, len, Rm));
#ifdef IEM_INSTR_IMPL_A64__LUTI4_asimdtbl_L5
            IEM_INSTR_IMPL_A64__LUTI4_asimdtbl_L5(Rd, Rn, len, Rm);
#else
            RT_NOREF(Rd, Rn, len, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe09c00/4e401000: LUTI4  <Vd>.8H, { <Vn1>.8H, <Vn2>.8H }, <Vm>[<index>]
   Instruction Set: A64  Groups: asimdtbl, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_LUTI4_asimdtbl_L7, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe09c00)) == UINT32_C(0x4e401000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const len        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LUT*/)
        {
            LogFlow(("%018x/%010x: LUTI4_asimdtbl_L7 Rd=%#x Rn=%#x len=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, len, Rm));
#ifdef IEM_INSTR_IMPL_A64__LUTI4_asimdtbl_L7
            IEM_INSTR_IMPL_A64__LUTI4_asimdtbl_L7(Rd, Rn, len, Rm);
#else
            RT_NOREF(Rd, Rn, len, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/9b600000: MADDPT  <Xd>, <Xn>, <Xm>, <Xa>
   Instruction Set: A64  Groups: dp_3src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_MADDPT_64A_dp_3src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x9b600000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CPA*/)
        {
            LogFlow(("%018x/%010x: MADDPT_64A_dp_3src Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__MADDPT_64A_dp_3src
            IEM_INSTR_IMPL_A64__MADDPT_64A_dp_3src(Rd, Rn, Ra, Rm);
#else
            RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1b000000: MADD  <Wd>, <Wn>, <Wm>, <Wa>
   Instruction Set: A64  Groups: dp_3src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_MADD_32A_dp_3src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: MADD_32A_dp_3src Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__MADD_32A_dp_3src
    IEM_INSTR_IMPL_A64__MADD_32A_dp_3src(Rd, Rn, Ra, Rm);
#else
    RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe08000/9b000000: MADD  <Xd>, <Xn>, <Xm>, <Xa>
   Instruction Set: A64  Groups: dp_3src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_MADD_64A_dp_3src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: MADD_64A_dp_3src Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__MADD_64A_dp_3src
    IEM_INSTR_IMPL_A64__MADD_64A_dp_3src(Rd, Rn, Ra, Rm);
#else
    RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf00f400/2f000000: MLA  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MLA_asimdelem_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MLA_asimdelem_R Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__MLA_asimdelem_R
        IEM_INSTR_IMPL_A64__MLA_asimdelem_R(Rd, Rn, H, o2, Rm, M, L, size, Q);
#else
        RT_NOREF(Rd, Rn, H, o2, Rm, M, L, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e209400: MLA  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MLA_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MLA_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__MLA_asimdsame_only
        IEM_INSTR_IMPL_A64__MLA_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/2f004000: MLS  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MLS_asimdelem_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x2f004000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: MLS_asimdelem_R Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__MLS_asimdelem_R
            IEM_INSTR_IMPL_A64__MLS_asimdelem_R(Rd, Rn, H, o2, Rm, M, L, size, Q);
#else
            RT_NOREF(Rd, Rn, H, o2, Rm, M, L, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e209400: MLS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MLS_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e209400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: MLS_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__MLS_asimdsame_only
            IEM_INSTR_IMPL_A64__MLS_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff8fc00/6f00e400: MOVI  <Vd>.2D, #<imm>
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MOVI_asimdimm_D2_d, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MOVI_asimdimm_D2_d Rd=%#x h=%u g=%u f=%u e=%u d=%u c=%u b=%u a=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, c, b, a));
#ifdef IEM_INSTR_IMPL_A64__MOVI_asimdimm_D2_d
        IEM_INSTR_IMPL_A64__MOVI_asimdimm_D2_d(Rd, h, g, f, e, d, c, b, a);
#else
        RT_NOREF(Rd, h, g, f, e, d, c, b, a, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff8fc00/2f00e400: MOVI  <Dd>, #<imm>
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MOVI_asimdimm_D_ds, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MOVI_asimdimm_D_ds Rd=%#x h=%u g=%u f=%u e=%u d=%u c=%u b=%u a=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, c, b, a));
#ifdef IEM_INSTR_IMPL_A64__MOVI_asimdimm_D_ds
        IEM_INSTR_IMPL_A64__MOVI_asimdimm_D_ds(Rd, h, g, f, e, d, c, b, a);
#else
        RT_NOREF(Rd, h, g, f, e, d, c, b, a, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bff8dc00/0f008400: MOVI  <Vd>.<T>, #<imm8>{, LSL #<amount>}
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MOVI_asimdimm_L_hl, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const cmode      = (uOpcode >> 12) & 0x0000000f;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MOVI_asimdimm_L_hl Rd=%#x h=%u g=%u f=%u e=%u d=%u cmode=%#x c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, cmode, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__MOVI_asimdimm_L_hl
        IEM_INSTR_IMPL_A64__MOVI_asimdimm_L_hl(Rd, h, g, f, e, d, cmode, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, cmode, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bff89c00/0f000400: MOVI  <Vd>.<T>, #<imm8>{, LSL #<amount>}
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MOVI_asimdimm_L_sl, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const cmode      = (uOpcode >> 12) & 0x0000000f;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MOVI_asimdimm_L_sl Rd=%#x h=%u g=%u f=%u e=%u d=%u cmode=%#x c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, cmode, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__MOVI_asimdimm_L_sl
        IEM_INSTR_IMPL_A64__MOVI_asimdimm_L_sl(Rd, h, g, f, e, d, cmode, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, cmode, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bff8ec00/0f00c400: MOVI  <Vd>.<T>, #<imm8>, MSL #<amount>
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MOVI_asimdimm_M_sm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const cmode      = (uOpcode >> 12) & 0x0000000f;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MOVI_asimdimm_M_sm Rd=%#x h=%u g=%u f=%u e=%u d=%u cmode=%#x c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, cmode, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__MOVI_asimdimm_M_sm
        IEM_INSTR_IMPL_A64__MOVI_asimdimm_M_sm(Rd, h, g, f, e, d, cmode, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, cmode, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bff8fc00/0f00e400: MOVI  <Vd>.<T>, #<imm8>{, LSL #0}
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MOVI_asimdimm_N_b, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MOVI_asimdimm_N_b Rd=%#x h=%u g=%u f=%u e=%u d=%u c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__MOVI_asimdimm_N_b
        IEM_INSTR_IMPL_A64__MOVI_asimdimm_N_b(Rd, h, g, f, e, d, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/72800000: MOVK  <Wd>, #<imm>{, LSL #<shift>}
   Instruction Set: A64  Groups: movewide, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_MOVK_32_movewide, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x72800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        uint32_t const hw         = (uOpcode >> 21) & 0x00000003;
        LogFlow(("%018x/%010x: MOVK_32_movewide Rd=%#x imm16=%#x hw=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm16, hw));
#ifdef IEM_INSTR_IMPL_A64__MOVK_32_movewide
        IEM_INSTR_IMPL_A64__MOVK_32_movewide(Rd, imm16, hw);
#else
        RT_NOREF(Rd, imm16, hw, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff800000/f2800000: MOVK  <Xd>, #<imm>{, LSL #<shift>}
   Instruction Set: A64  Groups: movewide, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_MOVK_64_movewide, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff800000)) == UINT32_C(0xf2800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        uint32_t const hw         = (uOpcode >> 21) & 0x00000003;
        LogFlow(("%018x/%010x: MOVK_64_movewide Rd=%#x imm16=%#x hw=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm16, hw));
#ifdef IEM_INSTR_IMPL_A64__MOVK_64_movewide
        IEM_INSTR_IMPL_A64__MOVK_64_movewide(Rd, imm16, hw);
#else
        RT_NOREF(Rd, imm16, hw, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/12800000: MOVN  <Wd>, #<imm>{, LSL #<shift>}
   Instruction Set: A64  Groups: movewide, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_MOVN_32_movewide, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x12800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        uint32_t const hw         = (uOpcode >> 21) & 0x00000003;
        LogFlow(("%018x/%010x: MOVN_32_movewide Rd=%#x imm16=%#x hw=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm16, hw));
#ifdef IEM_INSTR_IMPL_A64__MOVN_32_movewide
        IEM_INSTR_IMPL_A64__MOVN_32_movewide(Rd, imm16, hw);
#else
        RT_NOREF(Rd, imm16, hw, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff800000/92800000: MOVN  <Xd>, #<imm>{, LSL #<shift>}
   Instruction Set: A64  Groups: movewide, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_MOVN_64_movewide, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff800000)) == UINT32_C(0x92800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        uint32_t const hw         = (uOpcode >> 21) & 0x00000003;
        LogFlow(("%018x/%010x: MOVN_64_movewide Rd=%#x imm16=%#x hw=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm16, hw));
#ifdef IEM_INSTR_IMPL_A64__MOVN_64_movewide
        IEM_INSTR_IMPL_A64__MOVN_64_movewide(Rd, imm16, hw);
#else
        RT_NOREF(Rd, imm16, hw, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/52800000: MOVZ  <Wd>, #<imm>{, LSL #<shift>}
   Instruction Set: A64  Groups: movewide, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_MOVZ_32_movewide, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x52800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        uint32_t const hw         = (uOpcode >> 21) & 0x00000003;
        LogFlow(("%018x/%010x: MOVZ_32_movewide Rd=%#x imm16=%#x hw=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm16, hw));
#ifdef IEM_INSTR_IMPL_A64__MOVZ_32_movewide
        IEM_INSTR_IMPL_A64__MOVZ_32_movewide(Rd, imm16, hw);
#else
        RT_NOREF(Rd, imm16, hw, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff800000/d2800000: MOVZ  <Xd>, #<imm>{, LSL #<shift>}
   Instruction Set: A64  Groups: movewide, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_MOVZ_64_movewide, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff800000)) == UINT32_C(0xd2800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        uint32_t const hw         = (uOpcode >> 21) & 0x00000003;
        LogFlow(("%018x/%010x: MOVZ_64_movewide Rd=%#x imm16=%#x hw=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm16, hw));
#ifdef IEM_INSTR_IMPL_A64__MOVZ_64_movewide
        IEM_INSTR_IMPL_A64__MOVZ_64_movewide(Rd, imm16, hw);
#else
        RT_NOREF(Rd, imm16, hw, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff00000/d5700000: MRRS  <Xt>, <Xt+1>, {<systemreg> | S<op0>_<op1>_<Cn>_<Cm>_<op2>}
   Instruction Set: A64  Groups: systemmovepr, control */
FNIEMOP_DEF_1(iemDecodeA64_MRRS_RS_systemmovepr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const op2        = (uOpcode >>  5) & 0x00000007;
    uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
    uint32_t const CRn        = (uOpcode >> 12) & 0x0000000f;
    uint32_t const op1        = (uOpcode >> 16) & 0x00000007;
    uint32_t const o0         = (uOpcode >> 19) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSysReg128 /*FEAT_SYSREG128*/)
    {
        LogFlow(("%018x/%010x: MRRS_RS_systemmovepr Rt=%#x op2=%u CRm=%#x CRn=%#x op1=%u o0=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, op2, CRm, CRn, op1, o0));
#ifdef IEM_INSTR_IMPL_A64__MRRS_RS_systemmovepr
        IEM_INSTR_IMPL_A64__MRRS_RS_systemmovepr(Rt, op2, CRm, CRn, op1, o0);
#else
        RT_NOREF(Rt, op2, CRm, CRn, op1, o0, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff00000/d5300000: MRS  <Xt>, {<systemreg> | S<op0>_<op1>_<Cn>_<Cm>_<op2>}
   Instruction Set: A64  Groups: systemmove, control */
FNIEMOP_DEF_1(iemDecodeA64_MRS_RS_systemmove, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const op2        = (uOpcode >>  5) & 0x00000007;
    uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
    uint32_t const CRn        = (uOpcode >> 12) & 0x0000000f;
    uint32_t const op1        = (uOpcode >> 16) & 0x00000007;
    uint32_t const o0         = (uOpcode >> 19) & 0x00000001;
    LogFlow(("%018x/%010x: MRS_RS_systemmove Rt=%#x op2=%u CRm=%#x CRn=%#x op1=%u o0=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, op2, CRm, CRn, op1, o0));
#ifdef IEM_INSTR_IMPL_A64__MRS_RS_systemmove
    IEM_INSTR_IMPL_A64__MRS_RS_systemmove(Rt, op2, CRm, CRn, op1, o0);
#else
    RT_NOREF(Rt, op2, CRm, CRn, op1, o0, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fff00000/d5500000: MSRR  {<systemreg> | S<op0>_<op1>_<Cn>_<Cm>_<op2>}, <Xt>, <Xt+1>
   Instruction Set: A64  Groups: systemmovepr, control */
FNIEMOP_DEF_1(iemDecodeA64_MSRR_SR_systemmovepr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const op2        = (uOpcode >>  5) & 0x00000007;
    uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
    uint32_t const CRn        = (uOpcode >> 12) & 0x0000000f;
    uint32_t const op1        = (uOpcode >> 16) & 0x00000007;
    uint32_t const o0         = (uOpcode >> 19) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSysReg128 /*FEAT_SYSREG128*/)
    {
        LogFlow(("%018x/%010x: MSRR_SR_systemmovepr Rt=%#x op2=%u CRm=%#x CRn=%#x op1=%u o0=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, op2, CRm, CRn, op1, o0));
#ifdef IEM_INSTR_IMPL_A64__MSRR_SR_systemmovepr
        IEM_INSTR_IMPL_A64__MSRR_SR_systemmovepr(Rt, op2, CRm, CRn, op1, o0);
#else
        RT_NOREF(Rt, op2, CRm, CRn, op1, o0, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff8f01f/d500401f: MSR  <pstatefield>, #<imm>
   Instruction Set: A64  Groups: pstate, control */
FNIEMOP_DEF_1(iemDecodeA64_MSR_SI_pstate, uint32_t, uOpcode)
{
    uint32_t const op2        = (uOpcode >>  5) & 0x00000007;
    uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
    uint32_t const op1        = (uOpcode >> 16) & 0x00000007;
    if (!(op1 == 0 && ((op2 & 6) == 0 || op2 == 2)))
    {
        LogFlow(("%018x/%010x: MSR_SI_pstate op2=%u CRm=%#x op1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, op2, CRm, op1));
#ifdef IEM_INSTR_IMPL_A64__MSR_SI_pstate
        IEM_INSTR_IMPL_A64__MSR_SI_pstate(op2, CRm, op1);
#else
        RT_NOREF(op2, CRm, op1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff00000/d5100000: MSR  {<systemreg> | S<op0>_<op1>_<Cn>_<Cm>_<op2>}, <Xt>
   Instruction Set: A64  Groups: systemmove, control */
FNIEMOP_DEF_1(iemDecodeA64_MSR_SR_systemmove, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const op2        = (uOpcode >>  5) & 0x00000007;
    uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
    uint32_t const CRn        = (uOpcode >> 12) & 0x0000000f;
    uint32_t const op1        = (uOpcode >> 16) & 0x00000007;
    uint32_t const o0         = (uOpcode >> 19) & 0x00000001;
    LogFlow(("%018x/%010x: MSR_SR_systemmove Rt=%#x op2=%u CRm=%#x CRn=%#x op1=%u o0=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, op2, CRm, CRn, op1, o0));
#ifdef IEM_INSTR_IMPL_A64__MSR_SR_systemmove
    IEM_INSTR_IMPL_A64__MSR_SR_systemmove(Rt, op2, CRm, CRn, op1, o0);
#else
    RT_NOREF(Rt, op2, CRm, CRn, op1, o0, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe08000/9b608000: MSUBPT  <Xd>, <Xn>, <Xm>, <Xa>
   Instruction Set: A64  Groups: dp_3src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_MSUBPT_64A_dp_3src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x9b608000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CPA*/)
        {
            LogFlow(("%018x/%010x: MSUBPT_64A_dp_3src Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__MSUBPT_64A_dp_3src
            IEM_INSTR_IMPL_A64__MSUBPT_64A_dp_3src(Rd, Rn, Ra, Rm);
#else
            RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/1b008000: MSUB  <Wd>, <Wn>, <Wm>, <Wa>
   Instruction Set: A64  Groups: dp_3src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_MSUB_32A_dp_3src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: MSUB_32A_dp_3src Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__MSUB_32A_dp_3src
    IEM_INSTR_IMPL_A64__MSUB_32A_dp_3src(Rd, Rn, Ra, Rm);
#else
    RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe08000/9b008000: MSUB  <Xd>, <Xn>, <Xm>, <Xa>
   Instruction Set: A64  Groups: dp_3src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_MSUB_64A_dp_3src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: MSUB_64A_dp_3src Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__MSUB_64A_dp_3src
    IEM_INSTR_IMPL_A64__MSUB_64A_dp_3src(Rd, Rn, Ra, Rm);
#else
    RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf00f400/0f008000: MUL  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MUL_asimdelem_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MUL_asimdelem_R Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__MUL_asimdelem_R
        IEM_INSTR_IMPL_A64__MUL_asimdelem_R(Rd, Rn, H, Rm, M, L, size, Q);
#else
        RT_NOREF(Rd, Rn, H, Rm, M, L, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e209c00: MUL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MUL_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MUL_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__MUL_asimdsame_only
        IEM_INSTR_IMPL_A64__MUL_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bff8dc00/2f008400: MVNI  <Vd>.<T>, #<imm8>{, LSL #<amount>}
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MVNI_asimdimm_L_hl, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const cmode      = (uOpcode >> 12) & 0x0000000f;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MVNI_asimdimm_L_hl Rd=%#x h=%u g=%u f=%u e=%u d=%u cmode=%#x c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, cmode, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__MVNI_asimdimm_L_hl
        IEM_INSTR_IMPL_A64__MVNI_asimdimm_L_hl(Rd, h, g, f, e, d, cmode, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, cmode, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bff89c00/2f000400: MVNI  <Vd>.<T>, #<imm8>{, LSL #<amount>}
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MVNI_asimdimm_L_sl, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const cmode      = (uOpcode >> 12) & 0x0000000f;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MVNI_asimdimm_L_sl Rd=%#x h=%u g=%u f=%u e=%u d=%u cmode=%#x c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, cmode, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__MVNI_asimdimm_L_sl
        IEM_INSTR_IMPL_A64__MVNI_asimdimm_L_sl(Rd, h, g, f, e, d, cmode, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, cmode, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bff8ec00/2f00c400: MVNI  <Vd>.<T>, #<imm8>, MSL #<amount>
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_MVNI_asimdimm_M_sm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const cmode      = (uOpcode >> 12) & 0x0000000f;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: MVNI_asimdimm_M_sm Rd=%#x h=%u g=%u f=%u e=%u d=%u cmode=%#x c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, cmode, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__MVNI_asimdimm_M_sm
        IEM_INSTR_IMPL_A64__MVNI_asimdimm_M_sm(Rd, h, g, f, e, d, cmode, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, cmode, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e20b800: NEG  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_NEG_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: NEG_asimdmisc_R Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__NEG_asimdmisc_R
        IEM_INSTR_IMPL_A64__NEG_asimdmisc_R(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7ee0b800: NEG  D<d>, D<n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_NEG_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: NEG_asisdmisc_R Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__NEG_asisdmisc_R
        IEM_INSTR_IMPL_A64__NEG_asisdmisc_R(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503201f: NOP
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_NOP_HI_hints, uint32_t, uOpcode)
{
    LogFlow(("%018x/%010x: NOP_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__NOP_HI_hints
    IEM_INSTR_IMPL_A64__NOP_HI_hints();
#else
    RT_NOREF(pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bffffc00/2e205800: NOT  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_NOT_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: NOT_asimdmisc_R Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__NOT_asimdmisc_R
        IEM_INSTR_IMPL_A64__NOT_asimdmisc_R(Rd, Rn, Q);
#else
        RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff200000/2a200000: ORN  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ORN_32_log_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: ORN_32_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__ORN_32_log_shift
    IEM_INSTR_IMPL_A64__ORN_32_log_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/aa200000: ORN  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ORN_64_log_shift, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff200000)) == UINT32_C(0xaa200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
        LogFlow(("%018x/%010x: ORN_64_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__ORN_64_log_shift
        IEM_INSTR_IMPL_A64__ORN_64_log_shift(Rd, Rn, imm6, Rm, shift);
#else
        RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0ee01c00: ORN  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ORN_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0ee01c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ORN_asimdsame_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ORN_asimdsame_only
            IEM_INSTR_IMPL_A64__ORN_asimdsame_only(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/32000000: ORR  <Wd|WSP>, <Wn>, #<imm>
   Instruction Set: A64  Groups: log_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_ORR_32_log_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
    LogFlow(("%018x/%010x: ORR_32_log_imm Rd=%#x Rn=%#x imms=%#x immr=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr));
#ifdef IEM_INSTR_IMPL_A64__ORR_32_log_imm
    IEM_INSTR_IMPL_A64__ORR_32_log_imm(Rd, Rn, imms, immr);
#else
    RT_NOREF(Rd, Rn, imms, immr, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/2a000000: ORR  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ORR_32_log_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: ORR_32_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__ORR_32_log_shift
    IEM_INSTR_IMPL_A64__ORR_32_log_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff800000/b2000000: ORR  <Xd|SP>, <Xn>, #<imm>
   Instruction Set: A64  Groups: log_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_ORR_64_log_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const N          = (uOpcode >> 22) & 0x00000001;
    LogFlow(("%018x/%010x: ORR_64_log_imm Rd=%#x Rn=%#x imms=%#x immr=%#x N=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr, N));
#ifdef IEM_INSTR_IMPL_A64__ORR_64_log_imm
    IEM_INSTR_IMPL_A64__ORR_64_log_imm(Rd, Rn, imms, immr, N);
#else
    RT_NOREF(Rd, Rn, imms, immr, N, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/aa000000: ORR  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: log_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_ORR_64_log_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: ORR_64_log_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__ORR_64_log_shift
    IEM_INSTR_IMPL_A64__ORR_64_log_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bff8dc00/0f009400: ORR  <Vd>.<T>, #<imm8>{, LSL #<amount>}
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ORR_asimdimm_L_hl, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const cmode      = (uOpcode >> 12) & 0x0000000f;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ORR_asimdimm_L_hl Rd=%#x h=%u g=%u f=%u e=%u d=%u cmode=%#x c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, cmode, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__ORR_asimdimm_L_hl
        IEM_INSTR_IMPL_A64__ORR_asimdimm_L_hl(Rd, h, g, f, e, d, cmode, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, cmode, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bff89c00/0f001400: ORR  <Vd>.<T>, #<imm8>{, LSL #<amount>}
   Instruction Set: A64  Groups: asimdimm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ORR_asimdimm_L_sl, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const h          = (uOpcode >>  5) & 0x00000001;
    uint32_t const g          = (uOpcode >>  6) & 0x00000001;
    uint32_t const f          = (uOpcode >>  7) & 0x00000001;
    uint32_t const e          = (uOpcode >>  8) & 0x00000001;
    uint32_t const d          = (uOpcode >>  9) & 0x00000001;
    uint32_t const cmode      = (uOpcode >> 12) & 0x0000000f;
    uint32_t const c          = (uOpcode >> 16) & 0x00000001;
    uint32_t const b          = (uOpcode >> 17) & 0x00000001;
    uint32_t const a          = (uOpcode >> 18) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ORR_asimdimm_L_sl Rd=%#x h=%u g=%u f=%u e=%u d=%u cmode=%#x c=%u b=%u a=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, h, g, f, e, d, cmode, c, b, a, Q));
#ifdef IEM_INSTR_IMPL_A64__ORR_asimdimm_L_sl
        IEM_INSTR_IMPL_A64__ORR_asimdimm_L_sl(Rd, h, g, f, e, d, cmode, c, b, a, Q);
#else
        RT_NOREF(Rd, h, g, f, e, d, cmode, c, b, a, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0ea01c00: ORR  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ORR_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ORR_asimdsame_only Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ORR_asimdsame_only
        IEM_INSTR_IMPL_A64__ORR_asimdsame_only(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/dac10800: PACDA  <Xd>, <Xn|SP>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACDA_64P_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: PACDA_64P_dp_1src Rd=%#x Rn=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Z));
#ifdef IEM_INSTR_IMPL_A64__PACDA_64P_dp_1src
        IEM_INSTR_IMPL_A64__PACDA_64P_dp_1src(Rd, Rn, Z);
#else
        RT_NOREF(Rd, Rn, Z, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/dac10c00: PACDB  <Xd>, <Xn|SP>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACDB_64P_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: PACDB_64P_dp_1src Rd=%#x Rn=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Z));
#ifdef IEM_INSTR_IMPL_A64__PACDB_64P_dp_1src
        IEM_INSTR_IMPL_A64__PACDB_64P_dp_1src(Rd, Rn, Z);
#else
        RT_NOREF(Rd, Rn, Z, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/dac12be0: PACDZA  <Xd>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACDZA_64Z_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xdac12be0))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: PACDZA_64Z_dp_1src Rd=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Z));
#ifdef IEM_INSTR_IMPL_A64__PACDZA_64Z_dp_1src
            IEM_INSTR_IMPL_A64__PACDZA_64Z_dp_1src(Rd, Z);
#else
            RT_NOREF(Rd, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/dac12fe0: PACDZB  <Xd>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACDZB_64Z_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xdac12fe0))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: PACDZB_64Z_dp_1src Rd=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Z));
#ifdef IEM_INSTR_IMPL_A64__PACDZB_64Z_dp_1src
            IEM_INSTR_IMPL_A64__PACDZB_64Z_dp_1src(Rd, Z);
#else
            RT_NOREF(Rd, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9ac03000: PACGA  <Xd>, <Xn>, <Xm|SP>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACGA_64P_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac03000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: PACGA_64P_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__PACGA_64P_dp_2src
            IEM_INSTR_IMPL_A64__PACGA_64P_dp_2src(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/dac18bfe: PACIA171615
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACIA171615_64LR_dp_1src, uint32_t, uOpcode)
{
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
    {
        LogFlow(("%018x/%010x: PACIA171615_64LR_dp_1src\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACIA171615_64LR_dp_1src
        IEM_INSTR_IMPL_A64__PACIA171615_64LR_dp_1src();
#else
        RT_NOREF(pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503211f: PACIA1716
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_PACIA1716_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503211f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: PACIA1716_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACIA1716_HI_hints
            IEM_INSTR_IMPL_A64__PACIA1716_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/dac1a3fe: PACIASPPC
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACIASPPC_64LR_dp_1src, uint32_t, uOpcode)
{
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
    {
        LogFlow(("%018x/%010x: PACIASPPC_64LR_dp_1src\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACIASPPC_64LR_dp_1src
        IEM_INSTR_IMPL_A64__PACIASPPC_64LR_dp_1src();
#else
        RT_NOREF(pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503233f: PACIASP
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_PACIASP_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503233f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: PACIASP_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACIASP_HI_hints
            IEM_INSTR_IMPL_A64__PACIASP_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503231f: PACIAZ
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_PACIAZ_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503231f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: PACIAZ_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACIAZ_HI_hints
            IEM_INSTR_IMPL_A64__PACIAZ_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/dac10000: PACIA  <Xd>, <Xn|SP>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACIA_64P_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: PACIA_64P_dp_1src Rd=%#x Rn=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Z));
#ifdef IEM_INSTR_IMPL_A64__PACIA_64P_dp_1src
        IEM_INSTR_IMPL_A64__PACIA_64P_dp_1src(Rd, Rn, Z);
#else
        RT_NOREF(Rd, Rn, Z, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/dac18ffe: PACIB171615
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACIB171615_64LR_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xdac18ffe))
    {
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
        {
            LogFlow(("%018x/%010x: PACIB171615_64LR_dp_1src\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACIB171615_64LR_dp_1src
            IEM_INSTR_IMPL_A64__PACIB171615_64LR_dp_1src();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503215f: PACIB1716
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_PACIB1716_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503215f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: PACIB1716_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACIB1716_HI_hints
            IEM_INSTR_IMPL_A64__PACIB1716_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/dac1a7fe: PACIBSPPC
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACIBSPPC_64LR_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xdac1a7fe))
    {
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
        {
            LogFlow(("%018x/%010x: PACIBSPPC_64LR_dp_1src\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACIBSPPC_64LR_dp_1src
            IEM_INSTR_IMPL_A64__PACIBSPPC_64LR_dp_1src();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503237f: PACIBSP
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_PACIBSP_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503237f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: PACIBSP_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACIBSP_HI_hints
            IEM_INSTR_IMPL_A64__PACIBSP_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503235f: PACIBZ
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_PACIBZ_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503235f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: PACIBZ_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACIBZ_HI_hints
            IEM_INSTR_IMPL_A64__PACIBZ_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/dac10400: PACIB  <Xd>, <Xn|SP>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACIB_64P_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac10400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: PACIB_64P_dp_1src Rd=%#x Rn=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Z));
#ifdef IEM_INSTR_IMPL_A64__PACIB_64P_dp_1src
            IEM_INSTR_IMPL_A64__PACIB_64P_dp_1src(Rd, Rn, Z);
#else
            RT_NOREF(Rd, Rn, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/dac123e0: PACIZA  <Xd>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACIZA_64Z_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: PACIZA_64Z_dp_1src Rd=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Z));
#ifdef IEM_INSTR_IMPL_A64__PACIZA_64Z_dp_1src
        IEM_INSTR_IMPL_A64__PACIZA_64Z_dp_1src(Rd, Z);
#else
        RT_NOREF(Rd, Z, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/dac127e0: PACIZB  <Xd>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACIZB_64Z_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xdac127e0))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Z          = (uOpcode >> 13) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: PACIZB_64Z_dp_1src Rd=%#x Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Z));
#ifdef IEM_INSTR_IMPL_A64__PACIZB_64Z_dp_1src
            IEM_INSTR_IMPL_A64__PACIZB_64Z_dp_1src(Rd, Z);
#else
            RT_NOREF(Rd, Z, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d50324ff: PACM
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_PACM_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd50324ff))
    {
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
        {
            LogFlow(("%018x/%010x: PACM_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACM_HI_hints
            IEM_INSTR_IMPL_A64__PACM_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/dac183fe: PACNBIASPPC
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACNBIASPPC_64LR_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xdac183fe))
    {
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
        {
            LogFlow(("%018x/%010x: PACNBIASPPC_64LR_dp_1src\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACNBIASPPC_64LR_dp_1src
            IEM_INSTR_IMPL_A64__PACNBIASPPC_64LR_dp_1src();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/dac187fe: PACNBIBSPPC
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_PACNBIBSPPC_64LR_dp_1src, uint32_t, uOpcode)
{
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
    {
        LogFlow(("%018x/%010x: PACNBIBSPPC_64LR_dp_1src\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PACNBIBSPPC_64LR_dp_1src
        IEM_INSTR_IMPL_A64__PACNBIBSPPC_64LR_dp_1src();
#else
        RT_NOREF(pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e20e000: PMULL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_PMULL_asimddiff_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e20e000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: PMULL_asimddiff_L Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__PMULL_asimddiff_L
            IEM_INSTR_IMPL_A64__PMULL_asimddiff_L(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e209c00: PMUL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_PMUL_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e209c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: PMUL_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__PMUL_asimdsame_only
            IEM_INSTR_IMPL_A64__PMUL_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/f9800000: PRFM  {<prfop> | #<imm5>}, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_PRFM_P_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xf9800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        LogFlow(("%018x/%010x: PRFM_P_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__PRFM_P_ldst_pos
        IEM_INSTR_IMPL_A64__PRFM_P_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/f8a00800: PRFM  {<prfop> | #<imm5>}, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_PRFM_P_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (!((Rt & 0x18) == 0x18) && (option & 2) == 2)
    {
        LogFlow(("%018x/%010x: PRFM_P_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__PRFM_P_ldst_regoff
        IEM_INSTR_IMPL_A64__PRFM_P_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff000000/d8000000: PRFM  {<prfop> | #<imm5>}, <label>
   Instruction Set: A64  Groups: loadlit, ldst */
FNIEMOP_DEF_1(iemDecodeA64_PRFM_P_loadlit, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm19      = (uOpcode >>  5) & 0x0007ffff;
    LogFlow(("%018x/%010x: PRFM_P_loadlit Rt=%#x imm19=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm19));
#ifdef IEM_INSTR_IMPL_A64__PRFM_P_loadlit
    IEM_INSTR_IMPL_A64__PRFM_P_loadlit(Rt, imm19);
#else
    RT_NOREF(Rt, imm19, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/f8800000: PRFUM  {<prfop> | #<imm5>}, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_PRFUM_P_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xf8800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: PRFUM_P_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__PRFUM_P_ldst_unscaled
        IEM_INSTR_IMPL_A64__PRFUM_P_ldst_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503223f: PSB  CSYNC
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_PSB_HC_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503223f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSpe /*FEAT_SPE*/)
        {
            LogFlow(("%018x/%010x: PSB_HC_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__PSB_HC_hints
            IEM_INSTR_IMPL_A64__PSB_HC_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e204000: RADDHN2  <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_RADDHN_asimddiff_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: RADDHN_asimddiff_N Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__RADDHN_asimddiff_N
        IEM_INSTR_IMPL_A64__RADDHN_asimddiff_N(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/ce608c00: RAX1  <Vd>.2D, <Vn>.2D, <Vm>.2D
   Instruction Set: A64  Groups: cryptosha512_3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_RAX1_VVV2_cryptosha512_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xce608c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha3 /*FEAT_SHA3*/)
        {
            LogFlow(("%018x/%010x: RAX1_VVV2_cryptosha512_3 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__RAX1_VVV2_cryptosha512_3
            IEM_INSTR_IMPL_A64__RAX1_VVV2_cryptosha512_3(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ac00000: RBIT  <Wd>, <Wn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_RBIT_32_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: RBIT_32_dp_1src Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__RBIT_32_dp_1src
    IEM_INSTR_IMPL_A64__RBIT_32_dp_1src(Rd, Rn);
#else
    RT_NOREF(Rd, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/dac00000: RBIT  <Xd>, <Xn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_RBIT_64_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: RBIT_64_dp_1src Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__RBIT_64_dp_1src
    IEM_INSTR_IMPL_A64__RBIT_64_dp_1src(Rd, Rn);
#else
    RT_NOREF(Rd, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bffffc00/2e605800: RBIT  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_RBIT_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2e605800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: RBIT_asimdmisc_R Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__RBIT_asimdmisc_R
            IEM_INSTR_IMPL_A64__RBIT_asimdmisc_R(Rd, Rn, Q);
#else
            RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19e00800: RCWCASAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCASAL_C64_rcwcomswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWCASAL_C64_rcwcomswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWCASAL_C64_rcwcomswap
        IEM_INSTR_IMPL_A64__RCWCASAL_C64_rcwcomswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19a00800: RCWCASA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCASA_C64_rcwcomswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWCASA_C64_rcwcomswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWCASA_C64_rcwcomswap
        IEM_INSTR_IMPL_A64__RCWCASA_C64_rcwcomswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19600800: RCWCASL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCASL_C64_rcwcomswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWCASL_C64_rcwcomswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWCASL_C64_rcwcomswap
        IEM_INSTR_IMPL_A64__RCWCASL_C64_rcwcomswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19e00c00: RCWCASPAL  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCASPAL_C64_rcwcomswappr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWCASPAL_C64_rcwcomswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWCASPAL_C64_rcwcomswappr
        IEM_INSTR_IMPL_A64__RCWCASPAL_C64_rcwcomswappr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19a00c00: RCWCASPA  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCASPA_C64_rcwcomswappr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWCASPA_C64_rcwcomswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWCASPA_C64_rcwcomswappr
        IEM_INSTR_IMPL_A64__RCWCASPA_C64_rcwcomswappr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19600c00: RCWCASPL  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCASPL_C64_rcwcomswappr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWCASPL_C64_rcwcomswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWCASPL_C64_rcwcomswappr
        IEM_INSTR_IMPL_A64__RCWCASPL_C64_rcwcomswappr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19200c00: RCWCASP  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCASP_C64_rcwcomswappr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWCASP_C64_rcwcomswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWCASP_C64_rcwcomswappr
        IEM_INSTR_IMPL_A64__RCWCASP_C64_rcwcomswappr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19200800: RCWCAS  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCAS_C64_rcwcomswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWCAS_C64_rcwcomswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWCAS_C64_rcwcomswap
        IEM_INSTR_IMPL_A64__RCWCAS_C64_rcwcomswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38e09000: RCWCLRAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCLRAL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38e09000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWCLRAL_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWCLRAL_64_memop
            IEM_INSTR_IMPL_A64__RCWCLRAL_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38a09000: RCWCLRA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCLRA_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38a09000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWCLRA_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWCLRA_64_memop
            IEM_INSTR_IMPL_A64__RCWCLRA_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38609000: RCWCLRL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCLRL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38609000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWCLRL_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWCLRL_64_memop
            IEM_INSTR_IMPL_A64__RCWCLRL_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19e09000: RCWCLRPAL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCLRPAL_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19e09000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWCLRPAL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWCLRPAL_128_memop_128
            IEM_INSTR_IMPL_A64__RCWCLRPAL_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19a09000: RCWCLRPA  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCLRPA_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19a09000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWCLRPA_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWCLRPA_128_memop_128
            IEM_INSTR_IMPL_A64__RCWCLRPA_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19609000: RCWCLRPL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCLRPL_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19609000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWCLRPL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWCLRPL_128_memop_128
            IEM_INSTR_IMPL_A64__RCWCLRPL_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19209000: RCWCLRP  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCLRP_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWCLRP_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWCLRP_128_memop_128
        IEM_INSTR_IMPL_A64__RCWCLRP_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38209000: RCWCLR  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWCLR_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWCLR_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWCLR_64_memop
        IEM_INSTR_IMPL_A64__RCWCLR_64_memop(Rt, Rn, Rs, S);
#else
        RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59e00800: RCWSCASAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCASAL_C64_rcwcomswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSCASAL_C64_rcwcomswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWSCASAL_C64_rcwcomswap
        IEM_INSTR_IMPL_A64__RCWSCASAL_C64_rcwcomswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59a00800: RCWSCASA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCASA_C64_rcwcomswap, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59a00800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSCASA_C64_rcwcomswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWSCASA_C64_rcwcomswap
            IEM_INSTR_IMPL_A64__RCWSCASA_C64_rcwcomswap(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59600800: RCWSCASL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCASL_C64_rcwcomswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSCASL_C64_rcwcomswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWSCASL_C64_rcwcomswap
        IEM_INSTR_IMPL_A64__RCWSCASL_C64_rcwcomswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59e00c00: RCWSCASPAL  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCASPAL_C64_rcwcomswappr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSCASPAL_C64_rcwcomswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWSCASPAL_C64_rcwcomswappr
        IEM_INSTR_IMPL_A64__RCWSCASPAL_C64_rcwcomswappr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59a00c00: RCWSCASPA  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCASPA_C64_rcwcomswappr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSCASPA_C64_rcwcomswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWSCASPA_C64_rcwcomswappr
        IEM_INSTR_IMPL_A64__RCWSCASPA_C64_rcwcomswappr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59600c00: RCWSCASPL  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCASPL_C64_rcwcomswappr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSCASPL_C64_rcwcomswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWSCASPL_C64_rcwcomswappr
        IEM_INSTR_IMPL_A64__RCWSCASPL_C64_rcwcomswappr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59200c00: RCWSCASP  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswappr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCASP_C64_rcwcomswappr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59200c00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSCASP_C64_rcwcomswappr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWSCASP_C64_rcwcomswappr
            IEM_INSTR_IMPL_A64__RCWSCASP_C64_rcwcomswappr(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59200800: RCWSCAS  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: rcwcomswap, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCAS_C64_rcwcomswap, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSCAS_C64_rcwcomswap Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__RCWSCAS_C64_rcwcomswap
        IEM_INSTR_IMPL_A64__RCWSCAS_C64_rcwcomswap(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78e09000: RCWSCLRAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCLRAL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78e09000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSCLRAL_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSCLRAL_64_memop
            IEM_INSTR_IMPL_A64__RCWSCLRAL_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78a09000: RCWSCLRA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCLRA_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78a09000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSCLRA_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSCLRA_64_memop
            IEM_INSTR_IMPL_A64__RCWSCLRA_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78609000: RCWSCLRL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCLRL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78609000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSCLRL_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSCLRL_64_memop
            IEM_INSTR_IMPL_A64__RCWSCLRL_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59e09000: RCWSCLRPAL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCLRPAL_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSCLRPAL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSCLRPAL_128_memop_128
        IEM_INSTR_IMPL_A64__RCWSCLRPAL_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59a09000: RCWSCLRPA  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCLRPA_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSCLRPA_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSCLRPA_128_memop_128
        IEM_INSTR_IMPL_A64__RCWSCLRPA_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59609000: RCWSCLRPL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCLRPL_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59609000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSCLRPL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSCLRPL_128_memop_128
            IEM_INSTR_IMPL_A64__RCWSCLRPL_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59209000: RCWSCLRP  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCLRP_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSCLRP_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSCLRP_128_memop_128
        IEM_INSTR_IMPL_A64__RCWSCLRP_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78209000: RCWSCLR  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSCLR_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSCLR_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSCLR_64_memop
        IEM_INSTR_IMPL_A64__RCWSCLR_64_memop(Rt, Rn, Rs, S);
#else
        RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38e0b000: RCWSETAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSETAL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38e0b000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSETAL_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSETAL_64_memop
            IEM_INSTR_IMPL_A64__RCWSETAL_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38a0b000: RCWSETA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSETA_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38a0b000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSETA_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSETA_64_memop
            IEM_INSTR_IMPL_A64__RCWSETA_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3860b000: RCWSETL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSETL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3860b000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSETL_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSETL_64_memop
            IEM_INSTR_IMPL_A64__RCWSETL_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19e0b000: RCWSETPAL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSETPAL_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19e0b000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSETPAL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSETPAL_128_memop_128
            IEM_INSTR_IMPL_A64__RCWSETPAL_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19a0b000: RCWSETPA  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSETPA_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19a0b000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSETPA_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSETPA_128_memop_128
            IEM_INSTR_IMPL_A64__RCWSETPA_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1960b000: RCWSETPL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSETPL_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1960b000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSETPL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSETPL_128_memop_128
            IEM_INSTR_IMPL_A64__RCWSETPL_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1920b000: RCWSETP  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSETP_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSETP_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSETP_128_memop_128
        IEM_INSTR_IMPL_A64__RCWSETP_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3820b000: RCWSET  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSET_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3820b000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSET_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSET_64_memop
            IEM_INSTR_IMPL_A64__RCWSET_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78e0b000: RCWSSETAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSETAL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78e0b000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSSETAL_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSSETAL_64_memop
            IEM_INSTR_IMPL_A64__RCWSSETAL_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78a0b000: RCWSSETA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSETA_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78a0b000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSSETA_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSSETA_64_memop
            IEM_INSTR_IMPL_A64__RCWSSETA_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7860b000: RCWSSETL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSETL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7860b000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSSETL_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSSETL_64_memop
            IEM_INSTR_IMPL_A64__RCWSSETL_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59e0b000: RCWSSETPAL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSETPAL_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSSETPAL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSSETPAL_128_memop_128
        IEM_INSTR_IMPL_A64__RCWSSETPAL_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59a0b000: RCWSSETPA  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSETPA_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSSETPA_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSSETPA_128_memop_128
        IEM_INSTR_IMPL_A64__RCWSSETPA_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5960b000: RCWSSETPL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSETPL_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5960b000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSSETPL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSSETPL_128_memop_128
            IEM_INSTR_IMPL_A64__RCWSSETPL_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5920b000: RCWSSETP  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSETP_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSSETP_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSSETP_128_memop_128
        IEM_INSTR_IMPL_A64__RCWSSETP_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7820b000: RCWSSET  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSET_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSSET_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSSET_64_memop
        IEM_INSTR_IMPL_A64__RCWSSET_64_memop(Rt, Rn, Rs, S);
#else
        RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78e0a000: RCWSSWPAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSWPAL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSSWPAL_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSSWPAL_64_memop
        IEM_INSTR_IMPL_A64__RCWSSWPAL_64_memop(Rt, Rn, Rs, S);
#else
        RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78a0a000: RCWSSWPA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSWPA_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSSWPA_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSSWPA_64_memop
        IEM_INSTR_IMPL_A64__RCWSSWPA_64_memop(Rt, Rn, Rs, S);
#else
        RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7860a000: RCWSSWPL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSWPL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSSWPL_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSSWPL_64_memop
        IEM_INSTR_IMPL_A64__RCWSSWPL_64_memop(Rt, Rn, Rs, S);
#else
        RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59e0a000: RCWSSWPPAL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSWPPAL_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSSWPPAL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSSWPPAL_128_memop_128
        IEM_INSTR_IMPL_A64__RCWSSWPPAL_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59a0a000: RCWSSWPPA  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSWPPA_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSSWPPA_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSSWPPA_128_memop_128
        IEM_INSTR_IMPL_A64__RCWSSWPPA_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5960a000: RCWSSWPPL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSWPPL_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSSWPPL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSSWPPL_128_memop_128
        IEM_INSTR_IMPL_A64__RCWSSWPPL_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5920a000: RCWSSWPP  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSWPP_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5920a000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSSWPP_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSSWPP_128_memop_128
            IEM_INSTR_IMPL_A64__RCWSSWPP_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7820a000: RCWSSWP  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSSWP_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSSWP_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSSWP_64_memop
        IEM_INSTR_IMPL_A64__RCWSSWP_64_memop(Rt, Rn, Rs, S);
#else
        RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38e0a000: RCWSWPAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSWPAL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38e0a000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSWPAL_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSWPAL_64_memop
            IEM_INSTR_IMPL_A64__RCWSWPAL_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38a0a000: RCWSWPA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSWPA_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38a0a000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSWPA_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSWPA_64_memop
            IEM_INSTR_IMPL_A64__RCWSWPA_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3860a000: RCWSWPL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSWPL_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSWPL_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSWPL_64_memop
        IEM_INSTR_IMPL_A64__RCWSWPL_64_memop(Rt, Rn, Rs, S);
#else
        RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19e0a000: RCWSWPPAL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSWPPAL_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSWPPAL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSWPPAL_128_memop_128
        IEM_INSTR_IMPL_A64__RCWSWPPAL_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19a0a000: RCWSWPPA  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSWPPA_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19a0a000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSWPPA_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSWPPA_128_memop_128
            IEM_INSTR_IMPL_A64__RCWSWPPA_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1960a000: RCWSWPPL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSWPPL_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
    {
        LogFlow(("%018x/%010x: RCWSWPPL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSWPPL_128_memop_128
        IEM_INSTR_IMPL_A64__RCWSWPPL_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1920a000: RCWSWPP  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSWPP_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1920a000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fD128 /*FEAT_D128*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSWPP_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__RCWSWPP_128_memop_128
            IEM_INSTR_IMPL_A64__RCWSWPP_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/3820a000: RCWSWP  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RCWSWP_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3820a000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fThe /*FEAT_THE*/)
        {
            LogFlow(("%018x/%010x: RCWSWP_64_memop Rt=%#x Rn=%#x Rs=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs, S));
#ifdef IEM_INSTR_IMPL_A64__RCWSWP_64_memop
            IEM_INSTR_IMPL_A64__RCWSWP_64_memop(Rt, Rn, Rs, S);
#else
            RT_NOREF(Rt, Rn, Rs, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/d65f0be0: RETAASPPCR  <Xm>
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_RETAASPPCR_64M_branch_reg, uint32_t, uOpcode)
{
    uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const M          = (uOpcode >> 10) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: RETAASPPCR_64M_branch_reg Rm=%#x M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, M));
#ifdef IEM_INSTR_IMPL_A64__RETAASPPCR_64M_branch_reg
        IEM_INSTR_IMPL_A64__RETAASPPCR_64M_branch_reg(Rm, M);
#else
        RT_NOREF(Rm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001f/5500001f: RETAASPPC  <label>
   Instruction Set: A64  Groups: miscbranch, control */
FNIEMOP_DEF_1(iemDecodeA64_RETAASPPC_only_miscbranch, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0x5500001f))
    {
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
        {
            LogFlow(("%018x/%010x: RETAASPPC_only_miscbranch imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__RETAASPPC_only_miscbranch
            IEM_INSTR_IMPL_A64__RETAASPPC_only_miscbranch(imm16);
#else
            RT_NOREF(imm16, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d65f0bff: RETAA
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_RETAA_64E_branch_reg, uint32_t, uOpcode)
{
    uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const M          = (uOpcode >> 10) & 0x00000001;
    uint32_t const A          = (uOpcode >> 11) & 0x00000001;
    uint32_t const op         = (uOpcode >> 21) & 0x00000003;
    uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: RETAA_64E_branch_reg Rm=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__RETAA_64E_branch_reg
        IEM_INSTR_IMPL_A64__RETAA_64E_branch_reg(Rm, M, A, op, Z);
#else
        RT_NOREF(Rm, M, A, op, Z, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/d65f0fe0: RETABSPPCR  <Xm>
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_RETABSPPCR_64M_branch_reg, uint32_t, uOpcode)
{
    uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const M          = (uOpcode >> 10) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: RETABSPPCR_64M_branch_reg Rm=%#x M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, M));
#ifdef IEM_INSTR_IMPL_A64__RETABSPPCR_64M_branch_reg
        IEM_INSTR_IMPL_A64__RETABSPPCR_64M_branch_reg(Rm, M);
#else
        RT_NOREF(Rm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001f/5520001f: RETABSPPC  <label>
   Instruction Set: A64  Groups: miscbranch, control */
FNIEMOP_DEF_1(iemDecodeA64_RETABSPPC_only_miscbranch, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0x5520001f))
    {
        uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PAuth_LR*/)
        {
            LogFlow(("%018x/%010x: RETABSPPC_only_miscbranch imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__RETABSPPC_only_miscbranch
            IEM_INSTR_IMPL_A64__RETABSPPC_only_miscbranch(imm16);
#else
            RT_NOREF(imm16, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d65f0fff: RETAB
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_RETAB_64E_branch_reg, uint32_t, uOpcode)
{
    uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const M          = (uOpcode >> 10) & 0x00000001;
    uint32_t const A          = (uOpcode >> 11) & 0x00000001;
    uint32_t const op         = (uOpcode >> 21) & 0x00000003;
    uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
    {
        LogFlow(("%018x/%010x: RETAB_64E_branch_reg Rm=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__RETAB_64E_branch_reg
        IEM_INSTR_IMPL_A64__RETAB_64E_branch_reg(Rm, M, A, op, Z);
#else
        RT_NOREF(Rm, M, A, op, Z, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/d65f0000: RET{  <Xn>}
   Instruction Set: A64  Groups: branch_reg, control */
FNIEMOP_DEF_1(iemDecodeA64_RET_64R_branch_reg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0xd65f0000))
    {
        uint32_t const Rm         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const M          = (uOpcode >> 10) & 0x00000001;
        uint32_t const A          = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 21) & 0x00000003;
        uint32_t const Z          = (uOpcode >> 24) & 0x00000001;
        LogFlow(("%018x/%010x: RET_64R_branch_reg Rm=%#x Rn=%#x M=%u A=%u op=%u Z=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rm, Rn, M, A, op, Z));
#ifdef IEM_INSTR_IMPL_A64__RET_64R_branch_reg
        IEM_INSTR_IMPL_A64__RET_64R_branch_reg(Rm, Rn, M, A, op, Z);
#else
        RT_NOREF(Rm, Rn, M, A, op, Z, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ac00400: REV16  <Wd>, <Wn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_REV16_32_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ac00400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 10) & 0x00000003;
        LogFlow(("%018x/%010x: REV16_32_dp_1src Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__REV16_32_dp_1src
        IEM_INSTR_IMPL_A64__REV16_32_dp_1src(Rd, Rn, opc);
#else
        RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/dac00400: REV16  <Xd>, <Xn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_REV16_64_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac00400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const opc        = (uOpcode >> 10) & 0x00000003;
        LogFlow(("%018x/%010x: REV16_64_dp_1src Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__REV16_64_dp_1src
        IEM_INSTR_IMPL_A64__REV16_64_dp_1src(Rd, Rn, opc);
#else
        RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e201800: REV16  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_REV16_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: REV16_asimdmisc_R Rd=%#x Rn=%#x o0=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, size, Q));
#ifdef IEM_INSTR_IMPL_A64__REV16_asimdmisc_R
        IEM_INSTR_IMPL_A64__REV16_asimdmisc_R(Rd, Rn, o0, size, Q);
#else
        RT_NOREF(Rd, Rn, o0, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/dac00800: REV32  <Xd>, <Xn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_REV32_64_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const opc        = (uOpcode >> 10) & 0x00000003;
    LogFlow(("%018x/%010x: REV32_64_dp_1src Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__REV32_64_dp_1src
    IEM_INSTR_IMPL_A64__REV32_64_dp_1src(Rd, Rn, opc);
#else
    RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf3ffc00/2e200800: REV32  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_REV32_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e200800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: REV32_asimdmisc_R Rd=%#x Rn=%#x o0=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, size, Q));
#ifdef IEM_INSTR_IMPL_A64__REV32_asimdmisc_R
            IEM_INSTR_IMPL_A64__REV32_asimdmisc_R(Rd, Rn, o0, size, Q);
#else
            RT_NOREF(Rd, Rn, o0, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e200800: REV64  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_REV64_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: REV64_asimdmisc_R Rd=%#x Rn=%#x o0=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, size, Q));
#ifdef IEM_INSTR_IMPL_A64__REV64_asimdmisc_R
        IEM_INSTR_IMPL_A64__REV64_asimdmisc_R(Rd, Rn, o0, size, Q);
#else
        RT_NOREF(Rd, Rn, o0, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5ac00800: REV  <Wd>, <Wn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_REV_32_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const opc        = (uOpcode >> 10) & 0x00000003;
    LogFlow(("%018x/%010x: REV_32_dp_1src Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__REV_32_dp_1src
    IEM_INSTR_IMPL_A64__REV_32_dp_1src(Rd, Rn, opc);
#else
    RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/dac00c00: REV  <Xd>, <Xn>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_REV_64_dp_1src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const opc        = (uOpcode >> 10) & 0x00000003;
    LogFlow(("%018x/%010x: REV_64_dp_1src Rd=%#x Rn=%#x opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, opc));
#ifdef IEM_INSTR_IMPL_A64__REV_64_dp_1src
    IEM_INSTR_IMPL_A64__REV_64_dp_1src(Rd, Rn, opc);
#else
    RT_NOREF(Rd, Rn, opc, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe07c10/ba000400: RMIF  <Xn>, #<shift>, #<mask>
   Instruction Set: A64  Groups: rmif, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_RMIF_only_rmif, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe07c10)) == UINT32_C(0xba000400))
    {
        uint32_t const mask       = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm6       = (uOpcode >> 15) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFlagM /*FEAT_FlagM*/)
        {
            LogFlow(("%018x/%010x: RMIF_only_rmif mask=%#x Rn=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, mask, Rn, imm6));
#ifdef IEM_INSTR_IMPL_A64__RMIF_only_rmif
            IEM_INSTR_IMPL_A64__RMIF_only_rmif(mask, Rn, imm6);
#else
            RT_NOREF(mask, Rn, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac02c00: RORV  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_RORV_32_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op2        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: RORV_32_dp_2src Rd=%#x Rn=%#x op2=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op2, Rm));
#ifdef IEM_INSTR_IMPL_A64__RORV_32_dp_2src
    IEM_INSTR_IMPL_A64__RORV_32_dp_2src(Rd, Rn, op2, Rm);
#else
    RT_NOREF(Rd, Rn, op2, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/9ac02c00: RORV  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_RORV_64_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op2        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: RORV_64_dp_2src Rd=%#x Rn=%#x op2=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op2, Rm));
#ifdef IEM_INSTR_IMPL_A64__RORV_64_dp_2src
    IEM_INSTR_IMPL_A64__RORV_64_dp_2src(Rd, Rn, op2, Rm);
#else
    RT_NOREF(Rd, Rn, op2, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/f8a00800: RPRFM  {<rprfop> | #<imm6>}, <Xm>, [<Xn|SP>]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_RPRFM_R_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRprfm /*FEAT_RPRFM*/ && (option & 2) == 2 && (Rt & 0x18) == 0x18)
    {
        LogFlow(("%018x/%010x: RPRFM_R_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__RPRFM_R_ldst_regoff
        IEM_INSTR_IMPL_A64__RPRFM_R_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f008c00: RSHRN2  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_RSHRN_asimdshf_N, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f008c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 11) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
        {
            LogFlow(("%018x/%010x: RSHRN_asimdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__RSHRN_asimdshf_N
            IEM_INSTR_IMPL_A64__RSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q);
#else
            RT_NOREF(Rd, Rn, op, immb, immh, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e206000: RSUBHN2  <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_RSUBHN_asimddiff_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: RSUBHN_asimddiff_N Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__RSUBHN_asimddiff_N
        IEM_INSTR_IMPL_A64__RSUBHN_asimddiff_N(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e205000: SABAL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SABAL_asimddiff_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SABAL_asimddiff_L Rd=%#x Rn=%#x op=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SABAL_asimddiff_L
        IEM_INSTR_IMPL_A64__SABAL_asimddiff_L(Rd, Rn, op, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, op, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e207c00: SABA  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SABA_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SABA_asimdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SABA_asimdsame_only
        IEM_INSTR_IMPL_A64__SABA_asimdsame_only(Rd, Rn, ac, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, ac, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e207000: SABDL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SABDL_asimddiff_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SABDL_asimddiff_L Rd=%#x Rn=%#x op=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SABDL_asimddiff_L
        IEM_INSTR_IMPL_A64__SABDL_asimddiff_L(Rd, Rn, op, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, op, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e207400: SABD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SABD_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SABD_asimdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SABD_asimdsame_only
        IEM_INSTR_IMPL_A64__SABD_asimdsame_only(Rd, Rn, ac, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, ac, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e206800: SADALP  <Vd>.<Ta>, <Vn>.<Tb>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SADALP_asimdmisc_P, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e206800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 14) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SADALP_asimdmisc_P Rd=%#x Rn=%#x op=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SADALP_asimdmisc_P
            IEM_INSTR_IMPL_A64__SADALP_asimdmisc_P(Rd, Rn, op, size, Q);
#else
            RT_NOREF(Rd, Rn, op, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e202800: SADDLP  <Vd>.<Ta>, <Vn>.<Tb>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SADDLP_asimdmisc_P, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 14) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SADDLP_asimdmisc_P Rd=%#x Rn=%#x op=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SADDLP_asimdmisc_P
        IEM_INSTR_IMPL_A64__SADDLP_asimdmisc_P(Rd, Rn, op, size, Q);
#else
        RT_NOREF(Rd, Rn, op, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e303800: SADDLV  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SADDLV_asimdall_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SADDLV_asimdall_only Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SADDLV_asimdall_only
        IEM_INSTR_IMPL_A64__SADDLV_asimdall_only(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e200000: SADDL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SADDL_asimddiff_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SADDL_asimddiff_L Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SADDL_asimddiff_L
        IEM_INSTR_IMPL_A64__SADDL_asimddiff_L(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e201000: SADDW2  <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SADDW_asimddiff_W, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SADDW_asimddiff_W Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SADDW_asimddiff_W
        IEM_INSTR_IMPL_A64__SADDW_asimddiff_W(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7a000000: SBCS  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: addsub_carry, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SBCS_32_addsub_carry, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: SBCS_32_addsub_carry Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SBCS_32_addsub_carry
    IEM_INSTR_IMPL_A64__SBCS_32_addsub_carry(Rd, Rn, Rm);
#else
    RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/fa000000: SBCS  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: addsub_carry, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SBCS_64_addsub_carry, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: SBCS_64_addsub_carry Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SBCS_64_addsub_carry
    IEM_INSTR_IMPL_A64__SBCS_64_addsub_carry(Rd, Rn, Rm);
#else
    RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/5a000000: SBC  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: addsub_carry, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SBC_32_addsub_carry, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: SBC_32_addsub_carry Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SBC_32_addsub_carry
    IEM_INSTR_IMPL_A64__SBC_32_addsub_carry(Rd, Rn, Rm);
#else
    RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/da000000: SBC  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: addsub_carry, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SBC_64_addsub_carry, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: SBC_64_addsub_carry Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SBC_64_addsub_carry
    IEM_INSTR_IMPL_A64__SBC_64_addsub_carry(Rd, Rn, Rm);
#else
    RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/13000000: SBFM  <Wd>, <Wn>, #<immr>, #<imms>
   Instruction Set: A64  Groups: bitfield, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_SBFM_32M_bitfield, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
    LogFlow(("%018x/%010x: SBFM_32M_bitfield Rd=%#x Rn=%#x imms=%#x immr=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr));
#ifdef IEM_INSTR_IMPL_A64__SBFM_32M_bitfield
    IEM_INSTR_IMPL_A64__SBFM_32M_bitfield(Rd, Rn, imms, immr);
#else
    RT_NOREF(Rd, Rn, imms, immr, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/93400000: SBFM  <Xd>, <Xn>, #<immr>, #<imms>
   Instruction Set: A64  Groups: bitfield, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_SBFM_64M_bitfield, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x93400000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
        uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
        LogFlow(("%018x/%010x: SBFM_64M_bitfield Rd=%#x Rn=%#x imms=%#x immr=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr));
#ifdef IEM_INSTR_IMPL_A64__SBFM_64M_bitfield
        IEM_INSTR_IMPL_A64__SBFM_64M_bitfield(Rd, Rn, imms, immr);
#else
        RT_NOREF(Rd, Rn, imms, immr, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d50330ff: SB
   Instruction Set: A64  Groups: barriers, control */
FNIEMOP_DEF_1(iemDecodeA64_SB_only_barriers, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd50330ff))
    {
        uint32_t const opc        = (uOpcode >>  5) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSb /*FEAT_SB*/)
        {
            LogFlow(("%018x/%010x: SB_only_barriers opc=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, opc));
#ifdef IEM_INSTR_IMPL_A64__SB_only_barriers
            IEM_INSTR_IMPL_A64__SB_only_barriers(opc);
#else
            RT_NOREF(opc, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/1e420000: SCVTF  <Dd>, <Wn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_D32_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x1e420000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: SCVTF_D32_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_D32_float2fix
            IEM_INSTR_IMPL_A64__SCVTF_D32_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e620000: SCVTF  <Dd>, <Wn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_D32_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e620000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: SCVTF_D32_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_D32_float2int
            IEM_INSTR_IMPL_A64__SCVTF_D32_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/9e420000: SCVTF  <Dd>, <Xn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_D64_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x9e420000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: SCVTF_D64_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_D64_float2fix
            IEM_INSTR_IMPL_A64__SCVTF_D64_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e620000: SCVTF  <Dd>, <Xn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_D64_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e620000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: SCVTF_D64_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_D64_float2int
            IEM_INSTR_IMPL_A64__SCVTF_D64_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/1ec20000: SCVTF  <Hd>, <Wn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_H32_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x1ec20000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: SCVTF_H32_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_H32_float2fix
            IEM_INSTR_IMPL_A64__SCVTF_H32_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee20000: SCVTF  <Hd>, <Wn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_H32_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee20000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: SCVTF_H32_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_H32_float2int
            IEM_INSTR_IMPL_A64__SCVTF_H32_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/9ec20000: SCVTF  <Hd>, <Xn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_H64_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x9ec20000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: SCVTF_H64_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_H64_float2fix
            IEM_INSTR_IMPL_A64__SCVTF_H64_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ee20000: SCVTF  <Hd>, <Xn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_H64_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ee20000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: SCVTF_H64_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_H64_float2int
            IEM_INSTR_IMPL_A64__SCVTF_H64_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/1e020000: SCVTF  <Sd>, <Wn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_S32_float2fix, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: SCVTF_S32_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_S32_float2fix
        IEM_INSTR_IMPL_A64__SCVTF_S32_float2fix(Rd, Rn, scale);
#else
        RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e220000: SCVTF  <Sd>, <Wn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_S32_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e220000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: SCVTF_S32_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_S32_float2int
            IEM_INSTR_IMPL_A64__SCVTF_S32_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/9e020000: SCVTF  <Sd>, <Xn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_S64_float2fix, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: SCVTF_S64_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_S64_float2fix
        IEM_INSTR_IMPL_A64__SCVTF_S64_float2fix(Rd, Rn, scale);
#else
        RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e220000: SCVTF  <Sd>, <Xn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_S64_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e220000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: SCVTF_S64_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_S64_float2int
            IEM_INSTR_IMPL_A64__SCVTF_S64_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0e21d800: SCVTF  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0e21d800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SCVTF_asimdmisc_R Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_asimdmisc_R
            IEM_INSTR_IMPL_A64__SCVTF_asimdmisc_R(Rd, Rn, sz, Q);
#else
            RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0e79d800: SCVTF  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0e79d800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: SCVTF_asimdmiscfp16_R Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__SCVTF_asimdmiscfp16_R(Rd, Rn, Q);
#else
            RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f00e400: SCVTF  <Vd>.<T>, <Vn>.<T>, #<fbits>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_asimdshf_C, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: SCVTF_asimdshf_C Rd=%#x Rn=%#x immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_asimdshf_C
        IEM_INSTR_IMPL_A64__SCVTF_asimdshf_C(Rd, Rn, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/5e21d800: SCVTF  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SCVTF_asisdmisc_R Rd=%#x Rn=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_asisdmisc_R
        IEM_INSTR_IMPL_A64__SCVTF_asisdmisc_R(Rd, Rn, sz);
#else
        RT_NOREF(Rd, Rn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5e79d800: SCVTF  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_asisdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5e79d800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: SCVTF_asisdmiscfp16_R Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_asisdmiscfp16_R
            IEM_INSTR_IMPL_A64__SCVTF_asisdmiscfp16_R(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/5f00e400: SCVTF  <V><d>, <V><n>, #<fbits>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_asisdshf_C, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
    {
        LogFlow(("%018x/%010x: SCVTF_asisdshf_C Rd=%#x Rn=%#x immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_asisdshf_C
        IEM_INSTR_IMPL_A64__SCVTF_asisdshf_C(Rd, Rn, immb, immh);
#else
        RT_NOREF(Rd, Rn, immb, immh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e7c0000: SCVTF  <Dd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_sisd_32D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e7c0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: SCVTF_sisd_32D Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_sisd_32D
            IEM_INSTR_IMPL_A64__SCVTF_sisd_32D(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1efc0000: SCVTF  <Hd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_sisd_32H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1efc0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: SCVTF_sisd_32H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_sisd_32H
            IEM_INSTR_IMPL_A64__SCVTF_sisd_32H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9efc0000: SCVTF  <Hd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_sisd_64H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9efc0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: SCVTF_sisd_64H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_sisd_64H
            IEM_INSTR_IMPL_A64__SCVTF_sisd_64H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e3c0000: SCVTF  <Sd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SCVTF_sisd_64S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e3c0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: SCVTF_sisd_64S Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SCVTF_sisd_64S
            IEM_INSTR_IMPL_A64__SCVTF_sisd_64S(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac00c00: SDIV  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SDIV_32_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: SDIV_32_dp_2src Rd=%#x Rn=%#x o1=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm));
#ifdef IEM_INSTR_IMPL_A64__SDIV_32_dp_2src
    IEM_INSTR_IMPL_A64__SDIV_32_dp_2src(Rd, Rn, o1, Rm);
#else
    RT_NOREF(Rd, Rn, o1, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/9ac00c00: SDIV  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SDIV_64_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: SDIV_64_dp_2src Rd=%#x Rn=%#x o1=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm));
#ifdef IEM_INSTR_IMPL_A64__SDIV_64_dp_2src
    IEM_INSTR_IMPL_A64__SDIV_64_dp_2src(Rd, Rn, o1, Rm);
#else
    RT_NOREF(Rd, Rn, o1, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf00f400/0f00e000: SDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SDOT_asimdelem_D, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fDotProd /*FEAT_DotProd*/)
    {
        LogFlow(("%018x/%010x: SDOT_asimdelem_D Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SDOT_asimdelem_D
        IEM_INSTR_IMPL_A64__SDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, size, Q);
#else
        RT_NOREF(Rd, Rn, H, Rm, M, L, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e009400: SDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SDOT_asimdsame2_D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e009400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fDotProd /*FEAT_DotProd*/)
        {
            LogFlow(("%018x/%010x: SDOT_asimdsame2_D Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SDOT_asimdsame2_D
            IEM_INSTR_IMPL_A64__SDOT_asimdsame2_D(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19c0a400: SETEN  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETEN_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: SETEN_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETEN_SET_memcms
        IEM_INSTR_IMPL_A64__SETEN_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19c0b400: SETETN  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETETN_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: SETETN_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETETN_SET_memcms
        IEM_INSTR_IMPL_A64__SETETN_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19c09400: SETET  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETET_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: SETET_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETET_SET_memcms
        IEM_INSTR_IMPL_A64__SETET_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19c08400: SETE  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETE_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: SETE_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETE_SET_memcms
        IEM_INSTR_IMPL_A64__SETE_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/3a00480d: SETF16  <Wn>
   Instruction Set: A64  Groups: setf, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SETF16_only_setf, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0x3a00480d))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFlagM /*FEAT_FlagM*/)
        {
            LogFlow(("%018x/%010x: SETF16_only_setf Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn));
#ifdef IEM_INSTR_IMPL_A64__SETF16_only_setf
            IEM_INSTR_IMPL_A64__SETF16_only_setf(Rn);
#else
            RT_NOREF(Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/3a00080d: SETF8  <Wn>
   Instruction Set: A64  Groups: setf, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SETF8_only_setf, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFlagM /*FEAT_FlagM*/)
    {
        LogFlow(("%018x/%010x: SETF8_only_setf Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn));
#ifdef IEM_INSTR_IMPL_A64__SETF8_only_setf
        IEM_INSTR_IMPL_A64__SETF8_only_setf(Rn);
#else
        RT_NOREF(Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1dc0a400: SETGEN  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETGEN_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SETGEN_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETGEN_SET_memcms
        IEM_INSTR_IMPL_A64__SETGEN_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1dc0b400: SETGETN  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETGETN_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SETGETN_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETGETN_SET_memcms
        IEM_INSTR_IMPL_A64__SETGETN_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1dc09400: SETGET  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETGET_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SETGET_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETGET_SET_memcms
        IEM_INSTR_IMPL_A64__SETGET_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1dc08400: SETGE  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETGE_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SETGE_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETGE_SET_memcms
        IEM_INSTR_IMPL_A64__SETGE_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1dc06400: SETGMN  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETGMN_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SETGMN_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETGMN_SET_memcms
        IEM_INSTR_IMPL_A64__SETGMN_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1dc07400: SETGMTN  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETGMTN_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SETGMTN_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETGMTN_SET_memcms
        IEM_INSTR_IMPL_A64__SETGMTN_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1dc05400: SETGMT  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETGMT_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SETGMT_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETGMT_SET_memcms
        IEM_INSTR_IMPL_A64__SETGMT_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1dc04400: SETGM  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETGM_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SETGM_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETGM_SET_memcms
        IEM_INSTR_IMPL_A64__SETGM_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1dc02400: SETGPN  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETGPN_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SETGPN_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETGPN_SET_memcms
        IEM_INSTR_IMPL_A64__SETGPN_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1dc03400: SETGPTN  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETGPTN_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SETGPTN_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETGPTN_SET_memcms
        IEM_INSTR_IMPL_A64__SETGPTN_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1dc01400: SETGPT  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETGPT_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SETGPT_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETGPT_SET_memcms
        IEM_INSTR_IMPL_A64__SETGPT_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/1dc00400: SETGP  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETGP_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SETGP_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETGP_SET_memcms
        IEM_INSTR_IMPL_A64__SETGP_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19c06400: SETMN  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETMN_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: SETMN_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETMN_SET_memcms
        IEM_INSTR_IMPL_A64__SETMN_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19c07400: SETMTN  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETMTN_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: SETMTN_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETMTN_SET_memcms
        IEM_INSTR_IMPL_A64__SETMTN_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19c05400: SETMT  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETMT_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: SETMT_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETMT_SET_memcms
        IEM_INSTR_IMPL_A64__SETMT_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19c04400: SETM  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETM_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: SETM_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETM_SET_memcms
        IEM_INSTR_IMPL_A64__SETM_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19c02400: SETPN  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETPN_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: SETPN_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETPN_SET_memcms
        IEM_INSTR_IMPL_A64__SETPN_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19c03400: SETPTN  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETPTN_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: SETPTN_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETPTN_SET_memcms
        IEM_INSTR_IMPL_A64__SETPTN_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19c01400: SETPT  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETPT_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: SETPT_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETPT_SET_memcms
        IEM_INSTR_IMPL_A64__SETPT_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 3fe0fc00/19c00400: SETP  [<Xd>]!, <Xn>!, <Xs>
   Instruction Set: A64  Groups: memcms, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SETP_SET_memcms, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 30) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMops /*FEAT_MOPS*/)
    {
        LogFlow(("%018x/%010x: SETP_SET_memcms Rd=%#x Rn=%#x Rs=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rs, sz));
#ifdef IEM_INSTR_IMPL_A64__SETP_SET_memcms
        IEM_INSTR_IMPL_A64__SETP_SET_memcms(Rd, Rn, Rs, sz);
#else
        RT_NOREF(Rd, Rn, Rs, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d50320bf: SEVL
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_SEVL_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd50320bf))
    {
        LogFlow(("%018x/%010x: SEVL_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__SEVL_HI_hints
        IEM_INSTR_IMPL_A64__SEVL_HI_hints();
#else
        RT_NOREF(pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503209f: SEV
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_SEV_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503209f))
    {
        LogFlow(("%018x/%010x: SEV_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__SEV_HI_hints
        IEM_INSTR_IMPL_A64__SEV_HI_hints();
#else
        RT_NOREF(pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5e000000: SHA1C  <Qd>, <Sn>, <Vm>.4S
   Instruction Set: A64  Groups: cryptosha3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA1C_QSV_cryptosha3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5e000000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha1 /*FEAT_SHA1*/)
        {
            LogFlow(("%018x/%010x: SHA1C_QSV_cryptosha3 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SHA1C_QSV_cryptosha3
            IEM_INSTR_IMPL_A64__SHA1C_QSV_cryptosha3(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5e280800: SHA1H  <Sd>, <Sn>
   Instruction Set: A64  Groups: cryptosha2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA1H_SS_cryptosha2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5e280800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha1 /*FEAT_SHA1*/)
        {
            LogFlow(("%018x/%010x: SHA1H_SS_cryptosha2 Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SHA1H_SS_cryptosha2
            IEM_INSTR_IMPL_A64__SHA1H_SS_cryptosha2(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5e002000: SHA1M  <Qd>, <Sn>, <Vm>.4S
   Instruction Set: A64  Groups: cryptosha3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA1M_QSV_cryptosha3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5e002000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha1 /*FEAT_SHA1*/)
        {
            LogFlow(("%018x/%010x: SHA1M_QSV_cryptosha3 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SHA1M_QSV_cryptosha3
            IEM_INSTR_IMPL_A64__SHA1M_QSV_cryptosha3(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5e001000: SHA1P  <Qd>, <Sn>, <Vm>.4S
   Instruction Set: A64  Groups: cryptosha3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA1P_QSV_cryptosha3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5e001000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha1 /*FEAT_SHA1*/)
        {
            LogFlow(("%018x/%010x: SHA1P_QSV_cryptosha3 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SHA1P_QSV_cryptosha3
            IEM_INSTR_IMPL_A64__SHA1P_QSV_cryptosha3(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5e003000: SHA1SU0  <Vd>.4S, <Vn>.4S, <Vm>.4S
   Instruction Set: A64  Groups: cryptosha3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA1SU0_VVV_cryptosha3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5e003000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha1 /*FEAT_SHA1*/)
        {
            LogFlow(("%018x/%010x: SHA1SU0_VVV_cryptosha3 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SHA1SU0_VVV_cryptosha3
            IEM_INSTR_IMPL_A64__SHA1SU0_VVV_cryptosha3(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5e281800: SHA1SU1  <Vd>.4S, <Vn>.4S
   Instruction Set: A64  Groups: cryptosha2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA1SU1_VV_cryptosha2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5e281800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha1 /*FEAT_SHA1*/)
        {
            LogFlow(("%018x/%010x: SHA1SU1_VV_cryptosha2 Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SHA1SU1_VV_cryptosha2
            IEM_INSTR_IMPL_A64__SHA1SU1_VV_cryptosha2(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5e005000: SHA256H2  <Qd>, <Qn>, <Vm>.4S
   Instruction Set: A64  Groups: cryptosha3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA256H2_QQV_cryptosha3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const P          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha256 /*FEAT_SHA256*/)
    {
        LogFlow(("%018x/%010x: SHA256H2_QQV_cryptosha3 Rd=%#x Rn=%#x P=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, P, Rm));
#ifdef IEM_INSTR_IMPL_A64__SHA256H2_QQV_cryptosha3
        IEM_INSTR_IMPL_A64__SHA256H2_QQV_cryptosha3(Rd, Rn, P, Rm);
#else
        RT_NOREF(Rd, Rn, P, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5e004000: SHA256H  <Qd>, <Qn>, <Vm>.4S
   Instruction Set: A64  Groups: cryptosha3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA256H_QQV_cryptosha3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5e004000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const P          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha256 /*FEAT_SHA256*/)
        {
            LogFlow(("%018x/%010x: SHA256H_QQV_cryptosha3 Rd=%#x Rn=%#x P=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, P, Rm));
#ifdef IEM_INSTR_IMPL_A64__SHA256H_QQV_cryptosha3
            IEM_INSTR_IMPL_A64__SHA256H_QQV_cryptosha3(Rd, Rn, P, Rm);
#else
            RT_NOREF(Rd, Rn, P, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/5e282800: SHA256SU0  <Vd>.4S, <Vn>.4S
   Instruction Set: A64  Groups: cryptosha2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA256SU0_VV_cryptosha2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha256 /*FEAT_SHA256*/)
    {
        LogFlow(("%018x/%010x: SHA256SU0_VV_cryptosha2 Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SHA256SU0_VV_cryptosha2
        IEM_INSTR_IMPL_A64__SHA256SU0_VV_cryptosha2(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5e006000: SHA256SU1  <Vd>.4S, <Vn>.4S, <Vm>.4S
   Instruction Set: A64  Groups: cryptosha3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA256SU1_VVV_cryptosha3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5e006000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha256 /*FEAT_SHA256*/)
        {
            LogFlow(("%018x/%010x: SHA256SU1_VVV_cryptosha3 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SHA256SU1_VVV_cryptosha3
            IEM_INSTR_IMPL_A64__SHA256SU1_VVV_cryptosha3(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/ce608400: SHA512H2  <Qd>, <Qn>, <Vm>.2D
   Instruction Set: A64  Groups: cryptosha512_3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA512H2_QQV_cryptosha512_3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha512 /*FEAT_SHA512*/)
    {
        LogFlow(("%018x/%010x: SHA512H2_QQV_cryptosha512_3 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SHA512H2_QQV_cryptosha512_3
        IEM_INSTR_IMPL_A64__SHA512H2_QQV_cryptosha512_3(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/ce608000: SHA512H  <Qd>, <Qn>, <Vm>.2D
   Instruction Set: A64  Groups: cryptosha512_3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA512H_QQV_cryptosha512_3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha512 /*FEAT_SHA512*/)
    {
        LogFlow(("%018x/%010x: SHA512H_QQV_cryptosha512_3 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SHA512H_QQV_cryptosha512_3
        IEM_INSTR_IMPL_A64__SHA512H_QQV_cryptosha512_3(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/cec08000: SHA512SU0  <Vd>.2D, <Vn>.2D
   Instruction Set: A64  Groups: cryptosha512_2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA512SU0_VV2_cryptosha512_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xcec08000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha512 /*FEAT_SHA512*/)
        {
            LogFlow(("%018x/%010x: SHA512SU0_VV2_cryptosha512_2 Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SHA512SU0_VV2_cryptosha512_2
            IEM_INSTR_IMPL_A64__SHA512SU0_VV2_cryptosha512_2(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/ce608800: SHA512SU1  <Vd>.2D, <Vn>.2D, <Vm>.2D
   Instruction Set: A64  Groups: cryptosha512_3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHA512SU1_VVV2_cryptosha512_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xce608800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha512 /*FEAT_SHA512*/)
        {
            LogFlow(("%018x/%010x: SHA512SU1_VVV2_cryptosha512_3 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SHA512SU1_VVV2_cryptosha512_3
            IEM_INSTR_IMPL_A64__SHA512SU1_VVV2_cryptosha512_3(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e200400: SHADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHADD_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e200400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SHADD_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SHADD_asimdsame_only
            IEM_INSTR_IMPL_A64__SHADD_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e213800: SHLL2  <Vd>.<Ta>, <Vn>.<Tb>, #<shift>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHLL_asimdmisc_S, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SHLL_asimdmisc_S Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SHLL_asimdmisc_S
        IEM_INSTR_IMPL_A64__SHLL_asimdmisc_S(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f005400: SHL  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHL_asimdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: SHL_asimdshf_R Rd=%#x Rn=%#x immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SHL_asimdshf_R
        IEM_INSTR_IMPL_A64__SHL_asimdshf_R(Rd, Rn, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/5f005400: SHL  D<d>, D<n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHL_asisdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && (immh & 8) == 8)
    {
        LogFlow(("%018x/%010x: SHL_asisdshf_R Rd=%#x Rn=%#x immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SHL_asisdshf_R
        IEM_INSTR_IMPL_A64__SHL_asisdshf_R(Rd, Rn, immb, immh);
#else
        RT_NOREF(Rd, Rn, immb, immh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f008400: SHRN2  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHRN_asimdshf_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 11) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: SHRN_asimdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SHRN_asimdshf_N
        IEM_INSTR_IMPL_A64__SHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, op, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e202400: SHSUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SHSUB_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SHSUB_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SHSUB_asimdsame_only
        IEM_INSTR_IMPL_A64__SHSUB_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f005400: SLI  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SLI_asimdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f005400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
        {
            LogFlow(("%018x/%010x: SLI_asimdshf_R Rd=%#x Rn=%#x immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SLI_asimdshf_R
            IEM_INSTR_IMPL_A64__SLI_asimdshf_R(Rd, Rn, immb, immh, Q);
#else
            RT_NOREF(Rd, Rn, immb, immh, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f005400: SLI  D<d>, D<n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SLI_asisdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f005400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && (immh & 8) == 8)
        {
            LogFlow(("%018x/%010x: SLI_asisdshf_R Rd=%#x Rn=%#x immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SLI_asisdshf_R
            IEM_INSTR_IMPL_A64__SLI_asisdshf_R(Rd, Rn, immb, immh);
#else
            RT_NOREF(Rd, Rn, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/ce60c000: SM3PARTW1  <Vd>.4S, <Vn>.4S, <Vm>.4S
   Instruction Set: A64  Groups: cryptosha512_3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SM3PARTW1_VVV4_cryptosha512_3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSm3 /*FEAT_SM3*/)
    {
        LogFlow(("%018x/%010x: SM3PARTW1_VVV4_cryptosha512_3 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SM3PARTW1_VVV4_cryptosha512_3
        IEM_INSTR_IMPL_A64__SM3PARTW1_VVV4_cryptosha512_3(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/ce60c400: SM3PARTW2  <Vd>.4S, <Vn>.4S, <Vm>.4S
   Instruction Set: A64  Groups: cryptosha512_3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SM3PARTW2_VVV4_cryptosha512_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xce60c400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSm3 /*FEAT_SM3*/)
        {
            LogFlow(("%018x/%010x: SM3PARTW2_VVV4_cryptosha512_3 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SM3PARTW2_VVV4_cryptosha512_3
            IEM_INSTR_IMPL_A64__SM3PARTW2_VVV4_cryptosha512_3(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/ce400000: SM3SS1  <Vd>.4S, <Vn>.4S, <Vm>.4S, <Va>.4S
   Instruction Set: A64  Groups: crypto4, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SM3SS1_VVV4_crypto4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0xce400000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSm3 /*FEAT_SM3*/)
        {
            LogFlow(("%018x/%010x: SM3SS1_VVV4_crypto4 Rd=%#x Rn=%#x Ra=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm));
#ifdef IEM_INSTR_IMPL_A64__SM3SS1_VVV4_crypto4
            IEM_INSTR_IMPL_A64__SM3SS1_VVV4_crypto4(Rd, Rn, Ra, Rm);
#else
            RT_NOREF(Rd, Rn, Ra, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0cc00/ce408000: SM3TT1A  <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]
   Instruction Set: A64  Groups: crypto3_imm2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SM3TT1A_VVV4_crypto3_imm2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm2       = (uOpcode >> 12) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSm3 /*FEAT_SM3*/)
    {
        LogFlow(("%018x/%010x: SM3TT1A_VVV4_crypto3_imm2 Rd=%#x Rn=%#x imm2=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm2, Rm));
#ifdef IEM_INSTR_IMPL_A64__SM3TT1A_VVV4_crypto3_imm2
        IEM_INSTR_IMPL_A64__SM3TT1A_VVV4_crypto3_imm2(Rd, Rn, imm2, Rm);
#else
        RT_NOREF(Rd, Rn, imm2, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0cc00/ce408400: SM3TT1B  <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]
   Instruction Set: A64  Groups: crypto3_imm2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SM3TT1B_VVV4_crypto3_imm2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0cc00)) == UINT32_C(0xce408400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm2       = (uOpcode >> 12) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSm3 /*FEAT_SM3*/)
        {
            LogFlow(("%018x/%010x: SM3TT1B_VVV4_crypto3_imm2 Rd=%#x Rn=%#x imm2=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm2, Rm));
#ifdef IEM_INSTR_IMPL_A64__SM3TT1B_VVV4_crypto3_imm2
            IEM_INSTR_IMPL_A64__SM3TT1B_VVV4_crypto3_imm2(Rd, Rn, imm2, Rm);
#else
            RT_NOREF(Rd, Rn, imm2, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0cc00/ce408800: SM3TT2A  <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]
   Instruction Set: A64  Groups: crypto3_imm2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SM3TT2A_VVV4_crypto3_imm2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0cc00)) == UINT32_C(0xce408800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm2       = (uOpcode >> 12) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSm3 /*FEAT_SM3*/)
        {
            LogFlow(("%018x/%010x: SM3TT2A_VVV4_crypto3_imm2 Rd=%#x Rn=%#x imm2=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm2, Rm));
#ifdef IEM_INSTR_IMPL_A64__SM3TT2A_VVV4_crypto3_imm2
            IEM_INSTR_IMPL_A64__SM3TT2A_VVV4_crypto3_imm2(Rd, Rn, imm2, Rm);
#else
            RT_NOREF(Rd, Rn, imm2, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0cc00/ce408c00: SM3TT2B  <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]
   Instruction Set: A64  Groups: crypto3_imm2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SM3TT2B_VVV_crypto3_imm2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0cc00)) == UINT32_C(0xce408c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm2       = (uOpcode >> 12) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSm3 /*FEAT_SM3*/)
        {
            LogFlow(("%018x/%010x: SM3TT2B_VVV_crypto3_imm2 Rd=%#x Rn=%#x imm2=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm2, Rm));
#ifdef IEM_INSTR_IMPL_A64__SM3TT2B_VVV_crypto3_imm2
            IEM_INSTR_IMPL_A64__SM3TT2B_VVV_crypto3_imm2(Rd, Rn, imm2, Rm);
#else
            RT_NOREF(Rd, Rn, imm2, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/ce60c800: SM4EKEY  <Vd>.4S, <Vn>.4S, <Vm>.4S
   Instruction Set: A64  Groups: cryptosha512_3, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SM4EKEY_VVV4_cryptosha512_3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSm4 /*FEAT_SM4*/)
    {
        LogFlow(("%018x/%010x: SM4EKEY_VVV4_cryptosha512_3 Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SM4EKEY_VVV4_cryptosha512_3
        IEM_INSTR_IMPL_A64__SM4EKEY_VVV4_cryptosha512_3(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/cec08400: SM4E  <Vd>.4S, <Vn>.4S
   Instruction Set: A64  Groups: cryptosha512_2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SM4E_VV4_cryptosha512_2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSm4 /*FEAT_SM4*/)
    {
        LogFlow(("%018x/%010x: SM4E_VV4_cryptosha512_2 Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__SM4E_VV4_cryptosha512_2
        IEM_INSTR_IMPL_A64__SM4E_VV4_cryptosha512_2(Rd, Rn);
#else
        RT_NOREF(Rd, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/9b200000: SMADDL  <Xd>, <Wn>, <Wm>, <Xa>
   Instruction Set: A64  Groups: dp_3src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SMADDL_64WA_dp_3src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 23) & 0x00000001;
    LogFlow(("%018x/%010x: SMADDL_64WA_dp_3src Rd=%#x Rn=%#x Ra=%#x Rm=%#x U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm, U));
#ifdef IEM_INSTR_IMPL_A64__SMADDL_64WA_dp_3src
    IEM_INSTR_IMPL_A64__SMADDL_64WA_dp_3src(Rd, Rn, Ra, Rm, U);
#else
    RT_NOREF(Rd, Rn, Ra, Rm, U, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf20fc00/0e20a400: SMAXP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMAXP_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SMAXP_asimdsame_only Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SMAXP_asimdsame_only
        IEM_INSTR_IMPL_A64__SMAXP_asimdsame_only(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e30a800: SMAXV  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMAXV_asimdall_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SMAXV_asimdall_only Rd=%#x Rn=%#x op=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SMAXV_asimdall_only
        IEM_INSTR_IMPL_A64__SMAXV_asimdall_only(Rd, Rn, op, size, Q);
#else
        RT_NOREF(Rd, Rn, op, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac06000: SMAX  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SMAX_32_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac06000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
        {
            LogFlow(("%018x/%010x: SMAX_32_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SMAX_32_dp_2src
            IEM_INSTR_IMPL_A64__SMAX_32_dp_2src(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0000/11c00000: SMAX  <Wd>, <Wn>, #<simm>
   Instruction Set: A64  Groups: minmax_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_SMAX_32_minmax_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm8       = (uOpcode >> 10) & 0x000000ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: SMAX_32_minmax_imm Rd=%#x Rn=%#x imm8=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm8));
#ifdef IEM_INSTR_IMPL_A64__SMAX_32_minmax_imm
        IEM_INSTR_IMPL_A64__SMAX_32_minmax_imm(Rd, Rn, imm8);
#else
        RT_NOREF(Rd, Rn, imm8, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9ac06000: SMAX  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SMAX_64_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac06000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
        {
            LogFlow(("%018x/%010x: SMAX_64_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SMAX_64_dp_2src
            IEM_INSTR_IMPL_A64__SMAX_64_dp_2src(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0000/91c00000: SMAX  <Xd>, <Xn>, #<simm>
   Instruction Set: A64  Groups: minmax_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_SMAX_64_minmax_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm8       = (uOpcode >> 10) & 0x000000ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: SMAX_64_minmax_imm Rd=%#x Rn=%#x imm8=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm8));
#ifdef IEM_INSTR_IMPL_A64__SMAX_64_minmax_imm
        IEM_INSTR_IMPL_A64__SMAX_64_minmax_imm(Rd, Rn, imm8);
#else
        RT_NOREF(Rd, Rn, imm8, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e206400: SMAX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMAX_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SMAX_asimdsame_only Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SMAX_asimdsame_only
        IEM_INSTR_IMPL_A64__SMAX_asimdsame_only(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001f/d4000003: SMC  #<imm>
   Instruction Set: A64  Groups: exception, control */
FNIEMOP_DEF_1(iemDecodeA64_SMC_EX_exception, uint32_t, uOpcode)
{
    uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
    LogFlow(("%018x/%010x: SMC_EX_exception imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__SMC_EX_exception
    IEM_INSTR_IMPL_A64__SMC_EX_exception(imm16);
#else
    RT_NOREF(imm16, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf20fc00/0e20ac00: SMINP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMINP_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e20ac00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SMINP_asimdsame_only Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SMINP_asimdsame_only
            IEM_INSTR_IMPL_A64__SMINP_asimdsame_only(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e31a800: SMINV  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMINV_asimdall_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SMINV_asimdall_only Rd=%#x Rn=%#x op=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SMINV_asimdall_only
        IEM_INSTR_IMPL_A64__SMINV_asimdall_only(Rd, Rn, op, size, Q);
#else
        RT_NOREF(Rd, Rn, op, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac06800: SMIN  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SMIN_32_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: SMIN_32_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SMIN_32_dp_2src
        IEM_INSTR_IMPL_A64__SMIN_32_dp_2src(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0000/11c80000: SMIN  <Wd>, <Wn>, #<simm>
   Instruction Set: A64  Groups: minmax_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_SMIN_32_minmax_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm8       = (uOpcode >> 10) & 0x000000ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: SMIN_32_minmax_imm Rd=%#x Rn=%#x imm8=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm8));
#ifdef IEM_INSTR_IMPL_A64__SMIN_32_minmax_imm
        IEM_INSTR_IMPL_A64__SMIN_32_minmax_imm(Rd, Rn, imm8);
#else
        RT_NOREF(Rd, Rn, imm8, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9ac06800: SMIN  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SMIN_64_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: SMIN_64_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SMIN_64_dp_2src
        IEM_INSTR_IMPL_A64__SMIN_64_dp_2src(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0000/91c80000: SMIN  <Xd>, <Xn>, #<simm>
   Instruction Set: A64  Groups: minmax_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_SMIN_64_minmax_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm8       = (uOpcode >> 10) & 0x000000ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: SMIN_64_minmax_imm Rd=%#x Rn=%#x imm8=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm8));
#ifdef IEM_INSTR_IMPL_A64__SMIN_64_minmax_imm
        IEM_INSTR_IMPL_A64__SMIN_64_minmax_imm(Rd, Rn, imm8);
#else
        RT_NOREF(Rd, Rn, imm8, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e206c00: SMIN  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMIN_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SMIN_asimdsame_only Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SMIN_asimdsame_only
        IEM_INSTR_IMPL_A64__SMIN_asimdsame_only(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e208000: SMLAL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMLAL_asimddiff_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e208000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SMLAL_asimddiff_L Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SMLAL_asimddiff_L
            IEM_INSTR_IMPL_A64__SMLAL_asimddiff_L(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/0f002000: SMLAL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMLAL_asimdelem_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x0f002000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SMLAL_asimdelem_L Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SMLAL_asimdelem_L
            IEM_INSTR_IMPL_A64__SMLAL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q);
#else
            RT_NOREF(Rd, Rn, H, o2, Rm, M, L, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e20a000: SMLSL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMLSL_asimddiff_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e20a000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SMLSL_asimddiff_L Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SMLSL_asimddiff_L
            IEM_INSTR_IMPL_A64__SMLSL_asimddiff_L(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/0f006000: SMLSL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMLSL_asimdelem_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x0f006000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SMLSL_asimdelem_L Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SMLSL_asimdelem_L
            IEM_INSTR_IMPL_A64__SMLSL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q);
#else
            RT_NOREF(Rd, Rn, H, o2, Rm, M, L, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4e80a400: SMMLA  <Vd>.4S, <Vn>.16B, <Vm>.16B
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMMLA_asimdsame2_G, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4e80a400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const B          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fI8mm /*FEAT_I8MM*/)
        {
            LogFlow(("%018x/%010x: SMMLA_asimdsame2_G Rd=%#x Rn=%#x B=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, B, Rm));
#ifdef IEM_INSTR_IMPL_A64__SMMLA_asimdsame2_G
            IEM_INSTR_IMPL_A64__SMMLA_asimdsame2_G(Rd, Rn, B, Rm);
#else
            RT_NOREF(Rd, Rn, B, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/0e002c00: SMOV  <Wd>, <Vn>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdins, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMOV_asimdins_W_w, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x0e002c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SMOV_asimdins_W_w Rd=%#x Rn=%#x imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm5));
#ifdef IEM_INSTR_IMPL_A64__SMOV_asimdins_W_w
            IEM_INSTR_IMPL_A64__SMOV_asimdins_W_w(Rd, Rn, imm5);
#else
            RT_NOREF(Rd, Rn, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4e002c00: SMOV  <Xd>, <Vn>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdins, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMOV_asimdins_X_x, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4e002c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SMOV_asimdins_X_x Rd=%#x Rn=%#x imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm5));
#ifdef IEM_INSTR_IMPL_A64__SMOV_asimdins_X_x
            IEM_INSTR_IMPL_A64__SMOV_asimdins_X_x(Rd, Rn, imm5);
#else
            RT_NOREF(Rd, Rn, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/9b208000: SMSUBL  <Xd>, <Wn>, <Wm>, <Xa>
   Instruction Set: A64  Groups: dp_3src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SMSUBL_64WA_dp_3src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x9b208000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 23) & 0x00000001;
        LogFlow(("%018x/%010x: SMSUBL_64WA_dp_3src Rd=%#x Rn=%#x Ra=%#x Rm=%#x U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm, U));
#ifdef IEM_INSTR_IMPL_A64__SMSUBL_64WA_dp_3src
        IEM_INSTR_IMPL_A64__SMSUBL_64WA_dp_3src(Rd, Rn, Ra, Rm, U);
#else
        RT_NOREF(Rd, Rn, Ra, Rm, U, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9b407c00: SMULH  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: dp_3src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SMULH_64_dp_3src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 23) & 0x00000001;
    LogFlow(("%018x/%010x: SMULH_64_dp_3src Rd=%#x Rn=%#x Rm=%#x U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, U));
#ifdef IEM_INSTR_IMPL_A64__SMULH_64_dp_3src
    IEM_INSTR_IMPL_A64__SMULH_64_dp_3src(Rd, Rn, Rm, U);
#else
    RT_NOREF(Rd, Rn, Rm, U, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf20fc00/0e20c000: SMULL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMULL_asimddiff_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e20c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SMULL_asimddiff_L Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SMULL_asimddiff_L
            IEM_INSTR_IMPL_A64__SMULL_asimddiff_L(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/0f00a000: SMULL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SMULL_asimdelem_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SMULL_asimdelem_L Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SMULL_asimdelem_L
        IEM_INSTR_IMPL_A64__SMULL_asimdelem_L(Rd, Rn, H, Rm, M, L, size, Q);
#else
        RT_NOREF(Rd, Rn, H, Rm, M, L, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e207800: SQABS  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQABS_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQABS_asimdmisc_R Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQABS_asimdmisc_R
        IEM_INSTR_IMPL_A64__SQABS_asimdmisc_R(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/5e207800: SQABS  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQABS_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQABS_asisdmisc_R Rd=%#x Rn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size));
#ifdef IEM_INSTR_IMPL_A64__SQABS_asisdmisc_R
        IEM_INSTR_IMPL_A64__SQABS_asisdmisc_R(Rd, Rn, size);
#else
        RT_NOREF(Rd, Rn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e200c00: SQADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQADD_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQADD_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQADD_asimdsame_only
        IEM_INSTR_IMPL_A64__SQADD_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/5e200c00: SQADD  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQADD_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x5e200c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQADD_asisdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__SQADD_asisdsame_only
            IEM_INSTR_IMPL_A64__SQADD_asisdsame_only(Rd, Rn, Rm, size);
#else
            RT_NOREF(Rd, Rn, Rm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e209000: SQDMLAL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMLAL_asimddiff_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQDMLAL_asimddiff_L Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQDMLAL_asimddiff_L
        IEM_INSTR_IMPL_A64__SQDMLAL_asimddiff_L(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/0f003000: SQDMLAL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMLAL_asimdelem_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQDMLAL_asimdelem_L Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQDMLAL_asimdelem_L
        IEM_INSTR_IMPL_A64__SQDMLAL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q);
#else
        RT_NOREF(Rd, Rn, H, o2, Rm, M, L, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/5e209000: SQDMLAL  <Va><d>, <Vb><n>, <Vb><m>
   Instruction Set: A64  Groups: asisddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMLAL_asisddiff_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQDMLAL_asisddiff_only Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__SQDMLAL_asisddiff_only
        IEM_INSTR_IMPL_A64__SQDMLAL_asisddiff_only(Rd, Rn, o1, Rm, size);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff00f400/5f003000: SQDMLAL  <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMLAL_asisdelem_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff00f400)) == UINT32_C(0x5f003000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQDMLAL_asisdelem_L Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, size));
#ifdef IEM_INSTR_IMPL_A64__SQDMLAL_asisdelem_L
            IEM_INSTR_IMPL_A64__SQDMLAL_asisdelem_L(Rd, Rn, H, o2, Rm, M, L, size);
#else
            RT_NOREF(Rd, Rn, H, o2, Rm, M, L, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e20b000: SQDMLSL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMLSL_asimddiff_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQDMLSL_asimddiff_L Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQDMLSL_asimddiff_L
        IEM_INSTR_IMPL_A64__SQDMLSL_asimddiff_L(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/0f007000: SQDMLSL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMLSL_asimdelem_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQDMLSL_asimdelem_L Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQDMLSL_asimdelem_L
        IEM_INSTR_IMPL_A64__SQDMLSL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q);
#else
        RT_NOREF(Rd, Rn, H, o2, Rm, M, L, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/5e20b000: SQDMLSL  <Va><d>, <Vb><n>, <Vb><m>
   Instruction Set: A64  Groups: asisddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMLSL_asisddiff_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQDMLSL_asisddiff_only Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__SQDMLSL_asisddiff_only
        IEM_INSTR_IMPL_A64__SQDMLSL_asisddiff_only(Rd, Rn, o1, Rm, size);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff00f400/5f007000: SQDMLSL  <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMLSL_asisdelem_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQDMLSL_asisdelem_L Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, size));
#ifdef IEM_INSTR_IMPL_A64__SQDMLSL_asisdelem_L
        IEM_INSTR_IMPL_A64__SQDMLSL_asisdelem_L(Rd, Rn, H, o2, Rm, M, L, size);
#else
        RT_NOREF(Rd, Rn, H, o2, Rm, M, L, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/0f00c000: SQDMULH  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMULH_asimdelem_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x0f00c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQDMULH_asimdelem_R Rd=%#x Rn=%#x H=%u op=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, op, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQDMULH_asimdelem_R
            IEM_INSTR_IMPL_A64__SQDMULH_asimdelem_R(Rd, Rn, H, op, Rm, M, L, size, Q);
#else
            RT_NOREF(Rd, Rn, H, op, Rm, M, L, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e20b400: SQDMULH  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMULH_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e20b400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQDMULH_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQDMULH_asimdsame_only
            IEM_INSTR_IMPL_A64__SQDMULH_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff00f400/5f00c000: SQDMULH  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMULH_asisdelem_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff00f400)) == UINT32_C(0x5f00c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQDMULH_asisdelem_R Rd=%#x Rn=%#x H=%u op=%u Rm=%#x M=%u L=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, op, Rm, M, L, size));
#ifdef IEM_INSTR_IMPL_A64__SQDMULH_asisdelem_R
            IEM_INSTR_IMPL_A64__SQDMULH_asisdelem_R(Rd, Rn, H, op, Rm, M, L, size);
#else
            RT_NOREF(Rd, Rn, H, op, Rm, M, L, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/5e20b400: SQDMULH  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMULH_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQDMULH_asisdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__SQDMULH_asisdsame_only
        IEM_INSTR_IMPL_A64__SQDMULH_asisdsame_only(Rd, Rn, Rm, size);
#else
        RT_NOREF(Rd, Rn, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e20d000: SQDMULL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMULL_asimddiff_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e20d000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQDMULL_asimddiff_L Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQDMULL_asimddiff_L
            IEM_INSTR_IMPL_A64__SQDMULL_asimddiff_L(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/0f00b000: SQDMULL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMULL_asimdelem_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x0f00b000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQDMULL_asimdelem_L Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQDMULL_asimdelem_L
            IEM_INSTR_IMPL_A64__SQDMULL_asimdelem_L(Rd, Rn, H, Rm, M, L, size, Q);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/5e20d000: SQDMULL  <Va><d>, <Vb><n>, <Vb><m>
   Instruction Set: A64  Groups: asisddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMULL_asisddiff_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQDMULL_asisddiff_only Rd=%#x Rn=%#x Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__SQDMULL_asisddiff_only
        IEM_INSTR_IMPL_A64__SQDMULL_asisddiff_only(Rd, Rn, Rm, size);
#else
        RT_NOREF(Rd, Rn, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff00f400/5f00b000: SQDMULL  <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQDMULL_asisdelem_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQDMULL_asisdelem_L Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, size));
#ifdef IEM_INSTR_IMPL_A64__SQDMULL_asisdelem_L
        IEM_INSTR_IMPL_A64__SQDMULL_asisdelem_L(Rd, Rn, H, Rm, M, L, size);
#else
        RT_NOREF(Rd, Rn, H, Rm, M, L, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e207800: SQNEG  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQNEG_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQNEG_asimdmisc_R Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQNEG_asimdmisc_R
        IEM_INSTR_IMPL_A64__SQNEG_asimdmisc_R(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/7e207800: SQNEG  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQNEG_asisdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x7e207800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQNEG_asisdmisc_R Rd=%#x Rn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size));
#ifdef IEM_INSTR_IMPL_A64__SQNEG_asisdmisc_R
            IEM_INSTR_IMPL_A64__SQNEG_asisdmisc_R(Rd, Rn, size);
#else
            RT_NOREF(Rd, Rn, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/2f00d000: SQRDMLAH  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRDMLAH_asimdelem_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x2f00d000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const S          = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdm /*FEAT_RDM*/)
        {
            LogFlow(("%018x/%010x: SQRDMLAH_asimdelem_R Rd=%#x Rn=%#x H=%u S=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, S, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQRDMLAH_asimdelem_R
            IEM_INSTR_IMPL_A64__SQRDMLAH_asimdelem_R(Rd, Rn, H, S, Rm, M, L, size, Q);
#else
            RT_NOREF(Rd, Rn, H, S, Rm, M, L, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e008400: SQRDMLAH  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRDMLAH_asimdsame2_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdm /*FEAT_RDM*/)
    {
        LogFlow(("%018x/%010x: SQRDMLAH_asimdsame2_only Rd=%#x Rn=%#x S=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQRDMLAH_asimdsame2_only
        IEM_INSTR_IMPL_A64__SQRDMLAH_asimdsame2_only(Rd, Rn, S, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, S, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff00f400/7f00d000: SQRDMLAH  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRDMLAH_asisdelem_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff00f400)) == UINT32_C(0x7f00d000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const S          = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdm /*FEAT_RDM*/)
        {
            LogFlow(("%018x/%010x: SQRDMLAH_asisdelem_R Rd=%#x Rn=%#x H=%u S=%u Rm=%#x M=%u L=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, S, Rm, M, L, size));
#ifdef IEM_INSTR_IMPL_A64__SQRDMLAH_asisdelem_R
            IEM_INSTR_IMPL_A64__SQRDMLAH_asisdelem_R(Rd, Rn, H, S, Rm, M, L, size);
#else
            RT_NOREF(Rd, Rn, H, S, Rm, M, L, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/7e008400: SQRDMLAH  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRDMLAH_asisdsame2_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdm /*FEAT_RDM*/)
    {
        LogFlow(("%018x/%010x: SQRDMLAH_asisdsame2_only Rd=%#x Rn=%#x S=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__SQRDMLAH_asisdsame2_only
        IEM_INSTR_IMPL_A64__SQRDMLAH_asisdsame2_only(Rd, Rn, S, Rm, size);
#else
        RT_NOREF(Rd, Rn, S, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/2f00f000: SQRDMLSH  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRDMLSH_asimdelem_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const S          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdm /*FEAT_RDM*/)
    {
        LogFlow(("%018x/%010x: SQRDMLSH_asimdelem_R Rd=%#x Rn=%#x H=%u S=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, S, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQRDMLSH_asimdelem_R
        IEM_INSTR_IMPL_A64__SQRDMLSH_asimdelem_R(Rd, Rn, H, S, Rm, M, L, size, Q);
#else
        RT_NOREF(Rd, Rn, H, S, Rm, M, L, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e008c00: SQRDMLSH  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRDMLSH_asimdsame2_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdm /*FEAT_RDM*/)
    {
        LogFlow(("%018x/%010x: SQRDMLSH_asimdsame2_only Rd=%#x Rn=%#x S=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQRDMLSH_asimdsame2_only
        IEM_INSTR_IMPL_A64__SQRDMLSH_asimdsame2_only(Rd, Rn, S, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, S, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff00f400/7f00f000: SQRDMLSH  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRDMLSH_asisdelem_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff00f400)) == UINT32_C(0x7f00f000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const S          = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdm /*FEAT_RDM*/)
        {
            LogFlow(("%018x/%010x: SQRDMLSH_asisdelem_R Rd=%#x Rn=%#x H=%u S=%u Rm=%#x M=%u L=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, S, Rm, M, L, size));
#ifdef IEM_INSTR_IMPL_A64__SQRDMLSH_asisdelem_R
            IEM_INSTR_IMPL_A64__SQRDMLSH_asisdelem_R(Rd, Rn, H, S, Rm, M, L, size);
#else
            RT_NOREF(Rd, Rn, H, S, Rm, M, L, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/7e008c00: SQRDMLSH  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRDMLSH_asisdsame2_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdm /*FEAT_RDM*/)
    {
        LogFlow(("%018x/%010x: SQRDMLSH_asisdsame2_only Rd=%#x Rn=%#x S=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__SQRDMLSH_asisdsame2_only
        IEM_INSTR_IMPL_A64__SQRDMLSH_asisdsame2_only(Rd, Rn, S, Rm, size);
#else
        RT_NOREF(Rd, Rn, S, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/0f00d000: SQRDMULH  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRDMULH_asimdelem_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x0f00d000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQRDMULH_asimdelem_R Rd=%#x Rn=%#x H=%u op=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, op, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQRDMULH_asimdelem_R
            IEM_INSTR_IMPL_A64__SQRDMULH_asimdelem_R(Rd, Rn, H, op, Rm, M, L, size, Q);
#else
            RT_NOREF(Rd, Rn, H, op, Rm, M, L, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e20b400: SQRDMULH  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRDMULH_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e20b400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQRDMULH_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQRDMULH_asimdsame_only
            IEM_INSTR_IMPL_A64__SQRDMULH_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff00f400/5f00d000: SQRDMULH  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asisdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRDMULH_asisdelem_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 11) & 0x00000001;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    uint32_t const L          = (uOpcode >> 21) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQRDMULH_asisdelem_R Rd=%#x Rn=%#x H=%u op=%u Rm=%#x M=%u L=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, op, Rm, M, L, size));
#ifdef IEM_INSTR_IMPL_A64__SQRDMULH_asisdelem_R
        IEM_INSTR_IMPL_A64__SQRDMULH_asisdelem_R(Rd, Rn, H, op, Rm, M, L, size);
#else
        RT_NOREF(Rd, Rn, H, op, Rm, M, L, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/7e20b400: SQRDMULH  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRDMULH_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x7e20b400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQRDMULH_asisdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__SQRDMULH_asisdsame_only
            IEM_INSTR_IMPL_A64__SQRDMULH_asisdsame_only(Rd, Rn, Rm, size);
#else
            RT_NOREF(Rd, Rn, Rm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e205c00: SQRSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRSHL_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e205c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 11) & 0x00000001;
        uint32_t const R          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQRSHL_asimdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQRSHL_asimdsame_only
            IEM_INSTR_IMPL_A64__SQRSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, S, R, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/5e205c00: SQRSHL  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRSHL_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x5e205c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 11) & 0x00000001;
        uint32_t const R          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQRSHL_asisdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__SQRSHL_asisdsame_only
            IEM_INSTR_IMPL_A64__SQRSHL_asisdsame_only(Rd, Rn, S, R, Rm, size);
#else
            RT_NOREF(Rd, Rn, S, R, Rm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f009c00: SQRSHRN2  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRSHRN_asimdshf_N, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f009c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 11) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
        {
            LogFlow(("%018x/%010x: SQRSHRN_asimdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SQRSHRN_asimdshf_N
            IEM_INSTR_IMPL_A64__SQRSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q);
#else
            RT_NOREF(Rd, Rn, op, immb, immh, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/5f009c00: SQRSHRN  <Vb><d>, <Va><n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRSHRN_asisdshf_N, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x5f009c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 11) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
        {
            LogFlow(("%018x/%010x: SQRSHRN_asisdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SQRSHRN_asisdshf_N
            IEM_INSTR_IMPL_A64__SQRSHRN_asisdshf_N(Rd, Rn, op, immb, immh);
#else
            RT_NOREF(Rd, Rn, op, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f008c00: SQRSHRUN2  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRSHRUN_asimdshf_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 11) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: SQRSHRUN_asimdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SQRSHRUN_asimdshf_N
        IEM_INSTR_IMPL_A64__SQRSHRUN_asimdshf_N(Rd, Rn, op, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, op, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f008c00: SQRSHRUN  <Vb><d>, <Va><n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQRSHRUN_asisdshf_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 11) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
    {
        LogFlow(("%018x/%010x: SQRSHRUN_asisdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SQRSHRUN_asisdshf_N
        IEM_INSTR_IMPL_A64__SQRSHRUN_asisdshf_N(Rd, Rn, op, immb, immh);
#else
        RT_NOREF(Rd, Rn, op, immb, immh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f006400: SQSHLU  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQSHLU_asimdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f006400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
        {
            LogFlow(("%018x/%010x: SQSHLU_asimdshf_R Rd=%#x Rn=%#x op=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SQSHLU_asimdshf_R
            IEM_INSTR_IMPL_A64__SQSHLU_asimdshf_R(Rd, Rn, op, immb, immh, Q);
#else
            RT_NOREF(Rd, Rn, op, immb, immh, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f006400: SQSHLU  <V><d>, <V><n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQSHLU_asisdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f006400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
        {
            LogFlow(("%018x/%010x: SQSHLU_asisdshf_R Rd=%#x Rn=%#x op=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SQSHLU_asisdshf_R
            IEM_INSTR_IMPL_A64__SQSHLU_asisdshf_R(Rd, Rn, op, immb, immh);
#else
            RT_NOREF(Rd, Rn, op, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e204c00: SQSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQSHL_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const R          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQSHL_asimdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQSHL_asimdsame_only
        IEM_INSTR_IMPL_A64__SQSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, S, R, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f007400: SQSHL  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQSHL_asimdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: SQSHL_asimdshf_R Rd=%#x Rn=%#x op=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SQSHL_asimdshf_R
        IEM_INSTR_IMPL_A64__SQSHL_asimdshf_R(Rd, Rn, op, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, op, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/5e204c00: SQSHL  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQSHL_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const R          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQSHL_asisdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__SQSHL_asisdsame_only
        IEM_INSTR_IMPL_A64__SQSHL_asisdsame_only(Rd, Rn, S, R, Rm, size);
#else
        RT_NOREF(Rd, Rn, S, R, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/5f007400: SQSHL  <V><d>, <V><n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQSHL_asisdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 12) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
    {
        LogFlow(("%018x/%010x: SQSHL_asisdshf_R Rd=%#x Rn=%#x op=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SQSHL_asisdshf_R
        IEM_INSTR_IMPL_A64__SQSHL_asisdshf_R(Rd, Rn, op, immb, immh);
#else
        RT_NOREF(Rd, Rn, op, immb, immh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f009400: SQSHRN2  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQSHRN_asimdshf_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 11) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: SQSHRN_asimdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SQSHRN_asimdshf_N
        IEM_INSTR_IMPL_A64__SQSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, op, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/5f009400: SQSHRN  <Vb><d>, <Va><n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQSHRN_asisdshf_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 11) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
    {
        LogFlow(("%018x/%010x: SQSHRN_asisdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SQSHRN_asisdshf_N
        IEM_INSTR_IMPL_A64__SQSHRN_asisdshf_N(Rd, Rn, op, immb, immh);
#else
        RT_NOREF(Rd, Rn, op, immb, immh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f008400: SQSHRUN2  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQSHRUN_asimdshf_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 11) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: SQSHRUN_asimdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SQSHRUN_asimdshf_N
        IEM_INSTR_IMPL_A64__SQSHRUN_asimdshf_N(Rd, Rn, op, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, op, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f008400: SQSHRUN  <Vb><d>, <Va><n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQSHRUN_asisdshf_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 11) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
    {
        LogFlow(("%018x/%010x: SQSHRUN_asisdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SQSHRUN_asisdshf_N
        IEM_INSTR_IMPL_A64__SQSHRUN_asisdshf_N(Rd, Rn, op, immb, immh);
#else
        RT_NOREF(Rd, Rn, op, immb, immh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e202c00: SQSUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQSUB_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQSUB_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQSUB_asimdsame_only
        IEM_INSTR_IMPL_A64__SQSUB_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/5e202c00: SQSUB  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQSUB_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQSUB_asisdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__SQSUB_asisdsame_only
        IEM_INSTR_IMPL_A64__SQSUB_asisdsame_only(Rd, Rn, Rm, size);
#else
        RT_NOREF(Rd, Rn, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e214800: SQXTN2  <Vd>.<Tb>, <Vn>.<Ta>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQXTN_asimdmisc_N, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e214800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SQXTN_asimdmisc_N Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQXTN_asimdmisc_N
            IEM_INSTR_IMPL_A64__SQXTN_asimdmisc_N(Rd, Rn, size, Q);
#else
            RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/5e214800: SQXTN  <Vb><d>, <Va><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQXTN_asisdmisc_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQXTN_asisdmisc_N Rd=%#x Rn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size));
#ifdef IEM_INSTR_IMPL_A64__SQXTN_asisdmisc_N
        IEM_INSTR_IMPL_A64__SQXTN_asisdmisc_N(Rd, Rn, size);
#else
        RT_NOREF(Rd, Rn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e212800: SQXTUN2  <Vd>.<Tb>, <Vn>.<Ta>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQXTUN_asimdmisc_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQXTUN_asimdmisc_N Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SQXTUN_asimdmisc_N
        IEM_INSTR_IMPL_A64__SQXTUN_asimdmisc_N(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/7e212800: SQXTUN  <Vb><d>, <Va><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SQXTUN_asisdmisc_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SQXTUN_asisdmisc_N Rd=%#x Rn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size));
#ifdef IEM_INSTR_IMPL_A64__SQXTUN_asisdmisc_N
        IEM_INSTR_IMPL_A64__SQXTUN_asisdmisc_N(Rd, Rn, size);
#else
        RT_NOREF(Rd, Rn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e201400: SRHADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SRHADD_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SRHADD_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SRHADD_asimdsame_only
        IEM_INSTR_IMPL_A64__SRHADD_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f004400: SRI  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SRI_asimdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f004400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
        {
            LogFlow(("%018x/%010x: SRI_asimdshf_R Rd=%#x Rn=%#x immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SRI_asimdshf_R
            IEM_INSTR_IMPL_A64__SRI_asimdshf_R(Rd, Rn, immb, immh, Q);
#else
            RT_NOREF(Rd, Rn, immb, immh, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f004400: SRI  D<d>, D<n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SRI_asisdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f004400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && (immh & 8) == 8)
        {
            LogFlow(("%018x/%010x: SRI_asisdshf_R Rd=%#x Rn=%#x immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SRI_asisdshf_R
            IEM_INSTR_IMPL_A64__SRI_asisdshf_R(Rd, Rn, immb, immh);
#else
            RT_NOREF(Rd, Rn, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e205400: SRSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SRSHL_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const R          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SRSHL_asimdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SRSHL_asimdsame_only
        IEM_INSTR_IMPL_A64__SRSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, S, R, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5ee05400: SRSHL  D<d>, D<n>, D<m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SRSHL_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5ee05400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 11) & 0x00000001;
        uint32_t const R          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SRSHL_asisdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm));
#ifdef IEM_INSTR_IMPL_A64__SRSHL_asisdsame_only
            IEM_INSTR_IMPL_A64__SRSHL_asisdsame_only(Rd, Rn, S, R, Rm);
#else
            RT_NOREF(Rd, Rn, S, R, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f002400: SRSHR  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SRSHR_asimdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: SRSHR_asimdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SRSHR_asimdshf_R
        IEM_INSTR_IMPL_A64__SRSHR_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, o0, o1, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/5f002400: SRSHR  D<d>, D<n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SRSHR_asisdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x5f002400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && (immh & 8) == 8)
        {
            LogFlow(("%018x/%010x: SRSHR_asisdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SRSHR_asisdshf_R
            IEM_INSTR_IMPL_A64__SRSHR_asisdshf_R(Rd, Rn, o0, o1, immb, immh);
#else
            RT_NOREF(Rd, Rn, o0, o1, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f003400: SRSRA  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SRSRA_asimdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: SRSRA_asimdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SRSRA_asimdshf_R
        IEM_INSTR_IMPL_A64__SRSRA_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, o0, o1, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/5f003400: SRSRA  D<d>, D<n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SRSRA_asisdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && (immh & 8) == 8)
    {
        LogFlow(("%018x/%010x: SRSRA_asisdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SRSRA_asisdshf_R
        IEM_INSTR_IMPL_A64__SRSRA_asisdshf_R(Rd, Rn, o0, o1, immb, immh);
#else
        RT_NOREF(Rd, Rn, o0, o1, immb, immh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f00a400: SSHLL2  <Vd>.<Ta>, <Vn>.<Tb>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SSHLL_asimdshf_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: SSHLL_asimdshf_L Rd=%#x Rn=%#x immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SSHLL_asimdshf_L
        IEM_INSTR_IMPL_A64__SSHLL_asimdshf_L(Rd, Rn, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e204400: SSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SSHL_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const R          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SSHL_asimdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SSHL_asimdsame_only
        IEM_INSTR_IMPL_A64__SSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, S, R, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/5ee04400: SSHL  D<d>, D<n>, D<m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SSHL_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5ee04400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 11) & 0x00000001;
        uint32_t const R          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SSHL_asisdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm));
#ifdef IEM_INSTR_IMPL_A64__SSHL_asisdsame_only
            IEM_INSTR_IMPL_A64__SSHL_asisdsame_only(Rd, Rn, S, R, Rm);
#else
            RT_NOREF(Rd, Rn, S, R, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f000400: SSHR  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SSHR_asimdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: SSHR_asimdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SSHR_asimdshf_R
        IEM_INSTR_IMPL_A64__SSHR_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, o0, o1, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/5f000400: SSHR  D<d>, D<n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SSHR_asisdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x5f000400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && (immh & 8) == 8)
        {
            LogFlow(("%018x/%010x: SSHR_asisdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SSHR_asisdshf_R
            IEM_INSTR_IMPL_A64__SSHR_asisdshf_R(Rd, Rn, o0, o1, immb, immh);
#else
            RT_NOREF(Rd, Rn, o0, o1, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/0f001400: SSRA  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SSRA_asimdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: SSRA_asimdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__SSRA_asimdshf_R
        IEM_INSTR_IMPL_A64__SSRA_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, o0, o1, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/5f001400: SSRA  D<d>, D<n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SSRA_asisdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && (immh & 8) == 8)
    {
        LogFlow(("%018x/%010x: SSRA_asisdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__SSRA_asisdshf_R
        IEM_INSTR_IMPL_A64__SSRA_asisdshf_R(Rd, Rn, o0, o1, immb, immh);
#else
        RT_NOREF(Rd, Rn, o0, o1, immb, immh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e202000: SSUBL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SSUBL_asimddiff_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SSUBL_asimddiff_L Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SSUBL_asimddiff_L
        IEM_INSTR_IMPL_A64__SSUBL_asimddiff_L(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e203000: SSUBW2  <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SSUBW_asimddiff_W, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SSUBW_asimddiff_W Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SSUBW_asimddiff_W
        IEM_INSTR_IMPL_A64__SSUBW_asimddiff_W(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c007000: ST1  { <Vt>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlse_R1_1v, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST1_asisdlse_R1_1v Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlse_R1_1v
        IEM_INSTR_IMPL_A64__ST1_asisdlse_R1_1v(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c00a000: ST1  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlse_R2_2v, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST1_asisdlse_R2_2v Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlse_R2_2v
        IEM_INSTR_IMPL_A64__ST1_asisdlse_R2_2v(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c006000: ST1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlse_R3_3v, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c006000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST1_asisdlse_R3_3v Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlse_R3_3v
            IEM_INSTR_IMPL_A64__ST1_asisdlse_R3_3v(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c002000: ST1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlse_R4_4v, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST1_asisdlse_R4_4v Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlse_R4_4v
        IEM_INSTR_IMPL_A64__ST1_asisdlse_R4_4v(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c9f7000: ST1  { <Vt>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsep_I1_i1, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST1_asisdlsep_I1_i1 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsep_I1_i1
        IEM_INSTR_IMPL_A64__ST1_asisdlsep_I1_i1(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c9fa000: ST1  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsep_I2_i2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c9fa000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST1_asisdlsep_I2_i2 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsep_I2_i2
            IEM_INSTR_IMPL_A64__ST1_asisdlsep_I2_i2(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c9f6000: ST1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsep_I3_i3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c9f6000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST1_asisdlsep_I3_i3 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsep_I3_i3
            IEM_INSTR_IMPL_A64__ST1_asisdlsep_I3_i3(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c9f2000: ST1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsep_I4_i4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c9f2000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST1_asisdlsep_I4_i4 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsep_I4_i4
            IEM_INSTR_IMPL_A64__ST1_asisdlsep_I4_i4(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0c807000: ST1  { <Vt>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsep_R1_r1, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: ST1_asisdlsep_R1_r1 Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsep_R1_r1
        IEM_INSTR_IMPL_A64__ST1_asisdlsep_R1_r1(Rt, Rn, size, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0c80a000: ST1  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsep_R2_r2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0c80a000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: ST1_asisdlsep_R2_r2 Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsep_R2_r2
            IEM_INSTR_IMPL_A64__ST1_asisdlsep_R2_r2(Rt, Rn, size, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0c806000: ST1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsep_R3_r3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0c806000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: ST1_asisdlsep_R3_r3 Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsep_R3_r3
            IEM_INSTR_IMPL_A64__ST1_asisdlsep_R3_r3(Rt, Rn, size, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0c802000: ST1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsep_R4_r4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0c802000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: ST1_asisdlsep_R4_r4 Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsep_R4_r4
            IEM_INSTR_IMPL_A64__ST1_asisdlsep_R4_r4(Rt, Rn, size, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0d000000: ST1  { <Vt>.B }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlso_B1_1b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0d000000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST1_asisdlso_B1_1b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlso_B1_1b
            IEM_INSTR_IMPL_A64__ST1_asisdlso_B1_1b(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0d008400: ST1  { <Vt>.D }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlso_D1_1d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0d008400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST1_asisdlso_D1_1d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlso_D1_1d
            IEM_INSTR_IMPL_A64__ST1_asisdlso_D1_1d(Rt, Rn, Q);
#else
            RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0d004000: ST1  { <Vt>.H }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlso_H1_1h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0d004000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST1_asisdlso_H1_1h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlso_H1_1h
            IEM_INSTR_IMPL_A64__ST1_asisdlso_H1_1h(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0d008000: ST1  { <Vt>.S }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlso_S1_1s, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST1_asisdlso_S1_1s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlso_S1_1s
        IEM_INSTR_IMPL_A64__ST1_asisdlso_S1_1s(Rt, Rn, S, Q);
#else
        RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0d9f0000: ST1  { <Vt>.B }[<index>], [<Xn|SP>], #1
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsop_B1_i1b, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST1_asisdlsop_B1_i1b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsop_B1_i1b
        IEM_INSTR_IMPL_A64__ST1_asisdlsop_B1_i1b(Rt, Rn, size, S, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e000/0d800000: ST1  { <Vt>.B }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsop_BX1_r1b, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: ST1_asisdlsop_BX1_r1b Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsop_BX1_r1b
        IEM_INSTR_IMPL_A64__ST1_asisdlsop_BX1_r1b(Rt, Rn, size, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0d9f8400: ST1  { <Vt>.D }[<index>], [<Xn|SP>], #8
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsop_D1_i1d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST1_asisdlsop_D1_i1d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsop_D1_i1d
        IEM_INSTR_IMPL_A64__ST1_asisdlsop_D1_i1d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0d808400: ST1  { <Vt>.D }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsop_DX1_r1d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: ST1_asisdlsop_DX1_r1d Rt=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsop_DX1_r1d
        IEM_INSTR_IMPL_A64__ST1_asisdlsop_DX1_r1d(Rt, Rn, Rm, Q);
#else
        RT_NOREF(Rt, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0d9f4000: ST1  { <Vt>.H }[<index>], [<Xn|SP>], #2
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsop_H1_i1h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0d9f4000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST1_asisdlsop_H1_i1h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsop_H1_i1h
            IEM_INSTR_IMPL_A64__ST1_asisdlsop_H1_i1h(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e400/0d804000: ST1  { <Vt>.H }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsop_HX1_r1h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e400)) == UINT32_C(0x0d804000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: ST1_asisdlsop_HX1_r1h Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsop_HX1_r1h
            IEM_INSTR_IMPL_A64__ST1_asisdlsop_HX1_r1h(Rt, Rn, size, S, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0d9f8000: ST1  { <Vt>.S }[<index>], [<Xn|SP>], #4
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsop_S1_i1s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0d9f8000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST1_asisdlsop_S1_i1s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsop_S1_i1s
            IEM_INSTR_IMPL_A64__ST1_asisdlsop_S1_i1s(Rt, Rn, S, Q);
#else
            RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0ec00/0d808000: ST1  { <Vt>.S }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST1_asisdlsop_SX1_r1s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0ec00)) == UINT32_C(0x0d808000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: ST1_asisdlsop_SX1_r1s Rt=%#x Rn=%#x S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST1_asisdlsop_SX1_r1s
            IEM_INSTR_IMPL_A64__ST1_asisdlsop_SX1_r1s(Rt, Rn, S, Rm, Q);
#else
            RT_NOREF(Rt, Rn, S, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9a00800: ST2G  <Xt|SP>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2G_64Soffset_ldsttags, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9a00800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
        {
            LogFlow(("%018x/%010x: ST2G_64Soffset_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__ST2G_64Soffset_ldsttags
            IEM_INSTR_IMPL_A64__ST2G_64Soffset_ldsttags(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9a00400: ST2G  <Xt|SP>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2G_64Spost_ldsttags, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: ST2G_64Spost_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__ST2G_64Spost_ldsttags
        IEM_INSTR_IMPL_A64__ST2G_64Spost_ldsttags(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9a00c00: ST2G  <Xt|SP>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2G_64Spre_ldsttags, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: ST2G_64Spre_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__ST2G_64Spre_ldsttags
        IEM_INSTR_IMPL_A64__ST2G_64Spre_ldsttags(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c008000: ST2  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlse_R2, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST2_asisdlse_R2 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlse_R2
        IEM_INSTR_IMPL_A64__ST2_asisdlse_R2(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c9f8000: ST2  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlsep_I2_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c9f8000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST2_asisdlsep_I2_i Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlsep_I2_i
            IEM_INSTR_IMPL_A64__ST2_asisdlsep_I2_i(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0c808000: ST2  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlsep_R2_r, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0c808000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: ST2_asisdlsep_R2_r Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlsep_R2_r
            IEM_INSTR_IMPL_A64__ST2_asisdlsep_R2_r(Rt, Rn, size, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0d200000: ST2  { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlso_B2_2b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0d200000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST2_asisdlso_B2_2b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlso_B2_2b
            IEM_INSTR_IMPL_A64__ST2_asisdlso_B2_2b(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0d208400: ST2  { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlso_D2_2d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST2_asisdlso_D2_2d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlso_D2_2d
        IEM_INSTR_IMPL_A64__ST2_asisdlso_D2_2d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0d204000: ST2  { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlso_H2_2h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0d204000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST2_asisdlso_H2_2h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlso_H2_2h
            IEM_INSTR_IMPL_A64__ST2_asisdlso_H2_2h(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0d208000: ST2  { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlso_S2_2s, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST2_asisdlso_S2_2s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlso_S2_2s
        IEM_INSTR_IMPL_A64__ST2_asisdlso_S2_2s(Rt, Rn, S, Q);
#else
        RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0dbf0000: ST2  { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], #2
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlsop_B2_i2b, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST2_asisdlsop_B2_i2b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlsop_B2_i2b
        IEM_INSTR_IMPL_A64__ST2_asisdlsop_B2_i2b(Rt, Rn, size, S, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e000/0da00000: ST2  { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlsop_BX2_r2b, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: ST2_asisdlsop_BX2_r2b Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlsop_BX2_r2b
        IEM_INSTR_IMPL_A64__ST2_asisdlsop_BX2_r2b(Rt, Rn, size, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0dbf8400: ST2  { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], #16
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlsop_D2_i2d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST2_asisdlsop_D2_i2d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlsop_D2_i2d
        IEM_INSTR_IMPL_A64__ST2_asisdlsop_D2_i2d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0da08400: ST2  { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlsop_DX2_r2d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: ST2_asisdlsop_DX2_r2d Rt=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlsop_DX2_r2d
        IEM_INSTR_IMPL_A64__ST2_asisdlsop_DX2_r2d(Rt, Rn, Rm, Q);
#else
        RT_NOREF(Rt, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0dbf4000: ST2  { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], #4
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlsop_H2_i2h, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST2_asisdlsop_H2_i2h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlsop_H2_i2h
        IEM_INSTR_IMPL_A64__ST2_asisdlsop_H2_i2h(Rt, Rn, size, S, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e400/0da04000: ST2  { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlsop_HX2_r2h, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: ST2_asisdlsop_HX2_r2h Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlsop_HX2_r2h
        IEM_INSTR_IMPL_A64__ST2_asisdlsop_HX2_r2h(Rt, Rn, size, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0dbf8000: ST2  { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], #8
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlsop_S2_i2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0dbf8000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST2_asisdlsop_S2_i2s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlsop_S2_i2s
            IEM_INSTR_IMPL_A64__ST2_asisdlsop_S2_i2s(Rt, Rn, S, Q);
#else
            RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0ec00/0da08000: ST2  { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST2_asisdlsop_SX2_r2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0ec00)) == UINT32_C(0x0da08000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: ST2_asisdlsop_SX2_r2s Rt=%#x Rn=%#x S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST2_asisdlsop_SX2_r2s
            IEM_INSTR_IMPL_A64__ST2_asisdlsop_SX2_r2s(Rt, Rn, S, Rm, Q);
#else
            RT_NOREF(Rt, Rn, S, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c004000: ST3  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlse_R3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c004000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST3_asisdlse_R3 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlse_R3
            IEM_INSTR_IMPL_A64__ST3_asisdlse_R3(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c9f4000: ST3  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlsep_I3_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c9f4000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST3_asisdlsep_I3_i Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlsep_I3_i
            IEM_INSTR_IMPL_A64__ST3_asisdlsep_I3_i(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0c804000: ST3  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlsep_R3_r, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0c804000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: ST3_asisdlsep_R3_r Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlsep_R3_r
            IEM_INSTR_IMPL_A64__ST3_asisdlsep_R3_r(Rt, Rn, size, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0d002000: ST3  { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlso_B3_3b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0d002000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST3_asisdlso_B3_3b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlso_B3_3b
            IEM_INSTR_IMPL_A64__ST3_asisdlso_B3_3b(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0d00a400: ST3  { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlso_D3_3d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST3_asisdlso_D3_3d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlso_D3_3d
        IEM_INSTR_IMPL_A64__ST3_asisdlso_D3_3d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0d006000: ST3  { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlso_H3_3h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0d006000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST3_asisdlso_H3_3h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlso_H3_3h
            IEM_INSTR_IMPL_A64__ST3_asisdlso_H3_3h(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0d00a000: ST3  { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlso_S3_3s, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST3_asisdlso_S3_3s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlso_S3_3s
        IEM_INSTR_IMPL_A64__ST3_asisdlso_S3_3s(Rt, Rn, S, Q);
#else
        RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0d9f2000: ST3  { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], #3
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlsop_B3_i3b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0d9f2000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST3_asisdlsop_B3_i3b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlsop_B3_i3b
            IEM_INSTR_IMPL_A64__ST3_asisdlsop_B3_i3b(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e000/0d802000: ST3  { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlsop_BX3_r3b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e000)) == UINT32_C(0x0d802000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: ST3_asisdlsop_BX3_r3b Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlsop_BX3_r3b
            IEM_INSTR_IMPL_A64__ST3_asisdlsop_BX3_r3b(Rt, Rn, size, S, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0d9fa400: ST3  { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], #24
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlsop_D3_i3d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST3_asisdlsop_D3_i3d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlsop_D3_i3d
        IEM_INSTR_IMPL_A64__ST3_asisdlsop_D3_i3d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0d80a400: ST3  { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlsop_DX3_r3d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: ST3_asisdlsop_DX3_r3d Rt=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlsop_DX3_r3d
        IEM_INSTR_IMPL_A64__ST3_asisdlsop_DX3_r3d(Rt, Rn, Rm, Q);
#else
        RT_NOREF(Rt, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0d9f6000: ST3  { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], #6
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlsop_H3_i3h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0d9f6000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST3_asisdlsop_H3_i3h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlsop_H3_i3h
            IEM_INSTR_IMPL_A64__ST3_asisdlsop_H3_i3h(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e400/0d806000: ST3  { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlsop_HX3_r3h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e400)) == UINT32_C(0x0d806000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: ST3_asisdlsop_HX3_r3h Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlsop_HX3_r3h
            IEM_INSTR_IMPL_A64__ST3_asisdlsop_HX3_r3h(Rt, Rn, size, S, Rm, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0d9fa000: ST3  { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], #12
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlsop_S3_i3s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0d9fa000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST3_asisdlsop_S3_i3s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlsop_S3_i3s
            IEM_INSTR_IMPL_A64__ST3_asisdlsop_S3_i3s(Rt, Rn, S, Q);
#else
            RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0ec00/0d80a000: ST3  { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST3_asisdlsop_SX3_r3s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0ec00)) == UINT32_C(0x0d80a000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
        {
            LogFlow(("%018x/%010x: ST3_asisdlsop_SX3_r3s Rt=%#x Rn=%#x S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST3_asisdlsop_SX3_r3s
            IEM_INSTR_IMPL_A64__ST3_asisdlsop_SX3_r3s(Rt, Rn, S, Rm, Q);
#else
            RT_NOREF(Rt, Rn, S, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c000000: ST4  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlse, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlse_R4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c000000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST4_asisdlse_R4 Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlse_R4
            IEM_INSTR_IMPL_A64__ST4_asisdlse_R4(Rt, Rn, size, Q);
#else
            RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffff000/0c9f0000: ST4  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlsep_I4_i, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST4_asisdlsep_I4_i Rt=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlsep_I4_i
        IEM_INSTR_IMPL_A64__ST4_asisdlsep_I4_i(Rt, Rn, size, Q);
#else
        RT_NOREF(Rt, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0f000/0c800000: ST4  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsep, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlsep_R4_r, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: ST4_asisdlsep_R4_r Rt=%#x Rn=%#x size=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlsep_R4_r
        IEM_INSTR_IMPL_A64__ST4_asisdlsep_R4_r(Rt, Rn, size, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0d202000: ST4  { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlso_B4_4b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0d202000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST4_asisdlso_B4_4b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlso_B4_4b
            IEM_INSTR_IMPL_A64__ST4_asisdlso_B4_4b(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0d20a400: ST4  { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlso_D4_4d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST4_asisdlso_D4_4d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlso_D4_4d
        IEM_INSTR_IMPL_A64__ST4_asisdlso_D4_4d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0d206000: ST4  { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlso_H4_4h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0d206000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 10) & 0x00000003;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST4_asisdlso_H4_4h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlso_H4_4h
            IEM_INSTR_IMPL_A64__ST4_asisdlso_H4_4h(Rt, Rn, size, S, Q);
#else
            RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0d20a000: ST4  { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlso_S4_4s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0d20a000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ST4_asisdlso_S4_4s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlso_S4_4s
            IEM_INSTR_IMPL_A64__ST4_asisdlso_S4_4s(Rt, Rn, S, Q);
#else
            RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe000/0dbf2000: ST4  { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlsop_B4_i4b, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST4_asisdlsop_B4_i4b Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlsop_B4_i4b
        IEM_INSTR_IMPL_A64__ST4_asisdlsop_B4_i4b(Rt, Rn, size, S, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e000/0da02000: ST4  { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlsop_BX4_r4b, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: ST4_asisdlsop_BX4_r4b Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlsop_BX4_r4b
        IEM_INSTR_IMPL_A64__ST4_asisdlsop_BX4_r4b(Rt, Rn, size, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0dbfa400: ST4  { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlsop_D4_i4d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST4_asisdlsop_D4_i4d Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlsop_D4_i4d
        IEM_INSTR_IMPL_A64__ST4_asisdlsop_D4_i4d(Rt, Rn, Q);
#else
        RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0da0a400: ST4  { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlsop_DX4_r4d, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: ST4_asisdlsop_DX4_r4d Rt=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlsop_DX4_r4d
        IEM_INSTR_IMPL_A64__ST4_asisdlsop_DX4_r4d(Rt, Rn, Rm, Q);
#else
        RT_NOREF(Rt, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffe400/0dbf6000: ST4  { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlsop_H4_i4h, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST4_asisdlsop_H4_i4h Rt=%#x Rn=%#x size=%u S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlsop_H4_i4h
        IEM_INSTR_IMPL_A64__ST4_asisdlsop_H4_i4h(Rt, Rn, size, S, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0e400/0da06000: ST4  { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlsop_HX4_r4h, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 10) & 0x00000003;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: ST4_asisdlsop_HX4_r4h Rt=%#x Rn=%#x size=%u S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, size, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlsop_HX4_r4h
        IEM_INSTR_IMPL_A64__ST4_asisdlsop_HX4_r4h(Rt, Rn, size, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, size, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfffec00/0dbfa000: ST4  { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlsop_S4_i4s, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: ST4_asisdlsop_S4_i4s Rt=%#x Rn=%#x S=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlsop_S4_i4s
        IEM_INSTR_IMPL_A64__ST4_asisdlsop_S4_i4s(Rt, Rn, S, Q);
#else
        RT_NOREF(Rt, Rn, S, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0ec00/0da0a000: ST4  { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm>
   Instruction Set: A64  Groups: asisdlsop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST4_asisdlsop_SX4_r4s, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && Rm != 0x1f)
    {
        LogFlow(("%018x/%010x: ST4_asisdlsop_SX4_r4s Rt=%#x Rn=%#x S=%u Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__ST4_asisdlsop_SX4_r4s
        IEM_INSTR_IMPL_A64__ST4_asisdlsop_SX4_r4s(Rt, Rn, S, Rm, Q);
#else
        RT_NOREF(Rt, Rn, S, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f820a000: ST64BV0  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST64BV0_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLs64Accdata /*FEAT_LS64_ACCDATA*/)
    {
        LogFlow(("%018x/%010x: ST64BV0_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__ST64BV0_64_memop
        IEM_INSTR_IMPL_A64__ST64BV0_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f820b000: ST64BV  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST64BV_64_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLs64V /*FEAT_LS64_V*/)
    {
        LogFlow(("%018x/%010x: ST64BV_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__ST64BV_64_memop
        IEM_INSTR_IMPL_A64__ST64BV_64_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/f83f9000: ST64B  <Xt>, [<Xn|SP>{ , #0}]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_ST64B_64L_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLs64 /*FEAT_LS64*/)
    {
        LogFlow(("%018x/%010x: ST64B_64L_memop Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__ST64B_64L_memop
        IEM_INSTR_IMPL_A64__ST64B_64L_memop(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/3c60801f: STBFADDL  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STBFADDL_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x3c60801f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STBFADDL_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STBFADDL_16
            IEM_INSTR_IMPL_A64__STBFADDL_16(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/3c20801f: STBFADD  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STBFADD_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x3c20801f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STBFADD_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STBFADD_16
            IEM_INSTR_IMPL_A64__STBFADD_16(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/3c60c01f: STBFMAXL  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STBFMAXL_16, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STBFMAXL_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STBFMAXL_16
        IEM_INSTR_IMPL_A64__STBFMAXL_16(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/3c60e01f: STBFMAXNML  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STBFMAXNML_16, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STBFMAXNML_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STBFMAXNML_16
        IEM_INSTR_IMPL_A64__STBFMAXNML_16(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/3c20e01f: STBFMAXNM  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STBFMAXNM_16, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STBFMAXNM_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STBFMAXNM_16
        IEM_INSTR_IMPL_A64__STBFMAXNM_16(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/3c20c01f: STBFMAX  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STBFMAX_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x3c20c01f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STBFMAX_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STBFMAX_16
            IEM_INSTR_IMPL_A64__STBFMAX_16(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/3c60d01f: STBFMINL  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STBFMINL_16, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STBFMINL_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STBFMINL_16
        IEM_INSTR_IMPL_A64__STBFMINL_16(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/3c60f01f: STBFMINNML  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STBFMINNML_16, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STBFMINNML_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STBFMINNML_16
        IEM_INSTR_IMPL_A64__STBFMINNML_16(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/3c20f01f: STBFMINNM  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STBFMINNM_16, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STBFMINNM_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STBFMINNM_16
        IEM_INSTR_IMPL_A64__STBFMINNM_16(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/3c20d01f: STBFMIN  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STBFMIN_16, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STBFMIN_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STBFMIN_16
        IEM_INSTR_IMPL_A64__STBFMIN_16(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/7c60801f: STFADDL  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFADDL_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x7c60801f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STFADDL_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFADDL_16
            IEM_INSTR_IMPL_A64__STFADDL_16(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/bc60801f: STFADDL  <Ss>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFADDL_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xbc60801f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STFADDL_32 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFADDL_32
            IEM_INSTR_IMPL_A64__STFADDL_32(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/fc60801f: STFADDL  <Ds>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFADDL_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xfc60801f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STFADDL_64 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFADDL_64
            IEM_INSTR_IMPL_A64__STFADDL_64(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/7c20801f: STFADD  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFADD_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x7c20801f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STFADD_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFADD_16
            IEM_INSTR_IMPL_A64__STFADD_16(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/bc20801f: STFADD  <Ss>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFADD_32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xbc20801f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STFADD_32 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFADD_32
            IEM_INSTR_IMPL_A64__STFADD_32(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/fc20801f: STFADD  <Ds>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFADD_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xfc20801f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STFADD_64 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFADD_64
            IEM_INSTR_IMPL_A64__STFADD_64(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/7c60c01f: STFMAXL  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMAXL_16, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMAXL_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMAXL_16
        IEM_INSTR_IMPL_A64__STFMAXL_16(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/bc60c01f: STFMAXL  <Ss>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMAXL_32, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMAXL_32 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMAXL_32
        IEM_INSTR_IMPL_A64__STFMAXL_32(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/fc60c01f: STFMAXL  <Ds>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMAXL_64, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMAXL_64 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMAXL_64
        IEM_INSTR_IMPL_A64__STFMAXL_64(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/7c60e01f: STFMAXNML  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMAXNML_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x7c60e01f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STFMAXNML_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMAXNML_16
            IEM_INSTR_IMPL_A64__STFMAXNML_16(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/bc60e01f: STFMAXNML  <Ss>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMAXNML_32, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMAXNML_32 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMAXNML_32
        IEM_INSTR_IMPL_A64__STFMAXNML_32(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/fc60e01f: STFMAXNML  <Ds>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMAXNML_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xfc60e01f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STFMAXNML_64 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMAXNML_64
            IEM_INSTR_IMPL_A64__STFMAXNML_64(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/7c20e01f: STFMAXNM  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMAXNM_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x7c20e01f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STFMAXNM_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMAXNM_16
            IEM_INSTR_IMPL_A64__STFMAXNM_16(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/bc20e01f: STFMAXNM  <Ss>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMAXNM_32, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMAXNM_32 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMAXNM_32
        IEM_INSTR_IMPL_A64__STFMAXNM_32(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/fc20e01f: STFMAXNM  <Ds>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMAXNM_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xfc20e01f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STFMAXNM_64 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMAXNM_64
            IEM_INSTR_IMPL_A64__STFMAXNM_64(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/7c20c01f: STFMAX  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMAX_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x7c20c01f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STFMAX_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMAX_16
            IEM_INSTR_IMPL_A64__STFMAX_16(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/bc20c01f: STFMAX  <Ss>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMAX_32, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMAX_32 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMAX_32
        IEM_INSTR_IMPL_A64__STFMAX_32(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/fc20c01f: STFMAX  <Ds>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMAX_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xfc20c01f))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
        {
            LogFlow(("%018x/%010x: STFMAX_64 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMAX_64
            IEM_INSTR_IMPL_A64__STFMAX_64(Rn, Rs);
#else
            RT_NOREF(Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/7c60d01f: STFMINL  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMINL_16, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMINL_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMINL_16
        IEM_INSTR_IMPL_A64__STFMINL_16(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/bc60d01f: STFMINL  <Ss>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMINL_32, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMINL_32 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMINL_32
        IEM_INSTR_IMPL_A64__STFMINL_32(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/fc60d01f: STFMINL  <Ds>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMINL_64, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMINL_64 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMINL_64
        IEM_INSTR_IMPL_A64__STFMINL_64(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/7c60f01f: STFMINNML  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMINNML_16, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMINNML_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMINNML_16
        IEM_INSTR_IMPL_A64__STFMINNML_16(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/bc60f01f: STFMINNML  <Ss>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMINNML_32, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMINNML_32 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMINNML_32
        IEM_INSTR_IMPL_A64__STFMINNML_32(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/fc60f01f: STFMINNML  <Ds>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMINNML_64, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMINNML_64 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMINNML_64
        IEM_INSTR_IMPL_A64__STFMINNML_64(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/7c20f01f: STFMINNM  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMINNM_16, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMINNM_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMINNM_16
        IEM_INSTR_IMPL_A64__STFMINNM_16(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/bc20f01f: STFMINNM  <Ss>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMINNM_32, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMINNM_32 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMINNM_32
        IEM_INSTR_IMPL_A64__STFMINNM_32(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/fc20f01f: STFMINNM  <Ds>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMINNM_64, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMINNM_64 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMINNM_64
        IEM_INSTR_IMPL_A64__STFMINNM_64(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/7c20d01f: STFMIN  <Hs>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMIN_16, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMIN_16 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMIN_16
        IEM_INSTR_IMPL_A64__STFMIN_16(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/bc20d01f: STFMIN  <Ss>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMIN_32, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMIN_32 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMIN_32
        IEM_INSTR_IMPL_A64__STFMIN_32(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc1f/fc20d01f: STFMIN  <Ds>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STFMIN_64, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSFE*/)
    {
        LogFlow(("%018x/%010x: STFMIN_64 Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STFMIN_64
        IEM_INSTR_IMPL_A64__STFMIN_64(Rn, Rs);
#else
        RT_NOREF(Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/d9a00000: STGM  <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STGM_64bulk_ldsttags, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xd9a00000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte2 /*FEAT_MTE2*/)
        {
            LogFlow(("%018x/%010x: STGM_64bulk_ldsttags Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__STGM_64bulk_ldsttags
            IEM_INSTR_IMPL_A64__STGM_64bulk_ldsttags(Rt, Rn);
#else
            RT_NOREF(Rt, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/69000000: STGP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STGP_64_ldstpair_off, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const simm7      = (uOpcode >> 15) & 0x0000007f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: STGP_64_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x simm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, simm7));
#ifdef IEM_INSTR_IMPL_A64__STGP_64_ldstpair_off
        IEM_INSTR_IMPL_A64__STGP_64_ldstpair_off(Rt, Rn, Rt2, simm7);
#else
        RT_NOREF(Rt, Rn, Rt2, simm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/68800000: STGP  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STGP_64_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x68800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const simm7      = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
        {
            LogFlow(("%018x/%010x: STGP_64_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x simm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, simm7));
#ifdef IEM_INSTR_IMPL_A64__STGP_64_ldstpair_post
            IEM_INSTR_IMPL_A64__STGP_64_ldstpair_post(Rt, Rn, Rt2, simm7);
#else
            RT_NOREF(Rt, Rn, Rt2, simm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/69800000: STGP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STGP_64_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x69800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const simm7      = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
        {
            LogFlow(("%018x/%010x: STGP_64_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x simm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, simm7));
#ifdef IEM_INSTR_IMPL_A64__STGP_64_ldstpair_pre
            IEM_INSTR_IMPL_A64__STGP_64_ldstpair_pre(Rt, Rn, Rt2, simm7);
#else
            RT_NOREF(Rt, Rn, Rt2, simm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9200800: STG  <Xt|SP>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STG_64Soffset_ldsttags, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: STG_64Soffset_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STG_64Soffset_ldsttags
        IEM_INSTR_IMPL_A64__STG_64Soffset_ldsttags(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9200400: STG  <Xt|SP>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STG_64Spost_ldsttags, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9200400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
        {
            LogFlow(("%018x/%010x: STG_64Spost_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STG_64Spost_ldsttags
            IEM_INSTR_IMPL_A64__STG_64Spost_ldsttags(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9200c00: STG  <Xt|SP>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STG_64Spre_ldsttags, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9200c00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
        {
            LogFlow(("%018x/%010x: STG_64Spre_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STG_64Spre_ldsttags
            IEM_INSTR_IMPL_A64__STG_64Spre_ldsttags(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/99000800: STILP  <Wt1>, <Wt2>, [<Xn|SP>, #-8]!
   Instruction Set: A64  Groups: ldiappstilp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STILP_32SE_ldiappstilp, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: STILP_32SE_ldiappstilp Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__STILP_32SE_ldiappstilp
        IEM_INSTR_IMPL_A64__STILP_32SE_ldiappstilp(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/99001800: STILP  <Wt1>, <Wt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: ldiappstilp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STILP_32S_ldiappstilp, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: STILP_32S_ldiappstilp Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__STILP_32S_ldiappstilp
        IEM_INSTR_IMPL_A64__STILP_32S_ldiappstilp(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/d9000800: STILP  <Xt1>, <Xt2>, [<Xn|SP>, #-16]!
   Instruction Set: A64  Groups: ldiappstilp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STILP_64SS_ldiappstilp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xd9000800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
        {
            LogFlow(("%018x/%010x: STILP_64SS_ldiappstilp Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__STILP_64SS_ldiappstilp
            IEM_INSTR_IMPL_A64__STILP_64SS_ldiappstilp(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/d9001800: STILP  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: ldiappstilp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STILP_64S_ldiappstilp, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: STILP_64S_ldiappstilp Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__STILP_64S_ldiappstilp
        IEM_INSTR_IMPL_A64__STILP_64S_ldiappstilp(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/0d018400: STL1  { <Vt>.D }[<index>], [<Xn|SP>]
   Instruction Set: A64  Groups: asisdlso, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STL1_asisdlso_D1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0d018400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
        {
            LogFlow(("%018x/%010x: STL1_asisdlso_D1 Rt=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__STL1_asisdlso_D1
            IEM_INSTR_IMPL_A64__STL1_asisdlso_D1(Rt, Rn, Q);
#else
            RT_NOREF(Rt, Rn, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/089f7c00: STLLRB  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLLRB_SL32_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLor /*FEAT_LOR*/)
    {
        LogFlow(("%018x/%010x: STLLRB_SL32_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__STLLRB_SL32_ldstord
        IEM_INSTR_IMPL_A64__STLLRB_SL32_ldstord(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/489f7c00: STLLRH  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLLRH_SL32_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLor /*FEAT_LOR*/)
    {
        LogFlow(("%018x/%010x: STLLRH_SL32_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__STLLRH_SL32_ldstord
        IEM_INSTR_IMPL_A64__STLLRH_SL32_ldstord(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/889f7c00: STLLR  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLLR_SL32_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLor /*FEAT_LOR*/)
    {
        LogFlow(("%018x/%010x: STLLR_SL32_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__STLLR_SL32_ldstord
        IEM_INSTR_IMPL_A64__STLLR_SL32_ldstord(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/c89f7c00: STLLR  <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLLR_SL64_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLor /*FEAT_LOR*/)
    {
        LogFlow(("%018x/%010x: STLLR_SL64_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__STLLR_SL64_ldstord
        IEM_INSTR_IMPL_A64__STLLR_SL64_ldstord(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/089ffc00: STLRB  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLRB_SL32_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: STLRB_SL32_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__STLRB_SL32_ldstord
    IEM_INSTR_IMPL_A64__STLRB_SL32_ldstord(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/489ffc00: STLRH  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLRH_SL32_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: STLRH_SL32_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__STLRH_SL32_ldstord
    IEM_INSTR_IMPL_A64__STLRH_SL32_ldstord(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/99800800: STLR  <Wt>, [<Xn|SP>, #-4]!
   Instruction Set: A64  Groups: ldapstl_writeback, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLR_32S_ldapstl_writeback, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: STLR_32S_ldapstl_writeback Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__STLR_32S_ldapstl_writeback
        IEM_INSTR_IMPL_A64__STLR_32S_ldapstl_writeback(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/d9800800: STLR  <Xt>, [<Xn|SP>, #-8]!
   Instruction Set: A64  Groups: ldapstl_writeback, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLR_64S_ldapstl_writeback, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: STLR_64S_ldapstl_writeback Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__STLR_64S_ldapstl_writeback
        IEM_INSTR_IMPL_A64__STLR_64S_ldapstl_writeback(Rt, Rn);
#else
        RT_NOREF(Rt, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/889ffc00: STLR  <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLR_SL32_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: STLR_SL32_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__STLR_SL32_ldstord
    IEM_INSTR_IMPL_A64__STLR_SL32_ldstord(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* fffffc00/c89ffc00: STLR  <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstord, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLR_SL64_ldstord, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    LogFlow(("%018x/%010x: STLR_SL64_ldstord Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__STLR_SL64_ldstord
    IEM_INSTR_IMPL_A64__STLR_SL64_ldstord(Rt, Rn);
#else
    RT_NOREF(Rt, Rn, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/8900fc00: STLTXR  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLTXR_SR32_ldstexclr_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x8900fc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: STLTXR_SR32_ldstexclr_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STLTXR_SR32_ldstexclr_unpriv
            IEM_INSTR_IMPL_A64__STLTXR_SR32_ldstexclr_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/c900fc00: STLTXR  <Ws>, <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLTXR_SR64_ldstexclr_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xc900fc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: STLTXR_SR64_ldstexclr_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STLTXR_SR64_ldstexclr_unpriv
            IEM_INSTR_IMPL_A64__STLTXR_SR64_ldstexclr_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/19000000: STLURB  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLURB_32_ldapstl_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
    {
        LogFlow(("%018x/%010x: STLURB_32_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STLURB_32_ldapstl_unscaled
        IEM_INSTR_IMPL_A64__STLURB_32_ldapstl_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/59000000: STLURH  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLURH_32_ldapstl_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
    {
        LogFlow(("%018x/%010x: STLURH_32_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STLURH_32_ldapstl_unscaled
        IEM_INSTR_IMPL_A64__STLURH_32_ldapstl_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/99000000: STLUR  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLUR_32_ldapstl_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
    {
        LogFlow(("%018x/%010x: STLUR_32_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STLUR_32_ldapstl_unscaled
        IEM_INSTR_IMPL_A64__STLUR_32_ldapstl_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9000000: STLUR  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLUR_64_ldapstl_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc2 /*FEAT_LRCPC2*/)
    {
        LogFlow(("%018x/%010x: STLUR_64_ldapstl_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STLUR_64_ldapstl_unscaled
        IEM_INSTR_IMPL_A64__STLUR_64_ldapstl_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/1d000800: STLUR  <Bt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_simd, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLUR_B_ldapstl_simd, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: STLUR_B_ldapstl_simd Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STLUR_B_ldapstl_simd
        IEM_INSTR_IMPL_A64__STLUR_B_ldapstl_simd(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/dd000800: STLUR  <Dt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_simd, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLUR_D_ldapstl_simd, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xdd000800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
        {
            LogFlow(("%018x/%010x: STLUR_D_ldapstl_simd Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STLUR_D_ldapstl_simd
            IEM_INSTR_IMPL_A64__STLUR_D_ldapstl_simd(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/5d000800: STLUR  <Ht>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_simd, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLUR_H_ldapstl_simd, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x5d000800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
        {
            LogFlow(("%018x/%010x: STLUR_H_ldapstl_simd Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STLUR_H_ldapstl_simd
            IEM_INSTR_IMPL_A64__STLUR_H_ldapstl_simd(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/1d800800: STLUR  <Qt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_simd, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLUR_Q_ldapstl_simd, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: STLUR_Q_ldapstl_simd Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STLUR_Q_ldapstl_simd
        IEM_INSTR_IMPL_A64__STLUR_Q_ldapstl_simd(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/9d000800: STLUR  <St>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldapstl_simd, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLUR_S_ldapstl_simd, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLrcpc3 /*FEAT_LRCPC3*/)
    {
        LogFlow(("%018x/%010x: STLUR_S_ldapstl_simd Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STLUR_S_ldapstl_simd
        IEM_INSTR_IMPL_A64__STLUR_S_ldapstl_simd(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/88208000: STLXP  <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLXP_SP32_ldstexclp, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: STLXP_SP32_ldstexclp Rt=%#x Rn=%#x Rt2=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, Rs));
#ifdef IEM_INSTR_IMPL_A64__STLXP_SP32_ldstexclp
    IEM_INSTR_IMPL_A64__STLXP_SP32_ldstexclp(Rt, Rn, Rt2, Rs);
#else
    RT_NOREF(Rt, Rn, Rt2, Rs, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe08000/c8208000: STLXP  <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLXP_SP64_ldstexclp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0xc8208000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: STLXP_SP64_ldstexclp Rt=%#x Rn=%#x Rt2=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, Rs));
#ifdef IEM_INSTR_IMPL_A64__STLXP_SP64_ldstexclp
        IEM_INSTR_IMPL_A64__STLXP_SP64_ldstexclp(Rt, Rn, Rt2, Rs);
#else
        RT_NOREF(Rt, Rn, Rt2, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/0800fc00: STLXRB  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLXRB_SR32_ldstexclr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x0800fc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: STLXRB_SR32_ldstexclr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STLXRB_SR32_ldstexclr
        IEM_INSTR_IMPL_A64__STLXRB_SR32_ldstexclr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4800fc00: STLXRH  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLXRH_SR32_ldstexclr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4800fc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: STLXRH_SR32_ldstexclr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STLXRH_SR32_ldstexclr
        IEM_INSTR_IMPL_A64__STLXRH_SR32_ldstexclr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/8800fc00: STLXR  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLXR_SR32_ldstexclr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x8800fc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: STLXR_SR32_ldstexclr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STLXR_SR32_ldstexclr
        IEM_INSTR_IMPL_A64__STLXR_SR32_ldstexclr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/c800fc00: STLXR  <Ws>, <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STLXR_SR64_ldstexclr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xc800fc00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: STLXR_SR64_ldstexclr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STLXR_SR64_ldstexclr
        IEM_INSTR_IMPL_A64__STLXR_SR64_ldstexclr(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/28000000: STNP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STNP_32_ldstnapair_offs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    LogFlow(("%018x/%010x: STNP_32_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STNP_32_ldstnapair_offs
    IEM_INSTR_IMPL_A64__STNP_32_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
    RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/a8000000: STNP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STNP_64_ldstnapair_offs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    LogFlow(("%018x/%010x: STNP_64_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STNP_64_ldstnapair_offs
    IEM_INSTR_IMPL_A64__STNP_64_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
    RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/6c000000: STNP  <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STNP_D_ldstnapair_offs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STNP_D_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STNP_D_ldstnapair_offs
        IEM_INSTR_IMPL_A64__STNP_D_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ac000000: STNP  <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STNP_Q_ldstnapair_offs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STNP_Q_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STNP_Q_ldstnapair_offs
        IEM_INSTR_IMPL_A64__STNP_Q_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/2c000000: STNP  <St1>, <St2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STNP_S_ldstnapair_offs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STNP_S_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STNP_S_ldstnapair_offs
        IEM_INSTR_IMPL_A64__STNP_S_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/29000000: STP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_32_ldstpair_off, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    LogFlow(("%018x/%010x: STP_32_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_32_ldstpair_off
    IEM_INSTR_IMPL_A64__STP_32_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
    RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/28800000: STP  <Wt1>, <Wt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_32_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x28800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: STP_32_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_32_ldstpair_post
        IEM_INSTR_IMPL_A64__STP_32_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/29800000: STP  <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_32_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x29800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: STP_32_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_32_ldstpair_pre
        IEM_INSTR_IMPL_A64__STP_32_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/a9000000: STP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_64_ldstpair_off, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    LogFlow(("%018x/%010x: STP_64_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_64_ldstpair_off
    IEM_INSTR_IMPL_A64__STP_64_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
    RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/a8800000: STP  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_64_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xa8800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: STP_64_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_64_ldstpair_post
        IEM_INSTR_IMPL_A64__STP_64_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/a9800000: STP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_64_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xa9800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        LogFlow(("%018x/%010x: STP_64_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_64_ldstpair_pre
        IEM_INSTR_IMPL_A64__STP_64_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/6d000000: STP  <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_D_ldstpair_off, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STP_D_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_D_ldstpair_off
        IEM_INSTR_IMPL_A64__STP_D_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/6c800000: STP  <Dt1>, <Dt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_D_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x6c800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STP_D_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_D_ldstpair_post
            IEM_INSTR_IMPL_A64__STP_D_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/6d800000: STP  <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_D_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x6d800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STP_D_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_D_ldstpair_pre
            IEM_INSTR_IMPL_A64__STP_D_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ad000000: STP  <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_Q_ldstpair_off, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STP_Q_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_Q_ldstpair_off
        IEM_INSTR_IMPL_A64__STP_Q_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ac800000: STP  <Qt1>, <Qt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_Q_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xac800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STP_Q_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_Q_ldstpair_post
            IEM_INSTR_IMPL_A64__STP_Q_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ad800000: STP  <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_Q_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xad800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STP_Q_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_Q_ldstpair_pre
            IEM_INSTR_IMPL_A64__STP_Q_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/2d000000: STP  <St1>, <St2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_S_ldstpair_off, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STP_S_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_S_ldstpair_off
        IEM_INSTR_IMPL_A64__STP_S_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/2c800000: STP  <St1>, <St2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_S_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x2c800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STP_S_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_S_ldstpair_post
            IEM_INSTR_IMPL_A64__STP_S_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/2d800000: STP  <St1>, <St2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STP_S_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x2d800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STP_S_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STP_S_ldstpair_pre
            IEM_INSTR_IMPL_A64__STP_S_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0ec00/38206800: STRB  <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STRB_32BL_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: STRB_32BL_ldst_regoff Rt=%#x Rn=%#x S=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm));
#ifdef IEM_INSTR_IMPL_A64__STRB_32BL_ldst_regoff
    IEM_INSTR_IMPL_A64__STRB_32BL_ldst_regoff(Rt, Rn, S, Rm);
#else
    RT_NOREF(Rt, Rn, S, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/38200800: STRB  <Wt>, [<Xn|SP>, {<Wm> | <Xm>}, <extend>{ <amount>}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STRB_32B_ldst_regoff, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38200800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (option != 3)
        {
            LogFlow(("%018x/%010x: STRB_32B_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__STRB_32B_ldst_regoff
            IEM_INSTR_IMPL_A64__STRB_32B_ldst_regoff(Rt, Rn, S, option, Rm);
#else
            RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38000400: STRB  <Wt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STRB_32_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38000400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: STRB_32_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STRB_32_ldst_immpost
        IEM_INSTR_IMPL_A64__STRB_32_ldst_immpost(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38000c00: STRB  <Wt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STRB_32_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: STRB_32_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STRB_32_ldst_immpre
    IEM_INSTR_IMPL_A64__STRB_32_ldst_immpre(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/39000000: STRB  <Wt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STRB_32_ldst_pos, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    LogFlow(("%018x/%010x: STRB_32_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__STRB_32_ldst_pos
    IEM_INSTR_IMPL_A64__STRB_32_ldst_pos(Rt, Rn, imm12);
#else
    RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/78000400: STRH  <Wt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STRH_32_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78000400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: STRH_32_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STRH_32_ldst_immpost
        IEM_INSTR_IMPL_A64__STRH_32_ldst_immpost(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/78000c00: STRH  <Wt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STRH_32_ldst_immpre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78000c00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: STRH_32_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STRH_32_ldst_immpre
        IEM_INSTR_IMPL_A64__STRH_32_ldst_immpre(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/79000000: STRH  <Wt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STRH_32_ldst_pos, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    LogFlow(("%018x/%010x: STRH_32_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__STRH_32_ldst_pos
    IEM_INSTR_IMPL_A64__STRH_32_ldst_pos(Rt, Rn, imm12);
#else
    RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/78200800: STRH  <Wt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STRH_32_ldst_regoff, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78200800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: STRH_32_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__STRH_32_ldst_regoff
        IEM_INSTR_IMPL_A64__STRH_32_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/b8000400: STR  <Wt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_32_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8000400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: STR_32_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_32_ldst_immpost
        IEM_INSTR_IMPL_A64__STR_32_ldst_immpost(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/b8000c00: STR  <Wt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_32_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: STR_32_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_32_ldst_immpre
    IEM_INSTR_IMPL_A64__STR_32_ldst_immpre(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/b9000000: STR  <Wt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_32_ldst_pos, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    LogFlow(("%018x/%010x: STR_32_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__STR_32_ldst_pos
    IEM_INSTR_IMPL_A64__STR_32_ldst_pos(Rt, Rn, imm12);
#else
    RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/b8200800: STR  <Wt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_32_ldst_regoff, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8200800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: STR_32_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__STR_32_ldst_regoff
        IEM_INSTR_IMPL_A64__STR_32_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/f8000400: STR  <Xt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_64_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xf8000400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: STR_64_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_64_ldst_immpost
        IEM_INSTR_IMPL_A64__STR_64_ldst_immpost(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/f8000c00: STR  <Xt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_64_ldst_immpre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xf8000c00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        LogFlow(("%018x/%010x: STR_64_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_64_ldst_immpre
        IEM_INSTR_IMPL_A64__STR_64_ldst_immpre(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/f9000000: STR  <Xt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_64_ldst_pos, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    LogFlow(("%018x/%010x: STR_64_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__STR_64_ldst_pos
    IEM_INSTR_IMPL_A64__STR_64_ldst_pos(Rt, Rn, imm12);
#else
    RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/f8200800: STR  <Xt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_64_ldst_regoff, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xf8200800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: STR_64_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__STR_64_ldst_regoff
        IEM_INSTR_IMPL_A64__STR_64_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0ec00/3c206800: STR  <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_BL_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STR_BL_ldst_regoff Rt=%#x Rn=%#x S=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, Rm));
#ifdef IEM_INSTR_IMPL_A64__STR_BL_ldst_regoff
        IEM_INSTR_IMPL_A64__STR_BL_ldst_regoff(Rt, Rn, S, Rm);
#else
        RT_NOREF(Rt, Rn, S, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3c000400: STR  <Bt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_B_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3c000400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STR_B_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_B_ldst_immpost
            IEM_INSTR_IMPL_A64__STR_B_ldst_immpost(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3c000c00: STR  <Bt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_B_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STR_B_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_B_ldst_immpre
        IEM_INSTR_IMPL_A64__STR_B_ldst_immpre(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/3d000000: STR  <Bt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_B_ldst_pos, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STR_B_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__STR_B_ldst_pos
        IEM_INSTR_IMPL_A64__STR_B_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3c200800: STR  <Bt>, [<Xn|SP>, {<Wm> | <Xm>}, <extend>{ <amount>}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_B_ldst_regoff, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3c200800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && option != 3)
        {
            LogFlow(("%018x/%010x: STR_B_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__STR_B_ldst_regoff
            IEM_INSTR_IMPL_A64__STR_B_ldst_regoff(Rt, Rn, S, option, Rm);
#else
            RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/fc000400: STR  <Dt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_D_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xfc000400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STR_D_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_D_ldst_immpost
            IEM_INSTR_IMPL_A64__STR_D_ldst_immpost(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/fc000c00: STR  <Dt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_D_ldst_immpre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xfc000c00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STR_D_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_D_ldst_immpre
            IEM_INSTR_IMPL_A64__STR_D_ldst_immpre(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/fd000000: STR  <Dt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_D_ldst_pos, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STR_D_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__STR_D_ldst_pos
        IEM_INSTR_IMPL_A64__STR_D_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/fc200800: STR  <Dt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_D_ldst_regoff, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xfc200800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STR_D_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__STR_D_ldst_regoff
            IEM_INSTR_IMPL_A64__STR_D_ldst_regoff(Rt, Rn, S, option, Rm);
#else
            RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/7c000400: STR  <Ht>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_H_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x7c000400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STR_H_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_H_ldst_immpost
            IEM_INSTR_IMPL_A64__STR_H_ldst_immpost(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/7c000c00: STR  <Ht>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_H_ldst_immpre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x7c000c00))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STR_H_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_H_ldst_immpre
            IEM_INSTR_IMPL_A64__STR_H_ldst_immpre(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/7d000000: STR  <Ht>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_H_ldst_pos, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STR_H_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__STR_H_ldst_pos
        IEM_INSTR_IMPL_A64__STR_H_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/7c200800: STR  <Ht>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_H_ldst_regoff, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x7c200800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STR_H_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__STR_H_ldst_regoff
            IEM_INSTR_IMPL_A64__STR_H_ldst_regoff(Rt, Rn, S, option, Rm);
#else
            RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3c800400: STR  <Qt>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_Q_ldst_immpost, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STR_Q_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_Q_ldst_immpost
        IEM_INSTR_IMPL_A64__STR_Q_ldst_immpost(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3c800c00: STR  <Qt>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_Q_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STR_Q_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_Q_ldst_immpre
        IEM_INSTR_IMPL_A64__STR_Q_ldst_immpre(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/3d800000: STR  <Qt>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_Q_ldst_pos, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0x3d800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STR_Q_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__STR_Q_ldst_pos
            IEM_INSTR_IMPL_A64__STR_Q_ldst_pos(Rt, Rn, imm12);
#else
            RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3ca00800: STR  <Qt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_Q_ldst_regoff, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const option     = (uOpcode >> 13) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STR_Q_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__STR_Q_ldst_regoff
        IEM_INSTR_IMPL_A64__STR_Q_ldst_regoff(Rt, Rn, S, option, Rm);
#else
        RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/bc000400: STR  <St>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldst_immpost, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_S_ldst_immpost, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xbc000400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STR_S_ldst_immpost Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_S_ldst_immpost
            IEM_INSTR_IMPL_A64__STR_S_ldst_immpost(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/bc000c00: STR  <St>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldst_immpre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_S_ldst_immpre, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STR_S_ldst_immpre Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STR_S_ldst_immpre
        IEM_INSTR_IMPL_A64__STR_S_ldst_immpre(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/bd000000: STR  <St>, [<Xn|SP>{, #<pimm>}]
   Instruction Set: A64  Groups: ldst_pos, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_S_ldst_pos, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STR_S_ldst_pos Rt=%#x Rn=%#x imm12=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm12));
#ifdef IEM_INSTR_IMPL_A64__STR_S_ldst_pos
        IEM_INSTR_IMPL_A64__STR_S_ldst_pos(Rt, Rn, imm12);
#else
        RT_NOREF(Rt, Rn, imm12, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/bc200800: STR  <St>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}]
   Instruction Set: A64  Groups: ldst_regoff, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STR_S_ldst_regoff, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xbc200800))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STR_S_ldst_regoff Rt=%#x Rn=%#x S=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, S, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__STR_S_ldst_regoff
            IEM_INSTR_IMPL_A64__STR_S_ldst_regoff(Rt, Rn, S, option, Rm);
#else
            RT_NOREF(Rt, Rn, S, option, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffff1f/d503261f: STSHH  <policy>
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_STSHH_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffff1f)) == UINT32_C(0xd503261f))
    {
        uint32_t const op2        = (uOpcode >>  5) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_PCDPHINT*/ && (op2 & 6) == 0)
        {
            LogFlow(("%018x/%010x: STSHH_HI_hints op2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, op2));
#ifdef IEM_INSTR_IMPL_A64__STSHH_HI_hints
            IEM_INSTR_IMPL_A64__STSHH_HI_hints(op2);
#else
            RT_NOREF(op2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/e8000000: STTNP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTNP_64_ldstnapair_offs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: STTNP_64_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STTNP_64_ldstnapair_offs
        IEM_INSTR_IMPL_A64__STTNP_64_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ec000000: STTNP  <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstnapair_offs, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTNP_Q_ldstnapair_offs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: STTNP_Q_ldstnapair_offs Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STTNP_Q_ldstnapair_offs
        IEM_INSTR_IMPL_A64__STTNP_Q_ldstnapair_offs(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/e9000000: STTP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTP_64_ldstpair_off, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: STTP_64_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STTP_64_ldstpair_off
        IEM_INSTR_IMPL_A64__STTP_64_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/e8800000: STTP  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTP_64_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xe8800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: STTP_64_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STTP_64_ldstpair_post
            IEM_INSTR_IMPL_A64__STTP_64_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/e9800000: STTP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTP_64_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xe9800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: STTP_64_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STTP_64_ldstpair_pre
            IEM_INSTR_IMPL_A64__STTP_64_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ed000000: STTP  <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: ldstpair_off, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTP_Q_ldstpair_off, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: STTP_Q_ldstpair_off Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STTP_Q_ldstpair_off
        IEM_INSTR_IMPL_A64__STTP_Q_ldstpair_off(Rt, Rn, Rt2, imm7);
#else
        RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ec800000: STTP  <Qt1>, <Qt2>, [<Xn|SP>], #<imm>
   Instruction Set: A64  Groups: ldstpair_post, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTP_Q_ldstpair_post, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xec800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: STTP_Q_ldstpair_post Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STTP_Q_ldstpair_post
            IEM_INSTR_IMPL_A64__STTP_Q_ldstpair_post(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/ed800000: STTP  <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!
   Instruction Set: A64  Groups: ldstpair_pre, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTP_Q_ldstpair_pre, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xed800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const imm7       = (uOpcode >> 15) & 0x0000007f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: STTP_Q_ldstpair_pre Rt=%#x Rn=%#x Rt2=%#x imm7=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, imm7));
#ifdef IEM_INSTR_IMPL_A64__STTP_Q_ldstpair_pre
            IEM_INSTR_IMPL_A64__STTP_Q_ldstpair_pre(Rt, Rn, Rt2, imm7);
#else
            RT_NOREF(Rt, Rn, Rt2, imm7, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38000800: STTRB  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTRB_32_ldst_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: STTRB_32_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STTRB_32_ldst_unpriv
    IEM_INSTR_IMPL_A64__STTRB_32_ldst_unpriv(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/78000800: STTRH  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTRH_32_ldst_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: STTRH_32_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STTRH_32_ldst_unpriv
    IEM_INSTR_IMPL_A64__STTRH_32_ldst_unpriv(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/b8000800: STTR  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTR_32_ldst_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: STTR_32_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STTR_32_ldst_unpriv
    IEM_INSTR_IMPL_A64__STTR_32_ldst_unpriv(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/f8000800: STTR  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTR_64_ldst_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: STTR_64_ldst_unpriv Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STTR_64_ldst_unpriv
    IEM_INSTR_IMPL_A64__STTR_64_ldst_unpriv(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/89007c00: STTXR  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTXR_SR32_ldstexclr_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: STTXR_SR32_ldstexclr_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STTXR_SR32_ldstexclr_unpriv
        IEM_INSTR_IMPL_A64__STTXR_SR32_ldstexclr_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/c9007c00: STTXR  <Ws>, <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STTXR_SR64_ldstexclr_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: STTXR_SR64_ldstexclr_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STTXR_SR64_ldstexclr_unpriv
        IEM_INSTR_IMPL_A64__STTXR_SR64_ldstexclr_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/38000000: STURB  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STURB_32_ldst_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: STURB_32_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STURB_32_ldst_unscaled
    IEM_INSTR_IMPL_A64__STURB_32_ldst_unscaled(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/78000000: STURH  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STURH_32_ldst_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: STURH_32_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STURH_32_ldst_unscaled
    IEM_INSTR_IMPL_A64__STURH_32_ldst_unscaled(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/b8000000: STUR  <Wt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STUR_32_ldst_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: STUR_32_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STUR_32_ldst_unscaled
    IEM_INSTR_IMPL_A64__STUR_32_ldst_unscaled(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/f8000000: STUR  <Xt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STUR_64_ldst_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    LogFlow(("%018x/%010x: STUR_64_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STUR_64_ldst_unscaled
    IEM_INSTR_IMPL_A64__STUR_64_ldst_unscaled(Rt, Rn, imm9);
#else
    RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/3c000000: STUR  <Bt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STUR_B_ldst_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STUR_B_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STUR_B_ldst_unscaled
        IEM_INSTR_IMPL_A64__STUR_B_ldst_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/fc000000: STUR  <Dt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STUR_D_ldst_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STUR_D_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STUR_D_ldst_unscaled
        IEM_INSTR_IMPL_A64__STUR_D_ldst_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/7c000000: STUR  <Ht>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STUR_H_ldst_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STUR_H_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STUR_H_ldst_unscaled
        IEM_INSTR_IMPL_A64__STUR_H_ldst_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/3c800000: STUR  <Qt>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STUR_Q_ldst_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3c800000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: STUR_Q_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STUR_Q_ldst_unscaled
            IEM_INSTR_IMPL_A64__STUR_Q_ldst_unscaled(Rt, Rn, imm9);
#else
            RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/bc000000: STUR  <St>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldst_unscaled, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STUR_S_ldst_unscaled, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: STUR_S_ldst_unscaled Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STUR_S_ldst_unscaled
        IEM_INSTR_IMPL_A64__STUR_S_ldst_unscaled(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/88200000: STXP  <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STXP_SP32_ldstexclp, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: STXP_SP32_ldstexclp Rt=%#x Rn=%#x Rt2=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, Rs));
#ifdef IEM_INSTR_IMPL_A64__STXP_SP32_ldstexclp
    IEM_INSTR_IMPL_A64__STXP_SP32_ldstexclp(Rt, Rn, Rt2, Rs);
#else
    RT_NOREF(Rt, Rn, Rt2, Rs, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe08000/c8200000: STXP  <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclp, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STXP_SP64_ldstexclp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0xc8200000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: STXP_SP64_ldstexclp Rt=%#x Rn=%#x Rt2=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2, Rs));
#ifdef IEM_INSTR_IMPL_A64__STXP_SP64_ldstexclp
        IEM_INSTR_IMPL_A64__STXP_SP64_ldstexclp(Rt, Rn, Rt2, Rs);
#else
        RT_NOREF(Rt, Rn, Rt2, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/08007c00: STXRB  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STXRB_SR32_ldstexclr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: STXRB_SR32_ldstexclr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STXRB_SR32_ldstexclr
    IEM_INSTR_IMPL_A64__STXRB_SR32_ldstexclr(Rt, Rn, Rs);
#else
    RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/48007c00: STXRH  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STXRH_SR32_ldstexclr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: STXRH_SR32_ldstexclr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STXRH_SR32_ldstexclr
    IEM_INSTR_IMPL_A64__STXRH_SR32_ldstexclr(Rt, Rn, Rs);
#else
    RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/88007c00: STXR  <Ws>, <Wt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STXR_SR32_ldstexclr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: STXR_SR32_ldstexclr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STXR_SR32_ldstexclr
    IEM_INSTR_IMPL_A64__STXR_SR32_ldstexclr(Rt, Rn, Rs);
#else
    RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/c8007c00: STXR  <Ws>, <Xt>, [<Xn|SP>{, #0}]
   Instruction Set: A64  Groups: ldstexclr, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STXR_SR64_ldstexclr, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: STXR_SR64_ldstexclr Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__STXR_SR64_ldstexclr
    IEM_INSTR_IMPL_A64__STXR_SR64_ldstexclr(Rt, Rn, Rs);
#else
    RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00c00/d9e00800: STZ2G  <Xt|SP>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STZ2G_64Soffset_ldsttags, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: STZ2G_64Soffset_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STZ2G_64Soffset_ldsttags
        IEM_INSTR_IMPL_A64__STZ2G_64Soffset_ldsttags(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9e00400: STZ2G  <Xt|SP>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STZ2G_64Spost_ldsttags, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: STZ2G_64Spost_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STZ2G_64Spost_ldsttags
        IEM_INSTR_IMPL_A64__STZ2G_64Spost_ldsttags(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9e00c00: STZ2G  <Xt|SP>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STZ2G_64Spre_ldsttags, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: STZ2G_64Spre_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STZ2G_64Spre_ldsttags
        IEM_INSTR_IMPL_A64__STZ2G_64Spre_ldsttags(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/d9200000: STZGM  <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STZGM_64bulk_ldsttags, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xd9200000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte2 /*FEAT_MTE2*/)
        {
            LogFlow(("%018x/%010x: STZGM_64bulk_ldsttags Rt=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn));
#ifdef IEM_INSTR_IMPL_A64__STZGM_64bulk_ldsttags
            IEM_INSTR_IMPL_A64__STZGM_64bulk_ldsttags(Rt, Rn);
#else
            RT_NOREF(Rt, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9600800: STZG  <Xt|SP>, [<Xn|SP>{, #<simm>}]
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STZG_64Soffset_ldsttags, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: STZG_64Soffset_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STZG_64Soffset_ldsttags
        IEM_INSTR_IMPL_A64__STZG_64Soffset_ldsttags(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9600400: STZG  <Xt|SP>, [<Xn|SP>], #<simm>
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STZG_64Spost_ldsttags, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: STZG_64Spost_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STZG_64Spost_ldsttags
        IEM_INSTR_IMPL_A64__STZG_64Spost_ldsttags(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00c00/d9600c00: STZG  <Xt|SP>, [<Xn|SP>, #<simm>]!
   Instruction Set: A64  Groups: ldsttags, ldst */
FNIEMOP_DEF_1(iemDecodeA64_STZG_64Spre_ldsttags, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9       = (uOpcode >> 12) & 0x000001ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: STZG_64Spre_ldsttags Rt=%#x Rn=%#x imm9=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, imm9));
#ifdef IEM_INSTR_IMPL_A64__STZG_64Spre_ldsttags
        IEM_INSTR_IMPL_A64__STZG_64Spre_ldsttags(Rt, Rn, imm9);
#else
        RT_NOREF(Rt, Rn, imm9, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0c000/d1800000: SUBG  <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4>
   Instruction Set: A64  Groups: addsub_immtags, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_SUBG_64_addsub_immtags, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 10) & 0x0000000f;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SUBG_64_addsub_immtags Rd=%#x Rn=%#x imm4=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm4, imm6));
#ifdef IEM_INSTR_IMPL_A64__SUBG_64_addsub_immtags
        IEM_INSTR_IMPL_A64__SUBG_64_addsub_immtags(Rd, Rn, imm4, imm6);
#else
        RT_NOREF(Rd, Rn, imm4, imm6, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e206000: SUBHN2  <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SUBHN_asimddiff_N, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e206000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SUBHN_asimddiff_N Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SUBHN_asimddiff_N
            IEM_INSTR_IMPL_A64__SUBHN_asimddiff_N(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/bac00000: SUBPS  <Xd>, <Xn|SP>, <Xm|SP>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SUBPS_64S_dp_2src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbac00000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
        {
            LogFlow(("%018x/%010x: SUBPS_64S_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SUBPS_64S_dp_2src
            IEM_INSTR_IMPL_A64__SUBPS_64S_dp_2src(Rd, Rn, Rm);
#else
            RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/da002000: SUBPT  <Xd|SP>, <Xn|SP>, <Xm>{, LSL #<amount>}
   Instruction Set: A64  Groups: addsub_pt, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SUBPT_64_addsub_pt, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xda002000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CPA*/)
        {
            LogFlow(("%018x/%010x: SUBPT_64_addsub_pt Rd=%#x Rn=%#x imm3=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm3, Rm));
#ifdef IEM_INSTR_IMPL_A64__SUBPT_64_addsub_pt
            IEM_INSTR_IMPL_A64__SUBPT_64_addsub_pt(Rd, Rn, imm3, Rm);
#else
            RT_NOREF(Rd, Rn, imm3, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9ac00000: SUBP  <Xd>, <Xn|SP>, <Xm|SP>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SUBP_64S_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMte /*FEAT_MTE*/)
    {
        LogFlow(("%018x/%010x: SUBP_64S_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SUBP_64S_dp_2src
        IEM_INSTR_IMPL_A64__SUBP_64S_dp_2src(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00000/6b200000: SUBS  <Wd>, <Wn|WSP>, <Wm>{, <extend>{ #<amount>}}
   Instruction Set: A64  Groups: addsub_ext, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SUBS_32S_addsub_ext, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00000)) == UINT32_C(0x6b200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >> 10) & 0x00000007;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: SUBS_32S_addsub_ext Rd=%#x Rn=%#x imm3=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm3, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__SUBS_32S_addsub_ext
        IEM_INSTR_IMPL_A64__SUBS_32S_addsub_ext(Rd, Rn, imm3, option, Rm);
#else
        RT_NOREF(Rd, Rn, imm3, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff800000/71000000: SUBS  <Wd>, <Wn|WSP>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: addsub_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_SUBS_32S_addsub_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    uint32_t const sh         = (uOpcode >> 22) & 0x00000001;
    LogFlow(("%018x/%010x: SUBS_32S_addsub_imm Rd=%#x Rn=%#x imm12=%#x sh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm12, sh));
#ifdef IEM_INSTR_IMPL_A64__SUBS_32S_addsub_imm
    IEM_INSTR_IMPL_A64__SUBS_32S_addsub_imm(Rd, Rn, imm12, sh);
#else
    RT_NOREF(Rd, Rn, imm12, sh, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/6b000000: SUBS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: addsub_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SUBS_32_addsub_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: SUBS_32_addsub_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__SUBS_32_addsub_shift
    IEM_INSTR_IMPL_A64__SUBS_32_addsub_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00000/eb200000: SUBS  <Xd>, <Xn|SP>, <R><m>{, <extend>{ #<amount>}}
   Instruction Set: A64  Groups: addsub_ext, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SUBS_64S_addsub_ext, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00000)) == UINT32_C(0xeb200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >> 10) & 0x00000007;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: SUBS_64S_addsub_ext Rd=%#x Rn=%#x imm3=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm3, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__SUBS_64S_addsub_ext
        IEM_INSTR_IMPL_A64__SUBS_64S_addsub_ext(Rd, Rn, imm3, option, Rm);
#else
        RT_NOREF(Rd, Rn, imm3, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff800000/f1000000: SUBS  <Xd>, <Xn|SP>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: addsub_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_SUBS_64S_addsub_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    uint32_t const sh         = (uOpcode >> 22) & 0x00000001;
    LogFlow(("%018x/%010x: SUBS_64S_addsub_imm Rd=%#x Rn=%#x imm12=%#x sh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm12, sh));
#ifdef IEM_INSTR_IMPL_A64__SUBS_64S_addsub_imm
    IEM_INSTR_IMPL_A64__SUBS_64S_addsub_imm(Rd, Rn, imm12, sh);
#else
    RT_NOREF(Rd, Rn, imm12, sh, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/eb000000: SUBS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: addsub_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SUBS_64_addsub_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: SUBS_64_addsub_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__SUBS_64_addsub_shift
    IEM_INSTR_IMPL_A64__SUBS_64_addsub_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00000/4b200000: SUB  <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend>{ #<amount>}}
   Instruction Set: A64  Groups: addsub_ext, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SUB_32_addsub_ext, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00000)) == UINT32_C(0x4b200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >> 10) & 0x00000007;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: SUB_32_addsub_ext Rd=%#x Rn=%#x imm3=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm3, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__SUB_32_addsub_ext
        IEM_INSTR_IMPL_A64__SUB_32_addsub_ext(Rd, Rn, imm3, option, Rm);
#else
        RT_NOREF(Rd, Rn, imm3, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff800000/51000000: SUB  <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: addsub_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_SUB_32_addsub_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    uint32_t const sh         = (uOpcode >> 22) & 0x00000001;
    LogFlow(("%018x/%010x: SUB_32_addsub_imm Rd=%#x Rn=%#x imm12=%#x sh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm12, sh));
#ifdef IEM_INSTR_IMPL_A64__SUB_32_addsub_imm
    IEM_INSTR_IMPL_A64__SUB_32_addsub_imm(Rd, Rn, imm12, sh);
#else
    RT_NOREF(Rd, Rn, imm12, sh, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/4b000000: SUB  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: addsub_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SUB_32_addsub_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: SUB_32_addsub_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__SUB_32_addsub_shift
    IEM_INSTR_IMPL_A64__SUB_32_addsub_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe00000/cb200000: SUB  <Xd|SP>, <Xn|SP>, <R><m>{, <extend>{ #<amount>}}
   Instruction Set: A64  Groups: addsub_ext, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SUB_64_addsub_ext, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00000)) == UINT32_C(0xcb200000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >> 10) & 0x00000007;
        uint32_t const option     = (uOpcode >> 13) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        LogFlow(("%018x/%010x: SUB_64_addsub_ext Rd=%#x Rn=%#x imm3=%u option=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm3, option, Rm));
#ifdef IEM_INSTR_IMPL_A64__SUB_64_addsub_ext
        IEM_INSTR_IMPL_A64__SUB_64_addsub_ext(Rd, Rn, imm3, option, Rm);
#else
        RT_NOREF(Rd, Rn, imm3, option, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff800000/d1000000: SUB  <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: addsub_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_SUB_64_addsub_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm12      = (uOpcode >> 10) & 0x00000fff;
    uint32_t const sh         = (uOpcode >> 22) & 0x00000001;
    LogFlow(("%018x/%010x: SUB_64_addsub_imm Rd=%#x Rn=%#x imm12=%#x sh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm12, sh));
#ifdef IEM_INSTR_IMPL_A64__SUB_64_addsub_imm
    IEM_INSTR_IMPL_A64__SUB_64_addsub_imm(Rd, Rn, imm12, sh);
#else
    RT_NOREF(Rd, Rn, imm12, sh, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ff200000/cb000000: SUB  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
   Instruction Set: A64  Groups: addsub_shift, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_SUB_64_addsub_shift, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const shift      = (uOpcode >> 22) & 0x00000003;
    LogFlow(("%018x/%010x: SUB_64_addsub_shift Rd=%#x Rn=%#x imm6=%#x Rm=%#x shift=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm, shift));
#ifdef IEM_INSTR_IMPL_A64__SUB_64_addsub_shift
    IEM_INSTR_IMPL_A64__SUB_64_addsub_shift(Rd, Rn, imm6, Rm, shift);
#else
    RT_NOREF(Rd, Rn, imm6, Rm, shift, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf20fc00/2e208400: SUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SUB_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e208400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: SUB_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SUB_asimdsame_only
            IEM_INSTR_IMPL_A64__SUB_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ee08400: SUB  D<d>, D<n>, D<m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SUB_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SUB_asisdsame_only Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__SUB_asisdsame_only
        IEM_INSTR_IMPL_A64__SUB_asisdsame_only(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/0f00f000: SUDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SUDOT_asimdelem_D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x0f00f000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const US         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fI8mm /*FEAT_I8MM*/)
        {
            LogFlow(("%018x/%010x: SUDOT_asimdelem_D Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u US=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, US, Q));
#ifdef IEM_INSTR_IMPL_A64__SUDOT_asimdelem_D
            IEM_INSTR_IMPL_A64__SUDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, US, Q);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, US, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e203800: SUQADD  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SUQADD_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SUQADD_asimdmisc_R Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__SUQADD_asimdmisc_R
        IEM_INSTR_IMPL_A64__SUQADD_asimdmisc_R(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/5e203800: SUQADD  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_SUQADD_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: SUQADD_asisdmisc_R Rd=%#x Rn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size));
#ifdef IEM_INSTR_IMPL_A64__SUQADD_asisdmisc_R
        IEM_INSTR_IMPL_A64__SUQADD_asisdmisc_R(Rd, Rn, size);
#else
        RT_NOREF(Rd, Rn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001f/d4000001: SVC  #<imm>
   Instruction Set: A64  Groups: exception, control */
FNIEMOP_DEF_1(iemDecodeA64_SVC_EX_exception, uint32_t, uOpcode)
{
    uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
    LogFlow(("%018x/%010x: SVC_EX_exception imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__SVC_EX_exception
    IEM_INSTR_IMPL_A64__SVC_EX_exception(imm16);
#else
    RT_NOREF(imm16, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/38a08000: SWPAB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPAB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: SWPAB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPAB_32_memop
        IEM_INSTR_IMPL_A64__SWPAB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78a08000: SWPAH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPAH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78a08000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: SWPAH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPAH_32_memop
            IEM_INSTR_IMPL_A64__SWPAH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38e08000: SWPALB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPALB_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: SWPALB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPALB_32_memop
        IEM_INSTR_IMPL_A64__SWPALB_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78e08000: SWPALH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPALH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78e08000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: SWPALH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPALH_32_memop
            IEM_INSTR_IMPL_A64__SWPALH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8e08000: SWPAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPAL_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: SWPAL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPAL_32_memop
        IEM_INSTR_IMPL_A64__SWPAL_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8e08000: SWPAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPAL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8e08000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: SWPAL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPAL_64_memop
            IEM_INSTR_IMPL_A64__SWPAL_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8a08000: SWPA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPA_32_memop, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
    {
        LogFlow(("%018x/%010x: SWPA_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPA_32_memop
        IEM_INSTR_IMPL_A64__SWPA_32_memop(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8a08000: SWPA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPA_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8a08000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: SWPA_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPA_64_memop
            IEM_INSTR_IMPL_A64__SWPA_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38208000: SWPB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38208000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: SWPB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPB_32_memop
            IEM_INSTR_IMPL_A64__SWPB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78208000: SWPH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78208000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: SWPH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPH_32_memop
            IEM_INSTR_IMPL_A64__SWPH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/38608000: SWPLB  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPLB_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38608000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: SWPLB_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPLB_32_memop
            IEM_INSTR_IMPL_A64__SWPLB_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/78608000: SWPLH  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPLH_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78608000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: SWPLH_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPLH_32_memop
            IEM_INSTR_IMPL_A64__SWPLH_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8608000: SWPL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPL_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8608000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: SWPL_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPL_32_memop
            IEM_INSTR_IMPL_A64__SWPL_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8608000: SWPL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPL_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8608000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: SWPL_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPL_64_memop
            IEM_INSTR_IMPL_A64__SWPL_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19e08000: SWPPAL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPPAL_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse128 /*FEAT_LSE128*/)
    {
        LogFlow(("%018x/%010x: SWPPAL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__SWPPAL_128_memop_128
        IEM_INSTR_IMPL_A64__SWPPAL_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19a08000: SWPPA  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPPA_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19a08000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse128 /*FEAT_LSE128*/)
        {
            LogFlow(("%018x/%010x: SWPPA_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__SWPPA_128_memop_128
            IEM_INSTR_IMPL_A64__SWPPA_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19608000: SWPPL  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPPL_128_memop_128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19608000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse128 /*FEAT_LSE128*/)
        {
            LogFlow(("%018x/%010x: SWPPL_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__SWPPL_128_memop_128
            IEM_INSTR_IMPL_A64__SWPPL_128_memop_128(Rt, Rn, Rt2);
#else
            RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19208000: SWPP  <Xt1>, <Xt2>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_128, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPP_128_memop_128, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rt2        = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse128 /*FEAT_LSE128*/)
    {
        LogFlow(("%018x/%010x: SWPP_128_memop_128 Rt=%#x Rn=%#x Rt2=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rt2));
#ifdef IEM_INSTR_IMPL_A64__SWPP_128_memop_128
        IEM_INSTR_IMPL_A64__SWPP_128_memop_128(Rt, Rn, Rt2);
#else
        RT_NOREF(Rt, Rn, Rt2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19e08400: SWPTAL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPTAL_32_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: SWPTAL_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPTAL_32_memop_unpriv
        IEM_INSTR_IMPL_A64__SWPTAL_32_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59e08400: SWPTAL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPTAL_64_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: SWPTAL_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPTAL_64_memop_unpriv
        IEM_INSTR_IMPL_A64__SWPTAL_64_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19a08400: SWPTA  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPTA_32_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: SWPTA_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPTA_32_memop_unpriv
        IEM_INSTR_IMPL_A64__SWPTA_32_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59a08400: SWPTA  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPTA_64_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: SWPTA_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPTA_64_memop_unpriv
        IEM_INSTR_IMPL_A64__SWPTA_64_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19608400: SWPTL  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPTL_32_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: SWPTL_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPTL_32_memop_unpriv
        IEM_INSTR_IMPL_A64__SWPTL_32_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59608400: SWPTL  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPTL_64_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: SWPTL_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPTL_64_memop_unpriv
        IEM_INSTR_IMPL_A64__SWPTL_64_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/19208400: SWPT  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPT_32_memop_unpriv, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
    {
        LogFlow(("%018x/%010x: SWPT_32_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPT_32_memop_unpriv
        IEM_INSTR_IMPL_A64__SWPT_32_memop_unpriv(Rt, Rn, Rs);
#else
        RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/59208400: SWPT  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop_unpriv, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWPT_64_memop_unpriv, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59208400))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LSUI*/)
        {
            LogFlow(("%018x/%010x: SWPT_64_memop_unpriv Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWPT_64_memop_unpriv
            IEM_INSTR_IMPL_A64__SWPT_64_memop_unpriv(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/b8208000: SWP  <Ws>, <Wt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWP_32_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8208000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: SWP_32_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWP_32_memop
            IEM_INSTR_IMPL_A64__SWP_32_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/f8208000: SWP  <Xs>, <Xt>, [<Xn|SP>]
   Instruction Set: A64  Groups: memop, ldst */
FNIEMOP_DEF_1(iemDecodeA64_SWP_64_memop, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8208000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rs         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLse /*FEAT_LSE*/)
        {
            LogFlow(("%018x/%010x: SWP_64_memop Rt=%#x Rn=%#x Rs=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, Rn, Rs));
#ifdef IEM_INSTR_IMPL_A64__SWP_64_memop
            IEM_INSTR_IMPL_A64__SWP_64_memop(Rt, Rn, Rs);
#else
            RT_NOREF(Rt, Rn, Rs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff80000/d5280000: SYSL  <Xt>, #<op1>, <Cn>, <Cm>, #<op2>
   Instruction Set: A64  Groups: systeminstrs, control */
FNIEMOP_DEF_1(iemDecodeA64_SYSL_RC_systeminstrs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff80000)) == UINT32_C(0xd5280000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const op2        = (uOpcode >>  5) & 0x00000007;
        uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
        uint32_t const CRn        = (uOpcode >> 12) & 0x0000000f;
        uint32_t const op1        = (uOpcode >> 16) & 0x00000007;
        LogFlow(("%018x/%010x: SYSL_RC_systeminstrs Rt=%#x op2=%u CRm=%#x CRn=%#x op1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, op2, CRm, CRn, op1));
#ifdef IEM_INSTR_IMPL_A64__SYSL_RC_systeminstrs
        IEM_INSTR_IMPL_A64__SYSL_RC_systeminstrs(Rt, op2, CRm, CRn, op1);
#else
        RT_NOREF(Rt, op2, CRm, CRn, op1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff80000/d5480000: SYSP  #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>}
   Instruction Set: A64  Groups: syspairinstrs, control */
FNIEMOP_DEF_1(iemDecodeA64_SYSP_CR_syspairinstrs, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const op2        = (uOpcode >>  5) & 0x00000007;
    uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
    uint32_t const CRn        = (uOpcode >> 12) & 0x0000000f;
    uint32_t const op1        = (uOpcode >> 16) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSysInstr128 /*FEAT_SYSINSTR128*/)
    {
        LogFlow(("%018x/%010x: SYSP_CR_syspairinstrs Rt=%#x op2=%u CRm=%#x CRn=%#x op1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, op2, CRm, CRn, op1));
#ifdef IEM_INSTR_IMPL_A64__SYSP_CR_syspairinstrs
        IEM_INSTR_IMPL_A64__SYSP_CR_syspairinstrs(Rt, op2, CRm, CRn, op1);
#else
        RT_NOREF(Rt, op2, CRm, CRn, op1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff80000/d5080000: SYS  #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}
   Instruction Set: A64  Groups: systeminstrs, control */
FNIEMOP_DEF_1(iemDecodeA64_SYS_CR_systeminstrs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff80000)) == UINT32_C(0xd5080000))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const op2        = (uOpcode >>  5) & 0x00000007;
        uint32_t const CRm        = (uOpcode >>  8) & 0x0000000f;
        uint32_t const CRn        = (uOpcode >> 12) & 0x0000000f;
        uint32_t const op1        = (uOpcode >> 16) & 0x00000007;
        LogFlow(("%018x/%010x: SYS_CR_systeminstrs Rt=%#x op2=%u CRm=%#x CRn=%#x op1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, op2, CRm, CRn, op1));
#ifdef IEM_INSTR_IMPL_A64__SYS_CR_systeminstrs
        IEM_INSTR_IMPL_A64__SYS_CR_systeminstrs(Rt, op2, CRm, CRn, op1);
#else
        RT_NOREF(Rt, op2, CRm, CRn, op1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e000000: TBL  <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>
   Instruction Set: A64  Groups: asimdtbl, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_TBL_asimdtbl_L1_1, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: TBL_asimdtbl_L1_1 Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__TBL_asimdtbl_L1_1
        IEM_INSTR_IMPL_A64__TBL_asimdtbl_L1_1(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e002000: TBL  <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>
   Instruction Set: A64  Groups: asimdtbl, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_TBL_asimdtbl_L2_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e002000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: TBL_asimdtbl_L2_2 Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__TBL_asimdtbl_L2_2
            IEM_INSTR_IMPL_A64__TBL_asimdtbl_L2_2(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e004000: TBL  <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>
   Instruction Set: A64  Groups: asimdtbl, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_TBL_asimdtbl_L3_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e004000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: TBL_asimdtbl_L3_3 Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__TBL_asimdtbl_L3_3
            IEM_INSTR_IMPL_A64__TBL_asimdtbl_L3_3(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e006000: TBL  <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>
   Instruction Set: A64  Groups: asimdtbl, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_TBL_asimdtbl_L4_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e006000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: TBL_asimdtbl_L4_4 Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__TBL_asimdtbl_L4_4
            IEM_INSTR_IMPL_A64__TBL_asimdtbl_L4_4(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 7f000000/37000000: TBNZ  <R><t>, #<imm>, <label>
   Instruction Set: A64  Groups: testbranch, control */
FNIEMOP_DEF_1(iemDecodeA64_TBNZ_only_testbranch, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm14      = (uOpcode >>  5) & 0x00003fff;
    uint32_t const b40        = (uOpcode >> 19) & 0x0000001f;
    uint32_t const b5         = (uOpcode >> 31) & 0x00000001;
    LogFlow(("%018x/%010x: TBNZ_only_testbranch Rt=%#x imm14=%#x b40=%#x b5=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm14, b40, b5));
#ifdef IEM_INSTR_IMPL_A64__TBNZ_only_testbranch
    IEM_INSTR_IMPL_A64__TBNZ_only_testbranch(Rt, imm14, b40, b5);
#else
    RT_NOREF(Rt, imm14, b40, b5, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bfe0fc00/0e001000: TBX  <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>
   Instruction Set: A64  Groups: asimdtbl, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_TBX_asimdtbl_L1_1, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: TBX_asimdtbl_L1_1 Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__TBX_asimdtbl_L1_1
        IEM_INSTR_IMPL_A64__TBX_asimdtbl_L1_1(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e003000: TBX  <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>
   Instruction Set: A64  Groups: asimdtbl, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_TBX_asimdtbl_L2_2, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: TBX_asimdtbl_L2_2 Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__TBX_asimdtbl_L2_2
        IEM_INSTR_IMPL_A64__TBX_asimdtbl_L2_2(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e005000: TBX  <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>
   Instruction Set: A64  Groups: asimdtbl, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_TBX_asimdtbl_L3_3, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: TBX_asimdtbl_L3_3 Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__TBX_asimdtbl_L3_3
        IEM_INSTR_IMPL_A64__TBX_asimdtbl_L3_3(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e007000: TBX  <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>
   Instruction Set: A64  Groups: asimdtbl, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_TBX_asimdtbl_L4_4, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: TBX_asimdtbl_L4_4 Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__TBX_asimdtbl_L4_4
        IEM_INSTR_IMPL_A64__TBX_asimdtbl_L4_4(Rd, Rn, Rm, Q);
#else
        RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* 7f000000/36000000: TBZ  <R><t>, #<imm>, <label>
   Instruction Set: A64  Groups: testbranch, control */
FNIEMOP_DEF_1(iemDecodeA64_TBZ_only_testbranch, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm14      = (uOpcode >>  5) & 0x00003fff;
    uint32_t const b40        = (uOpcode >> 19) & 0x0000001f;
    uint32_t const b5         = (uOpcode >> 31) & 0x00000001;
    LogFlow(("%018x/%010x: TBZ_only_testbranch Rt=%#x imm14=%#x b40=%#x b5=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, imm14, b40, b5));
#ifdef IEM_INSTR_IMPL_A64__TBZ_only_testbranch
    IEM_INSTR_IMPL_A64__TBZ_only_testbranch(Rt, imm14, b40, b5);
#else
    RT_NOREF(Rt, imm14, b40, b5, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0001f/d4600000: TCANCEL  #<imm>
   Instruction Set: A64  Groups: exception, control */
FNIEMOP_DEF_1(iemDecodeA64_TCANCEL_EX_exception, uint32_t, uOpcode)
{
    uint32_t const imm16      = (uOpcode >>  5) & 0x0000ffff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fTme /*FEAT_TME*/)
    {
        LogFlow(("%018x/%010x: TCANCEL_EX_exception imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__TCANCEL_EX_exception
        IEM_INSTR_IMPL_A64__TCANCEL_EX_exception(imm16);
#else
        RT_NOREF(imm16, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503307f: TCOMMIT
   Instruction Set: A64  Groups: barriers, control */
FNIEMOP_DEF_1(iemDecodeA64_TCOMMIT_only_barriers, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503307f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fTme /*FEAT_TME*/)
        {
            LogFlow(("%018x/%010x: TCOMMIT_only_barriers\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__TCOMMIT_only_barriers
            IEM_INSTR_IMPL_A64__TCOMMIT_only_barriers();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e002800: TRN1  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdperm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_TRN1_asimdperm_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e002800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: TRN1_asimdperm_only Rd=%#x Rn=%#x op=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__TRN1_asimdperm_only
            IEM_INSTR_IMPL_A64__TRN1_asimdperm_only(Rd, Rn, op, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, op, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e006800: TRN2  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdperm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_TRN2_asimdperm_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e006800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: TRN2_asimdperm_only Rd=%#x Rn=%#x op=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__TRN2_asimdperm_only
            IEM_INSTR_IMPL_A64__TRN2_asimdperm_only(Rd, Rn, op, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, op, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503225f: TSB  CSYNC
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_TSB_HC_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503225f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fTrf /*FEAT_TRF*/)
        {
            LogFlow(("%018x/%010x: TSB_HC_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__TSB_HC_hints
            IEM_INSTR_IMPL_A64__TSB_HC_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/d5233060: TSTART  <Xt>
   Instruction Set: A64  Groups: systemresult, control */
FNIEMOP_DEF_1(iemDecodeA64_TSTART_BR_systemresult, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fTme /*FEAT_TME*/)
    {
        LogFlow(("%018x/%010x: TSTART_BR_systemresult Rt=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt));
#ifdef IEM_INSTR_IMPL_A64__TSTART_BR_systemresult
        IEM_INSTR_IMPL_A64__TSTART_BR_systemresult(Rt);
#else
        RT_NOREF(Rt, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/d5233160: TTEST  <Xt>
   Instruction Set: A64  Groups: systemresult, control */
FNIEMOP_DEF_1(iemDecodeA64_TTEST_BR_systemresult, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fTme /*FEAT_TME*/)
    {
        LogFlow(("%018x/%010x: TTEST_BR_systemresult Rt=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt));
#ifdef IEM_INSTR_IMPL_A64__TTEST_BR_systemresult
        IEM_INSTR_IMPL_A64__TTEST_BR_systemresult(Rt);
#else
        RT_NOREF(Rt, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e205000: UABAL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UABAL_asimddiff_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e205000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UABAL_asimddiff_L Rd=%#x Rn=%#x op=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UABAL_asimddiff_L
            IEM_INSTR_IMPL_A64__UABAL_asimddiff_L(Rd, Rn, op, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, op, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e207c00: UABA  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UABA_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e207c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UABA_asimdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UABA_asimdsame_only
            IEM_INSTR_IMPL_A64__UABA_asimdsame_only(Rd, Rn, ac, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, ac, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e207000: UABDL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UABDL_asimddiff_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e207000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UABDL_asimddiff_L Rd=%#x Rn=%#x op=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UABDL_asimddiff_L
            IEM_INSTR_IMPL_A64__UABDL_asimddiff_L(Rd, Rn, op, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, op, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e207400: UABD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UABD_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const ac         = (uOpcode >> 11) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UABD_asimdsame_only Rd=%#x Rn=%#x ac=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, ac, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UABD_asimdsame_only
        IEM_INSTR_IMPL_A64__UABD_asimdsame_only(Rd, Rn, ac, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, ac, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e206800: UADALP  <Vd>.<Ta>, <Vn>.<Tb>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UADALP_asimdmisc_P, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 14) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UADALP_asimdmisc_P Rd=%#x Rn=%#x op=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UADALP_asimdmisc_P
        IEM_INSTR_IMPL_A64__UADALP_asimdmisc_P(Rd, Rn, op, size, Q);
#else
        RT_NOREF(Rd, Rn, op, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e202800: UADDLP  <Vd>.<Ta>, <Vn>.<Tb>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UADDLP_asimdmisc_P, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 14) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UADDLP_asimdmisc_P Rd=%#x Rn=%#x op=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UADDLP_asimdmisc_P
        IEM_INSTR_IMPL_A64__UADDLP_asimdmisc_P(Rd, Rn, op, size, Q);
#else
        RT_NOREF(Rd, Rn, op, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e303800: UADDLV  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UADDLV_asimdall_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UADDLV_asimdall_only Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UADDLV_asimdall_only
        IEM_INSTR_IMPL_A64__UADDLV_asimdall_only(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e200000: UADDL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UADDL_asimddiff_L, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UADDL_asimddiff_L Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UADDL_asimddiff_L
        IEM_INSTR_IMPL_A64__UADDL_asimddiff_L(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e201000: UADDW2  <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UADDW_asimddiff_W, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UADDW_asimddiff_W Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UADDW_asimddiff_W
        IEM_INSTR_IMPL_A64__UADDW_asimddiff_W(Rd, Rn, o1, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc00000/53000000: UBFM  <Wd>, <Wn>, #<immr>, #<imms>
   Instruction Set: A64  Groups: bitfield, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_UBFM_32M_bitfield, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
    uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
    LogFlow(("%018x/%010x: UBFM_32M_bitfield Rd=%#x Rn=%#x imms=%#x immr=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr));
#ifdef IEM_INSTR_IMPL_A64__UBFM_32M_bitfield
    IEM_INSTR_IMPL_A64__UBFM_32M_bitfield(Rd, Rn, imms, immr);
#else
    RT_NOREF(Rd, Rn, imms, immr, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffc00000/d3400000: UBFM  <Xd>, <Xn>, #<immr>, #<imms>
   Instruction Set: A64  Groups: bitfield, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_UBFM_64M_bitfield, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xd3400000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imms       = (uOpcode >> 10) & 0x0000003f;
        uint32_t const immr       = (uOpcode >> 16) & 0x0000003f;
        LogFlow(("%018x/%010x: UBFM_64M_bitfield Rd=%#x Rn=%#x imms=%#x immr=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imms, immr));
#ifdef IEM_INSTR_IMPL_A64__UBFM_64M_bitfield
        IEM_INSTR_IMPL_A64__UBFM_64M_bitfield(Rd, Rn, imms, immr);
#else
        RT_NOREF(Rd, Rn, imms, immr, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/1e430000: UCVTF  <Dd>, <Wn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_D32_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x1e430000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: UCVTF_D32_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_D32_float2fix
            IEM_INSTR_IMPL_A64__UCVTF_D32_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e630000: UCVTF  <Dd>, <Wn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_D32_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e630000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: UCVTF_D32_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_D32_float2int
            IEM_INSTR_IMPL_A64__UCVTF_D32_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/9e430000: UCVTF  <Dd>, <Xn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_D64_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x9e430000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: UCVTF_D64_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_D64_float2fix
            IEM_INSTR_IMPL_A64__UCVTF_D64_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e630000: UCVTF  <Dd>, <Xn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_D64_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e630000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: UCVTF_D64_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_D64_float2int
            IEM_INSTR_IMPL_A64__UCVTF_D64_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/1ec30000: UCVTF  <Hd>, <Wn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_H32_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x1ec30000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: UCVTF_H32_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_H32_float2fix
            IEM_INSTR_IMPL_A64__UCVTF_H32_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1ee30000: UCVTF  <Hd>, <Wn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_H32_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee30000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: UCVTF_H32_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_H32_float2int
            IEM_INSTR_IMPL_A64__UCVTF_H32_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/9ec30000: UCVTF  <Hd>, <Xn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_H64_float2fix, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x9ec30000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: UCVTF_H64_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_H64_float2fix
            IEM_INSTR_IMPL_A64__UCVTF_H64_float2fix(Rd, Rn, scale);
#else
            RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9ee30000: UCVTF  <Hd>, <Xn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_H64_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9ee30000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: UCVTF_H64_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_H64_float2int
            IEM_INSTR_IMPL_A64__UCVTF_H64_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/1e030000: UCVTF  <Sd>, <Wn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_S32_float2fix, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: UCVTF_S32_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_S32_float2fix
        IEM_INSTR_IMPL_A64__UCVTF_S32_float2fix(Rd, Rn, scale);
#else
        RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e230000: UCVTF  <Sd>, <Wn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_S32_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e230000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: UCVTF_S32_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_S32_float2int
            IEM_INSTR_IMPL_A64__UCVTF_S32_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/9e030000: UCVTF  <Sd>, <Xn>, #<fbits>
   Instruction Set: A64  Groups: float2fix, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_S64_float2fix, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const scale      = (uOpcode >> 10) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
    {
        LogFlow(("%018x/%010x: UCVTF_S64_float2fix Rd=%#x Rn=%#x scale=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, scale));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_S64_float2fix
        IEM_INSTR_IMPL_A64__UCVTF_S64_float2fix(Rd, Rn, scale);
#else
        RT_NOREF(Rd, Rn, scale, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e230000: UCVTF  <Sd>, <Xn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_S64_float2int, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e230000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp /*FEAT_FP*/)
        {
            LogFlow(("%018x/%010x: UCVTF_S64_float2int Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_S64_float2int
            IEM_INSTR_IMPL_A64__UCVTF_S64_float2int(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2e21d800: UCVTF  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_asimdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2e21d800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UCVTF_asimdmisc_R Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_asimdmisc_R
            IEM_INSTR_IMPL_A64__UCVTF_asimdmisc_R(Rd, Rn, sz, Q);
#else
            RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bffffc00/2e79d800: UCVTF  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_asimdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2e79d800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: UCVTF_asimdmiscfp16_R Rd=%#x Rn=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Q));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_asimdmiscfp16_R
            IEM_INSTR_IMPL_A64__UCVTF_asimdmiscfp16_R(Rd, Rn, Q);
#else
            RT_NOREF(Rd, Rn, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f00e400: UCVTF  <Vd>.<T>, <Vn>.<T>, #<fbits>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_asimdshf_C, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: UCVTF_asimdshf_C Rd=%#x Rn=%#x immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_asimdshf_C
        IEM_INSTR_IMPL_A64__UCVTF_asimdshf_C(Rd, Rn, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbffc00/7e21d800: UCVTF  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_asisdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UCVTF_asisdmisc_R Rd=%#x Rn=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_asisdmisc_R
        IEM_INSTR_IMPL_A64__UCVTF_asisdmisc_R(Rd, Rn, sz);
#else
        RT_NOREF(Rd, Rn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/7e79d800: UCVTF  <Hd>, <Hn>
   Instruction Set: A64  Groups: asisdmiscfp16, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_asisdmiscfp16_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7e79d800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFp16 /*FEAT_FP16*/)
        {
            LogFlow(("%018x/%010x: UCVTF_asisdmiscfp16_R Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_asisdmiscfp16_R
            IEM_INSTR_IMPL_A64__UCVTF_asisdmiscfp16_R(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f00e400: UCVTF  <V><d>, <V><n>, #<fbits>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_asisdshf_C, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
    {
        LogFlow(("%018x/%010x: UCVTF_asisdshf_C Rd=%#x Rn=%#x immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_asisdshf_C
        IEM_INSTR_IMPL_A64__UCVTF_asisdshf_C(Rd, Rn, immb, immh);
#else
        RT_NOREF(Rd, Rn, immb, immh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1e7d0000: UCVTF  <Dd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_sisd_32D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e7d0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: UCVTF_sisd_32D Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_sisd_32D
            IEM_INSTR_IMPL_A64__UCVTF_sisd_32D(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/1efd0000: UCVTF  <Hd>, <Sn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_sisd_32H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1efd0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: UCVTF_sisd_32H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_sisd_32H
            IEM_INSTR_IMPL_A64__UCVTF_sisd_32H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9efd0000: UCVTF  <Hd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_sisd_64H, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9efd0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: UCVTF_sisd_64H Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_sisd_64H
            IEM_INSTR_IMPL_A64__UCVTF_sisd_64H(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/9e3d0000: UCVTF  <Sd>, <Dn>
   Instruction Set: A64  Groups: float2int, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UCVTF_sisd_64S, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9e3d0000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FPRCVT*/)
        {
            LogFlow(("%018x/%010x: UCVTF_sisd_64S Rd=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn));
#ifdef IEM_INSTR_IMPL_A64__UCVTF_sisd_64S
            IEM_INSTR_IMPL_A64__UCVTF_sisd_64S(Rd, Rn);
#else
            RT_NOREF(Rd, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0000/00000000: UDF  #<imm>
   Instruction Set: A64  Groups: perm_undef, reserved */
FNIEMOP_DEF_1(iemDecodeA64_UDF_only_perm_undef, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x00000000))
    {
        uint32_t const imm16      = (uOpcode >>  0) & 0x0000ffff;
        LogFlow(("%018x/%010x: UDF_only_perm_undef imm16=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm16));
#ifdef IEM_INSTR_IMPL_A64__UDF_only_perm_undef
        IEM_INSTR_IMPL_A64__UDF_only_perm_undef(imm16);
#else
        RT_NOREF(imm16, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac00800: UDIV  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_UDIV_32_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: UDIV_32_dp_2src Rd=%#x Rn=%#x o1=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm));
#ifdef IEM_INSTR_IMPL_A64__UDIV_32_dp_2src
    IEM_INSTR_IMPL_A64__UDIV_32_dp_2src(Rd, Rn, o1, Rm);
#else
    RT_NOREF(Rd, Rn, o1, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* ffe0fc00/9ac00800: UDIV  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_UDIV_64_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o1         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    LogFlow(("%018x/%010x: UDIV_64_dp_2src Rd=%#x Rn=%#x o1=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm));
#ifdef IEM_INSTR_IMPL_A64__UDIV_64_dp_2src
    IEM_INSTR_IMPL_A64__UDIV_64_dp_2src(Rd, Rn, o1, Rm);
#else
    RT_NOREF(Rd, Rn, o1, Rm, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf00f400/2f00e000: UDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UDOT_asimdelem_D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x2f00e000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fDotProd /*FEAT_DotProd*/)
        {
            LogFlow(("%018x/%010x: UDOT_asimdelem_D Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UDOT_asimdelem_D
            IEM_INSTR_IMPL_A64__UDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, size, Q);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e009400: UDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UDOT_asimdsame2_D, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fDotProd /*FEAT_DotProd*/)
    {
        LogFlow(("%018x/%010x: UDOT_asimdsame2_D Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UDOT_asimdsame2_D
        IEM_INSTR_IMPL_A64__UDOT_asimdsame2_D(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e200400: UHADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UHADD_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UHADD_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UHADD_asimdsame_only
        IEM_INSTR_IMPL_A64__UHADD_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e202400: UHSUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UHSUB_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e202400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UHSUB_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UHSUB_asimdsame_only
            IEM_INSTR_IMPL_A64__UHSUB_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/9ba00000: UMADDL  <Xd>, <Wn>, <Wm>, <Xa>
   Instruction Set: A64  Groups: dp_3src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_UMADDL_64WA_dp_3src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x9ba00000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 23) & 0x00000001;
        LogFlow(("%018x/%010x: UMADDL_64WA_dp_3src Rd=%#x Rn=%#x Ra=%#x Rm=%#x U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm, U));
#ifdef IEM_INSTR_IMPL_A64__UMADDL_64WA_dp_3src
        IEM_INSTR_IMPL_A64__UMADDL_64WA_dp_3src(Rd, Rn, Ra, Rm, U);
#else
        RT_NOREF(Rd, Rn, Ra, Rm, U, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e20a400: UMAXP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMAXP_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e20a400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UMAXP_asimdsame_only Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UMAXP_asimdsame_only
            IEM_INSTR_IMPL_A64__UMAXP_asimdsame_only(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e30a800: UMAXV  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMAXV_asimdall_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UMAXV_asimdall_only Rd=%#x Rn=%#x op=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UMAXV_asimdall_only
        IEM_INSTR_IMPL_A64__UMAXV_asimdall_only(Rd, Rn, op, size, Q);
#else
        RT_NOREF(Rd, Rn, op, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0000/11c40000: UMAX  <Wd>, <Wn>, #<uimm>
   Instruction Set: A64  Groups: minmax_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_UMAX_32U_minmax_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm8       = (uOpcode >> 10) & 0x000000ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: UMAX_32U_minmax_imm Rd=%#x Rn=%#x imm8=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm8));
#ifdef IEM_INSTR_IMPL_A64__UMAX_32U_minmax_imm
        IEM_INSTR_IMPL_A64__UMAX_32U_minmax_imm(Rd, Rn, imm8);
#else
        RT_NOREF(Rd, Rn, imm8, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac06400: UMAX  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_UMAX_32_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: UMAX_32_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__UMAX_32_dp_2src
        IEM_INSTR_IMPL_A64__UMAX_32_dp_2src(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0000/91c40000: UMAX  <Xd>, <Xn>, #<uimm>
   Instruction Set: A64  Groups: minmax_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_UMAX_64U_minmax_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm8       = (uOpcode >> 10) & 0x000000ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: UMAX_64U_minmax_imm Rd=%#x Rn=%#x imm8=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm8));
#ifdef IEM_INSTR_IMPL_A64__UMAX_64U_minmax_imm
        IEM_INSTR_IMPL_A64__UMAX_64U_minmax_imm(Rd, Rn, imm8);
#else
        RT_NOREF(Rd, Rn, imm8, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9ac06400: UMAX  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_UMAX_64_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: UMAX_64_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__UMAX_64_dp_2src
        IEM_INSTR_IMPL_A64__UMAX_64_dp_2src(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e206400: UMAX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMAX_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e206400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UMAX_asimdsame_only Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UMAX_asimdsame_only
            IEM_INSTR_IMPL_A64__UMAX_asimdsame_only(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e20ac00: UMINP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMINP_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e20ac00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UMINP_asimdsame_only Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UMINP_asimdsame_only
            IEM_INSTR_IMPL_A64__UMINP_asimdsame_only(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e31a800: UMINV  <V><d>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdall, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMINV_asimdall_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UMINV_asimdall_only Rd=%#x Rn=%#x op=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UMINV_asimdall_only
        IEM_INSTR_IMPL_A64__UMINV_asimdall_only(Rd, Rn, op, size, Q);
#else
        RT_NOREF(Rd, Rn, op, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0000/11cc0000: UMIN  <Wd>, <Wn>, #<uimm>
   Instruction Set: A64  Groups: minmax_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_UMIN_32U_minmax_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm8       = (uOpcode >> 10) & 0x000000ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: UMIN_32U_minmax_imm Rd=%#x Rn=%#x imm8=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm8));
#ifdef IEM_INSTR_IMPL_A64__UMIN_32U_minmax_imm
        IEM_INSTR_IMPL_A64__UMIN_32U_minmax_imm(Rd, Rn, imm8);
#else
        RT_NOREF(Rd, Rn, imm8, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/1ac06c00: UMIN  <Wd>, <Wn>, <Wm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_UMIN_32_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: UMIN_32_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__UMIN_32_dp_2src
        IEM_INSTR_IMPL_A64__UMIN_32_dp_2src(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0000/91cc0000: UMIN  <Xd>, <Xn>, #<uimm>
   Instruction Set: A64  Groups: minmax_imm, dpimm */
FNIEMOP_DEF_1(iemDecodeA64_UMIN_64U_minmax_imm, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm8       = (uOpcode >> 10) & 0x000000ff;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: UMIN_64U_minmax_imm Rd=%#x Rn=%#x imm8=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm8));
#ifdef IEM_INSTR_IMPL_A64__UMIN_64U_minmax_imm
        IEM_INSTR_IMPL_A64__UMIN_64U_minmax_imm(Rd, Rn, imm8);
#else
        RT_NOREF(Rd, Rn, imm8, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9ac06c00: UMIN  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: dp_2src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_UMIN_64_dp_2src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCssc /*FEAT_CSSC*/)
    {
        LogFlow(("%018x/%010x: UMIN_64_dp_2src Rd=%#x Rn=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm));
#ifdef IEM_INSTR_IMPL_A64__UMIN_64_dp_2src
        IEM_INSTR_IMPL_A64__UMIN_64_dp_2src(Rd, Rn, Rm);
#else
        RT_NOREF(Rd, Rn, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e206c00: UMIN  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMIN_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e206c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UMIN_asimdsame_only Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UMIN_asimdsame_only
            IEM_INSTR_IMPL_A64__UMIN_asimdsame_only(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e208000: UMLAL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMLAL_asimddiff_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e208000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UMLAL_asimddiff_L Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UMLAL_asimddiff_L
            IEM_INSTR_IMPL_A64__UMLAL_asimddiff_L(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/2f002000: UMLAL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMLAL_asimdelem_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x2f002000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UMLAL_asimdelem_L Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UMLAL_asimdelem_L
            IEM_INSTR_IMPL_A64__UMLAL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q);
#else
            RT_NOREF(Rd, Rn, H, o2, Rm, M, L, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e20a000: UMLSL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMLSL_asimddiff_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e20a000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UMLSL_asimddiff_L Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UMLSL_asimddiff_L
            IEM_INSTR_IMPL_A64__UMLSL_asimddiff_L(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/2f006000: UMLSL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMLSL_asimdelem_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x2f006000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const o2         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UMLSL_asimdelem_L Rd=%#x Rn=%#x H=%u o2=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, o2, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UMLSL_asimdelem_L
            IEM_INSTR_IMPL_A64__UMLSL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q);
#else
            RT_NOREF(Rd, Rn, H, o2, Rm, M, L, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/6e80a400: UMMLA  <Vd>.4S, <Vn>.16B, <Vm>.16B
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMMLA_asimdsame2_G, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x6e80a400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const B          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fI8mm /*FEAT_I8MM*/)
        {
            LogFlow(("%018x/%010x: UMMLA_asimdsame2_G Rd=%#x Rn=%#x B=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, B, Rm));
#ifdef IEM_INSTR_IMPL_A64__UMMLA_asimdsame2_G
            IEM_INSTR_IMPL_A64__UMMLA_asimdsame2_G(Rd, Rn, B, Rm);
#else
            RT_NOREF(Rd, Rn, B, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/0e003c00: UMOV  <Wd>, <Vn>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdins, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMOV_asimdins_W_w, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x0e003c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UMOV_asimdins_W_w Rd=%#x Rn=%#x imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm5));
#ifdef IEM_INSTR_IMPL_A64__UMOV_asimdins_W_w
            IEM_INSTR_IMPL_A64__UMOV_asimdins_W_w(Rd, Rn, imm5);
#else
            RT_NOREF(Rd, Rn, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffeffc00/4e083c00: UMOV  <Xd>, <Vn>.D[<index>]
   Instruction Set: A64  Groups: asimdins, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMOV_asimdins_X_x, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UMOV_asimdins_X_x Rd=%#x Rn=%#x imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm5));
#ifdef IEM_INSTR_IMPL_A64__UMOV_asimdins_X_x
        IEM_INSTR_IMPL_A64__UMOV_asimdins_X_x(Rd, Rn, imm5);
#else
        RT_NOREF(Rd, Rn, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe08000/9ba08000: UMSUBL  <Xd>, <Wn>, <Wm>, <Xa>
   Instruction Set: A64  Groups: dp_3src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_UMSUBL_64WA_dp_3src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x9ba08000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Ra         = (uOpcode >> 10) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 23) & 0x00000001;
        LogFlow(("%018x/%010x: UMSUBL_64WA_dp_3src Rd=%#x Rn=%#x Ra=%#x Rm=%#x U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Ra, Rm, U));
#ifdef IEM_INSTR_IMPL_A64__UMSUBL_64WA_dp_3src
        IEM_INSTR_IMPL_A64__UMSUBL_64WA_dp_3src(Rd, Rn, Ra, Rm, U);
#else
        RT_NOREF(Rd, Rn, Ra, Rm, U, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/9bc07c00: UMULH  <Xd>, <Xn>, <Xm>
   Instruction Set: A64  Groups: dp_3src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_UMULH_64_dp_3src, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 23) & 0x00000001;
    LogFlow(("%018x/%010x: UMULH_64_dp_3src Rd=%#x Rn=%#x Rm=%#x U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, U));
#ifdef IEM_INSTR_IMPL_A64__UMULH_64_dp_3src
    IEM_INSTR_IMPL_A64__UMULH_64_dp_3src(Rd, Rn, Rm, U);
#else
    RT_NOREF(Rd, Rn, Rm, U, pVCpu, uOpcode);
    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
}

/* bf20fc00/2e20c000: UMULL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMULL_asimddiff_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e20c000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UMULL_asimddiff_L Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UMULL_asimddiff_L
            IEM_INSTR_IMPL_A64__UMULL_asimddiff_L(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf00f400/2f00a000: UMULL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UMULL_asimdelem_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x2f00a000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UMULL_asimdelem_L Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UMULL_asimdelem_L
            IEM_INSTR_IMPL_A64__UMULL_asimdelem_L(Rd, Rn, H, Rm, M, L, size, Q);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e200c00: UQADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQADD_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UQADD_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UQADD_asimdsame_only
        IEM_INSTR_IMPL_A64__UQADD_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/7e200c00: UQADD  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQADD_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UQADD_asisdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__UQADD_asisdsame_only
        IEM_INSTR_IMPL_A64__UQADD_asisdsame_only(Rd, Rn, Rm, size);
#else
        RT_NOREF(Rd, Rn, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e205c00: UQRSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQRSHL_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const R          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UQRSHL_asimdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UQRSHL_asimdsame_only
        IEM_INSTR_IMPL_A64__UQRSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, S, R, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/7e205c00: UQRSHL  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQRSHL_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x7e205c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 11) & 0x00000001;
        uint32_t const R          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UQRSHL_asisdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__UQRSHL_asisdsame_only
            IEM_INSTR_IMPL_A64__UQRSHL_asisdsame_only(Rd, Rn, S, R, Rm, size);
#else
            RT_NOREF(Rd, Rn, S, R, Rm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f009c00: UQRSHRN2  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQRSHRN_asimdshf_N, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f009c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 11) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
        {
            LogFlow(("%018x/%010x: UQRSHRN_asimdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__UQRSHRN_asimdshf_N
            IEM_INSTR_IMPL_A64__UQRSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q);
#else
            RT_NOREF(Rd, Rn, op, immb, immh, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f009c00: UQRSHRN  <Vb><d>, <Va><n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQRSHRN_asisdshf_N, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f009c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 11) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
        {
            LogFlow(("%018x/%010x: UQRSHRN_asisdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__UQRSHRN_asisdshf_N
            IEM_INSTR_IMPL_A64__UQRSHRN_asisdshf_N(Rd, Rn, op, immb, immh);
#else
            RT_NOREF(Rd, Rn, op, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e204c00: UQSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQSHL_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const R          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UQSHL_asimdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UQSHL_asimdsame_only
        IEM_INSTR_IMPL_A64__UQSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, S, R, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f007400: UQSHL  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQSHL_asimdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f007400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
        {
            LogFlow(("%018x/%010x: UQSHL_asimdshf_R Rd=%#x Rn=%#x op=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__UQSHL_asimdshf_R
            IEM_INSTR_IMPL_A64__UQSHL_asimdshf_R(Rd, Rn, op, immb, immh, Q);
#else
            RT_NOREF(Rd, Rn, op, immb, immh, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/7e204c00: UQSHL  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQSHL_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x7e204c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 11) & 0x00000001;
        uint32_t const R          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UQSHL_asisdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__UQSHL_asisdsame_only
            IEM_INSTR_IMPL_A64__UQSHL_asisdsame_only(Rd, Rn, S, R, Rm, size);
#else
            RT_NOREF(Rd, Rn, S, R, Rm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f007400: UQSHL  <V><d>, <V><n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQSHL_asisdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f007400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 12) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
        {
            LogFlow(("%018x/%010x: UQSHL_asisdshf_R Rd=%#x Rn=%#x op=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__UQSHL_asisdshf_R
            IEM_INSTR_IMPL_A64__UQSHL_asisdshf_R(Rd, Rn, op, immb, immh);
#else
            RT_NOREF(Rd, Rn, op, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f009400: UQSHRN2  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQSHRN_asimdshf_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 11) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: UQSHRN_asimdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__UQSHRN_asimdshf_N
        IEM_INSTR_IMPL_A64__UQSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, op, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f009400: UQSHRN  <Vb><d>, <Va><n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQSHRN_asisdshf_N, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f009400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 11) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0)
        {
            LogFlow(("%018x/%010x: UQSHRN_asisdshf_N Rd=%#x Rn=%#x op=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__UQSHRN_asisdshf_N
            IEM_INSTR_IMPL_A64__UQSHRN_asisdshf_N(Rd, Rn, op, immb, immh);
#else
            RT_NOREF(Rd, Rn, op, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e202c00: UQSUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQSUB_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e202c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UQSUB_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UQSUB_asimdsame_only
            IEM_INSTR_IMPL_A64__UQSUB_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/7e202c00: UQSUB  <V><d>, <V><n>, <V><m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQSUB_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x7e202c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UQSUB_asisdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__UQSUB_asisdsame_only
            IEM_INSTR_IMPL_A64__UQSUB_asisdsame_only(Rd, Rn, Rm, size);
#else
            RT_NOREF(Rd, Rn, Rm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e214800: UQXTN2  <Vd>.<Tb>, <Vn>.<Ta>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQXTN_asimdmisc_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UQXTN_asimdmisc_N Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UQXTN_asimdmisc_N
        IEM_INSTR_IMPL_A64__UQXTN_asimdmisc_N(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/7e214800: UQXTN  <Vb><d>, <Va><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UQXTN_asisdmisc_N, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x7e214800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UQXTN_asisdmisc_N Rd=%#x Rn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size));
#ifdef IEM_INSTR_IMPL_A64__UQXTN_asisdmisc_N
            IEM_INSTR_IMPL_A64__UQXTN_asisdmisc_N(Rd, Rn, size);
#else
            RT_NOREF(Rd, Rn, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/0ea1c800: URECPE  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_URECPE_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: URECPE_asimdmisc_R Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__URECPE_asimdmisc_R
        IEM_INSTR_IMPL_A64__URECPE_asimdmisc_R(Rd, Rn, sz, Q);
#else
        RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e201400: URHADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_URHADD_asimdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e201400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: URHADD_asimdsame_only Rd=%#x Rn=%#x Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__URHADD_asimdsame_only
            IEM_INSTR_IMPL_A64__URHADD_asimdsame_only(Rd, Rn, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e205400: URSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_URSHL_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const R          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: URSHL_asimdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__URSHL_asimdsame_only
        IEM_INSTR_IMPL_A64__URSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, S, R, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ee05400: URSHL  D<d>, D<n>, D<m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_URSHL_asisdsame_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ee05400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 11) & 0x00000001;
        uint32_t const R          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: URSHL_asisdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm));
#ifdef IEM_INSTR_IMPL_A64__URSHL_asisdsame_only
            IEM_INSTR_IMPL_A64__URSHL_asisdsame_only(Rd, Rn, S, R, Rm);
#else
            RT_NOREF(Rd, Rn, S, R, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f002400: URSHR  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_URSHR_asimdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f002400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
        {
            LogFlow(("%018x/%010x: URSHR_asimdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__URSHR_asimdshf_R
            IEM_INSTR_IMPL_A64__URSHR_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q);
#else
            RT_NOREF(Rd, Rn, o0, o1, immb, immh, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f002400: URSHR  D<d>, D<n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_URSHR_asisdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f002400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && (immh & 8) == 8)
        {
            LogFlow(("%018x/%010x: URSHR_asisdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__URSHR_asisdshf_R
            IEM_INSTR_IMPL_A64__URSHR_asisdshf_R(Rd, Rn, o0, o1, immb, immh);
#else
            RT_NOREF(Rd, Rn, o0, o1, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfbffc00/2ea1c800: URSQRTE  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_URSQRTE_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: URSQRTE_asimdmisc_R Rd=%#x Rn=%#x sz=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, sz, Q));
#ifdef IEM_INSTR_IMPL_A64__URSQRTE_asimdmisc_R
        IEM_INSTR_IMPL_A64__URSQRTE_asimdmisc_R(Rd, Rn, sz, Q);
#else
        RT_NOREF(Rd, Rn, sz, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f003400: URSRA  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_URSRA_asimdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f003400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
        {
            LogFlow(("%018x/%010x: URSRA_asimdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__URSRA_asimdshf_R
            IEM_INSTR_IMPL_A64__URSRA_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q);
#else
            RT_NOREF(Rd, Rn, o0, o1, immb, immh, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f003400: URSRA  D<d>, D<n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_URSRA_asisdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && (immh & 8) == 8)
    {
        LogFlow(("%018x/%010x: URSRA_asisdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__URSRA_asisdshf_R
        IEM_INSTR_IMPL_A64__URSRA_asisdshf_R(Rd, Rn, o0, o1, immb, immh);
#else
        RT_NOREF(Rd, Rn, o0, o1, immb, immh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfc0f400/0f80f000: USDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>]
   Instruction Set: A64  Groups: asimdelem, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USDOT_asimdelem_D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x0f80f000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        uint32_t const L          = (uOpcode >> 21) & 0x00000001;
        uint32_t const US         = (uOpcode >> 23) & 0x00000001;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fI8mm /*FEAT_I8MM*/)
        {
            LogFlow(("%018x/%010x: USDOT_asimdelem_D Rd=%#x Rn=%#x H=%u Rm=%#x M=%u L=%u US=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, H, Rm, M, L, US, Q));
#ifdef IEM_INSTR_IMPL_A64__USDOT_asimdelem_D
            IEM_INSTR_IMPL_A64__USDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, US, Q);
#else
            RT_NOREF(Rd, Rn, H, Rm, M, L, US, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bfe0fc00/0e809c00: USDOT  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USDOT_asimdsame2_D, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e809c00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fI8mm /*FEAT_I8MM*/)
        {
            LogFlow(("%018x/%010x: USDOT_asimdsame2_D Rd=%#x Rn=%#x Rm=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, Rm, Q));
#ifdef IEM_INSTR_IMPL_A64__USDOT_asimdsame2_D
            IEM_INSTR_IMPL_A64__USDOT_asimdsame2_D(Rd, Rn, Rm, Q);
#else
            RT_NOREF(Rd, Rn, Rm, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f00a400: USHLL2  <Vd>.<Ta>, <Vn>.<Tb>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USHLL_asimdshf_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f00a400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
        {
            LogFlow(("%018x/%010x: USHLL_asimdshf_L Rd=%#x Rn=%#x immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__USHLL_asimdshf_L
            IEM_INSTR_IMPL_A64__USHLL_asimdshf_L(Rd, Rn, immb, immh, Q);
#else
            RT_NOREF(Rd, Rn, immb, immh, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e204400: USHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USHL_asimdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const R          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: USHL_asimdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__USHL_asimdsame_only
        IEM_INSTR_IMPL_A64__USHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, S, R, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/7ee04400: USHL  D<d>, D<n>, D<m>
   Instruction Set: A64  Groups: asisdsame, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USHL_asisdsame_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 11) & 0x00000001;
    uint32_t const R          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: USHL_asisdsame_only Rd=%#x Rn=%#x S=%u R=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, S, R, Rm));
#ifdef IEM_INSTR_IMPL_A64__USHL_asisdsame_only
        IEM_INSTR_IMPL_A64__USHL_asisdsame_only(Rd, Rn, S, R, Rm);
#else
        RT_NOREF(Rd, Rn, S, R, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f000400: USHR  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USHR_asimdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: USHR_asimdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__USHR_asimdshf_R
        IEM_INSTR_IMPL_A64__USHR_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, o0, o1, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f000400: USHR  D<d>, D<n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USHR_asisdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f000400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && (immh & 8) == 8)
        {
            LogFlow(("%018x/%010x: USHR_asisdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__USHR_asisdshf_R
            IEM_INSTR_IMPL_A64__USHR_asisdshf_R(Rd, Rn, o0, o1, immb, immh);
#else
            RT_NOREF(Rd, Rn, o0, o1, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4e80ac00: USMMLA  <Vd>.4S, <Vn>.16B, <Vm>.16B
   Instruction Set: A64  Groups: asimdsame2, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USMMLA_asimdsame2_G, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4e80ac00))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const B          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fI8mm /*FEAT_I8MM*/)
        {
            LogFlow(("%018x/%010x: USMMLA_asimdsame2_G Rd=%#x Rn=%#x B=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, B, Rm));
#ifdef IEM_INSTR_IMPL_A64__USMMLA_asimdsame2_G
            IEM_INSTR_IMPL_A64__USMMLA_asimdsame2_G(Rd, Rn, B, Rm);
#else
            RT_NOREF(Rd, Rn, B, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/2e203800: USQADD  <Vd>.<T>, <Vn>.<T>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USQADD_asimdmisc_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: USQADD_asimdmisc_R Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__USQADD_asimdmisc_R
        IEM_INSTR_IMPL_A64__USQADD_asimdmisc_R(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/7e203800: USQADD  <V><d>, <V><n>
   Instruction Set: A64  Groups: asisdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USQADD_asisdmisc_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x7e203800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: USQADD_asisdmisc_R Rd=%#x Rn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size));
#ifdef IEM_INSTR_IMPL_A64__USQADD_asisdmisc_R
            IEM_INSTR_IMPL_A64__USQADD_asisdmisc_R(Rd, Rn, size);
#else
            RT_NOREF(Rd, Rn, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf80fc00/2f001400: USRA  <Vd>.<T>, <Vn>.<T>, #<shift>
   Instruction Set: A64  Groups: asimdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USRA_asimdshf_R, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
    uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
    uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
    uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && immh != 0 && immh != 0)
    {
        LogFlow(("%018x/%010x: USRA_asimdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh, Q));
#ifdef IEM_INSTR_IMPL_A64__USRA_asimdshf_R
        IEM_INSTR_IMPL_A64__USRA_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q);
#else
        RT_NOREF(Rd, Rn, o0, o1, immb, immh, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80fc00/7f001400: USRA  D<d>, D<n>, #<shift>
   Instruction Set: A64  Groups: asisdshf, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USRA_asisdshf_R, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f001400))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o0         = (uOpcode >> 12) & 0x00000001;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const immb       = (uOpcode >> 16) & 0x00000007;
        uint32_t const immh       = (uOpcode >> 19) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/ && (immh & 8) == 8)
        {
            LogFlow(("%018x/%010x: USRA_asisdshf_R Rd=%#x Rn=%#x o0=%u o1=%u immb=%u immh=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o0, o1, immb, immh));
#ifdef IEM_INSTR_IMPL_A64__USRA_asisdshf_R
            IEM_INSTR_IMPL_A64__USRA_asisdshf_R(Rd, Rn, o0, o1, immb, immh);
#else
            RT_NOREF(Rd, Rn, o0, o1, immb, immh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e202000: USUBL2  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USUBL_asimddiff_L, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e202000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: USUBL_asimddiff_L Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__USUBL_asimddiff_L
            IEM_INSTR_IMPL_A64__USUBL_asimddiff_L(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/2e203000: USUBW2  <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>
   Instruction Set: A64  Groups: asimddiff, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_USUBW_asimddiff_W, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e203000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const o1         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: USUBW_asimddiff_W Rd=%#x Rn=%#x o1=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, o1, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__USUBW_asimddiff_W
            IEM_INSTR_IMPL_A64__USUBW_asimddiff_W(Rd, Rn, o1, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, o1, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e001800: UZP1  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdperm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UZP1_asimdperm_only, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: UZP1_asimdperm_only Rd=%#x Rn=%#x op=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UZP1_asimdperm_only
        IEM_INSTR_IMPL_A64__UZP1_asimdperm_only(Rd, Rn, op, Rm, size, Q);
#else
        RT_NOREF(Rd, Rn, op, Rm, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e005800: UZP2  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdperm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_UZP2_asimdperm_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e005800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: UZP2_asimdperm_only Rd=%#x Rn=%#x op=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__UZP2_asimdperm_only
            IEM_INSTR_IMPL_A64__UZP2_asimdperm_only(Rd, Rn, op, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, op, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/d5031000: WFET  <Xt>
   Instruction Set: A64  Groups: systeminstrswithreg, control */
FNIEMOP_DEF_1(iemDecodeA64_WFET_only_systeminstrswithreg, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fWfxt /*FEAT_WFxT*/)
    {
        LogFlow(("%018x/%010x: WFET_only_systeminstrswithreg Rd=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd));
#ifdef IEM_INSTR_IMPL_A64__WFET_only_systeminstrswithreg
        IEM_INSTR_IMPL_A64__WFET_only_systeminstrswithreg(Rd);
#else
        RT_NOREF(Rd, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503205f: WFE
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_WFE_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503205f))
    {
        LogFlow(("%018x/%010x: WFE_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__WFE_HI_hints
        IEM_INSTR_IMPL_A64__WFE_HI_hints();
#else
        RT_NOREF(pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/d5031020: WFIT  <Xt>
   Instruction Set: A64  Groups: systeminstrswithreg, control */
FNIEMOP_DEF_1(iemDecodeA64_WFIT_only_systeminstrswithreg, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xd5031020))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fWfxt /*FEAT_WFxT*/)
        {
            LogFlow(("%018x/%010x: WFIT_only_systeminstrswithreg Rd=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd));
#ifdef IEM_INSTR_IMPL_A64__WFIT_only_systeminstrswithreg
            IEM_INSTR_IMPL_A64__WFIT_only_systeminstrswithreg(Rd);
#else
            RT_NOREF(Rd, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503207f: WFI
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_WFI_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503207f))
    {
        LogFlow(("%018x/%010x: WFI_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__WFI_HI_hints
        IEM_INSTR_IMPL_A64__WFI_HI_hints();
#else
        RT_NOREF(pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d500403f: XAFLAG
   Instruction Set: A64  Groups: pstate, control */
FNIEMOP_DEF_1(iemDecodeA64_XAFLAG_M_pstate, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd500403f))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFlagM2 /*FEAT_FlagM2*/)
        {
            LogFlow(("%018x/%010x: XAFLAG_M_pstate\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__XAFLAG_M_pstate
            IEM_INSTR_IMPL_A64__XAFLAG_M_pstate();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00000/ce800000: XAR  <Vd>.2D, <Vn>.2D, <Vm>.2D, #<imm6>
   Instruction Set: A64  Groups: crypto3_imm6, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_XAR_VVV2_crypto3_imm6, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00000)) == UINT32_C(0xce800000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm6       = (uOpcode >> 10) & 0x0000003f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha3 /*FEAT_SHA3*/)
        {
            LogFlow(("%018x/%010x: XAR_VVV2_crypto3_imm6 Rd=%#x Rn=%#x imm6=%#x Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, imm6, Rm));
#ifdef IEM_INSTR_IMPL_A64__XAR_VVV2_crypto3_imm6
            IEM_INSTR_IMPL_A64__XAR_VVV2_crypto3_imm6(Rd, Rn, imm6, Rm);
#else
            RT_NOREF(Rd, Rn, imm6, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/dac147e0: XPACD  <Xd>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_XPACD_64Z_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xdac147e0))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const D          = (uOpcode >> 10) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: XPACD_64Z_dp_1src Rd=%#x D=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, D));
#ifdef IEM_INSTR_IMPL_A64__XPACD_64Z_dp_1src
            IEM_INSTR_IMPL_A64__XPACD_64Z_dp_1src(Rd, D);
#else
            RT_NOREF(Rd, D, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/dac143e0: XPACI  <Xd>
   Instruction Set: A64  Groups: dp_1src, dpreg */
FNIEMOP_DEF_1(iemDecodeA64_XPACI_64Z_dp_1src, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xdac143e0))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const D          = (uOpcode >> 10) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: XPACI_64Z_dp_1src Rd=%#x D=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, D));
#ifdef IEM_INSTR_IMPL_A64__XPACI_64Z_dp_1src
            IEM_INSTR_IMPL_A64__XPACI_64Z_dp_1src(Rd, D);
#else
            RT_NOREF(Rd, D, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d50320ff: XPACLRI
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_XPACLRI_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd50320ff))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPAuth /*FEAT_PAuth*/)
        {
            LogFlow(("%018x/%010x: XPACLRI_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__XPACLRI_HI_hints
            IEM_INSTR_IMPL_A64__XPACLRI_HI_hints();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf3ffc00/0e212800: XTN2  <Vd>.<Tb>, <Vn>.<Ta>
   Instruction Set: A64  Groups: asimdmisc, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_XTN_asimdmisc_N, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
    {
        LogFlow(("%018x/%010x: XTN_asimdmisc_N Rd=%#x Rn=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, size, Q));
#ifdef IEM_INSTR_IMPL_A64__XTN_asimdmisc_N
        IEM_INSTR_IMPL_A64__XTN_asimdmisc_N(Rd, Rn, size, Q);
#else
        RT_NOREF(Rd, Rn, size, Q, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/d503203f: YIELD
   Instruction Set: A64  Groups: hints, control */
FNIEMOP_DEF_1(iemDecodeA64_YIELD_HI_hints, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503203f))
    {
        LogFlow(("%018x/%010x: YIELD_HI_hints\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__YIELD_HI_hints
        IEM_INSTR_IMPL_A64__YIELD_HI_hints();
#else
        RT_NOREF(pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e003800: ZIP1  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdperm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ZIP1_asimdperm_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e003800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ZIP1_asimdperm_only Rd=%#x Rn=%#x op=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ZIP1_asimdperm_only
            IEM_INSTR_IMPL_A64__ZIP1_asimdperm_only(Rd, Rn, op, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, op, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* bf20fc00/0e007800: ZIP2  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
   Instruction Set: A64  Groups: asimdperm, simd_dp */
FNIEMOP_DEF_1(iemDecodeA64_ZIP2_asimdperm_only, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e007800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        uint32_t const Q          = (uOpcode >> 30) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdvSimd /*FEAT_AdvSIMD*/)
        {
            LogFlow(("%018x/%010x: ZIP2_asimdperm_only Rd=%#x Rn=%#x op=%u Rm=%#x size=%u Q=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Rn, op, Rm, size, Q));
#ifdef IEM_INSTR_IMPL_A64__ZIP2_asimdperm_only
            IEM_INSTR_IMPL_A64__ZIP2_asimdperm_only(Rd, Rn, op, Rm, size, Q);
#else
            RT_NOREF(Rd, Rn, op, Rm, size, Q, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0416a000: ABS  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_abs_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0416a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: abs_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__abs_z_p_z_m
            IEM_INSTR_IMPL_A64__abs_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0406a000: ABS  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_abs_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0406a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: abs_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__abs_z_p_z_z
            IEM_INSTR_IMPL_A64__abs_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/4500d000: ADCLB  <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_adc_long, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_adclb_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: adclb_z_zzz Zda=%#x Zn=%#x T=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__adclb_z_zzz
        IEM_INSTR_IMPL_A64__adclb_z_zzz(Zda, Zn, T, Zm, sz);
#else
        RT_NOREF(Zda, Zn, T, Zm, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/4500d400: ADCLT  <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_adc_long, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_adclt_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x4500d400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: adclt_z_zzz Zda=%#x Zn=%#x T=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__adclt_z_zzz
            IEM_INSTR_IMPL_A64__adclt_z_zzz(Zda, Zn, T, Zm, sz);
#else
            RT_NOREF(Zda, Zn, T, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a300: ADD  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_add_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_add_mz_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a300))
    {
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: add_mz_zzv_2x1 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__add_mz_zzv_2x1
            IEM_INSTR_IMPL_A64__add_mz_zzv_2x1(Zdn, Zm, size);
#else
            RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120ab00: ADD  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_add_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_add_mz_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120ab00))
    {
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: add_mz_zzv_4x1 Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__add_mz_zzv_4x1
            IEM_INSTR_IMPL_A64__add_mz_zzv_4x1(Zdn, Zm, size);
#else
            RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04000000: ADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_0, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_add_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: add_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__add_z_p_zz
        IEM_INSTR_IMPL_A64__add_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fc000/2520c000: ADD  <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: sve_int_arith_imm0, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_add_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fc000)) == UINT32_C(0x2520c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const sh         = (uOpcode >> 13) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: add_z_zi Zdn=%#x imm8=%#x sh=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm8, sh, size));
#ifdef IEM_INSTR_IMPL_A64__add_z_zi
            IEM_INSTR_IMPL_A64__add_z_zi(Zdn, imm8, sh, size);
#else
            RT_NOREF(Zdn, imm8, sh, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04200000: ADD  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_cons_arit_0, sve_int_unpred_arit, sve */
FNIEMOP_DEF_1(iemDecodeA64_add_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04200000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: add_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__add_z_zz
            IEM_INSTR_IMPL_A64__add_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbf9c38/c1a01c10: ADD  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_int_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_add_za_zw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbf9c38)) == UINT32_C(0xc1a01c10))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zm         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: add_za_zw_2x2 off3=%u S=%u Zm=%#x Rv=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv, sz));
#ifdef IEM_INSTR_IMPL_A64__add_za_zw_2x2
            IEM_INSTR_IMPL_A64__add_za_zw_2x2(off3, S, Zm, Rv, sz);
#else
            RT_NOREF(off3, S, Zm, Rv, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbf9c78/c1a11c10: ADD  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_int_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_add_za_zw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbf9c78)) == UINT32_C(0xc1a11c10))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zm         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: add_za_zw_4x4 off3=%u S=%u Zm=%u Rv=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv, sz));
#ifdef IEM_INSTR_IMPL_A64__add_za_zw_4x4
            IEM_INSTR_IMPL_A64__add_za_zw_4x4(off3, S, Zm, Rv, sz);
#else
            RT_NOREF(off3, S, Zm, Rv, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c18/c1201810: ADD  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_int_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_add_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c18)) == UINT32_C(0xc1201810))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: add_za_zzv_2x1 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__add_za_zzv_2x1
            IEM_INSTR_IMPL_A64__add_za_zzv_2x1(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c18/c1301810: ADD  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_int_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_add_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c18)) == UINT32_C(0xc1301810))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: add_za_zzv_4x1 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__add_za_zzv_4x1
            IEM_INSTR_IMPL_A64__add_za_zzv_4x1(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa19c38/c1a01810: ADD  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_int_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_add_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa19c38)) == UINT32_C(0xc1a01810))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: add_za_zzw_2x2 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__add_za_zzw_2x2
            IEM_INSTR_IMPL_A64__add_za_zzw_2x2(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa39c78/c1a11810: ADD  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_int_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_add_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa39c78)) == UINT32_C(0xc1a11810))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: add_za_zzw_4x4 off3=%u S=%u Zn=%u Rv=%u Zm=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__add_za_zzw_4x4
            IEM_INSTR_IMPL_A64__add_za_zzw_4x4(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff001c/c0900000: ADDHA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S
   Instruction Set: A64  Groups: mortlach_addhv, mortlach_hvadd, sme */
FNIEMOP_DEF_1(iemDecodeA64_addha_za_pp_z_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: addha_za_pp_z_32 ZAda=%u Zn=%#x Pn=%u Pm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm));
#ifdef IEM_INSTR_IMPL_A64__addha_za_pp_z_32
        IEM_INSTR_IMPL_A64__addha_za_pp_z_32(ZAda, Zn, Pn, Pm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0018/c0d00000: ADDHA  <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.D
   Instruction Set: A64  Groups: mortlach_addhv, mortlach_hvadd, sme */
FNIEMOP_DEF_1(iemDecodeA64_addha_za_pp_z_64, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: addha_za_pp_z_64 ZAda=%u Zn=%#x Pn=%u Pm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm));
#ifdef IEM_INSTR_IMPL_A64__addha_za_pp_z_64
        IEM_INSTR_IMPL_A64__addha_za_pp_z_64(ZAda, Zn, Pn, Pm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45206000: ADDHNB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_arith_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_addhnb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: addhnb_z_zz Zd=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__addhnb_z_zz
        IEM_INSTR_IMPL_A64__addhnb_z_zz(Zd, Zn, T, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45206400: ADDHNT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_arith_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_addhnt_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45206400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: addhnt_z_zz Zd=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__addhnt_z_zz
            IEM_INSTR_IMPL_A64__addhnt_z_zz(Zd, Zn, T, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4411a000: ADDP  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_arith_binary_pairs, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_addp_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4411a000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: addp_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__addp_z_p_zz
            IEM_INSTR_IMPL_A64__addp_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f800/04605000: ADDPL  <Xd|SP>, <Xn|SP>, #<imm>
   Instruction Set: A64  Groups: sve_int_arith_vl, sve_alloca, sve */
FNIEMOP_DEF_1(iemDecodeA64_addpl_r_ri, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f800)) == UINT32_C(0x04605000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm6       = (uOpcode >>  5) & 0x0000003f;
        uint32_t const Rn         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: addpl_r_ri Rd=%#x imm6=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm6, Rn));
#ifdef IEM_INSTR_IMPL_A64__addpl_r_ri
            IEM_INSTR_IMPL_A64__addpl_r_ri(Rd, imm6, Rn);
#else
            RT_NOREF(Rd, imm6, Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/04c40000: ADDPT  <Zdn>.D, <Pg>/M, <Zdn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_0, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_addpt_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x04c40000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CPA*/)
        {
            LogFlow(("%018x/%010x: addpt_z_p_zz Zdn=%#x Zm=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg));
#ifdef IEM_INSTR_IMPL_A64__addpt_z_p_zz
            IEM_INSTR_IMPL_A64__addpt_z_p_zz(Zdn, Zm, Pg);
#else
            RT_NOREF(Zdn, Zm, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04e00800: ADDPT  <Zd>.D, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_cons_arit_0, sve_int_unpred_arit, sve */
FNIEMOP_DEF_1(iemDecodeA64_addpt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CPA*/)
    {
        LogFlow(("%018x/%010x: addpt_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__addpt_z_zz
        IEM_INSTR_IMPL_A64__addpt_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04052000: ADDQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_int_reduce_0q, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_addqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04052000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: addqv_z_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__addqv_z_p_z
            IEM_INSTR_IMPL_A64__addqv_z_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f800/04605800: ADDSPL  <Xd|SP>, <Xn|SP>, #<imm>
   Instruction Set: A64  Groups: sve_int_arith_svl, sve_alloca, sve */
FNIEMOP_DEF_1(iemDecodeA64_addspl_r_ri, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >>  5) & 0x0000003f;
    uint32_t const Rn         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: addspl_r_ri Rd=%#x imm6=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm6, Rn));
#ifdef IEM_INSTR_IMPL_A64__addspl_r_ri
        IEM_INSTR_IMPL_A64__addspl_r_ri(Rd, imm6, Rn);
#else
        RT_NOREF(Rd, imm6, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f800/04205800: ADDSVL  <Xd|SP>, <Xn|SP>, #<imm>
   Instruction Set: A64  Groups: sve_int_arith_svl, sve_alloca, sve */
FNIEMOP_DEF_1(iemDecodeA64_addsvl_r_ri, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >>  5) & 0x0000003f;
    uint32_t const Rn         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: addsvl_r_ri Rd=%#x imm6=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm6, Rn));
#ifdef IEM_INSTR_IMPL_A64__addsvl_r_ri
        IEM_INSTR_IMPL_A64__addsvl_r_ri(Rd, imm6, Rn);
#else
        RT_NOREF(Rd, imm6, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff001c/c0910000: ADDVA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S
   Instruction Set: A64  Groups: mortlach_addhv, mortlach_hvadd, sme */
FNIEMOP_DEF_1(iemDecodeA64_addva_za_pp_z_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: addva_za_pp_z_32 ZAda=%u Zn=%#x Pn=%u Pm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm));
#ifdef IEM_INSTR_IMPL_A64__addva_za_pp_z_32
        IEM_INSTR_IMPL_A64__addva_za_pp_z_32(ZAda, Zn, Pn, Pm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0018/c0d10000: ADDVA  <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.D
   Instruction Set: A64  Groups: mortlach_addhv, mortlach_hvadd, sme */
FNIEMOP_DEF_1(iemDecodeA64_addva_za_pp_z_64, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: addva_za_pp_z_64 ZAda=%u Zn=%#x Pn=%u Pm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm));
#ifdef IEM_INSTR_IMPL_A64__addva_za_pp_z_64
        IEM_INSTR_IMPL_A64__addva_za_pp_z_64(ZAda, Zn, Pn, Pm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f800/04205000: ADDVL  <Xd|SP>, <Xn|SP>, #<imm>
   Instruction Set: A64  Groups: sve_int_arith_vl, sve_alloca, sve */
FNIEMOP_DEF_1(iemDecodeA64_addvl_r_ri, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm6       = (uOpcode >>  5) & 0x0000003f;
    uint32_t const Rn         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: addvl_r_ri Rd=%#x imm6=%#x Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm6, Rn));
#ifdef IEM_INSTR_IMPL_A64__addvl_r_ri
        IEM_INSTR_IMPL_A64__addvl_r_ri(Rd, imm6, Rn);
#else
        RT_NOREF(Rd, imm6, Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/0420a000: ADR  <Zd>.D, [<Zn>.D, <Zm>.D, SXTW<amount>]
   Instruction Set: A64  Groups: sve_int_bin_cons_misc_0_a, sve_int_adr, sve */
FNIEMOP_DEF_1(iemDecodeA64_adr_z_az_d_s32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x0420a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const msz        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: adr_z_az_d_s32_scaled Zd=%#x Zn=%#x msz=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, msz, Zm));
#ifdef IEM_INSTR_IMPL_A64__adr_z_az_d_s32_scaled
            IEM_INSTR_IMPL_A64__adr_z_az_d_s32_scaled(Zd, Zn, msz, Zm);
#else
            RT_NOREF(Zd, Zn, msz, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/0460a000: ADR  <Zd>.D, [<Zn>.D, <Zm>.D, UXTW<amount>]
   Instruction Set: A64  Groups: sve_int_bin_cons_misc_0_a, sve_int_adr, sve */
FNIEMOP_DEF_1(iemDecodeA64_adr_z_az_d_u32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: adr_z_az_d_u32_scaled Zd=%#x Zn=%#x msz=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, msz, Zm));
#ifdef IEM_INSTR_IMPL_A64__adr_z_az_d_u32_scaled
        IEM_INSTR_IMPL_A64__adr_z_az_d_u32_scaled(Zd, Zn, msz, Zm);
#else
        RT_NOREF(Zd, Zn, msz, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0f000/04a0a000: ADR  <Zd>.<T>, [<Zn>.<T>, <Zm>.<T>{, <mod> <amount>}]
   Instruction Set: A64  Groups: sve_int_bin_cons_misc_0_a, sve_int_adr, sve */
FNIEMOP_DEF_1(iemDecodeA64_adr_z_az_sd_same_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0f000)) == UINT32_C(0x04a0a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const msz        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: adr_z_az_sd_same_scaled Zd=%#x Zn=%#x msz=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, msz, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__adr_z_az_sd_same_scaled
            IEM_INSTR_IMPL_A64__adr_z_az_sd_same_scaled(Zd, Zn, msz, Zm, sz);
#else
            RT_NOREF(Zd, Zn, msz, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe7fc01/4522ec00: AESD  { <Zdn1>.B-<Zdn2>.B }, { <Zdn1>.B-<Zdn2>.B }, <Zm>.Q[<index>]
   Instruction Set: A64  Groups: sve_crypto_binary_multi2, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_aesd_mz_zzi_2x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_AES2*/)
    {
        LogFlow(("%018x/%010x: aesd_mz_zzi_2x1 Zdn=%#x Zm=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__aesd_mz_zzi_2x1
        IEM_INSTR_IMPL_A64__aesd_mz_zzi_2x1(Zdn, Zm, i2);
#else
        RT_NOREF(Zdn, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe7fc03/4526ec00: AESD  { <Zdn1>.B-<Zdn4>.B }, { <Zdn1>.B-<Zdn4>.B }, <Zm>.Q[<index>]
   Instruction Set: A64  Groups: sve_crypto_binary_multi4, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_aesd_mz_zzi_4x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_AES2*/)
    {
        LogFlow(("%018x/%010x: aesd_mz_zzi_4x1 Zdn=%u Zm=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__aesd_mz_zzi_4x1
        IEM_INSTR_IMPL_A64__aesd_mz_zzi_4x1(Zdn, Zm, i2);
#else
        RT_NOREF(Zdn, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/4522e400: AESD  <Zdn>.B, <Zdn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_crypto_binary_dest, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_aesd_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x4522e400))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveAes /*FEAT_SVE_AES*/)
        {
            LogFlow(("%018x/%010x: aesd_z_zz Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__aesd_z_zz
            IEM_INSTR_IMPL_A64__aesd_z_zz(Zdn, Zm);
#else
            RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe7fc01/4523ec00: AESDIMC  { <Zdn1>.B-<Zdn2>.B }, { <Zdn1>.B-<Zdn2>.B }, <Zm>.Q[<index>]
   Instruction Set: A64  Groups: sve_crypto_binary_multi2, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_aesdimc_mz_zzi_2x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_AES2*/)
    {
        LogFlow(("%018x/%010x: aesdimc_mz_zzi_2x1 Zdn=%#x Zm=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__aesdimc_mz_zzi_2x1
        IEM_INSTR_IMPL_A64__aesdimc_mz_zzi_2x1(Zdn, Zm, i2);
#else
        RT_NOREF(Zdn, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe7fc03/4527ec00: AESDIMC  { <Zdn1>.B-<Zdn4>.B }, { <Zdn1>.B-<Zdn4>.B }, <Zm>.Q[<index>]
   Instruction Set: A64  Groups: sve_crypto_binary_multi4, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_aesdimc_mz_zzi_4x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_AES2*/)
    {
        LogFlow(("%018x/%010x: aesdimc_mz_zzi_4x1 Zdn=%u Zm=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__aesdimc_mz_zzi_4x1
        IEM_INSTR_IMPL_A64__aesdimc_mz_zzi_4x1(Zdn, Zm, i2);
#else
        RT_NOREF(Zdn, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe7fc01/4522e800: AESE  { <Zdn1>.B-<Zdn2>.B }, { <Zdn1>.B-<Zdn2>.B }, <Zm>.Q[<index>]
   Instruction Set: A64  Groups: sve_crypto_binary_multi2, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_aese_mz_zzi_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe7fc01)) == UINT32_C(0x4522e800))
    {
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_AES2*/)
        {
            LogFlow(("%018x/%010x: aese_mz_zzi_2x1 Zdn=%#x Zm=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__aese_mz_zzi_2x1
            IEM_INSTR_IMPL_A64__aese_mz_zzi_2x1(Zdn, Zm, i2);
#else
            RT_NOREF(Zdn, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe7fc03/4526e800: AESE  { <Zdn1>.B-<Zdn4>.B }, { <Zdn1>.B-<Zdn4>.B }, <Zm>.Q[<index>]
   Instruction Set: A64  Groups: sve_crypto_binary_multi4, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_aese_mz_zzi_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe7fc03)) == UINT32_C(0x4526e800))
    {
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_AES2*/)
        {
            LogFlow(("%018x/%010x: aese_mz_zzi_4x1 Zdn=%u Zm=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__aese_mz_zzi_4x1
            IEM_INSTR_IMPL_A64__aese_mz_zzi_4x1(Zdn, Zm, i2);
#else
            RT_NOREF(Zdn, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/4522e000: AESE  <Zdn>.B, <Zdn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_crypto_binary_dest, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_aese_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveAes /*FEAT_SVE_AES*/)
    {
        LogFlow(("%018x/%010x: aese_z_zz Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__aese_z_zz
        IEM_INSTR_IMPL_A64__aese_z_zz(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe7fc01/4523e800: AESEMC  { <Zdn1>.B-<Zdn2>.B }, { <Zdn1>.B-<Zdn2>.B }, <Zm>.Q[<index>]
   Instruction Set: A64  Groups: sve_crypto_binary_multi2, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_aesemc_mz_zzi_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe7fc01)) == UINT32_C(0x4523e800))
    {
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_AES2*/)
        {
            LogFlow(("%018x/%010x: aesemc_mz_zzi_2x1 Zdn=%#x Zm=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__aesemc_mz_zzi_2x1
            IEM_INSTR_IMPL_A64__aesemc_mz_zzi_2x1(Zdn, Zm, i2);
#else
            RT_NOREF(Zdn, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe7fc03/4527e800: AESEMC  { <Zdn1>.B-<Zdn4>.B }, { <Zdn1>.B-<Zdn4>.B }, <Zm>.Q[<index>]
   Instruction Set: A64  Groups: sve_crypto_binary_multi4, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_aesemc_mz_zzi_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe7fc03)) == UINT32_C(0x4527e800))
    {
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_AES2*/)
        {
            LogFlow(("%018x/%010x: aesemc_mz_zzi_4x1 Zdn=%u Zm=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__aesemc_mz_zzi_4x1
            IEM_INSTR_IMPL_A64__aesemc_mz_zzi_4x1(Zdn, Zm, i2);
#else
            RT_NOREF(Zdn, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/4520e400: AESIMC  <Zdn>.B, <Zdn>.B
   Instruction Set: A64  Groups: sve_crypto_unary, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_aesimc_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0x4520e400))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveAes /*FEAT_SVE_AES*/)
        {
            LogFlow(("%018x/%010x: aesimc_z_z Zdn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn));
#ifdef IEM_INSTR_IMPL_A64__aesimc_z_z
            IEM_INSTR_IMPL_A64__aesimc_z_z(Zdn);
#else
            RT_NOREF(Zdn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffe0/4520e000: AESMC  <Zdn>.B, <Zdn>.B
   Instruction Set: A64  Groups: sve_crypto_unary, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_aesmc_z_z, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveAes /*FEAT_SVE_AES*/)
    {
        LogFlow(("%018x/%010x: aesmc_z_z Zdn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn));
#ifdef IEM_INSTR_IMPL_A64__aesmc_z_z
        IEM_INSTR_IMPL_A64__aesmc_z_z(Zdn);
#else
        RT_NOREF(Zdn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25004000: AND  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_and_p_p_pp_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25004000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: and_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__and_p_p_pp_z
            IEM_INSTR_IMPL_A64__and_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/041a0000: AND  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_log, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_and_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: and_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__and_z_p_zz
        IEM_INSTR_IMPL_A64__and_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0000/05800000: AND  <Zdn>.<T>, <Zdn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_log_imm, sve_maskimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_and_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffc0000)) == UINT32_C(0x05800000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm13      = (uOpcode >>  5) & 0x00001fff;
        if (0x2 /*opc@22*/ != 3 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: and_z_zi Zdn=%#x imm13=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm13));
#ifdef IEM_INSTR_IMPL_A64__and_z_zi
            IEM_INSTR_IMPL_A64__and_z_zi(Zdn, imm13);
#else
            RT_NOREF(Zdn, imm13, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04203000: AND  <Zd>.D, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_cons_log, sve_int_unpred_logical, sve */
FNIEMOP_DEF_1(iemDecodeA64_and_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: and_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__and_z_zz
        IEM_INSTR_IMPL_A64__and_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/041e2000: ANDQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_int_reduce_2q, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_andqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x041e2000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: andqv_z_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__andqv_z_p_z
            IEM_INSTR_IMPL_A64__andqv_z_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25404000: ANDS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_ands_p_p_pp_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25404000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ands_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__ands_p_p_pp_z
            IEM_INSTR_IMPL_A64__ands_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/041a2000: ANDV  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_reduce_2, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_andv_r_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x041a2000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: andv_r_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__andv_r_p_z
            IEM_INSTR_IMPL_A64__andv_r_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04008000: ASR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_0, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_asr_z_p_zi, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm3       = (uOpcode >>  5) & 0x00000007;
    uint32_t const tszl       = (uOpcode >>  8) & 0x00000003;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: asr_z_p_zi Zdn=%#x imm3=%u tszl=%u Pg=%u U=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm3, tszl, Pg, U, tszh));
#ifdef IEM_INSTR_IMPL_A64__asr_z_p_zi
        IEM_INSTR_IMPL_A64__asr_z_p_zi(Zdn, imm3, tszl, Pg, U, tszh);
#else
        RT_NOREF(Zdn, imm3, tszl, Pg, U, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04188000: ASR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_2, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_asr_z_p_zw, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04188000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: asr_z_p_zw Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__asr_z_p_zw
            IEM_INSTR_IMPL_A64__asr_z_p_zw(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04108000: ASR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_1, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_asr_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: asr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__asr_z_p_zz
        IEM_INSTR_IMPL_A64__asr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04209000: ASR  <Zd>.<T>, <Zn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_bin_cons_shift_b, sve_int_unpred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_asr_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: asr_z_zi Zd=%#x Zn=%#x U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__asr_z_zi
        IEM_INSTR_IMPL_A64__asr_z_zi(Zd, Zn, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04208000: ASR  <Zd>.<T>, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_cons_shift_a, sve_int_unpred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_asr_z_zw, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: asr_z_zw Zd=%#x Zn=%#x U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__asr_z_zw
        IEM_INSTR_IMPL_A64__asr_z_zw(Zd, Zn, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04048000: ASRD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_0, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_asrd_z_p_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04048000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >>  5) & 0x00000007;
        uint32_t const tszl       = (uOpcode >>  8) & 0x00000003;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: asrd_z_p_zi Zdn=%#x imm3=%u tszl=%u Pg=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm3, tszl, Pg, tszh));
#ifdef IEM_INSTR_IMPL_A64__asrd_z_p_zi
            IEM_INSTR_IMPL_A64__asrd_z_p_zi(Zdn, imm3, tszl, Pg, tszh);
#else
            RT_NOREF(Zdn, imm3, tszl, Pg, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04148000: ASRR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_1, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_asrr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04148000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: asrr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__asrr_z_p_zz
            IEM_INSTR_IMPL_A64__asrr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04603800: BCAX  <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
   Instruction Set: A64  Groups: sve_int_tern_log, sve_int_unpred_logical, sve */
FNIEMOP_DEF_1(iemDecodeA64_bcax_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zk         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: bcax_z_zzz Zdn=%#x Zk=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zk, Zm));
#ifdef IEM_INSTR_IMPL_A64__bcax_z_zzz
        IEM_INSTR_IMPL_A64__bcax_z_zzz(Zdn, Zk, Zm);
#else
        RT_NOREF(Zdn, Zk, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500b400: BDEP  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_perm_bit, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_bdep_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500b400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveBitPerm /*FEAT_SVE_BitPerm*/)
        {
            LogFlow(("%018x/%010x: bdep_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__bdep_z_zz
            IEM_INSTR_IMPL_A64__bdep_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500b000: BEXT  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_perm_bit, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_bext_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveBitPerm /*FEAT_SVE_BitPerm*/)
    {
        LogFlow(("%018x/%010x: bext_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__bext_z_zz
        IEM_INSTR_IMPL_A64__bext_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc01/c166e000: BF1CVT  { <Zd1>.H-<Zd2>.H }, <Zn>.B
   Instruction Set: A64  Groups: mortlach_multi2_wide_fp8_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bf1cvt_mz2_z8, uint32_t, uOpcode)
{
    uint32_t const L          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: bf1cvt_mz2_z8 L=%u Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, L, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__bf1cvt_mz2_z8
        IEM_INSTR_IMPL_A64__bf1cvt_mz2_z8(L, Zd, Zn);
#else
        RT_NOREF(L, Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/65083800: BF1CVT  <Zd>.H, <Zn>.B
   Instruction Set: A64  Groups: sve_fp8_fcvt_wide, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bf1cvt_z_z8_b2bf, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const L          = (uOpcode >> 16) & 0x00000001;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: bf1cvt_z_z8_b2bf Zd=%#x Zn=%#x L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, L));
#ifdef IEM_INSTR_IMPL_A64__bf1cvt_z_z8_b2bf
        IEM_INSTR_IMPL_A64__bf1cvt_z_z8_b2bf(Zd, Zn, L);
#else
        RT_NOREF(Zd, Zn, L, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc01/c166e001: BF1CVTL  { <Zd1>.H-<Zd2>.H }, <Zn>.B
   Instruction Set: A64  Groups: mortlach_multi2_wide_fp8_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bf1cvtl_mz2_z8, uint32_t, uOpcode)
{
    uint32_t const L          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: bf1cvtl_mz2_z8 L=%u Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, L, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__bf1cvtl_mz2_z8
        IEM_INSTR_IMPL_A64__bf1cvtl_mz2_z8(L, Zd, Zn);
#else
        RT_NOREF(L, Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/65093800: BF1CVTLT  <Zd>.H, <Zn>.B
   Instruction Set: A64  Groups: sve_fp8_fcvt_wide, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bf1cvtlt_z_z8_b2bf, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const L          = (uOpcode >> 16) & 0x00000001;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: bf1cvtlt_z_z8_b2bf Zd=%#x Zn=%#x L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, L));
#ifdef IEM_INSTR_IMPL_A64__bf1cvtlt_z_z8_b2bf
        IEM_INSTR_IMPL_A64__bf1cvtlt_z_z8_b2bf(Zd, Zn, L);
#else
        RT_NOREF(Zd, Zn, L, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc01/c1e6e000: BF2CVT  { <Zd1>.H-<Zd2>.H }, <Zn>.B
   Instruction Set: A64  Groups: mortlach_multi2_wide_fp8_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bf2cvt_mz2_z8, uint32_t, uOpcode)
{
    uint32_t const L          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: bf2cvt_mz2_z8 L=%u Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, L, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__bf2cvt_mz2_z8
        IEM_INSTR_IMPL_A64__bf2cvt_mz2_z8(L, Zd, Zn);
#else
        RT_NOREF(L, Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/65083c00: BF2CVT  <Zd>.H, <Zn>.B
   Instruction Set: A64  Groups: sve_fp8_fcvt_wide, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bf2cvt_z_z8_b2bf, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const L          = (uOpcode >> 16) & 0x00000001;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: bf2cvt_z_z8_b2bf Zd=%#x Zn=%#x L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, L));
#ifdef IEM_INSTR_IMPL_A64__bf2cvt_z_z8_b2bf
        IEM_INSTR_IMPL_A64__bf2cvt_z_z8_b2bf(Zd, Zn, L);
#else
        RT_NOREF(Zd, Zn, L, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc01/c1e6e001: BF2CVTL  { <Zd1>.H-<Zd2>.H }, <Zn>.B
   Instruction Set: A64  Groups: mortlach_multi2_wide_fp8_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bf2cvtl_mz2_z8, uint32_t, uOpcode)
{
    uint32_t const L          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: bf2cvtl_mz2_z8 L=%u Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, L, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__bf2cvtl_mz2_z8
        IEM_INSTR_IMPL_A64__bf2cvtl_mz2_z8(L, Zd, Zn);
#else
        RT_NOREF(L, Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/65093c00: BF2CVTLT  <Zd>.H, <Zn>.B
   Instruction Set: A64  Groups: sve_fp8_fcvt_wide, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bf2cvtlt_z_z8_b2bf, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const L          = (uOpcode >> 16) & 0x00000001;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: bf2cvtlt_z_z8_b2bf Zd=%#x Zn=%#x L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, L));
#ifdef IEM_INSTR_IMPL_A64__bf2cvtlt_z_z8_b2bf
        IEM_INSTR_IMPL_A64__bf2cvtlt_z_z8_b2bf(Zd, Zn, L);
#else
        RT_NOREF(Zd, Zn, L, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65008000: BFADD  <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfadd_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfadd_z_p_zz Zdn=%#x Zm=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg));
#ifdef IEM_INSTR_IMPL_A64__bfadd_z_p_zz
        IEM_INSTR_IMPL_A64__bfadd_z_p_zz(Zdn, Zm, Pg);
#else
        RT_NOREF(Zdn, Zm, Pg, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/65000000: BFADD  <Zd>.H, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_3op_u_zd, sve_fp_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfadd_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfadd_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfadd_z_zz
        IEM_INSTR_IMPL_A64__bfadd_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9c38/c1e41c00: BFADD  ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_f16_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfadd_za_zw_2x2_16, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const Zm         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfadd_za_zw_2x2_16 off3=%u S=%u Zm=%#x Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv));
#ifdef IEM_INSTR_IMPL_A64__bfadd_za_zw_2x2_16
        IEM_INSTR_IMPL_A64__bfadd_za_zw_2x2_16(off3, S, Zm, Rv);
#else
        RT_NOREF(off3, S, Zm, Rv, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9c78/c1e51c00: BFADD  ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_f16_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfadd_za_zw_4x4_16, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const Zm         = (uOpcode >>  7) & 0x00000007;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfadd_za_zw_4x4_16 off3=%u S=%u Zm=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv));
#ifdef IEM_INSTR_IMPL_A64__bfadd_za_zw_4x4_16
        IEM_INSTR_IMPL_A64__bfadd_za_zw_4x4_16(off3, S, Zm, Rv);
#else
        RT_NOREF(off3, S, Zm, Rv, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc01/c120c000: BFCLAMP  { <Zd1>.H-<Zd2>.H }, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_fclamp, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfclamp_mz_zz_2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfclamp_mz_zz_2 Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfclamp_mz_zz_2
        IEM_INSTR_IMPL_A64__bfclamp_mz_zz_2(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc03/c120c800: BFCLAMP  { <Zd1>.H-<Zd4>.H }, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_fclamp, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfclamp_mz_zz_4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfclamp_mz_zz_4 Zd=%u Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfclamp_mz_zz_4
        IEM_INSTR_IMPL_A64__bfclamp_mz_zz_4(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64202400: BFCLAMP  <Zd>.H, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_clamp_lvl2, sve_fp_clamp, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfclamp_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfclamp_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfclamp_z_zz
        IEM_INSTR_IMPL_A64__bfclamp_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/c164e000: BFCVT  <Zd>.B, { <Zn1>.H-<Zn2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_narrow_fp8_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfcvt_z8_mz2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0xc164e000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
        {
            LogFlow(("%018x/%010x: bfcvt_z8_mz2 Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__bfcvt_z8_mz2
            IEM_INSTR_IMPL_A64__bfcvt_z8_mz2(Zd, Zn);
#else
            RT_NOREF(Zd, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/c160e000: BFCVT  <Zd>.H, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_narrow_fp_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfcvt_z_mz2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const N          = (uOpcode >>  5) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfcvt_z_mz2 Zd=%#x N=%u Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, N, Zn));
#ifdef IEM_INSTR_IMPL_A64__bfcvt_z_mz2
        IEM_INSTR_IMPL_A64__bfcvt_z_mz2(Zd, N, Zn);
#else
        RT_NOREF(Zd, N, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/658aa000: BFCVT  <Zd>.H, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_b_0, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfcvt_z_p_z_s2bf, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x658aa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: bfcvt_z_p_z_s2bf Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__bfcvt_z_p_z_s2bf
            IEM_INSTR_IMPL_A64__bfcvt_z_p_z_s2bf(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/649ac000: BFCVT  <Zd>.H, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_b_0, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfcvt_z_p_z_s2bfz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x649ac000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: bfcvt_z_p_z_s2bfz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__bfcvt_z_p_z_s2bfz
            IEM_INSTR_IMPL_A64__bfcvt_z_p_z_s2bfz(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/650a3800: BFCVTN  <Zd>.B, { <Zn1>.H-<Zn2>.H }
   Instruction Set: A64  Groups: sve_fp8_fcvt_narrow, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfcvtn_z8_mz2_bf2b, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: bfcvtn_z8_mz2_bf2b Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__bfcvtn_z8_mz2_bf2b
        IEM_INSTR_IMPL_A64__bfcvtn_z8_mz2_bf2b(Zd, Zn);
#else
        RT_NOREF(Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/c160e020: BFCVTN  <Zd>.H, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_narrow_fp_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfcvtn_z_mz2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const N          = (uOpcode >>  5) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfcvtn_z_mz2 Zd=%#x N=%u Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, N, Zn));
#ifdef IEM_INSTR_IMPL_A64__bfcvtn_z_mz2
        IEM_INSTR_IMPL_A64__bfcvtn_z_mz2(Zd, N, Zn);
#else
        RT_NOREF(Zd, N, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/648aa000: BFCVTNT  <Zd>.H, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_fcvt2_lvl2, sve_fp_fcvt2, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfcvtnt_z_p_z_s2bf, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x648aa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: bfcvtnt_z_p_z_s2bf Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__bfcvtnt_z_p_z_s2bf
            IEM_INSTR_IMPL_A64__bfcvtnt_z_p_z_s2bf(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6482a000: BFCVTNT  <Zd>.H, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_fcvt2z_lvl2, sve_fp_fcvt2z, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfcvtnt_z_p_z_s2bfz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6482a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: bfcvtnt_z_p_z_s2bfz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__bfcvtnt_z_p_z_s2bfz
            IEM_INSTR_IMPL_A64__bfcvtnt_z_p_z_s2bfz(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64608000: BFDOT  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_fdot, sve_fp_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfdot_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64608000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: bfdot_z_zzz Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfdot_z_zzz
            IEM_INSTR_IMPL_A64__bfdot_z_zzz(Zda, Zn, Zm);
#else
            RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64604000: BFDOT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fdot_by_indexed_elem, sve_fp_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfdot_z_zzzi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64604000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: bfdot_z_zzzi Zda=%#x Zn=%#x Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__bfdot_z_zzzi
            IEM_INSTR_IMPL_A64__bfdot_z_zzzi(Zda, Zn, Zm, i2);
#else
            RT_NOREF(Zda, Zn, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1501018: BFDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfdot_za_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1501018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfdot_za_zzi_2xi off3=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfdot_za_zzi_2xi
            IEM_INSTR_IMPL_A64__bfdot_za_zzi_2xi(off3, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1509018: BFDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfdot_za_zzi_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1509018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfdot_za_zzi_4xi off3=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfdot_za_zzi_4xi
            IEM_INSTR_IMPL_A64__bfdot_za_zzi_4xi(off3, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1201010: BFDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_z_za_fpdot_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfdot_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1201010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfdot_za_zzv_2x1 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfdot_za_zzv_2x1
            IEM_INSTR_IMPL_A64__bfdot_za_zzv_2x1(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1301010: BFDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_z_za_fpdot_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfdot_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1301010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfdot_za_zzv_4x1 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfdot_za_zzv_4x1
            IEM_INSTR_IMPL_A64__bfdot_za_zzv_4x1(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c38/c1a01010: BFDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_fpdot_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfdot_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c38)) == UINT32_C(0xc1a01010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfdot_za_zzw_2x2 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfdot_za_zzw_2x2
            IEM_INSTR_IMPL_A64__bfdot_za_zzw_2x2(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c78/c1a11010: BFDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_fpdot_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfdot_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c78)) == UINT32_C(0xc1a11010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfdot_za_zzw_4x4 off3=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfdot_za_zzw_4x4
            IEM_INSTR_IMPL_A64__bfdot_za_zzw_4x4(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0ffe1/c120a100: BFMAX  { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmax_mz_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmax_mz_zzv_2x1 Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmax_mz_zzv_2x1
        IEM_INSTR_IMPL_A64__bfmax_mz_zzv_2x1(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0ffe3/c120a900: BFMAX  { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmax_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmax_mz_zzv_4x1 Zdn=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmax_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__bfmax_mz_zzv_4x1(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe1ffe1/c120b100: BFMAX  { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmax_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmax_mz_zzw_2x2 Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmax_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__bfmax_mz_zzw_2x2(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe3ffe3/c120b900: BFMAX  { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmax_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmax_mz_zzw_4x4 Zdn=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmax_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__bfmax_mz_zzw_4x4(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65068000: BFMAX  <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmax_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmax_z_p_zz Zdn=%#x Zm=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg));
#ifdef IEM_INSTR_IMPL_A64__bfmax_z_p_zz
        IEM_INSTR_IMPL_A64__bfmax_z_p_zz(Zdn, Zm, Pg);
#else
        RT_NOREF(Zdn, Zm, Pg, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0ffe1/c120a120: BFMAXNM  { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmaxnm_mz_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmaxnm_mz_zzv_2x1 Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmaxnm_mz_zzv_2x1
        IEM_INSTR_IMPL_A64__bfmaxnm_mz_zzv_2x1(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0ffe3/c120a920: BFMAXNM  { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmaxnm_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmaxnm_mz_zzv_4x1 Zdn=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmaxnm_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__bfmaxnm_mz_zzv_4x1(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe1ffe1/c120b120: BFMAXNM  { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmaxnm_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmaxnm_mz_zzw_2x2 Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmaxnm_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__bfmaxnm_mz_zzw_2x2(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe3ffe3/c120b920: BFMAXNM  { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmaxnm_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmaxnm_mz_zzw_4x4 Zdn=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmaxnm_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__bfmaxnm_mz_zzw_4x4(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65048000: BFMAXNM  <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmaxnm_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmaxnm_z_p_zz Zdn=%#x Zm=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg));
#ifdef IEM_INSTR_IMPL_A64__bfmaxnm_z_p_zz
        IEM_INSTR_IMPL_A64__bfmaxnm_z_p_zz(Zdn, Zm, Pg);
#else
        RT_NOREF(Zdn, Zm, Pg, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0ffe1/c120a101: BFMIN  { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmin_mz_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmin_mz_zzv_2x1 Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmin_mz_zzv_2x1
        IEM_INSTR_IMPL_A64__bfmin_mz_zzv_2x1(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0ffe3/c120a901: BFMIN  { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmin_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmin_mz_zzv_4x1 Zdn=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmin_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__bfmin_mz_zzv_4x1(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe1ffe1/c120b101: BFMIN  { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmin_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmin_mz_zzw_2x2 Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmin_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__bfmin_mz_zzw_2x2(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe3ffe3/c120b901: BFMIN  { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmin_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmin_mz_zzw_4x4 Zdn=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmin_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__bfmin_mz_zzw_4x4(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65078000: BFMIN  <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmin_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmin_z_p_zz Zdn=%#x Zm=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg));
#ifdef IEM_INSTR_IMPL_A64__bfmin_z_p_zz
        IEM_INSTR_IMPL_A64__bfmin_z_p_zz(Zdn, Zm, Pg);
#else
        RT_NOREF(Zdn, Zm, Pg, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0ffe1/c120a121: BFMINNM  { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfminnm_mz_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfminnm_mz_zzv_2x1 Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfminnm_mz_zzv_2x1
        IEM_INSTR_IMPL_A64__bfminnm_mz_zzv_2x1(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0ffe3/c120a921: BFMINNM  { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfminnm_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfminnm_mz_zzv_4x1 Zdn=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfminnm_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__bfminnm_mz_zzv_4x1(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe1ffe1/c120b121: BFMINNM  { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfminnm_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfminnm_mz_zzw_2x2 Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfminnm_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__bfminnm_mz_zzw_2x2(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe3ffe3/c120b921: BFMINNM  { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfminnm_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfminnm_mz_zzw_4x4 Zdn=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfminnm_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__bfminnm_mz_zzw_4x4(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65058000: BFMINNM  <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfminnm_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfminnm_z_p_zz Zdn=%#x Zm=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg));
#ifdef IEM_INSTR_IMPL_A64__bfminnm_z_p_zz
        IEM_INSTR_IMPL_A64__bfminnm_z_p_zz(Zdn, Zm, Pg);
#else
        RT_NOREF(Zdn, Zm, Pg, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/65200000: BFMLA  <Zda>.H, <Pg>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_3op_p_zds_a, sve_fp_fma, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmla_z_p_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmla_z_p_zzz Zda=%#x Zn=%#x Pg=%u op=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Pg, op, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmla_z_p_zzz
        IEM_INSTR_IMPL_A64__bfmla_z_p_zzz(Zda, Zn, Pg, op, Zm);
#else
        RT_NOREF(Zda, Zn, Pg, op, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/64200800: BFMLA  <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_by_indexed_elem_lvl2, sve_fp_fma_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmla_z_zzzi_h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x64200800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
        {
            LogFlow(("%018x/%010x: bfmla_z_zzzi_h Zda=%#x Zn=%#x op=%u Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, op, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__bfmla_z_zzzi_h
            IEM_INSTR_IMPL_A64__bfmla_z_zzzi_h(Zda, Zn, op, Zm, i3l, i3h);
#else
            RT_NOREF(Zda, Zn, op, Zm, i3l, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09030/c1101020: BFMLA  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_h, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmla_za_zzi_h2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09030)) == UINT32_C(0xc1101020))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i3l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
        {
            LogFlow(("%018x/%010x: bfmla_za_zzi_h2xi off3=%u i3l=%u S=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmla_za_zzi_h2xi
            IEM_INSTR_IMPL_A64__bfmla_za_zzi_h2xi(off3, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off3, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09070/c1109020: BFMLA  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_h, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmla_za_zzi_h4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09070)) == UINT32_C(0xc1109020))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i3l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
        {
            LogFlow(("%018x/%010x: bfmla_za_zzi_h4xi off3=%u i3l=%u S=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmla_za_zzi_h4xi
            IEM_INSTR_IMPL_A64__bfmla_za_zzi_h4xi(off3, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off3, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1601c00: BFMLA  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_f16_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmla_za_zzv_2x1_16, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmla_za_zzv_2x1_16 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmla_za_zzv_2x1_16
        IEM_INSTR_IMPL_A64__bfmla_za_zzv_2x1_16(off3, S, Zn, Rv, Zm);
#else
        RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1701c00: BFMLA  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_f16_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmla_za_zzv_4x1_16, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmla_za_zzv_4x1_16 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmla_za_zzv_4x1_16
        IEM_INSTR_IMPL_A64__bfmla_za_zzv_4x1_16(off3, S, Zn, Rv, Zm);
#else
        RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c38/c1e01008: BFMLA  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_f16_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmla_za_zzw_2x2_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c38)) == UINT32_C(0xc1e01008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
        {
            LogFlow(("%018x/%010x: bfmla_za_zzw_2x2_16 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmla_za_zzw_2x2_16
            IEM_INSTR_IMPL_A64__bfmla_za_zzw_2x2_16(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c78/c1e11008: BFMLA  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_f16_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmla_za_zzw_4x4_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c78)) == UINT32_C(0xc1e11008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
        {
            LogFlow(("%018x/%010x: bfmla_za_zzw_4x4_16 off3=%u S=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmla_za_zzw_4x4_16
            IEM_INSTR_IMPL_A64__bfmla_za_zzw_4x4_16(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff01018/c1801010: BFMLAL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_fma_long_idx, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlal_za_zzi_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff01018)) == UINT32_C(0xc1801010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i3l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlal_za_zzi_1 off3=%u S=%u Zn=%#x i3l=%u Rv=%u i3h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, i3l, Rv, i3h, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlal_za_zzi_1
            IEM_INSTR_IMPL_A64__bfmlal_za_zzi_1(off3, S, Zn, i3l, Rv, i3h, Zm);
#else
            RT_NOREF(off3, S, Zn, i3l, Rv, i3h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1901010: BFMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_fma_long_idx, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlal_za_zzi_2xi, uint32_t, uOpcode)
{
    uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
    uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfmlal_za_zzi_2xi off2=%u i3l=%u S=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlal_za_zzi_2xi
        IEM_INSTR_IMPL_A64__bfmlal_za_zzi_2xi(off2, i3l, S, Zn, i3h, Rv, Zm);
#else
        RT_NOREF(off2, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1909010: BFMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_fma_long_idx, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlal_za_zzi_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1909010))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlal_za_zzi_4xi off2=%u i3l=%u S=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlal_za_zzi_4xi
            IEM_INSTR_IMPL_A64__bfmlal_za_zzi_4xi(off2, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1200c10: BFMLAL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_fma_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlal_za_zzv_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1200c10))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlal_za_zzv_1 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlal_za_zzv_1
            IEM_INSTR_IMPL_A64__bfmlal_za_zzv_1(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1200810: BFMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_fma_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlal_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1200810))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlal_za_zzv_2x1 off2=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlal_za_zzv_2x1
            IEM_INSTR_IMPL_A64__bfmlal_za_zzv_2x1(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1300810: BFMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_fma_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlal_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1300810))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlal_za_zzv_4x1 off2=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlal_za_zzv_4x1
            IEM_INSTR_IMPL_A64__bfmlal_za_zzv_4x1(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c3c/c1a00810: BFMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_fma_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlal_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c3c)) == UINT32_C(0xc1a00810))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlal_za_zzw_2x2 off2=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlal_za_zzw_2x2
            IEM_INSTR_IMPL_A64__bfmlal_za_zzw_2x2(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c7c/c1a10810: BFMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_fma_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlal_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c7c)) == UINT32_C(0xc1a10810))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlal_za_zzw_4x4 off2=%u S=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlal_za_zzw_4x4
            IEM_INSTR_IMPL_A64__bfmlal_za_zzw_4x4(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64e08000: BFMLALB  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_fma_long, sve_fp_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmlalb_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64e08000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: bfmlalb_z_zzz Zda=%#x Zn=%#x T=%u op=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, op, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlalb_z_zzz
            IEM_INSTR_IMPL_A64__bfmlalb_z_zzz(Zda, Zn, T, op, Zm);
#else
            RT_NOREF(Zda, Zn, T, op, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/64e04000: BFMLALB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_long_by_indexed_elem, sve_fp_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmlalb_z_zzzi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x64e04000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: bfmlalb_z_zzzi Zda=%#x Zn=%#x T=%u i3l=%u op=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, op, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__bfmlalb_z_zzzi
            IEM_INSTR_IMPL_A64__bfmlalb_z_zzzi(Zda, Zn, T, i3l, op, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, T, i3l, op, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64e08400: BFMLALT  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_fma_long, sve_fp_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmlalt_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
    {
        LogFlow(("%018x/%010x: bfmlalt_z_zzz Zda=%#x Zn=%#x T=%u op=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, op, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlalt_z_zzz
        IEM_INSTR_IMPL_A64__bfmlalt_z_zzz(Zda, Zn, T, op, Zm);
#else
        RT_NOREF(Zda, Zn, T, op, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/64e04400: BFMLALT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_long_by_indexed_elem, sve_fp_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmlalt_z_zzzi, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
    {
        LogFlow(("%018x/%010x: bfmlalt_z_zzzi Zda=%#x Zn=%#x T=%u i3l=%u op=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, op, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__bfmlalt_z_zzzi
        IEM_INSTR_IMPL_A64__bfmlalt_z_zzzi(Zda, Zn, T, i3l, op, Zm, i3h);
#else
        RT_NOREF(Zda, Zn, T, i3l, op, Zm, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/65202000: BFMLS  <Zda>.H, <Pg>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_3op_p_zds_a, sve_fp_fma, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmls_z_p_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmls_z_p_zzz Zda=%#x Zn=%#x Pg=%u op=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Pg, op, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmls_z_p_zzz
        IEM_INSTR_IMPL_A64__bfmls_z_p_zzz(Zda, Zn, Pg, op, Zm);
#else
        RT_NOREF(Zda, Zn, Pg, op, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/64200c00: BFMLS  <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_by_indexed_elem_lvl2, sve_fp_fma_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmls_z_zzzi_h, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
    uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmls_z_zzzi_h Zda=%#x Zn=%#x op=%u Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, op, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__bfmls_z_zzzi_h
        IEM_INSTR_IMPL_A64__bfmls_z_zzzi_h(Zda, Zn, op, Zm, i3l, i3h);
#else
        RT_NOREF(Zda, Zn, op, Zm, i3l, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09030/c1101030: BFMLS  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_h, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmls_za_zzi_h2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09030)) == UINT32_C(0xc1101030))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i3l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
        {
            LogFlow(("%018x/%010x: bfmls_za_zzi_h2xi off3=%u i3l=%u S=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmls_za_zzi_h2xi
            IEM_INSTR_IMPL_A64__bfmls_za_zzi_h2xi(off3, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off3, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09070/c1109030: BFMLS  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_h, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmls_za_zzi_h4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09070)) == UINT32_C(0xc1109030))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i3l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
        {
            LogFlow(("%018x/%010x: bfmls_za_zzi_h4xi off3=%u i3l=%u S=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmls_za_zzi_h4xi
            IEM_INSTR_IMPL_A64__bfmls_za_zzi_h4xi(off3, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off3, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1601c08: BFMLS  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_f16_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmls_za_zzv_2x1_16, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmls_za_zzv_2x1_16 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmls_za_zzv_2x1_16
        IEM_INSTR_IMPL_A64__bfmls_za_zzv_2x1_16(off3, S, Zn, Rv, Zm);
#else
        RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1701c08: BFMLS  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_f16_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmls_za_zzv_4x1_16, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmls_za_zzv_4x1_16 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmls_za_zzv_4x1_16
        IEM_INSTR_IMPL_A64__bfmls_za_zzv_4x1_16(off3, S, Zn, Rv, Zm);
#else
        RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c38/c1e01018: BFMLS  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_f16_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmls_za_zzw_2x2_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c38)) == UINT32_C(0xc1e01018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
        {
            LogFlow(("%018x/%010x: bfmls_za_zzw_2x2_16 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmls_za_zzw_2x2_16
            IEM_INSTR_IMPL_A64__bfmls_za_zzw_2x2_16(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c78/c1e11018: BFMLS  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_f16_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmls_za_zzw_4x4_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c78)) == UINT32_C(0xc1e11018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
        {
            LogFlow(("%018x/%010x: bfmls_za_zzw_4x4_16 off3=%u S=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmls_za_zzw_4x4_16
            IEM_INSTR_IMPL_A64__bfmls_za_zzw_4x4_16(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff01018/c1801018: BFMLSL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_fma_long_idx, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlsl_za_zzi_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff01018)) == UINT32_C(0xc1801018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i3l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlsl_za_zzi_1 off3=%u S=%u Zn=%#x i3l=%u Rv=%u i3h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, i3l, Rv, i3h, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlsl_za_zzi_1
            IEM_INSTR_IMPL_A64__bfmlsl_za_zzi_1(off3, S, Zn, i3l, Rv, i3h, Zm);
#else
            RT_NOREF(off3, S, Zn, i3l, Rv, i3h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1901018: BFMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_fma_long_idx, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlsl_za_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1901018))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlsl_za_zzi_2xi off2=%u i3l=%u S=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlsl_za_zzi_2xi
            IEM_INSTR_IMPL_A64__bfmlsl_za_zzi_2xi(off2, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1909018: BFMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_fma_long_idx, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlsl_za_zzi_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1909018))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlsl_za_zzi_4xi off2=%u i3l=%u S=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlsl_za_zzi_4xi
            IEM_INSTR_IMPL_A64__bfmlsl_za_zzi_4xi(off2, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1200c18: BFMLSL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_fma_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlsl_za_zzv_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1200c18))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlsl_za_zzv_1 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlsl_za_zzv_1
            IEM_INSTR_IMPL_A64__bfmlsl_za_zzv_1(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1200818: BFMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_fma_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlsl_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1200818))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlsl_za_zzv_2x1 off2=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlsl_za_zzv_2x1
            IEM_INSTR_IMPL_A64__bfmlsl_za_zzv_2x1(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1300818: BFMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_fma_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlsl_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1300818))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlsl_za_zzv_4x1 off2=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlsl_za_zzv_4x1
            IEM_INSTR_IMPL_A64__bfmlsl_za_zzv_4x1(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c3c/c1a00818: BFMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_fma_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlsl_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c3c)) == UINT32_C(0xc1a00818))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlsl_za_zzw_2x2 off2=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlsl_za_zzw_2x2
            IEM_INSTR_IMPL_A64__bfmlsl_za_zzw_2x2(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c7c/c1a10818: BFMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_fma_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmlsl_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c7c)) == UINT32_C(0xc1a10818))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfmlsl_za_zzw_4x4 off2=%u S=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlsl_za_zzw_4x4
            IEM_INSTR_IMPL_A64__bfmlsl_za_zzw_4x4(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64e0a000: BFMLSLB  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_fma_long, sve_fp_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmlslb_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: bfmlslb_z_zzz Zda=%#x Zn=%#x T=%u op=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, op, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlslb_z_zzz
        IEM_INSTR_IMPL_A64__bfmlslb_z_zzz(Zda, Zn, T, op, Zm);
#else
        RT_NOREF(Zda, Zn, T, op, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/64e06000: BFMLSLB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_long_by_indexed_elem, sve_fp_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmlslb_z_zzzi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x64e06000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: bfmlslb_z_zzzi Zda=%#x Zn=%#x T=%u i3l=%u op=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, op, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__bfmlslb_z_zzzi
            IEM_INSTR_IMPL_A64__bfmlslb_z_zzzi(Zda, Zn, T, i3l, op, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, T, i3l, op, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64e0a400: BFMLSLT  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_fma_long, sve_fp_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmlslt_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64e0a400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: bfmlslt_z_zzz Zda=%#x Zn=%#x T=%u op=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, op, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmlslt_z_zzz
            IEM_INSTR_IMPL_A64__bfmlslt_z_zzz(Zda, Zn, T, op, Zm);
#else
            RT_NOREF(Zda, Zn, T, op, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/64e06400: BFMLSLT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_long_by_indexed_elem, sve_fp_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmlslt_z_zzzi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x64e06400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: bfmlslt_z_zzzi Zda=%#x Zn=%#x T=%u i3l=%u op=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, op, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__bfmlslt_z_zzzi
            IEM_INSTR_IMPL_A64__bfmlslt_z_zzzi(Zda, Zn, T, i3l, op, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, T, i3l, op, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/6460e400: BFMMLA  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_fmmla_lvl2, sve_fp_fmmla, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmmla_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x6460e400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBf16 /*FEAT_BF16*/)
        {
            LogFlow(("%018x/%010x: bfmmla_z_zzz Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmmla_z_zzz
            IEM_INSTR_IMPL_A64__bfmmla_z_zzz(Zda, Zn, Zm);
#else
            RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81000000: BFMOP4A  <ZAda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_b16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4a_za32_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81000000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4a_za32_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4a_za32_zz_h1x1
            IEM_INSTR_IMPL_A64__bfmop4a_za32_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81100000: BFMOP4A  <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_b16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4a_za32_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81100000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4a_za32_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4a_za32_zz_h1x2
            IEM_INSTR_IMPL_A64__bfmop4a_za32_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81000200: BFMOP4A  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_b16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4a_za32_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81000200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4a_za32_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4a_za32_zz_h2x1
            IEM_INSTR_IMPL_A64__bfmop4a_za32_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81100200: BFMOP4A  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_b16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4a_za32_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81100200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4a_za32_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4a_za32_zz_h2x2
            IEM_INSTR_IMPL_A64__bfmop4a_za32_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81200008: BFMOP4A  <ZAda>.H, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_b16b16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4a_za_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81200008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4a_za_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4a_za_zz_h1x1
            IEM_INSTR_IMPL_A64__bfmop4a_za_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81300008: BFMOP4A  <ZAda>.H, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_b16b16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4a_za_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81300008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4a_za_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4a_za_zz_h1x2
            IEM_INSTR_IMPL_A64__bfmop4a_za_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81200208: BFMOP4A  <ZAda>.H, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_b16b16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4a_za_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81200208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4a_za_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4a_za_zz_h2x1
            IEM_INSTR_IMPL_A64__bfmop4a_za_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81300208: BFMOP4A  <ZAda>.H, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_b16b16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4a_za_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81300208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4a_za_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4a_za_zz_h2x2
            IEM_INSTR_IMPL_A64__bfmop4a_za_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81000010: BFMOP4S  <ZAda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_b16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4s_za32_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81000010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4s_za32_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4s_za32_zz_h1x1
            IEM_INSTR_IMPL_A64__bfmop4s_za32_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81100010: BFMOP4S  <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_b16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4s_za32_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81100010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4s_za32_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4s_za32_zz_h1x2
            IEM_INSTR_IMPL_A64__bfmop4s_za32_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81000210: BFMOP4S  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_b16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4s_za32_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81000210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4s_za32_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4s_za32_zz_h2x1
            IEM_INSTR_IMPL_A64__bfmop4s_za32_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81100210: BFMOP4S  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_b16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4s_za32_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81100210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4s_za32_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4s_za32_zz_h2x2
            IEM_INSTR_IMPL_A64__bfmop4s_za32_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81200018: BFMOP4S  <ZAda>.H, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_b16b16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4s_za_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81200018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4s_za_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4s_za_zz_h1x1
            IEM_INSTR_IMPL_A64__bfmop4s_za_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81300018: BFMOP4S  <ZAda>.H, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_b16b16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4s_za_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81300018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4s_za_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4s_za_zz_h1x2
            IEM_INSTR_IMPL_A64__bfmop4s_za_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81200218: BFMOP4S  <ZAda>.H, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_b16b16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4s_za_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81200218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4s_za_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4s_za_zz_h2x1
            IEM_INSTR_IMPL_A64__bfmop4s_za_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81300218: BFMOP4S  <ZAda>.H, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_b16b16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmop4s_za_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81300218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: bfmop4s_za_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__bfmop4s_za_zz_h2x2
            IEM_INSTR_IMPL_A64__bfmop4s_za_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/81800000: BFMOPA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_b16f32_prod, mortlach_32bit_fp_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmopa_za32_pp_zz, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: bfmopa_za32_pp_zz ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmopa_za32_pp_zz
        IEM_INSTR_IMPL_A64__bfmopa_za32_pp_zz(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001e/81a00008: BFMOPA  <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_b16b16_prod, mortlach2_misc_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmopa_za_pp_zz_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001e)) == UINT32_C(0x81a00008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
        {
            LogFlow(("%018x/%010x: bfmopa_za_pp_zz_16 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmopa_za_pp_zz_16
            IEM_INSTR_IMPL_A64__bfmopa_za_pp_zz_16(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/81800010: BFMOPS  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_b16f32_prod, mortlach_32bit_fp_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmops_za32_pp_zz, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: bfmops_za32_pp_zz ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmops_za32_pp_zz
        IEM_INSTR_IMPL_A64__bfmops_za32_pp_zz(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001e/81a00018: BFMOPS  <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_b16b16_prod, mortlach2_misc_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmops_za_pp_zz_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001e)) == UINT32_C(0x81a00018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
        {
            LogFlow(("%018x/%010x: bfmops_za_pp_zz_16 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmops_za_pp_zz_16
            IEM_INSTR_IMPL_A64__bfmops_za_pp_zz_16(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe1fc21/c120e800: BFMUL  { <Zd1>.H-<Zd2>.H }, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_fmul_sm, mortlach_multi_sve_5b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmul_mz_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_BFSCALE*/)
    {
        LogFlow(("%018x/%010x: bfmul_mz_zzv_2x1 Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmul_mz_zzv_2x1
        IEM_INSTR_IMPL_A64__bfmul_mz_zzv_2x1(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe1fc63/c121e800: BFMUL  { <Zd1>.H-<Zd4>.H }, { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_fmul_sm, mortlach_multi_sve_5b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmul_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_BFSCALE*/)
    {
        LogFlow(("%018x/%010x: bfmul_mz_zzv_4x1 Zd=%u Zn=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmul_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__bfmul_mz_zzv_4x1(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe1fc21/c120e400: BFMUL  { <Zd1>.H-<Zd2>.H }, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_fmul_mm, mortlach_multi_sve_5a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmul_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_BFSCALE*/)
    {
        LogFlow(("%018x/%010x: bfmul_mz_zzw_2x2 Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmul_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__bfmul_mz_zzw_2x2(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe3fc63/c121e400: BFMUL  { <Zd1>.H-<Zd4>.H }, { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_fmul_mm, mortlach_multi_sve_5a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfmul_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_BFSCALE*/)
    {
        LogFlow(("%018x/%010x: bfmul_mz_zzw_4x4 Zd=%u Zn=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmul_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__bfmul_mz_zzw_4x4(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65028000: BFMUL  <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmul_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmul_z_p_zz Zdn=%#x Zm=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg));
#ifdef IEM_INSTR_IMPL_A64__bfmul_z_p_zz
        IEM_INSTR_IMPL_A64__bfmul_z_p_zz(Zdn, Zm, Pg);
#else
        RT_NOREF(Zdn, Zm, Pg, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/65000800: BFMUL  <Zd>.H, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_3op_u_zd, sve_fp_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmul_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmul_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfmul_z_zz
        IEM_INSTR_IMPL_A64__bfmul_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/64202800: BFMUL  <Zd>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fmul_by_indexed_elem_lvl2, sve_fp_fmul_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfmul_z_zzi_h, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
    uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfmul_z_zzi_h Zd=%#x Zn=%#x Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__bfmul_z_zzi_h
        IEM_INSTR_IMPL_A64__bfmul_z_zzi_h(Zd, Zn, Zm, i3l, i3h);
#else
        RT_NOREF(Zd, Zn, Zm, i3l, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0ffe1/c120a180: BFSCALE  { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fscale_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfscale_mz_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_BFSCALE*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfscale_mz_zzv_2x1 Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfscale_mz_zzv_2x1
        IEM_INSTR_IMPL_A64__bfscale_mz_zzv_2x1(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0ffe3/c120a980: BFSCALE  { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fscale_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfscale_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_BFSCALE*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfscale_mz_zzv_4x1 Zdn=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfscale_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__bfscale_mz_zzv_4x1(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe1ffe1/c120b180: BFSCALE  { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fscale_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfscale_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_BFSCALE*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfscale_mz_zzw_2x2 Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfscale_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__bfscale_mz_zzw_2x2(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe3ffe3/c120b980: BFSCALE  { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fscale_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfscale_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_BFSCALE*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bfscale_mz_zzw_4x4 Zdn=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfscale_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__bfscale_mz_zzw_4x4(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65098000: BFSCALE  <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfscale_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_BFSCALE*/)
    {
        LogFlow(("%018x/%010x: bfscale_z_p_zz Zdn=%#x Zm=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg));
#ifdef IEM_INSTR_IMPL_A64__bfscale_z_p_zz
        IEM_INSTR_IMPL_A64__bfscale_z_p_zz(Zdn, Zm, Pg);
#else
        RT_NOREF(Zdn, Zm, Pg, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65018000: BFSUB  <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfsub_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfsub_z_p_zz Zdn=%#x Zm=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg));
#ifdef IEM_INSTR_IMPL_A64__bfsub_z_p_zz
        IEM_INSTR_IMPL_A64__bfsub_z_p_zz(Zdn, Zm, Pg);
#else
        RT_NOREF(Zdn, Zm, Pg, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/65000400: BFSUB  <Zd>.H, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_3op_u_zd, sve_fp_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_bfsub_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveB16B16 /*FEAT_SVE_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfsub_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfsub_z_zz
        IEM_INSTR_IMPL_A64__bfsub_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9c38/c1e41c08: BFSUB  ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_f16_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfsub_za_zw_2x2_16, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const Zm         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfsub_za_zw_2x2_16 off3=%u S=%u Zm=%#x Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv));
#ifdef IEM_INSTR_IMPL_A64__bfsub_za_zw_2x2_16
        IEM_INSTR_IMPL_A64__bfsub_za_zw_2x2_16(off3, S, Zm, Rv);
#else
        RT_NOREF(off3, S, Zm, Rv, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9c78/c1e51c08: BFSUB  ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_f16_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfsub_za_zw_4x4_16, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const Zm         = (uOpcode >>  7) & 0x00000007;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/)
    {
        LogFlow(("%018x/%010x: bfsub_za_zw_4x4_16 off3=%u S=%u Zm=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv));
#ifdef IEM_INSTR_IMPL_A64__bfsub_za_zw_4x4_16
        IEM_INSTR_IMPL_A64__bfsub_za_zw_4x4_16(off3, S, Zm, Rv);
#else
        RT_NOREF(off3, S, Zm, Rv, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/81400000: BFTMOPA  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_b16f32_2in4ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_bftmopa_za32_zzzi_h2x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
    uint32_t const K          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
    {
        LogFlow(("%018x/%010x: bftmopa_za32_zzzi_h2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__bftmopa_za32_zzzi_h2x1
        IEM_INSTR_IMPL_A64__bftmopa_za32_zzzi_h2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
        RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00e/81600008: BFTMOPA  <ZAda>.H, { <Zn1>.H-<Zn2>.H }, <Zm>.H, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_b16b16_1in2ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_bftmopa_za_zzzi_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00e)) == UINT32_C(0x81600008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
        uint32_t const K          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_B16B16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
        {
            LogFlow(("%018x/%010x: bftmopa_za_zzzi_h2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__bftmopa_za_zzzi_h2x1
            IEM_INSTR_IMPL_A64__bftmopa_za_zzzi_h2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
            RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1500018: BFVDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_bfvdot_za_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1500018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: bfvdot_za_zzi_2xi off3=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__bfvdot_za_zzi_2xi
            IEM_INSTR_IMPL_A64__bfvdot_za_zzi_2xi(off3, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500b800: BGRP  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_perm_bit, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_bgrp_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500b800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveBitPerm /*FEAT_SVE_BitPerm*/)
        {
            LogFlow(("%018x/%010x: bgrp_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__bgrp_z_zz
            IEM_INSTR_IMPL_A64__bgrp_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25004010: BIC  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_bic_p_p_pp_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25004010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: bic_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__bic_p_p_pp_z
            IEM_INSTR_IMPL_A64__bic_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/041b0000: BIC  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_log, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_bic_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: bic_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__bic_z_p_zz
        IEM_INSTR_IMPL_A64__bic_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04e03000: BIC  <Zd>.D, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_cons_log, sve_int_unpred_logical, sve */
FNIEMOP_DEF_1(iemDecodeA64_bic_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: bic_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__bic_z_zz
        IEM_INSTR_IMPL_A64__bic_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25404010: BICS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_bics_p_p_pp_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25404010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: bics_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__bics_p_p_pp_z
            IEM_INSTR_IMPL_A64__bics_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/80800008: BMOPA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S, <Zm>.S
   Instruction Set: A64  Groups: mortlach_bini32_prod, mortlach2_misc_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_bmopa_za_pp_zz_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bmopa_za_pp_zz_32 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__bmopa_za_pp_zz_32
        IEM_INSTR_IMPL_A64__bmopa_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/80800018: BMOPS  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S, <Zm>.S
   Instruction Set: A64  Groups: mortlach_bini32_prod, mortlach2_misc_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_bmops_za_pp_zz_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: bmops_za_pp_zz_32 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__bmops_za_pp_zz_32
        IEM_INSTR_IMPL_A64__bmops_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffc200/25104000: BRKA  <Pd>.B, <Pg>/<ZM>, <Pn>.B
   Instruction Set: A64  Groups: sve_int_break, sve_pred_gen_c, sve */
FNIEMOP_DEF_1(iemDecodeA64_brka_p_p_p, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffc200)) == UINT32_C(0x25104000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const M          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: brka_p_p_p Pd=%#x M=%u Pn=%#x Pg=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, M, Pn, Pg));
#ifdef IEM_INSTR_IMPL_A64__brka_p_p_p
            IEM_INSTR_IMPL_A64__brka_p_p_p(Pd, M, Pn, Pg);
#else
            RT_NOREF(Pd, M, Pn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffc210/25504000: BRKAS  <Pd>.B, <Pg>/Z, <Pn>.B
   Instruction Set: A64  Groups: sve_int_break, sve_pred_gen_c, sve */
FNIEMOP_DEF_1(iemDecodeA64_brkas_p_p_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffc210)) == UINT32_C(0x25504000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: brkas_p_p_p_z Pd=%#x Pn=%#x Pg=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg));
#ifdef IEM_INSTR_IMPL_A64__brkas_p_p_p_z
            IEM_INSTR_IMPL_A64__brkas_p_p_p_z(Pd, Pn, Pg);
#else
            RT_NOREF(Pd, Pn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffc200/25904000: BRKB  <Pd>.B, <Pg>/<ZM>, <Pn>.B
   Instruction Set: A64  Groups: sve_int_break, sve_pred_gen_c, sve */
FNIEMOP_DEF_1(iemDecodeA64_brkb_p_p_p, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffc200)) == UINT32_C(0x25904000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const M          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: brkb_p_p_p Pd=%#x M=%u Pn=%#x Pg=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, M, Pn, Pg));
#ifdef IEM_INSTR_IMPL_A64__brkb_p_p_p
            IEM_INSTR_IMPL_A64__brkb_p_p_p(Pd, M, Pn, Pg);
#else
            RT_NOREF(Pd, M, Pn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffc210/25d04000: BRKBS  <Pd>.B, <Pg>/Z, <Pn>.B
   Instruction Set: A64  Groups: sve_int_break, sve_pred_gen_c, sve */
FNIEMOP_DEF_1(iemDecodeA64_brkbs_p_p_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffc210)) == UINT32_C(0x25d04000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: brkbs_p_p_p_z Pd=%#x Pn=%#x Pg=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg));
#ifdef IEM_INSTR_IMPL_A64__brkbs_p_p_p_z
            IEM_INSTR_IMPL_A64__brkbs_p_p_p_z(Pd, Pn, Pg);
#else
            RT_NOREF(Pd, Pn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffc210/25184000: BRKN  <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B
   Instruction Set: A64  Groups: sve_int_brkn, sve_pred_gen_c, sve */
FNIEMOP_DEF_1(iemDecodeA64_brkn_p_p_pp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffc210)) == UINT32_C(0x25184000))
    {
        uint32_t const Pdm        = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: brkn_p_p_pp Pdm=%#x Pn=%#x Pg=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pdm, Pn, Pg, S));
#ifdef IEM_INSTR_IMPL_A64__brkn_p_p_pp
            IEM_INSTR_IMPL_A64__brkn_p_p_pp(Pdm, Pn, Pg, S);
#else
            RT_NOREF(Pdm, Pn, Pg, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffc210/25584000: BRKNS  <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B
   Instruction Set: A64  Groups: sve_int_brkn, sve_pred_gen_c, sve */
FNIEMOP_DEF_1(iemDecodeA64_brkns_p_p_pp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffc210)) == UINT32_C(0x25584000))
    {
        uint32_t const Pdm        = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: brkns_p_p_pp Pdm=%#x Pn=%#x Pg=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pdm, Pn, Pg, S));
#ifdef IEM_INSTR_IMPL_A64__brkns_p_p_pp
            IEM_INSTR_IMPL_A64__brkns_p_p_pp(Pdm, Pn, Pg, S);
#else
            RT_NOREF(Pdm, Pn, Pg, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/2500c000: BRKPA  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_brkp, sve_pred_gen_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_brkpa_p_p_pp, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const B          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
    uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const S          = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: brkpa_p_p_pp Pd=%#x B=%u Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, B, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__brkpa_p_p_pp
        IEM_INSTR_IMPL_A64__brkpa_p_p_pp(Pd, B, Pn, Pg, Pm, S);
#else
        RT_NOREF(Pd, B, Pn, Pg, Pm, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/2540c000: BRKPAS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_brkp, sve_pred_gen_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_brkpas_p_p_pp, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const B          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
    uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const S          = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: brkpas_p_p_pp Pd=%#x B=%u Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, B, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__brkpas_p_p_pp
        IEM_INSTR_IMPL_A64__brkpas_p_p_pp(Pd, B, Pn, Pg, Pm, S);
#else
        RT_NOREF(Pd, B, Pn, Pg, Pm, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/2500c010: BRKPB  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_brkp, sve_pred_gen_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_brkpb_p_p_pp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x2500c010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const B          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: brkpb_p_p_pp Pd=%#x B=%u Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, B, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__brkpb_p_p_pp
            IEM_INSTR_IMPL_A64__brkpb_p_p_pp(Pd, B, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, B, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/2540c010: BRKPBS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_brkp, sve_pred_gen_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_brkpbs_p_p_pp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x2540c010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const B          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: brkpbs_p_p_pp Pd=%#x B=%u Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, B, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__brkpbs_p_p_pp
            IEM_INSTR_IMPL_A64__brkpbs_p_p_pp(Pd, B, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, B, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04603c00: BSL1N  <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
   Instruction Set: A64  Groups: sve_int_tern_log, sve_int_unpred_logical, sve */
FNIEMOP_DEF_1(iemDecodeA64_bsl1n_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04603c00))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zk         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: bsl1n_z_zzz Zdn=%#x Zk=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zk, Zm));
#ifdef IEM_INSTR_IMPL_A64__bsl1n_z_zzz
            IEM_INSTR_IMPL_A64__bsl1n_z_zzz(Zdn, Zk, Zm);
#else
            RT_NOREF(Zdn, Zk, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04a03c00: BSL2N  <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
   Instruction Set: A64  Groups: sve_int_tern_log, sve_int_unpred_logical, sve */
FNIEMOP_DEF_1(iemDecodeA64_bsl2n_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04a03c00))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zk         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: bsl2n_z_zzz Zdn=%#x Zk=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zk, Zm));
#ifdef IEM_INSTR_IMPL_A64__bsl2n_z_zzz
            IEM_INSTR_IMPL_A64__bsl2n_z_zzz(Zdn, Zk, Zm);
#else
            RT_NOREF(Zdn, Zk, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04203c00: BSL  <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
   Instruction Set: A64  Groups: sve_int_tern_log, sve_int_unpred_logical, sve */
FNIEMOP_DEF_1(iemDecodeA64_bsl_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zk         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: bsl_z_zzz Zdn=%#x Zk=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zk, Zm));
#ifdef IEM_INSTR_IMPL_A64__bsl_z_zzz
        IEM_INSTR_IMPL_A64__bsl_z_zzz(Zdn, Zk, Zm);
#else
        RT_NOREF(Zdn, Zk, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ff800/4500d800: CADD  <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
   Instruction Set: A64  Groups: sve_intx_cadd, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_cadd_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const rot        = (uOpcode >> 10) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cadd_z_zz Zdn=%#x Zm=%#x rot=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, rot, size));
#ifdef IEM_INSTR_IMPL_A64__cadd_z_zz
        IEM_INSTR_IMPL_A64__cadd_z_zz(Zdn, Zm, rot, size);
#else
        RT_NOREF(Zdn, Zm, rot, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20f000/44001000: CDOT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>, <const>
   Instruction Set: A64  Groups: sve_intx_cdot, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_cdot_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20f000)) == UINT32_C(0x44001000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rot        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cdot_z_zzz Zda=%#x Zn=%#x rot=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, rot, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cdot_z_zzz
            IEM_INSTR_IMPL_A64__cdot_z_zzz(Zda, Zn, rot, Zm, size);
#else
            RT_NOREF(Zda, Zn, rot, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/44e04000: CDOT  <Zda>.D, <Zn>.H, <Zm>.H[<imm>], <const>
   Instruction Set: A64  Groups: sve_intx_cdot_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_cdot_z_zzzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x44e04000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rot        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cdot_z_zzzi_d Zda=%#x Zn=%#x rot=%u Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, rot, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__cdot_z_zzzi_d
            IEM_INSTR_IMPL_A64__cdot_z_zzzi_d(Zda, Zn, rot, Zm, i1);
#else
            RT_NOREF(Zda, Zn, rot, Zm, i1, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/44a04000: CDOT  <Zda>.S, <Zn>.B, <Zm>.B[<imm>], <const>
   Instruction Set: A64  Groups: sve_intx_cdot_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_cdot_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const rot        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cdot_z_zzzi_s Zda=%#x Zn=%#x rot=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, rot, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__cdot_z_zzzi_s
        IEM_INSTR_IMPL_A64__cdot_z_zzzi_s(Zda, Zn, rot, Zm, i2);
#else
        RT_NOREF(Zda, Zn, rot, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0530a000: CLASTA  <R><dn>, <Pg>, <R><dn>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_clast_rz, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_clasta_r_p_z, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const B          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: clasta_r_p_z Rdn=%#x Zm=%#x Pg=%u B=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, Zm, Pg, B, size));
#ifdef IEM_INSTR_IMPL_A64__clasta_r_p_z
        IEM_INSTR_IMPL_A64__clasta_r_p_z(Rdn, Zm, Pg, B, size);
#else
        RT_NOREF(Rdn, Zm, Pg, B, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/052a8000: CLASTA  <V><dn>, <Pg>, <V><dn>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_clast_vz, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_clasta_v_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x052a8000))
    {
        uint32_t const Vdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: clasta_v_p_z Vdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__clasta_v_p_z
            IEM_INSTR_IMPL_A64__clasta_v_p_z(Vdn, Zm, Pg, size);
#else
            RT_NOREF(Vdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/05288000: CLASTA  <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_clast_zz, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_clasta_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x05288000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const B          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: clasta_z_p_zz Zdn=%#x Zm=%#x Pg=%u B=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, B, size));
#ifdef IEM_INSTR_IMPL_A64__clasta_z_p_zz
            IEM_INSTR_IMPL_A64__clasta_z_p_zz(Zdn, Zm, Pg, B, size);
#else
            RT_NOREF(Zdn, Zm, Pg, B, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0531a000: CLASTB  <R><dn>, <Pg>, <R><dn>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_clast_rz, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_clastb_r_p_z, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const B          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: clastb_r_p_z Rdn=%#x Zm=%#x Pg=%u B=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, Zm, Pg, B, size));
#ifdef IEM_INSTR_IMPL_A64__clastb_r_p_z
        IEM_INSTR_IMPL_A64__clastb_r_p_z(Rdn, Zm, Pg, B, size);
#else
        RT_NOREF(Rdn, Zm, Pg, B, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/052b8000: CLASTB  <V><dn>, <Pg>, <V><dn>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_clast_vz, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_clastb_v_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x052b8000))
    {
        uint32_t const Vdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: clastb_v_p_z Vdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__clastb_v_p_z
            IEM_INSTR_IMPL_A64__clastb_v_p_z(Vdn, Zm, Pg, size);
#else
            RT_NOREF(Vdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/05298000: CLASTB  <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_clast_zz, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_clastb_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x05298000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const B          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: clastb_z_p_zz Zdn=%#x Zm=%#x Pg=%u B=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, B, size));
#ifdef IEM_INSTR_IMPL_A64__clastb_z_p_zz
            IEM_INSTR_IMPL_A64__clastb_z_p_zz(Zdn, Zm, Pg, B, size);
#else
            RT_NOREF(Zdn, Zm, Pg, B, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0418a000: CLS  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_cls_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0418a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cls_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__cls_z_p_z_m
            IEM_INSTR_IMPL_A64__cls_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0408a000: CLS  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_cls_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0408a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: cls_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__cls_z_p_z_z
            IEM_INSTR_IMPL_A64__cls_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0419a000: CLZ  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_clz_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0419a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: clz_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__clz_z_p_z_m
            IEM_INSTR_IMPL_A64__clz_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0409a000: CLZ  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_clz_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0409a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: clz_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__clz_z_p_z_z
            IEM_INSTR_IMPL_A64__clz_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20f000/44002000: CMLA  <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
   Instruction Set: A64  Groups: sve_intx_cmla, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmla_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20f000)) == UINT32_C(0x44002000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rot        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cmla_z_zzz Zda=%#x Zn=%#x rot=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, rot, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmla_z_zzz
            IEM_INSTR_IMPL_A64__cmla_z_zzz(Zda, Zn, rot, Zm, size);
#else
            RT_NOREF(Zda, Zn, rot, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/44a06000: CMLA  <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
   Instruction Set: A64  Groups: sve_intx_cmla_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmla_z_zzzi_h, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const rot        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmla_z_zzzi_h Zda=%#x Zn=%#x rot=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, rot, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__cmla_z_zzzi_h
        IEM_INSTR_IMPL_A64__cmla_z_zzzi_h(Zda, Zn, rot, Zm, i2);
#else
        RT_NOREF(Zda, Zn, rot, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/44e06000: CMLA  <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
   Instruction Set: A64  Groups: sve_intx_cmla_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmla_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x44e06000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rot        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cmla_z_zzzi_s Zda=%#x Zn=%#x rot=%u Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, rot, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__cmla_z_zzzi_s
            IEM_INSTR_IMPL_A64__cmla_z_zzzi_s(Zda, Zn, rot, Zm, i1);
#else
            RT_NOREF(Zda, Zn, rot, Zm, i1, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/25008000: CMPEQ  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_scmp_vi, sve_cmpsimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpeq_p_p_zi, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmpeq_p_p_zi Pd=%#x ne=%u Zn=%#x Pg=%u imm5=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, imm5, size));
#ifdef IEM_INSTR_IMPL_A64__cmpeq_p_p_zi
        IEM_INSTR_IMPL_A64__cmpeq_p_p_zi(Pd, ne, Zn, Pg, imm5, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, imm5, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/24002000: CMPEQ  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_cmp_0, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpeq_p_p_zw, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmpeq_p_p_zw Pd=%#x ne=%u Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmpeq_p_p_zw
        IEM_INSTR_IMPL_A64__cmpeq_p_p_zw(Pd, ne, Zn, Pg, Zm, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/2400a000: CMPEQ  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_cmp_0, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpeq_p_p_zz, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmpeq_p_p_zz Pd=%#x ne=%u Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmpeq_p_p_zz
        IEM_INSTR_IMPL_A64__cmpeq_p_p_zz(Pd, ne, Zn, Pg, Zm, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/25000000: CMPGE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_scmp_vi, sve_cmpsimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpge_p_p_zi, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmpge_p_p_zi Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u imm5=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, imm5, size));
#ifdef IEM_INSTR_IMPL_A64__cmpge_p_p_zi
        IEM_INSTR_IMPL_A64__cmpge_p_p_zi(Pd, ne, Zn, Pg, lt, imm5, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, lt, imm5, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/24004000: CMPGE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_cmp_1, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpge_p_p_zw, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmpge_p_p_zw Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmpge_p_p_zw
        IEM_INSTR_IMPL_A64__cmpge_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, lt, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/24008000: CMPGE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_cmp_0, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpge_p_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x24008000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cmpge_p_p_zz Pd=%#x ne=%u Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmpge_p_p_zz
            IEM_INSTR_IMPL_A64__cmpge_p_p_zz(Pd, ne, Zn, Pg, Zm, size);
#else
            RT_NOREF(Pd, ne, Zn, Pg, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/25000010: CMPGT  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_scmp_vi, sve_cmpsimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpgt_p_p_zi, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmpgt_p_p_zi Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u imm5=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, imm5, size));
#ifdef IEM_INSTR_IMPL_A64__cmpgt_p_p_zi
        IEM_INSTR_IMPL_A64__cmpgt_p_p_zi(Pd, ne, Zn, Pg, lt, imm5, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, lt, imm5, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/24004010: CMPGT  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_cmp_1, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpgt_p_p_zw, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x24004010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cmpgt_p_p_zw Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmpgt_p_p_zw
            IEM_INSTR_IMPL_A64__cmpgt_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size);
#else
            RT_NOREF(Pd, ne, Zn, Pg, lt, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/24008010: CMPGT  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_cmp_0, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpgt_p_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x24008010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cmpgt_p_p_zz Pd=%#x ne=%u Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmpgt_p_p_zz
            IEM_INSTR_IMPL_A64__cmpgt_p_p_zz(Pd, ne, Zn, Pg, Zm, size);
#else
            RT_NOREF(Pd, ne, Zn, Pg, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff202010/24200010: CMPHI  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_ucmp_vi, sve_cmpuimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmphi_p_p_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff202010)) == UINT32_C(0x24200010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
        uint32_t const imm7       = (uOpcode >> 14) & 0x0000007f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cmphi_p_p_zi Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u imm7=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, imm7, size));
#ifdef IEM_INSTR_IMPL_A64__cmphi_p_p_zi
            IEM_INSTR_IMPL_A64__cmphi_p_p_zi(Pd, ne, Zn, Pg, lt, imm7, size);
#else
            RT_NOREF(Pd, ne, Zn, Pg, lt, imm7, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/2400c010: CMPHI  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_cmp_1, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmphi_p_p_zw, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x2400c010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cmphi_p_p_zw Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmphi_p_p_zw
            IEM_INSTR_IMPL_A64__cmphi_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size);
#else
            RT_NOREF(Pd, ne, Zn, Pg, lt, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/24000010: CMPHI  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_cmp_0, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmphi_p_p_zz, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmphi_p_p_zz Pd=%#x ne=%u Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmphi_p_p_zz
        IEM_INSTR_IMPL_A64__cmphi_p_p_zz(Pd, ne, Zn, Pg, Zm, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff202010/24200000: CMPHS  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_ucmp_vi, sve_cmpuimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmphs_p_p_zi, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
    uint32_t const imm7       = (uOpcode >> 14) & 0x0000007f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmphs_p_p_zi Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u imm7=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, imm7, size));
#ifdef IEM_INSTR_IMPL_A64__cmphs_p_p_zi
        IEM_INSTR_IMPL_A64__cmphs_p_p_zi(Pd, ne, Zn, Pg, lt, imm7, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, lt, imm7, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/2400c000: CMPHS  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_cmp_1, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmphs_p_p_zw, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmphs_p_p_zw Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmphs_p_p_zw
        IEM_INSTR_IMPL_A64__cmphs_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, lt, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/24000000: CMPHS  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_cmp_0, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmphs_p_p_zz, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmphs_p_p_zz Pd=%#x ne=%u Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmphs_p_p_zz
        IEM_INSTR_IMPL_A64__cmphs_p_p_zz(Pd, ne, Zn, Pg, Zm, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/25002010: CMPLE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_scmp_vi, sve_cmpsimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmple_p_p_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x25002010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cmple_p_p_zi Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u imm5=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, imm5, size));
#ifdef IEM_INSTR_IMPL_A64__cmple_p_p_zi
            IEM_INSTR_IMPL_A64__cmple_p_p_zi(Pd, ne, Zn, Pg, lt, imm5, size);
#else
            RT_NOREF(Pd, ne, Zn, Pg, lt, imm5, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/24006010: CMPLE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_cmp_1, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmple_p_p_zw, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmple_p_p_zw Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmple_p_p_zw
        IEM_INSTR_IMPL_A64__cmple_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, lt, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff202010/24202000: CMPLO  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_ucmp_vi, sve_cmpuimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmplo_p_p_zi, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
    uint32_t const imm7       = (uOpcode >> 14) & 0x0000007f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmplo_p_p_zi Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u imm7=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, imm7, size));
#ifdef IEM_INSTR_IMPL_A64__cmplo_p_p_zi
        IEM_INSTR_IMPL_A64__cmplo_p_p_zi(Pd, ne, Zn, Pg, lt, imm7, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, lt, imm7, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/2400e000: CMPLO  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_cmp_1, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmplo_p_p_zw, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmplo_p_p_zw Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmplo_p_p_zw
        IEM_INSTR_IMPL_A64__cmplo_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, lt, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff202010/24202010: CMPLS  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_ucmp_vi, sve_cmpuimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpls_p_p_zi, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
    uint32_t const imm7       = (uOpcode >> 14) & 0x0000007f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmpls_p_p_zi Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u imm7=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, imm7, size));
#ifdef IEM_INSTR_IMPL_A64__cmpls_p_p_zi
        IEM_INSTR_IMPL_A64__cmpls_p_p_zi(Pd, ne, Zn, Pg, lt, imm7, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, lt, imm7, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/2400e010: CMPLS  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_cmp_1, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpls_p_p_zw, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmpls_p_p_zw Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmpls_p_p_zw
        IEM_INSTR_IMPL_A64__cmpls_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, lt, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/25002000: CMPLT  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_scmp_vi, sve_cmpsimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmplt_p_p_zi, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmplt_p_p_zi Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u imm5=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, imm5, size));
#ifdef IEM_INSTR_IMPL_A64__cmplt_p_p_zi
        IEM_INSTR_IMPL_A64__cmplt_p_p_zi(Pd, ne, Zn, Pg, lt, imm5, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, lt, imm5, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/24006000: CMPLT  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_cmp_1, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmplt_p_p_zw, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const lt         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmplt_p_p_zw Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmplt_p_p_zw
        IEM_INSTR_IMPL_A64__cmplt_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, lt, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/25008010: CMPNE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_scmp_vi, sve_cmpsimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpne_p_p_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x25008010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cmpne_p_p_zi Pd=%#x ne=%u Zn=%#x Pg=%u imm5=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, imm5, size));
#ifdef IEM_INSTR_IMPL_A64__cmpne_p_p_zi
            IEM_INSTR_IMPL_A64__cmpne_p_p_zi(Pd, ne, Zn, Pg, imm5, size);
#else
            RT_NOREF(Pd, ne, Zn, Pg, imm5, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/24002010: CMPNE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_cmp_0, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpne_p_p_zw, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x24002010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cmpne_p_p_zw Pd=%#x ne=%u Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmpne_p_p_zw
            IEM_INSTR_IMPL_A64__cmpne_p_p_zw(Pd, ne, Zn, Pg, Zm, size);
#else
            RT_NOREF(Pd, ne, Zn, Pg, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/2400a010: CMPNE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_cmp_0, sve_cmpvec, sve */
FNIEMOP_DEF_1(iemDecodeA64_cmpne_p_p_zz, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cmpne_p_p_zz Pd=%#x ne=%u Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__cmpne_p_p_zz
        IEM_INSTR_IMPL_A64__cmpne_p_p_zz(Pd, ne, Zn, Pg, Zm, size);
#else
        RT_NOREF(Pd, ne, Zn, Pg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/041ba000: CNOT  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_cnot_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x041ba000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cnot_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__cnot_z_p_z_m
            IEM_INSTR_IMPL_A64__cnot_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040ba000: CNOT  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_cnot_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040ba000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: cnot_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__cnot_z_p_z_z
            IEM_INSTR_IMPL_A64__cnot_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/041aa000: CNT  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_cnt_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x041aa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cnt_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__cnt_z_p_z_m
            IEM_INSTR_IMPL_A64__cnt_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040aa000: CNT  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_cnt_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040aa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: cnt_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__cnt_z_p_z_z
            IEM_INSTR_IMPL_A64__cnt_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0420e000: CNTB  <Xd>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_count, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_cntb_r_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0420e000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cntb_r_s Rd=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__cntb_r_s
            IEM_INSTR_IMPL_A64__cntb_r_s(Rd, pattern, imm4, size);
#else
            RT_NOREF(Rd, pattern, imm4, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04e0e000: CNTD  <Xd>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_count, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_cntd_r_s, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cntd_r_s Rd=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__cntd_r_s
        IEM_INSTR_IMPL_A64__cntd_r_s(Rd, pattern, imm4, size);
#else
        RT_NOREF(Rd, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0460e000: CNTH  <Xd>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_count, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_cnth_r_s, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cnth_r_s Rd=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__cnth_r_s
        IEM_INSTR_IMPL_A64__cnth_r_s(Rd, pattern, imm4, size);
#else
        RT_NOREF(Rd, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fc200/25208000: CNTP  <Xd>, <Pg>, <Pn>.<T>
   Instruction Set: A64  Groups: sve_int_pcount_pred, sve_pred_count_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_cntp_r_p_p, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cntp_r_p_p Rd=%#x Pn=%#x Pg=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Pn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__cntp_r_p_p
        IEM_INSTR_IMPL_A64__cntp_r_p_p(Rd, Pn, Pg, size);
#else
        RT_NOREF(Rd, Pn, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffa00/25208200: CNTP  <Xd>, <PNn>.<T>, <vl>
   Instruction Set: A64  Groups: sve_int_pcount_pn, sve_pred_count_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_cntp_r_pn, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const PNn        = (uOpcode >>  5) & 0x0000000f;
    uint32_t const vl         = (uOpcode >> 10) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: cntp_r_pn Rd=%#x PNn=%#x vl=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, PNn, vl, size));
#ifdef IEM_INSTR_IMPL_A64__cntp_r_pn
        IEM_INSTR_IMPL_A64__cntp_r_pn(Rd, PNn, vl, size);
#else
        RT_NOREF(Rd, PNn, vl, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04a0e000: CNTW  <Xd>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_count, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_cntw_r_s, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cntw_r_s Rd=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__cntw_r_s
        IEM_INSTR_IMPL_A64__cntw_r_s(Rd, pattern, imm4, size);
#else
        RT_NOREF(Rd, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbfe000/05a18000: COMPACT  <Zd>.<T>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_compact, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_compact_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbfe000)) == UINT32_C(0x05a18000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: compact_z_p_z Zd=%#x Zn=%#x Pg=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, sz));
#ifdef IEM_INSTR_IMPL_A64__compact_z_p_z
            IEM_INSTR_IMPL_A64__compact_z_p_z(Zd, Zn, Pg, sz);
#else
            RT_NOREF(Zd, Zn, Pg, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbfe000/05218000: COMPACT  <Zd>.<T>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_compact, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_compact_z_p_z_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbfe000)) == UINT32_C(0x05218000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: compact_z_p_z_s Zd=%#x Zn=%#x Pg=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, sz));
#ifdef IEM_INSTR_IMPL_A64__compact_z_p_z_s
            IEM_INSTR_IMPL_A64__compact_z_p_z_s(Zd, Zn, Pg, sz);
#else
            RT_NOREF(Zd, Zn, Pg, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30c000/05100000: CPY  <Zd>.<T>, <Pg>/Z, #<imm>{, <shift>}
   Instruction Set: A64  Groups: sve_int_dup_imm_pred, sve_wideimm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_cpy_z_o_i, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
    uint32_t const sh         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Pg         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cpy_z_o_i Zd=%#x imm8=%#x sh=%u Pg=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, imm8, sh, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__cpy_z_o_i
        IEM_INSTR_IMPL_A64__cpy_z_o_i(Zd, imm8, sh, Pg, size);
#else
        RT_NOREF(Zd, imm8, sh, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30c000/05104000: CPY  <Zd>.<T>, <Pg>/M, #<imm>{, <shift>}
   Instruction Set: A64  Groups: sve_int_dup_imm_pred, sve_wideimm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_cpy_z_p_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30c000)) == UINT32_C(0x05104000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const sh         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Pg         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cpy_z_p_i Zd=%#x imm8=%#x sh=%u Pg=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, imm8, sh, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__cpy_z_p_i
            IEM_INSTR_IMPL_A64__cpy_z_p_i(Zd, imm8, sh, Pg, size);
#else
            RT_NOREF(Zd, imm8, sh, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0528a000: CPY  <Zd>.<T>, <Pg>/M, <R><n|SP>
   Instruction Set: A64  Groups: sve_int_perm_cpy_r, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_cpy_z_p_r, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0528a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: cpy_z_p_r Zd=%#x Rn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Rn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__cpy_z_p_r
            IEM_INSTR_IMPL_A64__cpy_z_p_r(Zd, Rn, Pg, size);
#else
            RT_NOREF(Zd, Rn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/05208000: CPY  <Zd>.<T>, <Pg>/M, <V><n>
   Instruction Set: A64  Groups: sve_int_perm_cpy_v, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_cpy_z_p_v, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Vn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: cpy_z_p_v Zd=%#x Vn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Vn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__cpy_z_p_v
        IEM_INSTR_IMPL_A64__cpy_z_p_v(Zd, Vn, Pg, size);
#else
        RT_NOREF(Zd, Vn, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc1f/25a02000: CTERMEQ  <R><n>, <R><m>
   Instruction Set: A64  Groups: sve_int_cterm, sve_cmpgpr, sve */
FNIEMOP_DEF_1(iemDecodeA64_ctermeq_rr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc1f)) == UINT32_C(0x25a02000))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ctermeq_rr Rn=%#x Rm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rm, sz));
#ifdef IEM_INSTR_IMPL_A64__ctermeq_rr
            IEM_INSTR_IMPL_A64__ctermeq_rr(Rn, Rm, sz);
#else
            RT_NOREF(Rn, Rm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc1f/25a02010: CTERMNE  <R><n>, <R><m>
   Instruction Set: A64  Groups: sve_int_cterm, sve_cmpgpr, sve */
FNIEMOP_DEF_1(iemDecodeA64_ctermne_rr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc1f)) == UINT32_C(0x25a02010))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ctermne_rr Rn=%#x Rm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn, Rm, sz));
#ifdef IEM_INSTR_IMPL_A64__ctermne_rr
            IEM_INSTR_IMPL_A64__ctermne_rr(Rn, Rm, sz);
#else
            RT_NOREF(Rn, Rm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0430e400: DECB  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_a, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_decb_r_rs, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: decb_r_rs Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__decb_r_rs
        IEM_INSTR_IMPL_A64__decb_r_rs(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04f0e400: DECD  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_a, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_decd_r_rs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04f0e400))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: decd_r_rs Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__decd_r_rs
            IEM_INSTR_IMPL_A64__decd_r_rs(Rdn, pattern, imm4, size);
#else
            RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04f0c400: DECD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv1, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_decd_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: decd_z_zs Zdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__decd_z_zs
        IEM_INSTR_IMPL_A64__decd_z_zs(Zdn, pattern, imm4, size);
#else
        RT_NOREF(Zdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0470e400: DECH  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_a, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_dech_r_rs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0470e400))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: dech_r_rs Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__dech_r_rs
            IEM_INSTR_IMPL_A64__dech_r_rs(Rdn, pattern, imm4, size);
#else
            RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0470c400: DECH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv1, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_dech_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: dech_z_zs Zdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__dech_z_zs
        IEM_INSTR_IMPL_A64__dech_z_zs(Zdn, pattern, imm4, size);
#else
        RT_NOREF(Zdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/252d8800: DECP  <Xdn>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_r, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_decp_r_p_r, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x252d8800))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: decp_r_p_r Rdn=%#x Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__decp_r_p_r
            IEM_INSTR_IMPL_A64__decp_r_p_r(Rdn, Pm, size);
#else
            RT_NOREF(Rdn, Pm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/252d8000: DECP  <Zdn>.<T>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_v, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_decp_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x252d8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: decp_z_p_z Zdn=%#x Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__decp_z_p_z
            IEM_INSTR_IMPL_A64__decp_z_p_z(Zdn, Pm, size);
#else
            RT_NOREF(Zdn, Pm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04b0e400: DECW  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_a, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_decw_r_rs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04b0e400))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: decw_r_rs Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__decw_r_rs
            IEM_INSTR_IMPL_A64__decw_r_rs(Rdn, pattern, imm4, size);
#else
            RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04b0c400: DECW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv1, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_decw_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: decw_z_zs Zdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__decw_z_zs
        IEM_INSTR_IMPL_A64__decw_z_zs(Zdn, pattern, imm4, size);
#else
        RT_NOREF(Zdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fc000/2538c000: DUP  <Zd>.<T>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: sve_int_dup_imm, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_dup_z_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fc000)) == UINT32_C(0x2538c000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const sh         = (uOpcode >> 13) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: dup_z_i Zd=%#x imm8=%#x sh=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, imm8, sh, size));
#ifdef IEM_INSTR_IMPL_A64__dup_z_i
            IEM_INSTR_IMPL_A64__dup_z_i(Zd, imm8, sh, size);
#else
            RT_NOREF(Zd, imm8, sh, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/05203800: DUP  <Zd>.<T>, <R><n|SP>
   Instruction Set: A64  Groups: sve_int_perm_dup_r, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_dup_z_r, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: dup_z_r Zd=%#x Rn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Rn, size));
#ifdef IEM_INSTR_IMPL_A64__dup_z_r
        IEM_INSTR_IMPL_A64__dup_z_r(Zd, Rn, size);
#else
        RT_NOREF(Zd, Rn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/05202000: DUP  <Zd>.<T>, <Zn>.<T>[<imm>]
   Instruction Set: A64  Groups: sve_int_perm_dup_i, sve_perm_unpred_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_dup_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x05202000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const tsz        = (uOpcode >> 16) & 0x0000001f;
        uint32_t const imm2       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: dup_z_zi Zd=%#x Zn=%#x tsz=%#x imm2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, tsz, imm2));
#ifdef IEM_INSTR_IMPL_A64__dup_z_zi
            IEM_INSTR_IMPL_A64__dup_z_zi(Zd, Zn, tsz, imm2);
#else
            RT_NOREF(Zd, Zn, tsz, imm2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0000/05c00000: DUPM  <Zd>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_dup_mask_imm, sve_maskimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_dupm_z_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffc0000)) == UINT32_C(0x05c00000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm13      = (uOpcode >>  5) & 0x00001fff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: dupm_z_i Zd=%#x imm13=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, imm13));
#ifdef IEM_INSTR_IMPL_A64__dupm_z_i
            IEM_INSTR_IMPL_A64__dupm_z_i(Zd, imm13);
#else
            RT_NOREF(Zd, imm13, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/05202400: DUPQ  <Zd>.<T>, <Zn>.<T>[<imm>]
   Instruction Set: A64  Groups: sve_int_perm_dupq_i, sve_perm_quads_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_dupq_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const tsz        = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: dupq_z_zi Zd=%#x Zn=%#x tsz=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, tsz, i1));
#ifdef IEM_INSTR_IMPL_A64__dupq_z_zi
        IEM_INSTR_IMPL_A64__dupq_z_zi(Zd, Zn, tsz, i1);
#else
        RT_NOREF(Zd, Zn, tsz, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04203800: EOR3  <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
   Instruction Set: A64  Groups: sve_int_tern_log, sve_int_unpred_logical, sve */
FNIEMOP_DEF_1(iemDecodeA64_eor3_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zk         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: eor3_z_zzz Zdn=%#x Zk=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zk, Zm));
#ifdef IEM_INSTR_IMPL_A64__eor3_z_zzz
        IEM_INSTR_IMPL_A64__eor3_z_zzz(Zdn, Zk, Zm);
#else
        RT_NOREF(Zdn, Zk, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25004200: EOR  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_eor_p_p_pp_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25004200))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: eor_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__eor_p_p_pp_z
            IEM_INSTR_IMPL_A64__eor_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04190000: EOR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_log, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_eor_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: eor_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__eor_z_p_zz
        IEM_INSTR_IMPL_A64__eor_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0000/05400000: EOR  <Zdn>.<T>, <Zdn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_log_imm, sve_maskimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_eor_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffc0000)) == UINT32_C(0x05400000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm13      = (uOpcode >>  5) & 0x00001fff;
        if (0x1 /*opc@22*/ != 3 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: eor_z_zi Zdn=%#x imm13=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm13));
#ifdef IEM_INSTR_IMPL_A64__eor_z_zi
            IEM_INSTR_IMPL_A64__eor_z_zi(Zdn, imm13);
#else
            RT_NOREF(Zdn, imm13, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04a03000: EOR  <Zd>.D, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_cons_log, sve_int_unpred_logical, sve */
FNIEMOP_DEF_1(iemDecodeA64_eor_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: eor_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__eor_z_zz
        IEM_INSTR_IMPL_A64__eor_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45009000: EORBT  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_eorx, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_eorbt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: eorbt_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__eorbt_z_zz
        IEM_INSTR_IMPL_A64__eorbt_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/041d2000: EORQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_int_reduce_2q, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_eorqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x041d2000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: eorqv_z_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__eorqv_z_p_z
            IEM_INSTR_IMPL_A64__eorqv_z_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25404200: EORS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_eors_p_p_pp_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25404200))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: eors_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__eors_p_p_pp_z
            IEM_INSTR_IMPL_A64__eors_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45009400: EORTB  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_eorx, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_eortb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: eortb_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__eortb_z_zz
        IEM_INSTR_IMPL_A64__eortb_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04192000: EORV  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_reduce_2, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_eorv_r_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04192000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: eorv_r_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__eorv_r_p_z
            IEM_INSTR_IMPL_A64__eorv_r_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/05318000: EXPAND  <Zd>.<T>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_expand, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_expand_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x05318000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: expand_z_p_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__expand_z_p_z
            IEM_INSTR_IMPL_A64__expand_z_p_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/05600000: EXT  <Zd>.B, { <Zn1>.B, <Zn2>.B }, #<imm>
   Instruction Set: A64  Groups: sve_intx_perm_extract_i, sve_perm_extract, sve */
FNIEMOP_DEF_1(iemDecodeA64_ext_z_zi_con, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x05600000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm8l      = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm8h      = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ext_z_zi_con Zd=%#x Zn=%#x imm8l=%u imm8h=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, imm8l, imm8h));
#ifdef IEM_INSTR_IMPL_A64__ext_z_zi_con
            IEM_INSTR_IMPL_A64__ext_z_zi_con(Zd, Zn, imm8l, imm8h);
#else
            RT_NOREF(Zd, Zn, imm8l, imm8h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/05200000: EXT  <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm>
   Instruction Set: A64  Groups: sve_int_perm_extract_i, sve_perm_extract, sve */
FNIEMOP_DEF_1(iemDecodeA64_ext_z_zi_des, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x05200000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm8l      = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm8h      = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ext_z_zi_des Zdn=%#x Zm=%#x imm8l=%u imm8h=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, imm8l, imm8h));
#ifdef IEM_INSTR_IMPL_A64__ext_z_zi_des
            IEM_INSTR_IMPL_A64__ext_z_zi_des(Zdn, Zm, imm8l, imm8h);
#else
            RT_NOREF(Zdn, Zm, imm8l, imm8h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/05602400: EXTQ  <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm>
   Instruction Set: A64  Groups: sve_int_perm_extq, sve_perm_quads_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_extq_z_zi_des, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x05602400))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: extq_z_zi_des Zdn=%#x Zm=%#x imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, imm4));
#ifdef IEM_INSTR_IMPL_A64__extq_z_zi_des
            IEM_INSTR_IMPL_A64__extq_z_zi_des(Zdn, Zm, imm4);
#else
            RT_NOREF(Zdn, Zm, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc01/c126e000: F1CVT  { <Zd1>.H-<Zd2>.H }, <Zn>.B
   Instruction Set: A64  Groups: mortlach_multi2_wide_fp8_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_f1cvt_mz2_z8, uint32_t, uOpcode)
{
    uint32_t const L          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: f1cvt_mz2_z8 L=%u Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, L, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__f1cvt_mz2_z8
        IEM_INSTR_IMPL_A64__f1cvt_mz2_z8(L, Zd, Zn);
#else
        RT_NOREF(L, Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/65083000: F1CVT  <Zd>.H, <Zn>.B
   Instruction Set: A64  Groups: sve_fp8_fcvt_wide, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_f1cvt_z_z8_b2h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x65083000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const L          = (uOpcode >> 16) & 0x00000001;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
        {
            LogFlow(("%018x/%010x: f1cvt_z_z8_b2h Zd=%#x Zn=%#x L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, L));
#ifdef IEM_INSTR_IMPL_A64__f1cvt_z_z8_b2h
            IEM_INSTR_IMPL_A64__f1cvt_z_z8_b2h(Zd, Zn, L);
#else
            RT_NOREF(Zd, Zn, L, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc01/c126e001: F1CVTL  { <Zd1>.H-<Zd2>.H }, <Zn>.B
   Instruction Set: A64  Groups: mortlach_multi2_wide_fp8_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_f1cvtl_mz2_z8, uint32_t, uOpcode)
{
    uint32_t const L          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: f1cvtl_mz2_z8 L=%u Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, L, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__f1cvtl_mz2_z8
        IEM_INSTR_IMPL_A64__f1cvtl_mz2_z8(L, Zd, Zn);
#else
        RT_NOREF(L, Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/65093000: F1CVTLT  <Zd>.H, <Zn>.B
   Instruction Set: A64  Groups: sve_fp8_fcvt_wide, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_f1cvtlt_z_z8_b2h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x65093000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const L          = (uOpcode >> 16) & 0x00000001;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
        {
            LogFlow(("%018x/%010x: f1cvtlt_z_z8_b2h Zd=%#x Zn=%#x L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, L));
#ifdef IEM_INSTR_IMPL_A64__f1cvtlt_z_z8_b2h
            IEM_INSTR_IMPL_A64__f1cvtlt_z_z8_b2h(Zd, Zn, L);
#else
            RT_NOREF(Zd, Zn, L, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc01/c1a6e000: F2CVT  { <Zd1>.H-<Zd2>.H }, <Zn>.B
   Instruction Set: A64  Groups: mortlach_multi2_wide_fp8_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_f2cvt_mz2_z8, uint32_t, uOpcode)
{
    uint32_t const L          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: f2cvt_mz2_z8 L=%u Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, L, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__f2cvt_mz2_z8
        IEM_INSTR_IMPL_A64__f2cvt_mz2_z8(L, Zd, Zn);
#else
        RT_NOREF(L, Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/65083400: F2CVT  <Zd>.H, <Zn>.B
   Instruction Set: A64  Groups: sve_fp8_fcvt_wide, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_f2cvt_z_z8_b2h, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const L          = (uOpcode >> 16) & 0x00000001;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: f2cvt_z_z8_b2h Zd=%#x Zn=%#x L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, L));
#ifdef IEM_INSTR_IMPL_A64__f2cvt_z_z8_b2h
        IEM_INSTR_IMPL_A64__f2cvt_z_z8_b2h(Zd, Zn, L);
#else
        RT_NOREF(Zd, Zn, L, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc01/c1a6e001: F2CVTL  { <Zd1>.H-<Zd2>.H }, <Zn>.B
   Instruction Set: A64  Groups: mortlach_multi2_wide_fp8_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_f2cvtl_mz2_z8, uint32_t, uOpcode)
{
    uint32_t const L          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: f2cvtl_mz2_z8 L=%u Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, L, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__f2cvtl_mz2_z8
        IEM_INSTR_IMPL_A64__f2cvtl_mz2_z8(L, Zd, Zn);
#else
        RT_NOREF(L, Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/65093400: F2CVTLT  <Zd>.H, <Zn>.B
   Instruction Set: A64  Groups: sve_fp8_fcvt_wide, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_f2cvtlt_z_z8_b2h, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const L          = (uOpcode >> 16) & 0x00000001;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: f2cvtlt_z_z8_b2h Zd=%#x Zn=%#x L=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, L));
#ifdef IEM_INSTR_IMPL_A64__f2cvtlt_z_z8_b2h
        IEM_INSTR_IMPL_A64__f2cvtlt_z_z8_b2h(Zd, Zn, L);
#else
        RT_NOREF(Zd, Zn, L, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65088000: FABD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fabd_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65088000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fabd_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fabd_z_p_zz
            IEM_INSTR_IMPL_A64__fabd_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/041ca000: FABS  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_fabs_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x041ca000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fabs_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fabs_z_p_z_m
            IEM_INSTR_IMPL_A64__fabs_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040ca000: FABS  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_fabs_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040ca000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fabs_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fabs_z_p_z_z
            IEM_INSTR_IMPL_A64__fabs_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/6500c010: FACGE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_pd, sve_fp_cmpvev, sve */
FNIEMOP_DEF_1(iemDecodeA64_facge_p_p_zz, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: facge_p_p_zz Pd=%#x Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__facge_p_p_zz
        IEM_INSTR_IMPL_A64__facge_p_p_zz(Pd, Zn, Pg, Zm, size);
#else
        RT_NOREF(Pd, Zn, Pg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/6500e010: FACGT  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_pd, sve_fp_cmpvev, sve */
FNIEMOP_DEF_1(iemDecodeA64_facgt_p_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x6500e010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: facgt_p_p_zz Pd=%#x Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__facgt_p_p_zz
            IEM_INSTR_IMPL_A64__facgt_p_p_zz(Pd, Zn, Pg, Zm, size);
#else
            RT_NOREF(Pd, Zn, Pg, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe3c0/65188000: FADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
   Instruction Set: A64  Groups: sve_fp_2op_i_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fadd_z_p_zs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe3c0)) == UINT32_C(0x65188000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const i1         = (uOpcode >>  5) & 0x00000001;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fadd_z_p_zs Zdn=%#x i1=%u Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, i1, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fadd_z_p_zs
            IEM_INSTR_IMPL_A64__fadd_z_p_zs(Zdn, i1, Pg, size);
#else
            RT_NOREF(Zdn, i1, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65008000: FADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fadd_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fadd_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fadd_z_p_zz
        IEM_INSTR_IMPL_A64__fadd_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/65000000: FADD  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_u_zd, sve_fp_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fadd_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fadd_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fadd_z_zz
        IEM_INSTR_IMPL_A64__fadd_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbf9c38/c1a01c00: FADD  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_float_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fadd_za_zw_2x2, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const Zm         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fadd_za_zw_2x2 off3=%u S=%u Zm=%#x Rv=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv, sz));
#ifdef IEM_INSTR_IMPL_A64__fadd_za_zw_2x2
        IEM_INSTR_IMPL_A64__fadd_za_zw_2x2(off3, S, Zm, Rv, sz);
#else
        RT_NOREF(off3, S, Zm, Rv, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9c38/c1a41c00: FADD  ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_f16_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fadd_za_zw_2x2_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9c38)) == UINT32_C(0xc1a41c00))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zm         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fadd_za_zw_2x2_16 off3=%u S=%u Zm=%#x Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv));
#ifdef IEM_INSTR_IMPL_A64__fadd_za_zw_2x2_16
            IEM_INSTR_IMPL_A64__fadd_za_zw_2x2_16(off3, S, Zm, Rv);
#else
            RT_NOREF(off3, S, Zm, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbf9c78/c1a11c00: FADD  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_float_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fadd_za_zw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbf9c78)) == UINT32_C(0xc1a11c00))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zm         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fadd_za_zw_4x4 off3=%u S=%u Zm=%u Rv=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv, sz));
#ifdef IEM_INSTR_IMPL_A64__fadd_za_zw_4x4
            IEM_INSTR_IMPL_A64__fadd_za_zw_4x4(off3, S, Zm, Rv, sz);
#else
            RT_NOREF(off3, S, Zm, Rv, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9c78/c1a51c00: FADD  ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_f16_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fadd_za_zw_4x4_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9c78)) == UINT32_C(0xc1a51c00))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zm         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fadd_za_zw_4x4_16 off3=%u S=%u Zm=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv));
#ifdef IEM_INSTR_IMPL_A64__fadd_za_zw_4x4_16
            IEM_INSTR_IMPL_A64__fadd_za_zw_4x4_16(off3, S, Zm, Rv);
#else
            RT_NOREF(off3, S, Zm, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65182000: FADDA  <V><dn>, <Pg>, <V><dn>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_vd, sve_fp_slowreduce, sve */
FNIEMOP_DEF_1(iemDecodeA64_fadda_v_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65182000))
    {
        uint32_t const Vdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: fadda_v_p_z Vdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fadda_v_p_z
            IEM_INSTR_IMPL_A64__fadda_v_p_z(Vdn, Zm, Pg, size);
#else
            RT_NOREF(Vdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/64108000: FADDP  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_pairwise_lvl2, sve_fp_pairwise, sve */
FNIEMOP_DEF_1(iemDecodeA64_faddp_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x64108000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: faddp_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__faddp_z_p_zz
            IEM_INSTR_IMPL_A64__faddp_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6410a000: FADDQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_fp_fast_redq, sve_fp_fastreduceq, sve */
FNIEMOP_DEF_1(iemDecodeA64_faddqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6410a000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: faddqv_z_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__faddqv_z_p_z
            IEM_INSTR_IMPL_A64__faddqv_z_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65002000: FADDV  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_fast_red, sve_fp_fastreduce, sve */
FNIEMOP_DEF_1(iemDecodeA64_faddv_v_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65002000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: faddv_v_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__faddv_v_p_z
            IEM_INSTR_IMPL_A64__faddv_v_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b140: FAMAX  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_famax_mz_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b140))
    {
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FAMINMAX*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: famax_mz_zzw_2x2 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__famax_mz_zzw_2x2
            IEM_INSTR_IMPL_A64__famax_mz_zzw_2x2(Zdn, Zm, size);
#else
            RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120b940: FAMAX  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_famax_mz_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120b940))
    {
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FAMINMAX*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: famax_mz_zzw_4x4 Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__famax_mz_zzw_4x4
            IEM_INSTR_IMPL_A64__famax_mz_zzw_4x4(Zdn, Zm, size);
#else
            RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/650e8000: FAMAX  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_famax_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x650e8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FAMINMAX*/)
        {
            LogFlow(("%018x/%010x: famax_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__famax_z_p_zz
            IEM_INSTR_IMPL_A64__famax_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b141: FAMIN  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_famin_mz_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b141))
    {
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FAMINMAX*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: famin_mz_zzw_2x2 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__famin_mz_zzw_2x2
            IEM_INSTR_IMPL_A64__famin_mz_zzw_2x2(Zdn, Zm, size);
#else
            RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120b941: FAMIN  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_famin_mz_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120b941))
    {
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FAMINMAX*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: famin_mz_zzw_4x4 Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__famin_mz_zzw_4x4
            IEM_INSTR_IMPL_A64__famin_mz_zzw_4x4(Zdn, Zm, size);
#else
            RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/650f8000: FAMIN  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_famin_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x650f8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FAMINMAX*/)
        {
            LogFlow(("%018x/%010x: famin_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__famin_z_p_zz
            IEM_INSTR_IMPL_A64__famin_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ee000/64008000: FCADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, <const>
   Instruction Set: A64  Groups: sve_fp_fcadd_lvl2, sve_fp_fcadd, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcadd_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const rot        = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fcadd_z_p_zz Zdn=%#x Zm=%#x Pg=%u rot=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, rot, size));
#ifdef IEM_INSTR_IMPL_A64__fcadd_z_p_zz
        IEM_INSTR_IMPL_A64__fcadd_z_p_zz(Zdn, Zm, Pg, rot, size);
#else
        RT_NOREF(Zdn, Zm, Pg, rot, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc01/c120c000: FCLAMP  { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_fclamp, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fclamp_mz_zz_2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fclamp_mz_zz_2 Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fclamp_mz_zz_2
        IEM_INSTR_IMPL_A64__fclamp_mz_zz_2(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc03/c120c800: FCLAMP  { <Zd1>.<T>-<Zd4>.<T> }, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_fclamp, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fclamp_mz_zz_4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fclamp_mz_zz_4 Zd=%u Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fclamp_mz_zz_4
        IEM_INSTR_IMPL_A64__fclamp_mz_zz_4(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/64202400: FCLAMP  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_clamp_lvl2, sve_fp_clamp, sve */
FNIEMOP_DEF_1(iemDecodeA64_fclamp_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fclamp_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fclamp_z_zz
        IEM_INSTR_IMPL_A64__fclamp_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe010/65122000: FCMEQ  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
   Instruction Set: A64  Groups: sve_fp_2op_p_pd, sve_fp_cmpzero, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmeq_p_p_z0, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe010)) == UINT32_C(0x65122000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const lt         = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcmeq_p_p_z0 Pd=%#x Zn=%#x Pg=%u lt=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Zn, Pg, lt, size));
#ifdef IEM_INSTR_IMPL_A64__fcmeq_p_p_z0
            IEM_INSTR_IMPL_A64__fcmeq_p_p_z0(Pd, Zn, Pg, lt, size);
#else
            RT_NOREF(Pd, Zn, Pg, lt, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/65006000: FCMEQ  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_pd, sve_fp_cmpvev, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmeq_p_p_zz, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const cmpl       = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const cmph       = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fcmeq_p_p_zz Pd=%#x cmpl=%u Zn=%#x Pg=%u cmph=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, cmpl, Zn, Pg, cmph, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fcmeq_p_p_zz
        IEM_INSTR_IMPL_A64__fcmeq_p_p_zz(Pd, cmpl, Zn, Pg, cmph, Zm, size);
#else
        RT_NOREF(Pd, cmpl, Zn, Pg, cmph, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe010/65102000: FCMGE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
   Instruction Set: A64  Groups: sve_fp_2op_p_pd, sve_fp_cmpzero, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmge_p_p_z0, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe010)) == UINT32_C(0x65102000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const lt         = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcmge_p_p_z0 Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, size));
#ifdef IEM_INSTR_IMPL_A64__fcmge_p_p_z0
            IEM_INSTR_IMPL_A64__fcmge_p_p_z0(Pd, ne, Zn, Pg, lt, size);
#else
            RT_NOREF(Pd, ne, Zn, Pg, lt, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/65004000: FCMGE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_pd, sve_fp_cmpvev, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmge_p_p_zz, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const cmpl       = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const cmph       = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fcmge_p_p_zz Pd=%#x cmpl=%u Zn=%#x Pg=%u cmph=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, cmpl, Zn, Pg, cmph, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fcmge_p_p_zz
        IEM_INSTR_IMPL_A64__fcmge_p_p_zz(Pd, cmpl, Zn, Pg, cmph, Zm, size);
#else
        RT_NOREF(Pd, cmpl, Zn, Pg, cmph, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe010/65102010: FCMGT  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
   Instruction Set: A64  Groups: sve_fp_2op_p_pd, sve_fp_cmpzero, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmgt_p_p_z0, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe010)) == UINT32_C(0x65102010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const lt         = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcmgt_p_p_z0 Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, size));
#ifdef IEM_INSTR_IMPL_A64__fcmgt_p_p_z0
            IEM_INSTR_IMPL_A64__fcmgt_p_p_z0(Pd, ne, Zn, Pg, lt, size);
#else
            RT_NOREF(Pd, ne, Zn, Pg, lt, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/65004010: FCMGT  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_pd, sve_fp_cmpvev, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmgt_p_p_zz, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const cmpl       = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const cmph       = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fcmgt_p_p_zz Pd=%#x cmpl=%u Zn=%#x Pg=%u cmph=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, cmpl, Zn, Pg, cmph, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fcmgt_p_p_zz
        IEM_INSTR_IMPL_A64__fcmgt_p_p_zz(Pd, cmpl, Zn, Pg, cmph, Zm, size);
#else
        RT_NOREF(Pd, cmpl, Zn, Pg, cmph, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff208000/64000000: FCMLA  <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, <const>
   Instruction Set: A64  Groups: sve_fp_fcmla_lvl2, sve_fp_fcmla, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmla_z_p_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const rot        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fcmla_z_p_zzz Zda=%#x Zn=%#x Pg=%u rot=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Pg, rot, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fcmla_z_p_zzz
        IEM_INSTR_IMPL_A64__fcmla_z_p_zzz(Zda, Zn, Pg, rot, Zm, size);
#else
        RT_NOREF(Zda, Zn, Pg, rot, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/64a01000: FCMLA  <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
   Instruction Set: A64  Groups: sve_fp_fcmla_by_indexed_elem_lvl2, sve_fp_fcmla_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmla_z_zzzi_h, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const rot        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fcmla_z_zzzi_h Zda=%#x Zn=%#x rot=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, rot, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__fcmla_z_zzzi_h
        IEM_INSTR_IMPL_A64__fcmla_z_zzzi_h(Zda, Zn, rot, Zm, i2);
#else
        RT_NOREF(Zda, Zn, rot, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/64e01000: FCMLA  <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
   Instruction Set: A64  Groups: sve_fp_fcmla_by_indexed_elem_lvl2, sve_fp_fcmla_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmla_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const rot        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fcmla_z_zzzi_s Zda=%#x Zn=%#x rot=%u Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, rot, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__fcmla_z_zzzi_s
        IEM_INSTR_IMPL_A64__fcmla_z_zzzi_s(Zda, Zn, rot, Zm, i1);
#else
        RT_NOREF(Zda, Zn, rot, Zm, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe010/65112010: FCMLE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
   Instruction Set: A64  Groups: sve_fp_2op_p_pd, sve_fp_cmpzero, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmle_p_p_z0, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe010)) == UINT32_C(0x65112010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const lt         = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcmle_p_p_z0 Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, size));
#ifdef IEM_INSTR_IMPL_A64__fcmle_p_p_z0
            IEM_INSTR_IMPL_A64__fcmle_p_p_z0(Pd, ne, Zn, Pg, lt, size);
#else
            RT_NOREF(Pd, ne, Zn, Pg, lt, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe010/65112000: FCMLT  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
   Instruction Set: A64  Groups: sve_fp_2op_p_pd, sve_fp_cmpzero, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmlt_p_p_z0, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe010)) == UINT32_C(0x65112000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const ne         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const lt         = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcmlt_p_p_z0 Pd=%#x ne=%u Zn=%#x Pg=%u lt=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, ne, Zn, Pg, lt, size));
#ifdef IEM_INSTR_IMPL_A64__fcmlt_p_p_z0
            IEM_INSTR_IMPL_A64__fcmlt_p_p_z0(Pd, ne, Zn, Pg, lt, size);
#else
            RT_NOREF(Pd, ne, Zn, Pg, lt, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe010/65132000: FCMNE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
   Instruction Set: A64  Groups: sve_fp_2op_p_pd, sve_fp_cmpzero, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmne_p_p_z0, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe010)) == UINT32_C(0x65132000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const lt         = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcmne_p_p_z0 Pd=%#x Zn=%#x Pg=%u lt=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Zn, Pg, lt, size));
#ifdef IEM_INSTR_IMPL_A64__fcmne_p_p_z0
            IEM_INSTR_IMPL_A64__fcmne_p_p_z0(Pd, Zn, Pg, lt, size);
#else
            RT_NOREF(Pd, Zn, Pg, lt, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/65006010: FCMNE  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_pd, sve_fp_cmpvev, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmne_p_p_zz, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const cmpl       = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const cmph       = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fcmne_p_p_zz Pd=%#x cmpl=%u Zn=%#x Pg=%u cmph=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, cmpl, Zn, Pg, cmph, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fcmne_p_p_zz
        IEM_INSTR_IMPL_A64__fcmne_p_p_zz(Pd, cmpl, Zn, Pg, cmph, Zm, size);
#else
        RT_NOREF(Pd, cmpl, Zn, Pg, cmph, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/6500c000: FCMUO  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_pd, sve_fp_cmpvev, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcmuo_p_p_zz, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fcmuo_p_p_zz Pd=%#x Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fcmuo_p_p_zz
        IEM_INSTR_IMPL_A64__fcmuo_p_p_zz(Pd, Zn, Pg, Zm, size);
#else
        RT_NOREF(Pd, Zn, Pg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30e000/0510c000: FCPY  <Zd>.<T>, <Pg>/M, #<const>
   Instruction Set: A64  Groups: sve_int_dup_fpimm_pred, sve_wideimm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcpy_z_p_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30e000)) == UINT32_C(0x0510c000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const Pg         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcpy_z_p_i Zd=%#x imm8=%#x Pg=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, imm8, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fcpy_z_p_i
            IEM_INSTR_IMPL_A64__fcpy_z_p_i(Zd, imm8, Pg, size);
#else
            RT_NOREF(Zd, imm8, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc01/c1a0e000: FCVT  { <Zd1>.S-<Zd2>.S }, <Zn>.H
   Instruction Set: A64  Groups: mortlach_multi2_wide_fp_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_mz2_z, uint32_t, uOpcode)
{
    uint32_t const L          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
    {
        LogFlow(("%018x/%010x: fcvt_mz2_z L=%u Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, L, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__fcvt_mz2_z
        IEM_INSTR_IMPL_A64__fcvt_mz2_z(L, Zd, Zn);
#else
        RT_NOREF(L, Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/c124e000: FCVT  <Zd>.B, { <Zn1>.H-<Zn2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_narrow_fp8_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z8_mz2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0xc124e000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
        {
            LogFlow(("%018x/%010x: fcvt_z8_mz2 Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z8_mz2
            IEM_INSTR_IMPL_A64__fcvt_z8_mz2(Zd, Zn);
#else
            RT_NOREF(Zd, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc60/c134e000: FCVT  <Zd>.B, { <Zn1>.S-<Zn4>.S }
   Instruction Set: A64  Groups: mortlach_multi4_narrow_fp8_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z8_mz4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc60)) == UINT32_C(0xc134e000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const N          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
        {
            LogFlow(("%018x/%010x: fcvt_z8_mz4 Zd=%#x N=%u Zn=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, N, Zn));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z8_mz4
            IEM_INSTR_IMPL_A64__fcvt_z8_mz4(Zd, N, Zn);
#else
            RT_NOREF(Zd, N, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/c120e000: FCVT  <Zd>.H, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_narrow_fp_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_mz2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const N          = (uOpcode >>  5) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fcvt_z_mz2 Zd=%#x N=%u Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, N, Zn));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_mz2
        IEM_INSTR_IMPL_A64__fcvt_z_mz2(Zd, N, Zn);
#else
        RT_NOREF(Zd, N, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65c8a000: FCVT  <Zd>.H, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_b_0, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_p_z_d2h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65c8a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvt_z_p_z_d2h Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_p_z_d2h
            IEM_INSTR_IMPL_A64__fcvt_z_p_z_d2h(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64da8000: FCVT  <Zd>.H, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_b_0, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_p_z_d2hz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64da8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvt_z_p_z_d2hz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_p_z_d2hz
            IEM_INSTR_IMPL_A64__fcvt_z_p_z_d2hz(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65caa000: FCVT  <Zd>.S, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_b_0, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_p_z_d2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65caa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvt_z_p_z_d2s Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_p_z_d2s
            IEM_INSTR_IMPL_A64__fcvt_z_p_z_d2s(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64dac000: FCVT  <Zd>.S, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_b_0, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_p_z_d2sz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
    {
        LogFlow(("%018x/%010x: fcvt_z_p_z_d2sz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_p_z_d2sz
        IEM_INSTR_IMPL_A64__fcvt_z_p_z_d2sz(Zd, Zn, Pg);
#else
        RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65c9a000: FCVT  <Zd>.D, <Pg>/M, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_b_0, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_p_z_h2d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65c9a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvt_z_p_z_h2d Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_p_z_h2d
            IEM_INSTR_IMPL_A64__fcvt_z_p_z_h2d(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64daa000: FCVT  <Zd>.D, <Pg>/Z, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_b_0, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_p_z_h2dz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64daa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvt_z_p_z_h2dz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_p_z_h2dz
            IEM_INSTR_IMPL_A64__fcvt_z_p_z_h2dz(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6589a000: FCVT  <Zd>.S, <Pg>/M, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_b_0, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_p_z_h2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6589a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvt_z_p_z_h2s Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_p_z_h2s
            IEM_INSTR_IMPL_A64__fcvt_z_p_z_h2s(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/649aa000: FCVT  <Zd>.S, <Pg>/Z, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_b_0, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_p_z_h2sz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x649aa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvt_z_p_z_h2sz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_p_z_h2sz
            IEM_INSTR_IMPL_A64__fcvt_z_p_z_h2sz(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65cba000: FCVT  <Zd>.D, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_b_0, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_p_z_s2d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65cba000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvt_z_p_z_s2d Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_p_z_s2d
            IEM_INSTR_IMPL_A64__fcvt_z_p_z_s2d(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64dae000: FCVT  <Zd>.D, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_b_0, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_p_z_s2dz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64dae000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvt_z_p_z_s2dz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_p_z_s2dz
            IEM_INSTR_IMPL_A64__fcvt_z_p_z_s2dz(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6588a000: FCVT  <Zd>.H, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_b_0, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_p_z_s2h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6588a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvt_z_p_z_s2h Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_p_z_s2h
            IEM_INSTR_IMPL_A64__fcvt_z_p_z_s2h(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/649a8000: FCVT  <Zd>.H, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_b_0, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvt_z_p_z_s2hz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x649a8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvt_z_p_z_s2hz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvt_z_p_z_s2hz
            IEM_INSTR_IMPL_A64__fcvt_z_p_z_s2hz(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc01/c1a0e001: FCVTL  { <Zd1>.S-<Zd2>.S }, <Zn>.H
   Instruction Set: A64  Groups: mortlach_multi2_wide_fp_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fcvtl_mz2_z, uint32_t, uOpcode)
{
    uint32_t const L          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
    {
        LogFlow(("%018x/%010x: fcvtl_mz2_z L=%u Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, L, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__fcvtl_mz2_z
        IEM_INSTR_IMPL_A64__fcvtl_mz2_z(L, Zd, Zn);
#else
        RT_NOREF(L, Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6489a000: FCVTLT  <Zd>.S, <Pg>/M, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_fcvt2_lvl2, sve_fp_fcvt2, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtlt_z_p_z_h2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6489a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtlt_z_p_z_h2s Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvtlt_z_p_z_h2s
            IEM_INSTR_IMPL_A64__fcvtlt_z_p_z_h2s(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6481a000: FCVTLT  <Zd>.S, <Pg>/Z, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_fcvt2z_lvl2, sve_fp_fcvt2z, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtlt_z_p_z_h2sz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6481a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtlt_z_p_z_h2sz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvtlt_z_p_z_h2sz
            IEM_INSTR_IMPL_A64__fcvtlt_z_p_z_h2sz(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64cba000: FCVTLT  <Zd>.D, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_fcvt2_lvl2, sve_fp_fcvt2, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtlt_z_p_z_s2d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64cba000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtlt_z_p_z_s2d Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvtlt_z_p_z_s2d
            IEM_INSTR_IMPL_A64__fcvtlt_z_p_z_s2d(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64c3a000: FCVTLT  <Zd>.D, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_fcvt2z_lvl2, sve_fp_fcvt2z, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtlt_z_p_z_s2dz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64c3a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtlt_z_p_z_s2dz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvtlt_z_p_z_s2dz
            IEM_INSTR_IMPL_A64__fcvtlt_z_p_z_s2dz(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/650a3000: FCVTN  <Zd>.B, { <Zn1>.H-<Zn2>.H }
   Instruction Set: A64  Groups: sve_fp8_fcvt_narrow, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtn_z8_mz2_h2b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0x650a3000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
        {
            LogFlow(("%018x/%010x: fcvtn_z8_mz2_h2b Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__fcvtn_z8_mz2_h2b
            IEM_INSTR_IMPL_A64__fcvtn_z8_mz2_h2b(Zd, Zn);
#else
            RT_NOREF(Zd, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc60/c134e020: FCVTN  <Zd>.B, { <Zn1>.S-<Zn4>.S }
   Instruction Set: A64  Groups: mortlach_multi4_narrow_fp8_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fcvtn_z8_mz4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc60)) == UINT32_C(0xc134e020))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const N          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
        {
            LogFlow(("%018x/%010x: fcvtn_z8_mz4 Zd=%#x N=%u Zn=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, N, Zn));
#ifdef IEM_INSTR_IMPL_A64__fcvtn_z8_mz4
            IEM_INSTR_IMPL_A64__fcvtn_z8_mz4(Zd, N, Zn);
#else
            RT_NOREF(Zd, N, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/c120e020: FCVTN  <Zd>.H, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_narrow_fp_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fcvtn_z_mz2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0xc120e020))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const N          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fcvtn_z_mz2 Zd=%#x N=%u Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, N, Zn));
#ifdef IEM_INSTR_IMPL_A64__fcvtn_z_mz2
            IEM_INSTR_IMPL_A64__fcvtn_z_mz2(Zd, N, Zn);
#else
            RT_NOREF(Zd, N, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/650a3400: FCVTNB  <Zd>.B, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: sve_fp8_fcvt_narrow, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtnb_z8_mz2_s2b, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const T          = (uOpcode >> 11) & 0x00000001;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: fcvtnb_z8_mz2_s2b Zd=%#x Zn=%#x T=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T));
#ifdef IEM_INSTR_IMPL_A64__fcvtnb_z8_mz2_s2b
        IEM_INSTR_IMPL_A64__fcvtnb_z8_mz2_s2b(Zd, Zn, T);
#else
        RT_NOREF(Zd, Zn, T, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/650a3c00: FCVTNT  <Zd>.B, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: sve_fp8_fcvt_narrow, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtnt_z8_mz2_s2b, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const T          = (uOpcode >> 11) & 0x00000001;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/)
    {
        LogFlow(("%018x/%010x: fcvtnt_z8_mz2_s2b Zd=%#x Zn=%#x T=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T));
#ifdef IEM_INSTR_IMPL_A64__fcvtnt_z8_mz2_s2b
        IEM_INSTR_IMPL_A64__fcvtnt_z8_mz2_s2b(Zd, Zn, T);
#else
        RT_NOREF(Zd, Zn, T, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64caa000: FCVTNT  <Zd>.S, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_fcvt2_lvl2, sve_fp_fcvt2, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtnt_z_p_z_d2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64caa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtnt_z_p_z_d2s Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvtnt_z_p_z_d2s
            IEM_INSTR_IMPL_A64__fcvtnt_z_p_z_d2s(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64c2a000: FCVTNT  <Zd>.S, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_fcvt2z_lvl2, sve_fp_fcvt2z, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtnt_z_p_z_d2sz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64c2a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtnt_z_p_z_d2sz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvtnt_z_p_z_d2sz
            IEM_INSTR_IMPL_A64__fcvtnt_z_p_z_d2sz(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6488a000: FCVTNT  <Zd>.H, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_fcvt2_lvl2, sve_fp_fcvt2, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtnt_z_p_z_s2h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6488a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtnt_z_p_z_s2h Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvtnt_z_p_z_s2h
            IEM_INSTR_IMPL_A64__fcvtnt_z_p_z_s2h(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6480a000: FCVTNT  <Zd>.H, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_fcvt2z_lvl2, sve_fp_fcvt2z, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtnt_z_p_z_s2hz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
    {
        LogFlow(("%018x/%010x: fcvtnt_z_p_z_s2hz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvtnt_z_p_z_s2hz
        IEM_INSTR_IMPL_A64__fcvtnt_z_p_z_s2hz(Zd, Zn, Pg);
#else
        RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/650aa000: FCVTX  <Zd>.S, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_b_0, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtx_z_p_z_d2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x650aa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtx_z_p_z_d2s Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvtx_z_p_z_d2s
            IEM_INSTR_IMPL_A64__fcvtx_z_p_z_d2s(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/641ac000: FCVTX  <Zd>.S, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_b_0, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtx_z_p_z_d2sz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x641ac000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtx_z_p_z_d2sz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvtx_z_p_z_d2sz
            IEM_INSTR_IMPL_A64__fcvtx_z_p_z_d2sz(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/640aa000: FCVTXNT  <Zd>.S, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_fcvt2_lvl2, sve_fp_fcvt2, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtxnt_z_p_z_d2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x640aa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtxnt_z_p_z_d2s Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvtxnt_z_p_z_d2s
            IEM_INSTR_IMPL_A64__fcvtxnt_z_p_z_d2s(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6402a000: FCVTXNT  <Zd>.S, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_fcvt2z_lvl2, sve_fp_fcvt2z, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtxnt_z_p_z_d2sz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6402a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtxnt_z_p_z_d2sz Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__fcvtxnt_z_p_z_d2sz
            IEM_INSTR_IMPL_A64__fcvtxnt_z_p_z_d2sz(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc21/c121e000: FCVTZS  { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_fpint_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_mz_z_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc21)) == UINT32_C(0xc121e000))
    {
        uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const U          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_mz_z_2 Zd=%#x U=%u Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_mz_z_2
            IEM_INSTR_IMPL_A64__fcvtzs_mz_z_2(Zd, U, Zn);
#else
            RT_NOREF(Zd, U, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc63/c131e000: FCVTZS  { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S }
   Instruction Set: A64  Groups: mortlach_multi4_fpint_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_mz_z_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc63)) == UINT32_C(0xc131e000))
    {
        uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
        uint32_t const U          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_mz_z_4 Zd=%u U=%u Zn=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_mz_z_4
            IEM_INSTR_IMPL_A64__fcvtzs_mz_z_4(Zd, U, Zn);
#else
            RT_NOREF(Zd, U, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65d8a000: FCVTZS  <Zd>.S, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_d2w, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65d8a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_z_p_z_d2w Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_d2w
            IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_d2w(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64de8000: FCVTZS  <Zd>.S, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_d2wz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64de8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_z_p_z_d2wz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_d2wz
            IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_d2wz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65dea000: FCVTZS  <Zd>.D, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_d2x, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65dea000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_z_p_z_d2x Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_d2x
            IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_d2x(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64dfc000: FCVTZS  <Zd>.D, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_d2xz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
    {
        LogFlow(("%018x/%010x: fcvtzs_z_p_z_d2xz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_d2xz
        IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_d2xz(Zd, Zn, Pg, int_U);
#else
        RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/655aa000: FCVTZS  <Zd>.H, <Pg>/M, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_fp162h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x655aa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_z_p_z_fp162h Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162h
            IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162h(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/645ec000: FCVTZS  <Zd>.H, <Pg>/Z, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_fp162hz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x645ec000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_z_p_z_fp162hz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162hz
            IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162hz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/655ca000: FCVTZS  <Zd>.S, <Pg>/M, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_fp162w, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x655ca000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_z_p_z_fp162w Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162w
            IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162w(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/645f8000: FCVTZS  <Zd>.S, <Pg>/Z, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_fp162wz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
    {
        LogFlow(("%018x/%010x: fcvtzs_z_p_z_fp162wz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162wz
        IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162wz(Zd, Zn, Pg, int_U);
#else
        RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/655ea000: FCVTZS  <Zd>.D, <Pg>/M, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_fp162x, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x655ea000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_z_p_z_fp162x Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162x
            IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162x(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/645fc000: FCVTZS  <Zd>.D, <Pg>/Z, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_fp162xz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x645fc000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_z_p_z_fp162xz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162xz
            IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162xz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/659ca000: FCVTZS  <Zd>.S, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_s2w, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x659ca000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_z_p_z_s2w Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_s2w
            IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_s2w(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/649f8000: FCVTZS  <Zd>.S, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_s2wz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x649f8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_z_p_z_s2wz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_s2wz
            IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_s2wz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65dca000: FCVTZS  <Zd>.D, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_s2x, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65dca000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_z_p_z_s2x Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_s2x
            IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_s2x(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64df8000: FCVTZS  <Zd>.D, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzs_z_p_z_s2xz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64df8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtzs_z_p_z_s2xz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_s2xz
            IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_s2xz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc21/c121e020: FCVTZU  { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_fpint_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_mz_z_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc21)) == UINT32_C(0xc121e020))
    {
        uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const U          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_mz_z_2 Zd=%#x U=%u Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_mz_z_2
            IEM_INSTR_IMPL_A64__fcvtzu_mz_z_2(Zd, U, Zn);
#else
            RT_NOREF(Zd, U, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc63/c131e020: FCVTZU  { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S }
   Instruction Set: A64  Groups: mortlach_multi4_fpint_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_mz_z_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc63)) == UINT32_C(0xc131e020))
    {
        uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
        uint32_t const U          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_mz_z_4 Zd=%u U=%u Zn=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_mz_z_4
            IEM_INSTR_IMPL_A64__fcvtzu_mz_z_4(Zd, U, Zn);
#else
            RT_NOREF(Zd, U, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65d9a000: FCVTZU  <Zd>.S, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_d2w, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65d9a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_d2w Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_d2w
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_d2w(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64dea000: FCVTZU  <Zd>.S, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_d2wz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64dea000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_d2wz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_d2wz
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_d2wz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65dfa000: FCVTZU  <Zd>.D, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_d2x, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65dfa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_d2x Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_d2x
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_d2x(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64dfe000: FCVTZU  <Zd>.D, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_d2xz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64dfe000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_d2xz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_d2xz
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_d2xz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/655ba000: FCVTZU  <Zd>.H, <Pg>/M, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_fp162h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x655ba000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_fp162h Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162h
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162h(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/645ee000: FCVTZU  <Zd>.H, <Pg>/Z, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_fp162hz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x645ee000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_fp162hz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162hz
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162hz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/655da000: FCVTZU  <Zd>.S, <Pg>/M, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_fp162w, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x655da000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_fp162w Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162w
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162w(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/645fa000: FCVTZU  <Zd>.S, <Pg>/Z, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_fp162wz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x645fa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_fp162wz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162wz
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162wz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/655fa000: FCVTZU  <Zd>.D, <Pg>/M, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_fp162x, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x655fa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_fp162x Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162x
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162x(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/645fe000: FCVTZU  <Zd>.D, <Pg>/Z, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_fp162xz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x645fe000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_fp162xz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162xz
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162xz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/659da000: FCVTZU  <Zd>.S, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_s2w, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x659da000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_s2w Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_s2w
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_s2w(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/649fa000: FCVTZU  <Zd>.S, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_s2wz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x649fa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_s2wz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_s2wz
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_s2wz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65dda000: FCVTZU  <Zd>.D, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_s2x, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65dda000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_s2x Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_s2x
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_s2x(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64dfa000: FCVTZU  <Zd>.D, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fcvtzu_z_p_z_s2xz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64dfa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fcvtzu_z_p_z_s2xz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_s2xz
            IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_s2xz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/650d8000: FDIV  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fdiv_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x650d8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fdiv_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fdiv_z_p_zz
            IEM_INSTR_IMPL_A64__fdiv_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/650c8000: FDIVR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fdivr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x650c8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fdivr_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fdivr_z_p_zz
            IEM_INSTR_IMPL_A64__fdivr_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64608400: FDOT  <Zda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_fp_fdot, sve_fp_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fdot_z32_zz8z8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64608400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8DOT4*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8DOT4*/)
        {
            LogFlow(("%018x/%010x: fdot_z32_zz8z8 Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_z32_zz8z8
            IEM_INSTR_IMPL_A64__fdot_z32_zz8z8(Zda, Zn, Zm);
#else
            RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64604400: FDOT  <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
   Instruction Set: A64  Groups: sve_fp_fdot_by_indexed_elem, sve_fp_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fdot_z32_zz8z8i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64604400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8DOT4*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8DOT4*/)
        {
            LogFlow(("%018x/%010x: fdot_z32_zz8z8i Zda=%#x Zn=%#x Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__fdot_z32_zz8z8i
            IEM_INSTR_IMPL_A64__fdot_z32_zz8z8i(Zda, Zn, Zm, i2);
#else
            RT_NOREF(Zda, Zn, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64208400: FDOT  <Zda>.H, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_fp_fdot, sve_fp_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fdot_z_zz8z8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64208400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8DOT2*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8DOT2*/)
        {
            LogFlow(("%018x/%010x: fdot_z_zz8z8 Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_z_zz8z8
            IEM_INSTR_IMPL_A64__fdot_z_zz8z8(Zda, Zn, Zm);
#else
            RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/64204400: FDOT  <Zda>.H, <Zn>.B, <Zm>.B[<imm>]
   Instruction Set: A64  Groups: sve_fp_fdot_by_indexed_elem, sve_fp_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fdot_z_zz8z8i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x64204400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8DOT2*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8DOT2*/)
        {
            LogFlow(("%018x/%010x: fdot_z_zz8z8i Zda=%#x Zn=%#x i3l=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, i3l, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__fdot_z_zz8z8i
            IEM_INSTR_IMPL_A64__fdot_z_zz8z8i(Zda, Zn, i3l, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, i3l, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64208000: FDOT  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_fdot, sve_fp_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fdot_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: fdot_z_zzz Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_z_zzz
        IEM_INSTR_IMPL_A64__fdot_z_zzz(Zda, Zn, Zm);
#else
        RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64204000: FDOT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fdot_by_indexed_elem, sve_fp_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fdot_z_zzzi, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: fdot_z_zzzi Zda=%#x Zn=%#x Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__fdot_z_zzzi
        IEM_INSTR_IMPL_A64__fdot_z_zzzi(Zda, Zn, Zm, i2);
#else
        RT_NOREF(Zda, Zn, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1500038: FDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za32_z8z8i_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1500038))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fdot_za32_z8z8i_2xi off3=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za32_z8z8i_2xi
            IEM_INSTR_IMPL_A64__fdot_za32_z8z8i_2xi(off3, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1508008: FDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za32_z8z8i_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1508008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fdot_za32_z8z8i_4xi off3=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za32_z8z8i_4xi
            IEM_INSTR_IMPL_A64__fdot_za32_z8z8i_4xi(off3, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1201018: FDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi2_z_za_fpdot_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za32_z8z8v_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1201018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fdot_za32_z8z8v_2x1 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za32_z8z8v_2x1
            IEM_INSTR_IMPL_A64__fdot_za32_z8z8v_2x1(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1301018: FDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi4_z_za_fpdot_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za32_z8z8v_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1301018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fdot_za32_z8z8v_4x1 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za32_z8z8v_4x1
            IEM_INSTR_IMPL_A64__fdot_za32_z8z8v_4x1(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c38/c1a01030: FDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_fpdot_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za32_z8z8w_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c38)) == UINT32_C(0xc1a01030))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fdot_za32_z8z8w_2x2 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za32_z8z8w_2x2
            IEM_INSTR_IMPL_A64__fdot_za32_z8z8w_2x2(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c78/c1a11030: FDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_fpdot_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za32_z8z8w_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c78)) == UINT32_C(0xc1a11030))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fdot_za32_z8z8w_4x4 off3=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za32_z8z8w_4x4
            IEM_INSTR_IMPL_A64__fdot_za32_z8z8w_4x4(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09030/c1d00020: FDOT  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_fp8_fdot_idx, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za_z8z8i_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09030)) == UINT32_C(0xc1d00020))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i3l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fdot_za_z8z8i_2xi off3=%u i3l=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i3l, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za_z8z8i_2xi
            IEM_INSTR_IMPL_A64__fdot_za_z8z8i_2xi(off3, i3l, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off3, i3l, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09070/c1109040: FDOT  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_fp8_fdot_idx_h, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za_z8z8i_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09070)) == UINT32_C(0xc1109040))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i3l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fdot_za_z8z8i_4xi off3=%u i3l=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i3l, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za_z8z8i_4xi
            IEM_INSTR_IMPL_A64__fdot_za_z8z8i_4xi(off3, i3l, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off3, i3l, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1201008: FDOT  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi2_z_za_fpdot_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za_z8z8v_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1201008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fdot_za_z8z8v_2x1 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za_z8z8v_2x1
            IEM_INSTR_IMPL_A64__fdot_za_z8z8v_2x1(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1301008: FDOT  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi4_z_za_fpdot_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za_z8z8v_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1301008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fdot_za_z8z8v_4x1 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za_z8z8v_4x1
            IEM_INSTR_IMPL_A64__fdot_za_z8z8v_4x1(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c38/c1a01020: FDOT  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_fpdot_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za_z8z8w_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c38)) == UINT32_C(0xc1a01020))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fdot_za_z8z8w_2x2 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za_z8z8w_2x2
            IEM_INSTR_IMPL_A64__fdot_za_z8z8w_2x2(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c78/c1a11020: FDOT  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_fpdot_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za_z8z8w_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c78)) == UINT32_C(0xc1a11020))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fdot_za_z8z8w_4x4 off3=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za_z8z8w_4x4
            IEM_INSTR_IMPL_A64__fdot_za_z8z8w_4x4(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1501008: FDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1501008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fdot_za_zzi_2xi off3=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za_zzi_2xi
            IEM_INSTR_IMPL_A64__fdot_za_zzi_2xi(off3, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1509008: FDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za_zzi_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1509008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fdot_za_zzi_4xi off3=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za_zzi_4xi
            IEM_INSTR_IMPL_A64__fdot_za_zzi_4xi(off3, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1201000: FDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_z_za_fpdot_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fdot_za_zzv_2x1 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za_zzv_2x1
        IEM_INSTR_IMPL_A64__fdot_za_zzv_2x1(off3, Zn, Rv, Zm);
#else
        RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1301000: FDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_z_za_fpdot_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1301000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fdot_za_zzv_4x1 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za_zzv_4x1
            IEM_INSTR_IMPL_A64__fdot_za_zzv_4x1(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c38/c1a01000: FDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_fpdot_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c38)) == UINT32_C(0xc1a01000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fdot_za_zzw_2x2 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za_zzw_2x2
            IEM_INSTR_IMPL_A64__fdot_za_zzw_2x2(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c78/c1a11000: FDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_fpdot_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fdot_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c78)) == UINT32_C(0xc1a11000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fdot_za_zzw_4x4 off3=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fdot_za_zzw_4x4
            IEM_INSTR_IMPL_A64__fdot_za_zzw_4x4(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/2539c000: FDUP  <Zd>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_dup_fpimm, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fdup_z_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x2539c000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fdup_z_i Zd=%#x imm8=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, imm8, size));
#ifdef IEM_INSTR_IMPL_A64__fdup_z_i
            IEM_INSTR_IMPL_A64__fdup_z_i(Zd, imm8, size);
#else
            RT_NOREF(Zd, imm8, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/0420b800: FEXPA  <Zd>.<T>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_bin_cons_misc_0_c, sve_int_unpred_misc, sve */
FNIEMOP_DEF_1(iemDecodeA64_fexpa_z_z, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
    {
        LogFlow(("%018x/%010x: fexpa_z_z Zd=%#x Zn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size));
#ifdef IEM_INSTR_IMPL_A64__fexpa_z_z
        IEM_INSTR_IMPL_A64__fexpa_z_z(Zd, Zn, size);
#else
        RT_NOREF(Zd, Zn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fc200/25218000: FIRSTP  <Xd>, <Pg>, <Pn>.<T>
   Instruction Set: A64  Groups: sve_int_pcount_pred, sve_pred_count_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_firstp_r_p_p, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fc200)) == UINT32_C(0x25218000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: firstp_r_p_p Rd=%#x Pn=%#x Pg=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Pn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__firstp_r_p_p
            IEM_INSTR_IMPL_A64__firstp_r_p_p(Rd, Pn, Pg, size);
#else
            RT_NOREF(Rd, Pn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff9e000/6518a000: FLOGB  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_d, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_flogb_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff9e000)) == UINT32_C(0x6518a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 17) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: flogb_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__flogb_z_p_z_m
            IEM_INSTR_IMPL_A64__flogb_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff8000/641e8000: FLOGB  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_d, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_flogb_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff8000)) == UINT32_C(0x641e8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 13) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: flogb_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__flogb_z_p_z_z
            IEM_INSTR_IMPL_A64__flogb_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/65208000: FMAD  <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_zds_b, sve_fp_fma, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmad_z_p_zzz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const N          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Za         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fmad_z_p_zzz Zdn=%#x Zm=%#x Pg=%u op=%u N=%u Za=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, op, N, Za, size));
#ifdef IEM_INSTR_IMPL_A64__fmad_z_p_zzz
        IEM_INSTR_IMPL_A64__fmad_z_p_zzz(Zdn, Zm, Pg, op, N, Za, size);
#else
        RT_NOREF(Zdn, Zm, Pg, op, N, Za, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a100: FMAX  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmax_mz_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmax_mz_zzv_2x1 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmax_mz_zzv_2x1
        IEM_INSTR_IMPL_A64__fmax_mz_zzv_2x1(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120a900: FMAX  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmax_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmax_mz_zzv_4x1 Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmax_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__fmax_mz_zzv_4x1(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b100: FMAX  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmax_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmax_mz_zzw_2x2 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmax_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__fmax_mz_zzw_2x2(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120b900: FMAX  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmax_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmax_mz_zzw_4x4 Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmax_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__fmax_mz_zzw_4x4(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe3c0/651e8000: FMAX  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
   Instruction Set: A64  Groups: sve_fp_2op_i_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmax_z_p_zs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe3c0)) == UINT32_C(0x651e8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const i1         = (uOpcode >>  5) & 0x00000001;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmax_z_p_zs Zdn=%#x i1=%u Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, i1, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmax_z_p_zs
            IEM_INSTR_IMPL_A64__fmax_z_p_zs(Zdn, i1, Pg, size);
#else
            RT_NOREF(Zdn, i1, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65068000: FMAX  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmax_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fmax_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmax_z_p_zz
        IEM_INSTR_IMPL_A64__fmax_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a120: FMAXNM  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmaxnm_mz_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmaxnm_mz_zzv_2x1 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmaxnm_mz_zzv_2x1
        IEM_INSTR_IMPL_A64__fmaxnm_mz_zzv_2x1(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120a920: FMAXNM  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmaxnm_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmaxnm_mz_zzv_4x1 Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmaxnm_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__fmaxnm_mz_zzv_4x1(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b120: FMAXNM  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmaxnm_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmaxnm_mz_zzw_2x2 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmaxnm_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__fmaxnm_mz_zzw_2x2(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120b920: FMAXNM  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmaxnm_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmaxnm_mz_zzw_4x4 Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmaxnm_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__fmaxnm_mz_zzw_4x4(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe3c0/651c8000: FMAXNM  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
   Instruction Set: A64  Groups: sve_fp_2op_i_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmaxnm_z_p_zs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe3c0)) == UINT32_C(0x651c8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const i1         = (uOpcode >>  5) & 0x00000001;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmaxnm_z_p_zs Zdn=%#x i1=%u Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, i1, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmaxnm_z_p_zs
            IEM_INSTR_IMPL_A64__fmaxnm_z_p_zs(Zdn, i1, Pg, size);
#else
            RT_NOREF(Zdn, i1, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65048000: FMAXNM  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmaxnm_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fmaxnm_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmaxnm_z_p_zz
        IEM_INSTR_IMPL_A64__fmaxnm_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/64148000: FMAXNMP  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_pairwise_lvl2, sve_fp_pairwise, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmaxnmp_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x64148000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmaxnmp_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmaxnmp_z_p_zz
            IEM_INSTR_IMPL_A64__fmaxnmp_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6414a000: FMAXNMQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_fp_fast_redq, sve_fp_fastreduceq, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmaxnmqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6414a000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: fmaxnmqv_z_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmaxnmqv_z_p_z
            IEM_INSTR_IMPL_A64__fmaxnmqv_z_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65042000: FMAXNMV  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_fast_red, sve_fp_fastreduce, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmaxnmv_v_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65042000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmaxnmv_v_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmaxnmv_v_p_z
            IEM_INSTR_IMPL_A64__fmaxnmv_v_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/64168000: FMAXP  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_pairwise_lvl2, sve_fp_pairwise, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmaxp_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x64168000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmaxp_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmaxp_z_p_zz
            IEM_INSTR_IMPL_A64__fmaxp_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6416a000: FMAXQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_fp_fast_redq, sve_fp_fastreduceq, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmaxqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6416a000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: fmaxqv_z_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmaxqv_z_p_z
            IEM_INSTR_IMPL_A64__fmaxqv_z_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65062000: FMAXV  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_fast_red, sve_fp_fastreduce, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmaxv_v_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65062000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmaxv_v_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmaxv_v_p_z
            IEM_INSTR_IMPL_A64__fmaxv_v_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a101: FMIN  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmin_mz_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmin_mz_zzv_2x1 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmin_mz_zzv_2x1
        IEM_INSTR_IMPL_A64__fmin_mz_zzv_2x1(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120a901: FMIN  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmin_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmin_mz_zzv_4x1 Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmin_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__fmin_mz_zzv_4x1(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b101: FMIN  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmin_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmin_mz_zzw_2x2 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmin_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__fmin_mz_zzw_2x2(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120b901: FMIN  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmin_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmin_mz_zzw_4x4 Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmin_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__fmin_mz_zzw_4x4(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe3c0/651f8000: FMIN  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
   Instruction Set: A64  Groups: sve_fp_2op_i_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmin_z_p_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const i1         = (uOpcode >>  5) & 0x00000001;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fmin_z_p_zs Zdn=%#x i1=%u Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, i1, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmin_z_p_zs
        IEM_INSTR_IMPL_A64__fmin_z_p_zs(Zdn, i1, Pg, size);
#else
        RT_NOREF(Zdn, i1, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65078000: FMIN  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmin_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fmin_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmin_z_p_zz
        IEM_INSTR_IMPL_A64__fmin_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a121: FMINNM  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fminnm_mz_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fminnm_mz_zzv_2x1 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fminnm_mz_zzv_2x1
        IEM_INSTR_IMPL_A64__fminnm_mz_zzv_2x1(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120a921: FMINNM  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fminnm_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fminnm_mz_zzv_4x1 Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fminnm_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__fminnm_mz_zzv_4x1(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b121: FMINNM  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fminmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_fminnm_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fminnm_mz_zzw_2x2 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fminnm_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__fminnm_mz_zzw_2x2(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120b921: FMINNM  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fminmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_fminnm_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fminnm_mz_zzw_4x4 Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fminnm_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__fminnm_mz_zzw_4x4(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe3c0/651d8000: FMINNM  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
   Instruction Set: A64  Groups: sve_fp_2op_i_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fminnm_z_p_zs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe3c0)) == UINT32_C(0x651d8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const i1         = (uOpcode >>  5) & 0x00000001;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fminnm_z_p_zs Zdn=%#x i1=%u Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, i1, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fminnm_z_p_zs
            IEM_INSTR_IMPL_A64__fminnm_z_p_zs(Zdn, i1, Pg, size);
#else
            RT_NOREF(Zdn, i1, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65058000: FMINNM  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fminnm_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fminnm_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fminnm_z_p_zz
        IEM_INSTR_IMPL_A64__fminnm_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/64158000: FMINNMP  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_pairwise_lvl2, sve_fp_pairwise, sve */
FNIEMOP_DEF_1(iemDecodeA64_fminnmp_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x64158000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fminnmp_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fminnmp_z_p_zz
            IEM_INSTR_IMPL_A64__fminnmp_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6415a000: FMINNMQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_fp_fast_redq, sve_fp_fastreduceq, sve */
FNIEMOP_DEF_1(iemDecodeA64_fminnmqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6415a000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: fminnmqv_z_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fminnmqv_z_p_z
            IEM_INSTR_IMPL_A64__fminnmqv_z_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65052000: FMINNMV  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_fast_red, sve_fp_fastreduce, sve */
FNIEMOP_DEF_1(iemDecodeA64_fminnmv_v_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65052000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fminnmv_v_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fminnmv_v_p_z
            IEM_INSTR_IMPL_A64__fminnmv_v_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/64178000: FMINP  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_pairwise_lvl2, sve_fp_pairwise, sve */
FNIEMOP_DEF_1(iemDecodeA64_fminp_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x64178000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fminp_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fminp_z_p_zz
            IEM_INSTR_IMPL_A64__fminp_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6417a000: FMINQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_fp_fast_redq, sve_fp_fastreduceq, sve */
FNIEMOP_DEF_1(iemDecodeA64_fminqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6417a000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: fminqv_z_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fminqv_z_p_z
            IEM_INSTR_IMPL_A64__fminqv_z_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65072000: FMINV  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_fast_red, sve_fp_fastreduce, sve */
FNIEMOP_DEF_1(iemDecodeA64_fminv_v_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65072000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fminv_v_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fminv_v_p_z
            IEM_INSTR_IMPL_A64__fminv_v_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/65200000: FMLA  <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_zds_a, sve_fp_fma, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmla_z_p_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const N          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fmla_z_p_zzz Zda=%#x Zn=%#x Pg=%u op=%u N=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Pg, op, N, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmla_z_p_zzz
        IEM_INSTR_IMPL_A64__fmla_z_p_zzz(Zda, Zn, Pg, op, N, Zm, size);
#else
        RT_NOREF(Zda, Zn, Pg, op, N, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64e00000: FMLA  <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_by_indexed_elem_lvl2, sve_fp_fma_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmla_z_zzzi_d, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fmla_z_zzzi_d Zda=%#x Zn=%#x op=%u Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, op, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__fmla_z_zzzi_d
        IEM_INSTR_IMPL_A64__fmla_z_zzzi_d(Zda, Zn, op, Zm, i1);
#else
        RT_NOREF(Zda, Zn, op, Zm, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/64200000: FMLA  <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_by_indexed_elem_lvl2, sve_fp_fma_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmla_z_zzzi_h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x64200000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmla_z_zzzi_h Zda=%#x Zn=%#x op=%u Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, op, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__fmla_z_zzzi_h
            IEM_INSTR_IMPL_A64__fmla_z_zzzi_h(Zda, Zn, op, Zm, i3l, i3h);
#else
            RT_NOREF(Zda, Zn, op, Zm, i3l, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64a00000: FMLA  <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_by_indexed_elem_lvl2, sve_fp_fma_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmla_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64a00000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmla_z_zzzi_s Zda=%#x Zn=%#x op=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, op, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__fmla_z_zzzi_s
            IEM_INSTR_IMPL_A64__fmla_z_zzzi_s(Zda, Zn, op, Zm, i2);
#else
            RT_NOREF(Zda, Zn, op, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09838/c1d00000: FMLA  ZA.D[<Wv>, <offs>{, VGx2}], { <Zn1>.D-<Zn2>.D }, <Zm>.D[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_d, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzi_d2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09838)) == UINT32_C(0xc1d00000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzi_d2xi off3=%u S=%u Zn=%#x i1=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, i1, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzi_d2xi
            IEM_INSTR_IMPL_A64__fmla_za_zzi_d2xi(off3, S, Zn, i1, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, i1, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09878/c1d08000: FMLA  ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.D-<Zn4>.D }, <Zm>.D[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_d, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzi_d4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09878)) == UINT32_C(0xc1d08000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i1         = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzi_d4xi off3=%u S=%u Zn=%u i1=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, i1, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzi_d4xi
            IEM_INSTR_IMPL_A64__fmla_za_zzi_d4xi(off3, S, Zn, i1, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, i1, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09030/c1101000: FMLA  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_h, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzi_h2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09030)) == UINT32_C(0xc1101000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i3l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzi_h2xi off3=%u i3l=%u S=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzi_h2xi
            IEM_INSTR_IMPL_A64__fmla_za_zzi_h2xi(off3, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off3, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09070/c1109000: FMLA  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_h, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzi_h4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09070)) == UINT32_C(0xc1109000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i3l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzi_h4xi off3=%u i3l=%u S=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzi_h4xi
            IEM_INSTR_IMPL_A64__fmla_za_zzi_h4xi(off3, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off3, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1500000: FMLA  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.S-<Zn2>.S }, <Zm>.S[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzi_s2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1500000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzi_s2xi off3=%u S=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzi_s2xi
            IEM_INSTR_IMPL_A64__fmla_za_zzi_s2xi(off3, S, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1508000: FMLA  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.S-<Zn4>.S }, <Zm>.S[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1508000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzi_s4xi off3=%u S=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__fmla_za_zzi_s4xi(off3, S, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c18/c1201800: FMLA  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_float_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c18)) == UINT32_C(0xc1201800))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzv_2x1 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzv_2x1
            IEM_INSTR_IMPL_A64__fmla_za_zzv_2x1(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1201c00: FMLA  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_f16_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzv_2x1_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1201c00))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzv_2x1_16 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzv_2x1_16
            IEM_INSTR_IMPL_A64__fmla_za_zzv_2x1_16(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c18/c1301800: FMLA  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_float_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c18)) == UINT32_C(0xc1301800))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzv_4x1 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzv_4x1
            IEM_INSTR_IMPL_A64__fmla_za_zzv_4x1(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1301c00: FMLA  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_f16_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzv_4x1_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1301c00))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzv_4x1_16 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzv_4x1_16
            IEM_INSTR_IMPL_A64__fmla_za_zzv_4x1_16(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa19c38/c1a01800: FMLA  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_float_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa19c38)) == UINT32_C(0xc1a01800))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzw_2x2 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzw_2x2
            IEM_INSTR_IMPL_A64__fmla_za_zzw_2x2(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c38/c1a01008: FMLA  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_f16_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzw_2x2_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c38)) == UINT32_C(0xc1a01008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzw_2x2_16 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzw_2x2_16
            IEM_INSTR_IMPL_A64__fmla_za_zzw_2x2_16(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa39c78/c1a11800: FMLA  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_float_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa39c78)) == UINT32_C(0xc1a11800))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzw_4x4 off3=%u S=%u Zn=%u Rv=%u Zm=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzw_4x4
            IEM_INSTR_IMPL_A64__fmla_za_zzw_4x4(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c78/c1a11008: FMLA  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_f16_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmla_za_zzw_4x4_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c78)) == UINT32_C(0xc1a11008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmla_za_zzw_4x4_16 off3=%u S=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmla_za_zzw_4x4_16
            IEM_INSTR_IMPL_A64__fmla_za_zzw_4x4_16(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff01010/c1c00000: FMLAL  ZA.H[<Wv>, <offs1>:<offs2>], <Zn>.B, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_fp8_fma_long_idx, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_z8z8i_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff01010)) == UINT32_C(0xc1c00000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i4C        = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i4B        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i4A        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_z8z8i_1 off3=%u i4C=%u Zn=%#x i4B=%u Rv=%u i4A=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i4C, Zn, i4B, Rv, i4A, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_z8z8i_1
            IEM_INSTR_IMPL_A64__fmlal_za_z8z8i_1(off3, i4C, Zn, i4B, Rv, i4A, Zm);
#else
            RT_NOREF(off3, i4C, Zn, i4B, Rv, i4A, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09030/c1901030: FMLAL  ZA.H[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_fp8_fma_long_idx, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_z8z8i_2xi, uint32_t, uOpcode)
{
    uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
    uint32_t const i4l        = (uOpcode >>  2) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
    {
        LogFlow(("%018x/%010x: fmlal_za_z8z8i_2xi off2=%u i4l=%u Zn=%#x i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i4l, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_z8z8i_2xi
        IEM_INSTR_IMPL_A64__fmlal_za_z8z8i_2xi(off2, i4l, Zn, i4h, Rv, Zm);
#else
        RT_NOREF(off2, i4l, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09070/c1909020: FMLAL  ZA.H[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_fp8_fma_long_idx, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_z8z8i_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09070)) == UINT32_C(0xc1909020))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i4l        = (uOpcode >>  2) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_z8z8i_4xi off2=%u i4l=%u Zn=%u i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i4l, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_z8z8i_4xi
            IEM_INSTR_IMPL_A64__fmlal_za_z8z8i_4xi(off2, i4l, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(off2, i4l, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1300c00: FMLAL  ZA.H[<Wv>, <offs1>:<offs2>], <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_fp8_fma_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_z8z8v_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1300c00))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_z8z8v_1 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_z8z8v_1
            IEM_INSTR_IMPL_A64__fmlal_za_z8z8v_1(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1200804: FMLAL  ZA.H[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_fma_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_z8z8v_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1200804))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_z8z8v_2x1 off2=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_z8z8v_2x1
            IEM_INSTR_IMPL_A64__fmlal_za_z8z8v_2x1(off2, Zn, Rv, Zm);
#else
            RT_NOREF(off2, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1300804: FMLAL  ZA.H[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_fma_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_z8z8v_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1300804))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_z8z8v_4x1 off2=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_z8z8v_4x1
            IEM_INSTR_IMPL_A64__fmlal_za_z8z8v_4x1(off2, Zn, Rv, Zm);
#else
            RT_NOREF(off2, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c3c/c1a00820: FMLAL  ZA.H[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_fp8_fma_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_z8z8w_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c3c)) == UINT32_C(0xc1a00820))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_z8z8w_2x2 off2=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_z8z8w_2x2
            IEM_INSTR_IMPL_A64__fmlal_za_z8z8w_2x2(off2, Zn, Rv, Zm);
#else
            RT_NOREF(off2, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c7c/c1a10820: FMLAL  ZA.H[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_fp8_fma_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_z8z8w_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c7c)) == UINT32_C(0xc1a10820))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_z8z8w_4x4 off2=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_z8z8w_4x4
            IEM_INSTR_IMPL_A64__fmlal_za_z8z8w_4x4(off2, Zn, Rv, Zm);
#else
            RT_NOREF(off2, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff01018/c1801000: FMLAL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_fma_long_idx, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_zzi_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff01018)) == UINT32_C(0xc1801000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i3l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_zzi_1 off3=%u S=%u Zn=%#x i3l=%u Rv=%u i3h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, i3l, Rv, i3h, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_zzi_1
            IEM_INSTR_IMPL_A64__fmlal_za_zzi_1(off3, S, Zn, i3l, Rv, i3h, Zm);
#else
            RT_NOREF(off3, S, Zn, i3l, Rv, i3h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1901000: FMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_fma_long_idx, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1901000))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_zzi_2xi off2=%u i3l=%u S=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_zzi_2xi
            IEM_INSTR_IMPL_A64__fmlal_za_zzi_2xi(off2, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1909000: FMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_fma_long_idx, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_zzi_4xi, uint32_t, uOpcode)
{
    uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
    uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fmlal_za_zzi_4xi off2=%u i3l=%u S=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_zzi_4xi
        IEM_INSTR_IMPL_A64__fmlal_za_zzi_4xi(off2, i3l, S, Zn, i3h, Rv, Zm);
#else
        RT_NOREF(off2, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1200c00: FMLAL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_fma_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_zzv_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1200c00))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_zzv_1 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_zzv_1
            IEM_INSTR_IMPL_A64__fmlal_za_zzv_1(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1200800: FMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_fma_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1200800))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_zzv_2x1 off2=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_zzv_2x1
            IEM_INSTR_IMPL_A64__fmlal_za_zzv_2x1(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1300800: FMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_fma_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1300800))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_zzv_4x1 off2=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_zzv_4x1
            IEM_INSTR_IMPL_A64__fmlal_za_zzv_4x1(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c3c/c1a00800: FMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_fma_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c3c)) == UINT32_C(0xc1a00800))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_zzw_2x2 off2=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_zzw_2x2
            IEM_INSTR_IMPL_A64__fmlal_za_zzw_2x2(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c7c/c1a10800: FMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_fma_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlal_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c7c)) == UINT32_C(0xc1a10800))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlal_za_zzw_4x4 off2=%u S=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlal_za_zzw_4x4
            IEM_INSTR_IMPL_A64__fmlal_za_zzw_4x4(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64a08800: FMLALB  <Zda>.H, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_fp8_fma_long, sve_fp8_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlalb_z_z8z8z8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64a08800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: fmlalb_z_z8z8z8 Zda=%#x Zn=%#x T=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlalb_z_z8z8z8
            IEM_INSTR_IMPL_A64__fmlalb_z_z8z8z8(Zda, Zn, T, Zm);
#else
            RT_NOREF(Zda, Zn, T, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/64205000: FMLALB  <Zda>.H, <Zn>.B, <Zm>.B[<imm>]
   Instruction Set: A64  Groups: sve_fp8_fma_long_by_indexed_elem, sve_fp8_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlalb_z_z8z8z8i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x64205000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i4l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i4h        = (uOpcode >> 19) & 0x00000003;
        uint32_t const T          = (uOpcode >> 23) & 0x00000001;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: fmlalb_z_z8z8z8i Zda=%#x Zn=%#x i4l=%u Zm=%u i4h=%u T=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, i4l, Zm, i4h, T));
#ifdef IEM_INSTR_IMPL_A64__fmlalb_z_z8z8z8i
            IEM_INSTR_IMPL_A64__fmlalb_z_z8z8z8i(Zda, Zn, i4l, Zm, i4h, T);
#else
            RT_NOREF(Zda, Zn, i4l, Zm, i4h, T, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64a08000: FMLALB  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_fma_long, sve_fp_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlalb_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64a08000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmlalb_z_zzz Zda=%#x Zn=%#x T=%u op=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, op, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlalb_z_zzz
            IEM_INSTR_IMPL_A64__fmlalb_z_zzz(Zda, Zn, T, op, Zm);
#else
            RT_NOREF(Zda, Zn, T, op, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/64a04000: FMLALB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_long_by_indexed_elem, sve_fp_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlalb_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x64a04000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmlalb_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u op=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, op, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__fmlalb_z_zzzi_s
            IEM_INSTR_IMPL_A64__fmlalb_z_zzzi_s(Zda, Zn, T, i3l, op, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, T, i3l, op, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0001c/c1400000: FMLALL  ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_fp8_fma_long_long_idx, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlall_za32_z8z8i_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0001c)) == UINT32_C(0xc1400000))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i4l        = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i4h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fmlall_za32_z8z8i_1 off2=%u Zn=%#x i4l=%u Rv=%u i4h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, Zn, i4l, Rv, i4h, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlall_za32_z8z8i_1
            IEM_INSTR_IMPL_A64__fmlall_za32_z8z8i_1(off2, Zn, i4l, Rv, i4h, Zm);
#else
            RT_NOREF(off2, Zn, i4l, Rv, i4h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1900020: FMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_fp8_fma_long_long_idx, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlall_za32_z8z8i_2xi, uint32_t, uOpcode)
{
    uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
    uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
    {
        LogFlow(("%018x/%010x: fmlall_za32_z8z8i_2xi o1=%u i4l=%u Zn=%#x i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlall_za32_z8z8i_2xi
        IEM_INSTR_IMPL_A64__fmlall_za32_z8z8i_2xi(o1, i4l, Zn, i4h, Rv, Zm);
#else
        RT_NOREF(o1, i4l, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1108040: FMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_fp8_fma_long_long_idx, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlall_za32_z8z8i_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1108040))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fmlall_za32_z8z8i_4xi o1=%u i4l=%u Zn=%u i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlall_za32_z8z8i_4xi
            IEM_INSTR_IMPL_A64__fmlall_za32_z8z8i_4xi(o1, i4l, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1300400: FMLALL  ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_fp8_fma_long_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlall_za32_z8z8v_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1300400))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fmlall_za32_z8z8v_1 off2=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlall_za32_z8z8v_1
            IEM_INSTR_IMPL_A64__fmlall_za32_z8z8v_1(off2, Zn, Rv, Zm);
#else
            RT_NOREF(off2, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1e/c1200002: FMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_fp8_fma_long_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlall_za32_z8z8v_2x1, uint32_t, uOpcode)
{
    uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
    {
        LogFlow(("%018x/%010x: fmlall_za32_z8z8v_2x1 o1=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlall_za32_z8z8v_2x1
        IEM_INSTR_IMPL_A64__fmlall_za32_z8z8v_2x1(o1, Zn, Rv, Zm);
#else
        RT_NOREF(o1, Zn, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1e/c1300002: FMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_fp8_fma_long_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlall_za32_z8z8v_4x1, uint32_t, uOpcode)
{
    uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
    {
        LogFlow(("%018x/%010x: fmlall_za32_z8z8v_4x1 o1=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlall_za32_z8z8v_4x1
        IEM_INSTR_IMPL_A64__fmlall_za32_z8z8v_4x1(o1, Zn, Rv, Zm);
#else
        RT_NOREF(o1, Zn, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c3e/c1a00020: FMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_fp8_fma_long_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlall_za32_z8z8w_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c3e)) == UINT32_C(0xc1a00020))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fmlall_za32_z8z8w_2x2 o1=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlall_za32_z8z8w_2x2
            IEM_INSTR_IMPL_A64__fmlall_za32_z8z8w_2x2(o1, Zn, Rv, Zm);
#else
            RT_NOREF(o1, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c7e/c1a10020: FMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_fp8_fma_long_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlall_za32_z8z8w_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c7e)) == UINT32_C(0xc1a10020))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fmlall_za32_z8z8w_4x4 o1=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlall_za32_z8z8w_4x4
            IEM_INSTR_IMPL_A64__fmlall_za32_z8z8w_4x4(o1, Zn, Rv, Zm);
#else
            RT_NOREF(o1, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64208800: FMLALLBB  <Zda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_fp8_fma_long_long, sve_fp8_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlallbb_z32_z8z8z8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64208800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const TT         = (uOpcode >> 12) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: fmlallbb_z32_z8z8z8 Zda=%#x Zn=%#x TT=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, TT, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlallbb_z32_z8z8z8
            IEM_INSTR_IMPL_A64__fmlallbb_z32_z8z8z8(Zda, Zn, TT, Zm);
#else
            RT_NOREF(Zda, Zn, TT, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/6420c000: FMLALLBB  <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
   Instruction Set: A64  Groups: sve_fp8_fma_long_long_by_indexed_elem, sve_fp8_fma_ww_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlallbb_z32_z8z8z8i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x6420c000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i4l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i4h        = (uOpcode >> 19) & 0x00000003;
        uint32_t const TT         = (uOpcode >> 22) & 0x00000003;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: fmlallbb_z32_z8z8z8i Zda=%#x Zn=%#x i4l=%u Zm=%u i4h=%u TT=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, i4l, Zm, i4h, TT));
#ifdef IEM_INSTR_IMPL_A64__fmlallbb_z32_z8z8z8i
            IEM_INSTR_IMPL_A64__fmlallbb_z32_z8z8z8i(Zda, Zn, i4l, Zm, i4h, TT);
#else
            RT_NOREF(Zda, Zn, i4l, Zm, i4h, TT, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64209800: FMLALLBT  <Zda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_fp8_fma_long_long, sve_fp8_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlallbt_z32_z8z8z8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64209800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const TT         = (uOpcode >> 12) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: fmlallbt_z32_z8z8z8 Zda=%#x Zn=%#x TT=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, TT, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlallbt_z32_z8z8z8
            IEM_INSTR_IMPL_A64__fmlallbt_z32_z8z8z8(Zda, Zn, TT, Zm);
#else
            RT_NOREF(Zda, Zn, TT, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/6460c000: FMLALLBT  <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
   Instruction Set: A64  Groups: sve_fp8_fma_long_long_by_indexed_elem, sve_fp8_fma_ww_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlallbt_z32_z8z8z8i, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i4l        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i4h        = (uOpcode >> 19) & 0x00000003;
    uint32_t const TT         = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8FMA*/)
    {
        LogFlow(("%018x/%010x: fmlallbt_z32_z8z8z8i Zda=%#x Zn=%#x i4l=%u Zm=%u i4h=%u TT=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, i4l, Zm, i4h, TT));
#ifdef IEM_INSTR_IMPL_A64__fmlallbt_z32_z8z8z8i
        IEM_INSTR_IMPL_A64__fmlallbt_z32_z8z8z8i(Zda, Zn, i4l, Zm, i4h, TT);
#else
        RT_NOREF(Zda, Zn, i4l, Zm, i4h, TT, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/6420a800: FMLALLTB  <Zda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_fp8_fma_long_long, sve_fp8_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlalltb_z32_z8z8z8, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const TT         = (uOpcode >> 12) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8FMA*/)
    {
        LogFlow(("%018x/%010x: fmlalltb_z32_z8z8z8 Zda=%#x Zn=%#x TT=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, TT, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlalltb_z32_z8z8z8
        IEM_INSTR_IMPL_A64__fmlalltb_z32_z8z8z8(Zda, Zn, TT, Zm);
#else
        RT_NOREF(Zda, Zn, TT, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/64a0c000: FMLALLTB  <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
   Instruction Set: A64  Groups: sve_fp8_fma_long_long_by_indexed_elem, sve_fp8_fma_ww_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlalltb_z32_z8z8z8i, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i4l        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i4h        = (uOpcode >> 19) & 0x00000003;
    uint32_t const TT         = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8FMA*/)
    {
        LogFlow(("%018x/%010x: fmlalltb_z32_z8z8z8i Zda=%#x Zn=%#x i4l=%u Zm=%u i4h=%u TT=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, i4l, Zm, i4h, TT));
#ifdef IEM_INSTR_IMPL_A64__fmlalltb_z32_z8z8z8i
        IEM_INSTR_IMPL_A64__fmlalltb_z32_z8z8z8i(Zda, Zn, i4l, Zm, i4h, TT);
#else
        RT_NOREF(Zda, Zn, i4l, Zm, i4h, TT, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/6420b800: FMLALLTT  <Zda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_fp8_fma_long_long, sve_fp8_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlalltt_z32_z8z8z8, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const TT         = (uOpcode >> 12) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8FMA*/)
    {
        LogFlow(("%018x/%010x: fmlalltt_z32_z8z8z8 Zda=%#x Zn=%#x TT=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, TT, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlalltt_z32_z8z8z8
        IEM_INSTR_IMPL_A64__fmlalltt_z32_z8z8z8(Zda, Zn, TT, Zm);
#else
        RT_NOREF(Zda, Zn, TT, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/64e0c000: FMLALLTT  <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
   Instruction Set: A64  Groups: sve_fp8_fma_long_long_by_indexed_elem, sve_fp8_fma_ww_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlalltt_z32_z8z8z8i, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i4l        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i4h        = (uOpcode >> 19) & 0x00000003;
    uint32_t const TT         = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8FMA*/)
    {
        LogFlow(("%018x/%010x: fmlalltt_z32_z8z8z8i Zda=%#x Zn=%#x i4l=%u Zm=%u i4h=%u TT=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, i4l, Zm, i4h, TT));
#ifdef IEM_INSTR_IMPL_A64__fmlalltt_z32_z8z8z8i
        IEM_INSTR_IMPL_A64__fmlalltt_z32_z8z8z8i(Zda, Zn, i4l, Zm, i4h, TT);
#else
        RT_NOREF(Zda, Zn, i4l, Zm, i4h, TT, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64a09800: FMLALT  <Zda>.H, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_fp8_fma_long, sve_fp8_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlalt_z_z8z8z8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64a09800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: fmlalt_z_z8z8z8 Zda=%#x Zn=%#x T=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlalt_z_z8z8z8
            IEM_INSTR_IMPL_A64__fmlalt_z_z8z8z8(Zda, Zn, T, Zm);
#else
            RT_NOREF(Zda, Zn, T, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/64a05000: FMLALT  <Zda>.H, <Zn>.B, <Zm>.B[<imm>]
   Instruction Set: A64  Groups: sve_fp8_fma_long_by_indexed_elem, sve_fp8_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlalt_z_z8z8z8i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x64a05000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i4l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i4h        = (uOpcode >> 19) & 0x00000003;
        uint32_t const T          = (uOpcode >> 23) & 0x00000001;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8FMA*/) || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SSVE_FP8FMA*/)
        {
            LogFlow(("%018x/%010x: fmlalt_z_z8z8z8i Zda=%#x Zn=%#x i4l=%u Zm=%u i4h=%u T=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, i4l, Zm, i4h, T));
#ifdef IEM_INSTR_IMPL_A64__fmlalt_z_z8z8z8i
            IEM_INSTR_IMPL_A64__fmlalt_z_z8z8z8i(Zda, Zn, i4l, Zm, i4h, T);
#else
            RT_NOREF(Zda, Zn, i4l, Zm, i4h, T, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64a08400: FMLALT  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_fma_long, sve_fp_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlalt_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64a08400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmlalt_z_zzz Zda=%#x Zn=%#x T=%u op=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, op, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlalt_z_zzz
            IEM_INSTR_IMPL_A64__fmlalt_z_zzz(Zda, Zn, T, op, Zm);
#else
            RT_NOREF(Zda, Zn, T, op, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/64a04400: FMLALT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_long_by_indexed_elem, sve_fp_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlalt_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x64a04400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmlalt_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u op=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, op, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__fmlalt_z_zzzi_s
            IEM_INSTR_IMPL_A64__fmlalt_z_zzzi_s(Zda, Zn, T, i3l, op, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, T, i3l, op, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/65202000: FMLS  <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_zds_a, sve_fp_fma, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmls_z_p_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const N          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fmls_z_p_zzz Zda=%#x Zn=%#x Pg=%u op=%u N=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Pg, op, N, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmls_z_p_zzz
        IEM_INSTR_IMPL_A64__fmls_z_p_zzz(Zda, Zn, Pg, op, N, Zm, size);
#else
        RT_NOREF(Zda, Zn, Pg, op, N, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64e00400: FMLS  <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_by_indexed_elem_lvl2, sve_fp_fma_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmls_z_zzzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64e00400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const op         = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmls_z_zzzi_d Zda=%#x Zn=%#x op=%u Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, op, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__fmls_z_zzzi_d
            IEM_INSTR_IMPL_A64__fmls_z_zzzi_d(Zda, Zn, op, Zm, i1);
#else
            RT_NOREF(Zda, Zn, op, Zm, i1, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/64200400: FMLS  <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_by_indexed_elem_lvl2, sve_fp_fma_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmls_z_zzzi_h, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
    uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fmls_z_zzzi_h Zda=%#x Zn=%#x op=%u Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, op, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__fmls_z_zzzi_h
        IEM_INSTR_IMPL_A64__fmls_z_zzzi_h(Zda, Zn, op, Zm, i3l, i3h);
#else
        RT_NOREF(Zda, Zn, op, Zm, i3l, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64a00400: FMLS  <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_by_indexed_elem_lvl2, sve_fp_fma_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmls_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const op         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fmls_z_zzzi_s Zda=%#x Zn=%#x op=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, op, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__fmls_z_zzzi_s
        IEM_INSTR_IMPL_A64__fmls_z_zzzi_s(Zda, Zn, op, Zm, i2);
#else
        RT_NOREF(Zda, Zn, op, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09838/c1d00010: FMLS  ZA.D[<Wv>, <offs>{, VGx2}], { <Zn1>.D-<Zn2>.D }, <Zm>.D[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_d, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzi_d2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09838)) == UINT32_C(0xc1d00010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzi_d2xi off3=%u S=%u Zn=%#x i1=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, i1, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzi_d2xi
            IEM_INSTR_IMPL_A64__fmls_za_zzi_d2xi(off3, S, Zn, i1, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, i1, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09878/c1d08010: FMLS  ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.D-<Zn4>.D }, <Zm>.D[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_d, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzi_d4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09878)) == UINT32_C(0xc1d08010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i1         = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzi_d4xi off3=%u S=%u Zn=%u i1=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, i1, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzi_d4xi
            IEM_INSTR_IMPL_A64__fmls_za_zzi_d4xi(off3, S, Zn, i1, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, i1, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09030/c1101010: FMLS  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_h, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzi_h2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09030)) == UINT32_C(0xc1101010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i3l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzi_h2xi off3=%u i3l=%u S=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzi_h2xi
            IEM_INSTR_IMPL_A64__fmls_za_zzi_h2xi(off3, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off3, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09070/c1109010: FMLS  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_h, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzi_h4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09070)) == UINT32_C(0xc1109010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i3l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzi_h4xi off3=%u i3l=%u S=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzi_h4xi
            IEM_INSTR_IMPL_A64__fmls_za_zzi_h4xi(off3, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off3, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1500010: FMLS  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.S-<Zn2>.S }, <Zm>.S[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzi_s2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1500010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzi_s2xi off3=%u S=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzi_s2xi
            IEM_INSTR_IMPL_A64__fmls_za_zzi_s2xi(off3, S, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1508010: FMLS  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.S-<Zn4>.S }, <Zm>.S[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1508010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzi_s4xi off3=%u S=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__fmls_za_zzi_s4xi(off3, S, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c18/c1201808: FMLS  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_float_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c18)) == UINT32_C(0xc1201808))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzv_2x1 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzv_2x1
            IEM_INSTR_IMPL_A64__fmls_za_zzv_2x1(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1201c08: FMLS  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_f16_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzv_2x1_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1201c08))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzv_2x1_16 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzv_2x1_16
            IEM_INSTR_IMPL_A64__fmls_za_zzv_2x1_16(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c18/c1301808: FMLS  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_float_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c18)) == UINT32_C(0xc1301808))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzv_4x1 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzv_4x1
            IEM_INSTR_IMPL_A64__fmls_za_zzv_4x1(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1301c08: FMLS  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_f16_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzv_4x1_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1301c08))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzv_4x1_16 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzv_4x1_16
            IEM_INSTR_IMPL_A64__fmls_za_zzv_4x1_16(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa19c38/c1a01808: FMLS  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_float_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa19c38)) == UINT32_C(0xc1a01808))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzw_2x2 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzw_2x2
            IEM_INSTR_IMPL_A64__fmls_za_zzw_2x2(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c38/c1a01018: FMLS  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_f16_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzw_2x2_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c38)) == UINT32_C(0xc1a01018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzw_2x2_16 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzw_2x2_16
            IEM_INSTR_IMPL_A64__fmls_za_zzw_2x2_16(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa39c78/c1a11808: FMLS  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_float_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa39c78)) == UINT32_C(0xc1a11808))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzw_4x4 off3=%u S=%u Zn=%u Rv=%u Zm=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzw_4x4
            IEM_INSTR_IMPL_A64__fmls_za_zzw_4x4(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c78/c1a11018: FMLS  ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_f16_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmls_za_zzw_4x4_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c78)) == UINT32_C(0xc1a11018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmls_za_zzw_4x4_16 off3=%u S=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmls_za_zzw_4x4_16
            IEM_INSTR_IMPL_A64__fmls_za_zzw_4x4_16(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff01018/c1801008: FMLSL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_fma_long_idx, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlsl_za_zzi_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff01018)) == UINT32_C(0xc1801008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i3l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlsl_za_zzi_1 off3=%u S=%u Zn=%#x i3l=%u Rv=%u i3h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, i3l, Rv, i3h, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlsl_za_zzi_1
            IEM_INSTR_IMPL_A64__fmlsl_za_zzi_1(off3, S, Zn, i3l, Rv, i3h, Zm);
#else
            RT_NOREF(off3, S, Zn, i3l, Rv, i3h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1901008: FMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_fma_long_idx, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlsl_za_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1901008))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlsl_za_zzi_2xi off2=%u i3l=%u S=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlsl_za_zzi_2xi
            IEM_INSTR_IMPL_A64__fmlsl_za_zzi_2xi(off2, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1909008: FMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_fma_long_idx, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlsl_za_zzi_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1909008))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlsl_za_zzi_4xi off2=%u i3l=%u S=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlsl_za_zzi_4xi
            IEM_INSTR_IMPL_A64__fmlsl_za_zzi_4xi(off2, i3l, S, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1200c08: FMLSL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_fma_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlsl_za_zzv_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1200c08))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlsl_za_zzv_1 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlsl_za_zzv_1
            IEM_INSTR_IMPL_A64__fmlsl_za_zzv_1(off3, S, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1200808: FMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_fma_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlsl_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1200808))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlsl_za_zzv_2x1 off2=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlsl_za_zzv_2x1
            IEM_INSTR_IMPL_A64__fmlsl_za_zzv_2x1(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1300808: FMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_fma_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlsl_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1300808))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlsl_za_zzv_4x1 off2=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlsl_za_zzv_4x1
            IEM_INSTR_IMPL_A64__fmlsl_za_zzv_4x1(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c3c/c1a00808: FMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_fma_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlsl_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c3c)) == UINT32_C(0xc1a00808))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlsl_za_zzw_2x2 off2=%u S=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlsl_za_zzw_2x2
            IEM_INSTR_IMPL_A64__fmlsl_za_zzw_2x2(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c7c/c1a10808: FMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_fma_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmlsl_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c7c)) == UINT32_C(0xc1a10808))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fmlsl_za_zzw_4x4 off2=%u S=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlsl_za_zzw_4x4
            IEM_INSTR_IMPL_A64__fmlsl_za_zzw_4x4(off2, S, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64a0a000: FMLSLB  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_fma_long, sve_fp_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlslb_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fmlslb_z_zzz Zda=%#x Zn=%#x T=%u op=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, op, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlslb_z_zzz
        IEM_INSTR_IMPL_A64__fmlslb_z_zzz(Zda, Zn, T, op, Zm);
#else
        RT_NOREF(Zda, Zn, T, op, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/64a06000: FMLSLB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_long_by_indexed_elem, sve_fp_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlslb_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x64a06000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmlslb_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u op=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, op, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__fmlslb_z_zzzi_s
            IEM_INSTR_IMPL_A64__fmlslb_z_zzzi_s(Zda, Zn, T, i3l, op, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, T, i3l, op, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64a0a400: FMLSLT  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_fma_long, sve_fp_fma_w, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlslt_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64a0a400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmlslt_z_zzz Zda=%#x Zn=%#x T=%u op=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, op, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmlslt_z_zzz
            IEM_INSTR_IMPL_A64__fmlslt_z_zzz(Zda, Zn, T, op, Zm);
#else
            RT_NOREF(Zda, Zn, T, op, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/64a06400: FMLSLT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fma_long_by_indexed_elem, sve_fp_fma_w_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmlslt_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x64a06400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmlslt_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u op=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, op, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__fmlslt_z_zzzi_s
            IEM_INSTR_IMPL_A64__fmlslt_z_zzzi_s(Zda, Zn, T, i3l, op, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, T, i3l, op, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/6460e000: FMMLA  <Zda>.H, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_fp8_fmmla_lvl2, sve_fp8_fmmla, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmmla_z16_zz8z8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x6460e000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_F8F16MM*/)
        {
            LogFlow(("%018x/%010x: fmmla_z16_zz8z8 Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmmla_z16_zz8z8
            IEM_INSTR_IMPL_A64__fmmla_z16_zz8z8(Zda, Zn, Zm);
#else
            RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/6420e000: FMMLA  <Zda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_fp8_fmmla_lvl2, sve_fp8_fmmla, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmmla_z32_zz8z8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x6420e000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_F8F32MM*/)
        {
            LogFlow(("%018x/%010x: fmmla_z32_zz8z8 Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmmla_z32_zz8z8
            IEM_INSTR_IMPL_A64__fmmla_z32_zz8z8(Zda, Zn, Zm);
#else
            RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/6420e400: FMMLA  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_fp_fmmla_lvl2, sve_fp_fmmla, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmmla_z32_zzz_h, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_F16F32MM*/)
    {
        LogFlow(("%018x/%010x: fmmla_z32_zzz_h Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmmla_z32_zzz_h
        IEM_INSTR_IMPL_A64__fmmla_z32_zzz_h(Zda, Zn, Zm);
#else
        RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64e0e400: FMMLA  <Zda>.D, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_fp_fmmla_lvl2, sve_fp_fmmla, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmmla_z_zzz_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64e0e400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
        {
            LogFlow(("%018x/%010x: fmmla_z_zzz_d Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmmla_z_zzz_d
            IEM_INSTR_IMPL_A64__fmmla_z_zzz_d(Zda, Zn, Zm);
#else
            RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64a0e400: FMMLA  <Zda>.S, <Zn>.S, <Zm>.S
   Instruction Set: A64  Groups: sve_fp_fmmla_lvl2, sve_fp_fmmla, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmmla_z_zzz_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF32mm /*FEAT_F32MM*/)
    {
        LogFlow(("%018x/%010x: fmmla_z_zzz_s Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmmla_z_zzz_s
        IEM_INSTR_IMPL_A64__fmmla_z_zzz_s(Zda, Zn, Zm);
#else
        RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/80200008: FMOP4A  <ZAda>.H, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_f8f16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za16_z8z8_b1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x80200008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za16_z8z8_b1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za16_z8z8_b1x1
            IEM_INSTR_IMPL_A64__fmop4a_za16_z8z8_b1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/80300008: FMOP4A  <ZAda>.H, <Zn>.B, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_f8f16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za16_z8z8_b1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x80300008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za16_z8z8_b1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za16_z8z8_b1x2
            IEM_INSTR_IMPL_A64__fmop4a_za16_z8z8_b1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/80200208: FMOP4A  <ZAda>.H, { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_f8f16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za16_z8z8_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x80200208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za16_z8z8_b2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za16_z8z8_b2x1
            IEM_INSTR_IMPL_A64__fmop4a_za16_z8z8_b2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/80300208: FMOP4A  <ZAda>.H, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_f8f16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za16_z8z8_b2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x80300208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za16_z8z8_b2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za16_z8z8_b2x2
            IEM_INSTR_IMPL_A64__fmop4a_za16_z8z8_b2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80200000: FMOP4A  <ZAda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_f8f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za32_z8z8_b1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80200000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za32_z8z8_b1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za32_z8z8_b1x1
            IEM_INSTR_IMPL_A64__fmop4a_za32_z8z8_b1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80300000: FMOP4A  <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_f8f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za32_z8z8_b1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80300000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za32_z8z8_b1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za32_z8z8_b1x2
            IEM_INSTR_IMPL_A64__fmop4a_za32_z8z8_b1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80200200: FMOP4A  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_f8f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za32_z8z8_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80200200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za32_z8z8_b2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za32_z8z8_b2x1
            IEM_INSTR_IMPL_A64__fmop4a_za32_z8z8_b2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80300200: FMOP4A  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_f8f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za32_z8z8_b2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80300200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za32_z8z8_b2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za32_z8z8_b2x2
            IEM_INSTR_IMPL_A64__fmop4a_za32_z8z8_b2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81200000: FMOP4A  <ZAda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_f16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za32_zz_h1x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
    {
        LogFlow(("%018x/%010x: fmop4a_za32_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za32_zz_h1x1
        IEM_INSTR_IMPL_A64__fmop4a_za32_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81300000: FMOP4A  <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_f16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za32_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81300000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za32_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za32_zz_h1x2
            IEM_INSTR_IMPL_A64__fmop4a_za32_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81200200: FMOP4A  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_f16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za32_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81200200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za32_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za32_zz_h2x1
            IEM_INSTR_IMPL_A64__fmop4a_za32_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81300200: FMOP4A  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_f16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za32_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81300200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za32_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za32_zz_h2x2
            IEM_INSTR_IMPL_A64__fmop4a_za32_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/80c00008: FMOP4A  <ZAda>.D, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: mortlach_f64f64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za_zz_d1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0x80c00008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za_zz_d1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za_zz_d1x1
            IEM_INSTR_IMPL_A64__fmop4a_za_zz_d1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/80d00008: FMOP4A  <ZAda>.D, <Zn>.D, { <Zm1>.D-<Zm2>.D }
   Instruction Set: A64  Groups: mortlach_f64f64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za_zz_d1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0x80d00008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za_zz_d1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za_zz_d1x2
            IEM_INSTR_IMPL_A64__fmop4a_za_zz_d1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/80c00208: FMOP4A  <ZAda>.D, { <Zn1>.D-<Zn2>.D }, <Zm>.D
   Instruction Set: A64  Groups: mortlach_f64f64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za_zz_d2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0x80c00208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za_zz_d2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za_zz_d2x1
            IEM_INSTR_IMPL_A64__fmop4a_za_zz_d2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/80d00208: FMOP4A  <ZAda>.D, { <Zn1>.D-<Zn2>.D }, { <Zm1>.D-<Zm2>.D }
   Instruction Set: A64  Groups: mortlach_f64f64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za_zz_d2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0x80d00208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za_zz_d2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za_zz_d2x2
            IEM_INSTR_IMPL_A64__fmop4a_za_zz_d2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81000008: FMOP4A  <ZAda>.H, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_f16f16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81000008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za_zz_h1x1
            IEM_INSTR_IMPL_A64__fmop4a_za_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81100008: FMOP4A  <ZAda>.H, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_f16f16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81100008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za_zz_h1x2
            IEM_INSTR_IMPL_A64__fmop4a_za_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81000208: FMOP4A  <ZAda>.H, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_f16f16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81000208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za_zz_h2x1
            IEM_INSTR_IMPL_A64__fmop4a_za_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81100208: FMOP4A  <ZAda>.H, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_f16f16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81100208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za_zz_h2x2
            IEM_INSTR_IMPL_A64__fmop4a_za_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80000000: FMOP4A  <ZAda>.S, <Zn>.S, <Zm>.S
   Instruction Set: A64  Groups: mortlach_f32f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za_zz_s1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80000000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za_zz_s1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za_zz_s1x1
            IEM_INSTR_IMPL_A64__fmop4a_za_zz_s1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80100000: FMOP4A  <ZAda>.S, <Zn>.S, { <Zm1>.S-<Zm2>.S }
   Instruction Set: A64  Groups: mortlach_f32f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za_zz_s1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80100000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za_zz_s1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za_zz_s1x2
            IEM_INSTR_IMPL_A64__fmop4a_za_zz_s1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80000200: FMOP4A  <ZAda>.S, { <Zn1>.S-<Zn2>.S }, <Zm>.S
   Instruction Set: A64  Groups: mortlach_f32f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za_zz_s2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80000200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za_zz_s2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za_zz_s2x1
            IEM_INSTR_IMPL_A64__fmop4a_za_zz_s2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80100200: FMOP4A  <ZAda>.S, { <Zn1>.S-<Zn2>.S }, { <Zm1>.S-<Zm2>.S }
   Instruction Set: A64  Groups: mortlach_f32f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4a_za_zz_s2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80100200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4a_za_zz_s2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4a_za_zz_s2x2
            IEM_INSTR_IMPL_A64__fmop4a_za_zz_s2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81200010: FMOP4S  <ZAda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_f16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za32_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81200010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za32_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za32_zz_h1x1
            IEM_INSTR_IMPL_A64__fmop4s_za32_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81300010: FMOP4S  <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_f16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za32_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81300010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za32_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za32_zz_h1x2
            IEM_INSTR_IMPL_A64__fmop4s_za32_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81200210: FMOP4S  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_f16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za32_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81200210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za32_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za32_zz_h2x1
            IEM_INSTR_IMPL_A64__fmop4s_za32_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81300210: FMOP4S  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_f16f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za32_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81300210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za32_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za32_zz_h2x2
            IEM_INSTR_IMPL_A64__fmop4s_za32_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/80c00018: FMOP4S  <ZAda>.D, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: mortlach_f64f64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za_zz_d1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0x80c00018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za_zz_d1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za_zz_d1x1
            IEM_INSTR_IMPL_A64__fmop4s_za_zz_d1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/80d00018: FMOP4S  <ZAda>.D, <Zn>.D, { <Zm1>.D-<Zm2>.D }
   Instruction Set: A64  Groups: mortlach_f64f64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za_zz_d1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0x80d00018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za_zz_d1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za_zz_d1x2
            IEM_INSTR_IMPL_A64__fmop4s_za_zz_d1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/80c00218: FMOP4S  <ZAda>.D, { <Zn1>.D-<Zn2>.D }, <Zm>.D
   Instruction Set: A64  Groups: mortlach_f64f64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za_zz_d2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0x80c00218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za_zz_d2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za_zz_d2x1
            IEM_INSTR_IMPL_A64__fmop4s_za_zz_d2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/80d00218: FMOP4S  <ZAda>.D, { <Zn1>.D-<Zn2>.D }, { <Zm1>.D-<Zm2>.D }
   Instruction Set: A64  Groups: mortlach_f64f64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za_zz_d2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0x80d00218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za_zz_d2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za_zz_d2x2
            IEM_INSTR_IMPL_A64__fmop4s_za_zz_d2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81000018: FMOP4S  <ZAda>.H, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_f16f16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81000018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za_zz_h1x1
            IEM_INSTR_IMPL_A64__fmop4s_za_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81100018: FMOP4S  <ZAda>.H, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_f16f16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81100018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za_zz_h1x2
            IEM_INSTR_IMPL_A64__fmop4s_za_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81000218: FMOP4S  <ZAda>.H, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_f16f16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81000218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za_zz_h2x1
            IEM_INSTR_IMPL_A64__fmop4s_za_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3e/81100218: FMOP4S  <ZAda>.H, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_f16f16_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3e)) == UINT32_C(0x81100218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za_zz_h2x2
            IEM_INSTR_IMPL_A64__fmop4s_za_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80000010: FMOP4S  <ZAda>.S, <Zn>.S, <Zm>.S
   Instruction Set: A64  Groups: mortlach_f32f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za_zz_s1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80000010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za_zz_s1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za_zz_s1x1
            IEM_INSTR_IMPL_A64__fmop4s_za_zz_s1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80100010: FMOP4S  <ZAda>.S, <Zn>.S, { <Zm1>.S-<Zm2>.S }
   Instruction Set: A64  Groups: mortlach_f32f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za_zz_s1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80100010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za_zz_s1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za_zz_s1x2
            IEM_INSTR_IMPL_A64__fmop4s_za_zz_s1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80000210: FMOP4S  <ZAda>.S, { <Zn1>.S-<Zn2>.S }, <Zm>.S
   Instruction Set: A64  Groups: mortlach_f32f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za_zz_s2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80000210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za_zz_s2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za_zz_s2x1
            IEM_INSTR_IMPL_A64__fmop4s_za_zz_s2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80100210: FMOP4S  <ZAda>.S, { <Zn1>.S-<Zn2>.S }, { <Zm1>.S-<Zm2>.S }
   Instruction Set: A64  Groups: mortlach_f32f32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmop4s_za_zz_s2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80100210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: fmop4s_za_zz_s2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__fmop4s_za_zz_s2x2
            IEM_INSTR_IMPL_A64__fmop4s_za_zz_s2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001e/80a00008: FMOPA  <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_f8f16_prod, mortlach2_misc_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmopa_za16_pp_z8z8_8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001e)) == UINT32_C(0x80a00008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fmopa_za16_pp_z8z8_8 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmopa_za16_pp_z8z8_8
            IEM_INSTR_IMPL_A64__fmopa_za16_pp_z8z8_8(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/80a00000: FMOPA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_f8f32_prod, mortlach_32bit_fp_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmopa_za32_pp_z8z8_8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0x80a00000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fmopa_za32_pp_z8z8_8 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmopa_za32_pp_z8z8_8
            IEM_INSTR_IMPL_A64__fmopa_za32_pp_z8z8_8(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/81a00000: FMOPA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_f16f32_prod, mortlach_32bit_fp_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmopa_za32_pp_zz_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0x81a00000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmopa_za32_pp_zz_16 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmopa_za32_pp_zz_16
            IEM_INSTR_IMPL_A64__fmopa_za32_pp_zz_16(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001e/81800008: FMOPA  <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_f16f16_prod, mortlach2_misc_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmopa_za_pp_zz_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001e)) == UINT32_C(0x81800008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmopa_za_pp_zz_16 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmopa_za_pp_zz_16
            IEM_INSTR_IMPL_A64__fmopa_za_pp_zz_16(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/80800000: FMOPA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S, <Zm>.S
   Instruction Set: A64  Groups: mortlach_f32f32_prod, mortlach_32bit_fp_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmopa_za_pp_zz_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fmopa_za_pp_zz_32 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmopa_za_pp_zz_32
        IEM_INSTR_IMPL_A64__fmopa_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00018/80c00000: FMOPA  <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: mortlach_f64f64_prod, mortlach_64bit_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmopa_za_pp_zz_64, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
    {
        LogFlow(("%018x/%010x: fmopa_za_pp_zz_64 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmopa_za_pp_zz_64
        IEM_INSTR_IMPL_A64__fmopa_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/81a00010: FMOPS  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_f16f32_prod, mortlach_32bit_fp_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmops_za32_pp_zz_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0x81a00010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmops_za32_pp_zz_16 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmops_za32_pp_zz_16
            IEM_INSTR_IMPL_A64__fmops_za32_pp_zz_16(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001e/81800018: FMOPS  <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_f16f16_prod, mortlach2_misc_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmops_za_pp_zz_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001e)) == UINT32_C(0x81800018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/)
        {
            LogFlow(("%018x/%010x: fmops_za_pp_zz_16 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmops_za_pp_zz_16
            IEM_INSTR_IMPL_A64__fmops_za_pp_zz_16(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/80800010: FMOPS  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S, <Zm>.S
   Instruction Set: A64  Groups: mortlach_f32f32_prod, mortlach_32bit_fp_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmops_za_pp_zz_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fmops_za_pp_zz_32 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmops_za_pp_zz_32
        IEM_INSTR_IMPL_A64__fmops_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00018/80c00010: FMOPS  <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: mortlach_f64f64_prod, mortlach_64bit_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmops_za_pp_zz_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00018)) == UINT32_C(0x80c00010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF64F64 /*FEAT_SME_F64F64*/)
        {
            LogFlow(("%018x/%010x: fmops_za_pp_zz_64 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__fmops_za_pp_zz_64
            IEM_INSTR_IMPL_A64__fmops_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/6520a000: FMSB  <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_zds_b, sve_fp_fma, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmsb_z_p_zzz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const N          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Za         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fmsb_z_p_zzz Zdn=%#x Zm=%#x Pg=%u op=%u N=%u Za=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, op, N, Za, size));
#ifdef IEM_INSTR_IMPL_A64__fmsb_z_p_zzz
        IEM_INSTR_IMPL_A64__fmsb_z_p_zzz(Zdn, Zm, Pg, op, N, Za, size);
#else
        RT_NOREF(Zdn, Zm, Pg, op, N, Za, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21fc21/c120e800: FMUL  { <Zd1>.<T>-<Zd2>.<T> }, { <Zn1>.<T>-<Zn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_fmul_sm, mortlach_multi_sve_5b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmul_mz_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/ && size != 0)
    {
        LogFlow(("%018x/%010x: fmul_mz_zzv_2x1 Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmul_mz_zzv_2x1
        IEM_INSTR_IMPL_A64__fmul_mz_zzv_2x1(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21fc63/c121e800: FMUL  { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<T>-<Zn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_fmul_sm, mortlach_multi_sve_5b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmul_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/ && size != 0)
    {
        LogFlow(("%018x/%010x: fmul_mz_zzv_4x1 Zd=%u Zn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmul_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__fmul_mz_zzv_4x1(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21fc21/c120e400: FMUL  { <Zd1>.<T>-<Zd2>.<T> }, { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_fmul_mm, mortlach_multi_sve_5a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmul_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/ && size != 0)
    {
        LogFlow(("%018x/%010x: fmul_mz_zzw_2x2 Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmul_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__fmul_mz_zzw_2x2(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23fc63/c121e400: FMUL  { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_fmul_mm, mortlach_multi_sve_5a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fmul_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/ && size != 0)
    {
        LogFlow(("%018x/%010x: fmul_mz_zzw_4x4 Zd=%u Zn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmul_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__fmul_mz_zzw_4x4(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe3c0/651a8000: FMUL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
   Instruction Set: A64  Groups: sve_fp_2op_i_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmul_z_p_zs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe3c0)) == UINT32_C(0x651a8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const i1         = (uOpcode >>  5) & 0x00000001;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmul_z_p_zs Zdn=%#x i1=%u Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, i1, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmul_z_p_zs
            IEM_INSTR_IMPL_A64__fmul_z_p_zs(Zdn, i1, Pg, size);
#else
            RT_NOREF(Zdn, i1, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65028000: FMUL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmul_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fmul_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmul_z_p_zz
        IEM_INSTR_IMPL_A64__fmul_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/65000800: FMUL  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_u_zd, sve_fp_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmul_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fmul_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fmul_z_zz
        IEM_INSTR_IMPL_A64__fmul_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64e02000: FMUL  <Zd>.D, <Zn>.D, <Zm>.D[<imm>]
   Instruction Set: A64  Groups: sve_fp_fmul_by_indexed_elem_lvl2, sve_fp_fmul_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmul_z_zzi_d, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fmul_z_zzi_d Zd=%#x Zn=%#x Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__fmul_z_zzi_d
        IEM_INSTR_IMPL_A64__fmul_z_zzi_d(Zd, Zn, Zm, i1);
#else
        RT_NOREF(Zd, Zn, Zm, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/64202000: FMUL  <Zd>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_fp_fmul_by_indexed_elem_lvl2, sve_fp_fmul_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmul_z_zzi_h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x64202000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmul_z_zzi_h Zd=%#x Zn=%#x Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__fmul_z_zzi_h
            IEM_INSTR_IMPL_A64__fmul_z_zzi_h(Zd, Zn, Zm, i3l, i3h);
#else
            RT_NOREF(Zd, Zn, Zm, i3l, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/64a02000: FMUL  <Zd>.S, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_fp_fmul_by_indexed_elem_lvl2, sve_fp_fmul_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmul_z_zzi_s, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: fmul_z_zzi_s Zd=%#x Zn=%#x Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__fmul_z_zzi_s
        IEM_INSTR_IMPL_A64__fmul_z_zzi_s(Zd, Zn, Zm, i2);
#else
        RT_NOREF(Zd, Zn, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/650a8000: FMULX  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fmulx_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x650a8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fmulx_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fmulx_z_p_zz
            IEM_INSTR_IMPL_A64__fmulx_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/041da000: FNEG  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_fneg_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x041da000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fneg_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fneg_z_p_z_m
            IEM_INSTR_IMPL_A64__fneg_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040da000: FNEG  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_fneg_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040da000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fneg_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fneg_z_p_z_z
            IEM_INSTR_IMPL_A64__fneg_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/6520c000: FNMAD  <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_zds_b, sve_fp_fma, sve */
FNIEMOP_DEF_1(iemDecodeA64_fnmad_z_p_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x6520c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const N          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Za         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fnmad_z_p_zzz Zdn=%#x Zm=%#x Pg=%u op=%u N=%u Za=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, op, N, Za, size));
#ifdef IEM_INSTR_IMPL_A64__fnmad_z_p_zzz
            IEM_INSTR_IMPL_A64__fnmad_z_p_zzz(Zdn, Zm, Pg, op, N, Za, size);
#else
            RT_NOREF(Zdn, Zm, Pg, op, N, Za, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/65204000: FNMLA  <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_zds_a, sve_fp_fma, sve */
FNIEMOP_DEF_1(iemDecodeA64_fnmla_z_p_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const op         = (uOpcode >> 13) & 0x00000001;
    uint32_t const N          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fnmla_z_p_zzz Zda=%#x Zn=%#x Pg=%u op=%u N=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Pg, op, N, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fnmla_z_p_zzz
        IEM_INSTR_IMPL_A64__fnmla_z_p_zzz(Zda, Zn, Pg, op, N, Zm, size);
#else
        RT_NOREF(Zda, Zn, Pg, op, N, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/65206000: FNMLS  <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_zds_a, sve_fp_fma, sve */
FNIEMOP_DEF_1(iemDecodeA64_fnmls_z_p_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x65206000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const N          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
        {
            LogFlow(("%018x/%010x: fnmls_z_p_zzz Zda=%#x Zn=%#x Pg=%u op=%u N=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Pg, op, N, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fnmls_z_p_zzz
            IEM_INSTR_IMPL_A64__fnmls_z_p_zzz(Zda, Zn, Pg, op, N, Zm, size);
#else
            RT_NOREF(Zda, Zn, Pg, op, N, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/6520e000: FNMSB  <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_p_zds_b, sve_fp_fma, sve */
FNIEMOP_DEF_1(iemDecodeA64_fnmsb_z_p_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x6520e000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const op         = (uOpcode >> 13) & 0x00000001;
        uint32_t const N          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Za         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fnmsb_z_p_zzz Zdn=%#x Zm=%#x Pg=%u op=%u N=%u Za=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, op, N, Za, size));
#ifdef IEM_INSTR_IMPL_A64__fnmsb_z_p_zzz
            IEM_INSTR_IMPL_A64__fnmsb_z_p_zzz(Zdn, Zm, Pg, op, N, Za, size);
#else
            RT_NOREF(Zdn, Zm, Pg, op, N, Za, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/650e3000: FRECPE  <Zd>.<T>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_u_zd, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_frecpe_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x650e3000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: frecpe_z_z Zd=%#x Zn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size));
#ifdef IEM_INSTR_IMPL_A64__frecpe_z_z
            IEM_INSTR_IMPL_A64__frecpe_z_z(Zd, Zn, size);
#else
            RT_NOREF(Zd, Zn, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/65001800: FRECPS  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_u_zd, sve_fp_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_frecps_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x65001800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: frecps_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__frecps_z_zz
            IEM_INSTR_IMPL_A64__frecps_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/650ca000: FRECPX  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_b_1, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frecpx_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x650ca000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: frecpx_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frecpx_z_p_z_m
            IEM_INSTR_IMPL_A64__frecpx_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/641b8000: FRECPX  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_b_1, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frecpx_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x641b8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frecpx_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frecpx_z_p_z_z
            IEM_INSTR_IMPL_A64__frecpx_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffde000/6511a000: FRINT32X  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frint32x_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffde000)) == UINT32_C(0x6511a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 17) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frint32x_z_p_z_m Zd=%#x Zn=%#x Pg=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, sz));
#ifdef IEM_INSTR_IMPL_A64__frint32x_z_p_z_m
            IEM_INSTR_IMPL_A64__frint32x_z_p_z_m(Zd, Zn, Pg, sz);
#else
            RT_NOREF(Zd, Zn, Pg, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffa000/641ca000: FRINT32X  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frint32x_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffa000)) == UINT32_C(0x641ca000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 14) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frint32x_z_p_z_z Zd=%#x Zn=%#x Pg=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, sz));
#ifdef IEM_INSTR_IMPL_A64__frint32x_z_p_z_z
            IEM_INSTR_IMPL_A64__frint32x_z_p_z_z(Zd, Zn, Pg, sz);
#else
            RT_NOREF(Zd, Zn, Pg, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffde000/6510a000: FRINT32Z  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frint32z_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffde000)) == UINT32_C(0x6510a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 17) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frint32z_z_p_z_m Zd=%#x Zn=%#x Pg=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, sz));
#ifdef IEM_INSTR_IMPL_A64__frint32z_z_p_z_m
            IEM_INSTR_IMPL_A64__frint32z_z_p_z_m(Zd, Zn, Pg, sz);
#else
            RT_NOREF(Zd, Zn, Pg, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffa000/641c8000: FRINT32Z  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frint32z_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffa000)) == UINT32_C(0x641c8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 14) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frint32z_z_p_z_z Zd=%#x Zn=%#x Pg=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, sz));
#ifdef IEM_INSTR_IMPL_A64__frint32z_z_p_z_z
            IEM_INSTR_IMPL_A64__frint32z_z_p_z_z(Zd, Zn, Pg, sz);
#else
            RT_NOREF(Zd, Zn, Pg, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffde000/6515a000: FRINT64X  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frint64x_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffde000)) == UINT32_C(0x6515a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 17) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frint64x_z_p_z_m Zd=%#x Zn=%#x Pg=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, sz));
#ifdef IEM_INSTR_IMPL_A64__frint64x_z_p_z_m
            IEM_INSTR_IMPL_A64__frint64x_z_p_z_m(Zd, Zn, Pg, sz);
#else
            RT_NOREF(Zd, Zn, Pg, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffa000/641da000: FRINT64X  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frint64x_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffa000)) == UINT32_C(0x641da000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 14) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frint64x_z_p_z_z Zd=%#x Zn=%#x Pg=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, sz));
#ifdef IEM_INSTR_IMPL_A64__frint64x_z_p_z_z
            IEM_INSTR_IMPL_A64__frint64x_z_p_z_z(Zd, Zn, Pg, sz);
#else
            RT_NOREF(Zd, Zn, Pg, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffde000/6514a000: FRINT64Z  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frint64z_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffde000)) == UINT32_C(0x6514a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 17) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frint64z_z_p_z_m Zd=%#x Zn=%#x Pg=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, sz));
#ifdef IEM_INSTR_IMPL_A64__frint64z_z_p_z_m
            IEM_INSTR_IMPL_A64__frint64z_z_p_z_m(Zd, Zn, Pg, sz);
#else
            RT_NOREF(Zd, Zn, Pg, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffa000/641d8000: FRINT64Z  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frint64z_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffa000)) == UINT32_C(0x641d8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 14) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frint64z_z_p_z_z Zd=%#x Zn=%#x Pg=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, sz));
#ifdef IEM_INSTR_IMPL_A64__frint64z_z_p_z_z
            IEM_INSTR_IMPL_A64__frint64z_z_p_z_z(Zd, Zn, Pg, sz);
#else
            RT_NOREF(Zd, Zn, Pg, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc21/c1ace000: FRINTA  { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_frint, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_frinta_mz_z_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc21)) == UINT32_C(0xc1ace000))
    {
        uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: frinta_mz_z_2 Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__frinta_mz_z_2
            IEM_INSTR_IMPL_A64__frinta_mz_z_2(Zd, Zn);
#else
            RT_NOREF(Zd, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc63/c1bce000: FRINTA  { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S }
   Instruction Set: A64  Groups: mortlach_multi4_frint, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_frinta_mz_z_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc63)) == UINT32_C(0xc1bce000))
    {
        uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: frinta_mz_z_4 Zd=%u Zn=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__frinta_mz_z_4
            IEM_INSTR_IMPL_A64__frinta_mz_z_4(Zd, Zn);
#else
            RT_NOREF(Zd, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6504a000: FRINTA  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_a, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frinta_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6504a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: frinta_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frinta_z_p_z_m
            IEM_INSTR_IMPL_A64__frinta_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/64198000: FRINTA  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_a, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frinta_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x64198000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frinta_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frinta_z_p_z_z
            IEM_INSTR_IMPL_A64__frinta_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6507a000: FRINTI  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_a, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frinti_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6507a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: frinti_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frinti_z_p_z_m
            IEM_INSTR_IMPL_A64__frinti_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6419e000: FRINTI  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_a, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frinti_z_p_z_z, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
    {
        LogFlow(("%018x/%010x: frinti_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frinti_z_p_z_z
        IEM_INSTR_IMPL_A64__frinti_z_p_z_z(Zd, Zn, Pg, size);
#else
        RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc21/c1aae000: FRINTM  { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_frint, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_frintm_mz_z_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc21)) == UINT32_C(0xc1aae000))
    {
        uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: frintm_mz_z_2 Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__frintm_mz_z_2
            IEM_INSTR_IMPL_A64__frintm_mz_z_2(Zd, Zn);
#else
            RT_NOREF(Zd, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc63/c1bae000: FRINTM  { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S }
   Instruction Set: A64  Groups: mortlach_multi4_frint, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_frintm_mz_z_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc63)) == UINT32_C(0xc1bae000))
    {
        uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: frintm_mz_z_4 Zd=%u Zn=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__frintm_mz_z_4
            IEM_INSTR_IMPL_A64__frintm_mz_z_4(Zd, Zn);
#else
            RT_NOREF(Zd, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6502a000: FRINTM  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_a, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frintm_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6502a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: frintm_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frintm_z_p_z_m
            IEM_INSTR_IMPL_A64__frintm_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6418c000: FRINTM  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_a, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frintm_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6418c000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frintm_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frintm_z_p_z_z
            IEM_INSTR_IMPL_A64__frintm_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc21/c1a8e000: FRINTN  { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_frint, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_frintn_mz_z_2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: frintn_mz_z_2 Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__frintn_mz_z_2
        IEM_INSTR_IMPL_A64__frintn_mz_z_2(Zd, Zn);
#else
        RT_NOREF(Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc63/c1b8e000: FRINTN  { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S }
   Instruction Set: A64  Groups: mortlach_multi4_frint, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_frintn_mz_z_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc63)) == UINT32_C(0xc1b8e000))
    {
        uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: frintn_mz_z_4 Zd=%u Zn=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__frintn_mz_z_4
            IEM_INSTR_IMPL_A64__frintn_mz_z_4(Zd, Zn);
#else
            RT_NOREF(Zd, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6500a000: FRINTN  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_a, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frintn_z_p_z_m, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: frintn_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frintn_z_p_z_m
        IEM_INSTR_IMPL_A64__frintn_z_p_z_m(Zd, Zn, Pg, size);
#else
        RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/64188000: FRINTN  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_a, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frintn_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x64188000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frintn_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frintn_z_p_z_z
            IEM_INSTR_IMPL_A64__frintn_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc21/c1a9e000: FRINTP  { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_frint, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_frintp_mz_z_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc21)) == UINT32_C(0xc1a9e000))
    {
        uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: frintp_mz_z_2 Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__frintp_mz_z_2
            IEM_INSTR_IMPL_A64__frintp_mz_z_2(Zd, Zn);
#else
            RT_NOREF(Zd, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc63/c1b9e000: FRINTP  { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S }
   Instruction Set: A64  Groups: mortlach_multi4_frint, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_frintp_mz_z_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc63)) == UINT32_C(0xc1b9e000))
    {
        uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: frintp_mz_z_4 Zd=%u Zn=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__frintp_mz_z_4
            IEM_INSTR_IMPL_A64__frintp_mz_z_4(Zd, Zn);
#else
            RT_NOREF(Zd, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6501a000: FRINTP  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_a, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frintp_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6501a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: frintp_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frintp_z_p_z_m
            IEM_INSTR_IMPL_A64__frintp_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6418a000: FRINTP  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_a, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frintp_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6418a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frintp_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frintp_z_p_z_z
            IEM_INSTR_IMPL_A64__frintp_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6506a000: FRINTX  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_a, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frintx_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6506a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: frintx_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frintx_z_p_z_m
            IEM_INSTR_IMPL_A64__frintx_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6419c000: FRINTX  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_a, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frintx_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6419c000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: frintx_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frintx_z_p_z_z
            IEM_INSTR_IMPL_A64__frintx_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6503a000: FRINTZ  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_a, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frintz_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6503a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: frintz_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frintz_z_p_z_m
            IEM_INSTR_IMPL_A64__frintz_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/6418e000: FRINTZ  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_a, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_frintz_z_p_z_z, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
    {
        LogFlow(("%018x/%010x: frintz_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__frintz_z_p_z_z
        IEM_INSTR_IMPL_A64__frintz_z_p_z_z(Zd, Zn, Pg, size);
#else
        RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/650f3000: FRSQRTE  <Zd>.<T>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_u_zd, sve_fp_unary_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_frsqrte_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x650f3000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: frsqrte_z_z Zd=%#x Zn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size));
#ifdef IEM_INSTR_IMPL_A64__frsqrte_z_z
            IEM_INSTR_IMPL_A64__frsqrte_z_z(Zd, Zn, size);
#else
            RT_NOREF(Zd, Zn, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/65001c00: FRSQRTS  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_u_zd, sve_fp_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_frsqrts_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x65001c00))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: frsqrts_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__frsqrts_z_zz
            IEM_INSTR_IMPL_A64__frsqrts_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a180: FSCALE  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fscale_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fscale_mz_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/ && size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fscale_mz_zzv_2x1 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fscale_mz_zzv_2x1
        IEM_INSTR_IMPL_A64__fscale_mz_zzv_2x1(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120a980: FSCALE  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fscale_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fscale_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/ && size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fscale_mz_zzv_4x1 Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fscale_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__fscale_mz_zzv_4x1(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b180: FSCALE  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_fscale_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_fscale_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/ && size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fscale_mz_zzw_2x2 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fscale_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__fscale_mz_zzw_2x2(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120b980: FSCALE  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_fscale_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_fscale_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_FP8*/ && size != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: fscale_mz_zzw_4x4 Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fscale_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__fscale_mz_zzw_4x4(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65098000: FSCALE  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fscale_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fscale_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fscale_z_p_zz
        IEM_INSTR_IMPL_A64__fscale_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/650da000: FSQRT  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_b_1, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fsqrt_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x650da000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fsqrt_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fsqrt_z_p_z_m
            IEM_INSTR_IMPL_A64__fsqrt_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/641ba000: FSQRT  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_b_1, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_fsqrt_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x641ba000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: fsqrt_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fsqrt_z_p_z_z
            IEM_INSTR_IMPL_A64__fsqrt_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe3c0/65198000: FSUB  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
   Instruction Set: A64  Groups: sve_fp_2op_i_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fsub_z_p_zs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe3c0)) == UINT32_C(0x65198000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const i1         = (uOpcode >>  5) & 0x00000001;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fsub_z_p_zs Zdn=%#x i1=%u Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, i1, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fsub_z_p_zs
            IEM_INSTR_IMPL_A64__fsub_z_p_zs(Zdn, i1, Pg, size);
#else
            RT_NOREF(Zdn, i1, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65018000: FSUB  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fsub_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fsub_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fsub_z_p_zz
        IEM_INSTR_IMPL_A64__fsub_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/65000400: FSUB  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_u_zd, sve_fp_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fsub_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: fsub_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__fsub_z_zz
        IEM_INSTR_IMPL_A64__fsub_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbf9c38/c1a01c08: FSUB  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_float_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fsub_za_zw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbf9c38)) == UINT32_C(0xc1a01c08))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zm         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fsub_za_zw_2x2 off3=%u S=%u Zm=%#x Rv=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv, sz));
#ifdef IEM_INSTR_IMPL_A64__fsub_za_zw_2x2
            IEM_INSTR_IMPL_A64__fsub_za_zw_2x2(off3, S, Zm, Rv, sz);
#else
            RT_NOREF(off3, S, Zm, Rv, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9c38/c1a41c08: FSUB  ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_f16_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_fsub_za_zw_2x2_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9c38)) == UINT32_C(0xc1a41c08))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zm         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fsub_za_zw_2x2_16 off3=%u S=%u Zm=%#x Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv));
#ifdef IEM_INSTR_IMPL_A64__fsub_za_zw_2x2_16
            IEM_INSTR_IMPL_A64__fsub_za_zw_2x2_16(off3, S, Zm, Rv);
#else
            RT_NOREF(off3, S, Zm, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbf9c78/c1a11c08: FSUB  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_float_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fsub_za_zw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbf9c78)) == UINT32_C(0xc1a11c08))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zm         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fsub_za_zw_4x4 off3=%u S=%u Zm=%u Rv=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv, sz));
#ifdef IEM_INSTR_IMPL_A64__fsub_za_zw_4x4
            IEM_INSTR_IMPL_A64__fsub_za_zw_4x4(off3, S, Zm, Rv, sz);
#else
            RT_NOREF(off3, S, Zm, Rv, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9c78/c1a51c08: FSUB  ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_f16_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_fsub_za_zw_4x4_16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9c78)) == UINT32_C(0xc1a51c08))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zm         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fsub_za_zw_4x4_16 off3=%u S=%u Zm=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv));
#ifdef IEM_INSTR_IMPL_A64__fsub_za_zw_4x4_16
            IEM_INSTR_IMPL_A64__fsub_za_zw_4x4_16(off3, S, Zm, Rv);
#else
            RT_NOREF(off3, S, Zm, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe3c0/651b8000: FSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
   Instruction Set: A64  Groups: sve_fp_2op_i_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fsubr_z_p_zs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe3c0)) == UINT32_C(0x651b8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const i1         = (uOpcode >>  5) & 0x00000001;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fsubr_z_p_zs Zdn=%#x i1=%u Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, i1, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fsubr_z_p_zs
            IEM_INSTR_IMPL_A64__fsubr_z_p_zs(Zdn, i1, Pg, size);
#else
            RT_NOREF(Zdn, i1, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/65038000: FSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_2op_p_zds, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_fsubr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65038000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: fsubr_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__fsubr_z_p_zz
            IEM_INSTR_IMPL_A64__fsubr_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff38fc00/65108000: FTMAD  <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_fp_ftmad, sve_fp_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_ftmad_z_zzi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff38fc00)) == UINT32_C(0x65108000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ftmad_z_zzi Zdn=%#x Zm=%#x imm3=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, imm3, size));
#ifdef IEM_INSTR_IMPL_A64__ftmad_z_zzi
            IEM_INSTR_IMPL_A64__ftmad_z_zzi(Zdn, Zm, imm3, size);
#else
            RT_NOREF(Zdn, Zm, imm3, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00e/80600008: FTMOPA  <ZAda>.H, { <Zn1>.B-<Zn2>.B }, <Zm>.B, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_f8f16_2in4ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_ftmopa_za16_z8z8zi_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00e)) == UINT32_C(0x80600008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
        uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
        uint32_t const K          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
        {
            LogFlow(("%018x/%010x: ftmopa_za16_z8z8zi_b2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__ftmopa_za16_z8z8zi_b2x1
            IEM_INSTR_IMPL_A64__ftmopa_za16_z8z8zi_b2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
            RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/80600000: FTMOPA  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_f8f32_2in4ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_ftmopa_za32_z8z8zi_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0x80600000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
        uint32_t const K          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
        {
            LogFlow(("%018x/%010x: ftmopa_za32_z8z8zi_b2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__ftmopa_za32_z8z8zi_b2x1
            IEM_INSTR_IMPL_A64__ftmopa_za32_z8z8zi_b2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
            RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/81600000: FTMOPA  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_f16f32_2in4ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_ftmopa_za32_zzzi_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0x81600000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
        uint32_t const K          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
        {
            LogFlow(("%018x/%010x: ftmopa_za32_zzzi_h2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__ftmopa_za32_zzzi_h2x1
            IEM_INSTR_IMPL_A64__ftmopa_za32_zzzi_h2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
            RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00e/81400008: FTMOPA  <ZAda>.H, { <Zn1>.H-<Zn2>.H }, <Zm>.H, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_f16f16_1in2ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_ftmopa_za_zzzi_h2x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000001;
    uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
    uint32_t const K          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeF16F16 /*FEAT_SME_F16F16*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
    {
        LogFlow(("%018x/%010x: ftmopa_za_zzzi_h2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__ftmopa_za_zzzi_h2x1
        IEM_INSTR_IMPL_A64__ftmopa_za_zzzi_h2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
        RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/80400000: FTMOPA  <ZAda>.S, { <Zn1>.S-<Zn2>.S }, <Zm>.S, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_f32f32_1in2ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_ftmopa_za_zzzi_s2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0x80400000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
        uint32_t const K          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
        {
            LogFlow(("%018x/%010x: ftmopa_za_zzzi_s2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__ftmopa_za_zzzi_s2x1
            IEM_INSTR_IMPL_A64__ftmopa_za_zzzi_s2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
            RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/65000c00: FTSMUL  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_fp_3op_u_zd, sve_fp_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_ftsmul_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x65000c00))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ftsmul_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__ftsmul_z_zz
            IEM_INSTR_IMPL_A64__ftsmul_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/0420b000: FTSSEL  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_cons_misc_0_b, sve_int_unpred_misc, sve */
FNIEMOP_DEF_1(iemDecodeA64_ftssel_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ftssel_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__ftssel_z_zz
        IEM_INSTR_IMPL_A64__ftssel_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09030/c1d01020: FVDOT  ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_fp8_fdot_idx, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fvdot_za_z8z8i_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09030)) == UINT32_C(0xc1d01020))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i3l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F16*/)
        {
            LogFlow(("%018x/%010x: fvdot_za_z8z8i_2xi off3=%u i3l=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i3l, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fvdot_za_z8z8i_2xi
            IEM_INSTR_IMPL_A64__fvdot_za_z8z8i_2xi(off3, i3l, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off3, i3l, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1500008: FVDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fvdot_za_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1500008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: fvdot_za_zzi_2xi off3=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fvdot_za_zzi_2xi
            IEM_INSTR_IMPL_A64__fvdot_za_zzi_2xi(off3, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09830/c1d00800: FVDOTB  ZA.S[<Wv>, <offs>, VGx4], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_fp8_fvdot_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fvdotb_za32_z8z8i_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09830)) == UINT32_C(0xc1d00800))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i2l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const T          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2h        = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fvdotb_za32_z8z8i_2xi off3=%u i2l=%u T=%u Zn=%#x i2h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i2l, T, Zn, i2h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fvdotb_za32_z8z8i_2xi
            IEM_INSTR_IMPL_A64__fvdotb_za32_z8z8i_2xi(off3, i2l, T, Zn, i2h, Rv, Zm);
#else
            RT_NOREF(off3, i2l, T, Zn, i2h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09830/c1d00810: FVDOTT  ZA.S[<Wv>, <offs>, VGx4], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_fp8_fvdot_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_fvdott_za32_z8z8i_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09830)) == UINT32_C(0xc1d00810))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const i2l        = (uOpcode >>  3) & 0x00000001;
        uint32_t const T          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2h        = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_F8F32*/)
        {
            LogFlow(("%018x/%010x: fvdott_za32_z8z8i_2xi off3=%u i2l=%u T=%u Zn=%#x i2h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, i2l, T, Zn, i2h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__fvdott_za32_z8z8i_2xi
            IEM_INSTR_IMPL_A64__fvdott_za32_z8z8i_2xi(off3, i2l, T, Zn, i2h, Rv, Zm);
#else
            RT_NOREF(off3, i2l, T, Zn, i2h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/4520c000: HISTCNT  <Zd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_histcnt_lvl2, sve_intx_histcnt, sve */
FNIEMOP_DEF_1(iemDecodeA64_histcnt_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x4520c000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
        {
            LogFlow(("%018x/%010x: histcnt_z_p_zz Zd=%#x Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__histcnt_z_p_zz
            IEM_INSTR_IMPL_A64__histcnt_z_p_zz(Zd, Zn, Pg, Zm, size);
#else
            RT_NOREF(Zd, Zn, Pg, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4520a000: HISTSEG  <Zd>.B, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_intx_histseg, sve_intx_histseg_lut, sve */
FNIEMOP_DEF_1(iemDecodeA64_histseg_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4520a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
        {
            LogFlow(("%018x/%010x: histseg_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__histseg_z_zz
            IEM_INSTR_IMPL_A64__histseg_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0430e000: INCB  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_a, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_incb_r_rs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0430e000))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: incb_r_rs Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__incb_r_rs
            IEM_INSTR_IMPL_A64__incb_r_rs(Rdn, pattern, imm4, size);
#else
            RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04f0e000: INCD  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_a, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_incd_r_rs, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: incd_r_rs Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__incd_r_rs
        IEM_INSTR_IMPL_A64__incd_r_rs(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04f0c000: INCD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv1, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_incd_z_zs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04f0c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: incd_z_zs Zdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__incd_z_zs
            IEM_INSTR_IMPL_A64__incd_z_zs(Zdn, pattern, imm4, size);
#else
            RT_NOREF(Zdn, pattern, imm4, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0470e000: INCH  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_a, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_inch_r_rs, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: inch_r_rs Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__inch_r_rs
        IEM_INSTR_IMPL_A64__inch_r_rs(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0470c000: INCH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv1, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_inch_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: inch_z_zs Zdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__inch_z_zs
        IEM_INSTR_IMPL_A64__inch_z_zs(Zdn, pattern, imm4, size);
#else
        RT_NOREF(Zdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/252c8800: INCP  <Xdn>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_r, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_incp_r_p_r, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x252c8800))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: incp_r_p_r Rdn=%#x Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__incp_r_p_r
            IEM_INSTR_IMPL_A64__incp_r_p_r(Rdn, Pm, size);
#else
            RT_NOREF(Rdn, Pm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/252c8000: INCP  <Zdn>.<T>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_v, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_incp_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x252c8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: incp_z_p_z Zdn=%#x Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__incp_z_p_z
            IEM_INSTR_IMPL_A64__incp_z_p_z(Zdn, Pm, size);
#else
            RT_NOREF(Zdn, Pm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04b0e000: INCW  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_a, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_incw_r_rs, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: incw_r_rs Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__incw_r_rs
        IEM_INSTR_IMPL_A64__incw_r_rs(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04b0c000: INCW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv1, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_incw_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: incw_z_zs Zdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__incw_z_zs
        IEM_INSTR_IMPL_A64__incw_z_zs(Zdn, pattern, imm4, size);
#else
        RT_NOREF(Zdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04204000: INDEX  <Zd>.<T>, #<imm1>, #<imm2>
   Instruction Set: A64  Groups: sve_int_index_ii, sve_index, sve */
FNIEMOP_DEF_1(iemDecodeA64_index_z_ii, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04204000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm5       = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm5b      = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: index_z_ii Zd=%#x imm5=%#x imm5b=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, imm5, imm5b, size));
#ifdef IEM_INSTR_IMPL_A64__index_z_ii
            IEM_INSTR_IMPL_A64__index_z_ii(Zd, imm5, imm5b, size);
#else
            RT_NOREF(Zd, imm5, imm5b, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04204800: INDEX  <Zd>.<T>, #<imm>, <R><m>
   Instruction Set: A64  Groups: sve_int_index_ir, sve_index, sve */
FNIEMOP_DEF_1(iemDecodeA64_index_z_ir, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04204800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm5       = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: index_z_ir Zd=%#x imm5=%#x Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, imm5, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__index_z_ir
            IEM_INSTR_IMPL_A64__index_z_ir(Zd, imm5, Rm, size);
#else
            RT_NOREF(Zd, imm5, Rm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04204400: INDEX  <Zd>.<T>, <R><n>, #<imm>
   Instruction Set: A64  Groups: sve_int_index_ri, sve_index, sve */
FNIEMOP_DEF_1(iemDecodeA64_index_z_ri, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: index_z_ri Zd=%#x Rn=%#x imm5=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Rn, imm5, size));
#ifdef IEM_INSTR_IMPL_A64__index_z_ri
        IEM_INSTR_IMPL_A64__index_z_ri(Zd, Rn, imm5, size);
#else
        RT_NOREF(Zd, Rn, imm5, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04204c00: INDEX  <Zd>.<T>, <R><n>, <R><m>
   Instruction Set: A64  Groups: sve_int_index_rr, sve_index, sve */
FNIEMOP_DEF_1(iemDecodeA64_index_z_rr, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: index_z_rr Zd=%#x Rn=%#x Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Rn, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__index_z_rr
        IEM_INSTR_IMPL_A64__index_z_rr(Zd, Rn, Rm, size);
#else
        RT_NOREF(Zd, Rn, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/05243800: INSR  <Zdn>.<T>, <R><m>
   Instruction Set: A64  Groups: sve_int_perm_insrs, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_insr_z_r, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: insr_z_r Zdn=%#x Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__insr_z_r
        IEM_INSTR_IMPL_A64__insr_z_r(Zdn, Rm, size);
#else
        RT_NOREF(Zdn, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/05343800: INSR  <Zdn>.<T>, <V><m>
   Instruction Set: A64  Groups: sve_int_perm_insrv, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_insr_z_v, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x05343800))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Vm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: insr_z_v Zdn=%#x Vm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Vm, size));
#ifdef IEM_INSTR_IMPL_A64__insr_z_v
            IEM_INSTR_IMPL_A64__insr_z_v(Zdn, Vm, size);
#else
            RT_NOREF(Zdn, Vm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0520a000: LASTA  <R><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_last_r, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_lasta_r_p_z, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const B          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: lasta_r_p_z Rd=%#x Zn=%#x Pg=%u B=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Zn, Pg, B, size));
#ifdef IEM_INSTR_IMPL_A64__lasta_r_p_z
        IEM_INSTR_IMPL_A64__lasta_r_p_z(Rd, Zn, Pg, B, size);
#else
        RT_NOREF(Rd, Zn, Pg, B, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/05228000: LASTA  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_last_v, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_lasta_v_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x05228000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const B          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: lasta_v_p_z Vd=%#x Zn=%#x Pg=%u B=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, B, size));
#ifdef IEM_INSTR_IMPL_A64__lasta_v_p_z
            IEM_INSTR_IMPL_A64__lasta_v_p_z(Vd, Zn, Pg, B, size);
#else
            RT_NOREF(Vd, Zn, Pg, B, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0521a000: LASTB  <R><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_last_r, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_lastb_r_p_z, uint32_t, uOpcode)
{
    uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const B          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: lastb_r_p_z Rd=%#x Zn=%#x Pg=%u B=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Zn, Pg, B, size));
#ifdef IEM_INSTR_IMPL_A64__lastb_r_p_z
        IEM_INSTR_IMPL_A64__lastb_r_p_z(Rd, Zn, Pg, B, size);
#else
        RT_NOREF(Rd, Zn, Pg, B, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/05238000: LASTB  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_last_v, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_lastb_v_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x05238000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const B          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: lastb_v_p_z Vd=%#x Zn=%#x Pg=%u B=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, B, size));
#ifdef IEM_INSTR_IMPL_A64__lastb_v_p_z
            IEM_INSTR_IMPL_A64__lastb_v_p_z(Vd, Zn, Pg, B, size);
#else
            RT_NOREF(Vd, Zn, Pg, B, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fc200/25228000: LASTP  <Xd>, <Pg>, <Pn>.<T>
   Instruction Set: A64  Groups: sve_int_pcount_pred, sve_pred_count_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_lastp_r_p_p, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fc200)) == UINT32_C(0x25228000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: lastp_r_p_p Rd=%#x Pn=%#x Pg=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, Pn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__lastp_r_p_p
            IEM_INSTR_IMPL_A64__lastp_r_p_p(Rd, Pn, Pg, size);
#else
            RT_NOREF(Rd, Pn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0400000: LD1B  { <Zt1>.B-<Zt2>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1b_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1b_mz_p_bi_2
        IEM_INSTR_IMPL_A64__ld1b_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a0408000: LD1B  { <Zt1>.B-<Zt4>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_mz_p_bi_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa0408000))
    {
        uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: ld1b_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1b_mz_p_bi_4
            IEM_INSTR_IMPL_A64__ld1b_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
            RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0000000: LD1B  { <Zt1>.B-<Zt2>.B }, <PNg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1b_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1b_mz_p_br_2
        IEM_INSTR_IMPL_A64__ld1b_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a0008000: LD1B  { <Zt1>.B-<Zt4>.B }, <PNg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1b_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1b_mz_p_br_4
        IEM_INSTR_IMPL_A64__ld1b_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1400000: LD1B  { <Zt1>.B, <Zt2>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1b_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1b_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__ld1b_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a1408000: LD1B  { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1b_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1b_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__ld1b_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1000000: LD1B  { <Zt1>.B, <Zt2>.B }, <PNg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1b_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1b_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__ld1b_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a1008000: LD1B  { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1b_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1b_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__ld1b_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c420c000: LD1B  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_ai_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc420c000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1b_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_ai_d
            IEM_INSTR_IMPL_A64__ld1b_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/8420c000: LD1B  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_ai_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x8420c000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1b_z_p_ai_s Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_ai_s
            IEM_INSTR_IMPL_A64__ld1b_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a420a000: LD1B  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_bi_u16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa420a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1b_z_p_bi_u16 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u16
            IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u16(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a440a000: LD1B  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_bi_u32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa440a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1b_z_p_bi_u32 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u32
            IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a460a000: LD1B  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_bi_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa460a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1b_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u64
            IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a400a000: LD1B  { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_bi_u8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1b_z_p_bi_u8 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u8
        IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u8(Zt, Rn, Pg, imm4, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4204000: LD1B  { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_br_u16, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1b_z_p_br_u16 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_br_u16
        IEM_INSTR_IMPL_A64__ld1b_z_p_br_u16(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4404000: LD1B  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_br_u32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4404000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld1b_z_p_br_u32 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_br_u32
            IEM_INSTR_IMPL_A64__ld1b_z_p_br_u32(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4604000: LD1B  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_br_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4604000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld1b_z_p_br_u64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_br_u64
            IEM_INSTR_IMPL_A64__ld1b_z_p_br_u64(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4004000: LD1B  { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_br_u8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1b_z_p_br_u8 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_br_u8
        IEM_INSTR_IMPL_A64__ld1b_z_p_br_u8(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c440c000: LD1B  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1b_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ld1b_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c4004000: LD1B  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc4004000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1b_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__ld1b_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/84004000: LD1B  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x84004000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (0x0 /*opc@23*/ != 3 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1b_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1b_z_p_bz_s_x32_unscaled
            IEM_INSTR_IMPL_A64__ld1b_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00010/e0000000: LD1B  { ZA0<HV>.B[<Ws>, <offs>] }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
   Instruction Set: A64  Groups: mortlach_contig_load, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1b_za_p_rrr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00010)) == UINT32_C(0xe0000000))
    {
        uint32_t const off4       = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1b_za_p_rrr off4=%#x Rn=%#x Pg=%u Rs=%u V=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off4, Rn, Pg, Rs, V, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1b_za_p_rrr
            IEM_INSTR_IMPL_A64__ld1b_za_p_rrr(off4, Rn, Pg, Rs, V, Rm);
#else
            RT_NOREF(off4, Rn, Pg, Rs, V, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0406000: LD1D  { <Zt1>.D-<Zt2>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_mz_p_bi_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0406000))
    {
        uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: ld1d_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1d_mz_p_bi_2
            IEM_INSTR_IMPL_A64__ld1d_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
            RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a040e000: LD1D  { <Zt1>.D-<Zt4>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_mz_p_bi_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa040e000))
    {
        uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: ld1d_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1d_mz_p_bi_4
            IEM_INSTR_IMPL_A64__ld1d_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
            RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0006000: LD1D  { <Zt1>.D-<Zt2>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1d_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1d_mz_p_br_2
        IEM_INSTR_IMPL_A64__ld1d_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a000e000: LD1D  { <Zt1>.D-<Zt4>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1d_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1d_mz_p_br_4
        IEM_INSTR_IMPL_A64__ld1d_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1406000: LD1D  { <Zt1>.D, <Zt2>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1d_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1d_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__ld1d_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a140e000: LD1D  { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1d_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1d_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__ld1d_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1006000: LD1D  { <Zt1>.D, <Zt2>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1d_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1d_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__ld1d_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a100e000: LD1D  { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1d_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1d_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__ld1d_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c5a0c000: LD1D  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_z_p_ai_d, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1d_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, imm5));
#ifdef IEM_INSTR_IMPL_A64__ld1d_z_p_ai_d
        IEM_INSTR_IMPL_A64__ld1d_z_p_ai_d(Zt, Zn, Pg, ff, imm5);
#else
        RT_NOREF(Zt, Zn, Pg, ff, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5902000: LD1D  { <Zt>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si_q, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_z_p_bi_u128, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1d_z_p_bi_u128 Zt=%#x Rn=%#x Pg=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1d_z_p_bi_u128
        IEM_INSTR_IMPL_A64__ld1d_z_p_bi_u128(Zt, Rn, Pg, imm4);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5e0a000: LD1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_z_p_bi_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5e0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1d_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1d_z_p_bi_u64
            IEM_INSTR_IMPL_A64__ld1d_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5808000: LD1D  { <Zt>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_cld_ss_q, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_z_p_br_u128, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (Rm != 0x1f && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1d_z_p_br_u128 Zt=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1d_z_p_br_u128
        IEM_INSTR_IMPL_A64__ld1d_z_p_br_u128(Zt, Rn, Pg, Rm);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5e04000: LD1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_z_p_br_u64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1d_z_p_br_u64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1d_z_p_br_u64
        IEM_INSTR_IMPL_A64__ld1d_z_p_br_u64(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c5e0c000: LD1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #3]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (0x3 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1d_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u ff=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, Zm));
#ifdef IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c5c0c000: LD1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1d_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, Zm));
#ifdef IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c5a04000: LD1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #3]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (0x3 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1d_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_x32_scaled
        IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c5804000: LD1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc5804000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1d_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00010/e0c00000: LD1D  { <ZAt><HV>.D[<Ws>, <offs>] }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #3}]
   Instruction Set: A64  Groups: mortlach_contig_load, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1d_za_p_rrr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00010)) == UINT32_C(0xe0c00000))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const ZAt        = (uOpcode >>  1) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1d_za_p_rrr o1=%u ZAt=%u Rn=%#x Pg=%u Rs=%u V=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, ZAt, Rn, Pg, Rs, V, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1d_za_p_rrr
            IEM_INSTR_IMPL_A64__ld1d_za_p_rrr(o1, ZAt, Rn, Pg, Rs, V, Rm);
#else
            RT_NOREF(o1, ZAt, Rn, Pg, Rs, V, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0402000: LD1H  { <Zt1>.H-<Zt2>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1h_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1h_mz_p_bi_2
        IEM_INSTR_IMPL_A64__ld1h_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a040a000: LD1H  { <Zt1>.H-<Zt4>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_mz_p_bi_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1h_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1h_mz_p_bi_4
        IEM_INSTR_IMPL_A64__ld1h_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0002000: LD1H  { <Zt1>.H-<Zt2>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1h_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1h_mz_p_br_2
        IEM_INSTR_IMPL_A64__ld1h_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a000a000: LD1H  { <Zt1>.H-<Zt4>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1h_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1h_mz_p_br_4
        IEM_INSTR_IMPL_A64__ld1h_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1402000: LD1H  { <Zt1>.H, <Zt2>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1h_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1h_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__ld1h_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a140a000: LD1H  { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1h_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1h_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__ld1h_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1002000: LD1H  { <Zt1>.H, <Zt2>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1h_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1h_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__ld1h_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a100a000: LD1H  { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1h_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1h_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__ld1h_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4a0c000: LD1H  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_ai_d, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1h_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_ai_d
        IEM_INSTR_IMPL_A64__ld1h_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5);
#else
        RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/84a0c000: LD1H  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_ai_s, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1h_z_p_ai_s Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_ai_s
        IEM_INSTR_IMPL_A64__ld1h_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5);
#else
        RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4a0a000: LD1H  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_bi_u16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4a0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1h_z_p_bi_u16 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_bi_u16
            IEM_INSTR_IMPL_A64__ld1h_z_p_bi_u16(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4c0a000: LD1H  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_bi_u32, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1h_z_p_bi_u32 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_bi_u32
        IEM_INSTR_IMPL_A64__ld1h_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4e0a000: LD1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_bi_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4e0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1h_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_bi_u64
            IEM_INSTR_IMPL_A64__ld1h_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4a04000: LD1H  { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_br_u16, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1h_z_p_br_u16 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_br_u16
        IEM_INSTR_IMPL_A64__ld1h_z_p_br_u16(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4c04000: LD1H  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_br_u32, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1h_z_p_br_u32 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_br_u32
        IEM_INSTR_IMPL_A64__ld1h_z_p_br_u32(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4e04000: LD1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_br_u64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1h_z_p_br_u64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_br_u64
        IEM_INSTR_IMPL_A64__ld1h_z_p_br_u64(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4e0c000: LD1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (0x1 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1h_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4c0c000: LD1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1h_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c4a04000: LD1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (0x1 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1h_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_x32_scaled
        IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c4804000: LD1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc4804000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1h_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/84a04000: LD1H  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1]
   Instruction Set: A64  Groups: sve_mem_32b_gld_sv_a, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_bz_s_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1h_z_p_bz_s_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_bz_s_x32_scaled
        IEM_INSTR_IMPL_A64__ld1h_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/84804000: LD1H  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x84804000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (0x1 /*opc@23*/ != 3 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1h_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1h_z_p_bz_s_x32_unscaled
            IEM_INSTR_IMPL_A64__ld1h_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00010/e0400000: LD1H  { <ZAt><HV>.H[<Ws>, <offs>] }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
   Instruction Set: A64  Groups: mortlach_contig_load, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1h_za_p_rrr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00010)) == UINT32_C(0xe0400000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const ZAt        = (uOpcode >>  3) & 0x00000001;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1h_za_p_rrr off3=%u ZAt=%u Rn=%#x Pg=%u Rs=%u V=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, ZAt, Rn, Pg, Rs, V, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1h_za_p_rrr
            IEM_INSTR_IMPL_A64__ld1h_za_p_rrr(off3, ZAt, Rn, Pg, Rs, V, Rm);
#else
            RT_NOREF(off3, ZAt, Rn, Pg, Rs, V, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c400a000: LD1Q  { <Zt>.Q }, <Pg>/Z, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gldq_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1q_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1q_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1q_z_p_ar_d_64_unscaled
        IEM_INSTR_IMPL_A64__ld1q_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00010/e1c00000: LD1Q  { <ZAt><HV>.Q[<Ws>, <offs>] }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #4}]
   Instruction Set: A64  Groups: mortlach_contig_qload, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1q_za_p_rrr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00010)) == UINT32_C(0xe1c00000))
    {
        uint32_t const ZAt        = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1q_za_p_rrr ZAt=%#x Rn=%#x Pg=%u Rs=%u V=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAt, Rn, Pg, Rs, V, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1q_za_p_rrr
            IEM_INSTR_IMPL_A64__ld1q_za_p_rrr(ZAt, Rn, Pg, Rs, V, Rm);
#else
            RT_NOREF(ZAt, Rn, Pg, Rs, V, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/8440a000: LD1RB  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rb_z_p_bi_u16, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rb_z_p_bi_u16 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u16
        IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u16(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
        RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/8440c000: LD1RB  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rb_z_p_bi_u32, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rb_z_p_bi_u32 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u32
        IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u32(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
        RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/8440e000: LD1RB  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rb_z_p_bi_u64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rb_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u64
        IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u64(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
        RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/84408000: LD1RB  { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rb_z_p_bi_u8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x84408000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
        uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1rb_z_p_bi_u8 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u8
            IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u8(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
            RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/85c0e000: LD1RD  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rd_z_p_bi_u64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rd_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rd_z_p_bi_u64
        IEM_INSTR_IMPL_A64__ld1rd_z_p_bi_u64(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
        RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/84c0a000: LD1RH  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rh_z_p_bi_u16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x84c0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
        uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1rh_z_p_bi_u16 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rh_z_p_bi_u16
            IEM_INSTR_IMPL_A64__ld1rh_z_p_bi_u16(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
            RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/84c0c000: LD1RH  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rh_z_p_bi_u32, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rh_z_p_bi_u32 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rh_z_p_bi_u32
        IEM_INSTR_IMPL_A64__ld1rh_z_p_bi_u32(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
        RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/84c0e000: LD1RH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rh_z_p_bi_u64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rh_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rh_z_p_bi_u64
        IEM_INSTR_IMPL_A64__ld1rh_z_p_bi_u64(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
        RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4202000: LD1ROB  { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ldqr_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rob_z_p_bi_u8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4202000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
        {
            LogFlow(("%018x/%010x: ld1rob_z_p_bi_u8 Zt=%#x Rn=%#x Pg=%u imm4=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1rob_z_p_bi_u8
            IEM_INSTR_IMPL_A64__ld1rob_z_p_bi_u8(Zt, Rn, Pg, imm4, ssz, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, ssz, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4200000: LD1ROB  { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_ldqr_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rob_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
    {
        LogFlow(("%018x/%010x: ld1rob_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1rob_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld1rob_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, ssz, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5a02000: LD1ROD  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ldqr_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rod_z_p_bi_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5a02000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
        {
            LogFlow(("%018x/%010x: ld1rod_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u imm4=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1rod_z_p_bi_u64
            IEM_INSTR_IMPL_A64__ld1rod_z_p_bi_u64(Zt, Rn, Pg, imm4, ssz, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, ssz, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5a00000: LD1ROD  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_ldqr_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rod_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5a00000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (Rm != 0x1f && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
        {
            LogFlow(("%018x/%010x: ld1rod_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1rod_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__ld1rod_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, ssz, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4a02000: LD1ROH  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ldqr_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1roh_z_p_bi_u16, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
    {
        LogFlow(("%018x/%010x: ld1roh_z_p_bi_u16 Zt=%#x Rn=%#x Pg=%u imm4=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1roh_z_p_bi_u16
        IEM_INSTR_IMPL_A64__ld1roh_z_p_bi_u16(Zt, Rn, Pg, imm4, ssz, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, ssz, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4a00000: LD1ROH  { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_ldqr_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1roh_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4a00000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (Rm != 0x1f && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
        {
            LogFlow(("%018x/%010x: ld1roh_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1roh_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__ld1roh_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, ssz, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5202000: LD1ROW  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ldqr_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1row_z_p_bi_u32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5202000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
        {
            LogFlow(("%018x/%010x: ld1row_z_p_bi_u32 Zt=%#x Rn=%#x Pg=%u imm4=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1row_z_p_bi_u32
            IEM_INSTR_IMPL_A64__ld1row_z_p_bi_u32(Zt, Rn, Pg, imm4, ssz, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, ssz, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5200000: LD1ROW  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_ldqr_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1row_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
    {
        LogFlow(("%018x/%010x: ld1row_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1row_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld1row_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, ssz, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4002000: LD1RQB  { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ldqr_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rqb_z_p_bi_u8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rqb_z_p_bi_u8 Zt=%#x Rn=%#x Pg=%u imm4=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1rqb_z_p_bi_u8
        IEM_INSTR_IMPL_A64__ld1rqb_z_p_bi_u8(Zt, Rn, Pg, imm4, ssz, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, ssz, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4000000: LD1RQB  { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_ldqr_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rqb_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1rqb_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1rqb_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld1rqb_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, ssz, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5802000: LD1RQD  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ldqr_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rqd_z_p_bi_u64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rqd_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u imm4=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1rqd_z_p_bi_u64
        IEM_INSTR_IMPL_A64__ld1rqd_z_p_bi_u64(Zt, Rn, Pg, imm4, ssz, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, ssz, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5800000: LD1RQD  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_ldqr_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rqd_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5800000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld1rqd_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1rqd_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__ld1rqd_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, ssz, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4802000: LD1RQH  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ldqr_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rqh_z_p_bi_u16, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rqh_z_p_bi_u16 Zt=%#x Rn=%#x Pg=%u imm4=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1rqh_z_p_bi_u16
        IEM_INSTR_IMPL_A64__ld1rqh_z_p_bi_u16(Zt, Rn, Pg, imm4, ssz, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, ssz, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4800000: LD1RQH  { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_ldqr_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rqh_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4800000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld1rqh_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1rqh_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__ld1rqh_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, ssz, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5002000: LD1RQW  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ldqr_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rqw_z_p_bi_u32, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rqw_z_p_bi_u32 Zt=%#x Rn=%#x Pg=%u imm4=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1rqw_z_p_bi_u32
        IEM_INSTR_IMPL_A64__ld1rqw_z_p_bi_u32(Zt, Rn, Pg, imm4, ssz, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, ssz, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5000000: LD1RQW  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_ldqr_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rqw_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const ssz        = (uOpcode >> 21) & 0x00000003;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1rqw_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x ssz=%u msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, ssz, msz));
#ifdef IEM_INSTR_IMPL_A64__ld1rqw_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld1rqw_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, ssz, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/85c0c000: LD1RSB  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rsb_z_p_bi_s16, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rsb_z_p_bi_s16 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rsb_z_p_bi_s16
        IEM_INSTR_IMPL_A64__ld1rsb_z_p_bi_s16(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
        RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/85c0a000: LD1RSB  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rsb_z_p_bi_s32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x85c0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
        uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1rsb_z_p_bi_s32 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rsb_z_p_bi_s32
            IEM_INSTR_IMPL_A64__ld1rsb_z_p_bi_s32(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
            RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/85c08000: LD1RSB  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rsb_z_p_bi_s64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x85c08000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
        uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1rsb_z_p_bi_s64 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rsb_z_p_bi_s64
            IEM_INSTR_IMPL_A64__ld1rsb_z_p_bi_s64(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
            RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/8540a000: LD1RSH  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rsh_z_p_bi_s32, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rsh_z_p_bi_s32 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rsh_z_p_bi_s32
        IEM_INSTR_IMPL_A64__ld1rsh_z_p_bi_s32(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
        RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/85408000: LD1RSH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rsh_z_p_bi_s64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x85408000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
        uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1rsh_z_p_bi_s64 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rsh_z_p_bi_s64
            IEM_INSTR_IMPL_A64__ld1rsh_z_p_bi_s64(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
            RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/84c08000: LD1RSW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rsw_z_p_bi_s64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x84c08000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
        uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1rsw_z_p_bi_s64 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rsw_z_p_bi_s64
            IEM_INSTR_IMPL_A64__ld1rsw_z_p_bi_s64(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
            RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/8540c000: LD1RW  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rw_z_p_bi_u32, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rw_z_p_bi_u32 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rw_z_p_bi_u32
        IEM_INSTR_IMPL_A64__ld1rw_z_p_bi_u32(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
        RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/8540e000: LD1RW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_ld_dup, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1rw_z_p_bi_u64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const dtypel     = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    uint32_t const dtypeh     = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1rw_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u dtypel=%u imm6=%#x dtypeh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, dtypel, imm6, dtypeh));
#ifdef IEM_INSTR_IMPL_A64__ld1rw_z_p_bi_u64
        IEM_INSTR_IMPL_A64__ld1rw_z_p_bi_u64(Zt, Rn, Pg, dtypel, imm6, dtypeh);
#else
        RT_NOREF(Zt, Rn, Pg, dtypel, imm6, dtypeh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4208000: LD1SB  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sb_z_p_ai_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4208000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1sb_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ld1sb_z_p_ai_d
            IEM_INSTR_IMPL_A64__ld1sb_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/84208000: LD1SB  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sb_z_p_ai_s, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1sb_z_p_ai_s Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ld1sb_z_p_ai_s
        IEM_INSTR_IMPL_A64__ld1sb_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5);
#else
        RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5c0a000: LD1SB  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sb_z_p_bi_s16, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1sb_z_p_bi_s16 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1sb_z_p_bi_s16
        IEM_INSTR_IMPL_A64__ld1sb_z_p_bi_s16(Zt, Rn, Pg, imm4, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5a0a000: LD1SB  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sb_z_p_bi_s32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5a0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1sb_z_p_bi_s32 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1sb_z_p_bi_s32
            IEM_INSTR_IMPL_A64__ld1sb_z_p_bi_s32(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a580a000: LD1SB  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sb_z_p_bi_s64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1sb_z_p_bi_s64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1sb_z_p_bi_s64
        IEM_INSTR_IMPL_A64__ld1sb_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5c04000: LD1SB  { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sb_z_p_br_s16, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1sb_z_p_br_s16 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1sb_z_p_br_s16
        IEM_INSTR_IMPL_A64__ld1sb_z_p_br_s16(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5a04000: LD1SB  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sb_z_p_br_s32, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1sb_z_p_br_s32 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1sb_z_p_br_s32
        IEM_INSTR_IMPL_A64__ld1sb_z_p_br_s32(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5804000: LD1SB  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sb_z_p_br_s64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1sb_z_p_br_s64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1sb_z_p_br_s64
        IEM_INSTR_IMPL_A64__ld1sb_z_p_br_s64(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4408000: LD1SB  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sb_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1sb_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ld1sb_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ld1sb_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c4000000: LD1SB  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sb_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc4000000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1sb_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1sb_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__ld1sb_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/84000000: LD1SB  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sb_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (0x0 /*opc@23*/ != 3 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1sb_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1sb_z_p_bz_s_x32_unscaled
        IEM_INSTR_IMPL_A64__ld1sb_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4a08000: LD1SH  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sh_z_p_ai_d, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1sh_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ld1sh_z_p_ai_d
        IEM_INSTR_IMPL_A64__ld1sh_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5);
#else
        RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/84a08000: LD1SH  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sh_z_p_ai_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x84a08000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1sh_z_p_ai_s Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ld1sh_z_p_ai_s
            IEM_INSTR_IMPL_A64__ld1sh_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a520a000: LD1SH  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sh_z_p_bi_s32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa520a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1sh_z_p_bi_s32 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1sh_z_p_bi_s32
            IEM_INSTR_IMPL_A64__ld1sh_z_p_bi_s32(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a500a000: LD1SH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sh_z_p_bi_s64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa500a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1sh_z_p_bi_s64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1sh_z_p_bi_s64
            IEM_INSTR_IMPL_A64__ld1sh_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5204000: LD1SH  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sh_z_p_br_s32, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1sh_z_p_br_s32 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1sh_z_p_br_s32
        IEM_INSTR_IMPL_A64__ld1sh_z_p_br_s32(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5004000: LD1SH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sh_z_p_br_s64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5004000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld1sh_z_p_br_s64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1sh_z_p_br_s64
            IEM_INSTR_IMPL_A64__ld1sh_z_p_br_s64(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4e08000: LD1SH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sh_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (0x1 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1sh_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4c08000: LD1SH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sh_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4c08000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1sh_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_64_unscaled
            IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c4a00000: LD1SH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sh_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (0x1 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1sh_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_x32_scaled
        IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c4800000: LD1SH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sh_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc4800000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1sh_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/84a00000: LD1SH  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1]
   Instruction Set: A64  Groups: sve_mem_32b_gld_sv_a, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sh_z_p_bz_s_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x84a00000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1sh_z_p_bz_s_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_s_x32_scaled
            IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/84800000: LD1SH  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sh_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x84800000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (0x1 /*opc@23*/ != 3 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1sh_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_s_x32_unscaled
            IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c5208000: LD1SW  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sw_z_p_ai_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc5208000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1sw_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ld1sw_z_p_ai_d
            IEM_INSTR_IMPL_A64__ld1sw_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a480a000: LD1SW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sw_z_p_bi_s64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ld1sw_z_p_bi_s64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1sw_z_p_bi_s64
        IEM_INSTR_IMPL_A64__ld1sw_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4804000: LD1SW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sw_z_p_br_s64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld1sw_z_p_br_s64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1sw_z_p_br_s64
        IEM_INSTR_IMPL_A64__ld1sw_z_p_br_s64(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c5608000: LD1SW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sw_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (0x2 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1sw_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c5408000: LD1SW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sw_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1sw_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c5200000: LD1SW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sw_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc5200000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (0x2 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1sw_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_x32_scaled
            IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c5000000: LD1SW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1sw_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc5000000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1sw_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0404000: LD1W  { <Zt1>.S-<Zt2>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1w_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1w_mz_p_bi_2
        IEM_INSTR_IMPL_A64__ld1w_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a040c000: LD1W  { <Zt1>.S-<Zt4>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_mz_p_bi_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1w_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1w_mz_p_bi_4
        IEM_INSTR_IMPL_A64__ld1w_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0004000: LD1W  { <Zt1>.S-<Zt2>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1w_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1w_mz_p_br_2
        IEM_INSTR_IMPL_A64__ld1w_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a000c000: LD1W  { <Zt1>.S-<Zt4>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1w_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1w_mz_p_br_4
        IEM_INSTR_IMPL_A64__ld1w_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1404000: LD1W  { <Zt1>.S, <Zt2>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1w_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1w_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__ld1w_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a140c000: LD1W  { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1w_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1w_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__ld1w_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1004000: LD1W  { <Zt1>.S, <Zt2>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1w_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1w_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__ld1w_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a100c000: LD1W  { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ld1w_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1w_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__ld1w_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c520c000: LD1W  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_ai_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc520c000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1w_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_ai_d
            IEM_INSTR_IMPL_A64__ld1w_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/8520c000: LD1W  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_ai_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x8520c000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1w_z_p_ai_s Zt=%#x Zn=%#x Pg=%u ff=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, imm5));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_ai_s
            IEM_INSTR_IMPL_A64__ld1w_z_p_ai_s(Zt, Zn, Pg, ff, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5102000: LD1W  { <Zt>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si_q, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_bi_u128, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1w_z_p_bi_u128 Zt=%#x Rn=%#x Pg=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_bi_u128
        IEM_INSTR_IMPL_A64__ld1w_z_p_bi_u128(Zt, Rn, Pg, imm4);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a540a000: LD1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_bi_u32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa540a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1w_z_p_bi_u32 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_bi_u32
            IEM_INSTR_IMPL_A64__ld1w_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a560a000: LD1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_bi_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa560a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1w_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_bi_u64
            IEM_INSTR_IMPL_A64__ld1w_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5008000: LD1W  { <Zt>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_cld_ss_q, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_br_u128, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (Rm != 0x1f && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ld1w_z_p_br_u128 Zt=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_br_u128
        IEM_INSTR_IMPL_A64__ld1w_z_p_br_u128(Zt, Rn, Pg, Rm);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5404000: LD1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_br_u32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5404000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld1w_z_p_br_u32 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_br_u32
            IEM_INSTR_IMPL_A64__ld1w_z_p_br_u32(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5604000: LD1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_cld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_br_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5604000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld1w_z_p_br_u64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_br_u64
            IEM_INSTR_IMPL_A64__ld1w_z_p_br_u64(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c560c000: LD1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (0x2 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1w_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c540c000: LD1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1w_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c5204000: LD1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (0x2 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ld1w_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_x32_scaled
        IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c5004000: LD1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc5004000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1w_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/85204000: LD1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #2]
   Instruction Set: A64  Groups: sve_mem_32b_gld_sv_b, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_bz_s_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x85204000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1w_z_p_bz_s_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_bz_s_x32_scaled
            IEM_INSTR_IMPL_A64__ld1w_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/85004000: LD1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x85004000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (0x2 /*opc@23*/ != 3 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ld1w_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ld1w_z_p_bz_s_x32_unscaled
            IEM_INSTR_IMPL_A64__ld1w_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00010/e0800000: LD1W  { <ZAt><HV>.S[<Ws>, <offs>] }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}]
   Instruction Set: A64  Groups: mortlach_contig_load, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_ld1w_za_p_rrr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00010)) == UINT32_C(0xe0800000))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const ZAt        = (uOpcode >>  2) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ld1w_za_p_rrr off2=%u ZAt=%u Rn=%#x Pg=%u Rs=%u V=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, ZAt, Rn, Pg, Rs, V, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld1w_za_p_rrr
            IEM_INSTR_IMPL_A64__ld1w_za_p_rrr(off2, ZAt, Rn, Pg, Rs, V, Rm);
#else
            RT_NOREF(off2, ZAt, Rn, Pg, Rs, V, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a420e000: LD2B  { <Zt1>.B, <Zt2>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld2b_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa420e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld2b_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ld2b_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__ld2b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a420c000: LD2B  { <Zt1>.B, <Zt2>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_eld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld2b_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld2b_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ld2b_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld2b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5a0e000: LD2D  { <Zt1>.D, <Zt2>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld2d_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld2d_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ld2d_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__ld2d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5a0c000: LD2D  { <Zt1>.D, <Zt2>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_eld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld2d_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld2d_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ld2d_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld2d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4a0e000: LD2H  { <Zt1>.H, <Zt2>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld2h_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld2h_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ld2h_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__ld2h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4a0c000: LD2H  { <Zt1>.H, <Zt2>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_eld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld2h_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld2h_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ld2h_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld2h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a490e000: LD2Q  { <Zt1>.Q, <Zt2>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eldq_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld2q_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: ld2q_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld2q_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__ld2q_z_p_bi_contiguous(Zt, Rn, Pg, imm4);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4a08000: LD2Q  { <Zt1>.Q, <Zt2>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #4]
   Instruction Set: A64  Groups: sve_mem_eldq_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld2q_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/))
    {
        LogFlow(("%018x/%010x: ld2q_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld2q_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld2q_z_p_br_contiguous(Zt, Rn, Pg, Rm);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a520e000: LD2W  { <Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld2w_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa520e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld2w_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ld2w_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__ld2w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a520c000: LD2W  { <Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_eld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld2w_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa520c000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (Rm != 0x1f && 0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld2w_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ld2w_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__ld2w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a440e000: LD3B  { <Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld3b_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa440e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld3b_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ld3b_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__ld3b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a440c000: LD3B  { <Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_eld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld3b_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa440c000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (Rm != 0x1f && 0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld3b_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ld3b_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__ld3b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5c0e000: LD3D  { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld3d_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld3d_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ld3d_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__ld3d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5c0c000: LD3D  { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_eld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld3d_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld3d_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ld3d_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld3d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4c0e000: LD3H  { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld3h_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld3h_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ld3h_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__ld3h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4c0c000: LD3H  { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_eld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld3h_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld3h_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ld3h_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld3h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a510e000: LD3Q  { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eldq_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld3q_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: ld3q_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld3q_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__ld3q_z_p_bi_contiguous(Zt, Rn, Pg, imm4);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5208000: LD3Q  { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #4]
   Instruction Set: A64  Groups: sve_mem_eldq_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld3q_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5208000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/))
        {
            LogFlow(("%018x/%010x: ld3q_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld3q_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__ld3q_z_p_br_contiguous(Zt, Rn, Pg, Rm);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a540e000: LD3W  { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld3w_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa540e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld3w_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ld3w_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__ld3w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a540c000: LD3W  { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_eld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld3w_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld3w_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ld3w_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld3w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a460e000: LD4B  { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld4b_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa460e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld4b_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ld4b_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__ld4b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a460c000: LD4B  { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_eld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld4b_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa460c000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (Rm != 0x1f && 0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld4b_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ld4b_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__ld4b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5e0e000: LD4D  { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld4d_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld4d_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ld4d_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__ld4d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5e0c000: LD4D  { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_eld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld4d_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld4d_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ld4d_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld4d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4e0e000: LD4H  { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld4h_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld4h_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ld4h_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__ld4h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4e0c000: LD4H  { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_eld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld4h_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ld4h_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ld4h_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld4h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a590e000: LD4Q  { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eldq_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld4q_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: ld4q_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4));
#ifdef IEM_INSTR_IMPL_A64__ld4q_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__ld4q_z_p_bi_contiguous(Zt, Rn, Pg, imm4);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5a08000: LD4Q  { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #4]
   Instruction Set: A64  Groups: sve_mem_eldq_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld4q_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/))
    {
        LogFlow(("%018x/%010x: ld4q_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__ld4q_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ld4q_z_p_br_contiguous(Zt, Rn, Pg, Rm);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a560e000: LD4W  { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_eld_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld4w_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa560e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld4w_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ld4w_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__ld4w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a560c000: LD4W  { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_eld_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ld4w_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa560c000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (Rm != 0x1f && 0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: ld4w_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ld4w_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__ld4w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c420e000: LDFF1B  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1b_z_p_ai_d, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1b_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ldff1b_z_p_ai_d
        IEM_INSTR_IMPL_A64__ldff1b_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5);
#else
        RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/8420e000: LDFF1B  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1b_z_p_ai_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x8420e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1b_z_p_ai_s Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ldff1b_z_p_ai_s
            IEM_INSTR_IMPL_A64__ldff1b_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4206000: LDFF1B  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1b_z_p_br_u16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4206000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1b_z_p_br_u16 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u16
            IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u16(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4406000: LDFF1B  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1b_z_p_br_u32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4406000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1b_z_p_br_u32 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u32
            IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u32(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4606000: LDFF1B  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1b_z_p_br_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4606000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1b_z_p_br_u64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u64
            IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u64(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4006000: LDFF1B  { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1b_z_p_br_u8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4006000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1b_z_p_br_u8 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u8
            IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u8(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c440e000: LDFF1B  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1b_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1b_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ldff1b_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ldff1b_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c4006000: LDFF1B  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1b_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc4006000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1b_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1b_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__ldff1b_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/84006000: LDFF1B  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1b_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (0x0 /*opc@23*/ != 3 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1b_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1b_z_p_bz_s_x32_unscaled
        IEM_INSTR_IMPL_A64__ldff1b_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c5a0e000: LDFF1D  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1d_z_p_ai_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc5a0e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1d_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, imm5));
#ifdef IEM_INSTR_IMPL_A64__ldff1d_z_p_ai_d
            IEM_INSTR_IMPL_A64__ldff1d_z_p_ai_d(Zt, Zn, Pg, ff, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5e06000: LDFF1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #3}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1d_z_p_br_u64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1d_z_p_br_u64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1d_z_p_br_u64
        IEM_INSTR_IMPL_A64__ldff1d_z_p_br_u64(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c5e0e000: LDFF1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #3]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1d_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc5e0e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (0x3 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1d_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u ff=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, Zm));
#ifdef IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_64_scaled
            IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, ff, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c5c0e000: LDFF1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1d_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1d_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, Zm));
#ifdef IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c5a06000: LDFF1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #3]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1d_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (0x3 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1d_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_x32_scaled
        IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c5806000: LDFF1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1d_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1d_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_x32_unscaled
        IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4a0e000: LDFF1H  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1h_z_p_ai_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4a0e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1h_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ldff1h_z_p_ai_d
            IEM_INSTR_IMPL_A64__ldff1h_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/84a0e000: LDFF1H  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1h_z_p_ai_s, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1h_z_p_ai_s Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ldff1h_z_p_ai_s
        IEM_INSTR_IMPL_A64__ldff1h_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5);
#else
        RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4a06000: LDFF1H  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1h_z_p_br_u16, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1h_z_p_br_u16 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1h_z_p_br_u16
        IEM_INSTR_IMPL_A64__ldff1h_z_p_br_u16(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4c06000: LDFF1H  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1h_z_p_br_u32, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1h_z_p_br_u32 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1h_z_p_br_u32
        IEM_INSTR_IMPL_A64__ldff1h_z_p_br_u32(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4e06000: LDFF1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1h_z_p_br_u64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1h_z_p_br_u64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1h_z_p_br_u64
        IEM_INSTR_IMPL_A64__ldff1h_z_p_br_u64(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4e0e000: LDFF1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1h_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4e0e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (0x1 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1h_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_64_scaled
            IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4c0e000: LDFF1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1h_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1h_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c4a06000: LDFF1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1h_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (0x1 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1h_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_x32_scaled
        IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c4806000: LDFF1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1h_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1h_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_x32_unscaled
        IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/84a06000: LDFF1H  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1]
   Instruction Set: A64  Groups: sve_mem_32b_gld_sv_a, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1h_z_p_bz_s_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1h_z_p_bz_s_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_s_x32_scaled
        IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/84806000: LDFF1H  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1h_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x84806000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (0x1 /*opc@23*/ != 3 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1h_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_s_x32_unscaled
            IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c420a000: LDFF1SB  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sb_z_p_ai_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc420a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1sb_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ldff1sb_z_p_ai_d
            IEM_INSTR_IMPL_A64__ldff1sb_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/8420a000: LDFF1SB  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sb_z_p_ai_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x8420a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1sb_z_p_ai_s Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ldff1sb_z_p_ai_s
            IEM_INSTR_IMPL_A64__ldff1sb_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5c06000: LDFF1SB  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sb_z_p_br_s16, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sb_z_p_br_s16 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1sb_z_p_br_s16
        IEM_INSTR_IMPL_A64__ldff1sb_z_p_br_s16(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5a06000: LDFF1SB  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sb_z_p_br_s32, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sb_z_p_br_s32 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1sb_z_p_br_s32
        IEM_INSTR_IMPL_A64__ldff1sb_z_p_br_s32(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5806000: LDFF1SB  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sb_z_p_br_s64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sb_z_p_br_s64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1sb_z_p_br_s64
        IEM_INSTR_IMPL_A64__ldff1sb_z_p_br_s64(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c440a000: LDFF1SB  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sb_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sb_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ldff1sb_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ldff1sb_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c4002000: LDFF1SB  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sb_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc4002000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1sb_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1sb_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__ldff1sb_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/84002000: LDFF1SB  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sb_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x84002000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (0x0 /*opc@23*/ != 3 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1sb_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1sb_z_p_bz_s_x32_unscaled
            IEM_INSTR_IMPL_A64__ldff1sb_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4a0a000: LDFF1SH  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sh_z_p_ai_d, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sh_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ldff1sh_z_p_ai_d
        IEM_INSTR_IMPL_A64__ldff1sh_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5);
#else
        RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/84a0a000: LDFF1SH  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sh_z_p_ai_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x84a0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1sh_z_p_ai_s Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ldff1sh_z_p_ai_s
            IEM_INSTR_IMPL_A64__ldff1sh_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5206000: LDFF1SH  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sh_z_p_br_s32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5206000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1sh_z_p_br_s32 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1sh_z_p_br_s32
            IEM_INSTR_IMPL_A64__ldff1sh_z_p_br_s32(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5006000: LDFF1SH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sh_z_p_br_s64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5006000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1sh_z_p_br_s64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1sh_z_p_br_s64
            IEM_INSTR_IMPL_A64__ldff1sh_z_p_br_s64(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4e0a000: LDFF1SH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sh_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (0x1 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sh_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4c0a000: LDFF1SH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sh_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sh_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c4a02000: LDFF1SH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sh_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (0x1 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sh_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_x32_scaled
        IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c4802000: LDFF1SH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sh_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc4802000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1sh_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/84a02000: LDFF1SH  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1]
   Instruction Set: A64  Groups: sve_mem_32b_gld_sv_a, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sh_z_p_bz_s_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sh_z_p_bz_s_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_s_x32_scaled
        IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/84802000: LDFF1SH  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sh_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x84802000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (0x1 /*opc@23*/ != 3 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1sh_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_s_x32_unscaled
            IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c520a000: LDFF1SW  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sw_z_p_ai_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc520a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1sw_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ldff1sw_z_p_ai_d
            IEM_INSTR_IMPL_A64__ldff1sw_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a4806000: LDFF1SW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sw_z_p_br_s64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sw_z_p_br_s64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1sw_z_p_br_s64
        IEM_INSTR_IMPL_A64__ldff1sw_z_p_br_s64(Zt, Rn, Pg, Rm, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c560a000: LDFF1SW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sw_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (0x2 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sw_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c540a000: LDFF1SW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sw_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sw_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c5202000: LDFF1SW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sw_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (0x2 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1sw_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_x32_scaled
        IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c5002000: LDFF1SW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1sw_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc5002000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1sw_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c520e000: LDFF1W  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1w_z_p_ai_d, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1w_z_p_ai_d Zt=%#x Zn=%#x Pg=%u ff=%u U=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, U, imm5));
#ifdef IEM_INSTR_IMPL_A64__ldff1w_z_p_ai_d
        IEM_INSTR_IMPL_A64__ldff1w_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5);
#else
        RT_NOREF(Zt, Zn, Pg, ff, U, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/8520e000: LDFF1W  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1w_z_p_ai_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x8520e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1w_z_p_ai_s Zt=%#x Zn=%#x Pg=%u ff=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, ff, imm5));
#ifdef IEM_INSTR_IMPL_A64__ldff1w_z_p_ai_s
            IEM_INSTR_IMPL_A64__ldff1w_z_p_ai_s(Zt, Zn, Pg, ff, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, ff, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5406000: LDFF1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1w_z_p_br_u32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5406000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1w_z_p_br_u32 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1w_z_p_br_u32
            IEM_INSTR_IMPL_A64__ldff1w_z_p_br_u32(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a5606000: LDFF1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}]
   Instruction Set: A64  Groups: sve_mem_cldff_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1w_z_p_br_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5606000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1w_z_p_br_u64 Zt=%#x Rn=%#x Pg=%u Rm=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldff1w_z_p_br_u64
            IEM_INSTR_IMPL_A64__ldff1w_z_p_br_u64(Zt, Rn, Pg, Rm, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c560e000: LDFF1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1w_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (0x2 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1w_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c540e000: LDFF1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1w_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1w_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c5206000: LDFF1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]
   Instruction Set: A64  Groups: sve_mem_64b_gld_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1w_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (0x2 /*opc@23*/ != 0 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldff1w_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_x32_scaled
        IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
        RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/c5006000: LDFF1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_gld_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1w_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc5006000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1w_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u U=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, U, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, U, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/85206000: LDFF1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #2]
   Instruction Set: A64  Groups: sve_mem_32b_gld_sv_b, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1w_z_p_bz_s_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x85206000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1w_z_p_bz_s_x32_scaled Zt=%#x Rn=%#x Pg=%u ff=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_s_x32_scaled
            IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e000/85006000: LDFF1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_32b_gld_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldff1w_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x85006000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const ff         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (0x2 /*opc@23*/ != 3 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldff1w_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u ff=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, ff, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_s_x32_unscaled
            IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, Zm, xs);
#else
            RT_NOREF(Zt, Rn, Pg, ff, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a430a000: LDNF1B  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1b_z_p_bi_u16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa430a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldnf1b_z_p_bi_u16 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u16
            IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u16(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a450a000: LDNF1B  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1b_z_p_bi_u32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa450a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldnf1b_z_p_bi_u32 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u32
            IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a470a000: LDNF1B  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1b_z_p_bi_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa470a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldnf1b_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u64
            IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a410a000: LDNF1B  { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1b_z_p_bi_u8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa410a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldnf1b_z_p_bi_u8 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u8
            IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u8(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5f0a000: LDNF1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1d_z_p_bi_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5f0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldnf1d_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1d_z_p_bi_u64
            IEM_INSTR_IMPL_A64__ldnf1d_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4b0a000: LDNF1H  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1h_z_p_bi_u16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4b0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldnf1h_z_p_bi_u16 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1h_z_p_bi_u16
            IEM_INSTR_IMPL_A64__ldnf1h_z_p_bi_u16(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4d0a000: LDNF1H  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1h_z_p_bi_u32, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldnf1h_z_p_bi_u32 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1h_z_p_bi_u32
        IEM_INSTR_IMPL_A64__ldnf1h_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a4f0a000: LDNF1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1h_z_p_bi_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4f0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldnf1h_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1h_z_p_bi_u64
            IEM_INSTR_IMPL_A64__ldnf1h_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5d0a000: LDNF1SB  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1sb_z_p_bi_s16, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldnf1sb_z_p_bi_s16 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1sb_z_p_bi_s16
        IEM_INSTR_IMPL_A64__ldnf1sb_z_p_bi_s16(Zt, Rn, Pg, imm4, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a5b0a000: LDNF1SB  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1sb_z_p_bi_s32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5b0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldnf1sb_z_p_bi_s32 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1sb_z_p_bi_s32
            IEM_INSTR_IMPL_A64__ldnf1sb_z_p_bi_s32(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a590a000: LDNF1SB  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1sb_z_p_bi_s64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldnf1sb_z_p_bi_s64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1sb_z_p_bi_s64
        IEM_INSTR_IMPL_A64__ldnf1sb_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a530a000: LDNF1SH  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1sh_z_p_bi_s32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa530a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldnf1sh_z_p_bi_s32 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1sh_z_p_bi_s32
            IEM_INSTR_IMPL_A64__ldnf1sh_z_p_bi_s32(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a510a000: LDNF1SH  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1sh_z_p_bi_s64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa510a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldnf1sh_z_p_bi_s64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1sh_z_p_bi_s64
            IEM_INSTR_IMPL_A64__ldnf1sh_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a490a000: LDNF1SW  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1sw_z_p_bi_s64, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: ldnf1sw_z_p_bi_s64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1sw_z_p_bi_s64
        IEM_INSTR_IMPL_A64__ldnf1sw_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a550a000: LDNF1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1w_z_p_bi_u32, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa550a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldnf1w_z_p_bi_u32 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1w_z_p_bi_u32
            IEM_INSTR_IMPL_A64__ldnf1w_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a570a000: LDNF1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnf_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnf1w_z_p_bi_u64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa570a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const dtype      = (uOpcode >> 21) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: ldnf1w_z_p_bi_u64 Zt=%#x Rn=%#x Pg=%u imm4=%#x dtype=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, dtype));
#ifdef IEM_INSTR_IMPL_A64__ldnf1w_z_p_bi_u64
            IEM_INSTR_IMPL_A64__ldnf1w_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, dtype, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0400001: LDNT1B  { <Zt1>.B-<Zt2>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1b_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1b_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1b_mz_p_bi_2
        IEM_INSTR_IMPL_A64__ldnt1b_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a0408001: LDNT1B  { <Zt1>.B-<Zt4>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1b_mz_p_bi_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa0408001))
    {
        uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: ldnt1b_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1b_mz_p_bi_4
            IEM_INSTR_IMPL_A64__ldnt1b_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
            RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0000001: LDNT1B  { <Zt1>.B-<Zt2>.B }, <PNg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1b_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1b_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1b_mz_p_br_2
        IEM_INSTR_IMPL_A64__ldnt1b_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a0008001: LDNT1B  { <Zt1>.B-<Zt4>.B }, <PNg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1b_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1b_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1b_mz_p_br_4
        IEM_INSTR_IMPL_A64__ldnt1b_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1400008: LDNT1B  { <Zt1>.B, <Zt2>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1b_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1b_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1b_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__ldnt1b_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a1408008: LDNT1B  { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1b_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1b_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1b_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__ldnt1b_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1000008: LDNT1B  { <Zt1>.B, <Zt2>.B }, <PNg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1b_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1b_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1b_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__ldnt1b_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a1008008: LDNT1B  { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1b_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1b_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1b_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__ldnt1b_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c400c000: LDNT1B  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gldnt_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1b_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc400c000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
        {
            LogFlow(("%018x/%010x: ldnt1b_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u U=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, U, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1b_z_p_ar_d_64_unscaled
            IEM_INSTR_IMPL_A64__ldnt1b_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm);
#else
            RT_NOREF(Zt, Zn, Pg, U, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/8400a000: LDNT1B  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gldnt_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1b_z_p_ar_s_x32_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: ldnt1b_z_p_ar_s_x32_unscaled Zt=%#x Zn=%#x Pg=%u U=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, U, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1b_z_p_ar_s_x32_unscaled
        IEM_INSTR_IMPL_A64__ldnt1b_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, U, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, U, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a400e000: LDNT1B  { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnt_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1b_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa400e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ldnt1b_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ldnt1b_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__ldnt1b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a400c000: LDNT1B  { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_cldnt_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1b_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ldnt1b_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ldnt1b_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ldnt1b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0406001: LDNT1D  { <Zt1>.D-<Zt2>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1d_mz_p_bi_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0406001))
    {
        uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: ldnt1d_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1d_mz_p_bi_2
            IEM_INSTR_IMPL_A64__ldnt1d_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
            RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a040e001: LDNT1D  { <Zt1>.D-<Zt4>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1d_mz_p_bi_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa040e001))
    {
        uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: ldnt1d_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1d_mz_p_bi_4
            IEM_INSTR_IMPL_A64__ldnt1d_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
            RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0006001: LDNT1D  { <Zt1>.D-<Zt2>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1d_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1d_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1d_mz_p_br_2
        IEM_INSTR_IMPL_A64__ldnt1d_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a000e001: LDNT1D  { <Zt1>.D-<Zt4>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1d_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1d_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1d_mz_p_br_4
        IEM_INSTR_IMPL_A64__ldnt1d_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1406008: LDNT1D  { <Zt1>.D, <Zt2>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1d_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1d_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1d_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__ldnt1d_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a140e008: LDNT1D  { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1d_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1d_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1d_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__ldnt1d_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1006008: LDNT1D  { <Zt1>.D, <Zt2>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1d_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1d_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1d_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__ldnt1d_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a100e008: LDNT1D  { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1d_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1d_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1d_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__ldnt1d_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c580c000: LDNT1D  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gldnt_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1d_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: ldnt1d_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1d_z_p_ar_d_64_unscaled
        IEM_INSTR_IMPL_A64__ldnt1d_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a580e000: LDNT1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnt_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1d_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ldnt1d_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ldnt1d_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__ldnt1d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a580c000: LDNT1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_cldnt_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1d_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ldnt1d_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ldnt1d_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ldnt1d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0402001: LDNT1H  { <Zt1>.H-<Zt2>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1h_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1h_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1h_mz_p_bi_2
        IEM_INSTR_IMPL_A64__ldnt1h_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a040a001: LDNT1H  { <Zt1>.H-<Zt4>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1h_mz_p_bi_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1h_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1h_mz_p_bi_4
        IEM_INSTR_IMPL_A64__ldnt1h_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0002001: LDNT1H  { <Zt1>.H-<Zt2>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1h_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1h_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1h_mz_p_br_2
        IEM_INSTR_IMPL_A64__ldnt1h_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a000a001: LDNT1H  { <Zt1>.H-<Zt4>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1h_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1h_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1h_mz_p_br_4
        IEM_INSTR_IMPL_A64__ldnt1h_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1402008: LDNT1H  { <Zt1>.H, <Zt2>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1h_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1h_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1h_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__ldnt1h_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a140a008: LDNT1H  { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1h_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1h_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1h_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__ldnt1h_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1002008: LDNT1H  { <Zt1>.H, <Zt2>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1h_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1h_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1h_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__ldnt1h_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a100a008: LDNT1H  { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1h_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1h_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1h_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__ldnt1h_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c480c000: LDNT1H  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gldnt_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1h_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: ldnt1h_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u U=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, U, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1h_z_p_ar_d_64_unscaled
        IEM_INSTR_IMPL_A64__ldnt1h_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, U, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/8480a000: LDNT1H  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gldnt_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1h_z_p_ar_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x8480a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
        {
            LogFlow(("%018x/%010x: ldnt1h_z_p_ar_s_x32_unscaled Zt=%#x Zn=%#x Pg=%u U=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, U, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1h_z_p_ar_s_x32_unscaled
            IEM_INSTR_IMPL_A64__ldnt1h_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, U, Rm);
#else
            RT_NOREF(Zt, Zn, Pg, U, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a480e000: LDNT1H  { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnt_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1h_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ldnt1h_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ldnt1h_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__ldnt1h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a480c000: LDNT1H  { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_cldnt_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1h_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ldnt1h_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ldnt1h_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ldnt1h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4008000: LDNT1SB  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gldnt_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1sb_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: ldnt1sb_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u U=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, U, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1sb_z_p_ar_d_64_unscaled
        IEM_INSTR_IMPL_A64__ldnt1sb_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, U, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/84008000: LDNT1SB  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gldnt_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1sb_z_p_ar_s_x32_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: ldnt1sb_z_p_ar_s_x32_unscaled Zt=%#x Zn=%#x Pg=%u U=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, U, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1sb_z_p_ar_s_x32_unscaled
        IEM_INSTR_IMPL_A64__ldnt1sb_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, U, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, U, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c4808000: LDNT1SH  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gldnt_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1sh_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: ldnt1sh_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u U=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, U, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1sh_z_p_ar_d_64_unscaled
        IEM_INSTR_IMPL_A64__ldnt1sh_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, U, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/84808000: LDNT1SH  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gldnt_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1sh_z_p_ar_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x84808000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
        {
            LogFlow(("%018x/%010x: ldnt1sh_z_p_ar_s_x32_unscaled Zt=%#x Zn=%#x Pg=%u U=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, U, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1sh_z_p_ar_s_x32_unscaled
            IEM_INSTR_IMPL_A64__ldnt1sh_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, U, Rm);
#else
            RT_NOREF(Zt, Zn, Pg, U, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c5008000: LDNT1SW  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gldnt_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1sw_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 14) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: ldnt1sw_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u U=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, U, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1sw_z_p_ar_d_64_unscaled
        IEM_INSTR_IMPL_A64__ldnt1sw_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, U, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0404001: LDNT1W  { <Zt1>.S-<Zt2>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1w_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1w_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1w_mz_p_bi_2
        IEM_INSTR_IMPL_A64__ldnt1w_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a040c001: LDNT1W  { <Zt1>.S-<Zt4>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1w_mz_p_bi_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1w_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1w_mz_p_bi_4
        IEM_INSTR_IMPL_A64__ldnt1w_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0004001: LDNT1W  { <Zt1>.S-<Zt2>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1w_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1w_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1w_mz_p_br_2
        IEM_INSTR_IMPL_A64__ldnt1w_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a000c001: LDNT1W  { <Zt1>.S-<Zt4>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1w_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ldnt1w_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1w_mz_p_br_4
        IEM_INSTR_IMPL_A64__ldnt1w_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1404008: LDNT1W  { <Zt1>.S, <Zt2>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1w_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1w_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1w_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__ldnt1w_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a140c008: LDNT1W  { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1w_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1w_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__ldnt1w_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__ldnt1w_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1004008: LDNT1W  { <Zt1>.S, <Zt2>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi2_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1w_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1w_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1w_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__ldnt1w_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a100c008: LDNT1W  { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi4_cld_cldnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1w_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldnt1w_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1w_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__ldnt1w_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/c500c000: LDNT1W  { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_64b_gldnt_vs, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1w_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc500c000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 14) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
        {
            LogFlow(("%018x/%010x: ldnt1w_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u U=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, U, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1w_z_p_ar_d_64_unscaled
            IEM_INSTR_IMPL_A64__ldnt1w_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm);
#else
            RT_NOREF(Zt, Zn, Pg, U, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/8500a000: LDNT1W  { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_32b_gldnt_vs, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1w_z_p_ar_s_x32_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: ldnt1w_z_p_ar_s_x32_unscaled Zt=%#x Zn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__ldnt1w_z_p_ar_s_x32_unscaled
        IEM_INSTR_IMPL_A64__ldnt1w_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/a500e000: LDNT1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cldnt_si, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1w_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ldnt1w_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__ldnt1w_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__ldnt1w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/a500c000: LDNT1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_cldnt_ss, sve_memcld, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldnt1w_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: ldnt1w_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__ldnt1w_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__ldnt1w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e010/85800000: LDR  <Pt>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_32b_pfill, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldr_p_bi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e010)) == UINT32_C(0x85800000))
    {
        uint32_t const Pt         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9l      = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm9h      = (uOpcode >> 16) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ldr_p_bi Pt=%#x Rn=%#x imm9l=%u imm9h=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pt, Rn, imm9l, imm9h));
#ifdef IEM_INSTR_IMPL_A64__ldr_p_bi
            IEM_INSTR_IMPL_A64__ldr_p_bi(Pt, Rn, imm9l, imm9h);
#else
            RT_NOREF(Pt, Rn, imm9l, imm9h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/85804000: LDR  <Zt>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_32b_fill, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_ldr_z_bi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x85804000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9l      = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm9h      = (uOpcode >> 16) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ldr_z_bi Zt=%#x Rn=%#x imm9l=%u imm9h=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, imm9l, imm9h));
#ifdef IEM_INSTR_IMPL_A64__ldr_z_bi
            IEM_INSTR_IMPL_A64__ldr_z_bi(Zt, Rn, imm9l, imm9h);
#else
            RT_NOREF(Zt, Rn, imm9l, imm9h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9c10/e1000000: LDR  ZA[<Wv>, <offs>], [<Xn|SP>{, #<offs>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_ctxt_ldst, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldr_za_ri, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9c10)) == UINT32_C(0xe1000000))
    {
        uint32_t const off4       = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ldr_za_ri off4=%#x Rn=%#x Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off4, Rn, Rv));
#ifdef IEM_INSTR_IMPL_A64__ldr_za_ri
            IEM_INSTR_IMPL_A64__ldr_za_ri(off4, Rn, Rv);
#else
            RT_NOREF(off4, Rn, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/e11f8000: LDR  ZT0, [<Xn|SP>]
   Instruction Set: A64  Groups: mortlach_zt_ldst, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_ldr_zt_br, uint32_t, uOpcode)
{
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: ldr_zt_br Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn));
#ifdef IEM_INSTR_IMPL_A64__ldr_zt_br
        IEM_INSTR_IMPL_A64__ldr_zt_br(Rn);
#else
        RT_NOREF(Rn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04038000: LSL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_0, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_lsl_z_p_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04038000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >>  5) & 0x00000007;
        uint32_t const tszl       = (uOpcode >>  8) & 0x00000003;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: lsl_z_p_zi Zdn=%#x imm3=%u tszl=%u Pg=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm3, tszl, Pg, tszh));
#ifdef IEM_INSTR_IMPL_A64__lsl_z_p_zi
            IEM_INSTR_IMPL_A64__lsl_z_p_zi(Zdn, imm3, tszl, Pg, tszh);
#else
            RT_NOREF(Zdn, imm3, tszl, Pg, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/041b8000: LSL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_2, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_lsl_z_p_zw, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x041b8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: lsl_z_p_zw Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__lsl_z_p_zw
            IEM_INSTR_IMPL_A64__lsl_z_p_zw(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04138000: LSL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_1, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_lsl_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04138000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: lsl_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__lsl_z_p_zz
            IEM_INSTR_IMPL_A64__lsl_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04209c00: LSL  <Zd>.<T>, <Zn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_bin_cons_shift_b, sve_int_unpred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_lsl_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: lsl_z_zi Zd=%#x Zn=%#x imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__lsl_z_zi
        IEM_INSTR_IMPL_A64__lsl_z_zi(Zd, Zn, imm3, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04208c00: LSL  <Zd>.<T>, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_cons_shift_a, sve_int_unpred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_lsl_z_zw, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: lsl_z_zw Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__lsl_z_zw
        IEM_INSTR_IMPL_A64__lsl_z_zw(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04178000: LSLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_1, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_lslr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04178000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: lslr_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__lslr_z_p_zz
            IEM_INSTR_IMPL_A64__lslr_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04018000: LSR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_0, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_lsr_z_p_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04018000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >>  5) & 0x00000007;
        uint32_t const tszl       = (uOpcode >>  8) & 0x00000003;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: lsr_z_p_zi Zdn=%#x imm3=%u tszl=%u Pg=%u U=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm3, tszl, Pg, U, tszh));
#ifdef IEM_INSTR_IMPL_A64__lsr_z_p_zi
            IEM_INSTR_IMPL_A64__lsr_z_p_zi(Zdn, imm3, tszl, Pg, U, tszh);
#else
            RT_NOREF(Zdn, imm3, tszl, Pg, U, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04198000: LSR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_2, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_lsr_z_p_zw, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04198000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: lsr_z_p_zw Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__lsr_z_p_zw
            IEM_INSTR_IMPL_A64__lsr_z_p_zw(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04118000: LSR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_1, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_lsr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04118000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: lsr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__lsr_z_p_zz
            IEM_INSTR_IMPL_A64__lsr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04209400: LSR  <Zd>.<T>, <Zn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_bin_cons_shift_b, sve_int_unpred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_lsr_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: lsr_z_zi Zd=%#x Zn=%#x U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__lsr_z_zi
        IEM_INSTR_IMPL_A64__lsr_z_zi(Zd, Zn, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04208400: LSR  <Zd>.<T>, <Zn>.<T>, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_cons_shift_a, sve_int_unpred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_lsr_z_zw, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: lsr_z_zw Zd=%#x Zn=%#x U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__lsr_z_zw
        IEM_INSTR_IMPL_A64__lsr_z_zw(Zd, Zn, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04158000: LSRR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_1, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_lsrr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04158000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: lsrr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__lsrr_z_p_zz
            IEM_INSTR_IMPL_A64__lsrr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc4c01/c08c4000: LUTI2  { <Zd1>.<T>-<Zd2>.<T> }, ZT0, <Zn>[<index>]
   Instruction Set: A64  Groups: mortlach_expand_2dst_ctg, mortlach_zt_expand_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_luti2_mz2_ztz_1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 12) & 0x00000003;
    uint32_t const i3         = (uOpcode >> 15) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: luti2_mz2_ztz_1 Zd=%#x Zn=%#x size=%u i3=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size, i3));
#ifdef IEM_INSTR_IMPL_A64__luti2_mz2_ztz_1
        IEM_INSTR_IMPL_A64__luti2_mz2_ztz_1(Zd, Zn, size, i3);
#else
        RT_NOREF(Zd, Zn, size, i3, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc4c08/c09c4000: LUTI2  { <Zd1>.<T>, <Zd2>.<T> }, ZT0, <Zn>[<index>]
   Instruction Set: A64  Groups: mortlach_expand_2dst_nctg, mortlach_zt_expand_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_luti2_mz2_ztz_8, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x00000007;
    uint32_t const D          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 12) & 0x00000003;
    uint32_t const i3         = (uOpcode >> 15) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: luti2_mz2_ztz_8 Zd=%u D=%u Zn=%#x size=%u i3=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, D, Zn, size, i3));
#ifdef IEM_INSTR_IMPL_A64__luti2_mz2_ztz_8
        IEM_INSTR_IMPL_A64__luti2_mz2_ztz_8(Zd, D, Zn, size, i3);
#else
        RT_NOREF(Zd, D, Zn, size, i3, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffccc03/c08c8000: LUTI2  { <Zd1>.<T>-<Zd4>.<T> }, ZT0, <Zn>[<index>]
   Instruction Set: A64  Groups: mortlach_expand_4dst_ctg, mortlach_zt_expand_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_luti2_mz4_ztz_1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 12) & 0x00000003;
    uint32_t const i2         = (uOpcode >> 16) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: luti2_mz4_ztz_1 Zd=%u Zn=%#x size=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size, i2));
#ifdef IEM_INSTR_IMPL_A64__luti2_mz4_ztz_1
        IEM_INSTR_IMPL_A64__luti2_mz4_ztz_1(Zd, Zn, size, i2);
#else
        RT_NOREF(Zd, Zn, size, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffccc0c/c09c8000: LUTI2  { <Zd1>.<T>, <Zd2>.<T>, <Zd3>.<T>, <Zd4>.<T> }, ZT0, <Zn>[<index>]
   Instruction Set: A64  Groups: mortlach_expand_4dst_nctg, mortlach_zt_expand_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_luti2_mz4_ztz_4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x00000003;
    uint32_t const D          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 12) & 0x00000003;
    uint32_t const i2         = (uOpcode >> 16) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: luti2_mz4_ztz_4 Zd=%u D=%u Zn=%#x size=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, D, Zn, size, i2));
#ifdef IEM_INSTR_IMPL_A64__luti2_mz4_ztz_4
        IEM_INSTR_IMPL_A64__luti2_mz4_ztz_4(Zd, D, Zn, size, i2);
#else
        RT_NOREF(Zd, D, Zn, size, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0c00/c0cc0000: LUTI2  <Zd>.<T>, ZT0, <Zn>[<index>]
   Instruction Set: A64  Groups: mortlach_expand_1dst, mortlach_zt_expand_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_luti2_z_ztz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffc0c00)) == UINT32_C(0xc0cc0000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 12) & 0x00000003;
        uint32_t const i4         = (uOpcode >> 14) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: luti2_z_ztz Zd=%#x Zn=%#x size=%u i4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size, i4));
#ifdef IEM_INSTR_IMPL_A64__luti2_z_ztz
            IEM_INSTR_IMPL_A64__luti2_z_ztz(Zd, Zn, size, i4);
#else
            RT_NOREF(Zd, Zn, size, i4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20ec00/4520a800: LUTI2  <Zd>.H, { <Zn>.H }, <Zm>[<index>]
   Instruction Set: A64  Groups: sve_intx_lut2_16, sve_intx_histseg_lut, sve */
FNIEMOP_DEF_1(iemDecodeA64_luti2_z_zz_16, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i3l        = (uOpcode >> 12) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const i3h        = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LUT*/)
    {
        LogFlow(("%018x/%010x: luti2_z_zz_16 Zd=%#x Zn=%#x i3l=%u Zm=%#x i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, i3l, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__luti2_z_zz_16
        IEM_INSTR_IMPL_A64__luti2_z_zz_16(Zd, Zn, i3l, Zm, i3h);
#else
        RT_NOREF(Zd, Zn, i3l, Zm, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4520b000: LUTI2  <Zd>.B, { <Zn>.B }, <Zm>[<index>]
   Instruction Set: A64  Groups: sve_intx_lut2_8, sve_intx_histseg_lut, sve */
FNIEMOP_DEF_1(iemDecodeA64_luti2_z_zz_8, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const i2         = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LUT*/)
    {
        LogFlow(("%018x/%010x: luti2_z_zz_8 Zd=%#x Zn=%#x Zm=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__luti2_z_zz_8
        IEM_INSTR_IMPL_A64__luti2_z_zz_8(Zd, Zn, Zm, i2);
#else
        RT_NOREF(Zd, Zn, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffe4c01/c08a4000: LUTI4  { <Zd1>.<T>-<Zd2>.<T> }, ZT0, <Zn>[<index>]
   Instruction Set: A64  Groups: mortlach_expand_2dst_ctg, mortlach_zt_expand_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_luti4_mz2_ztz_1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 12) & 0x00000003;
    uint32_t const i2         = (uOpcode >> 15) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: luti4_mz2_ztz_1 Zd=%#x Zn=%#x size=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size, i2));
#ifdef IEM_INSTR_IMPL_A64__luti4_mz2_ztz_1
        IEM_INSTR_IMPL_A64__luti4_mz2_ztz_1(Zd, Zn, size, i2);
#else
        RT_NOREF(Zd, Zn, size, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffe4c08/c09a4000: LUTI4  { <Zd1>.<T>, <Zd2>.<T> }, ZT0, <Zn>[<index>]
   Instruction Set: A64  Groups: mortlach_expand_2dst_nctg, mortlach_zt_expand_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_luti4_mz2_ztz_8, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x00000007;
    uint32_t const D          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 12) & 0x00000003;
    uint32_t const i2         = (uOpcode >> 15) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: luti4_mz2_ztz_8 Zd=%u D=%u Zn=%#x size=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, D, Zn, size, i2));
#ifdef IEM_INSTR_IMPL_A64__luti4_mz2_ztz_8
        IEM_INSTR_IMPL_A64__luti4_mz2_ztz_8(Zd, D, Zn, size, i2);
#else
        RT_NOREF(Zd, D, Zn, size, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffcc23/c08b0000: LUTI4  { <Zd1>.B-<Zd4>.B }, ZT0, { <Zn1>-<Zn2> }
   Instruction Set: A64  Groups: mortlach_expand_4dst2src_ctg, mortlach_zt_expand_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_luti4_mz4_ztmz2_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffcc23)) == UINT32_C(0xc08b0000))
    {
        uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 12) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_LUTv2*/)
        {
            LogFlow(("%018x/%010x: luti4_mz4_ztmz2_1 Zd=%u Zn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size));
#ifdef IEM_INSTR_IMPL_A64__luti4_mz4_ztmz2_1
            IEM_INSTR_IMPL_A64__luti4_mz4_ztmz2_1(Zd, Zn, size);
#else
            RT_NOREF(Zd, Zn, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffcc2c/c09b0000: LUTI4  { <Zd1>.B, <Zd2>.B, <Zd3>.B, <Zd4>.B }, ZT0, { <Zn1>-<Zn2> }
   Instruction Set: A64  Groups: mortlach_expand_4dst2src_nctg, mortlach_zt_expand_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_luti4_mz4_ztmz2_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffcc2c)) == UINT32_C(0xc09b0000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x00000003;
        uint32_t const D          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 12) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_LUTv2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: luti4_mz4_ztmz2_4 Zd=%u D=%u Zn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, D, Zn, size));
#ifdef IEM_INSTR_IMPL_A64__luti4_mz4_ztmz2_4
            IEM_INSTR_IMPL_A64__luti4_mz4_ztmz2_4(Zd, D, Zn, size);
#else
            RT_NOREF(Zd, D, Zn, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffecc03/c08a8000: LUTI4  { <Zd1>.<T>-<Zd4>.<T> }, ZT0, <Zn>[<index>]
   Instruction Set: A64  Groups: mortlach_expand_4dst_ctg, mortlach_zt_expand_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_luti4_mz4_ztz_1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 12) & 0x00000003;
    uint32_t const i1         = (uOpcode >> 16) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: luti4_mz4_ztz_1 Zd=%u Zn=%#x size=%u i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size, i1));
#ifdef IEM_INSTR_IMPL_A64__luti4_mz4_ztz_1
        IEM_INSTR_IMPL_A64__luti4_mz4_ztz_1(Zd, Zn, size, i1);
#else
        RT_NOREF(Zd, Zn, size, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffecc0c/c09a8000: LUTI4  { <Zd1>.H, <Zd2>.H, <Zd3>.H, <Zd4>.H }, ZT0, <Zn>[<index>]
   Instruction Set: A64  Groups: mortlach_expand_4dst_nctg, mortlach_zt_expand_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_luti4_mz4_ztz_4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x00000003;
    uint32_t const D          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 12) & 0x00000003;
    uint32_t const i1         = (uOpcode >> 16) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: luti4_mz4_ztz_4 Zd=%u D=%u Zn=%#x size=%u i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, D, Zn, size, i1));
#ifdef IEM_INSTR_IMPL_A64__luti4_mz4_ztz_4
        IEM_INSTR_IMPL_A64__luti4_mz4_ztz_4(Zd, D, Zn, size, i1);
#else
        RT_NOREF(Zd, D, Zn, size, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffe0c00/c0ca0000: LUTI4  <Zd>.<T>, ZT0, <Zn>[<index>]
   Instruction Set: A64  Groups: mortlach_expand_1dst, mortlach_zt_expand_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_luti4_z_ztz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffe0c00)) == UINT32_C(0xc0ca0000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 12) & 0x00000003;
        uint32_t const i3         = (uOpcode >> 14) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: luti4_z_ztz Zd=%#x Zn=%#x size=%u i3=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size, i3));
#ifdef IEM_INSTR_IMPL_A64__luti4_z_ztz
            IEM_INSTR_IMPL_A64__luti4_z_ztz(Zd, Zn, size, i3);
#else
            RT_NOREF(Zd, Zn, size, i3, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4520bc00: LUTI4  <Zd>.H, { <Zn>.H }, <Zm>[<index>]
   Instruction Set: A64  Groups: sve_intx_lut4_16, sve_intx_histseg_lut, sve */
FNIEMOP_DEF_1(iemDecodeA64_luti4_z_zz_1x16, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const i2         = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LUT*/)
    {
        LogFlow(("%018x/%010x: luti4_z_zz_1x16 Zd=%#x Zn=%#x Zm=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__luti4_z_zz_1x16
        IEM_INSTR_IMPL_A64__luti4_z_zz_1x16(Zd, Zn, Zm, i2);
#else
        RT_NOREF(Zd, Zn, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4520b400: LUTI4  <Zd>.H, { <Zn1>.H, <Zn2>.H }, <Zm>[<index>]
   Instruction Set: A64  Groups: sve_intx_lut4_16, sve_intx_histseg_lut, sve */
FNIEMOP_DEF_1(iemDecodeA64_luti4_z_zz_2x16, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const i2         = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LUT*/)
    {
        LogFlow(("%018x/%010x: luti4_z_zz_2x16 Zd=%#x Zn=%#x Zm=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__luti4_z_zz_2x16
        IEM_INSTR_IMPL_A64__luti4_z_zz_2x16(Zd, Zn, Zm, i2);
#else
        RT_NOREF(Zd, Zn, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff60fc00/4560a400: LUTI4  <Zd>.B, { <Zn>.B }, <Zm>[<index>]
   Instruction Set: A64  Groups: sve_intx_lut4_8, sve_intx_histseg_lut, sve */
FNIEMOP_DEF_1(iemDecodeA64_luti4_z_zz_8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff60fc00)) == UINT32_C(0x4560a400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const i1         = (uOpcode >> 23) & 0x00000001;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/) && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_LUT*/)
        {
            LogFlow(("%018x/%010x: luti4_z_zz_8 Zd=%#x Zn=%#x Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__luti4_z_zz_8
            IEM_INSTR_IMPL_A64__luti4_z_zz_8(Zd, Zn, Zm, i1);
#else
            RT_NOREF(Zd, Zn, Zm, i1, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/0400c000: MAD  <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
   Instruction Set: A64  Groups: sve_int_mladdsub_vvv_pred, sve_int_muladd_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_mad_z_p_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x0400c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Za         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mad_z_p_zzz Zdn=%#x Za=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Za, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__mad_z_p_zzz
            IEM_INSTR_IMPL_A64__mad_z_p_zzz(Zdn, Za, Pg, Zm, size);
#else
            RT_NOREF(Zdn, Za, Pg, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44c0d800: MADPT  <Zdn>.D, <Zm>.D, <Za>.D
   Instruction Set: A64  Groups: sve_ptr_muladd_unpred_lvl2, sve_ptr_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_madpt_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44c0d800))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Za         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CPA*/)
        {
            LogFlow(("%018x/%010x: madpt_z_zzz Zdn=%#x Za=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Za, Zm));
#ifdef IEM_INSTR_IMPL_A64__madpt_z_zzz
            IEM_INSTR_IMPL_A64__madpt_z_zzz(Zdn, Za, Zm);
#else
            RT_NOREF(Zdn, Za, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/45208000: MATCH  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_match, sve_intx_string, sve */
FNIEMOP_DEF_1(iemDecodeA64_match_p_p_zz, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: match_p_p_zz Pd=%#x Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__match_p_p_zz
        IEM_INSTR_IMPL_A64__match_p_p_zz(Pd, Zn, Pg, Zm, size);
#else
        RT_NOREF(Pd, Zn, Pg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/04004000: MLA  <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_mlas_vvv_pred, sve_int_muladd_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_mla_z_p_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x04004000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mla_z_p_zzz Zda=%#x Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__mla_z_p_zzz
            IEM_INSTR_IMPL_A64__mla_z_p_zzz(Zda, Zn, Pg, Zm, size);
#else
            RT_NOREF(Zda, Zn, Pg, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44e00800: MLA  <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_mla_z_zzzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44e00800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mla_z_zzzi_d Zda=%#x Zn=%#x S=%u Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, S, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__mla_z_zzzi_d
            IEM_INSTR_IMPL_A64__mla_z_zzzi_d(Zda, Zn, S, Zm, i1);
#else
            RT_NOREF(Zda, Zn, S, Zm, i1, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/44200800: MLA  <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_mla_z_zzzi_h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x44200800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mla_z_zzzi_h Zda=%#x Zn=%#x S=%u Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, S, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__mla_z_zzzi_h
            IEM_INSTR_IMPL_A64__mla_z_zzzi_h(Zda, Zn, S, Zm, i3l, i3h);
#else
            RT_NOREF(Zda, Zn, S, Zm, i3l, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44a00800: MLA  <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_mla_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44a00800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mla_z_zzzi_s Zda=%#x Zn=%#x S=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, S, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__mla_z_zzzi_s
            IEM_INSTR_IMPL_A64__mla_z_zzzi_s(Zda, Zn, S, Zm, i2);
#else
            RT_NOREF(Zda, Zn, S, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44c0d000: MLAPT  <Zda>.D, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_ptr_muladd_unpred_lvl2, sve_ptr_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_mlapt_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44c0d000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CPA*/)
        {
            LogFlow(("%018x/%010x: mlapt_z_zzz Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__mlapt_z_zzz
            IEM_INSTR_IMPL_A64__mlapt_z_zzz(Zda, Zn, Zm);
#else
            RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/04006000: MLS  <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_mlas_vvv_pred, sve_int_muladd_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_mls_z_p_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: mls_z_p_zzz Zda=%#x Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__mls_z_p_zzz
        IEM_INSTR_IMPL_A64__mls_z_p_zzz(Zda, Zn, Pg, Zm, size);
#else
        RT_NOREF(Zda, Zn, Pg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44e00c00: MLS  <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_mls_z_zzzi_d, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: mls_z_zzzi_d Zda=%#x Zn=%#x S=%u Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, S, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__mls_z_zzzi_d
        IEM_INSTR_IMPL_A64__mls_z_zzzi_d(Zda, Zn, S, Zm, i1);
#else
        RT_NOREF(Zda, Zn, S, Zm, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/44200c00: MLS  <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_mls_z_zzzi_h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x44200c00))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mls_z_zzzi_h Zda=%#x Zn=%#x S=%u Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, S, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__mls_z_zzzi_h
            IEM_INSTR_IMPL_A64__mls_z_zzzi_h(Zda, Zn, S, Zm, i3l, i3h);
#else
            RT_NOREF(Zda, Zn, S, Zm, i3l, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44a00c00: MLS  <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_mls_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: mls_z_zzzi_s Zda=%#x Zn=%#x S=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, S, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__mls_z_zzzi_s
        IEM_INSTR_IMPL_A64__mls_z_zzzi_s(Zda, Zn, S, Zm, i2);
#else
        RT_NOREF(Zda, Zn, S, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f01/c0060000: MOVA  { <Zd1>.B-<Zd2>.B }, ZA0<HV>.B[<Ws>, <offs1>:<offs2>]
   Instruction Set: A64  Groups: mortlach_multi2_extract_ctg, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_mz2_za_b1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const off3       = (uOpcode >>  5) & 0x00000007;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: mova_mz2_za_b1 Zd=%#x off3=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off3, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_mz2_za_b1
        IEM_INSTR_IMPL_A64__mova_mz2_za_b1(Zd, off3, Rs, V);
#else
        RT_NOREF(Zd, off3, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f01/c0c60000: MOVA  { <Zd1>.D-<Zd2>.D }, <ZAn><HV>.D[<Ws>, <offs1>:<offs2>]
   Instruction Set: A64  Groups: mortlach_multi2_extract_ctg, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_mz2_za_d1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1f01)) == UINT32_C(0xc0c60000))
    {
        uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const ZAn        = (uOpcode >>  5) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: mova_mz2_za_d1 Zd=%#x ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_mz2_za_d1
            IEM_INSTR_IMPL_A64__mova_mz2_za_d1(Zd, ZAn, Rs, V);
#else
            RT_NOREF(Zd, ZAn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f01/c0460000: MOVA  { <Zd1>.H-<Zd2>.H }, <ZAn><HV>.H[<Ws>, <offs1>:<offs2>]
   Instruction Set: A64  Groups: mortlach_multi2_extract_ctg, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_mz2_za_h1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1f01)) == UINT32_C(0xc0460000))
    {
        uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const off2       = (uOpcode >>  5) & 0x00000003;
        uint32_t const ZAn        = (uOpcode >>  7) & 0x00000001;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: mova_mz2_za_h1 Zd=%#x off2=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off2, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_mz2_za_h1
            IEM_INSTR_IMPL_A64__mova_mz2_za_h1(Zd, off2, ZAn, Rs, V);
#else
            RT_NOREF(Zd, off2, ZAn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f01/c0860000: MOVA  { <Zd1>.S-<Zd2>.S }, <ZAn><HV>.S[<Ws>, <offs1>:<offs2>]
   Instruction Set: A64  Groups: mortlach_multi2_extract_ctg, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_mz2_za_w1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1f01)) == UINT32_C(0xc0860000))
    {
        uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const o1         = (uOpcode >>  5) & 0x00000001;
        uint32_t const ZAn        = (uOpcode >>  6) & 0x00000003;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: mova_mz2_za_w1 Zd=%#x o1=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, o1, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_mz2_za_w1
            IEM_INSTR_IMPL_A64__mova_mz2_za_w1(Zd, o1, ZAn, Rs, V);
#else
            RT_NOREF(Zd, o1, ZAn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f83/c0060400: MOVA  { <Zd1>.B-<Zd4>.B }, ZA0<HV>.B[<Ws>, <offs1>:<offs4>]
   Instruction Set: A64  Groups: mortlach_multi4_extract_ctg, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_mz4_za_b1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const off2       = (uOpcode >>  5) & 0x00000003;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: mova_mz4_za_b1 Zd=%u off2=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off2, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_mz4_za_b1
        IEM_INSTR_IMPL_A64__mova_mz4_za_b1(Zd, off2, Rs, V);
#else
        RT_NOREF(Zd, off2, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f03/c0c60400: MOVA  { <Zd1>.D-<Zd4>.D }, <ZAn><HV>.D[<Ws>, <offs1>:<offs4>]
   Instruction Set: A64  Groups: mortlach_multi4_extract_ctg, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_mz4_za_d1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const ZAn        = (uOpcode >>  5) & 0x00000007;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: mova_mz4_za_d1 Zd=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_mz4_za_d1
        IEM_INSTR_IMPL_A64__mova_mz4_za_d1(Zd, ZAn, Rs, V);
#else
        RT_NOREF(Zd, ZAn, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f83/c0460400: MOVA  { <Zd1>.H-<Zd4>.H }, <ZAn><HV>.H[<Ws>, <offs1>:<offs4>]
   Instruction Set: A64  Groups: mortlach_multi4_extract_ctg, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_mz4_za_h1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const o1         = (uOpcode >>  5) & 0x00000001;
    uint32_t const ZAn        = (uOpcode >>  6) & 0x00000001;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: mova_mz4_za_h1 Zd=%u o1=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, o1, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_mz4_za_h1
        IEM_INSTR_IMPL_A64__mova_mz4_za_h1(Zd, o1, ZAn, Rs, V);
#else
        RT_NOREF(Zd, o1, ZAn, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f83/c0860400: MOVA  { <Zd1>.S-<Zd4>.S }, <ZAn><HV>.S[<Ws>, <offs1>:<offs4>]
   Instruction Set: A64  Groups: mortlach_multi4_extract_ctg, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_mz4_za_w1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const ZAn        = (uOpcode >>  5) & 0x00000003;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: mova_mz4_za_w1 Zd=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_mz4_za_w1
        IEM_INSTR_IMPL_A64__mova_mz4_za_w1(Zd, ZAn, Rs, V);
#else
        RT_NOREF(Zd, ZAn, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9f01/c0060800: MOVA  { <Zd1>.D-<Zd2>.D }, ZA.D[<Wv>, <offs>{, VGx2}]
   Instruction Set: A64  Groups: mortlach_multi2_za_extract_ctg, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_mz_za2_1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const off3       = (uOpcode >>  5) & 0x00000007;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: mova_mz_za2_1 Zd=%#x off3=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off3, Rv));
#ifdef IEM_INSTR_IMPL_A64__mova_mz_za2_1
        IEM_INSTR_IMPL_A64__mova_mz_za2_1(Zd, off3, Rv);
#else
        RT_NOREF(Zd, off3, Rv, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9f03/c0060c00: MOVA  { <Zd1>.D-<Zd4>.D }, ZA.D[<Wv>, <offs>{, VGx4}]
   Instruction Set: A64  Groups: mortlach_multi4_za_extract_ctg, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_mz_za4_1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const off3       = (uOpcode >>  5) & 0x00000007;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: mova_mz_za4_1 Zd=%u off3=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off3, Rv));
#ifdef IEM_INSTR_IMPL_A64__mova_mz_za4_1
        IEM_INSTR_IMPL_A64__mova_mz_za4_1(Zd, off3, Rv);
#else
        RT_NOREF(Zd, off3, Rv, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0200/c0020000: MOVA  <Zd>.B, <Pg>/M, ZA0<HV>.B[<Ws>, <offs>]
   Instruction Set: A64  Groups: mortlach_extract_pred, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_z_p_rza_b, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const off4       = (uOpcode >>  5) & 0x0000000f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: mova_z_p_rza_b Zd=%#x off4=%#x Pg=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off4, Pg, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_z_p_rza_b
        IEM_INSTR_IMPL_A64__mova_z_p_rza_b(Zd, off4, Pg, Rs, V);
#else
        RT_NOREF(Zd, off4, Pg, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0200/c0c20000: MOVA  <Zd>.D, <Pg>/M, <ZAn><HV>.D[<Ws>, <offs>]
   Instruction Set: A64  Groups: mortlach_extract_pred, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_z_p_rza_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0200)) == UINT32_C(0xc0c20000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const o1         = (uOpcode >>  5) & 0x00000001;
        uint32_t const ZAn        = (uOpcode >>  6) & 0x00000007;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mova_z_p_rza_d Zd=%#x o1=%u ZAn=%u Pg=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, o1, ZAn, Pg, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_z_p_rza_d
            IEM_INSTR_IMPL_A64__mova_z_p_rza_d(Zd, o1, ZAn, Pg, Rs, V);
#else
            RT_NOREF(Zd, o1, ZAn, Pg, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0200/c0420000: MOVA  <Zd>.H, <Pg>/M, <ZAn><HV>.H[<Ws>, <offs>]
   Instruction Set: A64  Groups: mortlach_extract_pred, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_z_p_rza_h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0200)) == UINT32_C(0xc0420000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const off3       = (uOpcode >>  5) & 0x00000007;
        uint32_t const ZAn        = (uOpcode >>  8) & 0x00000001;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mova_z_p_rza_h Zd=%#x off3=%u ZAn=%u Pg=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off3, ZAn, Pg, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_z_p_rza_h
            IEM_INSTR_IMPL_A64__mova_z_p_rza_h(Zd, off3, ZAn, Pg, Rs, V);
#else
            RT_NOREF(Zd, off3, ZAn, Pg, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0200/c0c30000: MOVA  <Zd>.Q, <Pg>/M, <ZAn><HV>.Q[<Ws>, <offs>]
   Instruction Set: A64  Groups: mortlach_extract_pred, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_z_p_rza_q, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0200)) == UINT32_C(0xc0c30000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const ZAn        = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mova_z_p_rza_q Zd=%#x ZAn=%#x Pg=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, ZAn, Pg, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_z_p_rza_q
            IEM_INSTR_IMPL_A64__mova_z_p_rza_q(Zd, ZAn, Pg, Rs, V);
#else
            RT_NOREF(Zd, ZAn, Pg, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0200/c0820000: MOVA  <Zd>.S, <Pg>/M, <ZAn><HV>.S[<Ws>, <offs>]
   Instruction Set: A64  Groups: mortlach_extract_pred, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_z_p_rza_w, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0200)) == UINT32_C(0xc0820000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const off2       = (uOpcode >>  5) & 0x00000003;
        uint32_t const ZAn        = (uOpcode >>  7) & 0x00000003;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mova_z_p_rza_w Zd=%#x off2=%u ZAn=%u Pg=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off2, ZAn, Pg, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_z_p_rza_w
            IEM_INSTR_IMPL_A64__mova_z_p_rza_w(Zd, off2, ZAn, Pg, Rs, V);
#else
            RT_NOREF(Zd, off2, ZAn, Pg, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1c38/c0040000: MOVA  ZA0<HV>.B[<Ws>, <offs1>:<offs2>], { <Zn1>.B-<Zn2>.B }
   Instruction Set: A64  Groups: mortlach_multi2_insert_ctg, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za2_z_b1, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: mova_za2_z_b1 off3=%u Zn=%#x Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za2_z_b1
        IEM_INSTR_IMPL_A64__mova_za2_z_b1(off3, Zn, Rs, V);
#else
        RT_NOREF(off3, Zn, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1c38/c0c40000: MOVA  <ZAd><HV>.D[<Ws>, <offs1>:<offs2>], { <Zn1>.D-<Zn2>.D }
   Instruction Set: A64  Groups: mortlach_multi2_insert_ctg, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za2_z_d1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1c38)) == UINT32_C(0xc0c40000))
    {
        uint32_t const ZAd        = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: mova_za2_z_d1 ZAd=%u Zn=%#x Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAd, Zn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za2_z_d1
            IEM_INSTR_IMPL_A64__mova_za2_z_d1(ZAd, Zn, Rs, V);
#else
            RT_NOREF(ZAd, Zn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1c38/c0440000: MOVA  <ZAd><HV>.H[<Ws>, <offs1>:<offs2>], { <Zn1>.H-<Zn2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_insert_ctg, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za2_z_h1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1c38)) == UINT32_C(0xc0440000))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const ZAd        = (uOpcode >>  2) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: mova_za2_z_h1 off2=%u ZAd=%u Zn=%#x Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, ZAd, Zn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za2_z_h1
            IEM_INSTR_IMPL_A64__mova_za2_z_h1(off2, ZAd, Zn, Rs, V);
#else
            RT_NOREF(off2, ZAd, Zn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1c38/c0840000: MOVA  <ZAd><HV>.S[<Ws>, <offs1>:<offs2>], { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_insert_ctg, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za2_z_w1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1c38)) == UINT32_C(0xc0840000))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const ZAd        = (uOpcode >>  1) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: mova_za2_z_w1 o1=%u ZAd=%u Zn=%#x Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, ZAd, Zn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za2_z_w1
            IEM_INSTR_IMPL_A64__mova_za2_z_w1(o1, ZAd, Zn, Rs, V);
#else
            RT_NOREF(o1, ZAd, Zn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1c7c/c0040400: MOVA  ZA0<HV>.B[<Ws>, <offs1>:<offs4>], { <Zn1>.B-<Zn4>.B }
   Instruction Set: A64  Groups: mortlach_multi4_insert_ctg, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za4_z_b1, uint32_t, uOpcode)
{
    uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: mova_za4_z_b1 off2=%u Zn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, Zn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za4_z_b1
        IEM_INSTR_IMPL_A64__mova_za4_z_b1(off2, Zn, Rs, V);
#else
        RT_NOREF(off2, Zn, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1c78/c0c40400: MOVA  <ZAd><HV>.D[<Ws>, <offs1>:<offs4>], { <Zn1>.D-<Zn4>.D }
   Instruction Set: A64  Groups: mortlach_multi4_insert_ctg, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za4_z_d1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1c78)) == UINT32_C(0xc0c40400))
    {
        uint32_t const ZAd        = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: mova_za4_z_d1 ZAd=%u Zn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAd, Zn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za4_z_d1
            IEM_INSTR_IMPL_A64__mova_za4_z_d1(ZAd, Zn, Rs, V);
#else
            RT_NOREF(ZAd, Zn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1c7c/c0440400: MOVA  <ZAd><HV>.H[<Ws>, <offs1>:<offs4>], { <Zn1>.H-<Zn4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_insert_ctg, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za4_z_h1, uint32_t, uOpcode)
{
    uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
    uint32_t const ZAd        = (uOpcode >>  1) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: mova_za4_z_h1 o1=%u ZAd=%u Zn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, ZAd, Zn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za4_z_h1
        IEM_INSTR_IMPL_A64__mova_za4_z_h1(o1, ZAd, Zn, Rs, V);
#else
        RT_NOREF(o1, ZAd, Zn, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1c7c/c0840400: MOVA  <ZAd><HV>.S[<Ws>, <offs1>:<offs4>], { <Zn1>.S-<Zn4>.S }
   Instruction Set: A64  Groups: mortlach_multi4_insert_ctg, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za4_z_w1, uint32_t, uOpcode)
{
    uint32_t const ZAd        = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: mova_za4_z_w1 ZAd=%u Zn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAd, Zn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za4_z_w1
        IEM_INSTR_IMPL_A64__mova_za4_z_w1(ZAd, Zn, Rs, V);
#else
        RT_NOREF(ZAd, Zn, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9c38/c0040800: MOVA  ZA.D[<Wv>, <offs>{, VGx2}], { <Zn1>.D-<Zn2>.D }
   Instruction Set: A64  Groups: mortlach_multi2_za_insert_ctg, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za_mz2_1, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: mova_za_mz2_1 off3=%u Zn=%#x Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv));
#ifdef IEM_INSTR_IMPL_A64__mova_za_mz2_1
        IEM_INSTR_IMPL_A64__mova_za_mz2_1(off3, Zn, Rv);
#else
        RT_NOREF(off3, Zn, Rv, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9c78/c0040c00: MOVA  ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.D-<Zn4>.D }
   Instruction Set: A64  Groups: mortlach_multi4_za_insert_ctg, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za_mz4_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9c78)) == UINT32_C(0xc0040c00))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: mova_za_mz4_1 off3=%u Zn=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv));
#ifdef IEM_INSTR_IMPL_A64__mova_za_mz4_1
            IEM_INSTR_IMPL_A64__mova_za_mz4_1(off3, Zn, Rv);
#else
            RT_NOREF(off3, Zn, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0010/c0000000: MOVA  ZA0<HV>.B[<Ws>, <offs>], <Pg>/M, <Zn>.B
   Instruction Set: A64  Groups: mortlach_insert_pred, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za_p_rz_b, uint32_t, uOpcode)
{
    uint32_t const off4       = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: mova_za_p_rz_b off4=%#x Zn=%#x Pg=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off4, Zn, Pg, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za_p_rz_b
        IEM_INSTR_IMPL_A64__mova_za_p_rz_b(off4, Zn, Pg, Rs, V);
#else
        RT_NOREF(off4, Zn, Pg, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0010/c0c00000: MOVA  <ZAd><HV>.D[<Ws>, <offs>], <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: mortlach_insert_pred, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za_p_rz_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0010)) == UINT32_C(0xc0c00000))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const ZAd        = (uOpcode >>  1) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mova_za_p_rz_d o1=%u ZAd=%u Zn=%#x Pg=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, ZAd, Zn, Pg, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za_p_rz_d
            IEM_INSTR_IMPL_A64__mova_za_p_rz_d(o1, ZAd, Zn, Pg, Rs, V);
#else
            RT_NOREF(o1, ZAd, Zn, Pg, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0010/c0400000: MOVA  <ZAd><HV>.H[<Ws>, <offs>], <Pg>/M, <Zn>.H
   Instruction Set: A64  Groups: mortlach_insert_pred, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za_p_rz_h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0010)) == UINT32_C(0xc0400000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const ZAd        = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mova_za_p_rz_h off3=%u ZAd=%u Zn=%#x Pg=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, ZAd, Zn, Pg, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za_p_rz_h
            IEM_INSTR_IMPL_A64__mova_za_p_rz_h(off3, ZAd, Zn, Pg, Rs, V);
#else
            RT_NOREF(off3, ZAd, Zn, Pg, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0010/c0c10000: MOVA  <ZAd><HV>.Q[<Ws>, <offs>], <Pg>/M, <Zn>.Q
   Instruction Set: A64  Groups: mortlach_insert_pred, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za_p_rz_q, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0010)) == UINT32_C(0xc0c10000))
    {
        uint32_t const ZAd        = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mova_za_p_rz_q ZAd=%#x Zn=%#x Pg=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAd, Zn, Pg, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za_p_rz_q
            IEM_INSTR_IMPL_A64__mova_za_p_rz_q(ZAd, Zn, Pg, Rs, V);
#else
            RT_NOREF(ZAd, Zn, Pg, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff0010/c0800000: MOVA  <ZAd><HV>.S[<Ws>, <offs>], <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: mortlach_insert_pred, mortlach_ins, sme */
FNIEMOP_DEF_1(iemDecodeA64_mova_za_p_rz_w, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0010)) == UINT32_C(0xc0800000))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const ZAd        = (uOpcode >>  2) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mova_za_p_rz_w off2=%u ZAd=%u Zn=%#x Pg=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, ZAd, Zn, Pg, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__mova_za_p_rz_w
            IEM_INSTR_IMPL_A64__mova_za_p_rz_w(off2, ZAd, Zn, Pg, Rs, V);
#else
            RT_NOREF(off2, ZAd, Zn, Pg, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f01/c0060200: MOVAZ  { <Zd1>.B-<Zd2>.B }, ZA0<HV>.B[<Ws>, <offs1>:<offs2>]
   Instruction Set: A64  Groups: mortlach_multi2_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_mz2_za_b1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const off3       = (uOpcode >>  5) & 0x00000007;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: movaz_mz2_za_b1 Zd=%#x off3=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off3, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_mz2_za_b1
        IEM_INSTR_IMPL_A64__movaz_mz2_za_b1(Zd, off3, Rs, V);
#else
        RT_NOREF(Zd, off3, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f01/c0c60200: MOVAZ  { <Zd1>.D-<Zd2>.D }, <ZAn><HV>.D[<Ws>, <offs1>:<offs2>]
   Instruction Set: A64  Groups: mortlach_multi2_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_mz2_za_d1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1f01)) == UINT32_C(0xc0c60200))
    {
        uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const ZAn        = (uOpcode >>  5) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: movaz_mz2_za_d1 Zd=%#x ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_mz2_za_d1
            IEM_INSTR_IMPL_A64__movaz_mz2_za_d1(Zd, ZAn, Rs, V);
#else
            RT_NOREF(Zd, ZAn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f01/c0460200: MOVAZ  { <Zd1>.H-<Zd2>.H }, <ZAn><HV>.H[<Ws>, <offs1>:<offs2>]
   Instruction Set: A64  Groups: mortlach_multi2_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_mz2_za_h1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1f01)) == UINT32_C(0xc0460200))
    {
        uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const off2       = (uOpcode >>  5) & 0x00000003;
        uint32_t const ZAn        = (uOpcode >>  7) & 0x00000001;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: movaz_mz2_za_h1 Zd=%#x off2=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off2, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_mz2_za_h1
            IEM_INSTR_IMPL_A64__movaz_mz2_za_h1(Zd, off2, ZAn, Rs, V);
#else
            RT_NOREF(Zd, off2, ZAn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f01/c0860200: MOVAZ  { <Zd1>.S-<Zd2>.S }, <ZAn><HV>.S[<Ws>, <offs1>:<offs2>]
   Instruction Set: A64  Groups: mortlach_multi2_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_mz2_za_w1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1f01)) == UINT32_C(0xc0860200))
    {
        uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const o1         = (uOpcode >>  5) & 0x00000001;
        uint32_t const ZAn        = (uOpcode >>  6) & 0x00000003;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: movaz_mz2_za_w1 Zd=%#x o1=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, o1, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_mz2_za_w1
            IEM_INSTR_IMPL_A64__movaz_mz2_za_w1(Zd, o1, ZAn, Rs, V);
#else
            RT_NOREF(Zd, o1, ZAn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f83/c0060600: MOVAZ  { <Zd1>.B-<Zd4>.B }, ZA0<HV>.B[<Ws>, <offs1>:<offs4>]
   Instruction Set: A64  Groups: mortlach_multi4_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_mz4_za_b1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1f83)) == UINT32_C(0xc0060600))
    {
        uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
        uint32_t const off2       = (uOpcode >>  5) & 0x00000003;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: movaz_mz4_za_b1 Zd=%u off2=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off2, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_mz4_za_b1
            IEM_INSTR_IMPL_A64__movaz_mz4_za_b1(Zd, off2, Rs, V);
#else
            RT_NOREF(Zd, off2, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f03/c0c60600: MOVAZ  { <Zd1>.D-<Zd4>.D }, <ZAn><HV>.D[<Ws>, <offs1>:<offs4>]
   Instruction Set: A64  Groups: mortlach_multi4_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_mz4_za_d1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const ZAn        = (uOpcode >>  5) & 0x00000007;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: movaz_mz4_za_d1 Zd=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_mz4_za_d1
        IEM_INSTR_IMPL_A64__movaz_mz4_za_d1(Zd, ZAn, Rs, V);
#else
        RT_NOREF(Zd, ZAn, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f83/c0460600: MOVAZ  { <Zd1>.H-<Zd4>.H }, <ZAn><HV>.H[<Ws>, <offs1>:<offs4>]
   Instruction Set: A64  Groups: mortlach_multi4_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_mz4_za_h1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const o1         = (uOpcode >>  5) & 0x00000001;
    uint32_t const ZAn        = (uOpcode >>  6) & 0x00000001;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: movaz_mz4_za_h1 Zd=%u o1=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, o1, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_mz4_za_h1
        IEM_INSTR_IMPL_A64__movaz_mz4_za_h1(Zd, o1, ZAn, Rs, V);
#else
        RT_NOREF(Zd, o1, ZAn, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1f83/c0860600: MOVAZ  { <Zd1>.S-<Zd4>.S }, <ZAn><HV>.S[<Ws>, <offs1>:<offs4>]
   Instruction Set: A64  Groups: mortlach_multi4_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_mz4_za_w1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1f83)) == UINT32_C(0xc0860600))
    {
        uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
        uint32_t const ZAn        = (uOpcode >>  5) & 0x00000003;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: movaz_mz4_za_w1 Zd=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_mz4_za_w1
            IEM_INSTR_IMPL_A64__movaz_mz4_za_w1(Zd, ZAn, Rs, V);
#else
            RT_NOREF(Zd, ZAn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9f01/c0060a00: MOVAZ  { <Zd1>.D-<Zd2>.D }, ZA.D[<Wv>, <offs>{, VGx2}]
   Instruction Set: A64  Groups: mortlach_multi2_za_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_mz_za2_1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const off3       = (uOpcode >>  5) & 0x00000007;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: movaz_mz_za2_1 Zd=%#x off3=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off3, Rv));
#ifdef IEM_INSTR_IMPL_A64__movaz_mz_za2_1
        IEM_INSTR_IMPL_A64__movaz_mz_za2_1(Zd, off3, Rv);
#else
        RT_NOREF(Zd, off3, Rv, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9f03/c0060e00: MOVAZ  { <Zd1>.D-<Zd4>.D }, ZA.D[<Wv>, <offs>{, VGx4}]
   Instruction Set: A64  Groups: mortlach_multi4_za_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_mz_za4_1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const off3       = (uOpcode >>  5) & 0x00000007;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: movaz_mz_za4_1 Zd=%u off3=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off3, Rv));
#ifdef IEM_INSTR_IMPL_A64__movaz_mz_za4_1
        IEM_INSTR_IMPL_A64__movaz_mz_za4_1(Zd, off3, Rv);
#else
        RT_NOREF(Zd, off3, Rv, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1e00/c0020200: MOVAZ  <Zd>.B, ZA0<HV>.B[<Ws>, <offs>]
   Instruction Set: A64  Groups: mortlach_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_z_rza_b, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const off4       = (uOpcode >>  5) & 0x0000000f;
    uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
    uint32_t const V          = (uOpcode >> 15) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: movaz_z_rza_b Zd=%#x off4=%#x Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off4, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_z_rza_b
        IEM_INSTR_IMPL_A64__movaz_z_rza_b(Zd, off4, Rs, V);
#else
        RT_NOREF(Zd, off4, Rs, V, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1e00/c0c20200: MOVAZ  <Zd>.D, <ZAn><HV>.D[<Ws>, <offs>]
   Instruction Set: A64  Groups: mortlach_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_z_rza_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1e00)) == UINT32_C(0xc0c20200))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const o1         = (uOpcode >>  5) & 0x00000001;
        uint32_t const ZAn        = (uOpcode >>  6) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: movaz_z_rza_d Zd=%#x o1=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, o1, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_z_rza_d
            IEM_INSTR_IMPL_A64__movaz_z_rza_d(Zd, o1, ZAn, Rs, V);
#else
            RT_NOREF(Zd, o1, ZAn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1e00/c0420200: MOVAZ  <Zd>.H, <ZAn><HV>.H[<Ws>, <offs>]
   Instruction Set: A64  Groups: mortlach_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_z_rza_h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1e00)) == UINT32_C(0xc0420200))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const off3       = (uOpcode >>  5) & 0x00000007;
        uint32_t const ZAn        = (uOpcode >>  8) & 0x00000001;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: movaz_z_rza_h Zd=%#x off3=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off3, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_z_rza_h
            IEM_INSTR_IMPL_A64__movaz_z_rza_h(Zd, off3, ZAn, Rs, V);
#else
            RT_NOREF(Zd, off3, ZAn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1e00/c0c30200: MOVAZ  <Zd>.Q, <ZAn><HV>.Q[<Ws>, <offs>]
   Instruction Set: A64  Groups: mortlach_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_z_rza_q, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1e00)) == UINT32_C(0xc0c30200))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const ZAn        = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: movaz_z_rza_q Zd=%#x ZAn=%#x Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_z_rza_q
            IEM_INSTR_IMPL_A64__movaz_z_rza_q(Zd, ZAn, Rs, V);
#else
            RT_NOREF(Zd, ZAn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff1e00/c0820200: MOVAZ  <Zd>.S, <ZAn><HV>.S[<Ws>, <offs>]
   Instruction Set: A64  Groups: mortlach_extract_zero, mortlach_ext, sme */
FNIEMOP_DEF_1(iemDecodeA64_movaz_z_rza_w, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1e00)) == UINT32_C(0xc0820200))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const off2       = (uOpcode >>  5) & 0x00000003;
        uint32_t const ZAn        = (uOpcode >>  7) & 0x00000003;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: movaz_z_rza_w Zd=%#x off2=%u ZAn=%u Rs=%u V=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, off2, ZAn, Rs, V));
#ifdef IEM_INSTR_IMPL_A64__movaz_z_rza_w
            IEM_INSTR_IMPL_A64__movaz_z_rza_w(Zd, off2, ZAn, Rs, V);
#else
            RT_NOREF(Zd, off2, ZAn, Rs, V, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ee000/04102000: MOVPRFX  <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_movprfx_pred, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_movprfx_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ee000)) == UINT32_C(0x04102000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const M          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: movprfx_z_p_z Zd=%#x Zn=%#x Pg=%u M=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, M, size));
#ifdef IEM_INSTR_IMPL_A64__movprfx_z_p_z
            IEM_INSTR_IMPL_A64__movprfx_z_p_z(Zd, Zn, Pg, M, size);
#else
            RT_NOREF(Zd, Zn, Pg, M, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/0420bc00: MOVPRFX  <Zd>, <Zn>
   Instruction Set: A64  Groups: sve_int_bin_cons_misc_0_d, sve_int_unpred_misc, sve */
FNIEMOP_DEF_1(iemDecodeA64_movprfx_z_z, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: movprfx_z_z Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__movprfx_z_z
        IEM_INSTR_IMPL_A64__movprfx_z_z(Zd, Zn);
#else
        RT_NOREF(Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff8fe0/c04c03e0: MOVT  <Xt>, ZT0[<offs>]
   Instruction Set: A64  Groups: mortlach_extract_zt, mortlach_mov_zt, sme */
FNIEMOP_DEF_1(iemDecodeA64_movt_r_zt, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff8fe0)) == UINT32_C(0xc04c03e0))
    {
        uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const off3       = (uOpcode >> 12) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: movt_r_zt Rt=%#x off3=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, off3));
#ifdef IEM_INSTR_IMPL_A64__movt_r_zt
            IEM_INSTR_IMPL_A64__movt_r_zt(Rt, off3);
#else
            RT_NOREF(Rt, off3, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff8fe0/c04e03e0: MOVT  ZT0[<offs>], <Xt>
   Instruction Set: A64  Groups: mortlach_insert_zt, mortlach_mov_zt, sme */
FNIEMOP_DEF_1(iemDecodeA64_movt_zt_r, uint32_t, uOpcode)
{
    uint32_t const Rt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const off3       = (uOpcode >> 12) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: movt_zt_r Rt=%#x off3=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rt, off3));
#ifdef IEM_INSTR_IMPL_A64__movt_zt_r
        IEM_INSTR_IMPL_A64__movt_zt_r(Rt, off3);
#else
        RT_NOREF(Rt, off3, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffcfe0/c04f03e0: MOVT  ZT0{[<offs>, MUL VL]}, <Zt>
   Instruction Set: A64  Groups: mortlach_move_to_zt, mortlach_mov_zt, sme */
FNIEMOP_DEF_1(iemDecodeA64_movt_zt_z, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const off2       = (uOpcode >> 12) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_LUTv2*/)
    {
        LogFlow(("%018x/%010x: movt_zt_z Zt=%#x off2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, off2));
#ifdef IEM_INSTR_IMPL_A64__movt_zt_z
        IEM_INSTR_IMPL_A64__movt_zt_z(Zt, off2);
#else
        RT_NOREF(Zt, off2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e000/0400e000: MSB  <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
   Instruction Set: A64  Groups: sve_int_mladdsub_vvv_pred, sve_int_muladd_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_msb_z_p_zzz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Za         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: msb_z_p_zzz Zdn=%#x Za=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Za, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__msb_z_p_zzz
        IEM_INSTR_IMPL_A64__msb_z_p_zzz(Zdn, Za, Pg, Zm, size);
#else
        RT_NOREF(Zdn, Za, Pg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04100000: MUL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_2, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_mul_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: mul_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__mul_z_p_zz
        IEM_INSTR_IMPL_A64__mul_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/2530c000: MUL  <Zdn>.<T>, <Zdn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_arith_imm2, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_mul_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x2530c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mul_z_zi Zdn=%#x imm8=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm8, size));
#ifdef IEM_INSTR_IMPL_A64__mul_z_zi
            IEM_INSTR_IMPL_A64__mul_z_zi(Zdn, imm8, size);
#else
            RT_NOREF(Zdn, imm8, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04206000: MUL  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_mul_b, sve_int_unpred_arit_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_mul_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04206000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: mul_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__mul_z_zz
            IEM_INSTR_IMPL_A64__mul_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44e0f800: MUL  <Zd>.D, <Zn>.D, <Zm>.D[<imm>]
   Instruction Set: A64  Groups: sve_intx_mul_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_mul_z_zzi_d, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: mul_z_zzi_d Zd=%#x Zn=%#x Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__mul_z_zzi_d
        IEM_INSTR_IMPL_A64__mul_z_zzi_d(Zd, Zn, Zm, i1);
#else
        RT_NOREF(Zd, Zn, Zm, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/4420f800: MUL  <Zd>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mul_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_mul_z_zzi_h, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
    uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: mul_z_zzi_h Zd=%#x Zn=%#x Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__mul_z_zzi_h
        IEM_INSTR_IMPL_A64__mul_z_zzi_h(Zd, Zn, Zm, i3l, i3h);
#else
        RT_NOREF(Zd, Zn, Zm, i3l, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44a0f800: MUL  <Zd>.S, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mul_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_mul_z_zzi_s, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: mul_z_zzi_s Zd=%#x Zn=%#x Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__mul_z_zzi_s
        IEM_INSTR_IMPL_A64__mul_z_zzi_s(Zd, Zn, Zm, i2);
#else
        RT_NOREF(Zd, Zn, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25804210: NAND  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_nand_p_p_pp_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25804210))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: nand_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__nand_p_p_pp_z
            IEM_INSTR_IMPL_A64__nand_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25c04210: NANDS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_nands_p_p_pp_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25c04210))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: nands_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__nands_p_p_pp_z
            IEM_INSTR_IMPL_A64__nands_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04e03c00: NBSL  <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
   Instruction Set: A64  Groups: sve_int_tern_log, sve_int_unpred_logical, sve */
FNIEMOP_DEF_1(iemDecodeA64_nbsl_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04e03c00))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zk         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: nbsl_z_zzz Zdn=%#x Zk=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zk, Zm));
#ifdef IEM_INSTR_IMPL_A64__nbsl_z_zzz
            IEM_INSTR_IMPL_A64__nbsl_z_zzz(Zdn, Zk, Zm);
#else
            RT_NOREF(Zdn, Zk, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0417a000: NEG  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_neg_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0417a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: neg_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__neg_z_p_z_m
            IEM_INSTR_IMPL_A64__neg_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0407a000: NEG  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_neg_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0407a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: neg_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__neg_z_p_z_z
            IEM_INSTR_IMPL_A64__neg_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20e010/45208010: NMATCH  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_match, sve_intx_string, sve */
FNIEMOP_DEF_1(iemDecodeA64_nmatch_p_p_zz, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: nmatch_p_p_zz Pd=%#x Zn=%#x Pg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Zn, Pg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__nmatch_p_p_zz
        IEM_INSTR_IMPL_A64__nmatch_p_p_zz(Pd, Zn, Pg, Zm, size);
#else
        RT_NOREF(Pd, Zn, Pg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25804200: NOR  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_nor_p_p_pp_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25804200))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: nor_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__nor_p_p_pp_z
            IEM_INSTR_IMPL_A64__nor_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25c04200: NORS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_nors_p_p_pp_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25c04200))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: nors_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__nors_p_p_pp_z
            IEM_INSTR_IMPL_A64__nors_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/041ea000: NOT  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_not_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x041ea000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: not_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__not_z_p_z_m
            IEM_INSTR_IMPL_A64__not_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040ea000: NOT  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_1, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_not_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040ea000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: not_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__not_z_p_z_z
            IEM_INSTR_IMPL_A64__not_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25804010: ORN  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_orn_p_p_pp_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25804010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: orn_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__orn_p_p_pp_z
            IEM_INSTR_IMPL_A64__orn_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25c04010: ORNS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_orns_p_p_pp_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25c04010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: orns_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__orns_p_p_pp_z
            IEM_INSTR_IMPL_A64__orns_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/041c2000: ORQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_int_reduce_2q, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_orqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x041c2000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: orqv_z_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__orqv_z_p_z
            IEM_INSTR_IMPL_A64__orqv_z_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25804000: ORR  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_orr_p_p_pp_z, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
    uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const S          = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: orr_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__orr_p_p_pp_z
        IEM_INSTR_IMPL_A64__orr_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
        RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04180000: ORR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_log, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_orr_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: orr_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__orr_z_p_zz
        IEM_INSTR_IMPL_A64__orr_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffc0000/05000000: ORR  <Zdn>.<T>, <Zdn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_log_imm, sve_maskimm, sve */
FNIEMOP_DEF_1(iemDecodeA64_orr_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const imm13      = (uOpcode >>  5) & 0x00001fff;
    if (0x0 /*opc@22*/ != 3 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: orr_z_zi Zdn=%#x imm13=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm13));
#ifdef IEM_INSTR_IMPL_A64__orr_z_zi
        IEM_INSTR_IMPL_A64__orr_z_zi(Zdn, imm13);
#else
        RT_NOREF(Zdn, imm13, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04603000: ORR  <Zd>.D, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_cons_log, sve_int_unpred_logical, sve */
FNIEMOP_DEF_1(iemDecodeA64_orr_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: orr_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__orr_z_zz
        IEM_INSTR_IMPL_A64__orr_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25c04000: ORRS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_orrs_p_p_pp_z, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
    uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const S          = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: orrs_p_p_pp_z Pd=%#x Pn=%#x Pg=%#x Pm=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm, S));
#ifdef IEM_INSTR_IMPL_A64__orrs_p_p_pp_z
        IEM_INSTR_IMPL_A64__orrs_p_p_pp_z(Pd, Pn, Pg, Pm, S);
#else
        RT_NOREF(Pd, Pn, Pg, Pm, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04182000: ORV  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_reduce_2, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_orv_r_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04182000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: orv_r_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__orv_r_p_z
            IEM_INSTR_IMPL_A64__orv_r_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc10/25207010: PEXT  <Pd>.<T>, <PNn>[<imm>]
   Instruction Set: A64  Groups: sve_int_ctr_to_mask, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_pext_pn_rr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc10)) == UINT32_C(0x25207010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const PNn        = (uOpcode >>  5) & 0x00000007;
        uint32_t const imm2       = (uOpcode >>  8) & 0x00000003;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: pext_pn_rr Pd=%#x PNn=%u imm2=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, PNn, imm2, size));
#ifdef IEM_INSTR_IMPL_A64__pext_pn_rr
            IEM_INSTR_IMPL_A64__pext_pn_rr(Pd, PNn, imm2, size);
#else
            RT_NOREF(Pd, PNn, imm2, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe10/25207410: PEXT  { <Pd1>.<T>, <Pd2>.<T> }, <PNn>[<imm>]
   Instruction Set: A64  Groups: sve_int_ctr_to_mask, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_pext_pp_rr, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const PNn        = (uOpcode >>  5) & 0x00000007;
    uint32_t const i1         = (uOpcode >>  8) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: pext_pp_rr Pd=%#x PNn=%u i1=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, PNn, i1, size));
#ifdef IEM_INSTR_IMPL_A64__pext_pp_rr
        IEM_INSTR_IMPL_A64__pext_pp_rr(Pd, PNn, i1, size);
#else
        RT_NOREF(Pd, PNn, i1, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffff0/2518e400: PFALSE  <Pd>.B
   Instruction Set: A64  Groups: sve_int_pfalse, sve_pred_gen_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_pfalse_p, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: pfalse_p Pd=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd));
#ifdef IEM_INSTR_IMPL_A64__pfalse_p
        IEM_INSTR_IMPL_A64__pfalse_p(Pd);
#else
        RT_NOREF(Pd, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffe10/2558c000: PFIRST  <Pdn>.B, <Pg>, <Pdn>.B
   Instruction Set: A64  Groups: sve_int_pfirst, sve_pred_gen_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_pfirst_p_p_p, uint32_t, uOpcode)
{
    uint32_t const Pdn        = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Pg         = (uOpcode >>  5) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: pfirst_p_p_p Pdn=%#x Pg=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pdn, Pg));
#ifdef IEM_INSTR_IMPL_A64__pfirst_p_p_p
        IEM_INSTR_IMPL_A64__pfirst_p_p_p(Pdn, Pg);
#else
        RT_NOREF(Pdn, Pg, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc01/4520fc00: PMLAL  { <Zda1>.Q-<Zda2>.Q }, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_crypto_pmlal_multi, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmlal_mz_zzzw_1x2, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_AES2*/)
    {
        LogFlow(("%018x/%010x: pmlal_mz_zzzw_1x2 Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__pmlal_mz_zzzw_1x2
        IEM_INSTR_IMPL_A64__pmlal_mz_zzzw_1x2(Zda, Zn, Zm);
#else
        RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc10/052a3800: PMOV  <Pd>.B, <Zn>
   Instruction Set: A64  Groups: sve_int_mov_v2p, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmov_p_zi_b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc10)) == UINT32_C(0x052a3800))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: pmov_p_zi_b Pd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Zn));
#ifdef IEM_INSTR_IMPL_A64__pmov_p_zi_b
            IEM_INSTR_IMPL_A64__pmov_p_zi_b(Pd, Zn);
#else
            RT_NOREF(Pd, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb9fc10/05a83800: PMOV  <Pd>.D, <Zn>{[<imm>]}
   Instruction Set: A64  Groups: sve_int_mov_v2p, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmov_p_zi_d, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i3l        = (uOpcode >> 17) & 0x00000003;
    uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: pmov_p_zi_d Pd=%#x Zn=%#x i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Zn, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__pmov_p_zi_d
        IEM_INSTR_IMPL_A64__pmov_p_zi_d(Pd, Zn, i3l, i3h);
#else
        RT_NOREF(Pd, Zn, i3l, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffdfc10/052c3800: PMOV  <Pd>.H, <Zn>{[<imm>]}
   Instruction Set: A64  Groups: sve_int_mov_v2p, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmov_p_zi_h, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i1         = (uOpcode >> 17) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: pmov_p_zi_h Pd=%#x Zn=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Zn, i1));
#ifdef IEM_INSTR_IMPL_A64__pmov_p_zi_h
        IEM_INSTR_IMPL_A64__pmov_p_zi_h(Pd, Zn, i1);
#else
        RT_NOREF(Pd, Zn, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff9fc10/05683800: PMOV  <Pd>.S, <Zn>{[<imm>]}
   Instruction Set: A64  Groups: sve_int_mov_v2p, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmov_p_zi_s, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i2         = (uOpcode >> 17) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: pmov_p_zi_s Pd=%#x Zn=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Zn, i2));
#ifdef IEM_INSTR_IMPL_A64__pmov_p_zi_s
        IEM_INSTR_IMPL_A64__pmov_p_zi_s(Pd, Zn, i2);
#else
        RT_NOREF(Pd, Zn, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffe00/052b3800: PMOV  <Zd>, <Pn>.B
   Instruction Set: A64  Groups: sve_int_mov_p2v, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmov_z_pi_b, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffe00)) == UINT32_C(0x052b3800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: pmov_z_pi_b Zd=%#x Pn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Pn));
#ifdef IEM_INSTR_IMPL_A64__pmov_z_pi_b
            IEM_INSTR_IMPL_A64__pmov_z_pi_b(Zd, Pn);
#else
            RT_NOREF(Zd, Pn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb9fe00/05a93800: PMOV  <Zd>{[<imm>]}, <Pn>.D
   Instruction Set: A64  Groups: sve_int_mov_p2v, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmov_z_pi_d, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const i3l        = (uOpcode >> 17) & 0x00000003;
    uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: pmov_z_pi_d Zd=%#x Pn=%#x i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Pn, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__pmov_z_pi_d
        IEM_INSTR_IMPL_A64__pmov_z_pi_d(Zd, Pn, i3l, i3h);
#else
        RT_NOREF(Zd, Pn, i3l, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffdfe00/052d3800: PMOV  <Zd>{[<imm>]}, <Pn>.H
   Instruction Set: A64  Groups: sve_int_mov_p2v, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmov_z_pi_h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffdfe00)) == UINT32_C(0x052d3800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 17) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: pmov_z_pi_h Zd=%#x Pn=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Pn, i1));
#ifdef IEM_INSTR_IMPL_A64__pmov_z_pi_h
            IEM_INSTR_IMPL_A64__pmov_z_pi_h(Zd, Pn, i1);
#else
            RT_NOREF(Zd, Pn, i1, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff9fe00/05693800: PMOV  <Zd>{[<imm>]}, <Pn>.S
   Instruction Set: A64  Groups: sve_int_mov_p2v, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmov_z_pi_s, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const i2         = (uOpcode >> 17) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: pmov_z_pi_s Zd=%#x Pn=%#x i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Pn, i2));
#ifdef IEM_INSTR_IMPL_A64__pmov_z_pi_s
        IEM_INSTR_IMPL_A64__pmov_z_pi_s(Zd, Pn, i2);
#else
        RT_NOREF(Zd, Pn, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04206400: PMUL  <Zd>.B, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_int_mul_b, sve_int_unpred_arit_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmul_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: pmul_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__pmul_z_zz
        IEM_INSTR_IMPL_A64__pmul_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc01/4520f800: PMULL  { <Zd1>.Q-<Zd2>.Q }, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_crypto_pmull_multi, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmull_mz_zzw_1x2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE_AES2*/)
    {
        LogFlow(("%018x/%010x: pmull_mz_zzw_1x2 Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__pmull_mz_zzw_1x2
        IEM_INSTR_IMPL_A64__pmull_mz_zzw_1x2(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45006800: PMULLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_mul_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmullb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: pmullb_z_zz Zd=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__pmullb_z_zz
        IEM_INSTR_IMPL_A64__pmullb_z_zz(Zd, Zn, T, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/45006800: PMULLB  <Zd>.Q, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_intx_cons_mul_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmullb_z_zz_q, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvePmull128 /*FEAT_SVE_PMULL128*/)
    {
        LogFlow(("%018x/%010x: pmullb_z_zz_q Zd=%#x Zn=%#x T=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm));
#ifdef IEM_INSTR_IMPL_A64__pmullb_z_zz_q
        IEM_INSTR_IMPL_A64__pmullb_z_zz_q(Zd, Zn, T, Zm);
#else
        RT_NOREF(Zd, Zn, T, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45006c00: PMULLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_mul_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmullt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && size != 0)
    {
        LogFlow(("%018x/%010x: pmullt_z_zz Zd=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__pmullt_z_zz
        IEM_INSTR_IMPL_A64__pmullt_z_zz(Zd, Zn, T, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/45006c00: PMULLT  <Zd>.Q, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_intx_cons_mul_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_pmullt_z_zz_q, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvePmull128 /*FEAT_SVE_PMULL128*/)
    {
        LogFlow(("%018x/%010x: pmullt_z_zz_q Zd=%#x Zn=%#x T=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm));
#ifdef IEM_INSTR_IMPL_A64__pmullt_z_zz_q
        IEM_INSTR_IMPL_A64__pmullt_z_zz_q(Zd, Zn, T, Zm);
#else
        RT_NOREF(Zd, Zn, T, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe10/2519c400: PNEXT  <Pdn>.<T>, <Pv>, <Pdn>.<T>
   Instruction Set: A64  Groups: sve_int_pnext, sve_pred_gen_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_pnext_p_p_p, uint32_t, uOpcode)
{
    uint32_t const Pdn        = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Pv         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: pnext_p_p_p Pdn=%#x Pv=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pdn, Pv, size));
#ifdef IEM_INSTR_IMPL_A64__pnext_p_p_p
        IEM_INSTR_IMPL_A64__pnext_p_p_p(Pdn, Pv, size);
#else
        RT_NOREF(Pdn, Pv, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/c400e000: PRFB  <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_prfm_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfb_i_p_ai_d, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfb_i_p_ai_d prfop=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__prfb_i_p_ai_d
        IEM_INSTR_IMPL_A64__prfb_i_p_ai_d(prfop, Zn, Pg, imm5);
#else
        RT_NOREF(prfop, Zn, Pg, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/8400e000: PRFB  <prfop>, <Pg>, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_prfm_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfb_i_p_ai_s, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfb_i_p_ai_s prfop=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__prfb_i_p_ai_s
        IEM_INSTR_IMPL_A64__prfb_i_p_ai_s(prfop, Zn, Pg, imm5);
#else
        RT_NOREF(prfop, Zn, Pg, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e010/85c00000: PRFB  <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_prfm_si, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfb_i_p_bi_s, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: prfb_i_p_bi_s prfop=%#x Rn=%#x Pg=%u imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, imm6));
#ifdef IEM_INSTR_IMPL_A64__prfb_i_p_bi_s
        IEM_INSTR_IMPL_A64__prfb_i_p_bi_s(prfop, Rn, Pg, imm6);
#else
        RT_NOREF(prfop, Rn, Pg, imm6, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/8400c000: PRFB  <prfop>, <Pg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_prfm_ss, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfb_i_p_br_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0x8400c000))
    {
        uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: prfb_i_p_br_s prfop=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__prfb_i_p_br_s
            IEM_INSTR_IMPL_A64__prfb_i_p_br_s(prfop, Rn, Pg, Rm);
#else
            RT_NOREF(prfop, Rn, Pg, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/c4608000: PRFB  <prfop>, <Pg>, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_64b_prfm_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfb_i_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfb_i_p_bz_d_64_scaled prfop=%#x Rn=%#x Pg=%u msz=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, msz, Zm));
#ifdef IEM_INSTR_IMPL_A64__prfb_i_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__prfb_i_p_bz_d_64_scaled(prfop, Rn, Pg, msz, Zm);
#else
        RT_NOREF(prfop, Rn, Pg, msz, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e010/c4200000: PRFB  <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_64b_prfm_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfb_i_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e010)) == UINT32_C(0xc4200000))
    {
        uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: prfb_i_p_bz_d_x32_scaled prfop=%#x Rn=%#x Pg=%u msz=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, msz, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__prfb_i_p_bz_d_x32_scaled
            IEM_INSTR_IMPL_A64__prfb_i_p_bz_d_x32_scaled(prfop, Rn, Pg, msz, Zm, xs);
#else
            RT_NOREF(prfop, Rn, Pg, msz, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e010/84200000: PRFB  <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_32b_prfm_sv, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfb_i_p_bz_s_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfb_i_p_bz_s_x32_scaled prfop=%#x Rn=%#x Pg=%u msz=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, msz, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__prfb_i_p_bz_s_x32_scaled
        IEM_INSTR_IMPL_A64__prfb_i_p_bz_s_x32_scaled(prfop, Rn, Pg, msz, Zm, xs);
#else
        RT_NOREF(prfop, Rn, Pg, msz, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/c580e000: PRFD  <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_prfm_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfd_i_p_ai_d, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfd_i_p_ai_d prfop=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__prfd_i_p_ai_d
        IEM_INSTR_IMPL_A64__prfd_i_p_ai_d(prfop, Zn, Pg, imm5);
#else
        RT_NOREF(prfop, Zn, Pg, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/8580e000: PRFD  <prfop>, <Pg>, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_prfm_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfd_i_p_ai_s, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfd_i_p_ai_s prfop=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__prfd_i_p_ai_s
        IEM_INSTR_IMPL_A64__prfd_i_p_ai_s(prfop, Zn, Pg, imm5);
#else
        RT_NOREF(prfop, Zn, Pg, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e010/85c06000: PRFD  <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_prfm_si, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfd_i_p_bi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e010)) == UINT32_C(0x85c06000))
    {
        uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: prfd_i_p_bi_s prfop=%#x Rn=%#x Pg=%u imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, imm6));
#ifdef IEM_INSTR_IMPL_A64__prfd_i_p_bi_s
            IEM_INSTR_IMPL_A64__prfd_i_p_bi_s(prfop, Rn, Pg, imm6);
#else
            RT_NOREF(prfop, Rn, Pg, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/8580c000: PRFD  <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_prfm_ss, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfd_i_p_br_s, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: prfd_i_p_br_s prfop=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__prfd_i_p_br_s
        IEM_INSTR_IMPL_A64__prfd_i_p_br_s(prfop, Rn, Pg, Rm);
#else
        RT_NOREF(prfop, Rn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/c460e000: PRFD  <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3]
   Instruction Set: A64  Groups: sve_mem_64b_prfm_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfd_i_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfd_i_p_bz_d_64_scaled prfop=%#x Rn=%#x Pg=%u msz=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, msz, Zm));
#ifdef IEM_INSTR_IMPL_A64__prfd_i_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__prfd_i_p_bz_d_64_scaled(prfop, Rn, Pg, msz, Zm);
#else
        RT_NOREF(prfop, Rn, Pg, msz, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e010/c4206000: PRFD  <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3]
   Instruction Set: A64  Groups: sve_mem_64b_prfm_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfd_i_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfd_i_p_bz_d_x32_scaled prfop=%#x Rn=%#x Pg=%u msz=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, msz, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__prfd_i_p_bz_d_x32_scaled
        IEM_INSTR_IMPL_A64__prfd_i_p_bz_d_x32_scaled(prfop, Rn, Pg, msz, Zm, xs);
#else
        RT_NOREF(prfop, Rn, Pg, msz, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e010/84206000: PRFD  <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #3]
   Instruction Set: A64  Groups: sve_mem_32b_prfm_sv, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfd_i_p_bz_s_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e010)) == UINT32_C(0x84206000))
    {
        uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: prfd_i_p_bz_s_x32_scaled prfop=%#x Rn=%#x Pg=%u msz=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, msz, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__prfd_i_p_bz_s_x32_scaled
            IEM_INSTR_IMPL_A64__prfd_i_p_bz_s_x32_scaled(prfop, Rn, Pg, msz, Zm, xs);
#else
            RT_NOREF(prfop, Rn, Pg, msz, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/c480e000: PRFH  <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_prfm_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfh_i_p_ai_d, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfh_i_p_ai_d prfop=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__prfh_i_p_ai_d
        IEM_INSTR_IMPL_A64__prfh_i_p_ai_d(prfop, Zn, Pg, imm5);
#else
        RT_NOREF(prfop, Zn, Pg, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/8480e000: PRFH  <prfop>, <Pg>, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_prfm_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfh_i_p_ai_s, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfh_i_p_ai_s prfop=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__prfh_i_p_ai_s
        IEM_INSTR_IMPL_A64__prfh_i_p_ai_s(prfop, Zn, Pg, imm5);
#else
        RT_NOREF(prfop, Zn, Pg, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e010/85c02000: PRFH  <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_prfm_si, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfh_i_p_bi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e010)) == UINT32_C(0x85c02000))
    {
        uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: prfh_i_p_bi_s prfop=%#x Rn=%#x Pg=%u imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, imm6));
#ifdef IEM_INSTR_IMPL_A64__prfh_i_p_bi_s
            IEM_INSTR_IMPL_A64__prfh_i_p_bi_s(prfop, Rn, Pg, imm6);
#else
            RT_NOREF(prfop, Rn, Pg, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/8480c000: PRFH  <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_prfm_ss, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfh_i_p_br_s, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: prfh_i_p_br_s prfop=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__prfh_i_p_br_s
        IEM_INSTR_IMPL_A64__prfh_i_p_br_s(prfop, Rn, Pg, Rm);
#else
        RT_NOREF(prfop, Rn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/c460a000: PRFH  <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #1]
   Instruction Set: A64  Groups: sve_mem_64b_prfm_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfh_i_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfh_i_p_bz_d_64_scaled prfop=%#x Rn=%#x Pg=%u msz=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, msz, Zm));
#ifdef IEM_INSTR_IMPL_A64__prfh_i_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__prfh_i_p_bz_d_64_scaled(prfop, Rn, Pg, msz, Zm);
#else
        RT_NOREF(prfop, Rn, Pg, msz, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e010/c4202000: PRFH  <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1]
   Instruction Set: A64  Groups: sve_mem_64b_prfm_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfh_i_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfh_i_p_bz_d_x32_scaled prfop=%#x Rn=%#x Pg=%u msz=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, msz, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__prfh_i_p_bz_d_x32_scaled
        IEM_INSTR_IMPL_A64__prfh_i_p_bz_d_x32_scaled(prfop, Rn, Pg, msz, Zm, xs);
#else
        RT_NOREF(prfop, Rn, Pg, msz, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e010/84202000: PRFH  <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1]
   Instruction Set: A64  Groups: sve_mem_32b_prfm_sv, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfh_i_p_bz_s_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e010)) == UINT32_C(0x84202000))
    {
        uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: prfh_i_p_bz_s_x32_scaled prfop=%#x Rn=%#x Pg=%u msz=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, msz, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__prfh_i_p_bz_s_x32_scaled
            IEM_INSTR_IMPL_A64__prfh_i_p_bz_s_x32_scaled(prfop, Rn, Pg, msz, Zm, xs);
#else
            RT_NOREF(prfop, Rn, Pg, msz, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/c500e000: PRFW  <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_64b_prfm_vi, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfw_i_p_ai_d, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfw_i_p_ai_d prfop=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__prfw_i_p_ai_d
        IEM_INSTR_IMPL_A64__prfw_i_p_ai_d(prfop, Zn, Pg, imm5);
#else
        RT_NOREF(prfop, Zn, Pg, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/8500e000: PRFW  <prfop>, <Pg>, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_32b_prfm_vi, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfw_i_p_ai_s, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfw_i_p_ai_s prfop=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__prfw_i_p_ai_s
        IEM_INSTR_IMPL_A64__prfw_i_p_ai_s(prfop, Zn, Pg, imm5);
#else
        RT_NOREF(prfop, Zn, Pg, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e010/85c04000: PRFW  <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_prfm_si, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfw_i_p_bi_s, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm6       = (uOpcode >> 16) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: prfw_i_p_bi_s prfop=%#x Rn=%#x Pg=%u imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, imm6));
#ifdef IEM_INSTR_IMPL_A64__prfw_i_p_bi_s
        IEM_INSTR_IMPL_A64__prfw_i_p_bi_s(prfop, Rn, Pg, imm6);
#else
        RT_NOREF(prfop, Rn, Pg, imm6, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/8500c000: PRFW  <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_prfm_ss, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfw_i_p_br_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0x8500c000))
    {
        uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: prfw_i_p_br_s prfop=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__prfw_i_p_br_s
            IEM_INSTR_IMPL_A64__prfw_i_p_br_s(prfop, Rn, Pg, Rm);
#else
            RT_NOREF(prfop, Rn, Pg, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e010/c460c000: PRFW  <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2]
   Instruction Set: A64  Groups: sve_mem_64b_prfm_sv2, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfw_i_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfw_i_p_bz_d_64_scaled prfop=%#x Rn=%#x Pg=%u msz=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, msz, Zm));
#ifdef IEM_INSTR_IMPL_A64__prfw_i_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__prfw_i_p_bz_d_64_scaled(prfop, Rn, Pg, msz, Zm);
#else
        RT_NOREF(prfop, Rn, Pg, msz, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e010/c4204000: PRFW  <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2]
   Instruction Set: A64  Groups: sve_mem_64b_prfm_sv, sve_mem64, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfw_i_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: prfw_i_p_bz_d_x32_scaled prfop=%#x Rn=%#x Pg=%u msz=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, msz, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__prfw_i_p_bz_d_x32_scaled
        IEM_INSTR_IMPL_A64__prfw_i_p_bz_d_x32_scaled(prfop, Rn, Pg, msz, Zm, xs);
#else
        RT_NOREF(prfop, Rn, Pg, msz, Zm, xs, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0e010/84204000: PRFW  <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2]
   Instruction Set: A64  Groups: sve_mem_32b_prfm_sv, sve_mem32, sve */
FNIEMOP_DEF_1(iemDecodeA64_prfw_i_p_bz_s_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e010)) == UINT32_C(0x84204000))
    {
        uint32_t const prfop      = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const xs         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: prfw_i_p_bz_s_x32_scaled prfop=%#x Rn=%#x Pg=%u msz=%u Zm=%#x xs=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, prfop, Rn, Pg, msz, Zm, xs));
#ifdef IEM_INSTR_IMPL_A64__prfw_i_p_bz_s_x32_scaled
            IEM_INSTR_IMPL_A64__prfw_i_p_bz_s_x32_scaled(prfop, Rn, Pg, msz, Zm, xs);
#else
            RT_NOREF(prfop, Rn, Pg, msz, Zm, xs, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20c210/25204000: PSEL  <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>]
   Instruction Set: A64  Groups: sve_int_pred_dup, sve_pred_dup, sve */
FNIEMOP_DEF_1(iemDecodeA64_psel_p_ppi, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x0000000f;
    uint32_t const Rv         = (uOpcode >> 16) & 0x00000003;
    uint32_t const tszl       = (uOpcode >> 18) & 0x00000007;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    uint32_t const i1         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: psel_p_ppi Pd=%#x Pm=%#x Pn=%#x Rv=%u tszl=%u tszh=%u i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pm, Pn, Rv, tszl, tszh, i1));
#ifdef IEM_INSTR_IMPL_A64__psel_p_ppi
        IEM_INSTR_IMPL_A64__psel_p_ppi(Pd, Pm, Pn, Rv, tszl, tszh, i1);
#else
        RT_NOREF(Pd, Pm, Pn, Rv, tszl, tszh, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffc21f/2550c000: PTEST  <Pg>, <Pn>.B
   Instruction Set: A64  Groups: sve_int_ptest, sve_pred_gen_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_ptest__p_p, uint32_t, uOpcode)
{
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ptest__p_p Pn=%#x Pg=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pn, Pg));
#ifdef IEM_INSTR_IMPL_A64__ptest__p_p
        IEM_INSTR_IMPL_A64__ptest__p_p(Pn, Pg);
#else
        RT_NOREF(Pn, Pg, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc10/2518e000: PTRUE  <Pd>.<T>{, <pattern>}
   Instruction Set: A64  Groups: sve_int_ptrue, sve_pred_gen_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_ptrue_p_s, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ptrue_p_s Pd=%#x pattern=%#x S=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, pattern, S, size));
#ifdef IEM_INSTR_IMPL_A64__ptrue_p_s
        IEM_INSTR_IMPL_A64__ptrue_p_s(Pd, pattern, S, size);
#else
        RT_NOREF(Pd, pattern, S, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffff8/25207810: PTRUE  <PNd>.<T>
   Instruction Set: A64  Groups: sve_int_pn_ptrue, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_ptrue_pn_i, uint32_t, uOpcode)
{
    uint32_t const PNd        = (uOpcode >>  0) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: ptrue_pn_i PNd=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, PNd, size));
#ifdef IEM_INSTR_IMPL_A64__ptrue_pn_i
        IEM_INSTR_IMPL_A64__ptrue_pn_i(PNd, size);
#else
        RT_NOREF(PNd, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc10/2519e000: PTRUES  <Pd>.<T>{, <pattern>}
   Instruction Set: A64  Groups: sve_int_ptrue, sve_pred_gen_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_ptrues_p_s, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ptrues_p_s Pd=%#x pattern=%#x S=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, pattern, S, size));
#ifdef IEM_INSTR_IMPL_A64__ptrues_p_s
        IEM_INSTR_IMPL_A64__ptrues_p_s(Pd, pattern, S, size);
#else
        RT_NOREF(Pd, pattern, S, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffe10/05314000: PUNPKHI  <Pd>.H, <Pn>.B
   Instruction Set: A64  Groups: sve_int_perm_punpk, sve_perm_predicates, sve */
FNIEMOP_DEF_1(iemDecodeA64_punpkhi_p_p, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffe10)) == UINT32_C(0x05314000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const H          = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: punpkhi_p_p Pd=%#x Pn=%#x H=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, H));
#ifdef IEM_INSTR_IMPL_A64__punpkhi_p_p
            IEM_INSTR_IMPL_A64__punpkhi_p_p(Pd, Pn, H);
#else
            RT_NOREF(Pd, Pn, H, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffe10/05304000: PUNPKLO  <Pd>.H, <Pn>.B
   Instruction Set: A64  Groups: sve_int_perm_punpk, sve_perm_predicates, sve */
FNIEMOP_DEF_1(iemDecodeA64_punpklo_p_p, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffe10)) == UINT32_C(0x05304000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const H          = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: punpklo_p_p Pd=%#x Pn=%#x H=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, H));
#ifdef IEM_INSTR_IMPL_A64__punpklo_p_p
            IEM_INSTR_IMPL_A64__punpklo_p_p(Pd, Pn, H);
#else
            RT_NOREF(Pd, Pn, H, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45206800: RADDHNB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_arith_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_raddhnb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: raddhnb_z_zz Zd=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__raddhnb_z_zz
        IEM_INSTR_IMPL_A64__raddhnb_z_zz(Zd, Zn, T, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45206c00: RADDHNT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_arith_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_raddhnt_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45206c00))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: raddhnt_z_zz Zd=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__raddhnt_z_zz
            IEM_INSTR_IMPL_A64__raddhnt_z_zz(Zd, Zn, T, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4520f400: RAX1  <Zd>.D, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_crypto_binary_const, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_rax1_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveSha3 /*FEAT_SVE_SHA3*/)
    {
        LogFlow(("%018x/%010x: rax1_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__rax1_z_zz
        IEM_INSTR_IMPL_A64__rax1_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/05278000: RBIT  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_rev, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_rbit_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x05278000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: rbit_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__rbit_z_p_z_m
            IEM_INSTR_IMPL_A64__rbit_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0527a000: RBIT  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_rev, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_rbit_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0527a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: rbit_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__rbit_z_p_z_z
            IEM_INSTR_IMPL_A64__rbit_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffff0/2519f000: RDFFR  <Pd>.B
   Instruction Set: A64  Groups: sve_int_rdffr_2, sve_pred_gen_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_rdffr_p_f, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: rdffr_p_f Pd=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd));
#ifdef IEM_INSTR_IMPL_A64__rdffr_p_f
        IEM_INSTR_IMPL_A64__rdffr_p_f(Pd);
#else
        RT_NOREF(Pd, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffe10/2518f000: RDFFR  <Pd>.B, <Pg>/Z
   Instruction Set: A64  Groups: sve_int_rdffr, sve_pred_gen_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_rdffr_p_p_f, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Pg         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const S          = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: rdffr_p_p_f Pd=%#x Pg=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pg, S));
#ifdef IEM_INSTR_IMPL_A64__rdffr_p_p_f
        IEM_INSTR_IMPL_A64__rdffr_p_p_f(Pd, Pg, S);
#else
        RT_NOREF(Pd, Pg, S, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffe10/2558f000: RDFFRS  <Pd>.B, <Pg>/Z
   Instruction Set: A64  Groups: sve_int_rdffr, sve_pred_gen_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_rdffrs_p_p_f, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffe10)) == UINT32_C(0x2558f000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const S          = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: rdffrs_p_p_f Pd=%#x Pg=%#x S=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pg, S));
#ifdef IEM_INSTR_IMPL_A64__rdffrs_p_p_f
            IEM_INSTR_IMPL_A64__rdffrs_p_p_f(Pd, Pg, S);
#else
            RT_NOREF(Pd, Pg, S, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffff800/04bf5800: RDSVL  <Xd>, #<imm>
   Instruction Set: A64  Groups: sve_int_read_svl_a, sve_alloca, sve */
FNIEMOP_DEF_1(iemDecodeA64_rdsvl_r_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffff800)) == UINT32_C(0x04bf5800))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm6       = (uOpcode >>  5) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: rdsvl_r_i Rd=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm6));
#ifdef IEM_INSTR_IMPL_A64__rdsvl_r_i
            IEM_INSTR_IMPL_A64__rdsvl_r_i(Rd, imm6);
#else
            RT_NOREF(Rd, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffff800/04bf5000: RDVL  <Xd>, #<imm>
   Instruction Set: A64  Groups: sve_int_read_vl_a, sve_alloca, sve */
FNIEMOP_DEF_1(iemDecodeA64_rdvl_r_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffff800)) == UINT32_C(0x04bf5000))
    {
        uint32_t const Rd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm6       = (uOpcode >>  5) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: rdvl_r_i Rd=%#x imm6=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rd, imm6));
#ifdef IEM_INSTR_IMPL_A64__rdvl_r_i
            IEM_INSTR_IMPL_A64__rdvl_r_i(Rd, imm6);
#else
            RT_NOREF(Rd, imm6, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe10/05344000: REV  <Pd>.<T>, <Pn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_reverse_p, sve_perm_predicates, sve */
FNIEMOP_DEF_1(iemDecodeA64_rev_p_p, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe10)) == UINT32_C(0x05344000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: rev_p_p Pd=%#x Pn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, size));
#ifdef IEM_INSTR_IMPL_A64__rev_p_p
            IEM_INSTR_IMPL_A64__rev_p_p(Pd, Pn, size);
#else
            RT_NOREF(Pd, Pn, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/05383800: REV  <Zd>.<T>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_reverse_z, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_rev_z_z, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: rev_z_z Zd=%#x Zn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size));
#ifdef IEM_INSTR_IMPL_A64__rev_z_z
        IEM_INSTR_IMPL_A64__rev_z_z(Zd, Zn, size);
#else
        RT_NOREF(Zd, Zn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/05248000: REVB  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_rev, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_revb_z_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x05248000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: revb_z_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__revb_z_z_m
            IEM_INSTR_IMPL_A64__revb_z_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0524a000: REVB  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_rev, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_revb_z_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0524a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: revb_z_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__revb_z_z_z
            IEM_INSTR_IMPL_A64__revb_z_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/052e8000: REVD  <Zd>.Q, <Pg>/M, <Zn>.Q
   Instruction Set: A64  Groups: sve_int_perm_revd, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_revd_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x052e8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: revd_z_p_z_m Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__revd_z_p_z_m
            IEM_INSTR_IMPL_A64__revd_z_p_z_m(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/052ea000: REVD  <Zd>.Q, <Pg>/Z, <Zn>.Q
   Instruction Set: A64  Groups: sve_int_perm_revd, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_revd_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x052ea000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: revd_z_p_z_z Zd=%#x Zn=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg));
#ifdef IEM_INSTR_IMPL_A64__revd_z_p_z_z
            IEM_INSTR_IMPL_A64__revd_z_p_z_z(Zd, Zn, Pg);
#else
            RT_NOREF(Zd, Zn, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/05258000: REVH  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_rev, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_revh_z_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x05258000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: revh_z_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__revh_z_z_m
            IEM_INSTR_IMPL_A64__revh_z_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0525a000: REVH  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_perm_rev, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_revh_z_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0525a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: revh_z_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__revh_z_z_z
            IEM_INSTR_IMPL_A64__revh_z_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/05268000: REVW  <Zd>.D, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_int_perm_rev, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_revw_z_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x05268000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: revw_z_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__revw_z_z_m
            IEM_INSTR_IMPL_A64__revw_z_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0526a000: REVW  <Zd>.D, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_int_perm_rev, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_revw_z_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0526a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: revw_z_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__revw_z_z_z
            IEM_INSTR_IMPL_A64__revw_z_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45201800: RSHRNB  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_rshrnb_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45201800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: rshrnb_z_zi Zd=%#x Zn=%#x T=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__rshrnb_z_zi
            IEM_INSTR_IMPL_A64__rshrnb_z_zi(Zd, Zn, T, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45201c00: RSHRNT  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_rshrnt_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45201c00))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: rshrnt_z_zi Zd=%#x Zn=%#x T=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__rshrnt_z_zi
            IEM_INSTR_IMPL_A64__rshrnt_z_zi(Zd, Zn, T, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45207800: RSUBHNB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_arith_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_rsubhnb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: rsubhnb_z_zz Zd=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__rsubhnb_z_zz
        IEM_INSTR_IMPL_A64__rsubhnb_z_zz(Zd, Zn, T, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45207c00: RSUBHNT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_arith_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_rsubhnt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: rsubhnt_z_zz Zd=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__rsubhnt_z_zz
        IEM_INSTR_IMPL_A64__rsubhnt_z_zz(Zd, Zn, T, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500f800: SABA  <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_aba, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_saba_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: saba_z_zzz Zda=%#x Zn=%#x U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__saba_z_zzz
        IEM_INSTR_IMPL_A64__saba_z_zzz(Zda, Zn, U, Zm, size);
#else
        RT_NOREF(Zda, Zn, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500c000: SABALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_aba_long, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_sabalb_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500c000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sabalb_z_zzz Zda=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sabalb_z_zzz
            IEM_INSTR_IMPL_A64__sabalb_z_zzz(Zda, Zn, T, U, Zm, size);
#else
            RT_NOREF(Zda, Zn, T, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500c400: SABALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_aba_long, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_sabalt_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sabalt_z_zzz Zda=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sabalt_z_zzz
        IEM_INSTR_IMPL_A64__sabalt_z_zzz(Zda, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040c0000: SABD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_1, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_sabd_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sabd_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sabd_z_p_zz
        IEM_INSTR_IMPL_A64__sabd_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45003000: SABDLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_sabdlb_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45003000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sabdlb_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sabdlb_z_zz
            IEM_INSTR_IMPL_A64__sabdlb_z_zz(Zd, Zn, T, U, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45003400: SABDLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_sabdlt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sabdlt_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sabdlt_z_zz
        IEM_INSTR_IMPL_A64__sabdlt_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4404a000: SADALP  <Zda>.<T>, <Pg>/M, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_intx_accumulate_long_pairs, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sadalp_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4404a000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sadalp_z_p_z Zda=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sadalp_z_p_z
            IEM_INSTR_IMPL_A64__sadalp_z_p_z(Zda, Zn, Pg, U, size);
#else
            RT_NOREF(Zda, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45000000: SADDLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_saddlb_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45000000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: saddlb_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__saddlb_z_zz
            IEM_INSTR_IMPL_A64__saddlb_z_zz(Zd, Zn, T, U, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45008000: SADDLBT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_clong, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_saddlbt_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45008000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: saddlbt_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__saddlbt_z_zz
            IEM_INSTR_IMPL_A64__saddlbt_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45000400: SADDLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_saddlt_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45000400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: saddlt_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__saddlt_z_zz
            IEM_INSTR_IMPL_A64__saddlt_z_zz(Zd, Zn, T, U, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04002000: SADDV  <Dd>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_reduce_0, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_saddv_r_p_z, uint32_t, uOpcode)
{
    uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: saddv_r_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__saddv_r_p_z
        IEM_INSTR_IMPL_A64__saddv_r_p_z(Vd, Zn, Pg, size);
#else
        RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45004000: SADDWB  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_wide, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_saddwb_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45004000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: saddwb_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__saddwb_z_zz
            IEM_INSTR_IMPL_A64__saddwb_z_zz(Zd, Zn, T, U, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45004400: SADDWT  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_wide, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_saddwt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: saddwt_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__saddwt_z_zz
        IEM_INSTR_IMPL_A64__saddwt_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/4580d000: SBCLB  <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_adc_long, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_sbclb_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x4580d000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sbclb_z_zzz Zda=%#x Zn=%#x T=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__sbclb_z_zzz
            IEM_INSTR_IMPL_A64__sbclb_z_zzz(Zda, Zn, T, Zm, sz);
#else
            RT_NOREF(Zda, Zn, T, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/4580d400: SBCLT  <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_adc_long, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_sbclt_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x4580d400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sbclt_z_zzz Zda=%#x Zn=%#x T=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__sbclt_z_zzz
            IEM_INSTR_IMPL_A64__sbclt_z_zzz(Zda, Zn, T, Zm, sz);
#else
            RT_NOREF(Zda, Zn, T, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc01/c120c400: SCLAMP  { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_clamp_int, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sclamp_mz_zz_2, uint32_t, uOpcode)
{
    uint32_t const U          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sclamp_mz_zz_2 U=%u Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sclamp_mz_zz_2
        IEM_INSTR_IMPL_A64__sclamp_mz_zz_2(U, Zd, Zn, Zm, size);
#else
        RT_NOREF(U, Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc03/c120cc00: SCLAMP  { <Zd1>.<T>-<Zd4>.<T> }, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_clamp_int, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sclamp_mz_zz_4, uint32_t, uOpcode)
{
    uint32_t const U          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sclamp_mz_zz_4 U=%u Zd=%u Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sclamp_mz_zz_4
        IEM_INSTR_IMPL_A64__sclamp_mz_zz_4(U, Zd, Zn, Zm, size);
#else
        RT_NOREF(U, Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4400c000: SCLAMP  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_clamp_lvl2, sve_intx_clamp, sve */
FNIEMOP_DEF_1(iemDecodeA64_sclamp_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4400c000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: sclamp_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sclamp_z_zz
            IEM_INSTR_IMPL_A64__sclamp_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc21/c122e000: SCVTF  { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_intfp_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_mz_z_2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const U          = (uOpcode >>  5) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: scvtf_mz_z_2 Zd=%#x U=%u Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn));
#ifdef IEM_INSTR_IMPL_A64__scvtf_mz_z_2
        IEM_INSTR_IMPL_A64__scvtf_mz_z_2(Zd, U, Zn);
#else
        RT_NOREF(Zd, U, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc63/c132e000: SCVTF  { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S }
   Instruction Set: A64  Groups: mortlach_multi4_intfp_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_mz_z_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc63)) == UINT32_C(0xc132e000))
    {
        uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
        uint32_t const U          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: scvtf_mz_z_4 Zd=%u U=%u Zn=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn));
#ifdef IEM_INSTR_IMPL_A64__scvtf_mz_z_4
            IEM_INSTR_IMPL_A64__scvtf_mz_z_4(Zd, U, Zn);
#else
            RT_NOREF(Zd, U, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6552a000: SCVTF  <Zd>.H, <Pg>/M, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_h2fp16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6552a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: scvtf_z_p_z_h2fp16 Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_h2fp16
            IEM_INSTR_IMPL_A64__scvtf_z_p_z_h2fp16(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/645cc000: SCVTF  <Zd>.H, <Pg>/Z, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_h2fp16z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x645cc000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: scvtf_z_p_z_h2fp16z Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_h2fp16z
            IEM_INSTR_IMPL_A64__scvtf_z_p_z_h2fp16z(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65d0a000: SCVTF  <Zd>.D, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_w2d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65d0a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: scvtf_z_p_z_w2d Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2d
            IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2d(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64dc8000: SCVTF  <Zd>.D, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_w2dz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64dc8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: scvtf_z_p_z_w2dz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2dz
            IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2dz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6554a000: SCVTF  <Zd>.H, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_w2fp16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6554a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: scvtf_z_p_z_w2fp16 Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2fp16
            IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2fp16(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/645d8000: SCVTF  <Zd>.H, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_w2fp16z, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
    {
        LogFlow(("%018x/%010x: scvtf_z_p_z_w2fp16z Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2fp16z
        IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2fp16z(Zd, Zn, Pg, int_U);
#else
        RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6594a000: SCVTF  <Zd>.S, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_w2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6594a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: scvtf_z_p_z_w2s Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2s
            IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2s(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/649d8000: SCVTF  <Zd>.S, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_w2sz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x649d8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: scvtf_z_p_z_w2sz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2sz
            IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2sz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65d6a000: SCVTF  <Zd>.D, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_x2d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65d6a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: scvtf_z_p_z_x2d Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2d
            IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2d(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64ddc000: SCVTF  <Zd>.D, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_x2dz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
    {
        LogFlow(("%018x/%010x: scvtf_z_p_z_x2dz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2dz
        IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2dz(Zd, Zn, Pg, int_U);
#else
        RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6556a000: SCVTF  <Zd>.H, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_x2fp16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6556a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: scvtf_z_p_z_x2fp16 Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2fp16
            IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2fp16(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/645dc000: SCVTF  <Zd>.H, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_x2fp16z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x645dc000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: scvtf_z_p_z_x2fp16z Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2fp16z
            IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2fp16z(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65d4a000: SCVTF  <Zd>.S, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_x2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65d4a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: scvtf_z_p_z_x2s Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2s
            IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2s(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64dd8000: SCVTF  <Zd>.S, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_scvtf_z_p_z_x2sz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64dd8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: scvtf_z_p_z_x2sz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2sz
            IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2sz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04140000: SDIV  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_div, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_sdiv_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sdiv_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sdiv_z_p_zz
        IEM_INSTR_IMPL_A64__sdiv_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04160000: SDIVR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_div, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_sdivr_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sdivr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sdivr_z_p_zz
        IEM_INSTR_IMPL_A64__sdivr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4400c800: SDOT  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_intx_dot2_lvl2, sve_intx_dot2, sve */
FNIEMOP_DEF_1(iemDecodeA64_sdot_z32_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: sdot_z32_zzz Zda=%#x Zn=%#x U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__sdot_z32_zzz
        IEM_INSTR_IMPL_A64__sdot_z32_zzz(Zda, Zn, U, Zm);
#else
        RT_NOREF(Zda, Zn, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4480c800: SDOT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_dot2_by_indexed_elem_lvl2, sve_intx_dot2_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sdot_z32_zzzi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4480c800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: sdot_z32_zzzi Zda=%#x Zn=%#x U=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__sdot_z32_zzzi
            IEM_INSTR_IMPL_A64__sdot_z32_zzzi(Zda, Zn, U, Zm, i2);
#else
            RT_NOREF(Zda, Zn, U, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/44800000: SDOT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_dot, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sdot_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x44800000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sdot_z_zzz Zda=%#x Zn=%#x U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sdot_z_zzz
            IEM_INSTR_IMPL_A64__sdot_z_zzz(Zda, Zn, U, Zm, size);
#else
            RT_NOREF(Zda, Zn, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44e00000: SDOT  <Zda>.D, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_dot_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sdot_z_zzzi_d, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sdot_z_zzzi_d Zda=%#x Zn=%#x U=%u Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__sdot_z_zzzi_d
        IEM_INSTR_IMPL_A64__sdot_z_zzzi_d(Zda, Zn, U, Zm, i1);
#else
        RT_NOREF(Zda, Zn, U, Zm, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44a00000: SDOT  <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
   Instruction Set: A64  Groups: sve_intx_dot_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sdot_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sdot_z_zzzi_s Zda=%#x Zn=%#x U=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__sdot_z_zzzi_s
        IEM_INSTR_IMPL_A64__sdot_z_zzzi_s(Zda, Zn, U, Zm, i2);
#else
        RT_NOREF(Zda, Zn, U, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1501000: SDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za32_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1501000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sdot_za32_zzi_2xi off3=%u U=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sdot_za32_zzi_2xi
            IEM_INSTR_IMPL_A64__sdot_za32_zzi_2xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1509000: SDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za32_zzi_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1509000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sdot_za32_zzi_4xi off3=%u U=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sdot_za32_zzi_4xi
            IEM_INSTR_IMPL_A64__sdot_za32_zzi_4xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1601408: SDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_z_za_2way_dot_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za32_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1601408))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sdot_za32_zzv_2x1 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sdot_za32_zzv_2x1
            IEM_INSTR_IMPL_A64__sdot_za32_zzv_2x1(off3, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1701408: SDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_z_za_2way_dot_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za32_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1701408))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sdot_za32_zzv_4x1 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sdot_za32_zzv_4x1
            IEM_INSTR_IMPL_A64__sdot_za32_zzv_4x1(off3, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c38/c1e01408: SDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_2way_dot_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za32_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c38)) == UINT32_C(0xc1e01408))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sdot_za32_zzw_2x2 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sdot_za32_zzw_2x2
            IEM_INSTR_IMPL_A64__sdot_za32_zzw_2x2(off3, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c78/c1e11408: SDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_2way_dot_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za32_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c78)) == UINT32_C(0xc1e11408))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sdot_za32_zzw_4x4 off3=%u U=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sdot_za32_zzw_4x4
            IEM_INSTR_IMPL_A64__sdot_za32_zzw_4x4(off3, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09838/c1d00008: SDOT  ZA.D[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_d, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za_zzi_d2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09838)) == UINT32_C(0xc1d00008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: sdot_za_zzi_d2xi off3=%u U=%u Zn=%#x i1=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i1, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sdot_za_zzi_d2xi
            IEM_INSTR_IMPL_A64__sdot_za_zzi_d2xi(off3, U, Zn, i1, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i1, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09878/c1d08008: SDOT  ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_d, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za_zzi_d4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09878)) == UINT32_C(0xc1d08008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i1         = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: sdot_za_zzi_d4xi off3=%u U=%u Zn=%u i1=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i1, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sdot_za_zzi_d4xi
            IEM_INSTR_IMPL_A64__sdot_za_zzi_d4xi(off3, U, Zn, i1, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i1, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1501020: SDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za_zzi_s2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1501020))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sdot_za_zzi_s2xi off3=%u U=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sdot_za_zzi_s2xi
            IEM_INSTR_IMPL_A64__sdot_za_zzi_s2xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1509020: SDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1509020))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sdot_za_zzi_s4xi off3=%u U=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sdot_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__sdot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c18/c1201400: SDOT  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi2_z_za_4way_dot_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c18)) == UINT32_C(0xc1201400))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sdot_za_zzv_2x1 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__sdot_za_zzv_2x1
            IEM_INSTR_IMPL_A64__sdot_za_zzv_2x1(off3, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c18/c1301400: SDOT  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi4_z_za_4way_dot_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c18)) == UINT32_C(0xc1301400))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sdot_za_zzv_4x1 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__sdot_za_zzv_4x1
            IEM_INSTR_IMPL_A64__sdot_za_zzv_4x1(off3, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa19c38/c1a01400: SDOT  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, { <Zm1>.<Tb>-<Zm2>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_4way_dot_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const U          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sdot_za_zzw_2x2 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__sdot_za_zzw_2x2
        IEM_INSTR_IMPL_A64__sdot_za_zzw_2x2(off3, U, Zn, Rv, Zm, sz);
#else
        RT_NOREF(off3, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa39c78/c1a11400: SDOT  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, { <Zm1>.<Tb>-<Zm4>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_4way_dot_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_sdot_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa39c78)) == UINT32_C(0xc1a11400))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sdot_za_zzw_4x4 off3=%u U=%u Zn=%u Rv=%u Zm=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__sdot_za_zzw_4x4
            IEM_INSTR_IMPL_A64__sdot_za_zzw_4x4(off3, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21e021/c1208000: SEL  { <Zd1>.<T>-<Zd2>.<T> }, <PNg>, { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_select_int, mortlach_multi_sve_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_sel_mz_p_zz_2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sel_mz_p_zz_2 Zd=%#x Zn=%#x PNg=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, PNg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sel_mz_p_zz_2
        IEM_INSTR_IMPL_A64__sel_mz_p_zz_2(Zd, Zn, PNg, Zm, size);
#else
        RT_NOREF(Zd, Zn, PNg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23e063/c1218000: SEL  { <Zd1>.<T>-<Zd4>.<T> }, <PNg>, { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_select_int, mortlach_multi_sve_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_sel_mz_p_zz_4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sel_mz_p_zz_4 Zd=%u Zn=%u PNg=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, PNg, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sel_mz_p_zz_4
        IEM_INSTR_IMPL_A64__sel_mz_p_zz_4(Zd, Zn, PNg, Zm, size);
#else
        RT_NOREF(Zd, Zn, PNg, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0c210/25004210: SEL  <Pd>.B, <Pg>, <Pn>.B, <Pm>.B
   Instruction Set: A64  Groups: sve_int_pred_log, sve_pred_gen_a, sve */
FNIEMOP_DEF_1(iemDecodeA64_sel_p_p_pp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25004210))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sel_p_p_pp Pd=%#x Pn=%#x Pg=%#x Pm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, Pg, Pm));
#ifdef IEM_INSTR_IMPL_A64__sel_p_p_pp
            IEM_INSTR_IMPL_A64__sel_p_p_pp(Pd, Pn, Pg, Pm);
#else
            RT_NOREF(Pd, Pn, Pg, Pm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20c000/0520c000: SEL  <Zd>.<T>, <Pv>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_sel_vvv, sve_int_select, sve */
FNIEMOP_DEF_1(iemDecodeA64_sel_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20c000)) == UINT32_C(0x0520c000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pv         = (uOpcode >> 10) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sel_z_p_zz Zd=%#x Zn=%#x Pv=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pv, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sel_z_p_zz
            IEM_INSTR_IMPL_A64__sel_z_p_zz(Zd, Zn, Pv, Zm, size);
#else
            RT_NOREF(Zd, Zn, Pv, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/252c9000: SETFFR
   Instruction Set: A64  Groups: sve_int_setffr, sve_pred_wrffr, sve */
FNIEMOP_DEF_1(iemDecodeA64_setffr_f, uint32_t, uOpcode)
{
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: setffr_f\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__setffr_f
        IEM_INSTR_IMPL_A64__setffr_f();
#else
        RT_NOREF(pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44108000: SHADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_shadd_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44108000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: shadd_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__shadd_z_p_zz
            IEM_INSTR_IMPL_A64__shadd_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45201000: SHRNB  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_shrnb_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: shrnb_z_zi Zd=%#x Zn=%#x T=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__shrnb_z_zi
        IEM_INSTR_IMPL_A64__shrnb_z_zi(Zd, Zn, T, imm3, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45201400: SHRNT  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_shrnt_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: shrnt_z_zi Zd=%#x Zn=%#x T=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__shrnt_z_zi
        IEM_INSTR_IMPL_A64__shrnt_z_zi(Zd, Zn, T, imm3, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44128000: SHSUB  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_shsub_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44128000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: shsub_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__shsub_z_p_zz
            IEM_INSTR_IMPL_A64__shsub_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44168000: SHSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_shsubr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44168000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: shsubr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__shsubr_z_p_zz
            IEM_INSTR_IMPL_A64__shsubr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500f400: SLI  <Zd>.<T>, <Zn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_insert, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_sli_z_zzi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500f400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sli_z_zzi Zd=%#x Zn=%#x imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sli_z_zzi
            IEM_INSTR_IMPL_A64__sli_z_zzi(Zd, Zn, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc00/4523e000: SM4E  <Zdn>.S, <Zdn>.S, <Zm>.S
   Instruction Set: A64  Groups: sve_crypto_binary_dest, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_sm4e_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveSm4 /*FEAT_SVE_SM4*/)
    {
        LogFlow(("%018x/%010x: sm4e_z_zz Zdn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm));
#ifdef IEM_INSTR_IMPL_A64__sm4e_z_zz
        IEM_INSTR_IMPL_A64__sm4e_z_zz(Zdn, Zm);
#else
        RT_NOREF(Zdn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4520f000: SM4EKEY  <Zd>.S, <Zn>.S, <Zm>.S
   Instruction Set: A64  Groups: sve_crypto_binary_const, sve_intx_crypto, sve */
FNIEMOP_DEF_1(iemDecodeA64_sm4ekey_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSveSm4 /*FEAT_SVE_SM4*/)
    {
        LogFlow(("%018x/%010x: sm4ekey_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__sm4ekey_z_zz
        IEM_INSTR_IMPL_A64__sm4ekey_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a000: SMAX  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_minmax_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smax_mz_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a000))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smax_mz_zzv_2x1 U=%u Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smax_mz_zzv_2x1
            IEM_INSTR_IMPL_A64__smax_mz_zzv_2x1(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120a800: SMAX  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_minmax_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_smax_mz_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const U          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: smax_mz_zzv_4x1 U=%u Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smax_mz_zzv_4x1
        IEM_INSTR_IMPL_A64__smax_mz_zzv_4x1(U, Zdn, Zm, size);
#else
        RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b000: SMAX  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_minmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_smax_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const U          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: smax_mz_zzw_2x2 U=%u Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smax_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__smax_mz_zzw_2x2(U, Zdn, Zm, size);
#else
        RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120b800: SMAX  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_minmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_smax_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const U          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: smax_mz_zzw_4x4 U=%u Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smax_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__smax_mz_zzw_4x4(U, Zdn, Zm, size);
#else
        RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04080000: SMAX  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_1, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_smax_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smax_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__smax_z_p_zz
        IEM_INSTR_IMPL_A64__smax_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/2528c000: SMAX  <Zdn>.<T>, <Zdn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_arith_imm1, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_smax_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x2528c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: smax_z_zi Zdn=%#x imm8=%#x U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm8, U, size));
#ifdef IEM_INSTR_IMPL_A64__smax_z_zi
            IEM_INSTR_IMPL_A64__smax_z_zi(Zdn, imm8, U, size);
#else
            RT_NOREF(Zdn, imm8, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4414a000: SMAXP  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_arith_binary_pairs, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_smaxp_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4414a000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: smaxp_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__smaxp_z_p_zz
            IEM_INSTR_IMPL_A64__smaxp_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040c2000: SMAXQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_int_reduce_1q, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_smaxqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040c2000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: smaxqv_z_p_z Vd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__smaxqv_z_p_z
            IEM_INSTR_IMPL_A64__smaxqv_z_p_z(Vd, Zn, Pg, U, size);
#else
            RT_NOREF(Vd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04082000: SMAXV  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_reduce_1, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_smaxv_r_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04082000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: smaxv_r_p_z Vd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__smaxv_r_p_z
            IEM_INSTR_IMPL_A64__smaxv_r_p_z(Vd, Zn, Pg, U, size);
#else
            RT_NOREF(Vd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a020: SMIN  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_minmax_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smin_mz_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a020))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smin_mz_zzv_2x1 U=%u Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smin_mz_zzv_2x1
            IEM_INSTR_IMPL_A64__smin_mz_zzv_2x1(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120a820: SMIN  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_minmax_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_smin_mz_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120a820))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smin_mz_zzv_4x1 U=%u Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smin_mz_zzv_4x1
            IEM_INSTR_IMPL_A64__smin_mz_zzv_4x1(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b020: SMIN  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_minmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_smin_mz_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b020))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smin_mz_zzw_2x2 U=%u Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smin_mz_zzw_2x2
            IEM_INSTR_IMPL_A64__smin_mz_zzw_2x2(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120b820: SMIN  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_minmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_smin_mz_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120b820))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smin_mz_zzw_4x4 U=%u Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smin_mz_zzw_4x4
            IEM_INSTR_IMPL_A64__smin_mz_zzw_4x4(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040a0000: SMIN  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_1, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_smin_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smin_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__smin_z_p_zz
        IEM_INSTR_IMPL_A64__smin_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/252ac000: SMIN  <Zdn>.<T>, <Zdn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_arith_imm1, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_smin_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x252ac000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: smin_z_zi Zdn=%#x imm8=%#x U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm8, U, size));
#ifdef IEM_INSTR_IMPL_A64__smin_z_zi
            IEM_INSTR_IMPL_A64__smin_z_zi(Zdn, imm8, U, size);
#else
            RT_NOREF(Zdn, imm8, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4416a000: SMINP  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_arith_binary_pairs, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sminp_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4416a000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sminp_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sminp_z_p_zz
            IEM_INSTR_IMPL_A64__sminp_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040e2000: SMINQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_int_reduce_1q, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_sminqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040e2000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: sminqv_z_p_z Vd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sminqv_z_p_z
            IEM_INSTR_IMPL_A64__sminqv_z_p_z(Vd, Zn, Pg, U, size);
#else
            RT_NOREF(Vd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040a2000: SMINV  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_reduce_1, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_sminv_r_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040a2000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sminv_r_p_z Vd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sminv_r_p_z
            IEM_INSTR_IMPL_A64__sminv_r_p_z(Vd, Zn, Pg, U, size);
#else
            RT_NOREF(Vd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff01018/c1c01000: SMLAL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_idx, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlal_za_zzi_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff01018)) == UINT32_C(0xc1c01000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i3l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlal_za_zzi_1 off3=%u S=%u U=%u Zn=%#x i3l=%u Rv=%u i3h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, U, Zn, i3l, Rv, i3h, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlal_za_zzi_1
            IEM_INSTR_IMPL_A64__smlal_za_zzi_1(off3, S, U, Zn, i3l, Rv, i3h, Zm);
#else
            RT_NOREF(off3, S, U, Zn, i3l, Rv, i3h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1d01000: SMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_idx, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlal_za_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1d01000))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlal_za_zzi_2xi off2=%u i3l=%u S=%u U=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlal_za_zzi_2xi
            IEM_INSTR_IMPL_A64__smlal_za_zzi_2xi(off2, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1d09000: SMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_idx, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlal_za_zzi_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1d09000))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlal_za_zzi_4xi off2=%u i3l=%u S=%u U=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlal_za_zzi_4xi
            IEM_INSTR_IMPL_A64__smlal_za_zzi_4xi(off2, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1600c00: SMLAL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_mla_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlal_za_zzv_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1600c00))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlal_za_zzv_1 off3=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlal_za_zzv_1
            IEM_INSTR_IMPL_A64__smlal_za_zzv_1(off3, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1600800: SMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlal_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1600800))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlal_za_zzv_2x1 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlal_za_zzv_2x1
            IEM_INSTR_IMPL_A64__smlal_za_zzv_2x1(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1700800: SMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlal_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1700800))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlal_za_zzv_4x1 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlal_za_zzv_4x1
            IEM_INSTR_IMPL_A64__smlal_za_zzv_4x1(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c3c/c1e00800: SMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlal_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c3c)) == UINT32_C(0xc1e00800))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlal_za_zzw_2x2 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlal_za_zzw_2x2
            IEM_INSTR_IMPL_A64__smlal_za_zzw_2x2(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c7c/c1e10800: SMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlal_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c7c)) == UINT32_C(0xc1e10800))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlal_za_zzw_4x4 off2=%u S=%u U=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlal_za_zzw_4x4
            IEM_INSTR_IMPL_A64__smlal_za_zzw_4x4(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44004000: SMLALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_mlal_long, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_smlalb_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44004000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: smlalb_z_zzz Zda=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smlalb_z_zzz
            IEM_INSTR_IMPL_A64__smlalb_z_zzz(Zda, Zn, T, U, Zm, size);
#else
            RT_NOREF(Zda, Zn, T, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e08000: SMLALB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_smlalb_z_zzzi_d, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const S          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smlalb_z_zzzi_d Zda=%#x Zn=%#x T=%u i2l=%u U=%u S=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i2l, U, S, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__smlalb_z_zzzi_d
        IEM_INSTR_IMPL_A64__smlalb_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h);
#else
        RT_NOREF(Zda, Zn, T, i2l, U, S, Zm, i2h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a08000: SMLALB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_smlalb_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const S          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smlalb_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u U=%u S=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, U, S, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__smlalb_z_zzzi_s
        IEM_INSTR_IMPL_A64__smlalb_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h);
#else
        RT_NOREF(Zda, Zn, T, i3l, U, S, Zm, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0101c/c1800000: SMLALL  ZA.D[<Wv>, <offs1>:<offs4>], <Zn>.H, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_long_idx_d, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlall_za_zzi_d, uint32_t, uOpcode)
{
    uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const U          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i3l        = (uOpcode >> 10) & 0x00000003;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const i3h        = (uOpcode >> 15) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: smlall_za_zzi_d off2=%u S=%u U=%u Zn=%#x i3l=%u Rv=%u i3h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, i3l, Rv, i3h, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlall_za_zzi_d
        IEM_INSTR_IMPL_A64__smlall_za_zzi_d(off2, S, U, Zn, i3l, Rv, i3h, Zm);
#else
        RT_NOREF(off2, S, U, Zn, i3l, Rv, i3h, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09838/c1900000: SMLALL  ZA.D[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_long_idx_d, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlall_za_zzi_d2xi, uint32_t, uOpcode)
{
    uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
    uint32_t const i3l        = (uOpcode >>  1) & 0x00000003;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const U          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const i3h        = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: smlall_za_zzi_d2xi o1=%u i3l=%u S=%u U=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlall_za_zzi_d2xi
        IEM_INSTR_IMPL_A64__smlall_za_zzi_d2xi(o1, i3l, S, U, Zn, i3h, Rv, Zm);
#else
        RT_NOREF(o1, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09878/c1908000: SMLALL  ZA.D[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_long_idx_d, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlall_za_zzi_d4xi, uint32_t, uOpcode)
{
    uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
    uint32_t const i3l        = (uOpcode >>  1) & 0x00000003;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const U          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const i3h        = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: smlall_za_zzi_d4xi o1=%u i3l=%u S=%u U=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlall_za_zzi_d4xi
        IEM_INSTR_IMPL_A64__smlall_za_zzi_d4xi(o1, i3l, S, U, Zn, i3h, Rv, Zm);
#else
        RT_NOREF(o1, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0001c/c1000000: SMLALL  ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_long_idx_s, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlall_za_zzi_s, uint32_t, uOpcode)
{
    uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const U          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i4l        = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const i4h        = (uOpcode >> 15) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: smlall_za_zzi_s off2=%u S=%u U=%u Zn=%#x i4l=%u Rv=%u i4h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, i4l, Rv, i4h, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlall_za_zzi_s
        IEM_INSTR_IMPL_A64__smlall_za_zzi_s(off2, S, U, Zn, i4l, Rv, i4h, Zm);
#else
        RT_NOREF(off2, S, U, Zn, i4l, Rv, i4h, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1100000: SMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_long_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlall_za_zzi_s2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1100000))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlall_za_zzi_s2xi o1=%u i4l=%u S=%u U=%u Zn=%#x i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, S, U, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlall_za_zzi_s2xi
            IEM_INSTR_IMPL_A64__smlall_za_zzi_s2xi(o1, i4l, S, U, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, S, U, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1108000: SMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_long_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlall_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1108000))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlall_za_zzi_s4xi o1=%u i4l=%u S=%u U=%u Zn=%u i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, S, U, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlall_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__smlall_za_zzi_s4xi(o1, i4l, S, U, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, S, U, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c1c/c1200400: SMLALL  ZA.<T>[<Wv>, <offs1>:<offs4>], <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_mla_long_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlall_za_zzv_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c1c)) == UINT32_C(0xc1200400))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlall_za_zzv_1 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__smlall_za_zzv_1
            IEM_INSTR_IMPL_A64__smlall_za_zzv_1(off2, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c1e/c1200000: SMLALL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlall_za_zzv_2x1, uint32_t, uOpcode)
{
    uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const U          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: smlall_za_zzv_2x1 o1=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__smlall_za_zzv_2x1
        IEM_INSTR_IMPL_A64__smlall_za_zzv_2x1(o1, S, U, Zn, Rv, Zm, sz);
#else
        RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c1e/c1300000: SMLALL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlall_za_zzv_4x1, uint32_t, uOpcode)
{
    uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const U          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: smlall_za_zzv_4x1 o1=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__smlall_za_zzv_4x1
        IEM_INSTR_IMPL_A64__smlall_za_zzv_4x1(o1, S, U, Zn, Rv, Zm, sz);
#else
        RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa19c3e/c1a00000: SMLALL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, { <Zm1>.<Tb>-<Zm2>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlall_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa19c3e)) == UINT32_C(0xc1a00000))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlall_za_zzw_2x2 o1=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__smlall_za_zzw_2x2
            IEM_INSTR_IMPL_A64__smlall_za_zzw_2x2(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa39c7e/c1a10000: SMLALL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, { <Zm1>.<Tb>-<Zm4>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlall_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa39c7e)) == UINT32_C(0xc1a10000))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlall_za_zzw_4x4 o1=%u S=%u U=%u Zn=%u Rv=%u Zm=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__smlall_za_zzw_4x4
            IEM_INSTR_IMPL_A64__smlall_za_zzw_4x4(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44004400: SMLALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_mlal_long, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_smlalt_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smlalt_z_zzz Zda=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smlalt_z_zzz
        IEM_INSTR_IMPL_A64__smlalt_z_zzz(Zda, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e08400: SMLALT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_smlalt_z_zzzi_d, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const S          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smlalt_z_zzzi_d Zda=%#x Zn=%#x T=%u i2l=%u U=%u S=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i2l, U, S, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__smlalt_z_zzzi_d
        IEM_INSTR_IMPL_A64__smlalt_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h);
#else
        RT_NOREF(Zda, Zn, T, i2l, U, S, Zm, i2h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a08400: SMLALT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_smlalt_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const S          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smlalt_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u U=%u S=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, U, S, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__smlalt_z_zzzi_s
        IEM_INSTR_IMPL_A64__smlalt_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h);
#else
        RT_NOREF(Zda, Zn, T, i3l, U, S, Zm, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff01018/c1c01008: SMLSL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_idx, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsl_za_zzi_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff01018)) == UINT32_C(0xc1c01008))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i3l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsl_za_zzi_1 off3=%u S=%u U=%u Zn=%#x i3l=%u Rv=%u i3h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, U, Zn, i3l, Rv, i3h, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsl_za_zzi_1
            IEM_INSTR_IMPL_A64__smlsl_za_zzi_1(off3, S, U, Zn, i3l, Rv, i3h, Zm);
#else
            RT_NOREF(off3, S, U, Zn, i3l, Rv, i3h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1d01008: SMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_idx, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsl_za_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1d01008))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsl_za_zzi_2xi off2=%u i3l=%u S=%u U=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsl_za_zzi_2xi
            IEM_INSTR_IMPL_A64__smlsl_za_zzi_2xi(off2, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1d09008: SMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_idx, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsl_za_zzi_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1d09008))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsl_za_zzi_4xi off2=%u i3l=%u S=%u U=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsl_za_zzi_4xi
            IEM_INSTR_IMPL_A64__smlsl_za_zzi_4xi(off2, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1600c08: SMLSL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_mla_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsl_za_zzv_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1600c08))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsl_za_zzv_1 off3=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsl_za_zzv_1
            IEM_INSTR_IMPL_A64__smlsl_za_zzv_1(off3, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1600808: SMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsl_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1600808))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsl_za_zzv_2x1 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsl_za_zzv_2x1
            IEM_INSTR_IMPL_A64__smlsl_za_zzv_2x1(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1700808: SMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsl_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1700808))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsl_za_zzv_4x1 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsl_za_zzv_4x1
            IEM_INSTR_IMPL_A64__smlsl_za_zzv_4x1(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c3c/c1e00808: SMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsl_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c3c)) == UINT32_C(0xc1e00808))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsl_za_zzw_2x2 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsl_za_zzw_2x2
            IEM_INSTR_IMPL_A64__smlsl_za_zzw_2x2(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c7c/c1e10808: SMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsl_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c7c)) == UINT32_C(0xc1e10808))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsl_za_zzw_4x4 off2=%u S=%u U=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsl_za_zzw_4x4
            IEM_INSTR_IMPL_A64__smlsl_za_zzw_4x4(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44005000: SMLSLB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_mlal_long, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_smlslb_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smlslb_z_zzz Zda=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smlslb_z_zzz
        IEM_INSTR_IMPL_A64__smlslb_z_zzz(Zda, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e0a000: SMLSLB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_smlslb_z_zzzi_d, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const S          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smlslb_z_zzzi_d Zda=%#x Zn=%#x T=%u i2l=%u U=%u S=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i2l, U, S, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__smlslb_z_zzzi_d
        IEM_INSTR_IMPL_A64__smlslb_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h);
#else
        RT_NOREF(Zda, Zn, T, i2l, U, S, Zm, i2h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a0a000: SMLSLB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_smlslb_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const S          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smlslb_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u U=%u S=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, U, S, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__smlslb_z_zzzi_s
        IEM_INSTR_IMPL_A64__smlslb_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h);
#else
        RT_NOREF(Zda, Zn, T, i3l, U, S, Zm, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0101c/c1800008: SMLSLL  ZA.D[<Wv>, <offs1>:<offs4>], <Zn>.H, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_long_idx_d, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsll_za_zzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0101c)) == UINT32_C(0xc1800008))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i3l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smlsll_za_zzi_d off2=%u S=%u U=%u Zn=%#x i3l=%u Rv=%u i3h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, i3l, Rv, i3h, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsll_za_zzi_d
            IEM_INSTR_IMPL_A64__smlsll_za_zzi_d(off2, S, U, Zn, i3l, Rv, i3h, Zm);
#else
            RT_NOREF(off2, S, U, Zn, i3l, Rv, i3h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09838/c1900008: SMLSLL  ZA.D[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_long_idx_d, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsll_za_zzi_d2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09838)) == UINT32_C(0xc1900008))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i3l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smlsll_za_zzi_d2xi o1=%u i3l=%u S=%u U=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsll_za_zzi_d2xi
            IEM_INSTR_IMPL_A64__smlsll_za_zzi_d2xi(o1, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(o1, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09878/c1908008: SMLSLL  ZA.D[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_long_idx_d, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsll_za_zzi_d4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09878)) == UINT32_C(0xc1908008))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i3l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smlsll_za_zzi_d4xi o1=%u i3l=%u S=%u U=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsll_za_zzi_d4xi
            IEM_INSTR_IMPL_A64__smlsll_za_zzi_d4xi(o1, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(o1, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0001c/c1000008: SMLSLL  ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_long_idx_s, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsll_za_zzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0001c)) == UINT32_C(0xc1000008))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i4l        = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i4h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsll_za_zzi_s off2=%u S=%u U=%u Zn=%#x i4l=%u Rv=%u i4h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, i4l, Rv, i4h, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsll_za_zzi_s
            IEM_INSTR_IMPL_A64__smlsll_za_zzi_s(off2, S, U, Zn, i4l, Rv, i4h, Zm);
#else
            RT_NOREF(off2, S, U, Zn, i4l, Rv, i4h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1100008: SMLSLL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_long_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsll_za_zzi_s2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1100008))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsll_za_zzi_s2xi o1=%u i4l=%u S=%u U=%u Zn=%#x i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, S, U, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsll_za_zzi_s2xi
            IEM_INSTR_IMPL_A64__smlsll_za_zzi_s2xi(o1, i4l, S, U, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, S, U, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1108008: SMLSLL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_long_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsll_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1108008))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsll_za_zzi_s4xi o1=%u i4l=%u S=%u U=%u Zn=%u i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, S, U, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__smlsll_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__smlsll_za_zzi_s4xi(o1, i4l, S, U, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, S, U, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c1c/c1200408: SMLSLL  ZA.<T>[<Wv>, <offs1>:<offs4>], <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_mla_long_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsll_za_zzv_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c1c)) == UINT32_C(0xc1200408))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsll_za_zzv_1 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__smlsll_za_zzv_1
            IEM_INSTR_IMPL_A64__smlsll_za_zzv_1(off2, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c1e/c1200008: SMLSLL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsll_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c1e)) == UINT32_C(0xc1200008))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsll_za_zzv_2x1 o1=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__smlsll_za_zzv_2x1
            IEM_INSTR_IMPL_A64__smlsll_za_zzv_2x1(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c1e/c1300008: SMLSLL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsll_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c1e)) == UINT32_C(0xc1300008))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsll_za_zzv_4x1 o1=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__smlsll_za_zzv_4x1
            IEM_INSTR_IMPL_A64__smlsll_za_zzv_4x1(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa19c3e/c1a00008: SMLSLL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, { <Zm1>.<Tb>-<Zm2>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsll_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa19c3e)) == UINT32_C(0xc1a00008))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsll_za_zzw_2x2 o1=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__smlsll_za_zzw_2x2
            IEM_INSTR_IMPL_A64__smlsll_za_zzw_2x2(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa39c7e/c1a10008: SMLSLL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, { <Zm1>.<Tb>-<Zm4>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_smlsll_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa39c7e)) == UINT32_C(0xc1a10008))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: smlsll_za_zzw_4x4 o1=%u S=%u U=%u Zn=%u Rv=%u Zm=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__smlsll_za_zzw_4x4
            IEM_INSTR_IMPL_A64__smlsll_za_zzw_4x4(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44005400: SMLSLT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_mlal_long, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_smlslt_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smlslt_z_zzz Zda=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smlslt_z_zzz
        IEM_INSTR_IMPL_A64__smlslt_z_zzz(Zda, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e0a400: SMLSLT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_smlslt_z_zzzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e0a400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const S          = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: smlslt_z_zzzi_d Zda=%#x Zn=%#x T=%u i2l=%u U=%u S=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i2l, U, S, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__smlslt_z_zzzi_d
            IEM_INSTR_IMPL_A64__smlslt_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h);
#else
            RT_NOREF(Zda, Zn, T, i2l, U, S, Zm, i2h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a0a400: SMLSLT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_smlslt_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a0a400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const S          = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: smlslt_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u U=%u S=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, U, S, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__smlslt_z_zzzi_s
            IEM_INSTR_IMPL_A64__smlslt_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, T, i3l, U, S, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/45009800: SMMLA  <Zda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_intx_mmla, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_smmla_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x45009800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const uns        = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fI8mm /*FEAT_I8MM*/)
        {
            LogFlow(("%018x/%010x: smmla_z_zzz Zda=%#x Zn=%#x Zm=%#x uns=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm, uns));
#ifdef IEM_INSTR_IMPL_A64__smmla_z_zzz
            IEM_INSTR_IMPL_A64__smmla_z_zzz(Zda, Zn, Zm, uns);
#else
            RT_NOREF(Zda, Zn, Zm, uns, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80008008: SMOP4A  <ZAda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4a_za32_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80008008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4a_za32_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4a_za32_zz_h1x1
            IEM_INSTR_IMPL_A64__smop4a_za32_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80108008: SMOP4A  <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4a_za32_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80108008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4a_za32_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4a_za32_zz_h1x2
            IEM_INSTR_IMPL_A64__smop4a_za32_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80008208: SMOP4A  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4a_za32_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80008208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4a_za32_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4a_za32_zz_h2x1
            IEM_INSTR_IMPL_A64__smop4a_za32_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80108208: SMOP4A  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4a_za32_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80108208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4a_za32_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4a_za32_zz_h2x2
            IEM_INSTR_IMPL_A64__smop4a_za32_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80008000: SMOP4A  <ZAda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4a_za_zz_b1x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
    {
        LogFlow(("%018x/%010x: smop4a_za_zz_b1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4a_za_zz_b1x1
        IEM_INSTR_IMPL_A64__smop4a_za_zz_b1x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80108000: SMOP4A  <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4a_za_zz_b1x2, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
    {
        LogFlow(("%018x/%010x: smop4a_za_zz_b1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4a_za_zz_b1x2
        IEM_INSTR_IMPL_A64__smop4a_za_zz_b1x2(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80008200: SMOP4A  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4a_za_zz_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80008200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4a_za_zz_b2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4a_za_zz_b2x1
            IEM_INSTR_IMPL_A64__smop4a_za_zz_b2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80108200: SMOP4A  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4a_za_zz_b2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80108200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4a_za_zz_b2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4a_za_zz_b2x2
            IEM_INSTR_IMPL_A64__smop4a_za_zz_b2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0c00008: SMOP4A  <ZAda>.D, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4a_za_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0c00008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smop4a_za_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4a_za_zz_h1x1
            IEM_INSTR_IMPL_A64__smop4a_za_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0d00008: SMOP4A  <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4a_za_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0d00008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smop4a_za_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4a_za_zz_h1x2
            IEM_INSTR_IMPL_A64__smop4a_za_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0c00208: SMOP4A  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4a_za_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0c00208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smop4a_za_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4a_za_zz_h2x1
            IEM_INSTR_IMPL_A64__smop4a_za_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0d00208: SMOP4A  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4a_za_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0d00208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smop4a_za_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4a_za_zz_h2x2
            IEM_INSTR_IMPL_A64__smop4a_za_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80008018: SMOP4S  <ZAda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4s_za32_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80008018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4s_za32_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4s_za32_zz_h1x1
            IEM_INSTR_IMPL_A64__smop4s_za32_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80108018: SMOP4S  <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4s_za32_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80108018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4s_za32_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4s_za32_zz_h1x2
            IEM_INSTR_IMPL_A64__smop4s_za32_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80008218: SMOP4S  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4s_za32_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80008218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4s_za32_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4s_za32_zz_h2x1
            IEM_INSTR_IMPL_A64__smop4s_za32_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80108218: SMOP4S  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4s_za32_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80108218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4s_za32_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4s_za32_zz_h2x2
            IEM_INSTR_IMPL_A64__smop4s_za32_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80008010: SMOP4S  <ZAda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4s_za_zz_b1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80008010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4s_za_zz_b1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4s_za_zz_b1x1
            IEM_INSTR_IMPL_A64__smop4s_za_zz_b1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80108010: SMOP4S  <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4s_za_zz_b1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80108010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4s_za_zz_b1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4s_za_zz_b1x2
            IEM_INSTR_IMPL_A64__smop4s_za_zz_b1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80008210: SMOP4S  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4s_za_zz_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80008210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4s_za_zz_b2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4s_za_zz_b2x1
            IEM_INSTR_IMPL_A64__smop4s_za_zz_b2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80108210: SMOP4S  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4s_za_zz_b2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80108210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: smop4s_za_zz_b2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4s_za_zz_b2x2
            IEM_INSTR_IMPL_A64__smop4s_za_zz_b2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0c00018: SMOP4S  <ZAda>.D, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4s_za_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0c00018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smop4s_za_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4s_za_zz_h1x1
            IEM_INSTR_IMPL_A64__smop4s_za_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0d00018: SMOP4S  <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4s_za_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0d00018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smop4s_za_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4s_za_zz_h1x2
            IEM_INSTR_IMPL_A64__smop4s_za_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0c00218: SMOP4S  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4s_za_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0c00218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smop4s_za_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4s_za_zz_h2x1
            IEM_INSTR_IMPL_A64__smop4s_za_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0d00218: SMOP4S  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_smop4s_za_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0d00218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smop4s_za_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__smop4s_za_zz_h2x2
            IEM_INSTR_IMPL_A64__smop4s_za_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/a0800008: SMOPA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i32_prod, mortlach_32bit_int_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_smopa_za32_pp_zz_16, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: smopa_za32_pp_zz_16 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__smopa_za32_pp_zz_16
        IEM_INSTR_IMPL_A64__smopa_za32_pp_zz_16(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/a0800000: SMOPA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod, mortlach_32bit_int_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_smopa_za_pp_zz_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smopa_za_pp_zz_32 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__smopa_za_pp_zz_32
        IEM_INSTR_IMPL_A64__smopa_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00018/a0c00000: SMOPA  <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod, mortlach_64bit_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_smopa_za_pp_zz_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00018)) == UINT32_C(0xa0c00000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smopa_za_pp_zz_64 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__smopa_za_pp_zz_64
            IEM_INSTR_IMPL_A64__smopa_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/a0800018: SMOPS  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i32_prod, mortlach_32bit_int_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_smops_za32_pp_zz_16, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: smops_za32_pp_zz_16 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__smops_za32_pp_zz_16
        IEM_INSTR_IMPL_A64__smops_za32_pp_zz_16(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/a0800010: SMOPS  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod, mortlach_32bit_int_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_smops_za_pp_zz_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smops_za_pp_zz_32 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__smops_za_pp_zz_32
        IEM_INSTR_IMPL_A64__smops_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00018/a0c00010: SMOPS  <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod, mortlach_64bit_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_smops_za_pp_zz_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00018)) == UINT32_C(0xa0c00010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: smops_za_pp_zz_64 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__smops_za_pp_zz_64
            IEM_INSTR_IMPL_A64__smops_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04120000: SMULH  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_2, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_smulh_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smulh_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__smulh_z_p_zz
        IEM_INSTR_IMPL_A64__smulh_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04206800: SMULH  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_mul_b, sve_int_unpred_arit_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_smulh_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04206800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: smulh_z_zz Zd=%#x Zn=%#x U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smulh_z_zz
            IEM_INSTR_IMPL_A64__smulh_z_zz(Zd, Zn, U, Zm, size);
#else
            RT_NOREF(Zd, Zn, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45007000: SMULLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_mul_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_smullb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smullb_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smullb_z_zz
        IEM_INSTR_IMPL_A64__smullb_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e0c000: SMULLB  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mul_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_smullb_z_zzi_d, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smullb_z_zzi_d Zd=%#x Zn=%#x T=%u i2l=%u U=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, i2l, U, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__smullb_z_zzi_d
        IEM_INSTR_IMPL_A64__smullb_z_zzi_d(Zd, Zn, T, i2l, U, Zm, i2h);
#else
        RT_NOREF(Zd, Zn, T, i2l, U, Zm, i2h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a0c000: SMULLB  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mul_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_smullb_z_zzi_s, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smullb_z_zzi_s Zd=%#x Zn=%#x T=%u i3l=%u U=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, i3l, U, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__smullb_z_zzi_s
        IEM_INSTR_IMPL_A64__smullb_z_zzi_s(Zd, Zn, T, i3l, U, Zm, i3h);
#else
        RT_NOREF(Zd, Zn, T, i3l, U, Zm, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45007400: SMULLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_mul_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_smullt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: smullt_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__smullt_z_zz
        IEM_INSTR_IMPL_A64__smullt_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e0c400: SMULLT  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mul_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_smullt_z_zzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e0c400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: smullt_z_zzi_d Zd=%#x Zn=%#x T=%u i2l=%u U=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, i2l, U, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__smullt_z_zzi_d
            IEM_INSTR_IMPL_A64__smullt_z_zzi_d(Zd, Zn, T, i2l, U, Zm, i2h);
#else
            RT_NOREF(Zd, Zn, T, i2l, U, Zm, i2h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a0c400: SMULLT  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mul_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_smullt_z_zzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a0c400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: smullt_z_zzi_s Zd=%#x Zn=%#x T=%u i3l=%u U=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, i3l, U, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__smullt_z_zzi_s
            IEM_INSTR_IMPL_A64__smullt_z_zzi_s(Zd, Zn, T, i3l, U, Zm, i3h);
#else
            RT_NOREF(Zd, Zn, T, i3l, U, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/052d8000: SPLICE  <Zd>.<T>, <Pv>, { <Zn1>.<T>, <Zn2>.<T> }
   Instruction Set: A64  Groups: sve_intx_perm_splice, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_splice_z_p_zz_con, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x052d8000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pv         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: splice_z_p_zz_con Zd=%#x Zn=%#x Pv=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pv, size));
#ifdef IEM_INSTR_IMPL_A64__splice_z_p_zz_con
            IEM_INSTR_IMPL_A64__splice_z_p_zz_con(Zd, Zn, Pv, size);
#else
            RT_NOREF(Zd, Zn, Pv, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/052c8000: SPLICE  <Zdn>.<T>, <Pv>, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_splice, sve_perm_pred, sve */
FNIEMOP_DEF_1(iemDecodeA64_splice_z_p_zz_des, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x052c8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pv         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: splice_z_p_zz_des Zdn=%#x Zm=%#x Pv=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pv, size));
#ifdef IEM_INSTR_IMPL_A64__splice_z_p_zz_des
            IEM_INSTR_IMPL_A64__splice_z_p_zz_des(Zdn, Zm, Pv, size);
#else
            RT_NOREF(Zdn, Zm, Pv, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4408a000: SQABS  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_unary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqabs_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4408a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqabs_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__sqabs_z_p_z_m
            IEM_INSTR_IMPL_A64__sqabs_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/440aa000: SQABS  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_unary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqabs_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x440aa000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: sqabs_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__sqabs_z_p_z_z
            IEM_INSTR_IMPL_A64__sqabs_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44188000: SQADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary_sat, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqadd_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44188000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqadd_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqadd_z_p_zz
            IEM_INSTR_IMPL_A64__sqadd_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fc000/2524c000: SQADD  <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: sve_int_arith_imm0, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqadd_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fc000)) == UINT32_C(0x2524c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const sh         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqadd_z_zi Zdn=%#x imm8=%#x sh=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm8, sh, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqadd_z_zi
            IEM_INSTR_IMPL_A64__sqadd_z_zi(Zdn, imm8, sh, U, size);
#else
            RT_NOREF(Zdn, imm8, sh, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04201000: SQADD  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_cons_arit_0, sve_int_unpred_arit, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqadd_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqadd_z_zz Zd=%#x Zn=%#x U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqadd_z_zz
        IEM_INSTR_IMPL_A64__sqadd_z_zz(Zd, Zn, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ff800/4501d800: SQCADD  <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
   Instruction Set: A64  Groups: sve_intx_cadd, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqcadd_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const rot        = (uOpcode >> 10) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqcadd_z_zz Zdn=%#x Zm=%#x rot=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, rot, size));
#ifdef IEM_INSTR_IMPL_A64__sqcadd_z_zz
        IEM_INSTR_IMPL_A64__sqcadd_z_zz(Zdn, Zm, rot, size);
#else
        RT_NOREF(Zdn, Zm, rot, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/c123e000: SQCVT  <Zd>.H, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_narrow_int_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqcvt_z_mz2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const U          = (uOpcode >>  5) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sqcvt_z_mz2 Zd=%#x U=%u Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn));
#ifdef IEM_INSTR_IMPL_A64__sqcvt_z_mz2
        IEM_INSTR_IMPL_A64__sqcvt_z_mz2(Zd, U, Zn);
#else
        RT_NOREF(Zd, U, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff7ffc60/c133e000: SQCVT  <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_narrow_int_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqcvt_z_mz4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const U          = (uOpcode >>  5) & 0x00000001;
    uint32_t const N          = (uOpcode >>  6) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const sz         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sqcvt_z_mz4 Zd=%#x U=%u N=%u Zn=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, N, Zn, sz));
#ifdef IEM_INSTR_IMPL_A64__sqcvt_z_mz4
        IEM_INSTR_IMPL_A64__sqcvt_z_mz4(Zd, U, N, Zn, sz);
#else
        RT_NOREF(Zd, U, N, Zn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/45314000: SQCVTN  <Zd>.H, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: sve_intx_multi_extract_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqcvtn_z_mz2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: sqcvtn_z_mz2 Zd=%#x Zn=%#x U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U));
#ifdef IEM_INSTR_IMPL_A64__sqcvtn_z_mz2
        IEM_INSTR_IMPL_A64__sqcvtn_z_mz2(Zd, Zn, U);
#else
        RT_NOREF(Zd, Zn, U, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff7ffc60/c133e040: SQCVTN  <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_narrow_int_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqcvtn_z_mz4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const U          = (uOpcode >>  5) & 0x00000001;
    uint32_t const N          = (uOpcode >>  6) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const sz         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sqcvtn_z_mz4 Zd=%#x U=%u N=%u Zn=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, N, Zn, sz));
#ifdef IEM_INSTR_IMPL_A64__sqcvtn_z_mz4
        IEM_INSTR_IMPL_A64__sqcvtn_z_mz4(Zd, U, N, Zn, sz);
#else
        RT_NOREF(Zd, U, N, Zn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/c163e000: SQCVTU  <Zd>.H, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_narrow_int_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqcvtu_z_mz2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0xc163e000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sqcvtu_z_mz2 Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__sqcvtu_z_mz2
            IEM_INSTR_IMPL_A64__sqcvtu_z_mz2(Zd, Zn);
#else
            RT_NOREF(Zd, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff7ffc60/c173e000: SQCVTU  <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_narrow_int_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqcvtu_z_mz4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff7ffc60)) == UINT32_C(0xc173e000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const N          = (uOpcode >>  6) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sqcvtu_z_mz4 Zd=%#x N=%u Zn=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, N, Zn, sz));
#ifdef IEM_INSTR_IMPL_A64__sqcvtu_z_mz4
            IEM_INSTR_IMPL_A64__sqcvtu_z_mz4(Zd, N, Zn, sz);
#else
            RT_NOREF(Zd, N, Zn, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/45315000: SQCVTUN  <Zd>.H, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: sve_intx_multi_extract_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqcvtun_z_mz2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: sqcvtun_z_mz2 Zd=%#x Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__sqcvtun_z_mz2
        IEM_INSTR_IMPL_A64__sqcvtun_z_mz2(Zd, Zn);
#else
        RT_NOREF(Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff7ffc60/c173e040: SQCVTUN  <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_narrow_int_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqcvtun_z_mz4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff7ffc60)) == UINT32_C(0xc173e040))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const N          = (uOpcode >>  6) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 23) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sqcvtun_z_mz4 Zd=%#x N=%u Zn=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, N, Zn, sz));
#ifdef IEM_INSTR_IMPL_A64__sqcvtun_z_mz4
            IEM_INSTR_IMPL_A64__sqcvtun_z_mz4(Zd, N, Zn, sz);
#else
            RT_NOREF(Zd, N, Zn, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0420f800: SQDECB  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdecb_r_rs_sx, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdecb_r_rs_sx Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqdecb_r_rs_sx
        IEM_INSTR_IMPL_A64__sqdecb_r_rs_sx(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0430f800: SQDECB  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdecb_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdecb_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqdecb_r_rs_x
        IEM_INSTR_IMPL_A64__sqdecb_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04e0f800: SQDECD  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdecd_r_rs_sx, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdecd_r_rs_sx Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqdecd_r_rs_sx
        IEM_INSTR_IMPL_A64__sqdecd_r_rs_sx(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04f0f800: SQDECD  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdecd_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdecd_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqdecd_r_rs_x
        IEM_INSTR_IMPL_A64__sqdecd_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04e0c800: SQDECD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv0, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdecd_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdecd_z_zs Zdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqdecd_z_zs
        IEM_INSTR_IMPL_A64__sqdecd_z_zs(Zdn, pattern, U, imm4, size);
#else
        RT_NOREF(Zdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0460f800: SQDECH  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdech_r_rs_sx, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdech_r_rs_sx Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqdech_r_rs_sx
        IEM_INSTR_IMPL_A64__sqdech_r_rs_sx(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0470f800: SQDECH  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdech_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdech_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqdech_r_rs_x
        IEM_INSTR_IMPL_A64__sqdech_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0460c800: SQDECH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv0, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdech_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdech_z_zs Zdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqdech_z_zs
        IEM_INSTR_IMPL_A64__sqdech_z_zs(Zdn, pattern, U, imm4, size);
#else
        RT_NOREF(Zdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/252a8800: SQDECP  <Xdn>, <Pm>.<T>, <Wdn>
   Instruction Set: A64  Groups: sve_int_count_r_sat, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdecp_r_p_r_sx, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x252a8800))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdecp_r_p_r_sx Rdn=%#x Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdecp_r_p_r_sx
            IEM_INSTR_IMPL_A64__sqdecp_r_p_r_sx(Rdn, Pm, size);
#else
            RT_NOREF(Rdn, Pm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/252a8c00: SQDECP  <Xdn>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_r_sat, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdecp_r_p_r_x, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x252a8c00))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdecp_r_p_r_x Rdn=%#x Pm=%#x U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, Pm, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqdecp_r_p_r_x
            IEM_INSTR_IMPL_A64__sqdecp_r_p_r_x(Rdn, Pm, U, size);
#else
            RT_NOREF(Rdn, Pm, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/252a8000: SQDECP  <Zdn>.<T>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_v_sat, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdecp_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x252a8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdecp_z_p_z Zdn=%#x Pm=%#x U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Pm, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqdecp_z_p_z
            IEM_INSTR_IMPL_A64__sqdecp_z_p_z(Zdn, Pm, U, size);
#else
            RT_NOREF(Zdn, Pm, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04a0f800: SQDECW  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdecw_r_rs_sx, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdecw_r_rs_sx Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqdecw_r_rs_sx
        IEM_INSTR_IMPL_A64__sqdecw_r_rs_sx(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04b0f800: SQDECW  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdecw_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdecw_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqdecw_r_rs_x
        IEM_INSTR_IMPL_A64__sqdecw_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04a0c800: SQDECW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv0, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdecw_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdecw_z_zs Zdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqdecw_z_zs
        IEM_INSTR_IMPL_A64__sqdecw_z_zs(Zdn, pattern, U, imm4, size);
#else
        RT_NOREF(Zdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44006000: SQDMLALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_qdmlal_long, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlalb_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44006000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmlalb_z_zzz Zda=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmlalb_z_zzz
            IEM_INSTR_IMPL_A64__sqdmlalb_z_zzz(Zda, Zn, T, Zm, size);
#else
            RT_NOREF(Zda, Zn, T, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e02000: SQDMLALB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlalb_z_zzzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e02000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmlalb_z_zzzi_d Zda=%#x Zn=%#x T=%u i2l=%u S=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i2l, S, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__sqdmlalb_z_zzzi_d
            IEM_INSTR_IMPL_A64__sqdmlalb_z_zzzi_d(Zda, Zn, T, i2l, S, Zm, i2h);
#else
            RT_NOREF(Zda, Zn, T, i2l, S, Zm, i2h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a02000: SQDMLALB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlalb_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdmlalb_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u S=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, S, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__sqdmlalb_z_zzzi_s
        IEM_INSTR_IMPL_A64__sqdmlalb_z_zzzi_s(Zda, Zn, T, i3l, S, Zm, i3h);
#else
        RT_NOREF(Zda, Zn, T, i3l, S, Zm, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44000800: SQDMLALBT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_qdmlalbt, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlalbt_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44000800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmlalbt_z_zzz Zda=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmlalbt_z_zzz
            IEM_INSTR_IMPL_A64__sqdmlalbt_z_zzz(Zda, Zn, Zm, size);
#else
            RT_NOREF(Zda, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44006400: SQDMLALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_qdmlal_long, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlalt_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdmlalt_z_zzz Zda=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmlalt_z_zzz
        IEM_INSTR_IMPL_A64__sqdmlalt_z_zzz(Zda, Zn, T, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e02400: SQDMLALT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlalt_z_zzzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e02400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmlalt_z_zzzi_d Zda=%#x Zn=%#x T=%u i2l=%u S=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i2l, S, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__sqdmlalt_z_zzzi_d
            IEM_INSTR_IMPL_A64__sqdmlalt_z_zzzi_d(Zda, Zn, T, i2l, S, Zm, i2h);
#else
            RT_NOREF(Zda, Zn, T, i2l, S, Zm, i2h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a02400: SQDMLALT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlalt_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a02400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmlalt_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u S=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, S, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__sqdmlalt_z_zzzi_s
            IEM_INSTR_IMPL_A64__sqdmlalt_z_zzzi_s(Zda, Zn, T, i3l, S, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, T, i3l, S, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44006800: SQDMLSLB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_qdmlal_long, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlslb_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdmlslb_z_zzz Zda=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmlslb_z_zzz
        IEM_INSTR_IMPL_A64__sqdmlslb_z_zzz(Zda, Zn, T, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e03000: SQDMLSLB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlslb_z_zzzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e03000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmlslb_z_zzzi_d Zda=%#x Zn=%#x T=%u i2l=%u S=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i2l, S, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__sqdmlslb_z_zzzi_d
            IEM_INSTR_IMPL_A64__sqdmlslb_z_zzzi_d(Zda, Zn, T, i2l, S, Zm, i2h);
#else
            RT_NOREF(Zda, Zn, T, i2l, S, Zm, i2h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a03000: SQDMLSLB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlslb_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a03000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const S          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmlslb_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u S=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, S, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__sqdmlslb_z_zzzi_s
            IEM_INSTR_IMPL_A64__sqdmlslb_z_zzzi_s(Zda, Zn, T, i3l, S, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, T, i3l, S, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44000c00: SQDMLSLBT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_qdmlalbt, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlslbt_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44000c00))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmlslbt_z_zzz Zda=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmlslbt_z_zzz
            IEM_INSTR_IMPL_A64__sqdmlslbt_z_zzz(Zda, Zn, Zm, size);
#else
            RT_NOREF(Zda, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44006c00: SQDMLSLT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_qdmlal_long, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlslt_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdmlslt_z_zzz Zda=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmlslt_z_zzz
        IEM_INSTR_IMPL_A64__sqdmlslt_z_zzz(Zda, Zn, T, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e03400: SQDMLSLT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlslt_z_zzzi_d, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdmlslt_z_zzzi_d Zda=%#x Zn=%#x T=%u i2l=%u S=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i2l, S, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__sqdmlslt_z_zzzi_d
        IEM_INSTR_IMPL_A64__sqdmlslt_z_zzzi_d(Zda, Zn, T, i2l, S, Zm, i2h);
#else
        RT_NOREF(Zda, Zn, T, i2l, S, Zm, i2h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a03400: SQDMLSLT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmlslt_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const S          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdmlslt_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u S=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, S, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__sqdmlslt_z_zzzi_s
        IEM_INSTR_IMPL_A64__sqdmlslt_z_zzzi_s(Zda, Zn, T, i3l, S, Zm, i3h);
#else
        RT_NOREF(Zda, Zn, T, i3l, S, Zm, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a400: SQDMULH  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_sqdmulh_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqdmulh_mz_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a400))
    {
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sqdmulh_mz_zzv_2x1 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmulh_mz_zzv_2x1
            IEM_INSTR_IMPL_A64__sqdmulh_mz_zzv_2x1(Zdn, Zm, size);
#else
            RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120ac00: SQDMULH  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_sqdmulh_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqdmulh_mz_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120ac00))
    {
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sqdmulh_mz_zzv_4x1 Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmulh_mz_zzv_4x1
            IEM_INSTR_IMPL_A64__sqdmulh_mz_zzv_4x1(Zdn, Zm, size);
#else
            RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b400: SQDMULH  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_sqdmulh_mm, mortlach_multi_sve_2c1, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqdmulh_mz_zzw_2x2, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sqdmulh_mz_zzw_2x2 Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmulh_mz_zzw_2x2
        IEM_INSTR_IMPL_A64__sqdmulh_mz_zzw_2x2(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120bc00: SQDMULH  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_sqdmulh_mm, mortlach_multi_sve_2d1, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqdmulh_mz_zzw_4x4, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sqdmulh_mz_zzw_4x4 Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmulh_mz_zzw_4x4
        IEM_INSTR_IMPL_A64__sqdmulh_mz_zzw_4x4(Zdn, Zm, size);
#else
        RT_NOREF(Zdn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04207000: SQDMULH  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_sqdmulh, sve_int_unpred_arit_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmulh_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdmulh_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmulh_z_zz
        IEM_INSTR_IMPL_A64__sqdmulh_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44e0f000: SQDMULH  <Zd>.D, <Zn>.D, <Zm>.D[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmulh_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmulh_z_zzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44e0f000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmulh_z_zzi_d Zd=%#x Zn=%#x Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__sqdmulh_z_zzi_d
            IEM_INSTR_IMPL_A64__sqdmulh_z_zzi_d(Zd, Zn, Zm, i1);
#else
            RT_NOREF(Zd, Zn, Zm, i1, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/4420f000: SQDMULH  <Zd>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmulh_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmulh_z_zzi_h, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
    uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdmulh_z_zzi_h Zd=%#x Zn=%#x Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__sqdmulh_z_zzi_h
        IEM_INSTR_IMPL_A64__sqdmulh_z_zzi_h(Zd, Zn, Zm, i3l, i3h);
#else
        RT_NOREF(Zd, Zn, Zm, i3l, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44a0f000: SQDMULH  <Zd>.S, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmulh_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmulh_z_zzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44a0f000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmulh_z_zzi_s Zd=%#x Zn=%#x Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__sqdmulh_z_zzi_s
            IEM_INSTR_IMPL_A64__sqdmulh_z_zzi_s(Zd, Zn, Zm, i2);
#else
            RT_NOREF(Zd, Zn, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45006000: SQDMULLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_mul_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmullb_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45006000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmullb_z_zz Zd=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmullb_z_zz
            IEM_INSTR_IMPL_A64__sqdmullb_z_zz(Zd, Zn, T, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e0e000: SQDMULLB  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmul_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmullb_z_zzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e0e000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmullb_z_zzi_d Zd=%#x Zn=%#x T=%u i2l=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, i2l, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__sqdmullb_z_zzi_d
            IEM_INSTR_IMPL_A64__sqdmullb_z_zzi_d(Zd, Zn, T, i2l, Zm, i2h);
#else
            RT_NOREF(Zd, Zn, T, i2l, Zm, i2h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a0e000: SQDMULLB  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmul_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmullb_z_zzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a0e000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmullb_z_zzi_s Zd=%#x Zn=%#x T=%u i3l=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, i3l, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__sqdmullb_z_zzi_s
            IEM_INSTR_IMPL_A64__sqdmullb_z_zzi_s(Zd, Zn, T, i3l, Zm, i3h);
#else
            RT_NOREF(Zd, Zn, T, i3l, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45006400: SQDMULLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_mul_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmullt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqdmullt_z_zz Zd=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqdmullt_z_zz
        IEM_INSTR_IMPL_A64__sqdmullt_z_zz(Zd, Zn, T, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e0e400: SQDMULLT  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmul_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmullt_z_zzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e0e400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmullt_z_zzi_d Zd=%#x Zn=%#x T=%u i2l=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, i2l, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__sqdmullt_z_zzi_d
            IEM_INSTR_IMPL_A64__sqdmullt_z_zzi_d(Zd, Zn, T, i2l, Zm, i2h);
#else
            RT_NOREF(Zd, Zn, T, i2l, Zm, i2h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a0e400: SQDMULLT  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmul_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqdmullt_z_zzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a0e400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqdmullt_z_zzi_s Zd=%#x Zn=%#x T=%u i3l=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, i3l, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__sqdmullt_z_zzi_s
            IEM_INSTR_IMPL_A64__sqdmullt_z_zzi_s(Zd, Zn, T, i3l, Zm, i3h);
#else
            RT_NOREF(Zd, Zn, T, i3l, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0420f000: SQINCB  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqincb_r_rs_sx, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqincb_r_rs_sx Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqincb_r_rs_sx
        IEM_INSTR_IMPL_A64__sqincb_r_rs_sx(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0430f000: SQINCB  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqincb_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqincb_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqincb_r_rs_x
        IEM_INSTR_IMPL_A64__sqincb_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04e0f000: SQINCD  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqincd_r_rs_sx, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqincd_r_rs_sx Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqincd_r_rs_sx
        IEM_INSTR_IMPL_A64__sqincd_r_rs_sx(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04f0f000: SQINCD  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqincd_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqincd_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqincd_r_rs_x
        IEM_INSTR_IMPL_A64__sqincd_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04e0c000: SQINCD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv0, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqincd_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqincd_z_zs Zdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqincd_z_zs
        IEM_INSTR_IMPL_A64__sqincd_z_zs(Zdn, pattern, U, imm4, size);
#else
        RT_NOREF(Zdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0460f000: SQINCH  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqinch_r_rs_sx, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqinch_r_rs_sx Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqinch_r_rs_sx
        IEM_INSTR_IMPL_A64__sqinch_r_rs_sx(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0470f000: SQINCH  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqinch_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqinch_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqinch_r_rs_x
        IEM_INSTR_IMPL_A64__sqinch_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0460c000: SQINCH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv0, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqinch_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqinch_z_zs Zdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqinch_z_zs
        IEM_INSTR_IMPL_A64__sqinch_z_zs(Zdn, pattern, U, imm4, size);
#else
        RT_NOREF(Zdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/25288800: SQINCP  <Xdn>, <Pm>.<T>, <Wdn>
   Instruction Set: A64  Groups: sve_int_count_r_sat, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqincp_r_p_r_sx, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x25288800))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqincp_r_p_r_sx Rdn=%#x Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__sqincp_r_p_r_sx
            IEM_INSTR_IMPL_A64__sqincp_r_p_r_sx(Rdn, Pm, size);
#else
            RT_NOREF(Rdn, Pm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/25288c00: SQINCP  <Xdn>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_r_sat, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqincp_r_p_r_x, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x25288c00))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqincp_r_p_r_x Rdn=%#x Pm=%#x U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, Pm, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqincp_r_p_r_x
            IEM_INSTR_IMPL_A64__sqincp_r_p_r_x(Rdn, Pm, U, size);
#else
            RT_NOREF(Rdn, Pm, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/25288000: SQINCP  <Zdn>.<T>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_v_sat, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqincp_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x25288000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqincp_z_p_z Zdn=%#x Pm=%#x U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Pm, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqincp_z_p_z
            IEM_INSTR_IMPL_A64__sqincp_z_p_z(Zdn, Pm, U, size);
#else
            RT_NOREF(Zdn, Pm, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04a0f000: SQINCW  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqincw_r_rs_sx, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqincw_r_rs_sx Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqincw_r_rs_sx
        IEM_INSTR_IMPL_A64__sqincw_r_rs_sx(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04b0f000: SQINCW  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqincw_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqincw_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqincw_r_rs_x
        IEM_INSTR_IMPL_A64__sqincw_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04a0c000: SQINCW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv0, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqincw_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqincw_z_zs Zdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__sqincw_z_zs
        IEM_INSTR_IMPL_A64__sqincw_z_zs(Zdn, pattern, U, imm4, size);
#else
        RT_NOREF(Zdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4409a000: SQNEG  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_unary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqneg_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4409a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqneg_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__sqneg_z_p_z_m
            IEM_INSTR_IMPL_A64__sqneg_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/440ba000: SQNEG  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_unary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqneg_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x440ba000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: sqneg_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__sqneg_z_p_z_z
            IEM_INSTR_IMPL_A64__sqneg_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20f000/44003000: SQRDCMLAH  <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
   Instruction Set: A64  Groups: sve_intx_cmla, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdcmlah_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20f000)) == UINT32_C(0x44003000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rot        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrdcmlah_z_zzz Zda=%#x Zn=%#x rot=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, rot, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqrdcmlah_z_zzz
            IEM_INSTR_IMPL_A64__sqrdcmlah_z_zzz(Zda, Zn, rot, Zm, size);
#else
            RT_NOREF(Zda, Zn, rot, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/44a07000: SQRDCMLAH  <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
   Instruction Set: A64  Groups: sve_intx_qrdcmla_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdcmlah_z_zzzi_h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x44a07000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rot        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrdcmlah_z_zzzi_h Zda=%#x Zn=%#x rot=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, rot, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__sqrdcmlah_z_zzzi_h
            IEM_INSTR_IMPL_A64__sqrdcmlah_z_zzzi_h(Zda, Zn, rot, Zm, i2);
#else
            RT_NOREF(Zda, Zn, rot, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f000/44e07000: SQRDCMLAH  <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
   Instruction Set: A64  Groups: sve_intx_qrdcmla_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdcmlah_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x44e07000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const rot        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrdcmlah_z_zzzi_s Zda=%#x Zn=%#x rot=%u Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, rot, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__sqrdcmlah_z_zzzi_s
            IEM_INSTR_IMPL_A64__sqrdcmlah_z_zzzi_s(Zda, Zn, rot, Zm, i1);
#else
            RT_NOREF(Zda, Zn, rot, Zm, i1, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44007000: SQRDMLAH  <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_qrdmlah, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdmlah_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqrdmlah_z_zzz Zda=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqrdmlah_z_zzz
        IEM_INSTR_IMPL_A64__sqrdmlah_z_zzz(Zda, Zn, Zm, size);
#else
        RT_NOREF(Zda, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44e01000: SQRDMLAH  <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
   Instruction Set: A64  Groups: sve_intx_qrdmlah_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdmlah_z_zzzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44e01000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrdmlah_z_zzzi_d Zda=%#x Zn=%#x S=%u Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, S, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__sqrdmlah_z_zzzi_d
            IEM_INSTR_IMPL_A64__sqrdmlah_z_zzzi_d(Zda, Zn, S, Zm, i1);
#else
            RT_NOREF(Zda, Zn, S, Zm, i1, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/44201000: SQRDMLAH  <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_qrdmlah_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdmlah_z_zzzi_h, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x44201000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrdmlah_z_zzzi_h Zda=%#x Zn=%#x S=%u Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, S, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__sqrdmlah_z_zzzi_h
            IEM_INSTR_IMPL_A64__sqrdmlah_z_zzzi_h(Zda, Zn, S, Zm, i3l, i3h);
#else
            RT_NOREF(Zda, Zn, S, Zm, i3l, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44a01000: SQRDMLAH  <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_qrdmlah_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdmlah_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44a01000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrdmlah_z_zzzi_s Zda=%#x Zn=%#x S=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, S, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__sqrdmlah_z_zzzi_s
            IEM_INSTR_IMPL_A64__sqrdmlah_z_zzzi_s(Zda, Zn, S, Zm, i2);
#else
            RT_NOREF(Zda, Zn, S, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44007400: SQRDMLSH  <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_qrdmlah, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdmlsh_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqrdmlsh_z_zzz Zda=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzz
        IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzz(Zda, Zn, Zm, size);
#else
        RT_NOREF(Zda, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44e01400: SQRDMLSH  <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
   Instruction Set: A64  Groups: sve_intx_qrdmlah_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdmlsh_z_zzzi_d, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqrdmlsh_z_zzzi_d Zda=%#x Zn=%#x S=%u Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, S, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzzi_d
        IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzzi_d(Zda, Zn, S, Zm, i1);
#else
        RT_NOREF(Zda, Zn, S, Zm, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/44201400: SQRDMLSH  <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_qrdmlah_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdmlsh_z_zzzi_h, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const S          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
    uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqrdmlsh_z_zzzi_h Zda=%#x Zn=%#x S=%u Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, S, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzzi_h
        IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzzi_h(Zda, Zn, S, Zm, i3l, i3h);
#else
        RT_NOREF(Zda, Zn, S, Zm, i3l, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44a01400: SQRDMLSH  <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_qrdmlah_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdmlsh_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44a01400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const S          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrdmlsh_z_zzzi_s Zda=%#x Zn=%#x S=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, S, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzzi_s
            IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzzi_s(Zda, Zn, S, Zm, i2);
#else
            RT_NOREF(Zda, Zn, S, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04207400: SQRDMULH  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_sqdmulh, sve_int_unpred_arit_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdmulh_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqrdmulh_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqrdmulh_z_zz
        IEM_INSTR_IMPL_A64__sqrdmulh_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44e0f400: SQRDMULH  <Zd>.D, <Zn>.D, <Zm>.D[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmulh_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdmulh_z_zzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44e0f400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrdmulh_z_zzi_d Zd=%#x Zn=%#x Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__sqrdmulh_z_zzi_d
            IEM_INSTR_IMPL_A64__sqrdmulh_z_zzi_d(Zd, Zn, Zm, i1);
#else
            RT_NOREF(Zd, Zn, Zm, i1, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/4420f400: SQRDMULH  <Zd>.H, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmulh_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdmulh_z_zzi_h, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3l        = (uOpcode >> 19) & 0x00000003;
    uint32_t const i3h        = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqrdmulh_z_zzi_h Zd=%#x Zn=%#x Zm=%u i3l=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i3l, i3h));
#ifdef IEM_INSTR_IMPL_A64__sqrdmulh_z_zzi_h
        IEM_INSTR_IMPL_A64__sqrdmulh_z_zzi_h(Zd, Zn, Zm, i3l, i3h);
#else
        RT_NOREF(Zd, Zn, Zm, i3l, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44a0f400: SQRDMULH  <Zd>.S, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_qdmulh_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrdmulh_z_zzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44a0f400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrdmulh_z_zzi_s Zd=%#x Zn=%#x Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__sqrdmulh_z_zzi_s
            IEM_INSTR_IMPL_A64__sqrdmulh_z_zzi_s(Zd, Zn, Zm, i2);
#else
            RT_NOREF(Zd, Zn, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/440a8000: SQRSHL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_bin_pred_shift_sat_round, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrshl_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x440a8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrshl_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqrshl_z_p_zz
            IEM_INSTR_IMPL_A64__sqrshl_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/440e8000: SQRSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_bin_pred_shift_sat_round, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrshlr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x440e8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrshlr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqrshlr_z_p_zz
            IEM_INSTR_IMPL_A64__sqrshlr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc20/c1e0d400: SQRSHR  <Zd>.H, { <Zn1>.S-<Zn2>.S }, #<const>
   Instruction Set: A64  Groups: mortlach_multi2_qrshr, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqrshr_z_mz2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const U          = (uOpcode >>  5) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sqrshr_z_mz2 Zd=%#x U=%u Zn=%#x imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn, imm4));
#ifdef IEM_INSTR_IMPL_A64__sqrshr_z_mz2
        IEM_INSTR_IMPL_A64__sqrshr_z_mz2(Zd, U, Zn, imm4);
#else
        RT_NOREF(Zd, U, Zn, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc60/c120d800: SQRSHR  <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const>
   Instruction Set: A64  Groups: mortlach_multi4_qrshr, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqrshr_z_mz4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc60)) == UINT32_C(0xc120d800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const U          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const N          = (uOpcode >> 10) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        uint32_t const tsize      = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sqrshr_z_mz4 Zd=%#x U=%u Zn=%u N=%u imm5=%#x tsize=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn, N, imm5, tsize));
#ifdef IEM_INSTR_IMPL_A64__sqrshr_z_mz4
            IEM_INSTR_IMPL_A64__sqrshr_z_mz4(Zd, U, Zn, N, imm5, tsize);
#else
            RT_NOREF(Zd, U, Zn, N, imm5, tsize, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc20/45b02800: SQRSHRN  <Zd>.H, { <Zn1>.S-<Zn2>.S }, #<const>
   Instruction Set: A64  Groups: sve_intx_multi_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrshrn_z_mz2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc20)) == UINT32_C(0x45b02800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: sqrshrn_z_mz2 Zd=%#x Zn=%#x U=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U, imm4));
#ifdef IEM_INSTR_IMPL_A64__sqrshrn_z_mz2
            IEM_INSTR_IMPL_A64__sqrshrn_z_mz2(Zd, Zn, U, imm4);
#else
            RT_NOREF(Zd, Zn, U, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc60/c120dc00: SQRSHRN  <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const>
   Instruction Set: A64  Groups: mortlach_multi4_qrshr, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqrshrn_z_mz4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const U          = (uOpcode >>  5) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const N          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    uint32_t const tsize      = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sqrshrn_z_mz4 Zd=%#x U=%u Zn=%u N=%u imm5=%#x tsize=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn, N, imm5, tsize));
#ifdef IEM_INSTR_IMPL_A64__sqrshrn_z_mz4
        IEM_INSTR_IMPL_A64__sqrshrn_z_mz4(Zd, U, Zn, N, imm5, tsize);
#else
        RT_NOREF(Zd, U, Zn, N, imm5, tsize, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45202800: SQRSHRNB  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrshrnb_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqrshrnb_z_zi Zd=%#x Zn=%#x T=%u U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqrshrnb_z_zi
        IEM_INSTR_IMPL_A64__sqrshrnb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45202c00: SQRSHRNT  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrshrnt_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqrshrnt_z_zi Zd=%#x Zn=%#x T=%u U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqrshrnt_z_zi
        IEM_INSTR_IMPL_A64__sqrshrnt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc20/c1f0d400: SQRSHRU  <Zd>.H, { <Zn1>.S-<Zn2>.S }, #<const>
   Instruction Set: A64  Groups: mortlach_multi2_qrshr, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqrshru_z_mz2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sqrshru_z_mz2 Zd=%#x Zn=%#x imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, imm4));
#ifdef IEM_INSTR_IMPL_A64__sqrshru_z_mz2
        IEM_INSTR_IMPL_A64__sqrshru_z_mz2(Zd, Zn, imm4);
#else
        RT_NOREF(Zd, Zn, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc60/c120d840: SQRSHRU  <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const>
   Instruction Set: A64  Groups: mortlach_multi4_qrshr, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqrshru_z_mz4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc60)) == UINT32_C(0xc120d840))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const N          = (uOpcode >> 10) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        uint32_t const tsize      = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sqrshru_z_mz4 Zd=%#x Zn=%u N=%u imm5=%#x tsize=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, N, imm5, tsize));
#ifdef IEM_INSTR_IMPL_A64__sqrshru_z_mz4
            IEM_INSTR_IMPL_A64__sqrshru_z_mz4(Zd, Zn, N, imm5, tsize);
#else
            RT_NOREF(Zd, Zn, N, imm5, tsize, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc20/45b00800: SQRSHRUN  <Zd>.H, { <Zn1>.S-<Zn2>.S }, #<const>
   Instruction Set: A64  Groups: sve_intx_multi_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrshrun_z_mz2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc20)) == UINT32_C(0x45b00800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: sqrshrun_z_mz2 Zd=%#x Zn=%#x imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, imm4));
#ifdef IEM_INSTR_IMPL_A64__sqrshrun_z_mz2
            IEM_INSTR_IMPL_A64__sqrshrun_z_mz2(Zd, Zn, imm4);
#else
            RT_NOREF(Zd, Zn, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc60/c120dc40: SQRSHRUN  <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const>
   Instruction Set: A64  Groups: mortlach_multi4_qrshr, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sqrshrun_z_mz4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const N          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    uint32_t const tsize      = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sqrshrun_z_mz4 Zd=%#x Zn=%u N=%u imm5=%#x tsize=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, N, imm5, tsize));
#ifdef IEM_INSTR_IMPL_A64__sqrshrun_z_mz4
        IEM_INSTR_IMPL_A64__sqrshrun_z_mz4(Zd, Zn, N, imm5, tsize);
#else
        RT_NOREF(Zd, Zn, N, imm5, tsize, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45200800: SQRSHRUNB  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrshrunb_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45200800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrshrunb_z_zi Zd=%#x Zn=%#x T=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqrshrunb_z_zi
            IEM_INSTR_IMPL_A64__sqrshrunb_z_zi(Zd, Zn, T, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45200c00: SQRSHRUNT  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqrshrunt_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45200c00))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqrshrunt_z_zi Zd=%#x Zn=%#x T=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqrshrunt_z_zi
            IEM_INSTR_IMPL_A64__sqrshrunt_z_zi(Zd, Zn, T, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04068000: SQSHL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_0, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqshl_z_p_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04068000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >>  5) & 0x00000007;
        uint32_t const tszl       = (uOpcode >>  8) & 0x00000003;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqshl_z_p_zi Zdn=%#x imm3=%u tszl=%u Pg=%u U=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm3, tszl, Pg, U, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqshl_z_p_zi
            IEM_INSTR_IMPL_A64__sqshl_z_p_zi(Zdn, imm3, tszl, Pg, U, tszh);
#else
            RT_NOREF(Zdn, imm3, tszl, Pg, U, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44088000: SQSHL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_bin_pred_shift_sat_round, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqshl_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44088000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqshl_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqshl_z_p_zz
            IEM_INSTR_IMPL_A64__sqshl_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/440c8000: SQSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_bin_pred_shift_sat_round, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqshlr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x440c8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqshlr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqshlr_z_p_zz
            IEM_INSTR_IMPL_A64__sqshlr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040f8000: SQSHLU  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_0, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqshlu_z_p_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040f8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >>  5) & 0x00000007;
        uint32_t const tszl       = (uOpcode >>  8) & 0x00000003;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqshlu_z_p_zi Zdn=%#x imm3=%u tszl=%u Pg=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm3, tszl, Pg, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqshlu_z_p_zi
            IEM_INSTR_IMPL_A64__sqshlu_z_p_zi(Zdn, imm3, tszl, Pg, tszh);
#else
            RT_NOREF(Zdn, imm3, tszl, Pg, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45202000: SQSHRNB  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqshrnb_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqshrnb_z_zi Zd=%#x Zn=%#x T=%u U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqshrnb_z_zi
        IEM_INSTR_IMPL_A64__sqshrnb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45202400: SQSHRNT  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqshrnt_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45202400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqshrnt_z_zi Zd=%#x Zn=%#x T=%u U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqshrnt_z_zi
            IEM_INSTR_IMPL_A64__sqshrnt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, U, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45200000: SQSHRUNB  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqshrunb_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45200000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqshrunb_z_zi Zd=%#x Zn=%#x T=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqshrunb_z_zi
            IEM_INSTR_IMPL_A64__sqshrunb_z_zi(Zd, Zn, T, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45200400: SQSHRUNT  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqshrunt_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45200400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqshrunt_z_zi Zd=%#x Zn=%#x T=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqshrunt_z_zi
            IEM_INSTR_IMPL_A64__sqshrunt_z_zi(Zd, Zn, T, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/441a8000: SQSUB  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary_sat, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqsub_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x441a8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqsub_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqsub_z_p_zz
            IEM_INSTR_IMPL_A64__sqsub_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fc000/2526c000: SQSUB  <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: sve_int_arith_imm0, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqsub_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fc000)) == UINT32_C(0x2526c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const sh         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqsub_z_zi Zdn=%#x imm8=%#x sh=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm8, sh, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqsub_z_zi
            IEM_INSTR_IMPL_A64__sqsub_z_zi(Zdn, imm8, sh, U, size);
#else
            RT_NOREF(Zdn, imm8, sh, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04201800: SQSUB  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_cons_arit_0, sve_int_unpred_arit, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqsub_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqsub_z_zz Zd=%#x Zn=%#x U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sqsub_z_zz
        IEM_INSTR_IMPL_A64__sqsub_z_zz(Zd, Zn, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/441e8000: SQSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary_sat, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqsubr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x441e8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqsubr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sqsubr_z_p_zz
            IEM_INSTR_IMPL_A64__sqsubr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa7fc00/45204000: SQXTNB  <Zd>.<T>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_intx_extract_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqxtnb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqxtnb_z_zz Zd=%#x Zn=%#x T=%u U=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqxtnb_z_zz
        IEM_INSTR_IMPL_A64__sqxtnb_z_zz(Zd, Zn, T, U, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, U, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa7fc00/45204400: SQXTNT  <Zd>.<T>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_intx_extract_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqxtnt_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa7fc00)) == UINT32_C(0x45204400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqxtnt_z_zz Zd=%#x Zn=%#x T=%u U=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqxtnt_z_zz
            IEM_INSTR_IMPL_A64__sqxtnt_z_zz(Zd, Zn, T, U, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, U, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa7fc00/45205000: SQXTUNB  <Zd>.<T>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_intx_extract_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqxtunb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sqxtunb_z_zz Zd=%#x Zn=%#x T=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqxtunb_z_zz
        IEM_INSTR_IMPL_A64__sqxtunb_z_zz(Zd, Zn, T, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa7fc00/45205400: SQXTUNT  <Zd>.<T>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_intx_extract_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_sqxtunt_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa7fc00)) == UINT32_C(0x45205400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sqxtunt_z_zz Zd=%#x Zn=%#x T=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sqxtunt_z_zz
            IEM_INSTR_IMPL_A64__sqxtunt_z_zz(Zd, Zn, T, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44148000: SRHADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_srhadd_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44148000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: srhadd_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__srhadd_z_p_zz
            IEM_INSTR_IMPL_A64__srhadd_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500f000: SRI  <Zd>.<T>, <Zn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_insert, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_sri_z_zzi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500f000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sri_z_zzi Zd=%#x Zn=%#x imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sri_z_zzi
            IEM_INSTR_IMPL_A64__sri_z_zzi(Zd, Zn, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a220: SRSHL  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_shift_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_srshl_mz_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a220))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: srshl_mz_zzv_2x1 U=%u Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__srshl_mz_zzv_2x1
            IEM_INSTR_IMPL_A64__srshl_mz_zzv_2x1(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120aa20: SRSHL  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_shift_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_srshl_mz_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120aa20))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: srshl_mz_zzv_4x1 U=%u Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__srshl_mz_zzv_4x1
            IEM_INSTR_IMPL_A64__srshl_mz_zzv_4x1(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b220: SRSHL  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_shift_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_srshl_mz_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b220))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: srshl_mz_zzw_2x2 U=%u Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__srshl_mz_zzw_2x2
            IEM_INSTR_IMPL_A64__srshl_mz_zzw_2x2(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120ba20: SRSHL  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_shift_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_srshl_mz_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120ba20))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: srshl_mz_zzw_4x4 U=%u Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__srshl_mz_zzw_4x4
            IEM_INSTR_IMPL_A64__srshl_mz_zzw_4x4(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44028000: SRSHL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_bin_pred_shift_sat_round, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_srshl_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44028000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: srshl_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__srshl_z_p_zz
            IEM_INSTR_IMPL_A64__srshl_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44068000: SRSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_bin_pred_shift_sat_round, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_srshlr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44068000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: srshlr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__srshlr_z_p_zz
            IEM_INSTR_IMPL_A64__srshlr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040c8000: SRSHR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_0, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_srshr_z_p_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040c8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >>  5) & 0x00000007;
        uint32_t const tszl       = (uOpcode >>  8) & 0x00000003;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: srshr_z_p_zi Zdn=%#x imm3=%u tszl=%u Pg=%u U=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm3, tszl, Pg, U, tszh));
#ifdef IEM_INSTR_IMPL_A64__srshr_z_p_zi
            IEM_INSTR_IMPL_A64__srshr_z_p_zi(Zdn, imm3, tszl, Pg, U, tszh);
#else
            RT_NOREF(Zdn, imm3, tszl, Pg, U, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500e800: SRSRA  <Zda>.<T>, <Zn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_intx_sra, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_srsra_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: srsra_z_zi Zda=%#x Zn=%#x U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__srsra_z_zi
        IEM_INSTR_IMPL_A64__srsra_z_zi(Zda, Zn, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zda, Zn, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/4500a000: SSHLLB  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_long, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_sshllb_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sshllb_z_zi Zd=%#x Zn=%#x T=%u U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sshllb_z_zi
        IEM_INSTR_IMPL_A64__sshllb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/4500a400: SSHLLT  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_long, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_sshllt_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x4500a400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sshllt_z_zi Zd=%#x Zn=%#x T=%u U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__sshllt_z_zi
            IEM_INSTR_IMPL_A64__sshllt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, U, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500e000: SSRA  <Zda>.<T>, <Zn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_intx_sra, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_ssra_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ssra_z_zi Zda=%#x Zn=%#x U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__ssra_z_zi
        IEM_INSTR_IMPL_A64__ssra_z_zi(Zda, Zn, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zda, Zn, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45001000: SSUBLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_ssublb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ssublb_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__ssublb_z_zz
        IEM_INSTR_IMPL_A64__ssublb_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45008800: SSUBLBT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_clong, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_ssublbt_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45008800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ssublbt_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__ssublbt_z_zz
            IEM_INSTR_IMPL_A64__ssublbt_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45001400: SSUBLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_ssublt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ssublt_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__ssublt_z_zz
        IEM_INSTR_IMPL_A64__ssublt_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45008c00: SSUBLTB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_clong, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_ssubltb_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45008c00))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ssubltb_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__ssubltb_z_zz
            IEM_INSTR_IMPL_A64__ssubltb_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45005000: SSUBWB  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_wide, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_ssubwb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ssubwb_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__ssubwb_z_zz
        IEM_INSTR_IMPL_A64__ssubwb_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45005400: SSUBWT  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_wide, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_ssubwt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ssubwt_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__ssubwt_z_zz
        IEM_INSTR_IMPL_A64__ssubwt_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0600000: ST1B  { <Zt1>.B-<Zt2>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1b_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1b_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1b_mz_p_bi_2
        IEM_INSTR_IMPL_A64__st1b_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a0608000: ST1B  { <Zt1>.B-<Zt4>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1b_mz_p_bi_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1b_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1b_mz_p_bi_4
        IEM_INSTR_IMPL_A64__st1b_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0200000: ST1B  { <Zt1>.B-<Zt2>.B }, <PNg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1b_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1b_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1b_mz_p_br_2
        IEM_INSTR_IMPL_A64__st1b_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a0208000: ST1B  { <Zt1>.B-<Zt4>.B }, <PNg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1b_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1b_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1b_mz_p_br_4
        IEM_INSTR_IMPL_A64__st1b_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1600000: ST1B  { <Zt1>.B, <Zt2>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1b_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1b_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1b_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__st1b_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a1608000: ST1B  { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1b_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1b_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1b_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__st1b_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1200000: ST1B  { <Zt1>.B, <Zt2>.B }, <PNg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1b_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1b_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1b_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__st1b_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a1208000: ST1B  { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1b_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1b_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1b_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__st1b_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e440a000: ST1B  { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_sst_vi_a, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1b_z_p_ai_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe440a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1b_z_p_ai_d Zt=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__st1b_z_p_ai_d
            IEM_INSTR_IMPL_A64__st1b_z_p_ai_d(Zt, Zn, Pg, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e460a000: ST1B  { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_sst_vi_b, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1b_z_p_ai_s, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: st1b_z_p_ai_s Zt=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__st1b_z_p_ai_s
        IEM_INSTR_IMPL_A64__st1b_z_p_ai_s(Zt, Zn, Pg, imm5);
#else
        RT_NOREF(Zt, Zn, Pg, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff90e000/e400e000: ST1B  { <Zt>.<T> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cst_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1b_z_p_bi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff90e000)) == UINT32_C(0xe400e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 21) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: st1b_z_p_bi Zt=%#x Rn=%#x Pg=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__st1b_z_p_bi
            IEM_INSTR_IMPL_A64__st1b_z_p_bi(Zt, Rn, Pg, imm4, size);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80e000/e4004000: ST1B  { <Zt>.<T> }, <Pg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_cst_ss, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1b_z_p_br, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 21) & 0x00000003;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && ((uOpcode >> 22) & 0x7) != 6)
    {
        LogFlow(("%018x/%010x: st1b_z_p_br Zt=%#x Rn=%#x Pg=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__st1b_z_p_br
        IEM_INSTR_IMPL_A64__st1b_z_p_br(Zt, Rn, Pg, Rm, size);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e400a000: ST1B  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_sst_vs2, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1b_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe400a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1b_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1b_z_p_bz_d_64_unscaled
            IEM_INSTR_IMPL_A64__st1b_z_p_bz_d_64_unscaled(Zt, Rn, Pg, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0a000/e4008000: ST1B  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_sst_vs_a, sve_memst_ss, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1b_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const xs         = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: st1b_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u xs=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, xs, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1b_z_p_bz_d_x32_unscaled
        IEM_INSTR_IMPL_A64__st1b_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, xs, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, xs, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0a000/e4408000: ST1B  { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_sst_vs_b, sve_memst_ss, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1b_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0a000)) == UINT32_C(0xe4408000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const xs         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1b_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u xs=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, xs, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1b_z_p_bz_s_x32_unscaled
            IEM_INSTR_IMPL_A64__st1b_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, xs, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, xs, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00010/e0200000: ST1B  { ZA0<HV>.B[<Ws>, <offs>] }, <Pg>, [<Xn|SP>{, <Xm>}]
   Instruction Set: A64  Groups: mortlach_contig_store, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1b_za_p_rrr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00010)) == UINT32_C(0xe0200000))
    {
        uint32_t const off4       = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: st1b_za_p_rrr off4=%#x Rn=%#x Pg=%u Rs=%u V=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off4, Rn, Pg, Rs, V, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1b_za_p_rrr
            IEM_INSTR_IMPL_A64__st1b_za_p_rrr(off4, Rn, Pg, Rs, V, Rm);
#else
            RT_NOREF(off4, Rn, Pg, Rs, V, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0606000: ST1D  { <Zt1>.D-<Zt2>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1d_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1d_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1d_mz_p_bi_2
        IEM_INSTR_IMPL_A64__st1d_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a060e000: ST1D  { <Zt1>.D-<Zt4>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1d_mz_p_bi_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa060e000))
    {
        uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: st1d_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1d_mz_p_bi_4
            IEM_INSTR_IMPL_A64__st1d_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
            RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0206000: ST1D  { <Zt1>.D-<Zt2>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1d_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1d_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1d_mz_p_br_2
        IEM_INSTR_IMPL_A64__st1d_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a020e000: ST1D  { <Zt1>.D-<Zt4>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1d_mz_p_br_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa020e000))
    {
        uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: st1d_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1d_mz_p_br_4
            IEM_INSTR_IMPL_A64__st1d_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
            RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1606000: ST1D  { <Zt1>.D, <Zt2>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1d_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1d_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1d_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__st1d_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a160e000: ST1D  { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1d_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1d_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1d_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__st1d_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1206000: ST1D  { <Zt1>.D, <Zt2>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1d_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1d_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1d_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__st1d_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a120e000: ST1D  { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1d_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1d_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1d_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__st1d_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5c0a000: ST1D  { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_sst_vi_a, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1d_z_p_ai_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5c0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1d_z_p_ai_d Zt=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__st1d_z_p_ai_d
            IEM_INSTR_IMPL_A64__st1d_z_p_ai_d(Zt, Zn, Pg, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e5e0e000: ST1D  { <Zt>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cst_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1d_z_p_bi, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: st1d_z_p_bi Zt=%#x Rn=%#x Pg=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1d_z_p_bi
        IEM_INSTR_IMPL_A64__st1d_z_p_bi(Zt, Rn, Pg, imm4);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e5c0e000: ST1D  { <Zt>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cst_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1d_z_p_bi_u128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe5c0e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: st1d_z_p_bi_u128 Zt=%#x Rn=%#x Pg=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1d_z_p_bi_u128
            IEM_INSTR_IMPL_A64__st1d_z_p_bi_u128(Zt, Rn, Pg, imm4);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5e04000: ST1D  { <Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_cst_ss, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1d_z_p_br, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5e04000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && 0x7 /*opc@22*/ != 6)
        {
            LogFlow(("%018x/%010x: st1d_z_p_br Zt=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1d_z_p_br
            IEM_INSTR_IMPL_A64__st1d_z_p_br(Zt, Rn, Pg, Rm);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5c04000: ST1D  { <Zt>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_cst_ss, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1d_z_p_br_u128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5c04000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ && Rm != 0x1f && 0x7 /*opc@22*/ != 6)
        {
            LogFlow(("%018x/%010x: st1d_z_p_br_u128 Zt=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1d_z_p_br_u128
            IEM_INSTR_IMPL_A64__st1d_z_p_br_u128(Zt, Rn, Pg, Rm);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5a0a000: ST1D  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3]
   Instruction Set: A64  Groups: sve_mem_sst_sv2, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1d_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: st1d_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_64_scaled(Zt, Rn, Pg, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e580a000: ST1D  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_sst_vs2, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1d_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe580a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1d_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_64_unscaled
            IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_64_unscaled(Zt, Rn, Pg, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0a000/e5a08000: ST1D  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3]
   Instruction Set: A64  Groups: sve_mem_sst_sv_a, sve_memst_ss, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1d_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0a000)) == UINT32_C(0xe5a08000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const xs         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1d_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u xs=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, xs, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_x32_scaled
            IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_x32_scaled(Zt, Rn, Pg, xs, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, xs, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0a000/e5808000: ST1D  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_sst_vs_a, sve_memst_ss, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1d_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0a000)) == UINT32_C(0xe5808000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const xs         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1d_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u xs=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, xs, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, xs, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, xs, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00010/e0e00000: ST1D  { <ZAt><HV>.D[<Ws>, <offs>] }, <Pg>, [<Xn|SP>{, <Xm>, LSL #3}]
   Instruction Set: A64  Groups: mortlach_contig_store, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1d_za_p_rrr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00010)) == UINT32_C(0xe0e00000))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const ZAt        = (uOpcode >>  1) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: st1d_za_p_rrr o1=%u ZAt=%u Rn=%#x Pg=%u Rs=%u V=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, ZAt, Rn, Pg, Rs, V, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1d_za_p_rrr
            IEM_INSTR_IMPL_A64__st1d_za_p_rrr(o1, ZAt, Rn, Pg, Rs, V, Rm);
#else
            RT_NOREF(o1, ZAt, Rn, Pg, Rs, V, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0602000: ST1H  { <Zt1>.H-<Zt2>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1h_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1h_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1h_mz_p_bi_2
        IEM_INSTR_IMPL_A64__st1h_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a060a000: ST1H  { <Zt1>.H-<Zt4>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1h_mz_p_bi_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1h_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1h_mz_p_bi_4
        IEM_INSTR_IMPL_A64__st1h_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0202000: ST1H  { <Zt1>.H-<Zt2>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1h_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1h_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1h_mz_p_br_2
        IEM_INSTR_IMPL_A64__st1h_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a020a000: ST1H  { <Zt1>.H-<Zt4>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1h_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1h_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1h_mz_p_br_4
        IEM_INSTR_IMPL_A64__st1h_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1602000: ST1H  { <Zt1>.H, <Zt2>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1h_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1h_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1h_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__st1h_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a160a000: ST1H  { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1h_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1h_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1h_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__st1h_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1202000: ST1H  { <Zt1>.H, <Zt2>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1h_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1h_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1h_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__st1h_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a120a000: ST1H  { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1h_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1h_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1h_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__st1h_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4c0a000: ST1H  { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_sst_vi_a, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1h_z_p_ai_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4c0a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1h_z_p_ai_d Zt=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__st1h_z_p_ai_d
            IEM_INSTR_IMPL_A64__st1h_z_p_ai_d(Zt, Zn, Pg, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4e0a000: ST1H  { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_sst_vi_b, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1h_z_p_ai_s, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: st1h_z_p_ai_s Zt=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__st1h_z_p_ai_s
        IEM_INSTR_IMPL_A64__st1h_z_p_ai_s(Zt, Zn, Pg, imm5);
#else
        RT_NOREF(Zt, Zn, Pg, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff90e000/e480e000: ST1H  { <Zt>.<T> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cst_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1h_z_p_bi, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 21) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: st1h_z_p_bi Zt=%#x Rn=%#x Pg=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__st1h_z_p_bi
        IEM_INSTR_IMPL_A64__st1h_z_p_bi(Zt, Rn, Pg, imm4, size);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff80e000/e4804000: ST1H  { <Zt>.<T> }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_cst_ss, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1h_z_p_br, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 21) & 0x00000003;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && ((uOpcode >> 22) & 0x7) != 6)
    {
        LogFlow(("%018x/%010x: st1h_z_p_br Zt=%#x Rn=%#x Pg=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__st1h_z_p_br
        IEM_INSTR_IMPL_A64__st1h_z_p_br(Zt, Rn, Pg, Rm, size);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4a0a000: ST1H  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #1]
   Instruction Set: A64  Groups: sve_mem_sst_sv2, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1h_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: st1h_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_64_scaled(Zt, Rn, Pg, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e480a000: ST1H  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_sst_vs2, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1h_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: st1h_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_64_unscaled(Zt, Rn, Pg, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0a000/e4a08000: ST1H  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1]
   Instruction Set: A64  Groups: sve_mem_sst_sv_a, sve_memst_ss, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1h_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0a000)) == UINT32_C(0xe4a08000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const xs         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1h_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u xs=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, xs, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_x32_scaled
            IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_x32_scaled(Zt, Rn, Pg, xs, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, xs, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0a000/e4808000: ST1H  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_sst_vs_a, sve_memst_ss, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1h_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0a000)) == UINT32_C(0xe4808000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const xs         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1h_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u xs=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, xs, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_x32_unscaled
            IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, xs, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, xs, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0a000/e4e08000: ST1H  { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1]
   Instruction Set: A64  Groups: sve_mem_sst_sv_b, sve_memst_ss, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1h_z_p_bz_s_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0a000)) == UINT32_C(0xe4e08000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const xs         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1h_z_p_bz_s_x32_scaled Zt=%#x Rn=%#x Pg=%u xs=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, xs, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1h_z_p_bz_s_x32_scaled
            IEM_INSTR_IMPL_A64__st1h_z_p_bz_s_x32_scaled(Zt, Rn, Pg, xs, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, xs, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0a000/e4c08000: ST1H  { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_sst_vs_b, sve_memst_ss, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1h_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const xs         = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: st1h_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u xs=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, xs, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1h_z_p_bz_s_x32_unscaled
        IEM_INSTR_IMPL_A64__st1h_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, xs, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, xs, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00010/e0600000: ST1H  { <ZAt><HV>.H[<Ws>, <offs>] }, <Pg>, [<Xn|SP>{, <Xm>, LSL #1}]
   Instruction Set: A64  Groups: mortlach_contig_store, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1h_za_p_rrr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00010)) == UINT32_C(0xe0600000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const ZAt        = (uOpcode >>  3) & 0x00000001;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: st1h_za_p_rrr off3=%u ZAt=%u Rn=%#x Pg=%u Rs=%u V=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, ZAt, Rn, Pg, Rs, V, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1h_za_p_rrr
            IEM_INSTR_IMPL_A64__st1h_za_p_rrr(off3, ZAt, Rn, Pg, Rs, V, Rm);
#else
            RT_NOREF(off3, ZAt, Rn, Pg, Rs, V, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4202000: ST1Q  { <Zt>.Q }, <Pg>, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_sstq_64b_vs, sve_memsst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1q_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4202000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: st1q_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1q_z_p_ar_d_64_unscaled
            IEM_INSTR_IMPL_A64__st1q_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm);
#else
            RT_NOREF(Zt, Zn, Pg, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00010/e1e00000: ST1Q  { <ZAt><HV>.Q[<Ws>, <offs>] }, <Pg>, [<Xn|SP>{, <Xm>, LSL #4}]
   Instruction Set: A64  Groups: mortlach_contig_qstore, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1q_za_p_rrr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00010)) == UINT32_C(0xe1e00000))
    {
        uint32_t const ZAt        = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: st1q_za_p_rrr ZAt=%#x Rn=%#x Pg=%u Rs=%u V=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAt, Rn, Pg, Rs, V, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1q_za_p_rrr
            IEM_INSTR_IMPL_A64__st1q_za_p_rrr(ZAt, Rn, Pg, Rs, V, Rm);
#else
            RT_NOREF(ZAt, Rn, Pg, Rs, V, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0604000: ST1W  { <Zt1>.S-<Zt2>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1w_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1w_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1w_mz_p_bi_2
        IEM_INSTR_IMPL_A64__st1w_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a060c000: ST1W  { <Zt1>.S-<Zt4>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1w_mz_p_bi_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa060c000))
    {
        uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: st1w_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1w_mz_p_bi_4
            IEM_INSTR_IMPL_A64__st1w_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
            RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0204000: ST1W  { <Zt1>.S-<Zt2>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1w_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1w_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1w_mz_p_br_2
        IEM_INSTR_IMPL_A64__st1w_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a020c000: ST1W  { <Zt1>.S-<Zt4>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1w_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: st1w_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1w_mz_p_br_4
        IEM_INSTR_IMPL_A64__st1w_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1604000: ST1W  { <Zt1>.S, <Zt2>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1w_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1w_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1w_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__st1w_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a160c000: ST1W  { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1w_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1w_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1w_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__st1w_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1204000: ST1W  { <Zt1>.S, <Zt2>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1w_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1w_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1w_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__st1w_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a120c000: ST1W  { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1w_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: st1w_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1w_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__st1w_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e540a000: ST1W  { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_sst_vi_a, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1w_z_p_ai_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe540a000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1w_z_p_ai_d Zt=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__st1w_z_p_ai_d
            IEM_INSTR_IMPL_A64__st1w_z_p_ai_d(Zt, Zn, Pg, imm5);
#else
            RT_NOREF(Zt, Zn, Pg, imm5, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e560a000: ST1W  { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
   Instruction Set: A64  Groups: sve_mem_sst_vi_b, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1w_z_p_ai_s, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: st1w_z_p_ai_s Zt=%#x Zn=%#x Pg=%u imm5=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, imm5));
#ifdef IEM_INSTR_IMPL_A64__st1w_z_p_ai_s
        IEM_INSTR_IMPL_A64__st1w_z_p_ai_s(Zt, Zn, Pg, imm5);
#else
        RT_NOREF(Zt, Zn, Pg, imm5, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffd0e000/e540e000: ST1W  { <Zt>.<T> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cst_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1w_z_p_bi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffd0e000)) == UINT32_C(0xe540e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 21) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: st1w_z_p_bi Zt=%#x Rn=%#x Pg=%u imm4=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, sz));
#ifdef IEM_INSTR_IMPL_A64__st1w_z_p_bi
            IEM_INSTR_IMPL_A64__st1w_z_p_bi(Zt, Rn, Pg, imm4, sz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e500e000: ST1W  { <Zt>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cst_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1w_z_p_bi_u128, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe500e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: st1w_z_p_bi_u128 Zt=%#x Rn=%#x Pg=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4));
#ifdef IEM_INSTR_IMPL_A64__st1w_z_p_bi_u128
            IEM_INSTR_IMPL_A64__st1w_z_p_bi_u128(Zt, Rn, Pg, imm4);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/e5404000: ST1W  { <Zt>.<T> }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_cst_ss, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1w_z_p_br, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0xe5404000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const sz         = (uOpcode >> 21) & 0x00000001;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && 0x5 /*opc@22*/ != 6)
        {
            LogFlow(("%018x/%010x: st1w_z_p_br Zt=%#x Rn=%#x Pg=%u Rm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, sz));
#ifdef IEM_INSTR_IMPL_A64__st1w_z_p_br
            IEM_INSTR_IMPL_A64__st1w_z_p_br(Zt, Rn, Pg, Rm, sz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5004000: ST1W  { <Zt>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_cst_ss, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1w_z_p_br_u128, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ && Rm != 0x1f && 0x4 /*opc@22*/ != 6)
    {
        LogFlow(("%018x/%010x: st1w_z_p_br_u128 Zt=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1w_z_p_br_u128
        IEM_INSTR_IMPL_A64__st1w_z_p_br_u128(Zt, Rn, Pg, Rm);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e520a000: ST1W  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2]
   Instruction Set: A64  Groups: sve_mem_sst_sv2, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1w_z_p_bz_d_64_scaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: st1w_z_p_bz_d_64_scaled Zt=%#x Rn=%#x Pg=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_64_scaled
        IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_64_scaled(Zt, Rn, Pg, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e500a000: ST1W  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
   Instruction Set: A64  Groups: sve_mem_sst_vs2, sve_memst_ss2, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1w_z_p_bz_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: st1w_z_p_bz_d_64_unscaled Zt=%#x Rn=%#x Pg=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_64_unscaled
        IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_64_unscaled(Zt, Rn, Pg, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0a000/e5208000: ST1W  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2]
   Instruction Set: A64  Groups: sve_mem_sst_sv_a, sve_memst_ss, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1w_z_p_bz_d_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0a000)) == UINT32_C(0xe5208000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const xs         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1w_z_p_bz_d_x32_scaled Zt=%#x Rn=%#x Pg=%u xs=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, xs, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_x32_scaled
            IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_x32_scaled(Zt, Rn, Pg, xs, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, xs, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0a000/e5008000: ST1W  { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
   Instruction Set: A64  Groups: sve_mem_sst_vs_a, sve_memst_ss, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1w_z_p_bz_d_x32_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const xs         = (uOpcode >> 14) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: st1w_z_p_bz_d_x32_unscaled Zt=%#x Rn=%#x Pg=%u xs=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, xs, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_x32_unscaled
        IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, xs, Zm);
#else
        RT_NOREF(Zt, Rn, Pg, xs, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0a000/e5608000: ST1W  { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2]
   Instruction Set: A64  Groups: sve_mem_sst_sv_b, sve_memst_ss, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1w_z_p_bz_s_x32_scaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0a000)) == UINT32_C(0xe5608000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const xs         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1w_z_p_bz_s_x32_scaled Zt=%#x Rn=%#x Pg=%u xs=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, xs, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1w_z_p_bz_s_x32_scaled
            IEM_INSTR_IMPL_A64__st1w_z_p_bz_s_x32_scaled(Zt, Rn, Pg, xs, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, xs, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0a000/e5408000: ST1W  { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
   Instruction Set: A64  Groups: sve_mem_sst_vs_b, sve_memst_ss, sve */
FNIEMOP_DEF_1(iemDecodeA64_st1w_z_p_bz_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0a000)) == UINT32_C(0xe5408000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const xs         = (uOpcode >> 14) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
        {
            LogFlow(("%018x/%010x: st1w_z_p_bz_s_x32_unscaled Zt=%#x Rn=%#x Pg=%u xs=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, xs, Zm));
#ifdef IEM_INSTR_IMPL_A64__st1w_z_p_bz_s_x32_unscaled
            IEM_INSTR_IMPL_A64__st1w_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, xs, Zm);
#else
            RT_NOREF(Zt, Rn, Pg, xs, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00010/e0a00000: ST1W  { <ZAt><HV>.S[<Ws>, <offs>] }, <Pg>, [<Xn|SP>{, <Xm>, LSL #2}]
   Instruction Set: A64  Groups: mortlach_contig_store, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_st1w_za_p_rrr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00010)) == UINT32_C(0xe0a00000))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const ZAt        = (uOpcode >>  2) & 0x00000003;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rs         = (uOpcode >> 13) & 0x00000003;
        uint32_t const V          = (uOpcode >> 15) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: st1w_za_p_rrr off2=%u ZAt=%u Rn=%#x Pg=%u Rs=%u V=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, ZAt, Rn, Pg, Rs, V, Rm));
#ifdef IEM_INSTR_IMPL_A64__st1w_za_p_rrr
            IEM_INSTR_IMPL_A64__st1w_za_p_rrr(off2, ZAt, Rn, Pg, Rs, V, Rm);
#else
            RT_NOREF(off2, ZAt, Rn, Pg, Rs, V, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e430e000: ST2B  { <Zt1>.B, <Zt2>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_est_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st2b_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe430e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: st2b_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__st2b_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__st2b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4206000: ST2B  { <Zt1>.B, <Zt2>.B }, <Pg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_est_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st2b_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st2b_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__st2b_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__st2b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e5b0e000: ST2D  { <Zt1>.D, <Zt2>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_est_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st2d_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st2d_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__st2d_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__st2d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5a06000: ST2D  { <Zt1>.D, <Zt2>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_est_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st2d_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5a06000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (Rm != 0x1f && 0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: st2d_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__st2d_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__st2d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e4b0e000: ST2H  { <Zt1>.H, <Zt2>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_est_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st2h_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st2h_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__st2h_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__st2h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4a06000: ST2H  { <Zt1>.H, <Zt2>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_est_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st2h_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4a06000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (Rm != 0x1f && 0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: st2h_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__st2h_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__st2h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e4400000: ST2Q  { <Zt1>.Q, <Zt2>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_estq_si, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_st2q_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe4400000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: st2q_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4));
#ifdef IEM_INSTR_IMPL_A64__st2q_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__st2q_z_p_bi_contiguous(Zt, Rn, Pg, imm4);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4600000: ST2Q  { <Zt1>.Q, <Zt2>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #4]
   Instruction Set: A64  Groups: sve_mem_estq_ss, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_st2q_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/))
    {
        LogFlow(("%018x/%010x: st2q_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__st2q_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__st2q_z_p_br_contiguous(Zt, Rn, Pg, Rm);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e530e000: ST2W  { <Zt1>.S, <Zt2>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_est_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st2w_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe530e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: st2w_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__st2w_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__st2w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5206000: ST2W  { <Zt1>.S, <Zt2>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_est_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st2w_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x1 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st2w_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__st2w_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__st2w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e450e000: ST3B  { <Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_est_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st3b_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st3b_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__st3b_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__st3b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4406000: ST3B  { <Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_est_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st3b_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st3b_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__st3b_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__st3b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e5d0e000: ST3D  { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_est_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st3d_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st3d_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__st3d_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__st3d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5c06000: ST3D  { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_est_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st3d_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st3d_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__st3d_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__st3d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e4d0e000: ST3H  { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_est_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st3h_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st3h_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__st3h_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__st3h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4c06000: ST3H  { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_est_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st3h_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st3h_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__st3h_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__st3h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e4800000: ST3Q  { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_estq_si, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_st3q_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe4800000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: st3q_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4));
#ifdef IEM_INSTR_IMPL_A64__st3q_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__st3q_z_p_bi_contiguous(Zt, Rn, Pg, imm4);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4a00000: ST3Q  { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #4]
   Instruction Set: A64  Groups: sve_mem_estq_ss, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_st3q_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4a00000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/))
        {
            LogFlow(("%018x/%010x: st3q_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__st3q_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__st3q_z_p_br_contiguous(Zt, Rn, Pg, Rm);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e550e000: ST3W  { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_est_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st3w_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st3w_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__st3w_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__st3w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5406000: ST3W  { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_est_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st3w_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x2 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st3w_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__st3w_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__st3w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e470e000: ST4B  { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_est_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st4b_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe470e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: st4b_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__st4b_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__st4b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4606000: ST4B  { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_est_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st4b_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st4b_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__st4b_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__st4b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e5f0e000: ST4D  { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_est_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st4d_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st4d_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__st4d_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__st4d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5e06000: ST4D  { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_est_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st4d_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5e06000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (Rm != 0x1f && 0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: st4d_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__st4d_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__st4d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e4f0e000: ST4H  { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_est_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st4h_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st4h_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__st4h_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__st4h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4e06000: ST4H  { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_est_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st4h_z_p_br_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4e06000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (Rm != 0x1f && 0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: st4h_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__st4h_z_p_br_contiguous
            IEM_INSTR_IMPL_A64__st4h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
            RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e4c00000: ST4Q  { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_estq_si, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_st4q_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe4c00000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: st4q_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4));
#ifdef IEM_INSTR_IMPL_A64__st4q_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__st4q_z_p_bi_contiguous(Zt, Rn, Pg, imm4);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4e00000: ST4Q  { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #4]
   Instruction Set: A64  Groups: sve_mem_estq_ss, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_st4q_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/))
    {
        LogFlow(("%018x/%010x: st4q_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__st4q_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__st4q_z_p_br_contiguous(Zt, Rn, Pg, Rm);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e570e000: ST4W  { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_est_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_st4w_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe570e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
        {
            LogFlow(("%018x/%010x: st4w_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__st4w_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__st4w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5606000: ST4W  { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_est_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_st4w_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && 0x3 /*opc@21*/ != 0 && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: st4w_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__st4w_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__st4w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/80408008: STMOPA  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_i16i32_2in4ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_stmopa_za32_zzzi_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0x80408008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
        uint32_t const K          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
        {
            LogFlow(("%018x/%010x: stmopa_za32_zzzi_h2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__stmopa_za32_zzzi_h2x1
            IEM_INSTR_IMPL_A64__stmopa_za32_zzzi_h2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
            RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/80408000: STMOPA  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_i8i32_2in4ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_stmopa_za_zzzi_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0x80408000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
        uint32_t const K          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
        {
            LogFlow(("%018x/%010x: stmopa_za_zzzi_b2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__stmopa_za_zzzi_b2x1
            IEM_INSTR_IMPL_A64__stmopa_za_zzzi_b2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
            RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0600001: STNT1B  { <Zt1>.B-<Zt2>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1b_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: stnt1b_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1b_mz_p_bi_2
        IEM_INSTR_IMPL_A64__stnt1b_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a0608001: STNT1B  { <Zt1>.B-<Zt4>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1b_mz_p_bi_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: stnt1b_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1b_mz_p_bi_4
        IEM_INSTR_IMPL_A64__stnt1b_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0200001: STNT1B  { <Zt1>.B-<Zt2>.B }, <PNg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1b_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: stnt1b_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1b_mz_p_br_2
        IEM_INSTR_IMPL_A64__stnt1b_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a0208001: STNT1B  { <Zt1>.B-<Zt4>.B }, <PNg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1b_mz_p_br_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa0208001))
    {
        uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: stnt1b_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1b_mz_p_br_4
            IEM_INSTR_IMPL_A64__stnt1b_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
            RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1600008: STNT1B  { <Zt1>.B, <Zt2>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1b_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1b_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1b_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__stnt1b_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a1608008: STNT1B  { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1b_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1b_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1b_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__stnt1b_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1200008: STNT1B  { <Zt1>.B, <Zt2>.B }, <PNg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1b_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1b_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1b_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__stnt1b_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a1208008: STNT1B  { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1b_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1b_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1b_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__stnt1b_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4002000: STNT1B  { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_sstnt_64b_vs, sve_memsst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1b_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4002000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
        {
            LogFlow(("%018x/%010x: stnt1b_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1b_z_p_ar_d_64_unscaled
            IEM_INSTR_IMPL_A64__stnt1b_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm);
#else
            RT_NOREF(Zt, Zn, Pg, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4402000: STNT1B  { <Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_sstnt_32b_vs, sve_memsst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1b_z_p_ar_s_x32_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: stnt1b_z_p_ar_s_x32_unscaled Zt=%#x Zn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1b_z_p_ar_s_x32_unscaled
        IEM_INSTR_IMPL_A64__stnt1b_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e410e000: STNT1B  { <Zt>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cstnt_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1b_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe410e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: stnt1b_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__stnt1b_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__stnt1b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4006000: STNT1B  { <Zt>.B }, <Pg>, [<Xn|SP>, <Xm>]
   Instruction Set: A64  Groups: sve_mem_cstnt_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1b_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: stnt1b_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__stnt1b_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__stnt1b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0606001: STNT1D  { <Zt1>.D-<Zt2>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1d_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: stnt1d_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1d_mz_p_bi_2
        IEM_INSTR_IMPL_A64__stnt1d_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a060e001: STNT1D  { <Zt1>.D-<Zt4>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1d_mz_p_bi_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa060e001))
    {
        uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: stnt1d_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1d_mz_p_bi_4
            IEM_INSTR_IMPL_A64__stnt1d_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
            RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0206001: STNT1D  { <Zt1>.D-<Zt2>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1d_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: stnt1d_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1d_mz_p_br_2
        IEM_INSTR_IMPL_A64__stnt1d_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a020e001: STNT1D  { <Zt1>.D-<Zt4>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1d_mz_p_br_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa020e001))
    {
        uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: stnt1d_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1d_mz_p_br_4
            IEM_INSTR_IMPL_A64__stnt1d_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
            RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1606008: STNT1D  { <Zt1>.D, <Zt2>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1d_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1d_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1d_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__stnt1d_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a160e008: STNT1D  { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1d_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1d_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1d_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__stnt1d_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1206008: STNT1D  { <Zt1>.D, <Zt2>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1d_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1d_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1d_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__stnt1d_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a120e008: STNT1D  { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1d_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1d_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1d_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__stnt1d_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5802000: STNT1D  { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_sstnt_64b_vs, sve_memsst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1d_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: stnt1d_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1d_z_p_ar_d_64_unscaled
        IEM_INSTR_IMPL_A64__stnt1d_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e590e000: STNT1D  { <Zt>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cstnt_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1d_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: stnt1d_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__stnt1d_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__stnt1d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5806000: STNT1D  { <Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
   Instruction Set: A64  Groups: sve_mem_cstnt_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1d_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: stnt1d_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__stnt1d_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__stnt1d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0602001: STNT1H  { <Zt1>.H-<Zt2>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1h_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: stnt1h_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1h_mz_p_bi_2
        IEM_INSTR_IMPL_A64__stnt1h_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a060a001: STNT1H  { <Zt1>.H-<Zt4>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1h_mz_p_bi_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: stnt1h_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1h_mz_p_bi_4
        IEM_INSTR_IMPL_A64__stnt1h_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0202001: STNT1H  { <Zt1>.H-<Zt2>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1h_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: stnt1h_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1h_mz_p_br_2
        IEM_INSTR_IMPL_A64__stnt1h_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a020a001: STNT1H  { <Zt1>.H-<Zt4>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1h_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: stnt1h_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1h_mz_p_br_4
        IEM_INSTR_IMPL_A64__stnt1h_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1602008: STNT1H  { <Zt1>.H, <Zt2>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1h_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1h_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1h_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__stnt1h_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a160a008: STNT1H  { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1h_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1h_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1h_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__stnt1h_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1202008: STNT1H  { <Zt1>.H, <Zt2>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1h_mzx_p_br_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1h_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1h_mzx_p_br_2x8
        IEM_INSTR_IMPL_A64__stnt1h_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a120a008: STNT1H  { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1h_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1h_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1h_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__stnt1h_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4802000: STNT1H  { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_sstnt_64b_vs, sve_memsst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1h_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: stnt1h_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1h_z_p_ar_d_64_unscaled
        IEM_INSTR_IMPL_A64__stnt1h_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4c02000: STNT1H  { <Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_sstnt_32b_vs, sve_memsst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1h_z_p_ar_s_x32_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4c02000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
        {
            LogFlow(("%018x/%010x: stnt1h_z_p_ar_s_x32_unscaled Zt=%#x Zn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1h_z_p_ar_s_x32_unscaled
            IEM_INSTR_IMPL_A64__stnt1h_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, Rm);
#else
            RT_NOREF(Zt, Zn, Pg, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e490e000: STNT1H  { <Zt>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cstnt_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1h_z_p_bi_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: stnt1h_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__stnt1h_z_p_bi_contiguous
        IEM_INSTR_IMPL_A64__stnt1h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
        RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e4806000: STNT1H  { <Zt>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
   Instruction Set: A64  Groups: sve_mem_cstnt_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1h_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: stnt1h_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__stnt1h_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__stnt1h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e001/a0604001: STNT1W  { <Zt1>.S-<Zt2>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1w_mz_p_bi_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: stnt1w_mz_p_bi_2 Zt=%#x Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1w_mz_p_bi_2
        IEM_INSTR_IMPL_A64__stnt1w_mz_p_bi_2(Zt, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e003/a060c001: STNT1W  { <Zt1>.S-<Zt4>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1w_mz_p_bi_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa060c001))
    {
        uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: stnt1w_mz_p_bi_4 Zt=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1w_mz_p_bi_4
            IEM_INSTR_IMPL_A64__stnt1w_mz_p_bi_4(Zt, Rn, PNg, msz, imm4);
#else
            RT_NOREF(Zt, Rn, PNg, msz, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e001/a0204001: STNT1W  { <Zt1>.S-<Zt2>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1w_mz_p_br_2, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: stnt1w_mz_p_br_2 Zt=%#x Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1w_mz_p_br_2
        IEM_INSTR_IMPL_A64__stnt1w_mz_p_br_2(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e003/a020c001: STNT1W  { <Zt1>.S-<Zt4>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_ctg, mortlach_multi_mem_ctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1w_mz_p_br_4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: stnt1w_mz_p_br_4 Zt=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1w_mz_p_br_4
        IEM_INSTR_IMPL_A64__stnt1w_mz_p_br_4(Zt, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e008/a1604008: STNT1W  { <Zt1>.S, <Zt2>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1w_mzx_p_bi_2x8, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1w_mzx_p_bi_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1w_mzx_p_bi_2x8
        IEM_INSTR_IMPL_A64__stnt1w_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e00c/a160c008: STNT1W  { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_si_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1w_mzx_p_bi_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1w_mzx_p_bi_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, imm4));
#ifdef IEM_INSTR_IMPL_A64__stnt1w_mzx_p_bi_4x4
        IEM_INSTR_IMPL_A64__stnt1w_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e008/a1204008: STNT1W  { <Zt1>.S, <Zt2>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi2_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1w_mzx_p_br_2x8, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1204008))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x00000007;
        uint32_t const T          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
        uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: stnt1w_mzx_p_br_2x8 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1w_mzx_p_br_2x8
            IEM_INSTR_IMPL_A64__stnt1w_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm);
#else
            RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/a120c008: STNT1W  { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: mortlach_multi4_cst_cstnt_ss_nctg, mortlach_multi_mem_nctg, sme */
FNIEMOP_DEF_1(iemDecodeA64_stnt1w_mzx_p_br_4x4, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x00000003;
    uint32_t const T          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const PNg        = (uOpcode >> 10) & 0x00000007;
    uint32_t const msz        = (uOpcode >> 13) & 0x00000003;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: stnt1w_mzx_p_br_4x4 Zt=%u T=%u Rn=%#x PNg=%u msz=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, T, Rn, PNg, msz, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1w_mzx_p_br_4x4
        IEM_INSTR_IMPL_A64__stnt1w_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm);
#else
        RT_NOREF(Zt, T, Rn, PNg, msz, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5002000: STNT1W  { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_sstnt_64b_vs, sve_memsst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1w_z_p_ar_d_64_unscaled, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5002000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
        {
            LogFlow(("%018x/%010x: stnt1w_z_p_ar_d_64_unscaled Zt=%#x Zn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1w_z_p_ar_d_64_unscaled
            IEM_INSTR_IMPL_A64__stnt1w_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm);
#else
            RT_NOREF(Zt, Zn, Pg, Rm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5402000: STNT1W  { <Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]
   Instruction Set: A64  Groups: sve_mem_sstnt_32b_vs, sve_memsst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1w_z_p_ar_s_x32_unscaled, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/)
    {
        LogFlow(("%018x/%010x: stnt1w_z_p_ar_s_x32_unscaled Zt=%#x Zn=%#x Pg=%u Rm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Zn, Pg, Rm));
#ifdef IEM_INSTR_IMPL_A64__stnt1w_z_p_ar_s_x32_unscaled
        IEM_INSTR_IMPL_A64__stnt1w_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, Rm);
#else
        RT_NOREF(Zt, Zn, Pg, Rm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0e000/e510e000: STNT1W  { <Zt>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_cstnt_si, sve_memst_si, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1w_z_p_bi_contiguous, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe510e000))
    {
        uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: stnt1w_z_p_bi_contiguous Zt=%#x Rn=%#x Pg=%u imm4=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, imm4, msz));
#ifdef IEM_INSTR_IMPL_A64__stnt1w_z_p_bi_contiguous
            IEM_INSTR_IMPL_A64__stnt1w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz);
#else
            RT_NOREF(Zt, Rn, Pg, imm4, msz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e000/e5006000: STNT1W  { <Zt>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
   Instruction Set: A64  Groups: sve_mem_cstnt_ss, sve_memcst_nt, sve */
FNIEMOP_DEF_1(iemDecodeA64_stnt1w_z_p_br_contiguous, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const msz        = (uOpcode >> 23) & 0x00000003;
    if (Rm != 0x1f && (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/))
    {
        LogFlow(("%018x/%010x: stnt1w_z_p_br_contiguous Zt=%#x Rn=%#x Pg=%u Rm=%#x msz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, Pg, Rm, msz));
#ifdef IEM_INSTR_IMPL_A64__stnt1w_z_p_br_contiguous
        IEM_INSTR_IMPL_A64__stnt1w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz);
#else
        RT_NOREF(Zt, Rn, Pg, Rm, msz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e010/e5800000: STR  <Pt>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_pspill, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_str_p_bi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e010)) == UINT32_C(0xe5800000))
    {
        uint32_t const Pt         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm9l      = (uOpcode >> 10) & 0x00000007;
        uint32_t const imm9h      = (uOpcode >> 16) & 0x0000003f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: str_p_bi Pt=%#x Rn=%#x imm9l=%u imm9h=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pt, Rn, imm9l, imm9h));
#ifdef IEM_INSTR_IMPL_A64__str_p_bi
            IEM_INSTR_IMPL_A64__str_p_bi(Pt, Rn, imm9l, imm9h);
#else
            RT_NOREF(Pt, Rn, imm9l, imm9h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffc0e000/e5804000: STR  <Zt>, [<Xn|SP>{, #<imm>, MUL VL}]
   Instruction Set: A64  Groups: sve_mem_spill, sve_memst_cs, sve */
FNIEMOP_DEF_1(iemDecodeA64_str_z_bi, uint32_t, uOpcode)
{
    uint32_t const Zt         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm9l      = (uOpcode >> 10) & 0x00000007;
    uint32_t const imm9h      = (uOpcode >> 16) & 0x0000003f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: str_z_bi Zt=%#x Rn=%#x imm9l=%u imm9h=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zt, Rn, imm9l, imm9h));
#ifdef IEM_INSTR_IMPL_A64__str_z_bi
        IEM_INSTR_IMPL_A64__str_z_bi(Zt, Rn, imm9l, imm9h);
#else
        RT_NOREF(Zt, Rn, imm9l, imm9h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9c10/e1200000: STR  ZA[<Wv>, <offs>], [<Xn|SP>{, #<offs>, MUL VL}]
   Instruction Set: A64  Groups: mortlach_ctxt_ldst, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_str_za_ri, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9c10)) == UINT32_C(0xe1200000))
    {
        uint32_t const off4       = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: str_za_ri off4=%#x Rn=%#x Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off4, Rn, Rv));
#ifdef IEM_INSTR_IMPL_A64__str_za_ri
            IEM_INSTR_IMPL_A64__str_za_ri(off4, Rn, Rv);
#else
            RT_NOREF(off4, Rn, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc1f/e13f8000: STR  ZT0, [<Xn|SP>]
   Instruction Set: A64  Groups: mortlach_zt_ldst, mortlach_mem, sme */
FNIEMOP_DEF_1(iemDecodeA64_str_zt_br, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0xe13f8000))
    {
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: str_zt_br Rn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rn));
#ifdef IEM_INSTR_IMPL_A64__str_zt_br
            IEM_INSTR_IMPL_A64__str_zt_br(Rn);
#else
            RT_NOREF(Rn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04010000: SUB  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_0, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_sub_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sub_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__sub_z_p_zz
        IEM_INSTR_IMPL_A64__sub_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fc000/2521c000: SUB  <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: sve_int_arith_imm0, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_sub_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fc000)) == UINT32_C(0x2521c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const sh         = (uOpcode >> 13) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sub_z_zi Zdn=%#x imm8=%#x sh=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm8, sh, size));
#ifdef IEM_INSTR_IMPL_A64__sub_z_zi
            IEM_INSTR_IMPL_A64__sub_z_zi(Zdn, imm8, sh, size);
#else
            RT_NOREF(Zdn, imm8, sh, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04200400: SUB  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_cons_arit_0, sve_int_unpred_arit, sve */
FNIEMOP_DEF_1(iemDecodeA64_sub_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04200400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sub_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__sub_z_zz
            IEM_INSTR_IMPL_A64__sub_z_zz(Zd, Zn, Zm, size);
#else
            RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbf9c38/c1a01c18: SUB  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_int_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_sub_za_zw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbf9c38)) == UINT32_C(0xc1a01c18))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zm         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sub_za_zw_2x2 off3=%u S=%u Zm=%#x Rv=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv, sz));
#ifdef IEM_INSTR_IMPL_A64__sub_za_zw_2x2
            IEM_INSTR_IMPL_A64__sub_za_zw_2x2(off3, S, Zm, Rv, sz);
#else
            RT_NOREF(off3, S, Zm, Rv, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffbf9c78/c1a11c18: SUB  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_int_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_sub_za_zw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbf9c78)) == UINT32_C(0xc1a11c18))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zm         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sub_za_zw_4x4 off3=%u S=%u Zm=%u Rv=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zm, Rv, sz));
#ifdef IEM_INSTR_IMPL_A64__sub_za_zw_4x4
            IEM_INSTR_IMPL_A64__sub_za_zw_4x4(off3, S, Zm, Rv, sz);
#else
            RT_NOREF(off3, S, Zm, Rv, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c18/c1201818: SUB  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_int_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_sub_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c18)) == UINT32_C(0xc1201818))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sub_za_zzv_2x1 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__sub_za_zzv_2x1
            IEM_INSTR_IMPL_A64__sub_za_zzv_2x1(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c18/c1301818: SUB  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_int_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_sub_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c18)) == UINT32_C(0xc1301818))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sub_za_zzv_4x1 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__sub_za_zzv_4x1
            IEM_INSTR_IMPL_A64__sub_za_zzv_4x1(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa19c38/c1a01818: SUB  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_int_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_sub_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa19c38)) == UINT32_C(0xc1a01818))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sub_za_zzw_2x2 off3=%u S=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__sub_za_zzw_2x2
            IEM_INSTR_IMPL_A64__sub_za_zzw_2x2(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa39c78/c1a11818: SUB  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_int_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_sub_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa39c78)) == UINT32_C(0xc1a11818))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sub_za_zzw_4x4 off3=%u S=%u Zn=%u Rv=%u Zm=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__sub_za_zzw_4x4
            IEM_INSTR_IMPL_A64__sub_za_zzw_4x4(off3, S, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, S, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45207000: SUBHNB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_arith_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_subhnb_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45207000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: subhnb_z_zz Zd=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__subhnb_z_zz
            IEM_INSTR_IMPL_A64__subhnb_z_zz(Zd, Zn, T, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45207400: SUBHNT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_arith_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_subhnt_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45207400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: subhnt_z_zz Zd=%#x Zn=%#x T=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__subhnt_z_zz
            IEM_INSTR_IMPL_A64__subhnt_z_zz(Zd, Zn, T, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/04c50000: SUBPT  <Zdn>.D, <Pg>/M, <Zdn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_0, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_subpt_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x04c50000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CPA*/)
        {
            LogFlow(("%018x/%010x: subpt_z_p_zz Zdn=%#x Zm=%#x Pg=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg));
#ifdef IEM_INSTR_IMPL_A64__subpt_z_p_zz
            IEM_INSTR_IMPL_A64__subpt_z_p_zz(Zdn, Zm, Pg);
#else
            RT_NOREF(Zdn, Zm, Pg, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04e00c00: SUBPT  <Zd>.D, <Zn>.D, <Zm>.D
   Instruction Set: A64  Groups: sve_int_bin_cons_arit_0, sve_int_unpred_arit, sve */
FNIEMOP_DEF_1(iemDecodeA64_subpt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ && false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_CPA*/)
    {
        LogFlow(("%018x/%010x: subpt_z_zz Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__subpt_z_zz
        IEM_INSTR_IMPL_A64__subpt_z_zz(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04030000: SUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_0, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_subr_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: subr_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__subr_z_p_zz
        IEM_INSTR_IMPL_A64__subr_z_p_zz(Zdn, Zm, Pg, size);
#else
        RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fc000/2523c000: SUBR  <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: sve_int_arith_imm0, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_subr_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fc000)) == UINT32_C(0x2523c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const sh         = (uOpcode >> 13) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: subr_z_zi Zdn=%#x imm8=%#x sh=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm8, sh, size));
#ifdef IEM_INSTR_IMPL_A64__subr_z_zi
            IEM_INSTR_IMPL_A64__subr_z_zi(Zdn, imm8, sh, size);
#else
            RT_NOREF(Zdn, imm8, sh, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44a01c00: SUDOT  <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
   Instruction Set: A64  Groups: sve_intx_mixed_dot_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_sudot_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fI8mm /*FEAT_I8MM*/)
    {
        LogFlow(("%018x/%010x: sudot_z_zzzi_s Zda=%#x Zn=%#x U=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__sudot_z_zzzi_s
        IEM_INSTR_IMPL_A64__sudot_z_zzzi_s(Zda, Zn, U, Zm, i2);
#else
        RT_NOREF(Zda, Zn, U, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1501038: SUDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_sudot_za_zzi_s2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1501038))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sudot_za_zzi_s2xi off3=%u U=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sudot_za_zzi_s2xi
            IEM_INSTR_IMPL_A64__sudot_za_zzi_s2xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1509038: SUDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sudot_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1509038))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sudot_za_zzi_s4xi off3=%u U=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sudot_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__sudot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1201418: SUDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi2_z_za_mixed_dot_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_sudot_za_zzv_s2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1201418))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sudot_za_zzv_s2x1 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sudot_za_zzv_s2x1
            IEM_INSTR_IMPL_A64__sudot_za_zzv_s2x1(off3, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1301418: SUDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi4_z_za_mixed_dot_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_sudot_za_zzv_s4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1301418))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sudot_za_zzv_s4x1 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sudot_za_zzv_s4x1
            IEM_INSTR_IMPL_A64__sudot_za_zzv_s4x1(off3, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0001c/c1000014: SUMLALL  ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_long_idx_s, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumlall_za_zzi_s, uint32_t, uOpcode)
{
    uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
    uint32_t const U          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i4l        = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const i4h        = (uOpcode >> 15) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sumlall_za_zzi_s off2=%u U=%u Zn=%#x i4l=%u Rv=%u i4h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, U, Zn, i4l, Rv, i4h, Zm));
#ifdef IEM_INSTR_IMPL_A64__sumlall_za_zzi_s
        IEM_INSTR_IMPL_A64__sumlall_za_zzi_s(off2, U, Zn, i4l, Rv, i4h, Zm);
#else
        RT_NOREF(off2, U, Zn, i4l, Rv, i4h, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1100030: SUMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_long_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumlall_za_zzi_s2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1100030))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sumlall_za_zzi_s2xi o1=%u i4l=%u U=%u Zn=%#x i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, U, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sumlall_za_zzi_s2xi
            IEM_INSTR_IMPL_A64__sumlall_za_zzi_s2xi(o1, i4l, U, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, U, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1108030: SUMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_long_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumlall_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1108030))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sumlall_za_zzi_s4xi o1=%u i4l=%u U=%u Zn=%u i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, U, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sumlall_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__sumlall_za_zzi_s4xi(o1, i4l, U, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, U, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1e/c1200014: SUMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumlall_za_zzv_s2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1e)) == UINT32_C(0xc1200014))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sumlall_za_zzv_s2x1 o1=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sumlall_za_zzv_s2x1
            IEM_INSTR_IMPL_A64__sumlall_za_zzv_s2x1(o1, U, Zn, Rv, Zm);
#else
            RT_NOREF(o1, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1e/c1300014: SUMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumlall_za_zzv_s4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1e)) == UINT32_C(0xc1300014))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: sumlall_za_zzv_s4x1 o1=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__sumlall_za_zzv_s4x1
            IEM_INSTR_IMPL_A64__sumlall_za_zzv_s4x1(o1, U, Zn, Rv, Zm);
#else
            RT_NOREF(o1, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80208000: SUMOP4A  <ZAda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4a_za_zz_b1x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
    {
        LogFlow(("%018x/%010x: sumop4a_za_zz_b1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4a_za_zz_b1x1
        IEM_INSTR_IMPL_A64__sumop4a_za_zz_b1x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80308000: SUMOP4A  <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4a_za_zz_b1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80308000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: sumop4a_za_zz_b1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4a_za_zz_b1x2
            IEM_INSTR_IMPL_A64__sumop4a_za_zz_b1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80208200: SUMOP4A  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4a_za_zz_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80208200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: sumop4a_za_zz_b2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4a_za_zz_b2x1
            IEM_INSTR_IMPL_A64__sumop4a_za_zz_b2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80308200: SUMOP4A  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4a_za_zz_b2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80308200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: sumop4a_za_zz_b2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4a_za_zz_b2x2
            IEM_INSTR_IMPL_A64__sumop4a_za_zz_b2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0e00008: SUMOP4A  <ZAda>.D, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4a_za_zz_h1x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: sumop4a_za_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4a_za_zz_h1x1
        IEM_INSTR_IMPL_A64__sumop4a_za_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0f00008: SUMOP4A  <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4a_za_zz_h1x2, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: sumop4a_za_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4a_za_zz_h1x2
        IEM_INSTR_IMPL_A64__sumop4a_za_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0e00208: SUMOP4A  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4a_za_zz_h2x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: sumop4a_za_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4a_za_zz_h2x1
        IEM_INSTR_IMPL_A64__sumop4a_za_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0f00208: SUMOP4A  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4a_za_zz_h2x2, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: sumop4a_za_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4a_za_zz_h2x2
        IEM_INSTR_IMPL_A64__sumop4a_za_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80208010: SUMOP4S  <ZAda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4s_za_zz_b1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80208010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: sumop4s_za_zz_b1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4s_za_zz_b1x1
            IEM_INSTR_IMPL_A64__sumop4s_za_zz_b1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80308010: SUMOP4S  <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4s_za_zz_b1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80308010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: sumop4s_za_zz_b1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4s_za_zz_b1x2
            IEM_INSTR_IMPL_A64__sumop4s_za_zz_b1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80208210: SUMOP4S  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4s_za_zz_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80208210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: sumop4s_za_zz_b2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4s_za_zz_b2x1
            IEM_INSTR_IMPL_A64__sumop4s_za_zz_b2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/80308210: SUMOP4S  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4s_za_zz_b2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80308210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: sumop4s_za_zz_b2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4s_za_zz_b2x2
            IEM_INSTR_IMPL_A64__sumop4s_za_zz_b2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0e00018: SUMOP4S  <ZAda>.D, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4s_za_zz_h1x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: sumop4s_za_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4s_za_zz_h1x1
        IEM_INSTR_IMPL_A64__sumop4s_za_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0f00018: SUMOP4S  <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4s_za_zz_h1x2, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: sumop4s_za_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4s_za_zz_h1x2
        IEM_INSTR_IMPL_A64__sumop4s_za_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0e00218: SUMOP4S  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4s_za_zz_h2x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: sumop4s_za_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4s_za_zz_h2x1
        IEM_INSTR_IMPL_A64__sumop4s_za_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a0f00218: SUMOP4S  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumop4s_za_zz_h2x2, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: sumop4s_za_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__sumop4s_za_zz_h2x2
        IEM_INSTR_IMPL_A64__sumop4s_za_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/a0a00000: SUMOPA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod, mortlach_32bit_int_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumopa_za_pp_zz_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sumopa_za_pp_zz_32 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__sumopa_za_pp_zz_32
        IEM_INSTR_IMPL_A64__sumopa_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00018/a0e00000: SUMOPA  <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod, mortlach_64bit_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumopa_za_pp_zz_64, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: sumopa_za_pp_zz_64 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__sumopa_za_pp_zz_64
        IEM_INSTR_IMPL_A64__sumopa_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/a0a00010: SUMOPS  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod, mortlach_32bit_int_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumops_za_pp_zz_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sumops_za_pp_zz_32 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__sumops_za_pp_zz_32
        IEM_INSTR_IMPL_A64__sumops_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00018/a0e00010: SUMOPS  <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod, mortlach_64bit_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_sumops_za_pp_zz_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00018)) == UINT32_C(0xa0e00010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: sumops_za_pp_zz_64 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__sumops_za_pp_zz_64
            IEM_INSTR_IMPL_A64__sumops_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc01/c125e000: SUNPK  { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi2_wide_int, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sunpk_mz_z_2, uint32_t, uOpcode)
{
    uint32_t const U          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sunpk_mz_z_2 U=%u Zd=%#x Zn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zd, Zn, size));
#ifdef IEM_INSTR_IMPL_A64__sunpk_mz_z_2
        IEM_INSTR_IMPL_A64__sunpk_mz_z_2(U, Zd, Zn, size);
#else
        RT_NOREF(U, Zd, Zn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc23/c135e000: SUNPK  { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<Tb>-<Zn2>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_wide_int, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_sunpk_mz_z_4, uint32_t, uOpcode)
{
    uint32_t const U          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: sunpk_mz_z_4 U=%u Zd=%u Zn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zd, Zn, size));
#ifdef IEM_INSTR_IMPL_A64__sunpk_mz_z_4
        IEM_INSTR_IMPL_A64__sunpk_mz_z_4(U, Zd, Zn, size);
#else
        RT_NOREF(U, Zd, Zn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/05313800: SUNPKHI  <Zd>.<T>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_int_perm_unpk, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_sunpkhi_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x05313800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 16) & 0x00000001;
        uint32_t const U          = (uOpcode >> 17) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sunpkhi_z_z Zd=%#x Zn=%#x H=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, U, size));
#ifdef IEM_INSTR_IMPL_A64__sunpkhi_z_z
            IEM_INSTR_IMPL_A64__sunpkhi_z_z(Zd, Zn, H, U, size);
#else
            RT_NOREF(Zd, Zn, H, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/05303800: SUNPKLO  <Zd>.<T>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_int_perm_unpk, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_sunpklo_z_z, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 16) & 0x00000001;
    uint32_t const U          = (uOpcode >> 17) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: sunpklo_z_z Zd=%#x Zn=%#x H=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, U, size));
#ifdef IEM_INSTR_IMPL_A64__sunpklo_z_z
        IEM_INSTR_IMPL_A64__sunpklo_z_z(Zd, Zn, H, U, size);
#else
        RT_NOREF(Zd, Zn, H, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/441c8000: SUQADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary_sat, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_suqadd_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x441c8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: suqadd_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__suqadd_z_p_zz
            IEM_INSTR_IMPL_A64__suqadd_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/80608000: SUTMOPA  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_i8i32_2in4ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_sutmopa_za_zzzi_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0x80608000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
        uint32_t const K          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
        {
            LogFlow(("%018x/%010x: sutmopa_za_zzzi_b2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__sutmopa_za_zzzi_b2x1
            IEM_INSTR_IMPL_A64__sutmopa_za_zzzi_b2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
            RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1508038: SUVDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_suvdot_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1508038))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: suvdot_za_zzi_s4xi off3=%u U=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__suvdot_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__suvdot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1500020: SVDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_svdot_za32_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1500020))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: svdot_za32_zzi_2xi off3=%u U=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__svdot_za32_zzi_2xi
            IEM_INSTR_IMPL_A64__svdot_za32_zzi_2xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09878/c1d08808: SVDOT  ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_d, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_svdot_za_zzi_d4xi, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const U          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const i1         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: svdot_za_zzi_d4xi off3=%u U=%u Zn=%u i1=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i1, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__svdot_za_zzi_d4xi
        IEM_INSTR_IMPL_A64__svdot_za_zzi_d4xi(off3, U, Zn, i1, Rv, Zm);
#else
        RT_NOREF(off3, U, Zn, i1, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1508020: SVDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_svdot_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1508020))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: svdot_za_zzi_s4xi off3=%u U=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__svdot_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__svdot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0410a000: SXTB  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_sxtb_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0410a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sxtb_z_p_z_m Zd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sxtb_z_p_z_m
            IEM_INSTR_IMPL_A64__sxtb_z_p_z_m(Zd, Zn, Pg, U, size);
#else
            RT_NOREF(Zd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0400a000: SXTB  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_sxtb_z_p_z_z, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
    {
        LogFlow(("%018x/%010x: sxtb_z_p_z_z Zd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sxtb_z_p_z_z
        IEM_INSTR_IMPL_A64__sxtb_z_p_z_z(Zd, Zn, Pg, U, size);
#else
        RT_NOREF(Zd, Zn, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0412a000: SXTH  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_sxth_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0412a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sxth_z_p_z_m Zd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sxth_z_p_z_m
            IEM_INSTR_IMPL_A64__sxth_z_p_z_m(Zd, Zn, Pg, U, size);
#else
            RT_NOREF(Zd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0402a000: SXTH  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_sxth_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0402a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: sxth_z_p_z_z Zd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sxth_z_p_z_z
            IEM_INSTR_IMPL_A64__sxth_z_p_z_z(Zd, Zn, Pg, U, size);
#else
            RT_NOREF(Zd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0414a000: SXTW  <Zd>.D, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_sxtw_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0414a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: sxtw_z_p_z_m Zd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sxtw_z_p_z_m
            IEM_INSTR_IMPL_A64__sxtw_z_p_z_m(Zd, Zn, Pg, U, size);
#else
            RT_NOREF(Zd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0404a000: SXTW  <Zd>.D, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_sxtw_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0404a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: sxtw_z_p_z_z Zd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__sxtw_z_p_z_z
            IEM_INSTR_IMPL_A64__sxtw_z_p_z_z(Zd, Zn, Pg, U, size);
#else
            RT_NOREF(Zd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/05203000: TBL  <Zd>.<T>, { <Zn>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_tbl, sve_perm_unpred_c, sve */
FNIEMOP_DEF_1(iemDecodeA64_tbl_z_zz_1, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: tbl_z_zz_1 Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__tbl_z_zz_1
        IEM_INSTR_IMPL_A64__tbl_z_zz_1(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/05202800: TBL  <Zd>.<T>, { <Zn1>.<T>, <Zn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_tbl_3src, sve_perm_unpred_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_tbl_z_zz_2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: tbl_z_zz_2 Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__tbl_z_zz_2
        IEM_INSTR_IMPL_A64__tbl_z_zz_2(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4400f800: TBLQ  <Zd>.<T>, { <Zn>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_binquads, sve_perm_quads_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_tblq_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: tblq_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__tblq_z_zz
        IEM_INSTR_IMPL_A64__tblq_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/05202c00: TBX  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_tbl_3src, sve_perm_unpred_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_tbx_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: tbx_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__tbx_z_zz
        IEM_INSTR_IMPL_A64__tbx_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/05203400: TBXQ  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_tbxquads, sve_perm_quads_c, sve */
FNIEMOP_DEF_1(iemDecodeA64_tbxq_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: tbxq_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__tbxq_z_zz
        IEM_INSTR_IMPL_A64__tbxq_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30fe10/05205000: TRN1  <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_bin_perm_pp, sve_perm_predicates, sve */
FNIEMOP_DEF_1(iemDecodeA64_trn1_p_pp, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: trn1_p_pp Pd=%#x Pn=%#x H=%u Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, H, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__trn1_p_pp
        IEM_INSTR_IMPL_A64__trn1_p_pp(Pd, Pn, H, Pm, size);
#else
        RT_NOREF(Pd, Pn, H, Pm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/05207000: TRN1  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_bin_perm_zz, sve_perm_inter, sve */
FNIEMOP_DEF_1(iemDecodeA64_trn1_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: trn1_z_zz Zd=%#x Zn=%#x H=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__trn1_z_zz
        IEM_INSTR_IMPL_A64__trn1_z_zz(Zd, Zn, H, Zm, size);
#else
        RT_NOREF(Zd, Zn, H, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/05a01800: TRN1  <Zd>.Q, <Zn>.Q, <Zm>.Q
   Instruction Set: A64  Groups: sve_int_perm_bin_long_perm_zz, sve_perm_inter_long, sve */
FNIEMOP_DEF_1(iemDecodeA64_trn1_z_zz_q, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x05a01800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
        {
            LogFlow(("%018x/%010x: trn1_z_zz_q Zd=%#x Zn=%#x H=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm));
#ifdef IEM_INSTR_IMPL_A64__trn1_z_zz_q
            IEM_INSTR_IMPL_A64__trn1_z_zz_q(Zd, Zn, H, Zm);
#else
            RT_NOREF(Zd, Zn, H, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30fe10/05205400: TRN2  <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_bin_perm_pp, sve_perm_predicates, sve */
FNIEMOP_DEF_1(iemDecodeA64_trn2_p_pp, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: trn2_p_pp Pd=%#x Pn=%#x H=%u Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, H, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__trn2_p_pp
        IEM_INSTR_IMPL_A64__trn2_p_pp(Pd, Pn, H, Pm, size);
#else
        RT_NOREF(Pd, Pn, H, Pm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/05207400: TRN2  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_bin_perm_zz, sve_perm_inter, sve */
FNIEMOP_DEF_1(iemDecodeA64_trn2_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: trn2_z_zz Zd=%#x Zn=%#x H=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__trn2_z_zz
        IEM_INSTR_IMPL_A64__trn2_z_zz(Zd, Zn, H, Zm, size);
#else
        RT_NOREF(Zd, Zn, H, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/05a01c00: TRN2  <Zd>.Q, <Zn>.Q, <Zm>.Q
   Instruction Set: A64  Groups: sve_int_perm_bin_long_perm_zz, sve_perm_inter_long, sve */
FNIEMOP_DEF_1(iemDecodeA64_trn2_z_zz_q, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
    {
        LogFlow(("%018x/%010x: trn2_z_zz_q Zd=%#x Zn=%#x H=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm));
#ifdef IEM_INSTR_IMPL_A64__trn2_z_zz_q
        IEM_INSTR_IMPL_A64__trn2_z_zz_q(Zd, Zn, H, Zm);
#else
        RT_NOREF(Zd, Zn, H, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500fc00: UABA  <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_aba, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_uaba_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500fc00))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uaba_z_zzz Zda=%#x Zn=%#x U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uaba_z_zzz
            IEM_INSTR_IMPL_A64__uaba_z_zzz(Zda, Zn, U, Zm, size);
#else
            RT_NOREF(Zda, Zn, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500c800: UABALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_aba_long, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_uabalb_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uabalb_z_zzz Zda=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uabalb_z_zzz
        IEM_INSTR_IMPL_A64__uabalb_z_zzz(Zda, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500cc00: UABALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_aba_long, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_uabalt_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uabalt_z_zzz Zda=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uabalt_z_zzz
        IEM_INSTR_IMPL_A64__uabalt_z_zzz(Zda, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040d0000: UABD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_1, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_uabd_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uabd_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uabd_z_p_zz
        IEM_INSTR_IMPL_A64__uabd_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45003800: UABDLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_uabdlb_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45003800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uabdlb_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uabdlb_z_zz
            IEM_INSTR_IMPL_A64__uabdlb_z_zz(Zd, Zn, T, U, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45003c00: UABDLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_uabdlt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uabdlt_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uabdlt_z_zz
        IEM_INSTR_IMPL_A64__uabdlt_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4405a000: UADALP  <Zda>.<T>, <Pg>/M, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_intx_accumulate_long_pairs, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_uadalp_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4405a000))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uadalp_z_p_z Zda=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uadalp_z_p_z
            IEM_INSTR_IMPL_A64__uadalp_z_p_z(Zda, Zn, Pg, U, size);
#else
            RT_NOREF(Zda, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45000800: UADDLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_uaddlb_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45000800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uaddlb_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uaddlb_z_zz
            IEM_INSTR_IMPL_A64__uaddlb_z_zz(Zd, Zn, T, U, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45000c00: UADDLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_uaddlt_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45000c00))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uaddlt_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uaddlt_z_zz
            IEM_INSTR_IMPL_A64__uaddlt_z_zz(Zd, Zn, T, U, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04012000: UADDV  <Dd>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_reduce_0, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_uaddv_r_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04012000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uaddv_r_p_z Vd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__uaddv_r_p_z
            IEM_INSTR_IMPL_A64__uaddv_r_p_z(Vd, Zn, Pg, size);
#else
            RT_NOREF(Vd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45004800: UADDWB  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_wide, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_uaddwb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uaddwb_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uaddwb_z_zz
        IEM_INSTR_IMPL_A64__uaddwb_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45004c00: UADDWT  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_wide, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_uaddwt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uaddwt_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uaddwt_z_zz
        IEM_INSTR_IMPL_A64__uaddwt_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc01/c120c401: UCLAMP  { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_clamp_int, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_uclamp_mz_zz_2, uint32_t, uOpcode)
{
    uint32_t const U          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: uclamp_mz_zz_2 U=%u Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uclamp_mz_zz_2
        IEM_INSTR_IMPL_A64__uclamp_mz_zz_2(U, Zd, Zn, Zm, size);
#else
        RT_NOREF(U, Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc03/c120cc01: UCLAMP  { <Zd1>.<T>-<Zd4>.<T> }, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_clamp_int, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_uclamp_mz_zz_4, uint32_t, uOpcode)
{
    uint32_t const U          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: uclamp_mz_zz_4 U=%u Zd=%u Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uclamp_mz_zz_4
        IEM_INSTR_IMPL_A64__uclamp_mz_zz_4(U, Zd, Zn, Zm, size);
#else
        RT_NOREF(U, Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4400c400: UCLAMP  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_clamp_lvl2, sve_intx_clamp, sve */
FNIEMOP_DEF_1(iemDecodeA64_uclamp_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: uclamp_z_zz Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uclamp_z_zz
        IEM_INSTR_IMPL_A64__uclamp_z_zz(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc21/c122e020: UCVTF  { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_intfp_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_mz_z_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc21)) == UINT32_C(0xc122e020))
    {
        uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
        uint32_t const U          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: ucvtf_mz_z_2 Zd=%#x U=%u Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_mz_z_2
            IEM_INSTR_IMPL_A64__ucvtf_mz_z_2(Zd, U, Zn);
#else
            RT_NOREF(Zd, U, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc63/c132e020: UCVTF  { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S }
   Instruction Set: A64  Groups: mortlach_multi4_intfp_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_mz_z_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc63)) == UINT32_C(0xc132e020))
    {
        uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
        uint32_t const U          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: ucvtf_mz_z_4 Zd=%u U=%u Zn=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_mz_z_4
            IEM_INSTR_IMPL_A64__ucvtf_mz_z_4(Zd, U, Zn);
#else
            RT_NOREF(Zd, U, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6553a000: UCVTF  <Zd>.H, <Pg>/M, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_h2fp16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6553a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_h2fp16 Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_h2fp16
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_h2fp16(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/645ce000: UCVTF  <Zd>.H, <Pg>/Z, <Zn>.H
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_h2fp16z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x645ce000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_h2fp16z Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_h2fp16z
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_h2fp16z(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65d1a000: UCVTF  <Zd>.D, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_w2d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65d1a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_w2d Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2d
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2d(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64dca000: UCVTF  <Zd>.D, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_w2dz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64dca000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_w2dz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2dz
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2dz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6555a000: UCVTF  <Zd>.H, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_w2fp16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6555a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_w2fp16 Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2fp16
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2fp16(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/645da000: UCVTF  <Zd>.H, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_w2fp16z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x645da000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_w2fp16z Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2fp16z
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2fp16z(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6595a000: UCVTF  <Zd>.S, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_w2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6595a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_w2s Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2s
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2s(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/649da000: UCVTF  <Zd>.S, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_w2sz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x649da000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_w2sz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2sz
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2sz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65d7a000: UCVTF  <Zd>.D, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_x2d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65d7a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_x2d Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2d
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2d(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64dde000: UCVTF  <Zd>.D, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_x2dz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64dde000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_x2dz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2dz
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2dz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/6557a000: UCVTF  <Zd>.H, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_x2fp16, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6557a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_x2fp16 Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2fp16
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2fp16(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/645de000: UCVTF  <Zd>.H, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_x2fp16z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x645de000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_x2fp16z Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2fp16z
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2fp16z(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/65d5a000: UCVTF  <Zd>.S, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_2op_p_zd_c, sve_fp_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_x2s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65d5a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 16) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_x2s Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2s
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2s(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffe000/64dda000: UCVTF  <Zd>.S, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_fp_z2op_p_zd_c, sve_fp_zeroing_unary, sve */
FNIEMOP_DEF_1(iemDecodeA64_ucvtf_z_p_z_x2sz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64dda000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const int_U      = (uOpcode >> 13) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: ucvtf_z_p_z_x2sz Zd=%#x Zn=%#x Pg=%u int_U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, int_U));
#ifdef IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2sz
            IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2sz(Zd, Zn, Pg, int_U);
#else
            RT_NOREF(Zd, Zn, Pg, int_U, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04150000: UDIV  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_div, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_udiv_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: udiv_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__udiv_z_p_zz
        IEM_INSTR_IMPL_A64__udiv_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04170000: UDIVR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_div, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_udivr_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: udivr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__udivr_z_p_zz
        IEM_INSTR_IMPL_A64__udivr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4400cc00: UDOT  <Zda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: sve_intx_dot2_lvl2, sve_intx_dot2, sve */
FNIEMOP_DEF_1(iemDecodeA64_udot_z32_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: udot_z32_zzz Zda=%#x Zn=%#x U=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm));
#ifdef IEM_INSTR_IMPL_A64__udot_z32_zzz
        IEM_INSTR_IMPL_A64__udot_z32_zzz(Zda, Zn, U, Zm);
#else
        RT_NOREF(Zda, Zn, U, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/4480cc00: UDOT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_dot2_by_indexed_elem_lvl2, sve_intx_dot2_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_udot_z32_zzzi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4480cc00))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: udot_z32_zzzi Zda=%#x Zn=%#x U=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__udot_z32_zzzi
            IEM_INSTR_IMPL_A64__udot_z32_zzzi(Zda, Zn, U, Zm, i2);
#else
            RT_NOREF(Zda, Zn, U, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/44800400: UDOT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_dot, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_udot_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x44800400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: udot_z_zzz Zda=%#x Zn=%#x U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__udot_z_zzz
            IEM_INSTR_IMPL_A64__udot_z_zzz(Zda, Zn, U, Zm, size);
#else
            RT_NOREF(Zda, Zn, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44e00400: UDOT  <Zda>.D, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_dot_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_udot_z_zzzi_d, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i1         = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: udot_z_zzzi_d Zda=%#x Zn=%#x U=%u Zm=%#x i1=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm, i1));
#ifdef IEM_INSTR_IMPL_A64__udot_z_zzzi_d
        IEM_INSTR_IMPL_A64__udot_z_zzzi_d(Zda, Zn, U, Zm, i1);
#else
        RT_NOREF(Zda, Zn, U, Zm, i1, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44a00400: UDOT  <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
   Instruction Set: A64  Groups: sve_intx_dot_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_udot_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: udot_z_zzzi_s Zda=%#x Zn=%#x U=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__udot_z_zzzi_s
        IEM_INSTR_IMPL_A64__udot_z_zzzi_s(Zda, Zn, U, Zm, i2);
#else
        RT_NOREF(Zda, Zn, U, Zm, i2, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1501010: UDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za32_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1501010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: udot_za32_zzi_2xi off3=%u U=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__udot_za32_zzi_2xi
            IEM_INSTR_IMPL_A64__udot_za32_zzi_2xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1509010: UDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za32_zzi_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1509010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: udot_za32_zzi_4xi off3=%u U=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__udot_za32_zzi_4xi
            IEM_INSTR_IMPL_A64__udot_za32_zzi_4xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1601418: UDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_z_za_2way_dot_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za32_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1601418))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: udot_za32_zzv_2x1 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__udot_za32_zzv_2x1
            IEM_INSTR_IMPL_A64__udot_za32_zzv_2x1(off3, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1701418: UDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_z_za_2way_dot_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za32_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1701418))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: udot_za32_zzv_4x1 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__udot_za32_zzv_4x1
            IEM_INSTR_IMPL_A64__udot_za32_zzv_4x1(off3, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c38/c1e01418: UDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_2way_dot_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za32_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c38)) == UINT32_C(0xc1e01418))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: udot_za32_zzw_2x2 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__udot_za32_zzw_2x2
            IEM_INSTR_IMPL_A64__udot_za32_zzw_2x2(off3, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c78/c1e11418: UDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_2way_dot_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za32_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c78)) == UINT32_C(0xc1e11418))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: udot_za32_zzw_4x4 off3=%u U=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__udot_za32_zzw_4x4
            IEM_INSTR_IMPL_A64__udot_za32_zzw_4x4(off3, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09838/c1d00018: UDOT  ZA.D[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_d, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za_zzi_d2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09838)) == UINT32_C(0xc1d00018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i1         = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: udot_za_zzi_d2xi off3=%u U=%u Zn=%#x i1=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i1, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__udot_za_zzi_d2xi
            IEM_INSTR_IMPL_A64__udot_za_zzi_d2xi(off3, U, Zn, i1, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i1, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09878/c1d08018: UDOT  ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_d, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za_zzi_d4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09878)) == UINT32_C(0xc1d08018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i1         = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: udot_za_zzi_d4xi off3=%u U=%u Zn=%u i1=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i1, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__udot_za_zzi_d4xi
            IEM_INSTR_IMPL_A64__udot_za_zzi_d4xi(off3, U, Zn, i1, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i1, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1501030: UDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za_zzi_s2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1501030))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: udot_za_zzi_s2xi off3=%u U=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__udot_za_zzi_s2xi
            IEM_INSTR_IMPL_A64__udot_za_zzi_s2xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1509030: UDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1509030))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: udot_za_zzi_s4xi off3=%u U=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__udot_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__udot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c18/c1201410: UDOT  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi2_z_za_4way_dot_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c18)) == UINT32_C(0xc1201410))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: udot_za_zzv_2x1 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__udot_za_zzv_2x1
            IEM_INSTR_IMPL_A64__udot_za_zzv_2x1(off3, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c18/c1301410: UDOT  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi4_z_za_4way_dot_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c18)) == UINT32_C(0xc1301410))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: udot_za_zzv_4x1 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__udot_za_zzv_4x1
            IEM_INSTR_IMPL_A64__udot_za_zzv_4x1(off3, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa19c38/c1a01410: UDOT  ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, { <Zm1>.<Tb>-<Zm2>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_4way_dot_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa19c38)) == UINT32_C(0xc1a01410))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: udot_za_zzw_2x2 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__udot_za_zzw_2x2
            IEM_INSTR_IMPL_A64__udot_za_zzw_2x2(off3, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa39c78/c1a11410: UDOT  ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, { <Zm1>.<Tb>-<Zm4>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_4way_dot_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_udot_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa39c78)) == UINT32_C(0xc1a11410))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: udot_za_zzw_4x4 off3=%u U=%u Zn=%u Rv=%u Zm=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__udot_za_zzw_4x4
            IEM_INSTR_IMPL_A64__udot_za_zzw_4x4(off3, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44118000: UHADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_uhadd_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44118000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uhadd_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uhadd_z_p_zz
            IEM_INSTR_IMPL_A64__uhadd_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44138000: UHSUB  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_uhsub_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44138000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uhsub_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uhsub_z_p_zz
            IEM_INSTR_IMPL_A64__uhsub_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44178000: UHSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_uhsubr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44178000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uhsubr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uhsubr_z_p_zz
            IEM_INSTR_IMPL_A64__uhsubr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a001: UMAX  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_minmax_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umax_mz_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a001))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umax_mz_zzv_2x1 U=%u Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umax_mz_zzv_2x1
            IEM_INSTR_IMPL_A64__umax_mz_zzv_2x1(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120a801: UMAX  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_minmax_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_umax_mz_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120a801))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umax_mz_zzv_4x1 U=%u Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umax_mz_zzv_4x1
            IEM_INSTR_IMPL_A64__umax_mz_zzv_4x1(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b001: UMAX  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_minmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_umax_mz_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b001))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umax_mz_zzw_2x2 U=%u Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umax_mz_zzw_2x2
            IEM_INSTR_IMPL_A64__umax_mz_zzw_2x2(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120b801: UMAX  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_minmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_umax_mz_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120b801))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umax_mz_zzw_4x4 U=%u Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umax_mz_zzw_4x4
            IEM_INSTR_IMPL_A64__umax_mz_zzw_4x4(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04090000: UMAX  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_1, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_umax_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umax_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__umax_z_p_zz
        IEM_INSTR_IMPL_A64__umax_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/2529c000: UMAX  <Zdn>.<T>, <Zdn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_arith_imm1, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_umax_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x2529c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: umax_z_zi Zdn=%#x imm8=%#x U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm8, U, size));
#ifdef IEM_INSTR_IMPL_A64__umax_z_zi
            IEM_INSTR_IMPL_A64__umax_z_zi(Zdn, imm8, U, size);
#else
            RT_NOREF(Zdn, imm8, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4415a000: UMAXP  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_arith_binary_pairs, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_umaxp_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4415a000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: umaxp_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__umaxp_z_p_zz
            IEM_INSTR_IMPL_A64__umaxp_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040d2000: UMAXQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_int_reduce_1q, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_umaxqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040d2000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: umaxqv_z_p_z Vd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__umaxqv_z_p_z
            IEM_INSTR_IMPL_A64__umaxqv_z_p_z(Vd, Zn, Pg, U, size);
#else
            RT_NOREF(Vd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04092000: UMAXV  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_reduce_1, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_umaxv_r_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04092000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: umaxv_r_p_z Vd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__umaxv_r_p_z
            IEM_INSTR_IMPL_A64__umaxv_r_p_z(Vd, Zn, Pg, U, size);
#else
            RT_NOREF(Vd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a021: UMIN  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_minmax_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umin_mz_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a021))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umin_mz_zzv_2x1 U=%u Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umin_mz_zzv_2x1
            IEM_INSTR_IMPL_A64__umin_mz_zzv_2x1(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120a821: UMIN  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_minmax_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_umin_mz_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120a821))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umin_mz_zzv_4x1 U=%u Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umin_mz_zzv_4x1
            IEM_INSTR_IMPL_A64__umin_mz_zzv_4x1(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b021: UMIN  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_minmax_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_umin_mz_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b021))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umin_mz_zzw_2x2 U=%u Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umin_mz_zzw_2x2
            IEM_INSTR_IMPL_A64__umin_mz_zzw_2x2(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120b821: UMIN  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_minmax_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_umin_mz_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120b821))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umin_mz_zzw_4x4 U=%u Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umin_mz_zzw_4x4
            IEM_INSTR_IMPL_A64__umin_mz_zzw_4x4(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040b0000: UMIN  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_1, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_umin_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umin_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__umin_z_p_zz
        IEM_INSTR_IMPL_A64__umin_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/252bc000: UMIN  <Zdn>.<T>, <Zdn>.<T>, #<imm>
   Instruction Set: A64  Groups: sve_int_arith_imm1, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_umin_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x252bc000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: umin_z_zi Zdn=%#x imm8=%#x U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm8, U, size));
#ifdef IEM_INSTR_IMPL_A64__umin_z_zi
            IEM_INSTR_IMPL_A64__umin_z_zi(Zdn, imm8, U, size);
#else
            RT_NOREF(Zdn, imm8, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4417a000: UMINP  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_arith_binary_pairs, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_uminp_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4417a000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uminp_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uminp_z_p_zz
            IEM_INSTR_IMPL_A64__uminp_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040f2000: UMINQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_int_reduce_1q, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_uminqv_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040f2000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: uminqv_z_p_z Vd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uminqv_z_p_z
            IEM_INSTR_IMPL_A64__uminqv_z_p_z(Vd, Zn, Pg, U, size);
#else
            RT_NOREF(Vd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040b2000: UMINV  <V><d>, <Pg>, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_reduce_1, sve_int_pred_red, sve */
FNIEMOP_DEF_1(iemDecodeA64_uminv_r_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040b2000))
    {
        uint32_t const Vd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uminv_r_p_z Vd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Vd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uminv_r_p_z
            IEM_INSTR_IMPL_A64__uminv_r_p_z(Vd, Zn, Pg, U, size);
#else
            RT_NOREF(Vd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff01018/c1c01010: UMLAL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_idx, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlal_za_zzi_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff01018)) == UINT32_C(0xc1c01010))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i3l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlal_za_zzi_1 off3=%u S=%u U=%u Zn=%#x i3l=%u Rv=%u i3h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, U, Zn, i3l, Rv, i3h, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlal_za_zzi_1
            IEM_INSTR_IMPL_A64__umlal_za_zzi_1(off3, S, U, Zn, i3l, Rv, i3h, Zm);
#else
            RT_NOREF(off3, S, U, Zn, i3l, Rv, i3h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1d01010: UMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_idx, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlal_za_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1d01010))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlal_za_zzi_2xi off2=%u i3l=%u S=%u U=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlal_za_zzi_2xi
            IEM_INSTR_IMPL_A64__umlal_za_zzi_2xi(off2, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1d09010: UMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_idx, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlal_za_zzi_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1d09010))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlal_za_zzi_4xi off2=%u i3l=%u S=%u U=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlal_za_zzi_4xi
            IEM_INSTR_IMPL_A64__umlal_za_zzi_4xi(off2, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1600c10: UMLAL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_mla_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlal_za_zzv_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1600c10))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlal_za_zzv_1 off3=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlal_za_zzv_1
            IEM_INSTR_IMPL_A64__umlal_za_zzv_1(off3, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1600810: UMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlal_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1600810))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlal_za_zzv_2x1 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlal_za_zzv_2x1
            IEM_INSTR_IMPL_A64__umlal_za_zzv_2x1(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1700810: UMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlal_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1700810))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlal_za_zzv_4x1 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlal_za_zzv_4x1
            IEM_INSTR_IMPL_A64__umlal_za_zzv_4x1(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c3c/c1e00810: UMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlal_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c3c)) == UINT32_C(0xc1e00810))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlal_za_zzw_2x2 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlal_za_zzw_2x2
            IEM_INSTR_IMPL_A64__umlal_za_zzw_2x2(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c7c/c1e10810: UMLAL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlal_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c7c)) == UINT32_C(0xc1e10810))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlal_za_zzw_4x4 off2=%u S=%u U=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlal_za_zzw_4x4
            IEM_INSTR_IMPL_A64__umlal_za_zzw_4x4(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44004800: UMLALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_mlal_long, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_umlalb_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umlalb_z_zzz Zda=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umlalb_z_zzz
        IEM_INSTR_IMPL_A64__umlalb_z_zzz(Zda, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e09000: UMLALB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_umlalb_z_zzzi_d, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const S          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umlalb_z_zzzi_d Zda=%#x Zn=%#x T=%u i2l=%u U=%u S=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i2l, U, S, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__umlalb_z_zzzi_d
        IEM_INSTR_IMPL_A64__umlalb_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h);
#else
        RT_NOREF(Zda, Zn, T, i2l, U, S, Zm, i2h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a09000: UMLALB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_umlalb_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const S          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umlalb_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u U=%u S=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, U, S, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__umlalb_z_zzzi_s
        IEM_INSTR_IMPL_A64__umlalb_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h);
#else
        RT_NOREF(Zda, Zn, T, i3l, U, S, Zm, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0101c/c1800010: UMLALL  ZA.D[<Wv>, <offs1>:<offs4>], <Zn>.H, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_long_idx_d, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlall_za_zzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0101c)) == UINT32_C(0xc1800010))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i3l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: umlall_za_zzi_d off2=%u S=%u U=%u Zn=%#x i3l=%u Rv=%u i3h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, i3l, Rv, i3h, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlall_za_zzi_d
            IEM_INSTR_IMPL_A64__umlall_za_zzi_d(off2, S, U, Zn, i3l, Rv, i3h, Zm);
#else
            RT_NOREF(off2, S, U, Zn, i3l, Rv, i3h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09838/c1900010: UMLALL  ZA.D[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_long_idx_d, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlall_za_zzi_d2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09838)) == UINT32_C(0xc1900010))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i3l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: umlall_za_zzi_d2xi o1=%u i3l=%u S=%u U=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlall_za_zzi_d2xi
            IEM_INSTR_IMPL_A64__umlall_za_zzi_d2xi(o1, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(o1, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09878/c1908010: UMLALL  ZA.D[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_long_idx_d, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlall_za_zzi_d4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09878)) == UINT32_C(0xc1908010))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i3l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: umlall_za_zzi_d4xi o1=%u i3l=%u S=%u U=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlall_za_zzi_d4xi
            IEM_INSTR_IMPL_A64__umlall_za_zzi_d4xi(o1, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(o1, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0001c/c1000010: UMLALL  ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_long_idx_s, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlall_za_zzi_s, uint32_t, uOpcode)
{
    uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
    uint32_t const S          = (uOpcode >>  3) & 0x00000001;
    uint32_t const U          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i4l        = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const i4h        = (uOpcode >> 15) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: umlall_za_zzi_s off2=%u S=%u U=%u Zn=%#x i4l=%u Rv=%u i4h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, i4l, Rv, i4h, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlall_za_zzi_s
        IEM_INSTR_IMPL_A64__umlall_za_zzi_s(off2, S, U, Zn, i4l, Rv, i4h, Zm);
#else
        RT_NOREF(off2, S, U, Zn, i4l, Rv, i4h, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1100010: UMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_long_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlall_za_zzi_s2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1100010))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlall_za_zzi_s2xi o1=%u i4l=%u S=%u U=%u Zn=%#x i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, S, U, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlall_za_zzi_s2xi
            IEM_INSTR_IMPL_A64__umlall_za_zzi_s2xi(o1, i4l, S, U, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, S, U, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1108010: UMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_long_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlall_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1108010))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlall_za_zzi_s4xi o1=%u i4l=%u S=%u U=%u Zn=%u i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, S, U, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlall_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__umlall_za_zzi_s4xi(o1, i4l, S, U, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, S, U, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c1c/c1200410: UMLALL  ZA.<T>[<Wv>, <offs1>:<offs4>], <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_mla_long_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlall_za_zzv_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c1c)) == UINT32_C(0xc1200410))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlall_za_zzv_1 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__umlall_za_zzv_1
            IEM_INSTR_IMPL_A64__umlall_za_zzv_1(off2, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c1e/c1200010: UMLALL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlall_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c1e)) == UINT32_C(0xc1200010))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlall_za_zzv_2x1 o1=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__umlall_za_zzv_2x1
            IEM_INSTR_IMPL_A64__umlall_za_zzv_2x1(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c1e/c1300010: UMLALL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlall_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c1e)) == UINT32_C(0xc1300010))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlall_za_zzv_4x1 o1=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__umlall_za_zzv_4x1
            IEM_INSTR_IMPL_A64__umlall_za_zzv_4x1(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa19c3e/c1a00010: UMLALL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, { <Zm1>.<Tb>-<Zm2>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlall_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa19c3e)) == UINT32_C(0xc1a00010))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlall_za_zzw_2x2 o1=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__umlall_za_zzw_2x2
            IEM_INSTR_IMPL_A64__umlall_za_zzw_2x2(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa39c7e/c1a10010: UMLALL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, { <Zm1>.<Tb>-<Zm4>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlall_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa39c7e)) == UINT32_C(0xc1a10010))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlall_za_zzw_4x4 o1=%u S=%u U=%u Zn=%u Rv=%u Zm=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__umlall_za_zzw_4x4
            IEM_INSTR_IMPL_A64__umlall_za_zzw_4x4(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44004c00: UMLALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_mlal_long, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_umlalt_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umlalt_z_zzz Zda=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umlalt_z_zzz
        IEM_INSTR_IMPL_A64__umlalt_z_zzz(Zda, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e09400: UMLALT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_umlalt_z_zzzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e09400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const S          = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: umlalt_z_zzzi_d Zda=%#x Zn=%#x T=%u i2l=%u U=%u S=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i2l, U, S, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__umlalt_z_zzzi_d
            IEM_INSTR_IMPL_A64__umlalt_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h);
#else
            RT_NOREF(Zda, Zn, T, i2l, U, S, Zm, i2h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a09400: UMLALT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_umlalt_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a09400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const S          = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: umlalt_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u U=%u S=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, U, S, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__umlalt_z_zzzi_s
            IEM_INSTR_IMPL_A64__umlalt_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, T, i3l, U, S, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff01018/c1c01018: UMLSL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_idx, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsl_za_zzi_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff01018)) == UINT32_C(0xc1c01018))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i3l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsl_za_zzi_1 off3=%u S=%u U=%u Zn=%#x i3l=%u Rv=%u i3h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, U, Zn, i3l, Rv, i3h, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsl_za_zzi_1
            IEM_INSTR_IMPL_A64__umlsl_za_zzi_1(off3, S, U, Zn, i3l, Rv, i3h, Zm);
#else
            RT_NOREF(off3, S, U, Zn, i3l, Rv, i3h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1d01018: UMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_idx, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsl_za_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1d01018))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsl_za_zzi_2xi off2=%u i3l=%u S=%u U=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsl_za_zzi_2xi
            IEM_INSTR_IMPL_A64__umlsl_za_zzi_2xi(off2, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1d09018: UMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_idx, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsl_za_zzi_4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1d09018))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i3l        = (uOpcode >>  2) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsl_za_zzi_4xi off2=%u i3l=%u S=%u U=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsl_za_zzi_4xi
            IEM_INSTR_IMPL_A64__umlsl_za_zzi_4xi(off2, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(off2, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1600c18: UMLSL  ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_mla_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsl_za_zzv_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1600c18))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsl_za_zzv_1 off3=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsl_za_zzv_1
            IEM_INSTR_IMPL_A64__umlsl_za_zzv_1(off3, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1600818: UMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsl_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1600818))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsl_za_zzv_2x1 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsl_za_zzv_2x1
            IEM_INSTR_IMPL_A64__umlsl_za_zzv_2x1(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1700818: UMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsl_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1700818))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsl_za_zzv_4x1 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsl_za_zzv_4x1
            IEM_INSTR_IMPL_A64__umlsl_za_zzv_4x1(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c3c/c1e00818: UMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsl_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c3c)) == UINT32_C(0xc1e00818))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsl_za_zzw_2x2 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsl_za_zzw_2x2
            IEM_INSTR_IMPL_A64__umlsl_za_zzw_2x2(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c7c/c1e10818: UMLSL  ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsl_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c7c)) == UINT32_C(0xc1e10818))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsl_za_zzw_4x4 off2=%u S=%u U=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsl_za_zzw_4x4
            IEM_INSTR_IMPL_A64__umlsl_za_zzw_4x4(off2, S, U, Zn, Rv, Zm);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44005800: UMLSLB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_mlal_long, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_umlslb_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umlslb_z_zzz Zda=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umlslb_z_zzz
        IEM_INSTR_IMPL_A64__umlslb_z_zzz(Zda, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e0b000: UMLSLB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_umlslb_z_zzzi_d, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const S          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umlslb_z_zzzi_d Zda=%#x Zn=%#x T=%u i2l=%u U=%u S=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i2l, U, S, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__umlslb_z_zzzi_d
        IEM_INSTR_IMPL_A64__umlslb_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h);
#else
        RT_NOREF(Zda, Zn, T, i2l, U, S, Zm, i2h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a0b000: UMLSLB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_umlslb_z_zzzi_s, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const S          = (uOpcode >> 13) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
    uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umlslb_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u U=%u S=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, U, S, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__umlslb_z_zzzi_s
        IEM_INSTR_IMPL_A64__umlslb_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h);
#else
        RT_NOREF(Zda, Zn, T, i3l, U, S, Zm, i3h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0101c/c1800018: UMLSLL  ZA.D[<Wv>, <offs1>:<offs4>], <Zn>.H, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_long_idx_d, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsll_za_zzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0101c)) == UINT32_C(0xc1800018))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i3l        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i3h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: umlsll_za_zzi_d off2=%u S=%u U=%u Zn=%#x i3l=%u Rv=%u i3h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, i3l, Rv, i3h, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsll_za_zzi_d
            IEM_INSTR_IMPL_A64__umlsll_za_zzi_d(off2, S, U, Zn, i3l, Rv, i3h, Zm);
#else
            RT_NOREF(off2, S, U, Zn, i3l, Rv, i3h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09838/c1900018: UMLSLL  ZA.D[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_long_idx_d, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsll_za_zzi_d2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09838)) == UINT32_C(0xc1900018))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i3l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: umlsll_za_zzi_d2xi o1=%u i3l=%u S=%u U=%u Zn=%#x i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsll_za_zzi_d2xi
            IEM_INSTR_IMPL_A64__umlsll_za_zzi_d2xi(o1, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(o1, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09878/c1908018: UMLSLL  ZA.D[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_long_idx_d, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsll_za_zzi_d4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09878)) == UINT32_C(0xc1908018))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i3l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 10) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: umlsll_za_zzi_d4xi o1=%u i3l=%u S=%u U=%u Zn=%u i3h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i3l, S, U, Zn, i3h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsll_za_zzi_d4xi
            IEM_INSTR_IMPL_A64__umlsll_za_zzi_d4xi(o1, i3l, S, U, Zn, i3h, Rv, Zm);
#else
            RT_NOREF(o1, i3l, S, U, Zn, i3h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0001c/c1000018: UMLSLL  ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_long_idx_s, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsll_za_zzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0001c)) == UINT32_C(0xc1000018))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const i4l        = (uOpcode >> 10) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const i4h        = (uOpcode >> 15) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsll_za_zzi_s off2=%u S=%u U=%u Zn=%#x i4l=%u Rv=%u i4h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, i4l, Rv, i4h, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsll_za_zzi_s
            IEM_INSTR_IMPL_A64__umlsll_za_zzi_s(off2, S, U, Zn, i4l, Rv, i4h, Zm);
#else
            RT_NOREF(off2, S, U, Zn, i4l, Rv, i4h, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1100018: UMLSLL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_long_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsll_za_zzi_s2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1100018))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsll_za_zzi_s2xi o1=%u i4l=%u S=%u U=%u Zn=%#x i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, S, U, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsll_za_zzi_s2xi
            IEM_INSTR_IMPL_A64__umlsll_za_zzi_s2xi(o1, i4l, S, U, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, S, U, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1108018: UMLSLL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_long_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsll_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1108018))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsll_za_zzi_s4xi o1=%u i4l=%u S=%u U=%u Zn=%u i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, S, U, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__umlsll_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__umlsll_za_zzi_s4xi(o1, i4l, S, U, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, S, U, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c1c/c1200418: UMLSLL  ZA.<T>[<Wv>, <offs1>:<offs4>], <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_mla_long_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsll_za_zzv_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c1c)) == UINT32_C(0xc1200418))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsll_za_zzv_1 off2=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__umlsll_za_zzv_1
            IEM_INSTR_IMPL_A64__umlsll_za_zzv_1(off2, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(off2, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c1e/c1200018: UMLSLL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsll_za_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c1e)) == UINT32_C(0xc1200018))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsll_za_zzv_2x1 o1=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__umlsll_za_zzv_2x1
            IEM_INSTR_IMPL_A64__umlsll_za_zzv_2x1(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffb09c1e/c1300018: UMLSLL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsll_za_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c1e)) == UINT32_C(0xc1300018))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsll_za_zzv_4x1 o1=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__umlsll_za_zzv_4x1
            IEM_INSTR_IMPL_A64__umlsll_za_zzv_4x1(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa19c3e/c1a00018: UMLSLL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, { <Zm1>.<Tb>-<Zm2>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsll_za_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa19c3e)) == UINT32_C(0xc1a00018))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsll_za_zzw_2x2 o1=%u S=%u U=%u Zn=%#x Rv=%u Zm=%#x sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__umlsll_za_zzw_2x2
            IEM_INSTR_IMPL_A64__umlsll_za_zzw_2x2(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa39c7e/c1a10018: UMLSLL  ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, { <Zm1>.<Tb>-<Zm4>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_umlsll_za_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa39c7e)) == UINT32_C(0xc1a10018))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const S          = (uOpcode >>  3) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const sz         = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: umlsll_za_zzw_4x4 o1=%u S=%u U=%u Zn=%u Rv=%u Zm=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, S, U, Zn, Rv, Zm, sz));
#ifdef IEM_INSTR_IMPL_A64__umlsll_za_zzw_4x4
            IEM_INSTR_IMPL_A64__umlsll_za_zzw_4x4(o1, S, U, Zn, Rv, Zm, sz);
#else
            RT_NOREF(o1, S, U, Zn, Rv, Zm, sz, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/44005c00: UMLSLT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_mlal_long, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_umlslt_z_zzz, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umlslt_z_zzz Zda=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umlslt_z_zzz
        IEM_INSTR_IMPL_A64__umlslt_z_zzz(Zda, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zda, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e0b400: UMLSLT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_umlslt_z_zzzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e0b400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const S          = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: umlslt_z_zzzi_d Zda=%#x Zn=%#x T=%u i2l=%u U=%u S=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i2l, U, S, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__umlslt_z_zzzi_d
            IEM_INSTR_IMPL_A64__umlslt_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h);
#else
            RT_NOREF(Zda, Zn, T, i2l, U, S, Zm, i2h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a0b400: UMLSLT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mla_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_umlslt_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a0b400))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const S          = (uOpcode >> 13) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: umlslt_z_zzzi_s Zda=%#x Zn=%#x T=%u i3l=%u U=%u S=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, T, i3l, U, S, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__umlslt_z_zzzi_s
            IEM_INSTR_IMPL_A64__umlslt_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h);
#else
            RT_NOREF(Zda, Zn, T, i3l, U, S, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/45c09800: UMMLA  <Zda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_intx_mmla, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_ummla_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x45c09800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const uns        = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fI8mm /*FEAT_I8MM*/)
        {
            LogFlow(("%018x/%010x: ummla_z_zzz Zda=%#x Zn=%#x Zm=%#x uns=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm, uns));
#ifdef IEM_INSTR_IMPL_A64__ummla_z_zzz
            IEM_INSTR_IMPL_A64__ummla_z_zzz(Zda, Zn, Zm, uns);
#else
            RT_NOREF(Zda, Zn, Zm, uns, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81008008: UMOP4A  <ZAda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4a_za32_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81008008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4a_za32_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4a_za32_zz_h1x1
            IEM_INSTR_IMPL_A64__umop4a_za32_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81108008: UMOP4A  <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4a_za32_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81108008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4a_za32_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4a_za32_zz_h1x2
            IEM_INSTR_IMPL_A64__umop4a_za32_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81008208: UMOP4A  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4a_za32_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81008208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4a_za32_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4a_za32_zz_h2x1
            IEM_INSTR_IMPL_A64__umop4a_za32_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81108208: UMOP4A  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4a_za32_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81108208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4a_za32_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4a_za32_zz_h2x2
            IEM_INSTR_IMPL_A64__umop4a_za32_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81208000: UMOP4A  <ZAda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4a_za_zz_b1x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
    {
        LogFlow(("%018x/%010x: umop4a_za_zz_b1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4a_za_zz_b1x1
        IEM_INSTR_IMPL_A64__umop4a_za_zz_b1x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81308000: UMOP4A  <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4a_za_zz_b1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81308000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4a_za_zz_b1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4a_za_zz_b1x2
            IEM_INSTR_IMPL_A64__umop4a_za_zz_b1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81208200: UMOP4A  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4a_za_zz_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81208200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4a_za_zz_b2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4a_za_zz_b2x1
            IEM_INSTR_IMPL_A64__umop4a_za_zz_b2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81308200: UMOP4A  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4a_za_zz_b2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81308200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4a_za_zz_b2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4a_za_zz_b2x2
            IEM_INSTR_IMPL_A64__umop4a_za_zz_b2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1e00008: UMOP4A  <ZAda>.D, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4a_za_zz_h1x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: umop4a_za_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4a_za_zz_h1x1
        IEM_INSTR_IMPL_A64__umop4a_za_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1f00008: UMOP4A  <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4a_za_zz_h1x2, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: umop4a_za_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4a_za_zz_h1x2
        IEM_INSTR_IMPL_A64__umop4a_za_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1e00208: UMOP4A  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4a_za_zz_h2x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: umop4a_za_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4a_za_zz_h2x1
        IEM_INSTR_IMPL_A64__umop4a_za_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1f00208: UMOP4A  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4a_za_zz_h2x2, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: umop4a_za_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4a_za_zz_h2x2
        IEM_INSTR_IMPL_A64__umop4a_za_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81008018: UMOP4S  <ZAda>.S, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4s_za32_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81008018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4s_za32_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4s_za32_zz_h1x1
            IEM_INSTR_IMPL_A64__umop4s_za32_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81108018: UMOP4S  <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4s_za32_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81108018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4s_za32_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4s_za32_zz_h1x2
            IEM_INSTR_IMPL_A64__umop4s_za32_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81008218: UMOP4S  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4s_za32_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81008218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4s_za32_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4s_za32_zz_h2x1
            IEM_INSTR_IMPL_A64__umop4s_za32_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81108218: UMOP4S  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4s_za32_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81108218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4s_za32_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4s_za32_zz_h2x2
            IEM_INSTR_IMPL_A64__umop4s_za32_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81208010: UMOP4S  <ZAda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4s_za_zz_b1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81208010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4s_za_zz_b1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4s_za_zz_b1x1
            IEM_INSTR_IMPL_A64__umop4s_za_zz_b1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81308010: UMOP4S  <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4s_za_zz_b1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81308010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4s_za_zz_b1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4s_za_zz_b1x2
            IEM_INSTR_IMPL_A64__umop4s_za_zz_b1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81208210: UMOP4S  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4s_za_zz_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81208210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4s_za_zz_b2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4s_za_zz_b2x1
            IEM_INSTR_IMPL_A64__umop4s_za_zz_b2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81308210: UMOP4S  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4s_za_zz_b2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81308210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: umop4s_za_zz_b2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4s_za_zz_b2x2
            IEM_INSTR_IMPL_A64__umop4s_za_zz_b2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1e00018: UMOP4S  <ZAda>.D, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4s_za_zz_h1x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: umop4s_za_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4s_za_zz_h1x1
        IEM_INSTR_IMPL_A64__umop4s_za_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1f00018: UMOP4S  <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4s_za_zz_h1x2, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: umop4s_za_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4s_za_zz_h1x2
        IEM_INSTR_IMPL_A64__umop4s_za_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1e00218: UMOP4S  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4s_za_zz_h2x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: umop4s_za_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4s_za_zz_h2x1
        IEM_INSTR_IMPL_A64__umop4s_za_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1f00218: UMOP4S  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_umop4s_za_zz_h2x2, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: umop4s_za_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__umop4s_za_zz_h2x2
        IEM_INSTR_IMPL_A64__umop4s_za_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/a1800008: UMOPA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i32_prod, mortlach_32bit_int_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_umopa_za32_pp_zz_16, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: umopa_za32_pp_zz_16 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__umopa_za32_pp_zz_16
        IEM_INSTR_IMPL_A64__umopa_za32_pp_zz_16(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/a1a00000: UMOPA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod, mortlach_32bit_int_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_umopa_za_pp_zz_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umopa_za_pp_zz_32 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__umopa_za_pp_zz_32
        IEM_INSTR_IMPL_A64__umopa_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00018/a1e00000: UMOPA  <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod, mortlach_64bit_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_umopa_za_pp_zz_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00018)) == UINT32_C(0xa1e00000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: umopa_za_pp_zz_64 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__umopa_za_pp_zz_64
            IEM_INSTR_IMPL_A64__umopa_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/a1800018: UMOPS  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i32_prod, mortlach_32bit_int_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_umops_za32_pp_zz_16, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: umops_za32_pp_zz_16 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__umops_za32_pp_zz_16
        IEM_INSTR_IMPL_A64__umops_za32_pp_zz_16(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/a1a00010: UMOPS  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod, mortlach_32bit_int_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_umops_za_pp_zz_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umops_za_pp_zz_32 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__umops_za_pp_zz_32
        IEM_INSTR_IMPL_A64__umops_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00018/a1e00010: UMOPS  <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod, mortlach_64bit_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_umops_za_pp_zz_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00018)) == UINT32_C(0xa1e00010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: umops_za_pp_zz_64 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__umops_za_pp_zz_64
            IEM_INSTR_IMPL_A64__umops_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04130000: UMULH  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_pred_arit_2, sve_int_pred_bin, sve */
FNIEMOP_DEF_1(iemDecodeA64_umulh_z_p_zz, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const U          = (uOpcode >> 16) & 0x00000001;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umulh_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__umulh_z_p_zz
        IEM_INSTR_IMPL_A64__umulh_z_p_zz(Zdn, Zm, Pg, U, size);
#else
        RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04206c00: UMULH  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_mul_b, sve_int_unpred_arit_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_umulh_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umulh_z_zz Zd=%#x Zn=%#x U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umulh_z_zz
        IEM_INSTR_IMPL_A64__umulh_z_zz(Zd, Zn, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45007800: UMULLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_mul_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_umullb_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45007800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: umullb_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umullb_z_zz
            IEM_INSTR_IMPL_A64__umullb_z_zz(Zd, Zn, T, U, Zm, size);
#else
            RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e0d000: UMULLB  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mul_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_umullb_z_zzi_d, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e0d000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: umullb_z_zzi_d Zd=%#x Zn=%#x T=%u i2l=%u U=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, i2l, U, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__umullb_z_zzi_d
            IEM_INSTR_IMPL_A64__umullb_z_zzi_d(Zd, Zn, T, i2l, U, Zm, i2h);
#else
            RT_NOREF(Zd, Zn, T, i2l, U, Zm, i2h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a0d000: UMULLB  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mul_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_umullb_z_zzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a0d000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: umullb_z_zzi_s Zd=%#x Zn=%#x T=%u i3l=%u U=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, i3l, U, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__umullb_z_zzi_s
            IEM_INSTR_IMPL_A64__umullb_z_zzi_s(Zd, Zn, T, i3l, U, Zm, i3h);
#else
            RT_NOREF(Zd, Zn, T, i3l, U, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45007c00: UMULLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_mul_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_umullt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umullt_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__umullt_z_zz
        IEM_INSTR_IMPL_A64__umullt_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44e0d400: UMULLT  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
   Instruction Set: A64  Groups: sve_intx_mul_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_umullt_z_zzi_d, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const i2l        = (uOpcode >> 11) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const i2h        = (uOpcode >> 20) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: umullt_z_zzi_d Zd=%#x Zn=%#x T=%u i2l=%u U=%u Zm=%#x i2h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, i2l, U, Zm, i2h));
#ifdef IEM_INSTR_IMPL_A64__umullt_z_zzi_d
        IEM_INSTR_IMPL_A64__umullt_z_zzi_d(Zd, Zn, T, i2l, U, Zm, i2h);
#else
        RT_NOREF(Zd, Zn, T, i2l, U, Zm, i2h, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0f400/44a0d400: UMULLT  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
   Instruction Set: A64  Groups: sve_intx_mul_long_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_umullt_z_zzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a0d400))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const i3l        = (uOpcode >> 11) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i3h        = (uOpcode >> 19) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: umullt_z_zzi_s Zd=%#x Zn=%#x T=%u i3l=%u U=%u Zm=%u i3h=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, i3l, U, Zm, i3h));
#ifdef IEM_INSTR_IMPL_A64__umullt_z_zzi_s
            IEM_INSTR_IMPL_A64__umullt_z_zzi_s(Zd, Zn, T, i3l, U, Zm, i3h);
#else
            RT_NOREF(Zd, Zn, T, i3l, U, Zm, i3h, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44198000: UQADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary_sat, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqadd_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44198000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqadd_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqadd_z_p_zz
            IEM_INSTR_IMPL_A64__uqadd_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fc000/2525c000: UQADD  <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: sve_int_arith_imm0, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqadd_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fc000)) == UINT32_C(0x2525c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const sh         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqadd_z_zi Zdn=%#x imm8=%#x sh=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm8, sh, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqadd_z_zi
            IEM_INSTR_IMPL_A64__uqadd_z_zi(Zdn, imm8, sh, U, size);
#else
            RT_NOREF(Zdn, imm8, sh, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04201400: UQADD  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_cons_arit_0, sve_int_unpred_arit, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqadd_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqadd_z_zz Zd=%#x Zn=%#x U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uqadd_z_zz
        IEM_INSTR_IMPL_A64__uqadd_z_zz(Zd, Zn, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/c123e020: UQCVT  <Zd>.H, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: mortlach_multi2_narrow_int_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_uqcvt_z_mz2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0xc123e020))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const U          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: uqcvt_z_mz2 Zd=%#x U=%u Zn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn));
#ifdef IEM_INSTR_IMPL_A64__uqcvt_z_mz2
            IEM_INSTR_IMPL_A64__uqcvt_z_mz2(Zd, U, Zn);
#else
            RT_NOREF(Zd, U, Zn, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff7ffc60/c133e020: UQCVT  <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_narrow_int_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_uqcvt_z_mz4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const U          = (uOpcode >>  5) & 0x00000001;
    uint32_t const N          = (uOpcode >>  6) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const sz         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: uqcvt_z_mz4 Zd=%#x U=%u N=%u Zn=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, N, Zn, sz));
#ifdef IEM_INSTR_IMPL_A64__uqcvt_z_mz4
        IEM_INSTR_IMPL_A64__uqcvt_z_mz4(Zd, U, N, Zn, sz);
#else
        RT_NOREF(Zd, U, N, Zn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc20/45314800: UQCVTN  <Zd>.H, { <Zn1>.S-<Zn2>.S }
   Instruction Set: A64  Groups: sve_intx_multi_extract_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqcvtn_z_mz2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: uqcvtn_z_mz2 Zd=%#x Zn=%#x U=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U));
#ifdef IEM_INSTR_IMPL_A64__uqcvtn_z_mz2
        IEM_INSTR_IMPL_A64__uqcvtn_z_mz2(Zd, Zn, U);
#else
        RT_NOREF(Zd, Zn, U, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff7ffc60/c133e060: UQCVTN  <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_narrow_int_cvrt, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_uqcvtn_z_mz4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const U          = (uOpcode >>  5) & 0x00000001;
    uint32_t const N          = (uOpcode >>  6) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const sz         = (uOpcode >> 23) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: uqcvtn_z_mz4 Zd=%#x U=%u N=%u Zn=%u sz=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, N, Zn, sz));
#ifdef IEM_INSTR_IMPL_A64__uqcvtn_z_mz4
        IEM_INSTR_IMPL_A64__uqcvtn_z_mz4(Zd, U, N, Zn, sz);
#else
        RT_NOREF(Zd, U, N, Zn, sz, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0420fc00: UQDECB  <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdecb_r_rs_uw, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqdecb_r_rs_uw Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqdecb_r_rs_uw
        IEM_INSTR_IMPL_A64__uqdecb_r_rs_uw(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0430fc00: UQDECB  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdecb_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqdecb_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqdecb_r_rs_x
        IEM_INSTR_IMPL_A64__uqdecb_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04e0fc00: UQDECD  <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdecd_r_rs_uw, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqdecd_r_rs_uw Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqdecd_r_rs_uw
        IEM_INSTR_IMPL_A64__uqdecd_r_rs_uw(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04f0fc00: UQDECD  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdecd_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqdecd_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqdecd_r_rs_x
        IEM_INSTR_IMPL_A64__uqdecd_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04e0cc00: UQDECD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv0, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdecd_z_zs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04e0cc00))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 10) & 0x00000001;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqdecd_z_zs Zdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqdecd_z_zs
            IEM_INSTR_IMPL_A64__uqdecd_z_zs(Zdn, pattern, U, imm4, size);
#else
            RT_NOREF(Zdn, pattern, U, imm4, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0460fc00: UQDECH  <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdech_r_rs_uw, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqdech_r_rs_uw Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqdech_r_rs_uw
        IEM_INSTR_IMPL_A64__uqdech_r_rs_uw(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0470fc00: UQDECH  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdech_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqdech_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqdech_r_rs_x
        IEM_INSTR_IMPL_A64__uqdech_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0460cc00: UQDECH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv0, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdech_z_zs, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0460cc00))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 10) & 0x00000001;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqdech_z_zs Zdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqdech_z_zs
            IEM_INSTR_IMPL_A64__uqdech_z_zs(Zdn, pattern, U, imm4, size);
#else
            RT_NOREF(Zdn, pattern, U, imm4, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/252b8800: UQDECP  <Wdn>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_r_sat, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdecp_r_p_r_uw, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x252b8800))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqdecp_r_p_r_uw Rdn=%#x Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__uqdecp_r_p_r_uw
            IEM_INSTR_IMPL_A64__uqdecp_r_p_r_uw(Rdn, Pm, size);
#else
            RT_NOREF(Rdn, Pm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/252b8c00: UQDECP  <Xdn>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_r_sat, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdecp_r_p_r_x, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x252b8c00))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqdecp_r_p_r_x Rdn=%#x Pm=%#x U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, Pm, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqdecp_r_p_r_x
            IEM_INSTR_IMPL_A64__uqdecp_r_p_r_x(Rdn, Pm, U, size);
#else
            RT_NOREF(Rdn, Pm, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/252b8000: UQDECP  <Zdn>.<T>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_v_sat, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdecp_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x252b8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqdecp_z_p_z Zdn=%#x Pm=%#x U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Pm, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqdecp_z_p_z
            IEM_INSTR_IMPL_A64__uqdecp_z_p_z(Zdn, Pm, U, size);
#else
            RT_NOREF(Zdn, Pm, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04a0fc00: UQDECW  <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdecw_r_rs_uw, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04a0fc00))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqdecw_r_rs_uw Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqdecw_r_rs_uw
            IEM_INSTR_IMPL_A64__uqdecw_r_rs_uw(Rdn, pattern, imm4, size);
#else
            RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04b0fc00: UQDECW  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdecw_r_rs_x, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04b0fc00))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 10) & 0x00000001;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqdecw_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqdecw_r_rs_x
            IEM_INSTR_IMPL_A64__uqdecw_r_rs_x(Rdn, pattern, U, imm4, size);
#else
            RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04a0cc00: UQDECW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv0, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqdecw_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqdecw_z_zs Zdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqdecw_z_zs
        IEM_INSTR_IMPL_A64__uqdecw_z_zs(Zdn, pattern, U, imm4, size);
#else
        RT_NOREF(Zdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0420f400: UQINCB  <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqincb_r_rs_uw, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqincb_r_rs_uw Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqincb_r_rs_uw
        IEM_INSTR_IMPL_A64__uqincb_r_rs_uw(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0430f400: UQINCB  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqincb_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqincb_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqincb_r_rs_x
        IEM_INSTR_IMPL_A64__uqincb_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04e0f400: UQINCD  <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqincd_r_rs_uw, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqincd_r_rs_uw Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqincd_r_rs_uw
        IEM_INSTR_IMPL_A64__uqincd_r_rs_uw(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04f0f400: UQINCD  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqincd_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqincd_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqincd_r_rs_x
        IEM_INSTR_IMPL_A64__uqincd_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04e0c400: UQINCD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv0, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqincd_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqincd_z_zs Zdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqincd_z_zs
        IEM_INSTR_IMPL_A64__uqincd_z_zs(Zdn, pattern, U, imm4, size);
#else
        RT_NOREF(Zdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0460f400: UQINCH  <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqinch_r_rs_uw, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqinch_r_rs_uw Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqinch_r_rs_uw
        IEM_INSTR_IMPL_A64__uqinch_r_rs_uw(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0470f400: UQINCH  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqinch_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqinch_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqinch_r_rs_x
        IEM_INSTR_IMPL_A64__uqinch_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/0460c400: UQINCH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv0, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqinch_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqinch_z_zs Zdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqinch_z_zs
        IEM_INSTR_IMPL_A64__uqinch_z_zs(Zdn, pattern, U, imm4, size);
#else
        RT_NOREF(Zdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/25298800: UQINCP  <Wdn>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_r_sat, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqincp_r_p_r_uw, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x25298800))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqincp_r_p_r_uw Rdn=%#x Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__uqincp_r_p_r_uw
            IEM_INSTR_IMPL_A64__uqincp_r_p_r_uw(Rdn, Pm, size);
#else
            RT_NOREF(Rdn, Pm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/25298c00: UQINCP  <Xdn>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_r_sat, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqincp_r_p_r_x, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x25298c00))
    {
        uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqincp_r_p_r_x Rdn=%#x Pm=%#x U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, Pm, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqincp_r_p_r_x
            IEM_INSTR_IMPL_A64__uqincp_r_p_r_x(Rdn, Pm, U, size);
#else
            RT_NOREF(Rdn, Pm, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffe00/25298000: UQINCP  <Zdn>.<T>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_count_v_sat, sve_pred_count_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqincp_z_p_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffe00)) == UINT32_C(0x25298000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Pm         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqincp_z_p_z Zdn=%#x Pm=%#x U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Pm, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqincp_z_p_z
            IEM_INSTR_IMPL_A64__uqincp_z_p_z(Zdn, Pm, U, size);
#else
            RT_NOREF(Zdn, Pm, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04a0f400: UQINCW  <Wdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqincw_r_rs_uw, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqincw_r_rs_uw Rdn=%#x pattern=%#x imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqincw_r_rs_uw
        IEM_INSTR_IMPL_A64__uqincw_r_rs_uw(Rdn, pattern, imm4, size);
#else
        RT_NOREF(Rdn, pattern, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04b0f400: UQINCW  <Xdn>{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_pred_pattern_b, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqincw_r_rs_x, uint32_t, uOpcode)
{
    uint32_t const Rdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqincw_r_rs_x Rdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Rdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqincw_r_rs_x
        IEM_INSTR_IMPL_A64__uqincw_r_rs_x(Rdn, pattern, U, imm4, size);
#else
        RT_NOREF(Rdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc00/04a0c400: UQINCW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
   Instruction Set: A64  Groups: sve_int_countvlv0, sve_countelt, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqincw_z_zs, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const pattern    = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqincw_z_zs Zdn=%#x pattern=%#x U=%u imm4=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, pattern, U, imm4, size));
#ifdef IEM_INSTR_IMPL_A64__uqincw_z_zs
        IEM_INSTR_IMPL_A64__uqincw_z_zs(Zdn, pattern, U, imm4, size);
#else
        RT_NOREF(Zdn, pattern, U, imm4, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/440b8000: UQRSHL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_bin_pred_shift_sat_round, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqrshl_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x440b8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqrshl_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqrshl_z_p_zz
            IEM_INSTR_IMPL_A64__uqrshl_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/440f8000: UQRSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_bin_pred_shift_sat_round, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqrshlr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x440f8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqrshlr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqrshlr_z_p_zz
            IEM_INSTR_IMPL_A64__uqrshlr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc20/c1e0d420: UQRSHR  <Zd>.H, { <Zn1>.S-<Zn2>.S }, #<const>
   Instruction Set: A64  Groups: mortlach_multi2_qrshr, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_uqrshr_z_mz2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const U          = (uOpcode >>  5) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: uqrshr_z_mz2 Zd=%#x U=%u Zn=%#x imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn, imm4));
#ifdef IEM_INSTR_IMPL_A64__uqrshr_z_mz2
        IEM_INSTR_IMPL_A64__uqrshr_z_mz2(Zd, U, Zn, imm4);
#else
        RT_NOREF(Zd, U, Zn, imm4, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc60/c120d820: UQRSHR  <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const>
   Instruction Set: A64  Groups: mortlach_multi4_qrshr, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_uqrshr_z_mz4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc60)) == UINT32_C(0xc120d820))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const U          = (uOpcode >>  5) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const N          = (uOpcode >> 10) & 0x00000001;
        uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
        uint32_t const tsize      = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: uqrshr_z_mz4 Zd=%#x U=%u Zn=%u N=%u imm5=%#x tsize=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn, N, imm5, tsize));
#ifdef IEM_INSTR_IMPL_A64__uqrshr_z_mz4
            IEM_INSTR_IMPL_A64__uqrshr_z_mz4(Zd, U, Zn, N, imm5, tsize);
#else
            RT_NOREF(Zd, U, Zn, N, imm5, tsize, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0fc20/45b03800: UQRSHRN  <Zd>.H, { <Zn1>.S-<Zn2>.S }, #<const>
   Instruction Set: A64  Groups: sve_intx_multi_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqrshrn_z_mz2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc20)) == UINT32_C(0x45b03800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const imm4       = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: uqrshrn_z_mz2 Zd=%#x Zn=%#x U=%u imm4=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U, imm4));
#ifdef IEM_INSTR_IMPL_A64__uqrshrn_z_mz2
            IEM_INSTR_IMPL_A64__uqrshrn_z_mz2(Zd, Zn, U, imm4);
#else
            RT_NOREF(Zd, Zn, U, imm4, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc60/c120dc20: UQRSHRN  <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const>
   Instruction Set: A64  Groups: mortlach_multi4_qrshr, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_uqrshrn_z_mz4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const U          = (uOpcode >>  5) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const N          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm5       = (uOpcode >> 16) & 0x0000001f;
    uint32_t const tsize      = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: uqrshrn_z_mz4 Zd=%#x U=%u Zn=%u N=%u imm5=%#x tsize=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, U, Zn, N, imm5, tsize));
#ifdef IEM_INSTR_IMPL_A64__uqrshrn_z_mz4
        IEM_INSTR_IMPL_A64__uqrshrn_z_mz4(Zd, U, Zn, N, imm5, tsize);
#else
        RT_NOREF(Zd, U, Zn, N, imm5, tsize, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45203800: UQRSHRNB  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqrshrnb_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqrshrnb_z_zi Zd=%#x Zn=%#x T=%u U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__uqrshrnb_z_zi
        IEM_INSTR_IMPL_A64__uqrshrnb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45203c00: UQRSHRNT  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqrshrnt_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45203c00))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 12) & 0x00000001;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqrshrnt_z_zi Zd=%#x Zn=%#x T=%u U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__uqrshrnt_z_zi
            IEM_INSTR_IMPL_A64__uqrshrnt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, U, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/04078000: UQSHL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_0, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqshl_z_p_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04078000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >>  5) & 0x00000007;
        uint32_t const tszl       = (uOpcode >>  8) & 0x00000003;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqshl_z_p_zi Zdn=%#x imm3=%u tszl=%u Pg=%u U=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm3, tszl, Pg, U, tszh));
#ifdef IEM_INSTR_IMPL_A64__uqshl_z_p_zi
            IEM_INSTR_IMPL_A64__uqshl_z_p_zi(Zdn, imm3, tszl, Pg, U, tszh);
#else
            RT_NOREF(Zdn, imm3, tszl, Pg, U, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44098000: UQSHL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_bin_pred_shift_sat_round, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqshl_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44098000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqshl_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqshl_z_p_zz
            IEM_INSTR_IMPL_A64__uqshl_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/440d8000: UQSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_bin_pred_shift_sat_round, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqshlr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x440d8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqshlr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqshlr_z_p_zz
            IEM_INSTR_IMPL_A64__uqshlr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45203000: UQSHRNB  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqshrnb_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqshrnb_z_zi Zd=%#x Zn=%#x T=%u U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__uqshrnb_z_zi
        IEM_INSTR_IMPL_A64__uqshrnb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/45203400: UQSHRNT  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqshrnt_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 12) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqshrnt_z_zi Zd=%#x Zn=%#x T=%u U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__uqshrnt_z_zi
        IEM_INSTR_IMPL_A64__uqshrnt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/441b8000: UQSUB  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary_sat, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqsub_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x441b8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqsub_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqsub_z_p_zz
            IEM_INSTR_IMPL_A64__uqsub_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fc000/2527c000: UQSUB  <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
   Instruction Set: A64  Groups: sve_int_arith_imm0, sve_wideimm_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqsub_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fc000)) == UINT32_C(0x2527c000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm8       = (uOpcode >>  5) & 0x000000ff;
        uint32_t const sh         = (uOpcode >> 13) & 0x00000001;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqsub_z_zi Zdn=%#x imm8=%#x sh=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm8, sh, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqsub_z_zi
            IEM_INSTR_IMPL_A64__uqsub_z_zi(Zdn, imm8, sh, U, size);
#else
            RT_NOREF(Zdn, imm8, sh, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04201c00: UQSUB  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_bin_cons_arit_0, sve_int_unpred_arit, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqsub_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqsub_z_zz Zd=%#x Zn=%#x U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uqsub_z_zz
        IEM_INSTR_IMPL_A64__uqsub_z_zz(Zd, Zn, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/441f8000: UQSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary_sat, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqsubr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x441f8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uqsubr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uqsubr_z_p_zz
            IEM_INSTR_IMPL_A64__uqsubr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa7fc00/45204800: UQXTNB  <Zd>.<T>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_intx_extract_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqxtnb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqxtnb_z_zz Zd=%#x Zn=%#x T=%u U=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__uqxtnb_z_zz
        IEM_INSTR_IMPL_A64__uqxtnb_z_zz(Zd, Zn, T, U, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, U, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa7fc00/45204c00: UQXTNT  <Zd>.<T>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_intx_extract_narrow, sve_intx_narrowing, sve */
FNIEMOP_DEF_1(iemDecodeA64_uqxtnt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uqxtnt_z_zz Zd=%#x Zn=%#x T=%u U=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__uqxtnt_z_zz
        IEM_INSTR_IMPL_A64__uqxtnt_z_zz(Zd, Zn, T, U, tszl, tszh);
#else
        RT_NOREF(Zd, Zn, T, U, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4400a000: URECPE  <Zd>.S, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_intx_pred_arith_unary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_urecpe_z_p_z_m, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: urecpe_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__urecpe_z_p_z_m
        IEM_INSTR_IMPL_A64__urecpe_z_p_z_m(Zd, Zn, Pg, size);
#else
        RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4402a000: URECPE  <Zd>.S, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_intx_pred_arith_unary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_urecpe_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4402a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: urecpe_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__urecpe_z_p_z_z
            IEM_INSTR_IMPL_A64__urecpe_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44158000: URHADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_urhadd_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44158000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: urhadd_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__urhadd_z_p_zz
            IEM_INSTR_IMPL_A64__urhadd_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe1/c120a221: URSHL  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_shift_sm, mortlach_multi_sve_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_urshl_mz_zzv_2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a221))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: urshl_mz_zzv_2x1 U=%u Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__urshl_mz_zzv_2x1
            IEM_INSTR_IMPL_A64__urshl_mz_zzv_2x1(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30ffe3/c120aa21: URSHL  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi4_z_z_shift_sm, mortlach_multi_sve_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_urshl_mz_zzv_4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120aa21))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: urshl_mz_zzv_4x1 U=%u Zdn=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__urshl_mz_zzv_4x1
            IEM_INSTR_IMPL_A64__urshl_mz_zzv_4x1(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff21ffe1/c120b221: URSHL  { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
   Instruction Set: A64  Groups: mortlach_multi2_z_z_shift_mm, mortlach_multi_sve_2c0, sme */
FNIEMOP_DEF_1(iemDecodeA64_urshl_mz_zzw_2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b221))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  1) & 0x0000000f;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: urshl_mz_zzw_2x2 U=%u Zdn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__urshl_mz_zzw_2x2
            IEM_INSTR_IMPL_A64__urshl_mz_zzw_2x2(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff23ffe3/c120ba21: URSHL  { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_shift_mm, mortlach_multi_sve_2d0, sme */
FNIEMOP_DEF_1(iemDecodeA64_urshl_mz_zzw_4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120ba21))
    {
        uint32_t const U          = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zdn        = (uOpcode >>  2) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: urshl_mz_zzw_4x4 U=%u Zdn=%u Zm=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zdn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__urshl_mz_zzw_4x4
            IEM_INSTR_IMPL_A64__urshl_mz_zzw_4x4(U, Zdn, Zm, size);
#else
            RT_NOREF(U, Zdn, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44038000: URSHL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_bin_pred_shift_sat_round, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_urshl_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44038000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: urshl_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__urshl_z_p_zz
            IEM_INSTR_IMPL_A64__urshl_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/44078000: URSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_bin_pred_shift_sat_round, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_urshlr_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x44078000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: urshlr_z_p_zz Zdn=%#x Zm=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__urshlr_z_p_zz
            IEM_INSTR_IMPL_A64__urshlr_z_p_zz(Zdn, Zm, Pg, U, size);
#else
            RT_NOREF(Zdn, Zm, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/040d8000: URSHR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_bin_pred_shift_0, sve_int_pred_shift, sve */
FNIEMOP_DEF_1(iemDecodeA64_urshr_z_p_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x040d8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const imm3       = (uOpcode >>  5) & 0x00000007;
        uint32_t const tszl       = (uOpcode >>  8) & 0x00000003;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: urshr_z_p_zi Zdn=%#x imm3=%u tszl=%u Pg=%u U=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, imm3, tszl, Pg, U, tszh));
#ifdef IEM_INSTR_IMPL_A64__urshr_z_p_zi
            IEM_INSTR_IMPL_A64__urshr_z_p_zi(Zdn, imm3, tszl, Pg, U, tszh);
#else
            RT_NOREF(Zdn, imm3, tszl, Pg, U, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4401a000: URSQRTE  <Zd>.S, <Pg>/M, <Zn>.S
   Instruction Set: A64  Groups: sve_intx_pred_arith_unary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_ursqrte_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4401a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ursqrte_z_p_z_m Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__ursqrte_z_p_z_m
            IEM_INSTR_IMPL_A64__ursqrte_z_p_z_m(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/4403a000: URSQRTE  <Zd>.S, <Pg>/Z, <Zn>.S
   Instruction Set: A64  Groups: sve_intx_pred_arith_unary, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_ursqrte_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4403a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: ursqrte_z_p_z_z Zd=%#x Zn=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__ursqrte_z_p_z_z
            IEM_INSTR_IMPL_A64__ursqrte_z_p_z_z(Zd, Zn, Pg, size);
#else
            RT_NOREF(Zd, Zn, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500ec00: URSRA  <Zda>.<T>, <Zn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_intx_sra, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_ursra_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: ursra_z_zi Zda=%#x Zn=%#x U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__ursra_z_zi
        IEM_INSTR_IMPL_A64__ursra_z_zi(Zda, Zn, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zda, Zn, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44807800: USDOT  <Zda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_intx_mixed_dot, sve_intx_muladd_unpred, sve */
FNIEMOP_DEF_1(iemDecodeA64_usdot_z_zzz_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44807800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fI8mm /*FEAT_I8MM*/)
        {
            LogFlow(("%018x/%010x: usdot_z_zzz_s Zda=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__usdot_z_zzz_s
            IEM_INSTR_IMPL_A64__usdot_z_zzz_s(Zda, Zn, Zm);
#else
            RT_NOREF(Zda, Zn, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/44a01800: USDOT  <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
   Instruction Set: A64  Groups: sve_intx_mixed_dot_by_indexed_elem, sve_intx_by_indexed_elem, sve */
FNIEMOP_DEF_1(iemDecodeA64_usdot_z_zzzi_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44a01800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const U          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 19) & 0x00000003;
        if ((IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/) && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fI8mm /*FEAT_I8MM*/)
        {
            LogFlow(("%018x/%010x: usdot_z_zzzi_s Zda=%#x Zn=%#x U=%u Zm=%u i2=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, Zm, i2));
#ifdef IEM_INSTR_IMPL_A64__usdot_z_zzzi_s
            IEM_INSTR_IMPL_A64__usdot_z_zzzi_s(Zda, Zn, U, Zm, i2);
#else
            RT_NOREF(Zda, Zn, U, Zm, i2, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1501028: USDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_usdot_za_zzi_s2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1501028))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usdot_za_zzi_s2xi off3=%u U=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usdot_za_zzi_s2xi
            IEM_INSTR_IMPL_A64__usdot_za_zzi_s2xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1509028: USDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_usdot_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1509028))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usdot_za_zzi_s4xi off3=%u U=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usdot_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__usdot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1201408: USDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi2_z_za_mixed_dot_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_usdot_za_zzv_s2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1201408))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usdot_za_zzv_s2x1 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usdot_za_zzv_s2x1
            IEM_INSTR_IMPL_A64__usdot_za_zzv_s2x1(off3, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c18/c1301408: USDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi4_z_za_mixed_dot_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_usdot_za_zzv_s4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1301408))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usdot_za_zzv_s4x1 off3=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usdot_za_zzv_s4x1
            IEM_INSTR_IMPL_A64__usdot_za_zzv_s4x1(off3, U, Zn, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c38/c1a01408: USDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_multi2_z_za_mixed_dot_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_usdot_za_zzw_s2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c38)) == UINT32_C(0xc1a01408))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usdot_za_zzw_s2x2 off3=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usdot_za_zzw_s2x2
            IEM_INSTR_IMPL_A64__usdot_za_zzw_s2x2(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c78/c1a11408: USDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B }
   Instruction Set: A64  Groups: mortlach_multi4_z_za_mixed_dot_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_usdot_za_zzw_s4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c78)) == UINT32_C(0xc1a11408))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usdot_za_zzw_s4x4 off3=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usdot_za_zzw_s4x4
            IEM_INSTR_IMPL_A64__usdot_za_zzw_s4x4(off3, Zn, Rv, Zm);
#else
            RT_NOREF(off3, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/4500a800: USHLLB  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_long, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_ushllb_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x4500a800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ushllb_z_zi Zd=%#x Zn=%#x T=%u U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__ushllb_z_zi
            IEM_INSTR_IMPL_A64__ushllb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, U, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffa0fc00/4500ac00: USHLLT  <Zd>.<T>, <Zn>.<Tb>, #<const>
   Instruction Set: A64  Groups: sve_intx_shift_long, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_ushllt_z_zi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x4500ac00))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const T          = (uOpcode >> 10) & 0x00000001;
        uint32_t const U          = (uOpcode >> 11) & 0x00000001;
        uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
        uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
        uint32_t const tszh       = (uOpcode >> 22) & 0x00000001;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: ushllt_z_zi Zd=%#x Zn=%#x T=%u U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__ushllt_z_zi
            IEM_INSTR_IMPL_A64__ushllt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh);
#else
            RT_NOREF(Zd, Zn, T, U, imm3, tszl, tszh, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff0001c/c1000004: USMLALL  ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi1_mla_long_long_idx_s, mortlach_multi_indexed_1, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmlall_za_zzi_s, uint32_t, uOpcode)
{
    uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
    uint32_t const U          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const i4l        = (uOpcode >> 10) & 0x00000007;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const i4h        = (uOpcode >> 15) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: usmlall_za_zzi_s off2=%u U=%u Zn=%#x i4l=%u Rv=%u i4h=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, U, Zn, i4l, Rv, i4h, Zm));
#ifdef IEM_INSTR_IMPL_A64__usmlall_za_zzi_s
        IEM_INSTR_IMPL_A64__usmlall_za_zzi_s(off2, U, Zn, i4l, Rv, i4h, Zm);
#else
        RT_NOREF(off2, U, Zn, i4l, Rv, i4h, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1100020: USMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_mla_long_long_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmlall_za_zzi_s2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1100020))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usmlall_za_zzi_s2xi o1=%u i4l=%u U=%u Zn=%#x i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, U, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usmlall_za_zzi_s2xi
            IEM_INSTR_IMPL_A64__usmlall_za_zzi_s2xi(o1, i4l, U, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, U, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1108020: USMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_mla_long_long_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmlall_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1108020))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const i4l        = (uOpcode >>  1) & 0x00000003;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i4h        = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usmlall_za_zzi_s4xi o1=%u i4l=%u U=%u Zn=%u i4h=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, i4l, U, Zn, i4h, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usmlall_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__usmlall_za_zzi_s4xi(o1, i4l, U, Zn, i4h, Rv, Zm);
#else
            RT_NOREF(o1, i4l, U, Zn, i4h, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1c/c1200404: USMLALL  ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi1_zz_za_mla_long_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmlall_za_zzv_s, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1c)) == UINT32_C(0xc1200404))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usmlall_za_zzv_s off2=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usmlall_za_zzv_s
            IEM_INSTR_IMPL_A64__usmlall_za_zzv_s(off2, Zn, Rv, Zm);
#else
            RT_NOREF(off2, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1e/c1200004: USMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_long_sm, mortlach_multi_array_1a, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmlall_za_zzv_s2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1e)) == UINT32_C(0xc1200004))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usmlall_za_zzv_s2x1 o1=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usmlall_za_zzv_s2x1
            IEM_INSTR_IMPL_A64__usmlall_za_zzv_s2x1(o1, U, Zn, Rv, Zm);
#else
            RT_NOREF(o1, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09c1e/c1300004: USMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_long_sm, mortlach_multi_array_1b, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmlall_za_zzv_s4x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c1e)) == UINT32_C(0xc1300004))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usmlall_za_zzv_s4x1 o1=%u U=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, U, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usmlall_za_zzv_s4x1
            IEM_INSTR_IMPL_A64__usmlall_za_zzv_s4x1(o1, U, Zn, Rv, Zm);
#else
            RT_NOREF(o1, U, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe19c3e/c1a00004: USMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_multi2_zz_za_mla_long_long_mm, mortlach_multi_array_2a, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmlall_za_zzw_s2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe19c3e)) == UINT32_C(0xc1a00004))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 17) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usmlall_za_zzw_s2x2 o1=%u Zn=%#x Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usmlall_za_zzw_s2x2
            IEM_INSTR_IMPL_A64__usmlall_za_zzw_s2x2(o1, Zn, Rv, Zm);
#else
            RT_NOREF(o1, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe39c7e/c1a10004: USMLALL  ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B }
   Instruction Set: A64  Groups: mortlach_multi4_zz_za_mla_long_long_mm, mortlach_multi_array_2b, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmlall_za_zzw_s4x4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe39c7e)) == UINT32_C(0xc1a10004))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 18) & 0x00000007;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usmlall_za_zzw_s4x4 o1=%u Zn=%u Rv=%u Zm=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, Zn, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usmlall_za_zzw_s4x4
            IEM_INSTR_IMPL_A64__usmlall_za_zzw_s4x4(o1, Zn, Rv, Zm);
#else
            RT_NOREF(o1, Zn, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/45809800: USMMLA  <Zda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: sve_intx_mmla, sve_intx_constructive, sve */
FNIEMOP_DEF_1(iemDecodeA64_usmmla_z_zzz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x45809800))
    {
        uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const uns        = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fI8mm /*FEAT_I8MM*/)
        {
            LogFlow(("%018x/%010x: usmmla_z_zzz Zda=%#x Zn=%#x Zm=%#x uns=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, Zm, uns));
#ifdef IEM_INSTR_IMPL_A64__usmmla_z_zzz
            IEM_INSTR_IMPL_A64__usmmla_z_zzz(Zda, Zn, Zm, uns);
#else
            RT_NOREF(Zda, Zn, Zm, uns, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81008000: USMOP4A  <ZAda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4a_za_zz_b1x1, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
    uint32_t const N          = (uOpcode >>  9) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
    uint32_t const M          = (uOpcode >> 20) & 0x00000001;
    if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
    {
        LogFlow(("%018x/%010x: usmop4a_za_zz_b1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4a_za_zz_b1x1
        IEM_INSTR_IMPL_A64__usmop4a_za_zz_b1x1(ZAda, Zn, N, Zm, M);
#else
        RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81108000: USMOP4A  <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4a_za_zz_b1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81108000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: usmop4a_za_zz_b1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4a_za_zz_b1x2
            IEM_INSTR_IMPL_A64__usmop4a_za_zz_b1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81008200: USMOP4A  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4a_za_zz_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81008200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: usmop4a_za_zz_b2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4a_za_zz_b2x1
            IEM_INSTR_IMPL_A64__usmop4a_za_zz_b2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81108200: USMOP4A  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4a_za_zz_b2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81108200))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: usmop4a_za_zz_b2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4a_za_zz_b2x2
            IEM_INSTR_IMPL_A64__usmop4a_za_zz_b2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1c00008: USMOP4A  <ZAda>.D, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4a_za_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1c00008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: usmop4a_za_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4a_za_zz_h1x1
            IEM_INSTR_IMPL_A64__usmop4a_za_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1d00008: USMOP4A  <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4a_za_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1d00008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: usmop4a_za_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4a_za_zz_h1x2
            IEM_INSTR_IMPL_A64__usmop4a_za_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1c00208: USMOP4A  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4a_za_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1c00208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: usmop4a_za_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4a_za_zz_h2x1
            IEM_INSTR_IMPL_A64__usmop4a_za_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1d00208: USMOP4A  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4a_za_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1d00208))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: usmop4a_za_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4a_za_zz_h2x2
            IEM_INSTR_IMPL_A64__usmop4a_za_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81008010: USMOP4S  <ZAda>.S, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4s_za_zz_b1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81008010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: usmop4s_za_zz_b1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4s_za_zz_b1x1
            IEM_INSTR_IMPL_A64__usmop4s_za_zz_b1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81108010: USMOP4S  <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4s_za_zz_b1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81108010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: usmop4s_za_zz_b1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4s_za_zz_b1x2
            IEM_INSTR_IMPL_A64__usmop4s_za_zz_b1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81008210: USMOP4S  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4s_za_zz_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81008210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: usmop4s_za_zz_b2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4s_za_zz_b2x1
            IEM_INSTR_IMPL_A64__usmop4s_za_zz_b2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe3c/81108210: USMOP4S  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }
   Instruction Set: A64  Groups: mortlach_i8i32_prod4, mortlach2_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4s_za_zz_b2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81108210))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/)
        {
            LogFlow(("%018x/%010x: usmop4s_za_zz_b2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4s_za_zz_b2x2
            IEM_INSTR_IMPL_A64__usmop4s_za_zz_b2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1c00018: USMOP4S  <ZAda>.D, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4s_za_zz_h1x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1c00018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: usmop4s_za_zz_h1x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4s_za_zz_h1x1
            IEM_INSTR_IMPL_A64__usmop4s_za_zz_h1x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1d00018: USMOP4S  <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4s_za_zz_h1x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1d00018))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: usmop4s_za_zz_h1x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4s_za_zz_h1x2
            IEM_INSTR_IMPL_A64__usmop4s_za_zz_h1x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1c00218: USMOP4S  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4s_za_zz_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1c00218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: usmop4s_za_zz_h2x1 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4s_za_zz_h2x1
            IEM_INSTR_IMPL_A64__usmop4s_za_zz_h2x1(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff1fe38/a1d00218: USMOP4S  <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }
   Instruction Set: A64  Groups: mortlach_i16i64_prod4, mortlach2_64bit_prod4, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmop4s_za_zz_h2x2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1d00218))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  6) & 0x00000007;
        uint32_t const N          = (uOpcode >>  9) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 17) & 0x00000007;
        uint32_t const M          = (uOpcode >> 20) & 0x00000001;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_MOP4*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: usmop4s_za_zz_h2x2 ZAda=%u Zn=%u N=%u Zm=%u M=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, N, Zm, M));
#ifdef IEM_INSTR_IMPL_A64__usmop4s_za_zz_h2x2
            IEM_INSTR_IMPL_A64__usmop4s_za_zz_h2x2(ZAda, Zn, N, Zm, M);
#else
            RT_NOREF(ZAda, Zn, N, Zm, M, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/a1800000: USMOPA  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod, mortlach_32bit_int_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmopa_za_pp_zz_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: usmopa_za_pp_zz_32 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__usmopa_za_pp_zz_32
        IEM_INSTR_IMPL_A64__usmopa_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00018/a1c00000: USMOPA  <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod, mortlach_64bit_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmopa_za_pp_zz_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00018)) == UINT32_C(0xa1c00000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: usmopa_za_pp_zz_64 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__usmopa_za_pp_zz_64
            IEM_INSTR_IMPL_A64__usmopa_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0001c/a1800010: USMOPS  <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B
   Instruction Set: A64  Groups: mortlach_i8i32_prod, mortlach_32bit_int_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmops_za_pp_zz_32, uint32_t, uOpcode)
{
    uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
    uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: usmops_za_pp_zz_32 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__usmops_za_pp_zz_32
        IEM_INSTR_IMPL_A64__usmops_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm);
#else
        RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe00018/a1c00010: USMOPS  <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H
   Instruction Set: A64  Groups: mortlach_i16i64_prod, mortlach_64bit_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_usmops_za_pp_zz_64, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00018)) == UINT32_C(0xa1c00010))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pn         = (uOpcode >> 10) & 0x00000007;
        uint32_t const Pm         = (uOpcode >> 13) & 0x00000007;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
        {
            LogFlow(("%018x/%010x: usmops_za_pp_zz_64 ZAda=%u Zn=%#x Pn=%u Pm=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, Zn, Pn, Pm, Zm));
#ifdef IEM_INSTR_IMPL_A64__usmops_za_pp_zz_64
            IEM_INSTR_IMPL_A64__usmops_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm);
#else
            RT_NOREF(ZAda, Zn, Pn, Pm, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/441d8000: USQADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_intx_pred_arith_binary_sat, sve_intx_predicated, sve */
FNIEMOP_DEF_1(iemDecodeA64_usqadd_z_p_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x441d8000))
    {
        uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: usqadd_z_p_zz Zdn=%#x Zm=%#x Pg=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, Pg, size));
#ifdef IEM_INSTR_IMPL_A64__usqadd_z_p_zz
            IEM_INSTR_IMPL_A64__usqadd_z_p_zz(Zdn, Zm, Pg, size);
#else
            RT_NOREF(Zdn, Zm, Pg, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4500e400: USRA  <Zda>.<T>, <Zn>.<T>, #<const>
   Instruction Set: A64  Groups: sve_intx_sra, sve_intx_acc, sve */
FNIEMOP_DEF_1(iemDecodeA64_usra_z_zi, uint32_t, uOpcode)
{
    uint32_t const Zda        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const U          = (uOpcode >> 10) & 0x00000001;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: usra_z_zi Zda=%#x Zn=%#x U=%u imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zda, Zn, U, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__usra_z_zi
        IEM_INSTR_IMPL_A64__usra_z_zi(Zda, Zn, U, imm3, tszl, tszh);
#else
        RT_NOREF(Zda, Zn, U, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/81408000: USTMOPA  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_i8i32_2in4ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_ustmopa_za_zzzi_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0x81408000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
        uint32_t const K          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
        {
            LogFlow(("%018x/%010x: ustmopa_za_zzzi_b2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__ustmopa_za_zzzi_b2x1
            IEM_INSTR_IMPL_A64__ustmopa_za_zzzi_b2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
            RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45001800: USUBLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_usublb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: usublb_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__usublb_z_zz
        IEM_INSTR_IMPL_A64__usublb_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45001c00: USUBLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_long, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_usublt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: usublt_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__usublt_z_zz
        IEM_INSTR_IMPL_A64__usublt_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45005800: USUBWB  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_wide, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_usubwb_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: usubwb_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__usubwb_z_zz
        IEM_INSTR_IMPL_A64__usubwb_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/45005c00: USUBWT  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
   Instruction Set: A64  Groups: sve_intx_cons_arith_wide, sve_intx_cons_widening, sve */
FNIEMOP_DEF_1(iemDecodeA64_usubwt_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const T          = (uOpcode >> 10) & 0x00000001;
    uint32_t const U          = (uOpcode >> 11) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: usubwt_z_zz Zd=%#x Zn=%#x T=%u U=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, T, U, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__usubwt_z_zz
        IEM_INSTR_IMPL_A64__usubwt_z_zz(Zd, Zn, T, U, Zm, size);
#else
        RT_NOREF(Zd, Zn, T, U, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1508028: USVDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_usvdot_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1508028))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: usvdot_za_zzi_s4xi off3=%u U=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__usvdot_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__usvdot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/81408008: UTMOPA  <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_i16i32_2in4ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_utmopa_za32_zzzi_h2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0x81408008))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
        uint32_t const K          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
        {
            LogFlow(("%018x/%010x: utmopa_za32_zzzi_h2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__utmopa_za32_zzzi_h2x1
            IEM_INSTR_IMPL_A64__utmopa_za32_zzzi_h2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
            RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0e00c/81608000: UTMOPA  <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B, <Zk>[<index>]
   Instruction Set: A64  Groups: mortlach_i8i32_2in4ss_prod, mortlach2_ss_prod, sme */
FNIEMOP_DEF_1(iemDecodeA64_utmopa_za_zzzi_b2x1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0x81608000))
    {
        uint32_t const ZAda       = (uOpcode >>  0) & 0x00000003;
        uint32_t const i2         = (uOpcode >>  4) & 0x00000003;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const Zk         = (uOpcode >> 10) & 0x00000003;
        uint32_t const K          = (uOpcode >> 12) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME_TMOP*/)
        {
            LogFlow(("%018x/%010x: utmopa_za_zzzi_b2x1 ZAda=%u i2=%u Zn=%#x Zk=%u K=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, ZAda, i2, Zn, Zk, K, Zm));
#ifdef IEM_INSTR_IMPL_A64__utmopa_za_zzzi_b2x1
            IEM_INSTR_IMPL_A64__utmopa_za_zzzi_b2x1(ZAda, i2, Zn, Zk, K, Zm);
#else
            RT_NOREF(ZAda, i2, Zn, Zk, K, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc01/c125e001: UUNPK  { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<Tb>
   Instruction Set: A64  Groups: mortlach_multi2_wide_int, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_uunpk_mz_z_2, uint32_t, uOpcode)
{
    uint32_t const U          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: uunpk_mz_z_2 U=%u Zd=%#x Zn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zd, Zn, size));
#ifdef IEM_INSTR_IMPL_A64__uunpk_mz_z_2
        IEM_INSTR_IMPL_A64__uunpk_mz_z_2(U, Zd, Zn, size);
#else
        RT_NOREF(U, Zd, Zn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc23/c135e001: UUNPK  { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<Tb>-<Zn2>.<Tb> }
   Instruction Set: A64  Groups: mortlach_multi4_wide_int, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_uunpk_mz_z_4, uint32_t, uOpcode)
{
    uint32_t const U          = (uOpcode >>  0) & 0x00000001;
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: uunpk_mz_z_4 U=%u Zd=%u Zn=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, U, Zd, Zn, size));
#ifdef IEM_INSTR_IMPL_A64__uunpk_mz_z_4
        IEM_INSTR_IMPL_A64__uunpk_mz_z_4(U, Zd, Zn, size);
#else
        RT_NOREF(U, Zd, Zn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/05333800: UUNPKHI  <Zd>.<T>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_int_perm_unpk, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_uunpkhi_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x05333800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 16) & 0x00000001;
        uint32_t const U          = (uOpcode >> 17) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uunpkhi_z_z Zd=%#x Zn=%#x H=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, U, size));
#ifdef IEM_INSTR_IMPL_A64__uunpkhi_z_z
            IEM_INSTR_IMPL_A64__uunpkhi_z_z(Zd, Zn, H, U, size);
#else
            RT_NOREF(Zd, Zn, H, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc00/05323800: UUNPKLO  <Zd>.<T>, <Zn>.<Tb>
   Instruction Set: A64  Groups: sve_int_perm_unpk, sve_perm_unpred_d, sve */
FNIEMOP_DEF_1(iemDecodeA64_uunpklo_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x05323800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 16) & 0x00000001;
        uint32_t const U          = (uOpcode >> 17) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uunpklo_z_z Zd=%#x Zn=%#x H=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, U, size));
#ifdef IEM_INSTR_IMPL_A64__uunpklo_z_z
            IEM_INSTR_IMPL_A64__uunpklo_z_z(Zd, Zn, H, U, size);
#else
            RT_NOREF(Zd, Zn, H, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09038/c1500030: UVDOT  ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi2_zza_idx_s, mortlach_multi_indexed_2, sme */
FNIEMOP_DEF_1(iemDecodeA64_uvdot_za32_zzi_2xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1500030))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  6) & 0x0000000f;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: uvdot_za32_zzi_2xi off3=%u U=%u Zn=%#x i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__uvdot_za32_zzi_2xi
            IEM_INSTR_IMPL_A64__uvdot_za32_zzi_2xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09878/c1d08818: UVDOT  ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_d, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_uvdot_za_zzi_d4xi, uint32_t, uOpcode)
{
    uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
    uint32_t const U          = (uOpcode >>  4) & 0x00000001;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const i1         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSmeI16I64 /*FEAT_SME_I16I64*/)
    {
        LogFlow(("%018x/%010x: uvdot_za_zzi_d4xi off3=%u U=%u Zn=%u i1=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i1, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__uvdot_za_zzi_d4xi
        IEM_INSTR_IMPL_A64__uvdot_za_zzi_d4xi(off3, U, Zn, i1, Rv, Zm);
#else
        RT_NOREF(off3, U, Zn, i1, Rv, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fff09078/c1508030: UVDOT  ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]
   Instruction Set: A64  Groups: mortlach_multi4_zza_idx_s, mortlach_multi_indexed_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_uvdot_za_zzi_s4xi, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1508030))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const U          = (uOpcode >>  4) & 0x00000001;
        uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
        uint32_t const i2         = (uOpcode >> 10) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000000f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: uvdot_za_zzi_s4xi off3=%u U=%u Zn=%u i2=%u Rv=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, U, Zn, i2, Rv, Zm));
#ifdef IEM_INSTR_IMPL_A64__uvdot_za_zzi_s4xi
            IEM_INSTR_IMPL_A64__uvdot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm);
#else
            RT_NOREF(off3, U, Zn, i2, Rv, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0411a000: UXTB  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_uxtb_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0411a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uxtb_z_p_z_m Zd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uxtb_z_p_z_m
            IEM_INSTR_IMPL_A64__uxtb_z_p_z_m(Zd, Zn, Pg, U, size);
#else
            RT_NOREF(Zd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0401a000: UXTB  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_uxtb_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0401a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: uxtb_z_p_z_z Zd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uxtb_z_p_z_z
            IEM_INSTR_IMPL_A64__uxtb_z_p_z_z(Zd, Zn, Pg, U, size);
#else
            RT_NOREF(Zd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0413a000: UXTH  <Zd>.<T>, <Pg>/M, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_uxth_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0413a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uxth_z_p_z_m Zd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uxth_z_p_z_m
            IEM_INSTR_IMPL_A64__uxth_z_p_z_m(Zd, Zn, Pg, U, size);
#else
            RT_NOREF(Zd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0403a000: UXTH  <Zd>.<T>, <Pg>/Z, <Zn>.<T>
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_uxth_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0403a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: uxth_z_p_z_z Zd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uxth_z_p_z_z
            IEM_INSTR_IMPL_A64__uxth_z_p_z_z(Zd, Zn, Pg, U, size);
#else
            RT_NOREF(Zd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0415a000: UXTW  <Zd>.D, <Pg>/M, <Zn>.D
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_uxtw_z_p_z_m, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0415a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uxtw_z_p_z_m Zd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uxtw_z_p_z_m
            IEM_INSTR_IMPL_A64__uxtw_z_p_z_m(Zd, Zn, Pg, U, size);
#else
            RT_NOREF(Zd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3fe000/0405a000: UXTW  <Zd>.D, <Pg>/Z, <Zn>.D
   Instruction Set: A64  Groups: sve_int_un_pred_arit_0, sve_int_pred_un, sve */
FNIEMOP_DEF_1(iemDecodeA64_uxtw_z_p_z_z, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0405a000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Pg         = (uOpcode >> 10) & 0x00000007;
        uint32_t const U          = (uOpcode >> 16) & 0x00000001;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SVE2p2*/ || false /** @todo IEM_GET_GUEST_CPU_FEATURES(pVCpu)->FEAT_SME2p2*/)
        {
            LogFlow(("%018x/%010x: uxtw_z_p_z_z Zd=%#x Zn=%#x Pg=%u U=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Pg, U, size));
#ifdef IEM_INSTR_IMPL_A64__uxtw_z_p_z_z
            IEM_INSTR_IMPL_A64__uxtw_z_p_z_z(Zd, Zn, Pg, U, size);
#else
            RT_NOREF(Zd, Zn, Pg, U, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30fe10/05204800: UZP1  <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_bin_perm_pp, sve_perm_predicates, sve */
FNIEMOP_DEF_1(iemDecodeA64_uzp1_p_pp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30fe10)) == UINT32_C(0x05204800))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const H          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uzp1_p_pp Pd=%#x Pn=%#x H=%u Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, H, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__uzp1_p_pp
            IEM_INSTR_IMPL_A64__uzp1_p_pp(Pd, Pn, H, Pm, size);
#else
            RT_NOREF(Pd, Pn, H, Pm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/05206800: UZP1  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_bin_perm_zz, sve_perm_inter, sve */
FNIEMOP_DEF_1(iemDecodeA64_uzp1_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x05206800))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: uzp1_z_zz Zd=%#x Zn=%#x H=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uzp1_z_zz
            IEM_INSTR_IMPL_A64__uzp1_z_zz(Zd, Zn, H, Zm, size);
#else
            RT_NOREF(Zd, Zn, H, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/05a00800: UZP1  <Zd>.Q, <Zn>.Q, <Zm>.Q
   Instruction Set: A64  Groups: sve_int_perm_bin_long_perm_zz, sve_perm_inter_long, sve */
FNIEMOP_DEF_1(iemDecodeA64_uzp1_z_zz_q, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
    {
        LogFlow(("%018x/%010x: uzp1_z_zz_q Zd=%#x Zn=%#x H=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm));
#ifdef IEM_INSTR_IMPL_A64__uzp1_z_zz_q
        IEM_INSTR_IMPL_A64__uzp1_z_zz_q(Zd, Zn, H, Zm);
#else
        RT_NOREF(Zd, Zn, H, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30fe10/05204c00: UZP2  <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_bin_perm_pp, sve_perm_predicates, sve */
FNIEMOP_DEF_1(iemDecodeA64_uzp2_p_pp, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uzp2_p_pp Pd=%#x Pn=%#x H=%u Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, H, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__uzp2_p_pp
        IEM_INSTR_IMPL_A64__uzp2_p_pp(Pd, Pn, H, Pm, size);
#else
        RT_NOREF(Pd, Pn, H, Pm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/05206c00: UZP2  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_bin_perm_zz, sve_perm_inter, sve */
FNIEMOP_DEF_1(iemDecodeA64_uzp2_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: uzp2_z_zz Zd=%#x Zn=%#x H=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uzp2_z_zz
        IEM_INSTR_IMPL_A64__uzp2_z_zz(Zd, Zn, H, Zm, size);
#else
        RT_NOREF(Zd, Zn, H, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/05a00c00: UZP2  <Zd>.Q, <Zn>.Q, <Zm>.Q
   Instruction Set: A64  Groups: sve_int_perm_bin_long_perm_zz, sve_perm_inter_long, sve */
FNIEMOP_DEF_1(iemDecodeA64_uzp2_z_zz_q, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
    {
        LogFlow(("%018x/%010x: uzp2_z_zz_q Zd=%#x Zn=%#x H=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm));
#ifdef IEM_INSTR_IMPL_A64__uzp2_z_zz_q
        IEM_INSTR_IMPL_A64__uzp2_z_zz_q(Zd, Zn, H, Zm);
#else
        RT_NOREF(Zd, Zn, H, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc63/c136e002: UZP  { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<T>-<Zn4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_zip, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_uzp_mz_z_4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: uzp_mz_z_4 Zd=%u Zn=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size));
#ifdef IEM_INSTR_IMPL_A64__uzp_mz_z_4
        IEM_INSTR_IMPL_A64__uzp_mz_z_4(Zd, Zn, size);
#else
        RT_NOREF(Zd, Zn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc63/c137e002: UZP  { <Zd1>.Q-<Zd4>.Q }, { <Zn1>.Q-<Zn4>.Q }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_long_zip, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_uzp_mz_z_4q, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: uzp_mz_z_4q Zd=%u Zn=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__uzp_mz_z_4q
        IEM_INSTR_IMPL_A64__uzp_mz_z_4q(Zd, Zn);
#else
        RT_NOREF(Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc01/c120d001: UZP  { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_zip, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_uzp_mz_zz_2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: uzp_mz_zz_2 Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uzp_mz_zz_2
        IEM_INSTR_IMPL_A64__uzp_mz_zz_2(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc01/c120d401: UZP  { <Zd1>.Q-<Zd2>.Q }, <Zn>.Q, <Zm>.Q
   Instruction Set: A64  Groups: mortlach_multi2_z_z_long_zip, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_uzp_mz_zz_2q, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: uzp_mz_zz_2q Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__uzp_mz_zz_2q
        IEM_INSTR_IMPL_A64__uzp_mz_zz_2q(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4400e800: UZPQ1  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_binquads, sve_perm_quads_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_uzpq1_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: uzpq1_z_zz Zd=%#x Zn=%#x H=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uzpq1_z_zz
        IEM_INSTR_IMPL_A64__uzpq1_z_zz(Zd, Zn, H, Zm, size);
#else
        RT_NOREF(Zd, Zn, H, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4400ec00: UZPQ2  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_binquads, sve_perm_quads_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_uzpq2_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: uzpq2_z_zz Zd=%#x Zn=%#x H=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__uzpq2_z_zz
        IEM_INSTR_IMPL_A64__uzpq2_z_zz(Zd, Zn, H, Zm, size);
#else
        RT_NOREF(Zd, Zn, H, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20ec10/25200000: WHILEGE  <Pd>.<T>, <R><n>, <R><m>
   Instruction Set: A64  Groups: sve_int_while_rr, sve_cmpgpr, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilege_p_p_rr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20ec10)) == UINT32_C(0x25200000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const eq         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
        uint32_t const sf         = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: whilege_p_p_rr Pd=%#x eq=%u Rn=%#x lt=%u sf=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, eq, Rn, lt, sf, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilege_p_p_rr
            IEM_INSTR_IMPL_A64__whilege_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size);
#else
            RT_NOREF(Pd, eq, Rn, lt, sf, Rm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20dc18/25204010: WHILEGE  <PNd>.<T>, <Xn>, <Xm>, <vl>
   Instruction Set: A64  Groups: sve_int_while_rr_pn, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilege_pn_rr, uint32_t, uOpcode)
{
    uint32_t const PNd        = (uOpcode >>  0) & 0x00000007;
    uint32_t const eq         = (uOpcode >>  3) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const vl         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilege_pn_rr PNd=%u eq=%u Rn=%#x lt=%u vl=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, PNd, eq, Rn, lt, vl, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilege_pn_rr
        IEM_INSTR_IMPL_A64__whilege_pn_rr(PNd, eq, Rn, lt, vl, Rm, size);
#else
        RT_NOREF(PNd, eq, Rn, lt, vl, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc11/25205010: WHILEGE  { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm>
   Instruction Set: A64  Groups: sve_int_while_rr_pair, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilege_pp_rr, uint32_t, uOpcode)
{
    uint32_t const eq         = (uOpcode >>  0) & 0x00000001;
    uint32_t const Pd         = (uOpcode >>  1) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilege_pp_rr eq=%u Pd=%u Rn=%#x lt=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, eq, Pd, Rn, lt, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilege_pp_rr
        IEM_INSTR_IMPL_A64__whilege_pp_rr(eq, Pd, Rn, lt, Rm, size);
#else
        RT_NOREF(eq, Pd, Rn, lt, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20ec10/25200010: WHILEGT  <Pd>.<T>, <R><n>, <R><m>
   Instruction Set: A64  Groups: sve_int_while_rr, sve_cmpgpr, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilegt_p_p_rr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20ec10)) == UINT32_C(0x25200010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const eq         = (uOpcode >>  4) & 0x00000001;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
        uint32_t const sf         = (uOpcode >> 12) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: whilegt_p_p_rr Pd=%#x eq=%u Rn=%#x lt=%u sf=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, eq, Rn, lt, sf, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilegt_p_p_rr
            IEM_INSTR_IMPL_A64__whilegt_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size);
#else
            RT_NOREF(Pd, eq, Rn, lt, sf, Rm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20dc18/25204018: WHILEGT  <PNd>.<T>, <Xn>, <Xm>, <vl>
   Instruction Set: A64  Groups: sve_int_while_rr_pn, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilegt_pn_rr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20dc18)) == UINT32_C(0x25204018))
    {
        uint32_t const PNd        = (uOpcode >>  0) & 0x00000007;
        uint32_t const eq         = (uOpcode >>  3) & 0x00000001;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
        uint32_t const vl         = (uOpcode >> 13) & 0x00000001;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
        {
            LogFlow(("%018x/%010x: whilegt_pn_rr PNd=%u eq=%u Rn=%#x lt=%u vl=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, PNd, eq, Rn, lt, vl, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilegt_pn_rr
            IEM_INSTR_IMPL_A64__whilegt_pn_rr(PNd, eq, Rn, lt, vl, Rm, size);
#else
            RT_NOREF(PNd, eq, Rn, lt, vl, Rm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc11/25205011: WHILEGT  { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm>
   Instruction Set: A64  Groups: sve_int_while_rr_pair, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilegt_pp_rr, uint32_t, uOpcode)
{
    uint32_t const eq         = (uOpcode >>  0) & 0x00000001;
    uint32_t const Pd         = (uOpcode >>  1) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilegt_pp_rr eq=%u Pd=%u Rn=%#x lt=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, eq, Pd, Rn, lt, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilegt_pp_rr
        IEM_INSTR_IMPL_A64__whilegt_pp_rr(eq, Pd, Rn, lt, Rm, size);
#else
        RT_NOREF(eq, Pd, Rn, lt, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20ec10/25200810: WHILEHI  <Pd>.<T>, <R><n>, <R><m>
   Instruction Set: A64  Groups: sve_int_while_rr, sve_cmpgpr, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilehi_p_p_rr, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const eq         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const sf         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: whilehi_p_p_rr Pd=%#x eq=%u Rn=%#x lt=%u sf=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, eq, Rn, lt, sf, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilehi_p_p_rr
        IEM_INSTR_IMPL_A64__whilehi_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size);
#else
        RT_NOREF(Pd, eq, Rn, lt, sf, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20dc18/25204818: WHILEHI  <PNd>.<T>, <Xn>, <Xm>, <vl>
   Instruction Set: A64  Groups: sve_int_while_rr_pn, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilehi_pn_rr, uint32_t, uOpcode)
{
    uint32_t const PNd        = (uOpcode >>  0) & 0x00000007;
    uint32_t const eq         = (uOpcode >>  3) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const vl         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilehi_pn_rr PNd=%u eq=%u Rn=%#x lt=%u vl=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, PNd, eq, Rn, lt, vl, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilehi_pn_rr
        IEM_INSTR_IMPL_A64__whilehi_pn_rr(PNd, eq, Rn, lt, vl, Rm, size);
#else
        RT_NOREF(PNd, eq, Rn, lt, vl, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc11/25205811: WHILEHI  { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm>
   Instruction Set: A64  Groups: sve_int_while_rr_pair, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilehi_pp_rr, uint32_t, uOpcode)
{
    uint32_t const eq         = (uOpcode >>  0) & 0x00000001;
    uint32_t const Pd         = (uOpcode >>  1) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilehi_pp_rr eq=%u Pd=%u Rn=%#x lt=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, eq, Pd, Rn, lt, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilehi_pp_rr
        IEM_INSTR_IMPL_A64__whilehi_pp_rr(eq, Pd, Rn, lt, Rm, size);
#else
        RT_NOREF(eq, Pd, Rn, lt, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20ec10/25200800: WHILEHS  <Pd>.<T>, <R><n>, <R><m>
   Instruction Set: A64  Groups: sve_int_while_rr, sve_cmpgpr, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilehs_p_p_rr, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const eq         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const sf         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: whilehs_p_p_rr Pd=%#x eq=%u Rn=%#x lt=%u sf=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, eq, Rn, lt, sf, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilehs_p_p_rr
        IEM_INSTR_IMPL_A64__whilehs_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size);
#else
        RT_NOREF(Pd, eq, Rn, lt, sf, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20dc18/25204810: WHILEHS  <PNd>.<T>, <Xn>, <Xm>, <vl>
   Instruction Set: A64  Groups: sve_int_while_rr_pn, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilehs_pn_rr, uint32_t, uOpcode)
{
    uint32_t const PNd        = (uOpcode >>  0) & 0x00000007;
    uint32_t const eq         = (uOpcode >>  3) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const vl         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilehs_pn_rr PNd=%u eq=%u Rn=%#x lt=%u vl=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, PNd, eq, Rn, lt, vl, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilehs_pn_rr
        IEM_INSTR_IMPL_A64__whilehs_pn_rr(PNd, eq, Rn, lt, vl, Rm, size);
#else
        RT_NOREF(PNd, eq, Rn, lt, vl, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc11/25205810: WHILEHS  { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm>
   Instruction Set: A64  Groups: sve_int_while_rr_pair, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilehs_pp_rr, uint32_t, uOpcode)
{
    uint32_t const eq         = (uOpcode >>  0) & 0x00000001;
    uint32_t const Pd         = (uOpcode >>  1) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilehs_pp_rr eq=%u Pd=%u Rn=%#x lt=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, eq, Pd, Rn, lt, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilehs_pp_rr
        IEM_INSTR_IMPL_A64__whilehs_pp_rr(eq, Pd, Rn, lt, Rm, size);
#else
        RT_NOREF(eq, Pd, Rn, lt, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20ec10/25200410: WHILELE  <Pd>.<T>, <R><n>, <R><m>
   Instruction Set: A64  Groups: sve_int_while_rr, sve_cmpgpr, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilele_p_p_rr, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const eq         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const sf         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: whilele_p_p_rr Pd=%#x eq=%u Rn=%#x lt=%u sf=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, eq, Rn, lt, sf, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilele_p_p_rr
        IEM_INSTR_IMPL_A64__whilele_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size);
#else
        RT_NOREF(Pd, eq, Rn, lt, sf, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20dc18/25204418: WHILELE  <PNd>.<T>, <Xn>, <Xm>, <vl>
   Instruction Set: A64  Groups: sve_int_while_rr_pn, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilele_pn_rr, uint32_t, uOpcode)
{
    uint32_t const PNd        = (uOpcode >>  0) & 0x00000007;
    uint32_t const eq         = (uOpcode >>  3) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const vl         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilele_pn_rr PNd=%u eq=%u Rn=%#x lt=%u vl=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, PNd, eq, Rn, lt, vl, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilele_pn_rr
        IEM_INSTR_IMPL_A64__whilele_pn_rr(PNd, eq, Rn, lt, vl, Rm, size);
#else
        RT_NOREF(PNd, eq, Rn, lt, vl, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc11/25205411: WHILELE  { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm>
   Instruction Set: A64  Groups: sve_int_while_rr_pair, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilele_pp_rr, uint32_t, uOpcode)
{
    uint32_t const eq         = (uOpcode >>  0) & 0x00000001;
    uint32_t const Pd         = (uOpcode >>  1) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilele_pp_rr eq=%u Pd=%u Rn=%#x lt=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, eq, Pd, Rn, lt, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilele_pp_rr
        IEM_INSTR_IMPL_A64__whilele_pp_rr(eq, Pd, Rn, lt, Rm, size);
#else
        RT_NOREF(eq, Pd, Rn, lt, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20ec10/25200c00: WHILELO  <Pd>.<T>, <R><n>, <R><m>
   Instruction Set: A64  Groups: sve_int_while_rr, sve_cmpgpr, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilelo_p_p_rr, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const eq         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const sf         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: whilelo_p_p_rr Pd=%#x eq=%u Rn=%#x lt=%u sf=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, eq, Rn, lt, sf, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilelo_p_p_rr
        IEM_INSTR_IMPL_A64__whilelo_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size);
#else
        RT_NOREF(Pd, eq, Rn, lt, sf, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20dc18/25204c10: WHILELO  <PNd>.<T>, <Xn>, <Xm>, <vl>
   Instruction Set: A64  Groups: sve_int_while_rr_pn, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilelo_pn_rr, uint32_t, uOpcode)
{
    uint32_t const PNd        = (uOpcode >>  0) & 0x00000007;
    uint32_t const eq         = (uOpcode >>  3) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const vl         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilelo_pn_rr PNd=%u eq=%u Rn=%#x lt=%u vl=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, PNd, eq, Rn, lt, vl, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilelo_pn_rr
        IEM_INSTR_IMPL_A64__whilelo_pn_rr(PNd, eq, Rn, lt, vl, Rm, size);
#else
        RT_NOREF(PNd, eq, Rn, lt, vl, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc11/25205c10: WHILELO  { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm>
   Instruction Set: A64  Groups: sve_int_while_rr_pair, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilelo_pp_rr, uint32_t, uOpcode)
{
    uint32_t const eq         = (uOpcode >>  0) & 0x00000001;
    uint32_t const Pd         = (uOpcode >>  1) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilelo_pp_rr eq=%u Pd=%u Rn=%#x lt=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, eq, Pd, Rn, lt, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilelo_pp_rr
        IEM_INSTR_IMPL_A64__whilelo_pp_rr(eq, Pd, Rn, lt, Rm, size);
#else
        RT_NOREF(eq, Pd, Rn, lt, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20ec10/25200c10: WHILELS  <Pd>.<T>, <R><n>, <R><m>
   Instruction Set: A64  Groups: sve_int_while_rr, sve_cmpgpr, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilels_p_p_rr, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const eq         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const sf         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: whilels_p_p_rr Pd=%#x eq=%u Rn=%#x lt=%u sf=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, eq, Rn, lt, sf, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilels_p_p_rr
        IEM_INSTR_IMPL_A64__whilels_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size);
#else
        RT_NOREF(Pd, eq, Rn, lt, sf, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20dc18/25204c18: WHILELS  <PNd>.<T>, <Xn>, <Xm>, <vl>
   Instruction Set: A64  Groups: sve_int_while_rr_pn, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilels_pn_rr, uint32_t, uOpcode)
{
    uint32_t const PNd        = (uOpcode >>  0) & 0x00000007;
    uint32_t const eq         = (uOpcode >>  3) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const vl         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilels_pn_rr PNd=%u eq=%u Rn=%#x lt=%u vl=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, PNd, eq, Rn, lt, vl, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilels_pn_rr
        IEM_INSTR_IMPL_A64__whilels_pn_rr(PNd, eq, Rn, lt, vl, Rm, size);
#else
        RT_NOREF(PNd, eq, Rn, lt, vl, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc11/25205c11: WHILELS  { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm>
   Instruction Set: A64  Groups: sve_int_while_rr_pair, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilels_pp_rr, uint32_t, uOpcode)
{
    uint32_t const eq         = (uOpcode >>  0) & 0x00000001;
    uint32_t const Pd         = (uOpcode >>  1) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilels_pp_rr eq=%u Pd=%u Rn=%#x lt=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, eq, Pd, Rn, lt, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilels_pp_rr
        IEM_INSTR_IMPL_A64__whilels_pp_rr(eq, Pd, Rn, lt, Rm, size);
#else
        RT_NOREF(eq, Pd, Rn, lt, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20ec10/25200400: WHILELT  <Pd>.<T>, <R><n>, <R><m>
   Instruction Set: A64  Groups: sve_int_while_rr, sve_cmpgpr, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilelt_p_p_rr, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const eq         = (uOpcode >>  4) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const sf         = (uOpcode >> 12) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: whilelt_p_p_rr Pd=%#x eq=%u Rn=%#x lt=%u sf=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, eq, Rn, lt, sf, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilelt_p_p_rr
        IEM_INSTR_IMPL_A64__whilelt_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size);
#else
        RT_NOREF(Pd, eq, Rn, lt, sf, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20dc18/25204410: WHILELT  <PNd>.<T>, <Xn>, <Xm>, <vl>
   Instruction Set: A64  Groups: sve_int_while_rr_pn, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilelt_pn_rr, uint32_t, uOpcode)
{
    uint32_t const PNd        = (uOpcode >>  0) & 0x00000007;
    uint32_t const eq         = (uOpcode >>  3) & 0x00000001;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const vl         = (uOpcode >> 13) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilelt_pn_rr PNd=%u eq=%u Rn=%#x lt=%u vl=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, PNd, eq, Rn, lt, vl, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilelt_pn_rr
        IEM_INSTR_IMPL_A64__whilelt_pn_rr(PNd, eq, Rn, lt, vl, Rm, size);
#else
        RT_NOREF(PNd, eq, Rn, lt, vl, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc11/25205410: WHILELT  { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm>
   Instruction Set: A64  Groups: sve_int_while_rr_pair, sve_while_pn, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilelt_pp_rr, uint32_t, uOpcode)
{
    uint32_t const eq         = (uOpcode >>  0) & 0x00000001;
    uint32_t const Pd         = (uOpcode >>  1) & 0x00000007;
    uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const lt         = (uOpcode >> 10) & 0x00000001;
    uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/)
    {
        LogFlow(("%018x/%010x: whilelt_pp_rr eq=%u Pd=%u Rn=%#x lt=%u Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, eq, Pd, Rn, lt, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilelt_pp_rr
        IEM_INSTR_IMPL_A64__whilelt_pp_rr(eq, Pd, Rn, lt, Rm, size);
#else
        RT_NOREF(eq, Pd, Rn, lt, Rm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc10/25203010: WHILERW  <Pd>.<T>, <Xn>, <Xm>
   Instruction Set: A64  Groups: sve_int_whilenc, sve_cmpgpr, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilerw_p_rr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc10)) == UINT32_C(0x25203010))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: whilerw_p_rr Pd=%#x Rn=%#x Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Rn, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilerw_p_rr
            IEM_INSTR_IMPL_A64__whilerw_p_rr(Pd, Rn, Rm, size);
#else
            RT_NOREF(Pd, Rn, Rm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc10/25203000: WHILEWR  <Pd>.<T>, <Xn>, <Xm>
   Instruction Set: A64  Groups: sve_int_whilenc, sve_cmpgpr, sve */
FNIEMOP_DEF_1(iemDecodeA64_whilewr_p_rr, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc10)) == UINT32_C(0x25203000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Rn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const Rm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: whilewr_p_rr Pd=%#x Rn=%#x Rm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Rn, Rm, size));
#ifdef IEM_INSTR_IMPL_A64__whilewr_p_rr
            IEM_INSTR_IMPL_A64__whilewr_p_rr(Pd, Rn, Rm, size);
#else
            RT_NOREF(Pd, Rn, Rm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffe1f/25289000: WRFFR  <Pn>.B
   Instruction Set: A64  Groups: sve_int_wrffr, sve_pred_wrffr, sve */
FNIEMOP_DEF_1(iemDecodeA64_wrffr_f_p, uint32_t, uOpcode)
{
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/)
    {
        LogFlow(("%018x/%010x: wrffr_f_p Pn=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pn));
#ifdef IEM_INSTR_IMPL_A64__wrffr_f_p
        IEM_INSTR_IMPL_A64__wrffr_f_p(Pn);
#else
        RT_NOREF(Pn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/04203400: XAR  <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<const>
   Instruction Set: A64  Groups: sve_int_rotate_imm, sve_int_unpred_logical, sve */
FNIEMOP_DEF_1(iemDecodeA64_xar_z_zzi, uint32_t, uOpcode)
{
    uint32_t const Zdn        = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const imm3       = (uOpcode >> 16) & 0x00000007;
    uint32_t const tszl       = (uOpcode >> 19) & 0x00000003;
    uint32_t const tszh       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2 /*FEAT_SVE2*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: xar_z_zzi Zdn=%#x Zm=%#x imm3=%u tszl=%u tszh=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zdn, Zm, imm3, tszl, tszh));
#ifdef IEM_INSTR_IMPL_A64__xar_z_zzi
        IEM_INSTR_IMPL_A64__xar_z_zzi(Zdn, Zm, imm3, tszl, tszh);
#else
        RT_NOREF(Zdn, Zm, imm3, tszl, tszh, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9ff8/c00c0000: ZERO  ZA.D[<Wv>, <offs>, VGx2]
   Instruction Set: A64  Groups: mortlach_multi_zero, mortlach_multizero, sme */
FNIEMOP_DEF_1(iemDecodeA64_zero_za1_ri_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9ff8)) == UINT32_C(0xc00c0000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: zero_za1_ri_2 off3=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Rv));
#ifdef IEM_INSTR_IMPL_A64__zero_za1_ri_2
            IEM_INSTR_IMPL_A64__zero_za1_ri_2(off3, Rv);
#else
            RT_NOREF(off3, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9ff8/c00e0000: ZERO  ZA.D[<Wv>, <offs>, VGx4]
   Instruction Set: A64  Groups: mortlach_multi_zero, mortlach_multizero, sme */
FNIEMOP_DEF_1(iemDecodeA64_zero_za1_ri_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9ff8)) == UINT32_C(0xc00e0000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: zero_za1_ri_4 off3=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Rv));
#ifdef IEM_INSTR_IMPL_A64__zero_za1_ri_4
            IEM_INSTR_IMPL_A64__zero_za1_ri_4(off3, Rv);
#else
            RT_NOREF(off3, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9ff8/c00c8000: ZERO  ZA.D[<Wv>, <offs1>:<offs2>]
   Instruction Set: A64  Groups: mortlach_multi_zero, mortlach_multizero, sme */
FNIEMOP_DEF_1(iemDecodeA64_zero_za2_ri_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9ff8)) == UINT32_C(0xc00c8000))
    {
        uint32_t const off3       = (uOpcode >>  0) & 0x00000007;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: zero_za2_ri_1 off3=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off3, Rv));
#ifdef IEM_INSTR_IMPL_A64__zero_za2_ri_1
            IEM_INSTR_IMPL_A64__zero_za2_ri_1(off3, Rv);
#else
            RT_NOREF(off3, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9ffc/c00d0000: ZERO  ZA.D[<Wv>, <offs1>:<offs2>, VGx2]
   Instruction Set: A64  Groups: mortlach_multi_zero, mortlach_multizero, sme */
FNIEMOP_DEF_1(iemDecodeA64_zero_za2_ri_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9ffc)) == UINT32_C(0xc00d0000))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: zero_za2_ri_2 off2=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, Rv));
#ifdef IEM_INSTR_IMPL_A64__zero_za2_ri_2
            IEM_INSTR_IMPL_A64__zero_za2_ri_2(off2, Rv);
#else
            RT_NOREF(off2, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9ffc/c00d8000: ZERO  ZA.D[<Wv>, <offs1>:<offs2>, VGx4]
   Instruction Set: A64  Groups: mortlach_multi_zero, mortlach_multizero, sme */
FNIEMOP_DEF_1(iemDecodeA64_zero_za2_ri_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9ffc)) == UINT32_C(0xc00d8000))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: zero_za2_ri_4 off2=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, Rv));
#ifdef IEM_INSTR_IMPL_A64__zero_za2_ri_4
            IEM_INSTR_IMPL_A64__zero_za2_ri_4(off2, Rv);
#else
            RT_NOREF(off2, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9ffc/c00e8000: ZERO  ZA.D[<Wv>, <offs1>:<offs4>]
   Instruction Set: A64  Groups: mortlach_multi_zero, mortlach_multizero, sme */
FNIEMOP_DEF_1(iemDecodeA64_zero_za4_ri_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9ffc)) == UINT32_C(0xc00e8000))
    {
        uint32_t const off2       = (uOpcode >>  0) & 0x00000003;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: zero_za4_ri_1 off2=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, off2, Rv));
#ifdef IEM_INSTR_IMPL_A64__zero_za4_ri_1
            IEM_INSTR_IMPL_A64__zero_za4_ri_1(off2, Rv);
#else
            RT_NOREF(off2, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9ffe/c00f0000: ZERO  ZA.D[<Wv>, <offs1>:<offs4>, VGx2]
   Instruction Set: A64  Groups: mortlach_multi_zero, mortlach_multizero, sme */
FNIEMOP_DEF_1(iemDecodeA64_zero_za4_ri_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9ffe)) == UINT32_C(0xc00f0000))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: zero_za4_ri_2 o1=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, Rv));
#ifdef IEM_INSTR_IMPL_A64__zero_za4_ri_2
            IEM_INSTR_IMPL_A64__zero_za4_ri_2(o1, Rv);
#else
            RT_NOREF(o1, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffff9ffe/c00f8000: ZERO  ZA.D[<Wv>, <offs1>:<offs4>, VGx4]
   Instruction Set: A64  Groups: mortlach_multi_zero, mortlach_multizero, sme */
FNIEMOP_DEF_1(iemDecodeA64_zero_za4_ri_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9ffe)) == UINT32_C(0xc00f8000))
    {
        uint32_t const o1         = (uOpcode >>  0) & 0x00000001;
        uint32_t const Rv         = (uOpcode >> 13) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
        {
            LogFlow(("%018x/%010x: zero_za4_ri_4 o1=%u Rv=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, o1, Rv));
#ifdef IEM_INSTR_IMPL_A64__zero_za4_ri_4
            IEM_INSTR_IMPL_A64__zero_za4_ri_4(o1, Rv);
#else
            RT_NOREF(o1, Rv, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffff00/c0080000: ZERO  { <mask> }
   Instruction Set: A64  Groups: mortlach_zero_lvl2, mortlach_zero, sme */
FNIEMOP_DEF_1(iemDecodeA64_zero_za_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffff00)) == UINT32_C(0xc0080000))
    {
        uint32_t const imm8       = (uOpcode >>  0) & 0x000000ff;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: zero_za_i imm8=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, imm8));
#ifdef IEM_INSTR_IMPL_A64__zero_za_i
            IEM_INSTR_IMPL_A64__zero_za_i(imm8);
#else
            RT_NOREF(imm8, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffffffff/c0480001: ZERO  { ZT0 }
   Instruction Set: A64  Groups: mortlach_zero_zt_lvl2, mortlach_zero_zt, sme */
FNIEMOP_DEF_1(iemDecodeA64_zero_zt_i, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xc0480001))
    {
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
        {
            LogFlow(("%018x/%010x: zero_zt_i\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode));
#ifdef IEM_INSTR_IMPL_A64__zero_zt_i
            IEM_INSTR_IMPL_A64__zero_zt_i();
#else
            RT_NOREF(pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30fe10/05204000: ZIP1  <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_bin_perm_pp, sve_perm_predicates, sve */
FNIEMOP_DEF_1(iemDecodeA64_zip1_p_pp, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30fe10)) == UINT32_C(0x05204000))
    {
        uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
        uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
        uint32_t const H          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: zip1_p_pp Pd=%#x Pn=%#x H=%u Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, H, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__zip1_p_pp
            IEM_INSTR_IMPL_A64__zip1_p_pp(Pd, Pn, H, Pm, size);
#else
            RT_NOREF(Pd, Pn, H, Pm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/05206000: ZIP1  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_bin_perm_zz, sve_perm_inter, sve */
FNIEMOP_DEF_1(iemDecodeA64_zip1_z_zz, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x05206000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        uint32_t const size       = (uOpcode >> 22) & 0x00000003;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
        {
            LogFlow(("%018x/%010x: zip1_z_zz Zd=%#x Zn=%#x H=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__zip1_z_zz
            IEM_INSTR_IMPL_A64__zip1_z_zz(Zd, Zn, H, Zm, size);
#else
            RT_NOREF(Zd, Zn, H, Zm, size, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/05a00000: ZIP1  <Zd>.Q, <Zn>.Q, <Zm>.Q
   Instruction Set: A64  Groups: sve_int_perm_bin_long_perm_zz, sve_perm_inter_long, sve */
FNIEMOP_DEF_1(iemDecodeA64_zip1_z_zz_q, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x05a00000))
    {
        uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
        uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
        uint32_t const H          = (uOpcode >> 10) & 0x00000001;
        uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
        {
            LogFlow(("%018x/%010x: zip1_z_zz_q Zd=%#x Zn=%#x H=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm));
#ifdef IEM_INSTR_IMPL_A64__zip1_z_zz_q
            IEM_INSTR_IMPL_A64__zip1_z_zz_q(Zd, Zn, H, Zm);
#else
            RT_NOREF(Zd, Zn, H, Zm, pVCpu, uOpcode);
            return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
        }
        Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
        IEMOP_RAISE_INVALID_OPCODE_RET();
    }
    Log(("Invalid instruction %%#x at %%x\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff30fe10/05204400: ZIP2  <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_bin_perm_pp, sve_perm_predicates, sve */
FNIEMOP_DEF_1(iemDecodeA64_zip2_p_pp, uint32_t, uOpcode)
{
    uint32_t const Pd         = (uOpcode >>  0) & 0x0000000f;
    uint32_t const Pn         = (uOpcode >>  5) & 0x0000000f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Pm         = (uOpcode >> 16) & 0x0000000f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: zip2_p_pp Pd=%#x Pn=%#x H=%u Pm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Pd, Pn, H, Pm, size));
#ifdef IEM_INSTR_IMPL_A64__zip2_p_pp
        IEM_INSTR_IMPL_A64__zip2_p_pp(Pd, Pn, H, Pm, size);
#else
        RT_NOREF(Pd, Pn, H, Pm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/05206400: ZIP2  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_bin_perm_zz, sve_perm_inter, sve */
FNIEMOP_DEF_1(iemDecodeA64_zip2_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve /*FEAT_SVE*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme /*FEAT_SME*/)
    {
        LogFlow(("%018x/%010x: zip2_z_zz Zd=%#x Zn=%#x H=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__zip2_z_zz
        IEM_INSTR_IMPL_A64__zip2_z_zz(Zd, Zn, H, Zm, size);
#else
        RT_NOREF(Zd, Zn, H, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/05a00400: ZIP2  <Zd>.Q, <Zn>.Q, <Zm>.Q
   Instruction Set: A64  Groups: sve_int_perm_bin_long_perm_zz, sve_perm_inter_long, sve */
FNIEMOP_DEF_1(iemDecodeA64_zip2_z_zz_q, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fF64mm /*FEAT_F64MM*/)
    {
        LogFlow(("%018x/%010x: zip2_z_zz_q Zd=%#x Zn=%#x H=%u Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm));
#ifdef IEM_INSTR_IMPL_A64__zip2_z_zz_q
        IEM_INSTR_IMPL_A64__zip2_z_zz_q(Zd, Zn, H, Zm);
#else
        RT_NOREF(Zd, Zn, H, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff3ffc63/c136e000: ZIP  { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<T>-<Zn4>.<T> }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_zip, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_zip_mz_z_4, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: zip_mz_z_4 Zd=%u Zn=%u size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, size));
#ifdef IEM_INSTR_IMPL_A64__zip_mz_z_4
        IEM_INSTR_IMPL_A64__zip_mz_z_4(Zd, Zn, size);
#else
        RT_NOREF(Zd, Zn, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* fffffc63/c137e000: ZIP  { <Zd1>.Q-<Zd4>.Q }, { <Zn1>.Q-<Zn4>.Q }
   Instruction Set: A64  Groups: mortlach_multi4_z_z_long_zip, mortlach_multi_sve_4, sme */
FNIEMOP_DEF_1(iemDecodeA64_zip_mz_z_4q, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  2) & 0x00000007;
    uint32_t const Zn         = (uOpcode >>  7) & 0x00000007;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: zip_mz_z_4q Zd=%u Zn=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn));
#ifdef IEM_INSTR_IMPL_A64__zip_mz_z_4q
        IEM_INSTR_IMPL_A64__zip_mz_z_4q(Zd, Zn);
#else
        RT_NOREF(Zd, Zn, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc01/c120d000: ZIP  { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: mortlach_multi2_z_z_zip, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_zip_mz_zz_2, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: zip_mz_zz_2 Zd=%#x Zn=%#x Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__zip_mz_zz_2
        IEM_INSTR_IMPL_A64__zip_mz_zz_2(Zd, Zn, Zm, size);
#else
        RT_NOREF(Zd, Zn, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc01/c120d400: ZIP  { <Zd1>.Q-<Zd2>.Q }, <Zn>.Q, <Zm>.Q
   Instruction Set: A64  Groups: mortlach_multi2_z_z_long_zip, mortlach_multi_sve_3, sme */
FNIEMOP_DEF_1(iemDecodeA64_zip_mz_zz_2q, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  1) & 0x0000000f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2 /*FEAT_SME2*/)
    {
        LogFlow(("%018x/%010x: zip_mz_zz_2q Zd=%#x Zn=%#x Zm=%#x\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, Zm));
#ifdef IEM_INSTR_IMPL_A64__zip_mz_zz_2q
        IEM_INSTR_IMPL_A64__zip_mz_zz_2q(Zd, Zn, Zm);
#else
        RT_NOREF(Zd, Zn, Zm, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4400e000: ZIPQ1  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_binquads, sve_perm_quads_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_zipq1_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: zipq1_z_zz Zd=%#x Zn=%#x H=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__zipq1_z_zz
        IEM_INSTR_IMPL_A64__zipq1_z_zz(Zd, Zn, H, Zm, size);
#else
        RT_NOREF(Zd, Zn, H, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ff20fc00/4400e400: ZIPQ2  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
   Instruction Set: A64  Groups: sve_int_perm_binquads, sve_perm_quads_b, sve */
FNIEMOP_DEF_1(iemDecodeA64_zipq2_z_zz, uint32_t, uOpcode)
{
    uint32_t const Zd         = (uOpcode >>  0) & 0x0000001f;
    uint32_t const Zn         = (uOpcode >>  5) & 0x0000001f;
    uint32_t const H          = (uOpcode >> 10) & 0x00000001;
    uint32_t const Zm         = (uOpcode >> 16) & 0x0000001f;
    uint32_t const size       = (uOpcode >> 22) & 0x00000003;
    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSve2p1 /*FEAT_SVE2p1*/ || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSme2p1 /*FEAT_SME2p1*/)
    {
        LogFlow(("%018x/%010x: zipq2_z_zz Zd=%#x Zn=%#x H=%u Zm=%#x size=%u\n", pVCpu->cpum.GstCtx.Pc.u64, uOpcode, Zd, Zn, H, Zm, size));
#ifdef IEM_INSTR_IMPL_A64__zipq2_z_zz
        IEM_INSTR_IMPL_A64__zipq2_z_zz(Zd, Zn, H, Zm, size);
#else
        RT_NOREF(Zd, Zn, H, Zm, size, pVCpu, uOpcode);
        return VERR_IEM_INSTR_NOT_IMPLEMENTED;
#endif
    }
    Log(("Invalid instruction %%#x at %%x (cond)\n", uOpcode, pVCpu->cpum.GstCtx.Pc.u64));
    IEMOP_RAISE_INVALID_OPCODE_RET();
}

/* ffe0fc00/04000000 level 2 - mask=0x1f0000 entries=0x20 valid=%62 (0x14) leaf=%62 (0x14) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_ffe0fc00_04000000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_add_z_p_zz,
        iemDecodeA64_sub_z_p_zz,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_subr_z_p_zz,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_smax_z_p_zz,
        iemDecodeA64_umax_z_p_zz,
        iemDecodeA64_smin_z_p_zz,
        iemDecodeA64_umin_z_p_zz,
        iemDecodeA64_sabd_z_p_zz,
        iemDecodeA64_uabd_z_p_zz,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_mul_z_p_zz,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_smulh_z_p_zz,
        iemDecodeA64_umulh_z_p_zz,
        iemDecodeA64_sdiv_z_p_zz,
        iemDecodeA64_udiv_z_p_zz,
        iemDecodeA64_sdivr_z_p_zz,
        iemDecodeA64_udivr_z_p_zz,
        iemDecodeA64_orr_z_p_zz,
        iemDecodeA64_eor_z_p_zz,
        iemDecodeA64_and_z_p_zz,
        iemDecodeA64_bic_z_p_zz,
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x001f0000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* ffe0fc00/05000000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ffe0fc00_05000000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30c000)) == UINT32_C(0x05100000))
        return iemDecodeA64_cpy_z_o_i(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffc0000)) == UINT32_C(0x05000000))
        return iemDecodeA64_orr_z_zi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ffe0fc00/1e000000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ffe0fc00_1e000000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x1e020000))
        return iemDecodeA64_SCVTF_S32_float2fix(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x1e030000))
        return iemDecodeA64_UCVTF_S32_float2fix(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x1e180000))
        return iemDecodeA64_FCVTZS_32S_float2fix(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x1e190000))
        return iemDecodeA64_FCVTZU_32S_float2fix(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ffe0fc00/80000000 level 2 - mask=0x100210 entries=0x8 valid=%100 (0x8) leaf=%100 (0x8) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_ffe0fc00_80000000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmop4a_za_zz_s1x1,
        iemDecodeA64_fmop4s_za_zz_s1x1,
        iemDecodeA64_fmop4a_za_zz_s2x1,
        iemDecodeA64_fmop4s_za_zz_s2x1,
        iemDecodeA64_fmop4a_za_zz_s1x2,
        iemDecodeA64_fmop4s_za_zz_s1x2,
        iemDecodeA64_fmop4a_za_zz_s2x2,
        iemDecodeA64_fmop4s_za_zz_s2x2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00100210 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >>  8) & UINT32_C(0x00000002)) /* bit  9 L 1 -> 1 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* ffe0fc00/81000000 level 2 - mask=0x100218 entries=0x10 valid=%100 (0x10) leaf=%100 (0x10) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_ffe0fc00_81000000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_bfmop4a_za32_zz_h1x1,
        iemDecodeA64_fmop4a_za_zz_h1x1,
        iemDecodeA64_bfmop4s_za32_zz_h1x1,
        iemDecodeA64_fmop4s_za_zz_h1x1,
        iemDecodeA64_bfmop4a_za32_zz_h2x1,
        iemDecodeA64_fmop4a_za_zz_h2x1,
        iemDecodeA64_bfmop4s_za32_zz_h2x1,
        iemDecodeA64_fmop4s_za_zz_h2x1,
        iemDecodeA64_bfmop4a_za32_zz_h1x2,
        iemDecodeA64_fmop4a_za_zz_h1x2,
        iemDecodeA64_bfmop4s_za32_zz_h1x2,
        iemDecodeA64_fmop4s_za_zz_h1x2,
        iemDecodeA64_bfmop4a_za32_zz_h2x2,
        iemDecodeA64_fmop4a_za_zz_h2x2,
        iemDecodeA64_bfmop4s_za32_zz_h2x2,
        iemDecodeA64_fmop4s_za_zz_h2x2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00100218 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >>  7) & UINT32_C(0x00000004)) /* bit  9 L 1 -> 2 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* ffe0fc00/9e000000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ffe0fc00_9e000000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x9e020000))
        return iemDecodeA64_SCVTF_S64_float2fix(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x9e030000))
        return iemDecodeA64_UCVTF_S64_float2fix(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x9e180000))
        return iemDecodeA64_FCVTZS_64S_float2fix(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x9e190000))
        return iemDecodeA64_FCVTZU_64S_float2fix(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00000000 level 1 - mask=0x9f000000 entries=0x40 valid=%56 (0x24) leaf=%47 (0x1e) multi-if=%5 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00000000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_UDF_only_perm_undef,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ffe0fc00_04000000_2,
        iemDecodeA64_ffe0fc00_05000000_2,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_AND_32_log_shift,
        iemDecodeA64_ADD_32_addsub_shift,
        iemDecodeA64_ST4_asisdlse_R4,
        iemDecodeA64_ST1_asisdlso_B1_1b,
        iemDecodeA64_TBL_asimdtbl_L1_1,
        iemDecodeA64_FDOT_asimdelem_D,
        iemDecodeA64_ADR_only_pcreladdr,
        iemDecodeA64_ADD_32_addsub_imm,
        iemDecodeA64_AND_32_log_imm,
        iemDecodeA64_SBFM_32M_bitfield,
        iemDecodeA64_B_only_branch_imm,
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_LDR_32_loadlit,
        iemDecodeA64_STLURB_32_ldapstl_unscaled,
        iemDecodeA64_ADC_32_addsub_carry,
        iemDecodeA64_MADD_32A_dp_3src,
        iemDecodeA64_LDR_S_loadlit,
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_ffe0fc00_1e000000_2,
        iemDecodeA64_FMADD_S_floatdp3,
        iemDecodeA64_ffe0fc00_80000000_2,
        iemDecodeA64_ffe0fc00_81000000_2,
        iemDecodeA64_Invalid, // 34
        iemDecodeA64_Invalid, // 35
        iemDecodeA64_ld1sb_z_p_bz_s_x32_unscaled,
        iemDecodeA64_Invalid, // 37
        iemDecodeA64_Invalid, // 38
        iemDecodeA64_Invalid, // 39
        iemDecodeA64_Invalid, // 40
        iemDecodeA64_Invalid, // 41
        iemDecodeA64_AND_64_log_shift,
        iemDecodeA64_ADD_64_addsub_shift,
        iemDecodeA64_Invalid, // 44
        iemDecodeA64_Invalid, // 45
        iemDecodeA64_Invalid, // 46
        iemDecodeA64_Invalid, // 47
        iemDecodeA64_ADRP_only_pcreladdr,
        iemDecodeA64_ADD_64_addsub_imm,
        iemDecodeA64_AND_64_log_imm,
        iemDecodeA64_Invalid, // 51
        iemDecodeA64_BL_only_branch_imm,
        iemDecodeA64_Invalid, // 53
        iemDecodeA64_Invalid, // 54
        iemDecodeA64_Invalid, // 55
        iemDecodeA64_LDRSW_64_loadlit,
        iemDecodeA64_STLUR_32_ldapstl_unscaled,
        iemDecodeA64_ADC_64_addsub_carry,
        iemDecodeA64_MADD_64A_dp_3src,
        iemDecodeA64_LDR_Q_loadlit,
        iemDecodeA64_Invalid, // 61
        iemDecodeA64_ffe0fc00_9e000000_2,
        iemDecodeA64_Invalid, // 63
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x40);

    /* fMask=0x9f000000 -> 0x0000003f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x0000001f)) /* bit 24 L 5 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000020)) /* bit 31 L 1 -> 5 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 67e0fc00/07000400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67e0fc00_07000400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f000400))
        return iemDecodeA64_SSHR_asimdshf_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff89c00)) == UINT32_C(0x0f000400))
        return iemDecodeA64_MOVI_asimdimm_L_sl(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00000400 level 1 - mask=0x7000000 entries=0x8 valid=%50 (0x4) leaf=%38 (0x3) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00000400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_CPYFP_CPY_memcms,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_CPYP_CPY_memcms,
        iemDecodeA64_DUP_asimdins_DV_v,
        iemDecodeA64_67e0fc00_07000400_2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x07000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000007)) /* bit 24 L 3 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00000800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00000800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x1d000800))
        return iemDecodeA64_STLUR_B_ldapstl_simd(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x9d000800))
        return iemDecodeA64_STLUR_S_ldapstl_simd(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x99000800))
        return iemDecodeA64_STILP_32SE_ldiappstilp(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00001000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00001000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x0f001000))
        return iemDecodeA64_FMLA_asimdelem_RH_H(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e001000))
        return iemDecodeA64_TBX_asimdtbl_L1_1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00001400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00001400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19001400))
        return iemDecodeA64_CPYFPWT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d001400))
        return iemDecodeA64_CPYPWT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f001400))
        return iemDecodeA64_SSRA_asimdshf_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff89c00)) == UINT32_C(0x0f001400))
        return iemDecodeA64_ORR_asimdimm_L_sl(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00001800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00001800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e001800))
        return iemDecodeA64_UZP1_asimdperm_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x99001800))
        return iemDecodeA64_STILP_32S_ldiappstilp(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e3fffc00/00002000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_e3fffc00_00002000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c002000))
        return iemDecodeA64_ST1_asisdlse_R4_4v(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04002000))
        return iemDecodeA64_saddv_r_p_z(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60fffc00/00002000 level 2 - mask=0x83000000 entries=0x8 valid=%75 (0x6) leaf=%62 (0x5) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60fffc00_00002000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_e3fffc00_00002000_3,
        iemDecodeA64_ST3_asisdlso_B3_3b,
        iemDecodeA64_TBL_asimdtbl_L2_2,
        iemDecodeA64_SMLAL_asimdelem_L,
        iemDecodeA64_ldff1sb_z_p_bz_s_x32_unscaled,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_ADDPT_64_addsub_pt,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x83000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00002000 level 1 - mask=0x1f0000 entries=0x20 valid=%56 (0x12) leaf=%53 (0x11) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00002000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60fffc00_00002000_2,
        iemDecodeA64_uaddv_r_p_z,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_addqv_z_p_z,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_smaxv_r_p_z,
        iemDecodeA64_umaxv_r_p_z,
        iemDecodeA64_sminv_r_p_z,
        iemDecodeA64_uminv_r_p_z,
        iemDecodeA64_smaxqv_z_p_z,
        iemDecodeA64_umaxqv_z_p_z,
        iemDecodeA64_sminqv_z_p_z,
        iemDecodeA64_uminqv_z_p_z,
        iemDecodeA64_movprfx_z_p_z,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_orv_r_p_z,
        iemDecodeA64_eorv_r_p_z,
        iemDecodeA64_andv_r_p_z,
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_orqv_z_p_z,
        iemDecodeA64_eorqv_z_p_z,
        iemDecodeA64_andqv_z_p_z,
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x001f0000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00002400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00002400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19002400))
        return iemDecodeA64_CPYFPRT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d002400))
        return iemDecodeA64_CPYPRT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f002400))
        return iemDecodeA64_SRSHR_asimdshf_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00003000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00003000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x0f003000))
        return iemDecodeA64_SQDMLAL_asimdelem_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e003000))
        return iemDecodeA64_TBX_asimdtbl_L2_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00003400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00003400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19003400))
        return iemDecodeA64_CPYFPT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d003400))
        return iemDecodeA64_CPYPT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f003400))
        return iemDecodeA64_SRSRA_asimdshf_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00004000 level 1 - mask=0x8b000000 entries=0x10 valid=%44 (0x7) leaf=%44 (0x7) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00004000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_mla_z_p_zzz,
        iemDecodeA64_cpy_z_p_i,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ST3_asisdlse_R3,
        iemDecodeA64_ST1_asisdlso_H1_1h,
        iemDecodeA64_TBL_asimdtbl_L3_3,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_ld1b_z_p_bz_s_x32_unscaled,
        iemDecodeA64_ld1w_z_p_bz_s_x32_unscaled,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8b000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000004)) /* bit 27 L 1 -> 2 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00004400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00004400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19004400))
        return iemDecodeA64_CPYFPWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d004400))
        return iemDecodeA64_CPYPWN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00005000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00005000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x0f005000))
        return iemDecodeA64_FMLS_asimdelem_RH_H(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e005000))
        return iemDecodeA64_TBX_asimdtbl_L3_3(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00005400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00005400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19005400))
        return iemDecodeA64_CPYFPWTWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d005400))
        return iemDecodeA64_CPYPWTWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f005400))
        return iemDecodeA64_SHL_asimdshf_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6be0fc00/00006000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6be0fc00_00006000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x04006000))
        return iemDecodeA64_mls_z_p_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x84006000))
        return iemDecodeA64_ldff1b_z_p_bz_s_x32_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00006000 level 1 - mask=0xb000000 entries=0x8 valid=%75 (0x6) leaf=%62 (0x5) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00006000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_6be0fc00_00006000_2,
        iemDecodeA64_ldff1w_z_p_bz_s_x32_unscaled,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ST1_asisdlse_R3_3v,
        iemDecodeA64_ST3_asisdlso_H3_3h,
        iemDecodeA64_TBL_asimdtbl_L4_4,
        iemDecodeA64_SMLSL_asimdelem_L,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x0b000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000004)) /* bit 27 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00006400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00006400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19006400))
        return iemDecodeA64_CPYFPRTWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d006400))
        return iemDecodeA64_CPYPRTWN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00007000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00007000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x0f007000))
        return iemDecodeA64_SQDMLSL_asimdelem_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e007000))
        return iemDecodeA64_TBX_asimdtbl_L4_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c007000))
        return iemDecodeA64_ST1_asisdlse_R1_1v(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00007400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00007400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19007400))
        return iemDecodeA64_CPYFPTWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d007400))
        return iemDecodeA64_CPYPTWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f007400))
        return iemDecodeA64_SQSHL_asimdshf_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00007c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00007c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x08007c00))
        return iemDecodeA64_STXRB_SR32_ldstexclr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x88007c00))
        return iemDecodeA64_STXR_SR32_ldstexclr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x89007c00))
        return iemDecodeA64_STTXR_SR32_ldstexclr_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 63fffe18/00008000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_63fffe18_00008000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c008000))
        return iemDecodeA64_ST2_asisdlse_R2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04008000))
        return iemDecodeA64_asr_z_p_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x84008000))
        return iemDecodeA64_ldnt1sb_z_p_ar_s_x32_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80008000))
        return iemDecodeA64_smop4a_za_zz_b1x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 63fffe18/01008000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_63fffe18_01008000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0d008000))
        return iemDecodeA64_ST1_asisdlso_S1_1s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81008000))
        return iemDecodeA64_usmop4a_za_zz_b1x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 63fffe18/03008000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_63fffe18_03008000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x0f008000))
        return iemDecodeA64_MUL_asimdelem_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x1b008000))
        return iemDecodeA64_MSUB_32A_dp_3src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x1f008000))
        return iemDecodeA64_FMSUB_S_floatdp3(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x9b008000))
        return iemDecodeA64_MSUB_64A_dp_3src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60fffc00/00008000 level 2 - mask=0x3000218 entries=0x20 valid=%53 (0x11) leaf=%44 (0xe) multi-if=%9 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60fffc00_00008000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_63fffe18_00008000_3,
        iemDecodeA64_smop4a_za32_zz_h1x1,
        iemDecodeA64_smop4s_za_zz_b1x1,
        iemDecodeA64_smop4s_za32_zz_h1x1,
        iemDecodeA64_smop4a_za_zz_b2x1,
        iemDecodeA64_smop4a_za32_zz_h2x1,
        iemDecodeA64_smop4s_za_zz_b2x1,
        iemDecodeA64_smop4s_za32_zz_h2x1,
        iemDecodeA64_63fffe18_01008000_3,
        iemDecodeA64_umop4a_za32_zz_h1x1,
        iemDecodeA64_usmop4s_za_zz_b1x1,
        iemDecodeA64_umop4s_za32_zz_h1x1,
        iemDecodeA64_usmop4a_za_zz_b2x1,
        iemDecodeA64_umop4a_za32_zz_h2x1,
        iemDecodeA64_usmop4s_za_zz_b2x1,
        iemDecodeA64_umop4s_za32_zz_h2x1,
        iemDecodeA64_Invalid, // 16
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_63fffe18_03008000_3,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x03000218 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >>  7) & UINT32_C(0x00000004)) /* bit  9 L 1 -> 2 */
                        | ((uOpcode >> 21) & UINT32_C(0x00000018)) /* bit 24 L 2 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 61fffe18/00108000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_61fffe18_00108000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x04108000))
        return iemDecodeA64_asr_z_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80108000))
        return iemDecodeA64_smop4a_za_zz_b1x2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60fffc00/00108000 level 2 - mask=0x1000218 entries=0x10 valid=%100 (0x10) leaf=%94 (0xf) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60fffc00_00108000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_61fffe18_00108000_3,
        iemDecodeA64_smop4a_za32_zz_h1x2,
        iemDecodeA64_smop4s_za_zz_b1x2,
        iemDecodeA64_smop4s_za32_zz_h1x2,
        iemDecodeA64_smop4a_za_zz_b2x2,
        iemDecodeA64_smop4a_za32_zz_h2x2,
        iemDecodeA64_smop4s_za_zz_b2x2,
        iemDecodeA64_smop4s_za32_zz_h2x2,
        iemDecodeA64_usmop4a_za_zz_b1x2,
        iemDecodeA64_umop4a_za32_zz_h1x2,
        iemDecodeA64_usmop4s_za_zz_b1x2,
        iemDecodeA64_umop4s_za32_zz_h1x2,
        iemDecodeA64_usmop4a_za_zz_b2x2,
        iemDecodeA64_umop4a_za32_zz_h2x2,
        iemDecodeA64_usmop4s_za_zz_b2x2,
        iemDecodeA64_umop4s_za32_zz_h2x2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x01000218 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >>  7) & UINT32_C(0x00000004)) /* bit  9 L 1 -> 2 */
                        | ((uOpcode >> 21) & UINT32_C(0x00000008)) /* bit 24 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00008000 level 1 - mask=0x1f0000 entries=0x20 valid=%56 (0x12) leaf=%50 (0x10) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00008000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60fffc00_00008000_2,
        iemDecodeA64_lsr_z_p_zi,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_lsl_z_p_zi,
        iemDecodeA64_asrd_z_p_zi,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_sqshl_z_p_zi,
        iemDecodeA64_uqshl_z_p_zi,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_srshr_z_p_zi,
        iemDecodeA64_urshr_z_p_zi,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_sqshlu_z_p_zi,
        iemDecodeA64_60fffc00_00108000_2,
        iemDecodeA64_lsr_z_p_zz,
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_lsl_z_p_zz,
        iemDecodeA64_asrr_z_p_zz,
        iemDecodeA64_lsrr_z_p_zz,
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_lslr_z_p_zz,
        iemDecodeA64_asr_z_p_zw,
        iemDecodeA64_lsr_z_p_zw,
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_lsl_z_p_zw,
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x001f0000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 76e1fc00/06008400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_76e1fc00_06008400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f008400))
        return iemDecodeA64_SHRN_asimdshf_N(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff8dc00)) == UINT32_C(0x0f008400))
        return iemDecodeA64_MOVI_asimdimm_L_hl(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00008400 level 1 - mask=0x16010000 entries=0x10 valid=%31 (0x5) leaf=%25 (0x4) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00008400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ST1_asisdlso_D1_1d,
        iemDecodeA64_STL1_asisdlso_D1,
        iemDecodeA64_76e1fc00_06008400_2,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_CPYFPRN_CPY_memcms,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_CPYPRN_CPY_memcms,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x16010000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000006)) /* bit 25 L 2 -> 1 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000008)) /* bit 28 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 67e0fc00/07009400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67e0fc00_07009400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f009400))
        return iemDecodeA64_SQSHRN_asimdshf_N(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff8dc00)) == UINT32_C(0x0f009400))
        return iemDecodeA64_ORR_asimdimm_L_hl(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00009400 level 1 - mask=0x7000000 entries=0x8 valid=%50 (0x4) leaf=%38 (0x3) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00009400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_CPYFPWTRN_CPY_memcms,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_CPYPWTRN_CPY_memcms,
        iemDecodeA64_SDOT_asimdsame2_D,
        iemDecodeA64_67e0fc00_07009400_2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x07000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000007)) /* bit 24 L 3 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 61fffc00/0000a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_0000a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c00a000))
        return iemDecodeA64_ST1_asisdlse_R2_2v(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0400a000))
        return iemDecodeA64_sxtb_z_p_z_z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x8400a000))
        return iemDecodeA64_ldnt1b_z_p_ar_s_x32_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61fffc00/0100a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_0100a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x0f00a000))
        return iemDecodeA64_SMULL_asimdelem_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0d00a000))
        return iemDecodeA64_ST3_asisdlso_S3_3s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x8500a000))
        return iemDecodeA64_ldnt1w_z_p_ar_s_x32_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0000a000 level 1 - mask=0x11f0000 entries=0x40 valid=%48 (0x1f) leaf=%45 (0x1d) multi-if=%3 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0000a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_61fffc00_0000a000_2,
        iemDecodeA64_uxtb_z_p_z_z,
        iemDecodeA64_sxth_z_p_z_z,
        iemDecodeA64_uxth_z_p_z_z,
        iemDecodeA64_sxtw_z_p_z_z,
        iemDecodeA64_uxtw_z_p_z_z,
        iemDecodeA64_abs_z_p_z_z,
        iemDecodeA64_neg_z_p_z_z,
        iemDecodeA64_cls_z_p_z_z,
        iemDecodeA64_clz_z_p_z_z,
        iemDecodeA64_cnt_z_p_z_z,
        iemDecodeA64_cnot_z_p_z_z,
        iemDecodeA64_fabs_z_p_z_z,
        iemDecodeA64_fneg_z_p_z_z,
        iemDecodeA64_not_z_p_z_z,
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_sxtb_z_p_z_m,
        iemDecodeA64_uxtb_z_p_z_m,
        iemDecodeA64_sxth_z_p_z_m,
        iemDecodeA64_uxth_z_p_z_m,
        iemDecodeA64_sxtw_z_p_z_m,
        iemDecodeA64_uxtw_z_p_z_m,
        iemDecodeA64_abs_z_p_z_m,
        iemDecodeA64_neg_z_p_z_m,
        iemDecodeA64_cls_z_p_z_m,
        iemDecodeA64_clz_z_p_z_m,
        iemDecodeA64_cnt_z_p_z_m,
        iemDecodeA64_cnot_z_p_z_m,
        iemDecodeA64_fabs_z_p_z_m,
        iemDecodeA64_fneg_z_p_z_m,
        iemDecodeA64_not_z_p_z_m,
        iemDecodeA64_Invalid, // 31
        iemDecodeA64_61fffc00_0100a000_2,
        iemDecodeA64_Invalid, // 33
        iemDecodeA64_Invalid, // 34
        iemDecodeA64_Invalid, // 35
        iemDecodeA64_Invalid, // 36
        iemDecodeA64_Invalid, // 37
        iemDecodeA64_Invalid, // 38
        iemDecodeA64_Invalid, // 39
        iemDecodeA64_Invalid, // 40
        iemDecodeA64_Invalid, // 41
        iemDecodeA64_Invalid, // 42
        iemDecodeA64_Invalid, // 43
        iemDecodeA64_Invalid, // 44
        iemDecodeA64_Invalid, // 45
        iemDecodeA64_Invalid, // 46
        iemDecodeA64_Invalid, // 47
        iemDecodeA64_Invalid, // 48
        iemDecodeA64_Invalid, // 49
        iemDecodeA64_Invalid, // 50
        iemDecodeA64_Invalid, // 51
        iemDecodeA64_Invalid, // 52
        iemDecodeA64_Invalid, // 53
        iemDecodeA64_Invalid, // 54
        iemDecodeA64_Invalid, // 55
        iemDecodeA64_Invalid, // 56
        iemDecodeA64_Invalid, // 57
        iemDecodeA64_Invalid, // 58
        iemDecodeA64_Invalid, // 59
        iemDecodeA64_Invalid, // 60
        iemDecodeA64_Invalid, // 61
        iemDecodeA64_Invalid, // 62
        iemDecodeA64_Invalid, // 63
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x40);

    /* fMask=0x011f0000 -> 0x0000003f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */
                        | ((uOpcode >> 19) & UINT32_C(0x00000020)) /* bit 24 L 1 -> 5 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/0000a400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0000a400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1900a400))
        return iemDecodeA64_CPYFPRTRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d00a400))
        return iemDecodeA64_CPYPRTRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f00a400))
        return iemDecodeA64_SSHLL_asimdshf_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0d00a400))
        return iemDecodeA64_ST3_asisdlso_D3_3d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0000b400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0000b400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1900b400))
        return iemDecodeA64_CPYFPTRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d00b400))
        return iemDecodeA64_CPYPTRN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0000c000 level 1 - mask=0x83000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0000c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_mad_z_p_zzz,
        iemDecodeA64_fcpy_z_p_i,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_SQDMULH_asimdelem_R,
        iemDecodeA64_prfb_i_p_br_s,
        iemDecodeA64_prfw_i_p_br_s,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x83000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/0000c400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0000c400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1900c400))
        return iemDecodeA64_CPYFPN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d00c400))
        return iemDecodeA64_CPYPN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff8ec00)) == UINT32_C(0x0f00c400))
        return iemDecodeA64_MOVI_asimdimm_M_sm(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x0e00c400))
        return iemDecodeA64_FMLALLBB_asimdsame2_G(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0000d400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0000d400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1900d400))
        return iemDecodeA64_CPYFPWTN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d00d400))
        return iemDecodeA64_CPYPWTN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0000e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0000e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x0f00e000))
        return iemDecodeA64_SDOT_asimdelem_D(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x0400e000))
        return iemDecodeA64_msb_z_p_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0x8400e000))
        return iemDecodeA64_prfb_i_p_ai_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0x8500e000))
        return iemDecodeA64_prfw_i_p_ai_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0000e400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0000e400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1900e400))
        return iemDecodeA64_CPYFPRTN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d00e400))
        return iemDecodeA64_CPYPRTN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f00e400))
        return iemDecodeA64_SCVTF_asimdshf_C(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff8fc00)) == UINT32_C(0x0f00e400))
        return iemDecodeA64_MOVI_asimdimm_N_b(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0000f400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0000f400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1900f400))
        return iemDecodeA64_CPYFPTN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d00f400))
        return iemDecodeA64_CPYPTN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e00f400))
        return iemDecodeA64_FCVTN_asimdsame2_H(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff8fc00)) == UINT32_C(0x0f00f400))
        return iemDecodeA64_FMOV_asimdimm_S_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e3e0fc00/0300fc00 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e3e0fc00_0300fc00_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x0f00fc00))
        return iemDecodeA64_FCVTZS_asimdshf_C(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff8fc00)) == UINT32_C(0x0f00fc00))
        return iemDecodeA64_FMOV_asimdimm_H_h(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0000fc00 level 1 - mask=0x83000000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0000fc00_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_STLXRB_SR32_ldstexclr,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_FDOT_asimdsame2_DD,
        iemDecodeA64_e3e0fc00_0300fc00_2,
        iemDecodeA64_STLXR_SR32_ldstexclr,
        iemDecodeA64_STLTXR_SR32_ldstexclr_unpriv,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x83000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* effffc00/0e200000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_effffc00_0e200000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e200000))
        return iemDecodeA64_SADDL_asimddiff_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e200000))
        return iemDecodeA64_FCVTNS_32S_float2int(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e0fffc00/00200000 level 2 - mask=0xf000000 entries=0x10 valid=%44 (0x7) leaf=%38 (0x6) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_e0fffc00_00200000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_add_z_zz,
        iemDecodeA64_ext_z_zi_des,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_BIC_32_log_shift,
        iemDecodeA64_ADD_32_addsub_ext,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_ST2_asisdlso_B2_2b,
        iemDecodeA64_effffc00_0e200000_3,
        iemDecodeA64_FNMADD_S_floatdp3,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x0f000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x0000000f)) /* bit 24 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e1fffe18/80200000 level 3 - mask=0x1e000000 entries=0x10 valid=%31 (0x5) leaf=%31 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_e1fffe18_80200000_3, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmop4a_za32_z8z8_b1x1,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_prfb_i_p_bz_s_x32_scaled,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_STXP_SP32_ldstexclp,
        iemDecodeA64_BIC_64_log_shift,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_FCVTNS_64S_float2int,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x1e000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 25) & UINT32_C(0x0000000f)) /* bit 25 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e1fffe18/81200000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_e1fffe18_81200000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00000)) == UINT32_C(0x8b200000))
        return iemDecodeA64_ADD_64_addsub_ext(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x9b200000))
        return iemDecodeA64_SMADDL_64WA_dp_3src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81200000))
        return iemDecodeA64_fmop4a_za32_zz_h1x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e0fffc00/80200000 level 2 - mask=0x1000218 entries=0x10 valid=%75 (0xc) leaf=%62 (0xa) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_e0fffc00_80200000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_e1fffe18_80200000_3,
        iemDecodeA64_fmop4a_za16_z8z8_b1x1,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_fmop4a_za32_z8z8_b2x1,
        iemDecodeA64_fmop4a_za16_z8z8_b2x1,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_e1fffe18_81200000_3,
        iemDecodeA64_bfmop4a_za_zz_h1x1,
        iemDecodeA64_fmop4s_za32_zz_h1x1,
        iemDecodeA64_bfmop4s_za_zz_h1x1,
        iemDecodeA64_fmop4a_za32_zz_h2x1,
        iemDecodeA64_bfmop4a_za_zz_h2x1,
        iemDecodeA64_fmop4s_za32_zz_h2x1,
        iemDecodeA64_bfmop4s_za_zz_h2x1,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x01000218 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >>  7) & UINT32_C(0x00000004)) /* bit  9 L 1 -> 2 */
                        | ((uOpcode >> 21) & UINT32_C(0x00000008)) /* bit 24 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e0fffc00/80300000 level 2 - mask=0x3000218 entries=0x20 valid=%41 (0xd) leaf=%41 (0xd) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_e0fffc00_80300000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmop4a_za32_z8z8_b1x2,
        iemDecodeA64_fmop4a_za16_z8z8_b1x2,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_fmop4a_za32_z8z8_b2x2,
        iemDecodeA64_fmop4a_za16_z8z8_b2x2,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_fmop4a_za32_zz_h1x2,
        iemDecodeA64_bfmop4a_za_zz_h1x2,
        iemDecodeA64_fmop4s_za32_zz_h1x2,
        iemDecodeA64_bfmop4s_za_zz_h1x2,
        iemDecodeA64_fmop4a_za32_zz_h2x2,
        iemDecodeA64_bfmop4a_za_zz_h2x2,
        iemDecodeA64_fmop4s_za32_zz_h2x2,
        iemDecodeA64_bfmop4s_za_zz_h2x2,
        iemDecodeA64_FCVTMS_64S_float2int,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x03000218 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >>  7) & UINT32_C(0x00000004)) /* bit  9 L 1 -> 2 */
                        | ((uOpcode >> 21) & UINT32_C(0x00000018)) /* bit 24 L 2 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00200000 level 1 - mask=0x801f0000 entries=0x40 valid=%59 (0x26) leaf=%55 (0x23) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00200000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_e0fffc00_00200000_2,
        iemDecodeA64_FCVTNU_32S_float2int,
        iemDecodeA64_SCVTF_S32_float2int,
        iemDecodeA64_UCVTF_S32_float2int,
        iemDecodeA64_FCVTAS_32S_float2int,
        iemDecodeA64_FCVTAU_32S_float2int,
        iemDecodeA64_FMOV_32S_float2int,
        iemDecodeA64_FMOV_S32_float2int,
        iemDecodeA64_FCVTPS_32S_float2int,
        iemDecodeA64_FCVTPU_32S_float2int,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_FCVTMS_32S_float2int,
        iemDecodeA64_FCVTMU_32S_float2int,
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_FCVTZS_32S_float2int,
        iemDecodeA64_FCVTZU_32S_float2int,
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
        iemDecodeA64_e0fffc00_80200000_2,
        iemDecodeA64_FCVTNU_64S_float2int,
        iemDecodeA64_SCVTF_S64_float2int,
        iemDecodeA64_UCVTF_S64_float2int,
        iemDecodeA64_FCVTAS_64S_float2int,
        iemDecodeA64_FCVTAU_64S_float2int,
        iemDecodeA64_Invalid, // 38
        iemDecodeA64_Invalid, // 39
        iemDecodeA64_FCVTPS_64S_float2int,
        iemDecodeA64_FCVTPU_64S_float2int,
        iemDecodeA64_FCVTNS_sisd_64S,
        iemDecodeA64_FCVTNU_sisd_64S,
        iemDecodeA64_Invalid, // 44
        iemDecodeA64_Invalid, // 45
        iemDecodeA64_Invalid, // 46
        iemDecodeA64_Invalid, // 47
        iemDecodeA64_e0fffc00_80300000_2,
        iemDecodeA64_FCVTMU_64S_float2int,
        iemDecodeA64_FCVTPS_sisd_64S,
        iemDecodeA64_FCVTPU_sisd_64S,
        iemDecodeA64_FCVTMS_sisd_64S,
        iemDecodeA64_FCVTMU_sisd_64S,
        iemDecodeA64_FCVTZS_sisd_64S,
        iemDecodeA64_FCVTZU_sisd_64S,
        iemDecodeA64_FCVTZS_64S_float2int,
        iemDecodeA64_FCVTZU_64S_float2int,
        iemDecodeA64_FCVTAS_sisd_64S,
        iemDecodeA64_FCVTAU_sisd_64S,
        iemDecodeA64_SCVTF_sisd_64S,
        iemDecodeA64_UCVTF_sisd_64S,
        iemDecodeA64_Invalid, // 62
        iemDecodeA64_Invalid, // 63
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x40);

    /* fMask=0x801f0000 -> 0x0000003f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000020)) /* bit 31 L 1 -> 5 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00200400 level 1 - mask=0x12000010 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00200400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sub_z_zz,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_SHADD_asimdsame_only,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDTADD_32_memop_unpriv,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_FCCMP_S_floatccmp,
        iemDecodeA64_FCCMPE_S_floatccmp,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x12000010 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000002)) /* bit 25 L 1 -> 1 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000004)) /* bit 28 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00200800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00200800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e200800))
        return iemDecodeA64_REV64_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19200800))
        return iemDecodeA64_RCWCAS_C64_rcwcomswap(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e200800))
        return iemDecodeA64_FMUL_S_floatdp2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00200c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00200c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e200c00))
        return iemDecodeA64_SQADD_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x1e200c00))
        return iemDecodeA64_FCSEL_S_floatsel(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19200c00))
        return iemDecodeA64_RCWCASP_C64_rcwcomswappr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00201000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00201000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e201000))
        return iemDecodeA64_SADDW_asimddiff_W(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04201000))
        return iemDecodeA64_sqadd_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe01fe0)) == UINT32_C(0x1e201000))
        return iemDecodeA64_FMOV_S_floatimm(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19201000))
        return iemDecodeA64_LDCLRP_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00201400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00201400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e201400))
        return iemDecodeA64_SRHADD_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04201400))
        return iemDecodeA64_uqadd_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19201400))
        return iemDecodeA64_LDTCLR_32_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00201800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00201800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e201800))
        return iemDecodeA64_REV16_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04201800))
        return iemDecodeA64_sqsub_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e201800))
        return iemDecodeA64_FDIV_S_floatdp2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00201c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00201c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e201c00))
        return iemDecodeA64_AND_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04201c00))
        return iemDecodeA64_uqsub_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 69e0fc18/08202000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_69e0fc18_08202000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e202000))
        return iemDecodeA64_SSUBL_asimddiff_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x1e202000))
        return iemDecodeA64_FCMP_S_floatcmp(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00202000 level 1 - mask=0x9000018 entries=0x10 valid=%44 (0x7) leaf=%38 (0x6) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00202000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_prfh_i_p_bz_s_x32_scaled,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_dup_z_zi,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_69e0fc18_08202000_2,
        iemDecodeA64_FCMP_SZ_floatcmp,
        iemDecodeA64_FCMPE_S_floatcmp,
        iemDecodeA64_FCMPE_SZ_floatcmp,
        iemDecodeA64_ST4_asisdlso_B4_4b,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x09000018 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000004)) /* bit 24 L 1 -> 2 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000008)) /* bit 27 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00202400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00202400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e202400))
        return iemDecodeA64_SHSUB_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x05202400))
        return iemDecodeA64_dupq_z_zi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00202800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00202800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e202800))
        return iemDecodeA64_SADDLP_asimdmisc_P(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e212800))
        return iemDecodeA64_XTN_asimdmisc_N(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x05202800))
        return iemDecodeA64_tbl_z_zz_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e202800))
        return iemDecodeA64_FADD_S_floatdp2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00202c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00202c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e202c00))
        return iemDecodeA64_SQSUB_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x05202c00))
        return iemDecodeA64_tbx_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00203000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00203000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e203000))
        return iemDecodeA64_SSUBW_asimddiff_W(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x05203000))
        return iemDecodeA64_tbl_z_zz_1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04203000))
        return iemDecodeA64_and_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19203000))
        return iemDecodeA64_LDSETP_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00203400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00203400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e203400))
        return iemDecodeA64_CMGT_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04203400))
        return iemDecodeA64_xar_z_zzi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x05203400))
        return iemDecodeA64_tbxq_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19203400))
        return iemDecodeA64_LDTSET_32_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc00/00203800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc00_00203800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e203800))
        return iemDecodeA64_SUQADD_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x05203800))
        return iemDecodeA64_dup_z_r(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04203800))
        return iemDecodeA64_eor3_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e203800))
        return iemDecodeA64_FSUB_S_floatdp2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc00/00243800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc00_00243800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x05243800))
        return iemDecodeA64_insr_z_r(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffdfc10)) == UINT32_C(0x052c3800))
        return iemDecodeA64_pmov_p_zi_h(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc00/00303800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc00_00303800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e303800))
        return iemDecodeA64_SADDLV_asimdall_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x05303800))
        return iemDecodeA64_sunpklo_z_z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x05383800))
        return iemDecodeA64_rev_z_z(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00203800 level 1 - mask=0x170000 entries=0x10 valid=%62 (0xa) leaf=%44 (0x7) multi-if=%19 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00203800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60f7fc00_00203800_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_pmov_p_zi_b,
        iemDecodeA64_pmov_z_pi_b,
        iemDecodeA64_60f7fc00_00243800_2,
        iemDecodeA64_pmov_z_pi_h,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_60f7fc00_00303800_2,
        iemDecodeA64_sunpkhi_z_z,
        iemDecodeA64_uunpklo_z_z,
        iemDecodeA64_uunpkhi_z_z,
        iemDecodeA64_insr_z_v,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00170000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000007)) /* bit 16 L 3 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00203c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00203c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e203c00))
        return iemDecodeA64_CMGE_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04203c00))
        return iemDecodeA64_bsl_z_zzz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* f9f7fc10/18204000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_f9f7fc10_18204000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e204000))
        return iemDecodeA64_FMOV_S_floatdp1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e284000))
        return iemDecodeA64_FRINT32Z_S_floatdp1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc10/00204000 level 2 - mask=0x99000000 entries=0x10 valid=%44 (0x7) leaf=%38 (0x6) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc10_00204000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_index_z_ii,
        iemDecodeA64_zip1_p_pp,
        iemDecodeA64_ADDHN_asimddiff_N,
        iemDecodeA64_ST2_asisdlso_H2_2h,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_f9f7fc10_18204000_3,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_prfw_i_p_bz_s_x32_scaled,
        iemDecodeA64_ld1w_z_p_bz_s_x32_scaled,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x99000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000006)) /* bit 27 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60f7fc10/00214000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc10_00214000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e214000))
        return iemDecodeA64_FNEG_S_floatdp1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e294000))
        return iemDecodeA64_FRINT64Z_S_floatdp1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00204000 level 1 - mask=0x170010 entries=0x20 valid=%28 (0x9) leaf=%22 (0x7) multi-if=%3 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00204000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60f7fc10_00204000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_60f7fc10_00214000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_FRINTN_S_floatdp1,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_FRINTM_S_floatdp1,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_FRINTA_S_floatdp1,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_FRINTX_S_floatdp1,
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_punpklo_p_p,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_punpkhi_p_p,
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_rev_p_p,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x00170010 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >> 15) & UINT32_C(0x0000000e)) /* bit 16 L 3 -> 1 */
                        | ((uOpcode >> 16) & UINT32_C(0x00000010)) /* bit 20 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00204400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00204400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e204400))
        return iemDecodeA64_SSHL_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04204400))
        return iemDecodeA64_index_z_ri(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff30fe10)) == UINT32_C(0x05204400))
        return iemDecodeA64_zip2_p_pp(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00204800 level 1 - mask=0x13010000 entries=0x10 valid=%31 (0x5) leaf=%31 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00204800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_index_z_ir,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_uzp1_p_pp,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_CLS_asimdmisc_R,
        iemDecodeA64_SQXTN_asimdmisc_N,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_FMAX_S_floatdp2,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x13010000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000006)) /* bit 24 L 2 -> 1 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000008)) /* bit 28 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00204c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00204c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e204c00))
        return iemDecodeA64_SQSHL_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04204c00))
        return iemDecodeA64_index_z_rr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff30fe10)) == UINT32_C(0x05204c00))
        return iemDecodeA64_uzp2_p_pp(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00205000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00205000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e205000))
        return iemDecodeA64_SABAL_asimddiff_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff30fe10)) == UINT32_C(0x05205000))
        return iemDecodeA64_trn1_p_pp(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f800)) == UINT32_C(0x04205000))
        return iemDecodeA64_addvl_r_ri(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00205400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00205400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e205400))
        return iemDecodeA64_SRSHL_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff30fe10)) == UINT32_C(0x05205400))
        return iemDecodeA64_trn2_p_pp(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00205800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00205800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e205800))
        return iemDecodeA64_CNT_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f800)) == UINT32_C(0x04205800))
        return iemDecodeA64_addsvl_r_ri(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e205800))
        return iemDecodeA64_FMIN_S_floatdp2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00206000 level 1 - mask=0x89000000 entries=0x8 valid=%75 (0x6) leaf=%75 (0x6) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00206000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_mul_z_zz,
        iemDecodeA64_zip1_z_zz,
        iemDecodeA64_SUBHN_asimddiff_N,
        iemDecodeA64_ST4_asisdlso_H4_4h,
        iemDecodeA64_prfd_i_p_bz_s_x32_scaled,
        iemDecodeA64_ldff1w_z_p_bz_s_x32_scaled,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x89000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000002)) /* bit 27 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00206400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00206400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e206400))
        return iemDecodeA64_SMAX_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x05206400))
        return iemDecodeA64_zip2_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04206400))
        return iemDecodeA64_pmul_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00206800 level 1 - mask=0x13010000 entries=0x10 valid=%31 (0x5) leaf=%31 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00206800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_smulh_z_zz,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_uzp1_z_zz,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_SADALP_asimdmisc_P,
        iemDecodeA64_FCVTN_asimdmisc_N,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_FMAXNM_S_floatdp2,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x13010000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000006)) /* bit 24 L 2 -> 1 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000008)) /* bit 28 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00206c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00206c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e206c00))
        return iemDecodeA64_SMIN_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04206c00))
        return iemDecodeA64_umulh_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x05206c00))
        return iemDecodeA64_uzp2_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00207000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00207000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e207000))
        return iemDecodeA64_SABDL_asimddiff_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04207000))
        return iemDecodeA64_sqdmulh_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x05207000))
        return iemDecodeA64_trn1_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00207400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00207400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e207400))
        return iemDecodeA64_SABD_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04207400))
        return iemDecodeA64_sqrdmulh_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x05207400))
        return iemDecodeA64_trn2_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00207800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00207800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e207800))
        return iemDecodeA64_SQABS_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0e217800))
        return iemDecodeA64_FCVTL_asimdmisc_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e207800))
        return iemDecodeA64_FMINNM_S_floatdp2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00207c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00207c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e207c00))
        return iemDecodeA64_SABA_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x08207c00))
        return iemDecodeA64_CASP_CP32_comswappr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67fffe10/00208000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_67fffe10_00208000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x88208000))
        return iemDecodeA64_STLXP_SP32_ldstexclp(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x80208000))
        return iemDecodeA64_sumop4a_za_zz_b1x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67fffe10/01208000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_67fffe10_01208000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19208000))
        return iemDecodeA64_SWPP_128_memop_128(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe3c)) == UINT32_C(0x81208000))
        return iemDecodeA64_umop4a_za_zz_b1x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67fffe10/04208000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_67fffe10_04208000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04208000))
        return iemDecodeA64_asr_z_zw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x84208000))
        return iemDecodeA64_ld1sb_z_p_ai_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67fffe10/05208000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_67fffe10_05208000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0d208000))
        return iemDecodeA64_ST2_asisdlso_S2_2s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x05208000))
        return iemDecodeA64_cpy_z_p_v(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60fffc00/00208000 level 2 - mask=0x7000210 entries=0x20 valid=%41 (0xd) leaf=%28 (0x9) multi-if=%12 (0x4) */
FNIEMOP_DEF_1(iemDecodeA64_60fffc00_00208000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_67fffe10_00208000_3,
        iemDecodeA64_sumop4s_za_zz_b1x1,
        iemDecodeA64_sumop4a_za_zz_b2x1,
        iemDecodeA64_sumop4s_za_zz_b2x1,
        iemDecodeA64_67fffe10_01208000_3,
        iemDecodeA64_umop4s_za_zz_b1x1,
        iemDecodeA64_umop4a_za_zz_b2x1,
        iemDecodeA64_umop4s_za_zz_b2x1,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_SMSUBL_64WA_dp_3src,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_67fffe10_04208000_3,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_67fffe10_05208000_3,
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_SMLAL_asimddiff_L,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_FNMSUB_S_floatdp3,
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x07000210 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >>  8) & UINT32_C(0x00000002)) /* bit  9 L 1 -> 1 */
                        | ((uOpcode >> 22) & UINT32_C(0x0000001c)) /* bit 24 L 3 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60fffc00/00308000 level 2 - mask=0x1000210 entries=0x8 valid=%100 (0x8) leaf=%100 (0x8) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60fffc00_00308000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sumop4a_za_zz_b1x2,
        iemDecodeA64_sumop4s_za_zz_b1x2,
        iemDecodeA64_sumop4a_za_zz_b2x2,
        iemDecodeA64_sumop4s_za_zz_b2x2,
        iemDecodeA64_umop4a_za_zz_b1x2,
        iemDecodeA64_umop4s_za_zz_b1x2,
        iemDecodeA64_umop4a_za_zz_b2x2,
        iemDecodeA64_umop4s_za_zz_b2x2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x01000210 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >>  8) & UINT32_C(0x00000002)) /* bit  9 L 1 -> 1 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000004)) /* bit 24 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00208000 level 1 - mask=0x1f0000 entries=0x20 valid=%53 (0x11) leaf=%47 (0xf) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00208000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60fffc00_00208000_2,
        iemDecodeA64_compact_z_p_z_s,
        iemDecodeA64_lasta_v_p_z,
        iemDecodeA64_lastb_v_p_z,
        iemDecodeA64_revb_z_z_m,
        iemDecodeA64_revh_z_z_m,
        iemDecodeA64_revw_z_z_m,
        iemDecodeA64_rbit_z_p_z_m,
        iemDecodeA64_clasta_z_p_zz,
        iemDecodeA64_clastb_z_p_zz,
        iemDecodeA64_clasta_v_p_z,
        iemDecodeA64_clastb_v_p_z,
        iemDecodeA64_splice_z_p_zz_des,
        iemDecodeA64_splice_z_p_zz_con,
        iemDecodeA64_revd_z_p_z_m,
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_60fffc00_00308000_2,
        iemDecodeA64_expand_z_p_z,
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x001f0000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00208400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00208400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e208400))
        return iemDecodeA64_ADD_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0d208400))
        return iemDecodeA64_ST2_asisdlso_D2_2d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04208400))
        return iemDecodeA64_lsr_z_zw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19208400))
        return iemDecodeA64_SWPT_32_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00208800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00208800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e208800))
        return iemDecodeA64_CMGT_asimdmisc_Z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0e218800))
        return iemDecodeA64_FRINTN_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e208800))
        return iemDecodeA64_FNMUL_S_floatdp2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00208c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00208c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e208c00))
        return iemDecodeA64_CMTST_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04208c00))
        return iemDecodeA64_lsl_z_zw(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00209000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00209000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e209000))
        return iemDecodeA64_SQDMLAL_asimddiff_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04209000))
        return iemDecodeA64_asr_z_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19209000))
        return iemDecodeA64_RCWCLRP_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00209400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00209400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e209400))
        return iemDecodeA64_MLA_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04209400))
        return iemDecodeA64_lsr_z_zi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00209800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00209800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e209800))
        return iemDecodeA64_CMEQ_asimdmisc_Z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0e219800))
        return iemDecodeA64_FRINTM_asimdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00209c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00209c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e209c00))
        return iemDecodeA64_MUL_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x04209c00))
        return iemDecodeA64_lsl_z_zi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* edeffc00/0520a000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_edeffc00_0520a000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0520a000))
        return iemDecodeA64_lasta_r_p_z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0530a000))
        return iemDecodeA64_clasta_r_p_z(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60effc00/0020a000 level 2 - mask=0x8d000000 entries=0x10 valid=%38 (0x6) leaf=%31 (0x5) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60effc00_0020a000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_adr_z_az_d_s32_scaled,
        iemDecodeA64_edeffc00_0520a000_3,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_RCWSWPP_128_memop_128,
        iemDecodeA64_SMLSL_asimddiff_L,
        iemDecodeA64_ST4_asisdlso_S4_4s,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_ldff1sb_z_p_ai_s,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8d000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60effc00/0021a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60effc00_0021a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0521a000))
        return iemDecodeA64_lastb_r_p_z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x0531a000))
        return iemDecodeA64_clastb_r_p_z(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0020a000 level 1 - mask=0xf0000 entries=0x10 valid=%50 (0x8) leaf=%38 (0x6) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60effc00_0020a000_2,
        iemDecodeA64_60effc00_0021a000_2,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_revb_z_z_z,
        iemDecodeA64_revh_z_z_z,
        iemDecodeA64_revw_z_z_z,
        iemDecodeA64_rbit_z_p_z_z,
        iemDecodeA64_cpy_z_p_r,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_revd_z_p_z_z,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x000f0000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000000f)) /* bit 16 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/0020a400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020a400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e20a400))
        return iemDecodeA64_SMAXP_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0d20a400))
        return iemDecodeA64_ST4_asisdlso_D4_4d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0020a800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020a800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e20a800))
        return iemDecodeA64_CMLT_asimdmisc_Z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e30a800))
        return iemDecodeA64_SMAXV_asimdall_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e31a800))
        return iemDecodeA64_SMINV_asimdall_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0e21a800))
        return iemDecodeA64_FCVTNS_asimdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0020b000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020b000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e20b000))
        return iemDecodeA64_SQDMLSL_asimddiff_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x0420b000))
        return iemDecodeA64_ftssel_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1920b000))
        return iemDecodeA64_RCWSETP_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0020b800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020b800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e20b800))
        return iemDecodeA64_ABS_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x0e31b800))
        return iemDecodeA64_ADDV_asimdall_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0e21b800))
        return iemDecodeA64_FCVTMS_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x0420b800))
        return iemDecodeA64_fexpa_z_z(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0020bc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020bc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e20bc00))
        return iemDecodeA64_ADDP_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x0420bc00))
        return iemDecodeA64_movprfx_z_z(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60effc00/0020c000 level 2 - mask=0x91000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60effc00_0020c000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_SMULL_asimddiff_L,
        iemDecodeA64_sel_z_p_zz,
        iemDecodeA64_FABS_S_floatdp1,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld1b_z_p_ai_s,
        iemDecodeA64_ld1w_z_p_ai_s,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x91000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000002)) /* bit 28 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/0020c000 level 1 - mask=0xf0000 entries=0x10 valid=%56 (0x9) leaf=%50 (0x8) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60effc00_0020c000_2,
        iemDecodeA64_FSQRT_S_floatdp1,
        iemDecodeA64_FCVT_DS_floatdp1,
        iemDecodeA64_FCVT_HS_floatdp1,
        iemDecodeA64_FRINTP_S_floatdp1,
        iemDecodeA64_FRINTZ_S_floatdp1,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_FRINTI_S_floatdp1,
        iemDecodeA64_FRINT32X_S_floatdp1,
        iemDecodeA64_FRINT64X_S_floatdp1,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x000f0000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000000f)) /* bit 16 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/0020c800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020c800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0e21c800))
        return iemDecodeA64_FCVTAS_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0e30c800))
        return iemDecodeA64_FMAXNMV_asimdall_only_H(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0020dc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020dc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x0e20dc00))
        return iemDecodeA64_FAMAX_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x0e20dc00))
        return iemDecodeA64_FMULX_asimdsame_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0020e000 level 1 - mask=0x83100000 entries=0x10 valid=%31 (0x5) leaf=%31 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_cntb_r_s,
        iemDecodeA64_incb_r_rs,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_PMULL_asimddiff_L,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_ldff1b_z_p_ai_s,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_ldff1w_z_p_ai_s,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x83100000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 20) & UINT32_C(0x00000001)) /* bit 20 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000006)) /* bit 24 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/0020e400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020e400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x0e20e400))
        return iemDecodeA64_FCMEQ_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0430e400))
        return iemDecodeA64_decb_r_rs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0020f000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020f000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0420f000))
        return iemDecodeA64_sqincb_r_rs_sx(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0430f000))
        return iemDecodeA64_sqincb_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0020f400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020f400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x0e20f400))
        return iemDecodeA64_FMAX_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0420f400))
        return iemDecodeA64_uqincb_r_rs_uw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0430f400))
        return iemDecodeA64_uqincb_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0020f800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020f800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0e21f800))
        return iemDecodeA64_FRINT64Z_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0e30f800))
        return iemDecodeA64_FMAXV_asimdall_only_H(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0420f800))
        return iemDecodeA64_sqdecb_r_rs_sx(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0430f800))
        return iemDecodeA64_sqdecb_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0020fc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0020fc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x0e20fc00))
        return iemDecodeA64_FRECPS_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x0820fc00))
        return iemDecodeA64_CASPL_CP32_comswappr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0420fc00))
        return iemDecodeA64_uqdecb_r_rs_uw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0430fc00))
        return iemDecodeA64_uqdecb_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6fe0fc00/01400000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6fe0fc00_01400000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0x81400000))
        return iemDecodeA64_bftmopa_za32_zzzi_h2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e00e)) == UINT32_C(0x81400008))
        return iemDecodeA64_ftmopa_za_zzzi_h2x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6fe0fc00/09400000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6fe0fc00_09400000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x19400000))
        return iemDecodeA64_LDAPURB_32_ldapstl_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x99400000))
        return iemDecodeA64_LDAPUR_32_ldapstl_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6fe0fc00/0e400000 level 2 - mask=0x80030000 entries=0x8 valid=%100 (0x8) leaf=%100 (0x8) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_6fe0fc00_0e400000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_FCVTZS_32D_float2fix,
        iemDecodeA64_FCVTZU_32D_float2fix,
        iemDecodeA64_SCVTF_D32_float2fix,
        iemDecodeA64_UCVTF_D32_float2fix,
        iemDecodeA64_FCVTZS_64D_float2fix,
        iemDecodeA64_FCVTZU_64D_float2fix,
        iemDecodeA64_SCVTF_D64_float2fix,
        iemDecodeA64_UCVTF_D64_float2fix,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x80030000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000003)) /* bit 16 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 6fe0fc00/0f400000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6fe0fc00_0f400000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x0f400000))
        return iemDecodeA64_FDOT_asimdelem_G(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x1f400000))
        return iemDecodeA64_FMADD_D_floatdp3(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00400000 level 1 - mask=0xf000000 entries=0x10 valid=%56 (0x9) leaf=%31 (0x5) multi-if=%19 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00400000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ftmopa_za_zzzi_s2x1,
        iemDecodeA64_6fe0fc00_01400000_2,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_SBFM_64M_bitfield,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_eor_z_zi,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_6fe0fc00_09400000_2,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LD4_asisdlse_R4,
        iemDecodeA64_LD1_asisdlso_B1_1b,
        iemDecodeA64_6fe0fc00_0e400000_2,
        iemDecodeA64_6fe0fc00_0f400000_2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x0f000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x0000000f)) /* bit 24 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00400400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00400400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19400400))
        return iemDecodeA64_CPYFM_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d400400))
        return iemDecodeA64_CPYM_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e400400))
        return iemDecodeA64_FMAXNM_asimdsamefp16_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00400800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00400800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x1d400800))
        return iemDecodeA64_LDAPUR_B_ldapstl_simd(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x9d400800))
        return iemDecodeA64_LDAPUR_S_ldapstl_simd(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x99400800))
        return iemDecodeA64_LDIAPP_32LE_ldiappstilp(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00401400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00401400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19401400))
        return iemDecodeA64_CPYFMWT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d401400))
        return iemDecodeA64_CPYMWT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e401400))
        return iemDecodeA64_FADD_asimdsamefp16_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00402000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00402000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0d402000))
        return iemDecodeA64_LD3_asisdlso_B3_3b(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c402000))
        return iemDecodeA64_LD1_asisdlse_R4_4v(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00402400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00402400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19402400))
        return iemDecodeA64_CPYFMRT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d402400))
        return iemDecodeA64_CPYMRT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e402400))
        return iemDecodeA64_FCMEQ_asimdsamefp16_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00403400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00403400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19403400))
        return iemDecodeA64_CPYFMT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d403400))
        return iemDecodeA64_CPYMT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e403400))
        return iemDecodeA64_FMAX_asimdsamefp16_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00404000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00404000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0d404000))
        return iemDecodeA64_LD1_asisdlso_H1_1h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c404000))
        return iemDecodeA64_LD3_asisdlse_R3(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00404400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00404400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19404400))
        return iemDecodeA64_CPYFMWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d404400))
        return iemDecodeA64_CPYMWN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00405400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00405400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19405400))
        return iemDecodeA64_CPYFMWTWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d405400))
        return iemDecodeA64_CPYMWTWN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00406000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00406000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0d406000))
        return iemDecodeA64_LD3_asisdlso_H3_3h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c406000))
        return iemDecodeA64_LD1_asisdlse_R3_3v(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00406400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00406400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19406400))
        return iemDecodeA64_CPYFMRTWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d406400))
        return iemDecodeA64_CPYMRTWN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00407400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00407400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19407400))
        return iemDecodeA64_CPYFMTWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d407400))
        return iemDecodeA64_CPYMTWN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00407c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00407c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9b407c00))
        return iemDecodeA64_SMULH_64_dp_3src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x085f7c00))
        return iemDecodeA64_LDXRB_LR32_ldstexclr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x885f7c00))
        return iemDecodeA64_LDXR_LR32_ldstexclr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x895f7c00))
        return iemDecodeA64_LDTXR_LR32_ldstexclr_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6de0fc08/0d408000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6de0fc08_0d408000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0d408000))
        return iemDecodeA64_LD1_asisdlso_S1_1s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x1f408000))
        return iemDecodeA64_FMSUB_D_floatdp3(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00408000 level 1 - mask=0xd000008 entries=0x10 valid=%50 (0x8) leaf=%44 (0x7) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00408000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_stmopa_za_zzzi_b2x1,
        iemDecodeA64_stmopa_za32_zzzi_h2x1,
        iemDecodeA64_ustmopa_za_zzzi_b2x1,
        iemDecodeA64_utmopa_za32_zzzi_h2x1,
        iemDecodeA64_ld1rb_z_p_bi_u8,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_ld1rsh_z_p_bi_s64,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LD2_asisdlse_R2,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_6de0fc08_0d408000_2,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x0d000008 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000001)) /* bit  3 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x0000000c)) /* bit 26 L 2 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00408400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00408400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19408400))
        return iemDecodeA64_CPYFMRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d408400))
        return iemDecodeA64_CPYMRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0d408400))
        return iemDecodeA64_LD1_asisdlso_D1_1d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0d418400))
        return iemDecodeA64_LDAP1_asisdlso_D1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00409400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00409400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19409400))
        return iemDecodeA64_CPYFMWTRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d409400))
        return iemDecodeA64_CPYMWTRN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0040a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0040a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0d40a000))
        return iemDecodeA64_LD3_asisdlso_S3_3s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c40a000))
        return iemDecodeA64_LD1_asisdlse_R2_2v(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x8440a000))
        return iemDecodeA64_ld1rb_z_p_bi_u16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x8540a000))
        return iemDecodeA64_ld1rsh_z_p_bi_s32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0040a400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0040a400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1940a400))
        return iemDecodeA64_CPYFMRTRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d40a400))
        return iemDecodeA64_CPYMRTRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0d40a400))
        return iemDecodeA64_LD3_asisdlso_D3_3d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0040b400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0040b400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1940b400))
        return iemDecodeA64_CPYFMTRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d40b400))
        return iemDecodeA64_CPYMTRN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0040c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0040c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0d40c000))
        return iemDecodeA64_LD1R_asisdlso_R1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x8440c000))
        return iemDecodeA64_ld1rb_z_p_bi_u32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x8540c000))
        return iemDecodeA64_ld1rw_z_p_bi_u32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0040c400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0040c400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1940c400))
        return iemDecodeA64_CPYFMN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d40c400))
        return iemDecodeA64_CPYMN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x0e40c400))
        return iemDecodeA64_FMLALLBT_asimdsame2_G(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0040d400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0040d400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1940d400))
        return iemDecodeA64_CPYFMWTN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d40d400))
        return iemDecodeA64_CPYMWTN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0040e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0040e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0d40e000))
        return iemDecodeA64_LD3R_asisdlso_R3(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x8440e000))
        return iemDecodeA64_ld1rb_z_p_bi_u64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x8540e000))
        return iemDecodeA64_ld1rw_z_p_bi_u64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0040e400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0040e400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1940e400))
        return iemDecodeA64_CPYFMRTN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d40e400))
        return iemDecodeA64_CPYMRTN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0040f400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0040f400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1940f400))
        return iemDecodeA64_CPYFMTN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d40f400))
        return iemDecodeA64_CPYMTN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e40f400))
        return iemDecodeA64_FCVTN_asimdsame2_D(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0040fc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0040fc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0e40fc00))
        return iemDecodeA64_FDOT_asimdsame2_D(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x085ffc00))
        return iemDecodeA64_LDAXRB_LR32_ldstexclr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x885ffc00))
        return iemDecodeA64_LDAXR_LR32_ldstexclr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x895ffc00))
        return iemDecodeA64_LDATXR_LR32_ldstexclr_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6de0fc08/0c600000 level 2 - mask=0x801f0000 entries=0x40 valid=%61 (0x27) leaf=%61 (0x27) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_6de0fc08_0c600000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_FCVTNS_32D_float2int,
        iemDecodeA64_FCVTNU_32D_float2int,
        iemDecodeA64_SCVTF_D32_float2int,
        iemDecodeA64_UCVTF_D32_float2int,
        iemDecodeA64_FCVTAS_32D_float2int,
        iemDecodeA64_FCVTAU_32D_float2int,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_FCVTPS_32D_float2int,
        iemDecodeA64_FCVTPU_32D_float2int,
        iemDecodeA64_FCVTNS_sisd_32D,
        iemDecodeA64_FCVTNU_sisd_32D,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_FCVTMS_32D_float2int,
        iemDecodeA64_FCVTMU_32D_float2int,
        iemDecodeA64_FCVTPS_sisd_32D,
        iemDecodeA64_FCVTPU_sisd_32D,
        iemDecodeA64_FCVTMS_sisd_32D,
        iemDecodeA64_FCVTMU_sisd_32D,
        iemDecodeA64_FCVTZS_sisd_32D,
        iemDecodeA64_FCVTZU_sisd_32D,
        iemDecodeA64_FCVTZS_32D_float2int,
        iemDecodeA64_FCVTZU_32D_float2int,
        iemDecodeA64_FCVTAS_sisd_32D,
        iemDecodeA64_FCVTAU_sisd_32D,
        iemDecodeA64_SCVTF_sisd_32D,
        iemDecodeA64_UCVTF_sisd_32D,
        iemDecodeA64_FJCVTZS_32D_float2int,
        iemDecodeA64_Invalid, // 31
        iemDecodeA64_FCVTNS_64D_float2int,
        iemDecodeA64_FCVTNU_64D_float2int,
        iemDecodeA64_SCVTF_D64_float2int,
        iemDecodeA64_UCVTF_D64_float2int,
        iemDecodeA64_FCVTAS_64D_float2int,
        iemDecodeA64_FCVTAU_64D_float2int,
        iemDecodeA64_FMOV_64D_float2int,
        iemDecodeA64_FMOV_D64_float2int,
        iemDecodeA64_FCVTPS_64D_float2int,
        iemDecodeA64_FCVTPU_64D_float2int,
        iemDecodeA64_Invalid, // 42
        iemDecodeA64_Invalid, // 43
        iemDecodeA64_Invalid, // 44
        iemDecodeA64_Invalid, // 45
        iemDecodeA64_Invalid, // 46
        iemDecodeA64_Invalid, // 47
        iemDecodeA64_FCVTMS_64D_float2int,
        iemDecodeA64_FCVTMU_64D_float2int,
        iemDecodeA64_Invalid, // 50
        iemDecodeA64_Invalid, // 51
        iemDecodeA64_Invalid, // 52
        iemDecodeA64_Invalid, // 53
        iemDecodeA64_Invalid, // 54
        iemDecodeA64_Invalid, // 55
        iemDecodeA64_FCVTZS_64D_float2int,
        iemDecodeA64_FCVTZU_64D_float2int,
        iemDecodeA64_Invalid, // 58
        iemDecodeA64_Invalid, // 59
        iemDecodeA64_Invalid, // 60
        iemDecodeA64_Invalid, // 61
        iemDecodeA64_Invalid, // 62
        iemDecodeA64_Invalid, // 63
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x40);

    /* fMask=0x801f0000 -> 0x0000003f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000020)) /* bit 31 L 1 -> 5 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 6de0fc08/0d600000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6de0fc08_0d600000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0d600000))
        return iemDecodeA64_LD2_asisdlso_B2_2b(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x1f600000))
        return iemDecodeA64_FNMADD_D_floatdp3(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00600000 level 1 - mask=0xd000008 entries=0x10 valid=%56 (0x9) leaf=%44 (0x7) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00600000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ftmopa_za32_z8z8zi_b2x1,
        iemDecodeA64_ftmopa_za16_z8z8zi_b2x1,
        iemDecodeA64_ftmopa_za32_zzzi_h2x1,
        iemDecodeA64_bftmopa_za_zzzi_h2x1,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_ext_z_zi_con,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_LDXP_LP32_ldstexclp,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_MADDPT_64A_dp_3src,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_6de0fc08_0c600000_2,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_6de0fc08_0d600000_2,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x0d000008 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000001)) /* bit  3 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x0000000c)) /* bit 26 L 2 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00600400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00600400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0x1e600400))
        return iemDecodeA64_FCCMP_D_floatccmp(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0x1e600410))
        return iemDecodeA64_FCCMPE_D_floatccmp(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19600400))
        return iemDecodeA64_LDTADDL_32_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00600800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00600800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19600800))
        return iemDecodeA64_RCWCASL_C64_rcwcomswap(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e600800))
        return iemDecodeA64_FMUL_D_floatdp2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00600c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00600c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x1e600c00))
        return iemDecodeA64_FCSEL_D_floatsel(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19600c00))
        return iemDecodeA64_RCWCASPL_C64_rcwcomswappr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00601000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00601000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe01fe0)) == UINT32_C(0x1e601000))
        return iemDecodeA64_FMOV_D_floatimm(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19601000))
        return iemDecodeA64_LDCLRPL_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00602000 level 1 - mask=0x1000018 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00602000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_FCMP_D_floatcmp,
        iemDecodeA64_FCMP_DZ_floatcmp,
        iemDecodeA64_FCMPE_D_floatcmp,
        iemDecodeA64_FCMPE_DZ_floatcmp,
        iemDecodeA64_LD4_asisdlso_B4_4b,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x01000018 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000004)) /* bit 24 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00603000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00603000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04603000))
        return iemDecodeA64_orr_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19603000))
        return iemDecodeA64_LDSETPL_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00603800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00603800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04603800))
        return iemDecodeA64_bcax_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e603800))
        return iemDecodeA64_FSUB_D_floatdp2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff9fc10)) == UINT32_C(0x05683800))
        return iemDecodeA64_pmov_p_zi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff9fe00)) == UINT32_C(0x05693800))
        return iemDecodeA64_pmov_z_pi_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60effc00/00604000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60effc00_00604000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0d604000))
        return iemDecodeA64_LD2_asisdlso_H2_2h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e604000))
        return iemDecodeA64_FMOV_D_floatdp1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00604000 level 1 - mask=0xf0000 entries=0x10 valid=%62 (0xa) leaf=%56 (0x9) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00604000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60effc00_00604000_2,
        iemDecodeA64_FNEG_D_floatdp1,
        iemDecodeA64_FCVT_SD_floatdp1,
        iemDecodeA64_BFCVT_BS_floatdp1,
        iemDecodeA64_FRINTN_D_floatdp1,
        iemDecodeA64_FRINTM_D_floatdp1,
        iemDecodeA64_FRINTA_D_floatdp1,
        iemDecodeA64_FRINTX_D_floatdp1,
        iemDecodeA64_FRINT32Z_D_floatdp1,
        iemDecodeA64_FRINT64Z_D_floatdp1,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x000f0000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000000f)) /* bit 16 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00605800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00605800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f800)) == UINT32_C(0x04605800))
        return iemDecodeA64_addspl_r_ri(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e605800))
        return iemDecodeA64_FMIN_D_floatdp2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00608000 level 1 - mask=0xf000000 entries=0x10 valid=%44 (0x7) leaf=%44 (0x7) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00608000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sutmopa_za_zzzi_b2x1,
        iemDecodeA64_utmopa_za_zzzi_b2x1,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_LDAXP_LP32_ldstexclp,
        iemDecodeA64_SWPPL_128_memop_128,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_MSUBPT_64A_dp_3src,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_LD2_asisdlso_S2_2s,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_FNMSUB_D_floatdp3,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x0f000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x0000000f)) /* bit 24 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00608400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00608400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0d608400))
        return iemDecodeA64_LD2_asisdlso_D2_2d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19608400))
        return iemDecodeA64_SWPTL_32_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00608800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00608800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0e798800))
        return iemDecodeA64_FRINTN_asimdmiscfp16_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1e608800))
        return iemDecodeA64_FNMUL_D_floatdp2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0060a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0060a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0d60a000))
        return iemDecodeA64_LD4_asisdlso_S4_4s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x0460a000))
        return iemDecodeA64_adr_z_az_d_u32_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1960a000))
        return iemDecodeA64_RCWSWPPL_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60effc00/0060c000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60effc00_0060c000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0d60c000))
        return iemDecodeA64_LD2R_asisdlso_R2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0460c000))
        return iemDecodeA64_sqinch_z_zs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0470c000))
        return iemDecodeA64_inch_z_zs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1e60c000))
        return iemDecodeA64_FABS_D_floatdp1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0060c000 level 1 - mask=0xf0000 entries=0x10 valid=%50 (0x8) leaf=%44 (0x7) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0060c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60effc00_0060c000_2,
        iemDecodeA64_FSQRT_D_floatdp1,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_FCVT_HD_floatdp1,
        iemDecodeA64_FRINTP_D_floatdp1,
        iemDecodeA64_FRINTZ_D_floatdp1,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_FRINTI_D_floatdp1,
        iemDecodeA64_FRINT32X_D_floatdp1,
        iemDecodeA64_FRINT64X_D_floatdp1,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x000f0000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000000f)) /* bit 16 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/0060c400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0060c400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0460c400))
        return iemDecodeA64_uqinch_z_zs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0470c400))
        return iemDecodeA64_dech_z_zs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0060c800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0060c800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0e79c800))
        return iemDecodeA64_FCVTAS_asimdmiscfp16_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0460c800))
        return iemDecodeA64_sqdech_z_zs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0060e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0060e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0d60e000))
        return iemDecodeA64_LD4R_asisdlso_R4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0460e000))
        return iemDecodeA64_cnth_r_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0470e000))
        return iemDecodeA64_inch_r_rs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0060f000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0060f000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0460f000))
        return iemDecodeA64_sqinch_r_rs_sx(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0470f000))
        return iemDecodeA64_sqinch_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0060f400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0060f400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0460f400))
        return iemDecodeA64_uqinch_r_rs_uw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0470f400))
        return iemDecodeA64_uqinch_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0060f800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0060f800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0460f800))
        return iemDecodeA64_sqdech_r_rs_sx(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0470f800))
        return iemDecodeA64_sqdech_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0060fc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0060fc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x0860fc00))
        return iemDecodeA64_CASPAL_CP32_comswappr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0460fc00))
        return iemDecodeA64_uqdech_r_rs_uw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x0470fc00))
        return iemDecodeA64_uqdech_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* efe0fc00/0c800000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_efe0fc00_0c800000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0c800000))
        return iemDecodeA64_ST4_asisdlsep_R4_r(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c9f0000))
        return iemDecodeA64_ST4_asisdlsep_I4_i(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* efe0fc00/0d800000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_efe0fc00_0d800000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e000)) == UINT32_C(0x0d800000))
        return iemDecodeA64_ST1_asisdlsop_BX1_r1b(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0d9f0000))
        return iemDecodeA64_ST1_asisdlsop_B1_i1b(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* efe0fc00/80800000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_efe0fc00_80800000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0x80800000))
        return iemDecodeA64_fmopa_za_pp_zz_32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0x80800008))
        return iemDecodeA64_bmopa_za_pp_zz_32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0x80800010))
        return iemDecodeA64_fmops_za_pp_zz_32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0x80800018))
        return iemDecodeA64_bmops_za_pp_zz_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* efe0fc00/81800000 level 2 - mask=0x1000001c entries=0x10 valid=%31 (0x5) leaf=%31 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_efe0fc00_81800000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_bfmopa_za32_pp_zz,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_fmopa_za_pp_zz_16,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_bfmops_za32_pp_zz,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_fmops_za_pp_zz_16,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_ADDG_64_addsub_immtags,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x1000001c -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  2) & UINT32_C(0x00000007)) /* bit  2 L 3 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000008)) /* bit 28 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00800000 level 1 - mask=0x8f000000 entries=0x20 valid=%47 (0xf) leaf=%34 (0xb) multi-if=%9 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00800000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_MOVN_32_movewide,
        iemDecodeA64_EXTR_32_extract,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_and_z_zi,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_LDAPURSB_64_ldapstl_unscaled,
        iemDecodeA64_CSEL_32_condsel,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_efe0fc00_0c800000_2,
        iemDecodeA64_efe0fc00_0d800000_2,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_FMLAL_asimdelem_LH,
        iemDecodeA64_efe0fc00_80800000_2,
        iemDecodeA64_efe0fc00_81800000_2,
        iemDecodeA64_MOVN_64_movewide,
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_ld1sh_z_p_bz_s_x32_unscaled,
        iemDecodeA64_ldr_p_bi,
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_LDAPURSW_64_ldapstl_unscaled,
        iemDecodeA64_CSEL_64_condsel,
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x8f000000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x0000000f)) /* bit 24 L 4 -> 0 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000010)) /* bit 31 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00800400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00800400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19800400))
        return iemDecodeA64_CPYFE_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d800400))
        return iemDecodeA64_CPYE_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x1a800400))
        return iemDecodeA64_CSINC_32_condsel(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x9a800400))
        return iemDecodeA64_CSINC_64_condsel(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00800800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00800800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x1d800800))
        return iemDecodeA64_STLUR_Q_ldapstl_simd(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x99800800))
        return iemDecodeA64_STLR_32S_ldapstl_writeback(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00801400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00801400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19801400))
        return iemDecodeA64_CPYFEWT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d801400))
        return iemDecodeA64_CPYEWT_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00802000 level 1 - mask=0x9010000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00802000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ldff1sh_z_p_bz_s_x32_unscaled,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ST1_asisdlsep_R4_r4,
        iemDecodeA64_ST1_asisdlsep_I4_i4,
        iemDecodeA64_ST3_asisdlsop_BX3_r3b,
        iemDecodeA64_ST3_asisdlsop_B3_i3b,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x09010000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000004)) /* bit 27 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00802400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00802400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19802400))
        return iemDecodeA64_CPYFERT_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d802400))
        return iemDecodeA64_CPYERT_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00803400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00803400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19803400))
        return iemDecodeA64_CPYFET_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d803400))
        return iemDecodeA64_CPYET_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00804000 level 1 - mask=0xb010000 entries=0x10 valid=%44 (0x7) leaf=%44 (0x7) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00804000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ld1h_z_p_bz_s_x32_unscaled,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_ldr_z_bi,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_ST3_asisdlsep_R3_r,
        iemDecodeA64_ST3_asisdlsep_I3_i,
        iemDecodeA64_ST1_asisdlsop_HX1_r1h,
        iemDecodeA64_ST1_asisdlsop_H1_i1h,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_FMLSL_asimdelem_LH,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x0b010000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000006)) /* bit 24 L 2 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000008)) /* bit 27 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00804400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00804400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19804400))
        return iemDecodeA64_CPYFEWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d804400))
        return iemDecodeA64_CPYEWN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00805400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00805400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19805400))
        return iemDecodeA64_CPYFEWTWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d805400))
        return iemDecodeA64_CPYEWTWN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00806000 level 1 - mask=0x9010000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00806000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ldff1h_z_p_bz_s_x32_unscaled,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ST1_asisdlsep_R3_r3,
        iemDecodeA64_ST1_asisdlsep_I3_i3,
        iemDecodeA64_ST3_asisdlsop_HX3_r3h,
        iemDecodeA64_ST3_asisdlsop_H3_i3h,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x09010000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000004)) /* bit 27 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00806400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00806400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19806400))
        return iemDecodeA64_CPYFERTWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d806400))
        return iemDecodeA64_CPYERTWN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00807000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00807000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0c807000))
        return iemDecodeA64_ST1_asisdlsep_R1_r1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0c9f7000))
        return iemDecodeA64_ST1_asisdlsep_I1_i1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00807400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00807400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19807400))
        return iemDecodeA64_CPYFETWN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d807400))
        return iemDecodeA64_CPYETWN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00807c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00807c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x089f7c00))
        return iemDecodeA64_STLLRB_SL32_ldstord(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x889f7c00))
        return iemDecodeA64_STLLR_SL32_ldstord(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00808000 level 1 - mask=0x9010000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00808000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ldnt1sh_z_p_ar_s_x32_unscaled,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ST2_asisdlsep_R2_r,
        iemDecodeA64_ST2_asisdlsep_I2_i,
        iemDecodeA64_ST1_asisdlsop_SX1_r1s,
        iemDecodeA64_ST1_asisdlsop_S1_i1s,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x09010000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000004)) /* bit 27 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00808400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00808400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19808400))
        return iemDecodeA64_CPYFERN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d808400))
        return iemDecodeA64_CPYERN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0d808400))
        return iemDecodeA64_ST1_asisdlsop_DX1_r1d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0d9f8400))
        return iemDecodeA64_ST1_asisdlsop_D1_i1d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00809400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00809400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19809400))
        return iemDecodeA64_CPYFEWTRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d809400))
        return iemDecodeA64_CPYEWTRN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0080a000 level 1 - mask=0x9010000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0080a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ldnt1h_z_p_ar_s_x32_unscaled,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ST1_asisdlsep_R2_r2,
        iemDecodeA64_ST1_asisdlsep_I2_i2,
        iemDecodeA64_ST3_asisdlsop_SX3_r3s,
        iemDecodeA64_ST3_asisdlsop_S3_i3s,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x09010000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000004)) /* bit 27 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/0080a400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0080a400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1980a400))
        return iemDecodeA64_CPYFERTRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d80a400))
        return iemDecodeA64_CPYERTRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0d80a400))
        return iemDecodeA64_ST3_asisdlsop_DX3_r3d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0d9fa400))
        return iemDecodeA64_ST3_asisdlsop_D3_i3d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0080b400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0080b400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1980b400))
        return iemDecodeA64_CPYFETRN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d80b400))
        return iemDecodeA64_CPYETRN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0080c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0080c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0x8480c000))
        return iemDecodeA64_prfh_i_p_br_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0x8580c000))
        return iemDecodeA64_prfd_i_p_br_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0080c400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0080c400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1980c400))
        return iemDecodeA64_CPYFEN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d80c400))
        return iemDecodeA64_CPYEN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0080d400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0080d400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1980d400))
        return iemDecodeA64_CPYFEWTN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d80d400))
        return iemDecodeA64_CPYEWTN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0080e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0080e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0x8480e000))
        return iemDecodeA64_prfh_i_p_ai_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0x8580e000))
        return iemDecodeA64_prfd_i_p_ai_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0080e400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0080e400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1980e400))
        return iemDecodeA64_CPYFERTN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d80e400))
        return iemDecodeA64_CPYERTN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0080f400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0080f400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1980f400))
        return iemDecodeA64_CPYFETN_CPY_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1d80f400))
        return iemDecodeA64_CPYETN_CPY_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/0080fc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_0080fc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x089ffc00))
        return iemDecodeA64_STLRB_SL32_ldstord(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x889ffc00))
        return iemDecodeA64_STLR_SL32_ldstord(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6de0fc18/0ca00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6de0fc18_0ca00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9eae0000))
        return iemDecodeA64_FMOV_64VX_float2int(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x9eaf0000))
        return iemDecodeA64_FMOV_V64I_float2int(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6de0fc18/0da00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6de0fc18_0da00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e000)) == UINT32_C(0x0da00000))
        return iemDecodeA64_ST2_asisdlsop_BX2_r2b(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0dbf0000))
        return iemDecodeA64_ST2_asisdlsop_B2_i2b(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a00000 level 1 - mask=0xd000018 entries=0x20 valid=%34 (0xb) leaf=%28 (0x9) multi-if=%6 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a00000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmopa_za32_pp_z8z8_8,
        iemDecodeA64_fmopa_za16_pp_z8z8_8,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_fmopa_za32_pp_zz_16,
        iemDecodeA64_bfmopa_za_pp_zz_16,
        iemDecodeA64_fmops_za32_pp_zz_16,
        iemDecodeA64_bfmops_za_pp_zz_16,
        iemDecodeA64_ld1sh_z_p_bz_s_x32_scaled,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_zip1_z_zz_q,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_Invalid, // 16
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_UMADDL_64WA_dp_3src,
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_6de0fc18_0ca00000_2,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_6de0fc18_0da00000_2,
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x0d000018 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000004)) /* bit 24 L 1 -> 2 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000018)) /* bit 26 L 2 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00a00400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a00400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x05a00400))
        return iemDecodeA64_zip2_z_zz_q(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19a00400))
        return iemDecodeA64_LDTADDA_32_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a00800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a00800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x05a00800))
        return iemDecodeA64_uzp1_z_zz_q(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19a00800))
        return iemDecodeA64_RCWCASA_C64_rcwcomswap(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a00c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a00c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x05a00c00))
        return iemDecodeA64_uzp2_z_zz_q(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19a00c00))
        return iemDecodeA64_RCWCASPA_C64_rcwcomswappr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a01c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a01c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0ea01c00))
        return iemDecodeA64_ORR_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x05a01c00))
        return iemDecodeA64_trn2_z_zz_q(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a02000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a02000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e000)) == UINT32_C(0x0da02000))
        return iemDecodeA64_ST4_asisdlsop_BX4_r4b(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0dbf2000))
        return iemDecodeA64_ST4_asisdlsop_B4_i4b(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x84a02000))
        return iemDecodeA64_ldff1sh_z_p_bz_s_x32_scaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a03000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a03000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04a03000))
        return iemDecodeA64_eor_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19a03000))
        return iemDecodeA64_LDSETPA_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a03800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a03800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb9fc10)) == UINT32_C(0x05a83800))
        return iemDecodeA64_pmov_p_zi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffb9fe00)) == UINT32_C(0x05a93800))
        return iemDecodeA64_pmov_z_pi_d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a04000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a04000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e400)) == UINT32_C(0x0da04000))
        return iemDecodeA64_ST2_asisdlsop_HX2_r2h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0dbf4000))
        return iemDecodeA64_ST2_asisdlsop_H2_i2h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x84a04000))
        return iemDecodeA64_ld1h_z_p_bz_s_x32_scaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a06000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a06000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e400)) == UINT32_C(0x0da06000))
        return iemDecodeA64_ST4_asisdlsop_HX4_r4h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0dbf6000))
        return iemDecodeA64_ST4_asisdlsop_H4_i4h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0x84a06000))
        return iemDecodeA64_ldff1h_z_p_bz_s_x32_scaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a07c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a07c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x08a07c00))
        return iemDecodeA64_CASB_C32_comswap(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x88a07c00))
        return iemDecodeA64_CAS_C32_comswap(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a08000 level 1 - mask=0xe010000 entries=0x10 valid=%38 (0x6) leaf=%38 (0x6) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a08000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld1sh_z_p_ai_s,
        iemDecodeA64_compact_z_p_z,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_SWPPA_128_memop_128,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_UMSUBL_64WA_dp_3src,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_ST2_asisdlsop_SX2_r2s,
        iemDecodeA64_ST2_asisdlsop_S2_i2s,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x0e010000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 24) & UINT32_C(0x0000000e)) /* bit 25 L 3 -> 1 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00a08400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a08400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0da08400))
        return iemDecodeA64_ST2_asisdlsop_DX2_r2d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0dbf8400))
        return iemDecodeA64_ST2_asisdlsop_D2_i2d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19a08400))
        return iemDecodeA64_SWPTA_32_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc00/0ca0a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc00_0ca0a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0ec00)) == UINT32_C(0x0da0a000))
        return iemDecodeA64_ST4_asisdlsop_SX4_r4s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0dbfa000))
        return iemDecodeA64_ST4_asisdlsop_S4_i4s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a0a000 level 1 - mask=0x8c000000 entries=0x8 valid=%50 (0x4) leaf=%38 (0x3) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a0a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_adr_z_az_sd_same_scaled,
        iemDecodeA64_RCWSWPPA_128_memop_128,
        iemDecodeA64_ece0fc00_0ca0a000_2,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_ldff1sh_z_p_ai_s,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00a0a400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a0a400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0da0a400))
        return iemDecodeA64_ST4_asisdlsop_DX4_r4d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0dbfa400))
        return iemDecodeA64_ST4_asisdlsop_D4_i4d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a0c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a0c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x84a0c000))
        return iemDecodeA64_ld1h_z_p_ai_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04a0c000))
        return iemDecodeA64_sqincw_z_zs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04b0c000))
        return iemDecodeA64_incw_z_zs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a0c400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a0c400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x0ea0c400))
        return iemDecodeA64_FMINNM_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04a0c400))
        return iemDecodeA64_uqincw_z_zs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04b0c400))
        return iemDecodeA64_decw_z_zs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a0c800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a0c800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0ea0c800))
        return iemDecodeA64_FCMGT_asimdmisc_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0ea1c800))
        return iemDecodeA64_URECPE_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0eb0c800))
        return iemDecodeA64_FMINNMV_asimdall_only_H(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04a0c800))
        return iemDecodeA64_sqdecw_z_zs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a0cc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a0cc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x0ea0cc00))
        return iemDecodeA64_FMLS_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04a0cc00))
        return iemDecodeA64_uqdecw_z_zs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a0d800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a0d800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0ea0d800))
        return iemDecodeA64_FCMEQ_asimdmisc_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0ea1d800))
        return iemDecodeA64_FRECPE_asimdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a0e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a0e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x84a0e000))
        return iemDecodeA64_ldff1h_z_p_ai_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04a0e000))
        return iemDecodeA64_cntw_r_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04b0e000))
        return iemDecodeA64_incw_r_rs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a0f000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a0f000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04a0f000))
        return iemDecodeA64_sqincw_r_rs_sx(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04b0f000))
        return iemDecodeA64_sqincw_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a0f400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a0f400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x0ea0f400))
        return iemDecodeA64_FMIN_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04a0f400))
        return iemDecodeA64_uqincw_r_rs_uw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04b0f400))
        return iemDecodeA64_uqincw_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a0f800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a0f800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x0ea0f800))
        return iemDecodeA64_FABS_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0eb0f800))
        return iemDecodeA64_FMINV_asimdall_only_H(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04a0f800))
        return iemDecodeA64_sqdecw_r_rs_sx(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04b0f800))
        return iemDecodeA64_sqdecw_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00a0fc00 level 1 - mask=0x86100000 entries=0x10 valid=%31 (0x5) leaf=%31 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00a0fc00_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_CASLB_C32_comswap,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_uqdecw_r_rs_uw,
        iemDecodeA64_uqdecw_r_rs_x,
        iemDecodeA64_FRSQRTS_asimdsame_only,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_CASL_C32_comswap,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x86100000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 20) & UINT32_C(0x00000001)) /* bit 20 L 1 -> 0 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000006)) /* bit 25 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e1e7fc00/00c00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e1e7fc00_00c00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0cc00000))
        return iemDecodeA64_LD4_asisdlsep_R4_r(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff0000)) == UINT32_C(0x1ed80000))
        return iemDecodeA64_FCVTZS_32H_float2fix(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ffe7fc00/11c00000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_ffe7fc00_11c00000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffc0000)) == UINT32_C(0x11c00000))
        return iemDecodeA64_SMAX_32_minmax_imm(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffc0000)) == UINT32_C(0x11c80000))
        return iemDecodeA64_SMIN_32_minmax_imm(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e1e7fc00/01c00000 level 2 - mask=0x1e000000 entries=0x10 valid=%38 (0x6) leaf=%31 (0x5) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_e1e7fc00_01c00000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_dupm_z_i,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LD1_asisdlsop_BX1_r1b,
        iemDecodeA64_FMLALB_asimdelem_H,
        iemDecodeA64_ffe7fc00_11c00000_3,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LDAPURSB_32_ldapstl_unscaled,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_FMADD_H_floatdp3,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x1e000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 25) & UINT32_C(0x0000000f)) /* bit 25 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e1e7fc00/01c40000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e1e7fc00_01c40000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffc0000)) == UINT32_C(0x11c40000))
        return iemDecodeA64_UMAX_32U_minmax_imm(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffc0000)) == UINT32_C(0x11cc0000))
        return iemDecodeA64_UMIN_32U_minmax_imm(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e1f7fe18/80c00000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_e1f7fe18_80c00000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00018)) == UINT32_C(0x80c00000))
        return iemDecodeA64_fmopa_za_pp_zz_64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac00000))
        return iemDecodeA64_SUBP_64S_dp_2src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e1e7fc00/80c00000 level 2 - mask=0x100218 entries=0x10 valid=%69 (0xb) leaf=%62 (0xa) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_e1e7fc00_80c00000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_e1f7fe18_80c00000_3,
        iemDecodeA64_fmop4a_za_zz_d1x1,
        iemDecodeA64_fmops_za_pp_zz_64,
        iemDecodeA64_fmop4s_za_zz_d1x1,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_fmop4a_za_zz_d2x1,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_fmop4s_za_zz_d2x1,
        iemDecodeA64_FCVTZS_64H_float2fix,
        iemDecodeA64_fmop4a_za_zz_d1x2,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_fmop4s_za_zz_d1x2,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_fmop4a_za_zz_d2x2,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_fmop4s_za_zz_d2x2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00100218 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >>  7) & UINT32_C(0x00000004)) /* bit  9 L 1 -> 2 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e1e7fc00/81c00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e1e7fc00_81c00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0e010)) == UINT32_C(0x85c00000))
        return iemDecodeA64_prfb_i_p_bi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00000)) == UINT32_C(0x93c00000))
        return iemDecodeA64_EXTR_64_extract(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffc0000)) == UINT32_C(0x91c00000))
        return iemDecodeA64_SMAX_64_minmax_imm(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffc0000)) == UINT32_C(0x91c80000))
        return iemDecodeA64_SMIN_64_minmax_imm(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e1e7fc00/81c40000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e1e7fc00_81c40000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffc0000)) == UINT32_C(0x91c40000))
        return iemDecodeA64_UMAX_64U_minmax_imm(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffc0000)) == UINT32_C(0x91cc0000))
        return iemDecodeA64_UMIN_64U_minmax_imm(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c00000 level 1 - mask=0x81070000 entries=0x20 valid=%50 (0x10) leaf=%31 (0xa) multi-if=%12 (0x4) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c00000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_e1e7fc00_00c00000_2,
        iemDecodeA64_FCVTZU_32H_float2fix,
        iemDecodeA64_SCVTF_H32_float2fix,
        iemDecodeA64_UCVTF_H32_float2fix,
        iemDecodeA64_addpt_z_p_zz,
        iemDecodeA64_subpt_z_p_zz,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_LD4_asisdlsep_I4_i,
        iemDecodeA64_e1e7fc00_01c00000_2,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_e1e7fc00_01c40000_2,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_LD1_asisdlsop_B1_i1b,
        iemDecodeA64_e1e7fc00_80c00000_2,
        iemDecodeA64_FCVTZU_64H_float2fix,
        iemDecodeA64_SCVTF_H64_float2fix,
        iemDecodeA64_UCVTF_H64_float2fix,
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_e1e7fc00_81c00000_2,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_e1e7fc00_81c40000_2,
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x81070000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000007)) /* bit 16 L 3 -> 0 */
                        | ((uOpcode >> 21) & UINT32_C(0x00000008)) /* bit 24 L 1 -> 3 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000010)) /* bit 31 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00c00400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c00400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19c00400))
        return iemDecodeA64_SETP_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1dc00400))
        return iemDecodeA64_SETGP_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0ec00400))
        return iemDecodeA64_FMINNM_asimdsamefp16_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c00800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c00800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x1dc00800))
        return iemDecodeA64_LDAPUR_Q_ldapstl_simd(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac00800))
        return iemDecodeA64_UDIV_32_dp_2src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac00800))
        return iemDecodeA64_UDIV_64_dp_2src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x99c00800))
        return iemDecodeA64_LDAPR_32L_ldapstl_writeback(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c00c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c00c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0ec00c00))
        return iemDecodeA64_FMLS_asimdsamefp16_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac00c00))
        return iemDecodeA64_SDIV_32_dp_2src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac00c00))
        return iemDecodeA64_SDIV_64_dp_2src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c01400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c01400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19c01400))
        return iemDecodeA64_SETPT_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1dc01400))
        return iemDecodeA64_SETGPT_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0ec01400))
        return iemDecodeA64_FSUB_asimdsamefp16_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac01400))
        return iemDecodeA64_GMI_64G_dp_2src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c02000 level 1 - mask=0x83010000 entries=0x10 valid=%44 (0x7) leaf=%44 (0x7) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c02000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LD1_asisdlsep_R4_r4,
        iemDecodeA64_LD1_asisdlsep_I4_i4,
        iemDecodeA64_LD3_asisdlsop_BX3_r3b,
        iemDecodeA64_LD3_asisdlsop_B3_i3b,
        iemDecodeA64_LSLV_32_dp_2src,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_prfh_i_p_bi_s,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LSLV_64_dp_2src,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x83010000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000006)) /* bit 24 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00c02400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c02400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19c02400))
        return iemDecodeA64_SETPN_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1dc02400))
        return iemDecodeA64_SETGPN_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac02400))
        return iemDecodeA64_LSRV_32_dp_2src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac02400))
        return iemDecodeA64_LSRV_64_dp_2src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c02800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c02800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac02800))
        return iemDecodeA64_ASRV_32_dp_2src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac02800))
        return iemDecodeA64_ASRV_64_dp_2src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c02c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c02c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac02c00))
        return iemDecodeA64_RORV_32_dp_2src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac02c00))
        return iemDecodeA64_RORV_64_dp_2src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c03400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c03400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19c03400))
        return iemDecodeA64_SETPTN_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1dc03400))
        return iemDecodeA64_SETGPTN_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0ec03400))
        return iemDecodeA64_FMIN_asimdsamefp16_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 63e1fc00/01c04000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_63e1fc00_01c04000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e400)) == UINT32_C(0x0dc04000))
        return iemDecodeA64_LD1_asisdlsop_HX1_r1h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0e010)) == UINT32_C(0x85c04000))
        return iemDecodeA64_prfw_i_p_bi_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c04000 level 1 - mask=0x3010000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c04000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LD3_asisdlsep_R3_r,
        iemDecodeA64_LD3_asisdlsep_I3_i,
        iemDecodeA64_63e1fc00_01c04000_2,
        iemDecodeA64_LD1_asisdlsop_H1_i1h,
        iemDecodeA64_CRC32B_32C_dp_2src,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x03010000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000006)) /* bit 24 L 2 -> 1 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00c04400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c04400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19c04400))
        return iemDecodeA64_SETM_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1dc04400))
        return iemDecodeA64_SETGM_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac04400))
        return iemDecodeA64_CRC32H_32C_dp_2src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c05400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c05400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19c05400))
        return iemDecodeA64_SETMT_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1dc05400))
        return iemDecodeA64_SETGMT_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac05400))
        return iemDecodeA64_CRC32CH_32C_dp_2src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c06000 level 1 - mask=0x83010000 entries=0x10 valid=%44 (0x7) leaf=%44 (0x7) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c06000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LD1_asisdlsep_R3_r3,
        iemDecodeA64_LD1_asisdlsep_I3_i3,
        iemDecodeA64_LD3_asisdlsop_HX3_r3h,
        iemDecodeA64_LD3_asisdlsop_H3_i3h,
        iemDecodeA64_SMAX_32_dp_2src,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_prfd_i_p_bi_s,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_SMAX_64_dp_2src,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x83010000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000006)) /* bit 24 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00c06400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c06400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19c06400))
        return iemDecodeA64_SETMN_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1dc06400))
        return iemDecodeA64_SETGMN_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac06400))
        return iemDecodeA64_UMAX_32_dp_2src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac06400))
        return iemDecodeA64_UMAX_64_dp_2src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c06800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c06800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac06800))
        return iemDecodeA64_SMIN_32_dp_2src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac06800))
        return iemDecodeA64_SMIN_64_dp_2src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c06c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c06c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ac06c00))
        return iemDecodeA64_UMIN_32_dp_2src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9ac06c00))
        return iemDecodeA64_UMIN_64_dp_2src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c07000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c07000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0cc07000))
        return iemDecodeA64_LD1_asisdlsep_R1_r1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0cdf7000))
        return iemDecodeA64_LD1_asisdlsep_I1_i1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c07400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c07400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19c07400))
        return iemDecodeA64_SETMTN_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1dc07400))
        return iemDecodeA64_SETGMTN_SET_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c07c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c07c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x9bc07c00))
        return iemDecodeA64_UMULH_64_dp_3src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x08df7c00))
        return iemDecodeA64_LDLARB_LR32_ldstord(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x88df7c00))
        return iemDecodeA64_LDLAR_LR32_ldstord(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c08000 level 1 - mask=0xb010000 entries=0x10 valid=%44 (0x7) leaf=%44 (0x7) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c08000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ld1rsw_z_p_bi_s64,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_ld1rsb_z_p_bi_s64,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_LD2_asisdlsep_R2_r,
        iemDecodeA64_LD2_asisdlsep_I2_i,
        iemDecodeA64_LD1_asisdlsop_SX1_r1s,
        iemDecodeA64_LD1_asisdlsop_S1_i1s,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_FMSUB_H_floatdp3,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x0b010000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000006)) /* bit 24 L 2 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000008)) /* bit 27 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00c08400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c08400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19c08400))
        return iemDecodeA64_SETE_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1dc08400))
        return iemDecodeA64_SETGE_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0dc08400))
        return iemDecodeA64_LD1_asisdlsop_DX1_r1d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0ddf8400))
        return iemDecodeA64_LD1_asisdlsop_D1_i1d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c09400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c09400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19c09400))
        return iemDecodeA64_SETET_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1dc09400))
        return iemDecodeA64_SETGET_SET_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c0a000 level 1 - mask=0x9010000 entries=0x8 valid=%75 (0x6) leaf=%75 (0x6) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c0a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ld1rh_z_p_bi_u16,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_ld1rsb_z_p_bi_s32,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LD1_asisdlsep_R2_r2,
        iemDecodeA64_LD1_asisdlsep_I2_i2,
        iemDecodeA64_LD3_asisdlsop_SX3_r3s,
        iemDecodeA64_LD3_asisdlsop_S3_i3s,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x09010000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000004)) /* bit 27 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00c0a400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c0a400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19c0a400))
        return iemDecodeA64_SETEN_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1dc0a400))
        return iemDecodeA64_SETGEN_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0dc0a400))
        return iemDecodeA64_LD3_asisdlsop_DX3_r3d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0ddfa400))
        return iemDecodeA64_LD3_asisdlsop_D3_i3d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c0b400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c0b400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x19c0b400))
        return iemDecodeA64_SETETN_SET_memcms(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0x3fe0fc00)) == UINT32_C(0x1dc0b400))
        return iemDecodeA64_SETGETN_SET_memcms(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c0c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c0c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0dc0c000))
        return iemDecodeA64_LD1R_asisdlsop_RX1_r(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0ddfc000))
        return iemDecodeA64_LD1R_asisdlsop_R1_i(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x84c0c000))
        return iemDecodeA64_ld1rh_z_p_bi_u32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x85c0c000))
        return iemDecodeA64_ld1rsb_z_p_bi_s16(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c0e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c0e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0dc0e000))
        return iemDecodeA64_LD3R_asisdlsop_RX3_r(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0ddfe000))
        return iemDecodeA64_LD3R_asisdlsop_R3_i(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x84c0e000))
        return iemDecodeA64_ld1rh_z_p_bi_u64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0x85c0e000))
        return iemDecodeA64_ld1rd_z_p_bi_u64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00c0fc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00c0fc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x0ec0fc00))
        return iemDecodeA64_FMLALB_asimdsame2_J(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x08dffc00))
        return iemDecodeA64_LDARB_LR32_ldstord(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x88dffc00))
        return iemDecodeA64_LDAR_LR32_ldstord(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e0fffc00/00e00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e0fffc00_00e00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e000)) == UINT32_C(0x0de00000))
        return iemDecodeA64_LD2_asisdlsop_BX2_r2b(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x1fe00000))
        return iemDecodeA64_FNMADD_H_floatdp3(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee00000))
        return iemDecodeA64_FCVTNS_32H_float2int(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e00000 level 1 - mask=0x801f0000 entries=0x40 valid=%83 (0x35) leaf=%81 (0x34) multi-if=%2 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e00000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_e0fffc00_00e00000_2,
        iemDecodeA64_FCVTNU_32H_float2int,
        iemDecodeA64_SCVTF_H32_float2int,
        iemDecodeA64_UCVTF_H32_float2int,
        iemDecodeA64_FCVTAS_32H_float2int,
        iemDecodeA64_FCVTAU_32H_float2int,
        iemDecodeA64_FMOV_32H_float2int,
        iemDecodeA64_FMOV_H32_float2int,
        iemDecodeA64_FCVTPS_32H_float2int,
        iemDecodeA64_FCVTPU_32H_float2int,
        iemDecodeA64_FCVTNS_sisd_32H,
        iemDecodeA64_FCVTNU_sisd_32H,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_FCVTMS_32H_float2int,
        iemDecodeA64_FCVTMU_32H_float2int,
        iemDecodeA64_FCVTPS_sisd_32H,
        iemDecodeA64_FCVTPU_sisd_32H,
        iemDecodeA64_FCVTMS_sisd_32H,
        iemDecodeA64_FCVTMU_sisd_32H,
        iemDecodeA64_FCVTZS_sisd_32H,
        iemDecodeA64_FCVTZU_sisd_32H,
        iemDecodeA64_FCVTZS_32H_float2int,
        iemDecodeA64_FCVTZU_32H_float2int,
        iemDecodeA64_FCVTAS_sisd_32H,
        iemDecodeA64_FCVTAU_sisd_32H,
        iemDecodeA64_SCVTF_sisd_32H,
        iemDecodeA64_UCVTF_sisd_32H,
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_LD2_asisdlsop_B2_i2b,
        iemDecodeA64_FCVTNS_64H_float2int,
        iemDecodeA64_FCVTNU_64H_float2int,
        iemDecodeA64_SCVTF_H64_float2int,
        iemDecodeA64_UCVTF_H64_float2int,
        iemDecodeA64_FCVTAS_64H_float2int,
        iemDecodeA64_FCVTAU_64H_float2int,
        iemDecodeA64_FMOV_64H_float2int,
        iemDecodeA64_FMOV_H64_float2int,
        iemDecodeA64_FCVTPS_64H_float2int,
        iemDecodeA64_FCVTPU_64H_float2int,
        iemDecodeA64_FCVTNS_sisd_64H,
        iemDecodeA64_FCVTNU_sisd_64H,
        iemDecodeA64_Invalid, // 44
        iemDecodeA64_Invalid, // 45
        iemDecodeA64_Invalid, // 46
        iemDecodeA64_Invalid, // 47
        iemDecodeA64_FCVTMS_64H_float2int,
        iemDecodeA64_FCVTMU_64H_float2int,
        iemDecodeA64_FCVTPS_sisd_64H,
        iemDecodeA64_FCVTPU_sisd_64H,
        iemDecodeA64_FCVTMS_sisd_64H,
        iemDecodeA64_FCVTMU_sisd_64H,
        iemDecodeA64_FCVTZS_sisd_64H,
        iemDecodeA64_FCVTZU_sisd_64H,
        iemDecodeA64_FCVTZS_64H_float2int,
        iemDecodeA64_FCVTZU_64H_float2int,
        iemDecodeA64_FCVTAS_sisd_64H,
        iemDecodeA64_FCVTAU_sisd_64H,
        iemDecodeA64_SCVTF_sisd_64H,
        iemDecodeA64_UCVTF_sisd_64H,
        iemDecodeA64_Invalid, // 62
        iemDecodeA64_Invalid, // 63
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x40);

    /* fMask=0x801f0000 -> 0x0000003f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000020)) /* bit 31 L 1 -> 5 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00e00400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e00400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0x1ee00400))
        return iemDecodeA64_FCCMP_H_floatccmp(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0x1ee00410))
        return iemDecodeA64_FCCMPE_H_floatccmp(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19e00400))
        return iemDecodeA64_LDTADDAL_32_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e00800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e00800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04e00800))
        return iemDecodeA64_addpt_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19e00800))
        return iemDecodeA64_RCWCASAL_C64_rcwcomswap(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ee00800))
        return iemDecodeA64_FMUL_H_floatdp2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e00c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e00c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x1ee00c00))
        return iemDecodeA64_FCSEL_H_floatsel(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04e00c00))
        return iemDecodeA64_subpt_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19e00c00))
        return iemDecodeA64_RCWCASPAL_C64_rcwcomswappr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e01000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e01000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe01fe0)) == UINT32_C(0x1ee01000))
        return iemDecodeA64_FMOV_H_floatimm(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19e01000))
        return iemDecodeA64_LDCLRPAL_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61e0fc18/01e02000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61e0fc18_01e02000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e000)) == UINT32_C(0x0de02000))
        return iemDecodeA64_LD4_asisdlsop_BX4_r4b(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfffe000)) == UINT32_C(0x0dff2000))
        return iemDecodeA64_LD4_asisdlsop_B4_i4b(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e02000 level 1 - mask=0x1000018 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e02000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_FCMP_H_floatcmp,
        iemDecodeA64_FCMP_HZ_floatcmp,
        iemDecodeA64_FCMPE_H_floatcmp,
        iemDecodeA64_FCMPE_HZ_floatcmp,
        iemDecodeA64_61e0fc18_01e02000_2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x01000018 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000004)) /* bit 24 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00e03000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e03000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x04e03000))
        return iemDecodeA64_bic_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19e03000))
        return iemDecodeA64_LDSETPAL_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60effc00/00e04000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60effc00_00e04000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e400)) == UINT32_C(0x0de04000))
        return iemDecodeA64_LD2_asisdlsop_HX2_r2h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee04000))
        return iemDecodeA64_FMOV_H_floatdp1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e04000 level 1 - mask=0xf0000 entries=0x10 valid=%50 (0x8) leaf=%44 (0x7) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e04000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60effc00_00e04000_2,
        iemDecodeA64_FNEG_H_floatdp1,
        iemDecodeA64_FCVT_SH_floatdp1,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_FRINTN_H_floatdp1,
        iemDecodeA64_FRINTM_H_floatdp1,
        iemDecodeA64_FRINTA_H_floatdp1,
        iemDecodeA64_FRINTX_H_floatdp1,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_LD2_asisdlsop_H2_i2h,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x000f0000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000000f)) /* bit 16 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00e06000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e06000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0e400)) == UINT32_C(0x0de06000))
        return iemDecodeA64_LD4_asisdlsop_HX4_r4h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfffe400)) == UINT32_C(0x0dff6000))
        return iemDecodeA64_LD4_asisdlsop_H4_i4h(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e07c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e07c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x08e07c00))
        return iemDecodeA64_CASAB_C32_comswap(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x88e07c00))
        return iemDecodeA64_CASA_C32_comswap(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e08000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e08000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0ec00)) == UINT32_C(0x0de08000))
        return iemDecodeA64_LD2_asisdlsop_SX2_r2s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0dff8000))
        return iemDecodeA64_LD2_asisdlsop_S2_i2s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe08000)) == UINT32_C(0x1fe08000))
        return iemDecodeA64_FNMSUB_H_floatdp3(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19e08000))
        return iemDecodeA64_SWPPAL_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e08400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e08400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0de08400))
        return iemDecodeA64_LD2_asisdlsop_DX2_r2d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0dff8400))
        return iemDecodeA64_LD2_asisdlsop_D2_i2d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19e08400))
        return iemDecodeA64_SWPTAL_32_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e08800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e08800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0ef98800))
        return iemDecodeA64_FRINTP_asimdmiscfp16_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x1ee08800))
        return iemDecodeA64_FNMUL_H_floatdp2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e0a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e0a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0ec00)) == UINT32_C(0x0de0a000))
        return iemDecodeA64_LD4_asisdlsop_SX4_r4s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfffec00)) == UINT32_C(0x0dffa000))
        return iemDecodeA64_LD4_asisdlsop_S4_i4s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x19e0a000))
        return iemDecodeA64_RCWSWPPAL_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e0a400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e0a400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x0de0a400))
        return iemDecodeA64_LD4_asisdlsop_DX4_r4d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0dffa400))
        return iemDecodeA64_LD4_asisdlsop_D4_i4d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc00/00e0c000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc00_00e0c000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0de0c000))
        return iemDecodeA64_LD2R_asisdlsop_RX2_r(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04e0c000))
        return iemDecodeA64_sqincd_z_zs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x1ee0c000))
        return iemDecodeA64_FABS_H_floatdp1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e0c000 level 1 - mask=0x170000 entries=0x10 valid=%50 (0x8) leaf=%44 (0x7) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e0c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60f7fc00_00e0c000_2,
        iemDecodeA64_FSQRT_H_floatdp1,
        iemDecodeA64_FCVT_DH_floatdp1,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_FRINTP_H_floatdp1,
        iemDecodeA64_FRINTZ_H_floatdp1,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_FRINTI_H_floatdp1,
        iemDecodeA64_incd_z_zs,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_LD2R_asisdlsop_R2_i,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00170000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000007)) /* bit 16 L 3 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/00e0c400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e0c400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04e0c400))
        return iemDecodeA64_uqincd_z_zs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04f0c400))
        return iemDecodeA64_decd_z_zs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e0c800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e0c800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0ef8c800))
        return iemDecodeA64_FCMGT_asimdmiscfp16_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04e0c800))
        return iemDecodeA64_sqdecd_z_zs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e0d800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e0d800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0ef8d800))
        return iemDecodeA64_FCMEQ_asimdmiscfp16_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0ef9d800))
        return iemDecodeA64_FRECPE_asimdmiscfp16_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e0e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e0e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0f000)) == UINT32_C(0x0de0e000))
        return iemDecodeA64_LD4R_asisdlsop_RX4_r(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffff000)) == UINT32_C(0x0dffe000))
        return iemDecodeA64_LD4R_asisdlsop_R4_i(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04e0e000))
        return iemDecodeA64_cntd_r_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04f0e000))
        return iemDecodeA64_incd_r_rs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e0f000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e0f000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04e0f000))
        return iemDecodeA64_sqincd_r_rs_sx(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04f0f000))
        return iemDecodeA64_sqincd_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e0f400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e0f400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04e0f400))
        return iemDecodeA64_uqincd_r_rs_uw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04f0f400))
        return iemDecodeA64_uqincd_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e0f800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e0f800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x0ef8f800))
        return iemDecodeA64_FABS_asimdmiscfp16_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04e0f800))
        return iemDecodeA64_sqdecd_r_rs_sx(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04f0f800))
        return iemDecodeA64_sqdecd_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/00e0fc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_00e0fc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x08e0fc00))
        return iemDecodeA64_CASALB_C32_comswap(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x88e0fc00))
        return iemDecodeA64_CASAL_C32_comswap(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04e0fc00))
        return iemDecodeA64_uqdecd_r_rs_uw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc00)) == UINT32_C(0x04f0fc00))
        return iemDecodeA64_uqdecd_r_rs_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ffe0fc00/24000000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ffe0fc00_24000000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x24000000))
        return iemDecodeA64_cmphs_p_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x24000010))
        return iemDecodeA64_cmphi_p_p_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ffe0fc00/25000000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ffe0fc00_25000000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x25000000))
        return iemDecodeA64_cmpge_p_p_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x25000010))
        return iemDecodeA64_cmpgt_p_p_zi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ffe0fc00/a0000000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ffe0fc00_a0000000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0000000))
        return iemDecodeA64_ld1b_mz_p_br_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0000001))
        return iemDecodeA64_ldnt1b_mz_p_br_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ffe0fc00/a1000000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ffe0fc00_a1000000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1000000))
        return iemDecodeA64_ld1b_mzx_p_br_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1000008))
        return iemDecodeA64_ldnt1b_mzx_p_br_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20000000 level 1 - mask=0x9f000000 entries=0x40 valid=%64 (0x29) leaf=%58 (0x25) multi-if=%6 (0x4) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20000000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ffe0fc00_24000000_2,
        iemDecodeA64_ffe0fc00_25000000_2,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_STNP_32_ldstnapair_offs,
        iemDecodeA64_STP_32_ldstpair_off,
        iemDecodeA64_ORR_32_log_shift,
        iemDecodeA64_ADDS_32_addsub_shift,
        iemDecodeA64_STNP_S_ldstnapair_offs,
        iemDecodeA64_STP_S_ldstpair_off,
        iemDecodeA64_EXT_asimdext_only,
        iemDecodeA64_MLA_asimdelem_R,
        iemDecodeA64_Invalid, // 16
        iemDecodeA64_ADDS_32S_addsub_imm,
        iemDecodeA64_ORR_32_log_imm,
        iemDecodeA64_BFM_32M_bitfield,
        iemDecodeA64_CBZ_32_compbranch,
        iemDecodeA64_CBNZ_32_compbranch,
        iemDecodeA64_TBZ_only_testbranch,
        iemDecodeA64_TBNZ_only_testbranch,
        iemDecodeA64_STURB_32_ldst_unscaled,
        iemDecodeA64_STRB_32_ldst_pos,
        iemDecodeA64_ADCS_32_addsub_carry,
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_STUR_B_ldst_unscaled,
        iemDecodeA64_STR_B_ldst_pos,
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
        iemDecodeA64_ffe0fc00_a0000000_2,
        iemDecodeA64_ffe0fc00_a1000000_2,
        iemDecodeA64_Invalid, // 34
        iemDecodeA64_Invalid, // 35
        iemDecodeA64_ld1rqb_z_p_br_contiguous,
        iemDecodeA64_ld1rqw_z_p_br_contiguous,
        iemDecodeA64_Invalid, // 38
        iemDecodeA64_Invalid, // 39
        iemDecodeA64_STNP_64_ldstnapair_offs,
        iemDecodeA64_STP_64_ldstpair_off,
        iemDecodeA64_ORR_64_log_shift,
        iemDecodeA64_ADDS_64_addsub_shift,
        iemDecodeA64_STNP_Q_ldstnapair_offs,
        iemDecodeA64_STP_Q_ldstpair_off,
        iemDecodeA64_Invalid, // 46
        iemDecodeA64_Invalid, // 47
        iemDecodeA64_Invalid, // 48
        iemDecodeA64_ADDS_64S_addsub_imm,
        iemDecodeA64_ORR_64_log_imm,
        iemDecodeA64_Invalid, // 51
        iemDecodeA64_CBZ_64_compbranch,
        iemDecodeA64_CBNZ_64_compbranch,
        iemDecodeA64_Invalid, // 54
        iemDecodeA64_Invalid, // 55
        iemDecodeA64_STUR_32_ldst_unscaled,
        iemDecodeA64_STR_32_ldst_pos,
        iemDecodeA64_ADCS_64_addsub_carry,
        iemDecodeA64_Invalid, // 59
        iemDecodeA64_STUR_S_ldst_unscaled,
        iemDecodeA64_STR_S_ldst_pos,
        iemDecodeA64_Invalid, // 62
        iemDecodeA64_Invalid, // 63
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x40);

    /* fMask=0x9f000000 -> 0x0000003f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x0000001f)) /* bit 24 L 5 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000020)) /* bit 31 L 1 -> 5 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e6e0fc00/26000400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e6e0fc00_26000400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f000400))
        return iemDecodeA64_USHR_asimdshf_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff89c00)) == UINT32_C(0x2f000400))
        return iemDecodeA64_MVNI_asimdimm_L_sl(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20000400 level 1 - mask=0x86000000 entries=0x8 valid=%75 (0x6) leaf=%62 (0x5) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20000400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_STRB_32_ldst_immpost,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_STR_B_ldst_immpost,
        iemDecodeA64_e6e0fc00_26000400_2,
        iemDecodeA64_STR_32_ldst_immpost,
        iemDecodeA64_RMIF_only_rmif,
        iemDecodeA64_STR_S_ldst_immpost,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x86000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 25) & UINT32_C(0x00000003)) /* bit 25 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20000800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20000800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38000800))
        return iemDecodeA64_STTRB_32_ldst_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8000800))
        return iemDecodeA64_STTR_32_ldst_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0x3a00080d))
        return iemDecodeA64_SETF8_only_setf(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20000c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20000c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38000c00))
        return iemDecodeA64_STRB_32_ldst_immpre(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3c000c00))
        return iemDecodeA64_STR_B_ldst_immpre(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8000c00))
        return iemDecodeA64_STR_32_ldst_immpre(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xbc000c00))
        return iemDecodeA64_STR_S_ldst_immpre(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20001400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20001400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f001400))
        return iemDecodeA64_USRA_asimdshf_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff89c00)) == UINT32_C(0x2f001400))
        return iemDecodeA64_BIC_asimdimm_L_sl(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67e0fc10/20002000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67e0fc10_20002000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0002000))
        return iemDecodeA64_ld1h_mz_p_br_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0002001))
        return iemDecodeA64_ldnt1h_mz_p_br_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67e0fc10/21002000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67e0fc10_21002000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1002000))
        return iemDecodeA64_ld1h_mzx_p_br_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1002008))
        return iemDecodeA64_ldnt1h_mzx_p_br_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67e0fc10/24002000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67e0fc10_24002000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x24002000))
        return iemDecodeA64_cmpeq_p_p_zw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4002000))
        return iemDecodeA64_ld1rqb_z_p_bi_u8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67e0fc10/25002000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67e0fc10_25002000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x25002000))
        return iemDecodeA64_cmplt_p_p_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5002000))
        return iemDecodeA64_ld1rqw_z_p_bi_u32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5102000))
        return iemDecodeA64_ld1w_z_p_bi_u128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20002000 level 1 - mask=0x7000010 entries=0x10 valid=%44 (0x7) leaf=%19 (0x3) multi-if=%25 (0x4) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20002000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_67e0fc10_20002000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_67e0fc10_21002000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_67e0fc10_24002000_2,
        iemDecodeA64_cmpne_p_p_zw,
        iemDecodeA64_67e0fc10_25002000_2,
        iemDecodeA64_cmple_p_p_zi,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_UMLAL_asimdelem_L,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x07000010 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x0000000e)) /* bit 24 L 3 -> 1 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 63e0fe10/20004000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_63e0fe10_20004000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x24004000))
        return iemDecodeA64_cmpge_p_p_zw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4004000))
        return iemDecodeA64_ld1b_z_p_br_u8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0004000))
        return iemDecodeA64_ld1w_mz_p_br_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0004001))
        return iemDecodeA64_ldnt1w_mz_p_br_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7f8fe10/a1004000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_e7f8fe10_a1004000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1004000))
        return iemDecodeA64_ld1w_mzx_p_br_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1004008))
        return iemDecodeA64_ldnt1w_mzx_p_br_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 63e0fe10/21004000 level 2 - mask=0x84180000 entries=0x10 valid=%31 (0x5) leaf=%25 (0x4) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_63e0fe10_21004000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_and_p_p_pp_z,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_brka_p_p_p,
        iemDecodeA64_brkn_p_p_pp,
        iemDecodeA64_e7f8fe10_a1004000_3,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_ld1sh_z_p_br_s64,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x84180000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 19) & UINT32_C(0x00000003)) /* bit 19 L 2 -> 0 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20004000 level 1 - mask=0x3000210 entries=0x10 valid=%44 (0x7) leaf=%31 (0x5) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20004000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_63e0fe10_20004000_2,
        iemDecodeA64_cmpgt_p_p_zw,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_63e0fe10_21004000_2,
        iemDecodeA64_bic_p_p_pp_z,
        iemDecodeA64_eor_p_p_pp_z,
        iemDecodeA64_sel_p_p_pp,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_MLS_asimdelem_R,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x03000210 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >>  8) & UINT32_C(0x00000002)) /* bit  9 L 1 -> 1 */
                        | ((uOpcode >> 22) & UINT32_C(0x0000000c)) /* bit 24 L 2 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e7e0fc00/24006000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e7e0fc00_24006000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x24006000))
        return iemDecodeA64_cmplt_p_p_zw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x24006010))
        return iemDecodeA64_cmple_p_p_zw(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7e0fc00/a0006000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e7e0fc00_a0006000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0006000))
        return iemDecodeA64_ld1d_mz_p_br_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0006001))
        return iemDecodeA64_ldnt1d_mz_p_br_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7e0fc00/a1006000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e7e0fc00_a1006000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1006000))
        return iemDecodeA64_ld1d_mzx_p_br_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1006008))
        return iemDecodeA64_ldnt1d_mzx_p_br_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20006000 level 1 - mask=0x87000000 entries=0x10 valid=%38 (0x6) leaf=%19 (0x3) multi-if=%19 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20006000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_e7e0fc00_24006000_2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_UMLSL_asimdelem_L,
        iemDecodeA64_e7e0fc00_a0006000_2,
        iemDecodeA64_e7e0fc00_a1006000_2,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_ldff1b_z_p_br_u8,
        iemDecodeA64_ldff1sh_z_p_br_s64,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x87000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000007)) /* bit 24 L 3 -> 0 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 67e0fc10/20008000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67e0fc10_20008000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa0008000))
        return iemDecodeA64_ld1b_mz_p_br_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa0008001))
        return iemDecodeA64_ldnt1b_mz_p_br_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67e0fc10/21008000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67e0fc10_21008000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa1008000))
        return iemDecodeA64_ld1b_mzx_p_br_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa1008008))
        return iemDecodeA64_ldnt1b_mzx_p_br_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67e0fc10/25008000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67e0fc10_25008000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x25008000))
        return iemDecodeA64_cmpeq_p_p_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5008000))
        return iemDecodeA64_ld1w_z_p_br_u128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20008000 level 1 - mask=0x7000010 entries=0x10 valid=%44 (0x7) leaf=%25 (0x4) multi-if=%19 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20008000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_67e0fc10_20008000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_67e0fc10_21008000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_cmpge_p_p_zz,
        iemDecodeA64_cmpgt_p_p_zz,
        iemDecodeA64_67e0fc10_25008000_2,
        iemDecodeA64_cmpne_p_p_zi,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_FMLALLBB_asimdelem_J,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x07000010 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x0000000e)) /* bit 24 L 3 -> 1 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20008400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20008400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e008400))
        return iemDecodeA64_SQRDMLAH_asimdsame2_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f008400))
        return iemDecodeA64_SQSHRUN_asimdshf_N(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff8dc00)) == UINT32_C(0x2f008400))
        return iemDecodeA64_MVNI_asimdimm_L_hl(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20008c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20008c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e008c00))
        return iemDecodeA64_SQRDMLSH_asimdsame2_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f008c00))
        return iemDecodeA64_SQRSHRUN_asimdshf_N(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20009400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20009400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e009400))
        return iemDecodeA64_UDOT_asimdsame2_D(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f009400))
        return iemDecodeA64_UQSHRN_asimdshf_N(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff8dc00)) == UINT32_C(0x2f009400))
        return iemDecodeA64_BIC_asimdimm_L_hl(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67f0fc00/2000a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67f0fc00_2000a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa000a000))
        return iemDecodeA64_ld1h_mz_p_br_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa000a001))
        return iemDecodeA64_ldnt1h_mz_p_br_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67f0fc00/2100a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67f0fc00_2100a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa100a000))
        return iemDecodeA64_ld1h_mzx_p_br_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa100a008))
        return iemDecodeA64_ldnt1h_mzx_p_br_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 67f0fc00/2400a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67f0fc00_2400a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x2400a000))
        return iemDecodeA64_cmpeq_p_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x2400a010))
        return iemDecodeA64_cmpne_p_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa400a000))
        return iemDecodeA64_ld1b_z_p_bi_u8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2000a000 level 1 - mask=0x7100000 entries=0x10 valid=%44 (0x7) leaf=%25 (0x4) multi-if=%19 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2000a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_67f0fc00_2000a000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_67f0fc00_2100a000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_67f0fc00_2400a000_2,
        iemDecodeA64_ldnf1b_z_p_bi_u8,
        iemDecodeA64_ld1sh_z_p_bi_s64,
        iemDecodeA64_ldnf1sh_z_p_bi_s64,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_UMULL_asimdelem_L,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x07100000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 20) & UINT32_C(0x00000001)) /* bit 20 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x0000000e)) /* bit 24 L 3 -> 1 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 65e0fc10/2000c000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc10_2000c000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa000c000))
        return iemDecodeA64_ld1w_mz_p_br_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa000c001))
        return iemDecodeA64_ldnt1w_mz_p_br_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc10/2100c000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc10_2100c000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa100c000))
        return iemDecodeA64_ld1w_mzx_p_br_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa100c008))
        return iemDecodeA64_ldnt1w_mzx_p_br_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc10/2400c000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc10_2400c000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x2400c000))
        return iemDecodeA64_cmphs_p_p_zw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa400c000))
        return iemDecodeA64_ldnt1b_z_p_br_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc10/2500c000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc10_2500c000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa500c000))
        return iemDecodeA64_ldnt1w_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x2500c000))
        return iemDecodeA64_brkpa_p_p_pp(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2000c000 level 1 - mask=0x5000010 entries=0x8 valid=%75 (0x6) leaf=%25 (0x2) multi-if=%50 (0x4) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2000c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_65e0fc10_2000c000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_65e0fc10_2100c000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_65e0fc10_2400c000_2,
        iemDecodeA64_cmphi_p_p_zw,
        iemDecodeA64_65e0fc10_2500c000_2,
        iemDecodeA64_brkpb_p_p_pp,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x05000010 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/2000c400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2000c400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20e400)) == UINT32_C(0x2e00c400))
        return iemDecodeA64_FCMLA_asimdsame2_C(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbff8ec00)) == UINT32_C(0x2f00c400))
        return iemDecodeA64_MVNI_asimdimm_M_sm(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffe10)) == UINT32_C(0x2519c400))
        return iemDecodeA64_pnext_p_p_p(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7e0fc00/2400e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e7e0fc00_2400e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x2400e000))
        return iemDecodeA64_cmplo_p_p_zw(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x2400e010))
        return iemDecodeA64_cmpls_p_p_zw(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7e0fc00/2500e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e7e0fc00_2500e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc10)) == UINT32_C(0x2518e000))
        return iemDecodeA64_ptrue_p_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffc10)) == UINT32_C(0x2519e000))
        return iemDecodeA64_ptrues_p_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7e0fc00/a000e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e7e0fc00_a000e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa000e000))
        return iemDecodeA64_ld1d_mz_p_br_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa000e001))
        return iemDecodeA64_ldnt1d_mz_p_br_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7e0fc00/a100e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e7e0fc00_a100e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa100e000))
        return iemDecodeA64_ld1d_mzx_p_br_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa100e008))
        return iemDecodeA64_ldnt1d_mzx_p_br_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7e0fc00/a500e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e7e0fc00_a500e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa500e000))
        return iemDecodeA64_ldnt1w_z_p_bi_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa510e000))
        return iemDecodeA64_ld3q_z_p_bi_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2000e000 level 1 - mask=0x87000000 entries=0x10 valid=%44 (0x7) leaf=%12 (0x2) multi-if=%31 (0x5) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2000e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_e7e0fc00_2400e000_2,
        iemDecodeA64_e7e0fc00_2500e000_2,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_UDOT_asimdelem_D,
        iemDecodeA64_e7e0fc00_a000e000_2,
        iemDecodeA64_e7e0fc00_a100e000_2,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_ldnt1b_z_p_bi_contiguous,
        iemDecodeA64_e7e0fc00_a500e000_2,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x87000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000007)) /* bit 24 L 3 -> 0 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/2000e400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2000e400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20ec00)) == UINT32_C(0x2e00e400))
        return iemDecodeA64_FCADD_asimdsame2_C(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf80fc00)) == UINT32_C(0x2f00e400))
        return iemDecodeA64_UCVTF_asimdshf_C(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff8fc00)) == UINT32_C(0x2f00e400))
        return iemDecodeA64_MOVI_asimdimm_D_ds(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffff0)) == UINT32_C(0x2518e400))
        return iemDecodeA64_pfalse_p(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2000f000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2000f000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf00f400)) == UINT32_C(0x2f00f000))
        return iemDecodeA64_SQRDMLSH_asimdelem_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffe10)) == UINT32_C(0x2518f000))
        return iemDecodeA64_rdffr_p_p_f(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffff0)) == UINT32_C(0x2519f000))
        return iemDecodeA64_rdffr_p_f(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e3e0fc10/20200000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e3e0fc10_20200000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff202010)) == UINT32_C(0x24200000))
        return iemDecodeA64_cmphs_p_p_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38200000))
        return iemDecodeA64_LDADDB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3c200000))
        return iemDecodeA64_LDBFADD_16(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e3e0fc10/22200000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e3e0fc10_22200000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e200000))
        return iemDecodeA64_UADDL_asimddiff_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff200000)) == UINT32_C(0x2a200000))
        return iemDecodeA64_ORN_32_log_shift(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e3e0fc10/a0200000 level 2 - mask=0x1c000001 entries=0x10 valid=%31 (0x5) leaf=%31 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_e3e0fc10_a0200000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_st1b_mz_p_br_2,
        iemDecodeA64_stnt1b_mz_p_br_2,
        iemDecodeA64_ld1rob_z_p_br_contiguous,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LDADD_32_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_LDFADD_32,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x1c000001 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x0000000e)) /* bit 26 L 3 -> 1 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e3e0fc10/a1200000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e3e0fc10_a1200000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5200000))
        return iemDecodeA64_ld1row_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1200000))
        return iemDecodeA64_st1b_mzx_p_br_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1200008))
        return iemDecodeA64_stnt1b_mzx_p_br_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20200000 level 1 - mask=0x83000010 entries=0x10 valid=%62 (0xa) leaf=%38 (0x6) multi-if=%19 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20200000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_e3e0fc10_20200000_2,
        iemDecodeA64_cmphi_p_p_zi,
        iemDecodeA64_whilege_p_p_rr,
        iemDecodeA64_whilegt_p_p_rr,
        iemDecodeA64_e3e0fc10_22200000_2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_ADDS_32S_addsub_ext,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_e3e0fc10_a0200000_2,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_e3e0fc10_a1200000_2,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_ORN_64_log_shift,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_ADDS_64S_addsub_ext,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x83000010 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000006)) /* bit 24 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20200400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20200400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e200400))
        return iemDecodeA64_UHADD_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20ec10)) == UINT32_C(0x25200400))
        return iemDecodeA64_whilelt_p_p_rr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20ec10)) == UINT32_C(0x25200410))
        return iemDecodeA64_whilele_p_p_rr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7e0fc00/25200800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e7e0fc00_25200800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20ec10)) == UINT32_C(0x25200800))
        return iemDecodeA64_whilehs_p_p_rr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20ec10)) == UINT32_C(0x25200810))
        return iemDecodeA64_whilehi_p_p_rr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20200800 level 1 - mask=0x87000000 entries=0x10 valid=%38 (0x6) leaf=%31 (0x5) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20200800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_STRB_32B_ldst_regoff,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_STR_B_ldst_regoff,
        iemDecodeA64_e7e0fc00_25200800_2,
        iemDecodeA64_REV32_asimdmisc_R,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_STR_32_ldst_regoff,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_STR_S_ldst_regoff,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x87000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000007)) /* bit 24 L 3 -> 0 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20200c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20200c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e200c00))
        return iemDecodeA64_UQADD_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20ec10)) == UINT32_C(0x25200c00))
        return iemDecodeA64_whilelo_p_p_rr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20ec10)) == UINT32_C(0x25200c10))
        return iemDecodeA64_whilels_p_p_rr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20201000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20201000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e201000))
        return iemDecodeA64_UADDW_asimddiff_W(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38201000))
        return iemDecodeA64_LDCLRB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8201000))
        return iemDecodeA64_LDCLR_32_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/24202000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_24202000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff202010)) == UINT32_C(0x24202000))
        return iemDecodeA64_cmplo_p_p_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff202010)) == UINT32_C(0x24202010))
        return iemDecodeA64_cmpls_p_p_zi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/a0202000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_a0202000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0202000))
        return iemDecodeA64_st1h_mz_p_br_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0202001))
        return iemDecodeA64_stnt1h_mz_p_br_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/a1202000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_a1202000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1202000))
        return iemDecodeA64_st1h_mzx_p_br_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1202008))
        return iemDecodeA64_stnt1h_mzx_p_br_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20202000 level 1 - mask=0x8d000000 entries=0x10 valid=%50 (0x8) leaf=%31 (0x5) multi-if=%19 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20202000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_ede0fc00_24202000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDEORB_32_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_USUBL_asimddiff_L,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_ede0fc00_a0202000_2,
        iemDecodeA64_ede0fc00_a1202000_2,
        iemDecodeA64_ld1rob_z_p_bi_u8,
        iemDecodeA64_ld1row_z_p_bi_u32,
        iemDecodeA64_LDEOR_32_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8d000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20202800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20202800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e202800))
        return iemDecodeA64_UADDLP_asimdmisc_P(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e212800))
        return iemDecodeA64_SQXTUN_asimdmisc_N(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20203000 level 1 - mask=0x83000010 entries=0x10 valid=%31 (0x5) leaf=%31 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20203000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LDSETB_32_memop,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_whilewr_p_rr,
        iemDecodeA64_whilerw_p_rr,
        iemDecodeA64_USUBW_asimddiff_W,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_LDSET_32_memop,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x83000010 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000006)) /* bit 24 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20203800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20203800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e203800))
        return iemDecodeA64_USQADD_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e213800))
        return iemDecodeA64_SHLL_asimdmisc_S(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e303800))
        return iemDecodeA64_UADDLV_asimdall_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc08/24204000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc08_24204000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20c210)) == UINT32_C(0x25204000))
        return iemDecodeA64_psel_p_ppi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20dc18)) == UINT32_C(0x25204010))
        return iemDecodeA64_whilege_pn_rr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc08/2c204000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc08_2c204000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e204000))
        return iemDecodeA64_RADDHN_asimddiff_N(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3c204000))
        return iemDecodeA64_LDBFMAX_16(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc08/a0204000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc08_a0204000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0204000))
        return iemDecodeA64_st1w_mz_p_br_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0204001))
        return iemDecodeA64_stnt1w_mz_p_br_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1204000))
        return iemDecodeA64_st1w_mzx_p_br_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc08/a4204000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc08_a4204000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4204000))
        return iemDecodeA64_ld1b_z_p_br_u16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5204000))
        return iemDecodeA64_ld1sh_z_p_br_s32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20204000 level 1 - mask=0x8c000008 entries=0x10 valid=%56 (0x9) leaf=%31 (0x5) multi-if=%25 (0x4) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20204000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_ece0fc08_24204000_2,
        iemDecodeA64_whilegt_pn_rr,
        iemDecodeA64_LDSMAXB_32_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_ece0fc08_2c204000_2,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_ece0fc08_a0204000_2,
        iemDecodeA64_stnt1w_mzx_p_br_2x8,
        iemDecodeA64_ece0fc08_a4204000_2,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LDSMAX_32_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_LDFMAX_32,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8c000008 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000001)) /* bit  3 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20204400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20204400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e204400))
        return iemDecodeA64_USHL_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20dc18)) == UINT32_C(0x25204410))
        return iemDecodeA64_whilelt_pn_rr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20dc18)) == UINT32_C(0x25204418))
        return iemDecodeA64_whilele_pn_rr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20204800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20204800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e204800))
        return iemDecodeA64_CLZ_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e214800))
        return iemDecodeA64_UQXTN_asimdmisc_N(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20dc18)) == UINT32_C(0x25204810))
        return iemDecodeA64_whilehs_pn_rr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20dc18)) == UINT32_C(0x25204818))
        return iemDecodeA64_whilehi_pn_rr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20204c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20204c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e204c00))
        return iemDecodeA64_UQSHL_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20dc18)) == UINT32_C(0x25204c10))
        return iemDecodeA64_whilelo_pn_rr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20dc18)) == UINT32_C(0x25204c18))
        return iemDecodeA64_whilels_pn_rr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7e0fc00/25205000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e7e0fc00_25205000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc11)) == UINT32_C(0x25205010))
        return iemDecodeA64_whilege_pp_rr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc11)) == UINT32_C(0x25205011))
        return iemDecodeA64_whilegt_pp_rr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20205000 level 1 - mask=0x87000000 entries=0x10 valid=%38 (0x6) leaf=%31 (0x5) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20205000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LDSMINB_32_memop,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDBFMIN_16,
        iemDecodeA64_e7e0fc00_25205000_2,
        iemDecodeA64_UABAL_asimddiff_L,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_LDSMIN_32_memop,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LDFMIN_32,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x87000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000007)) /* bit 24 L 3 -> 0 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20205400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20205400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e205400))
        return iemDecodeA64_URSHL_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc11)) == UINT32_C(0x25205410))
        return iemDecodeA64_whilelt_pp_rr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc11)) == UINT32_C(0x25205411))
        return iemDecodeA64_whilele_pp_rr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20205800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20205800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2e205800))
        return iemDecodeA64_NOT_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc11)) == UINT32_C(0x25205810))
        return iemDecodeA64_whilehs_pp_rr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc11)) == UINT32_C(0x25205811))
        return iemDecodeA64_whilehi_pp_rr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20205c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20205c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e205c00))
        return iemDecodeA64_UQRSHL_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc11)) == UINT32_C(0x25205c10))
        return iemDecodeA64_whilelo_pp_rr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc11)) == UINT32_C(0x25205c11))
        return iemDecodeA64_whilels_pp_rr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/2c206000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_2c206000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e206000))
        return iemDecodeA64_RSUBHN_asimddiff_N(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3c206000))
        return iemDecodeA64_LDBFMAXNM_16(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/a0206000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_a0206000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0206000))
        return iemDecodeA64_st1d_mz_p_br_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e001)) == UINT32_C(0xa0206001))
        return iemDecodeA64_stnt1d_mz_p_br_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/a1206000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_a1206000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1206000))
        return iemDecodeA64_st1d_mzx_p_br_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e008)) == UINT32_C(0xa1206008))
        return iemDecodeA64_stnt1d_mzx_p_br_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20206000 level 1 - mask=0x8d000000 entries=0x10 valid=%50 (0x8) leaf=%31 (0x5) multi-if=%19 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20206000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDUMAXB_32_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_ede0fc00_2c206000_2,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_ede0fc00_a0206000_2,
        iemDecodeA64_ede0fc00_a1206000_2,
        iemDecodeA64_ldff1b_z_p_br_u16,
        iemDecodeA64_ldff1sh_z_p_br_s32,
        iemDecodeA64_LDUMAX_32_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_LDFMAXNM_32,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8d000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20206800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20206800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e206800))
        return iemDecodeA64_UADALP_asimdmisc_P(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0ec00)) == UINT32_C(0x38206800))
        return iemDecodeA64_STRB_32BL_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0ec00)) == UINT32_C(0x3c206800))
        return iemDecodeA64_STR_BL_ldst_regoff(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20207000 level 1 - mask=0x87000000 entries=0x10 valid=%38 (0x6) leaf=%38 (0x6) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20207000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LDUMINB_32_memop,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDBFMINNM_16,
        iemDecodeA64_pext_pn_rr,
        iemDecodeA64_UABDL_asimddiff_L,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_LDUMIN_32_memop,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LDFMINNM_32,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x87000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000007)) /* bit 24 L 3 -> 0 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20207400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20207400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e207400))
        return iemDecodeA64_UABD_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffe10)) == UINT32_C(0x25207410))
        return iemDecodeA64_pext_pp_rr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20207800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20207800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e207800))
        return iemDecodeA64_SQNEG_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2e217800))
        return iemDecodeA64_F1CVTL_asimdmisc_V(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffff8)) == UINT32_C(0x25207810))
        return iemDecodeA64_ptrue_pn_i(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* eceffc01/24208000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_eceffc01_24208000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fc200)) == UINT32_C(0x25208000))
        return iemDecodeA64_cntp_r_p_p(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffa00)) == UINT32_C(0x25208200))
        return iemDecodeA64_cntp_r_pn(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc01/24208000 level 2 - mask=0xf0000 entries=0x10 valid=%56 (0x9) leaf=%50 (0x8) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc01_24208000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_eceffc01_24208000_3,
        iemDecodeA64_firstp_r_p_p,
        iemDecodeA64_lastp_r_p_p,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_sqincp_z_p_z,
        iemDecodeA64_uqincp_z_p_z,
        iemDecodeA64_sqdecp_z_p_z,
        iemDecodeA64_uqdecp_z_p_z,
        iemDecodeA64_incp_z_p_z,
        iemDecodeA64_decp_z_p_z,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x000f0000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000000f)) /* bit 16 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* ece0fc01/a0208000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc01_a0208000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa0208000))
        return iemDecodeA64_st1b_mz_p_br_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa1208000))
        return iemDecodeA64_st1b_mzx_p_br_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa1208008))
        return iemDecodeA64_stnt1b_mzx_p_br_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20208000 level 1 - mask=0x8c000001 entries=0x10 valid=%56 (0x9) leaf=%44 (0x7) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20208000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_ece0fc01_24208000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_SWPB_32_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_UMLAL_asimddiff_L,
        iemDecodeA64_STBFADD_16,
        iemDecodeA64_ece0fc01_a0208000_2,
        iemDecodeA64_stnt1b_mz_p_br_4,
        iemDecodeA64_ld3q_z_p_br_contiguous,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_SWP_32_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_STFADD_32,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8c000001 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20208800 level 1 - mask=0xf0000 entries=0x10 valid=%50 (0x8) leaf=%50 (0x8) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20208800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_CMGE_asimdmisc_Z,
        iemDecodeA64_FRINTA_asimdmisc_R,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_sqincp_r_p_r_sx,
        iemDecodeA64_uqincp_r_p_r_uw,
        iemDecodeA64_sqdecp_r_p_r_sx,
        iemDecodeA64_uqdecp_r_p_r_uw,
        iemDecodeA64_incp_r_p_r,
        iemDecodeA64_decp_r_p_r,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x000f0000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000000f)) /* bit 16 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20208c00 level 1 - mask=0xb0000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20208c00_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_CMEQ_asimdsame_only,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_sqincp_r_p_r_x,
        iemDecodeA64_uqincp_r_p_r_x,
        iemDecodeA64_sqdecp_r_p_r_x,
        iemDecodeA64_uqdecp_r_p_r_x,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x000b0000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000003)) /* bit 16 L 2 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000004)) /* bit 19 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20209000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20209000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38209000))
        return iemDecodeA64_RCWCLR_64_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffe1f)) == UINT32_C(0x25289000))
        return iemDecodeA64_wrffr_f_p(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0x252c9000))
        return iemDecodeA64_setffr_f(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20209800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20209800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e209800))
        return iemDecodeA64_CMLE_asimdmisc_Z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2e219800))
        return iemDecodeA64_FRINTX_asimdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6df0fc00/2020a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6df0fc00_2020a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa020a000))
        return iemDecodeA64_st1h_mz_p_br_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa020a001))
        return iemDecodeA64_stnt1h_mz_p_br_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6df0fc00/2120a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6df0fc00_2120a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa120a000))
        return iemDecodeA64_st1h_mzx_p_br_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa120a008))
        return iemDecodeA64_stnt1h_mzx_p_br_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2020a000 level 1 - mask=0xd100000 entries=0x10 valid=%50 (0x8) leaf=%38 (0x6) multi-if=%12 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2020a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_6df0fc00_2020a000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_6df0fc00_2120a000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld1b_z_p_bi_u16,
        iemDecodeA64_ldnf1b_z_p_bi_u16,
        iemDecodeA64_ld1sh_z_p_bi_s32,
        iemDecodeA64_ldnf1sh_z_p_bi_s32,
        iemDecodeA64_RCWSWP_64_memop,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_UMLSL_asimddiff_L,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x0d100000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 20) & UINT32_C(0x00000001)) /* bit 20 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x0000000c)) /* bit 26 L 2 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/2020a800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2020a800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e30a800))
        return iemDecodeA64_UMAXV_asimdall_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e31a800))
        return iemDecodeA64_UMINV_asimdall_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2e21a800))
        return iemDecodeA64_FCVTNU_asimdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2020b800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2020b800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf3ffc00)) == UINT32_C(0x2e20b800))
        return iemDecodeA64_NEG_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2e21b800))
        return iemDecodeA64_FCVTMU_asimdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7fffc00/a020c000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_e7fffc00_a020c000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa020c000))
        return iemDecodeA64_st1w_mz_p_br_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e003)) == UINT32_C(0xa020c001))
        return iemDecodeA64_stnt1w_mz_p_br_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7fffc00/a120c000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_e7fffc00_a120c000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa120c000))
        return iemDecodeA64_st1w_mzx_p_br_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa120c008))
        return iemDecodeA64_stnt1w_mzx_p_br_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e7fffc00/a420c000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_e7fffc00_a420c000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa420c000))
        return iemDecodeA64_ld2b_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xbc20c01f))
        return iemDecodeA64_STFMAX_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60fffc00/2020c000 level 2 - mask=0x87000000 entries=0x10 valid=%44 (0x7) leaf=%25 (0x4) multi-if=%19 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60fffc00_2020c000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_STBFMAX_16,
        iemDecodeA64_add_z_zi,
        iemDecodeA64_UMULL_asimddiff_L,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_e7fffc00_a020c000_3,
        iemDecodeA64_e7fffc00_a120c000_3,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_e7fffc00_a420c000_3,
        iemDecodeA64_ld2w_z_p_br_contiguous,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x87000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000007)) /* bit 24 L 3 -> 0 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/2020c000 level 1 - mask=0x1f0000 entries=0x20 valid=%44 (0xe) leaf=%41 (0xd) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2020c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60fffc00_2020c000_2,
        iemDecodeA64_sub_z_zi,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_subr_z_zi,
        iemDecodeA64_sqadd_z_zi,
        iemDecodeA64_uqadd_z_zi,
        iemDecodeA64_sqsub_z_zi,
        iemDecodeA64_uqsub_z_zi,
        iemDecodeA64_smax_z_zi,
        iemDecodeA64_umax_z_zi,
        iemDecodeA64_smin_z_zi,
        iemDecodeA64_umin_z_zi,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_mul_z_zi,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_dup_z_i,
        iemDecodeA64_fdup_z_i,
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x001f0000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/2020d000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2020d000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x3c20d01f))
        return iemDecodeA64_STBFMIN_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xbc20d01f))
        return iemDecodeA64_STFMIN_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2020dc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2020dc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e20dc00))
        return iemDecodeA64_FAMIN_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x2e20dc00))
        return iemDecodeA64_FMUL_asimdsame_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc01/2120e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc01_2120e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa120e000))
        return iemDecodeA64_st1d_mzx_p_br_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e00c)) == UINT32_C(0xa120e008))
        return iemDecodeA64_stnt1d_mzx_p_br_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc01/2420e001 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc01_2420e001_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x3c20e01f))
        return iemDecodeA64_STBFMAXNM_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xbc20e01f))
        return iemDecodeA64_STFMAXNM_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2020e000 level 1 - mask=0x5000001 entries=0x8 valid=%75 (0x6) leaf=%50 (0x4) multi-if=%25 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2020e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_st1d_mz_p_br_4,
        iemDecodeA64_stnt1d_mz_p_br_4,
        iemDecodeA64_65e0fc01_2120e000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld2b_z_p_bi_contiguous,
        iemDecodeA64_65e0fc01_2420e001_2,
        iemDecodeA64_ld2w_z_p_bi_contiguous,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x05000001 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/2020f000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2020f000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x3c20f01f))
        return iemDecodeA64_STBFMINNM_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xbc20f01f))
        return iemDecodeA64_STFMINNM_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2020fc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2020fc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbf20fc00)) == UINT32_C(0x2e20fc00))
        return iemDecodeA64_FSCALE_asimdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfa0fc00)) == UINT32_C(0x2e20fc00))
        return iemDecodeA64_FDIV_asimdsame_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* f7e0fc00/a0400000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_f7e0fc00_a0400000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xa8400000))
        return iemDecodeA64_LDNP_64_ldstnapair_offs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0400000))
        return iemDecodeA64_ld1b_mz_p_bi_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0400001))
        return iemDecodeA64_ldnt1b_mz_p_bi_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* f7e0fc00/a1400000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_f7e0fc00_a1400000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc00000)) == UINT32_C(0xa9400000))
        return iemDecodeA64_LDP_64_ldstpair_off(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1400000))
        return iemDecodeA64_ld1b_mzx_p_bi_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1400008))
        return iemDecodeA64_ldnt1b_mzx_p_bi_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20400000 level 1 - mask=0x97000000 entries=0x20 valid=%59 (0x13) leaf=%53 (0x11) multi-if=%6 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20400000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LDNP_32_ldstnapair_offs,
        iemDecodeA64_LDP_32_ldstpair_off,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDNP_S_ldstnapair_offs,
        iemDecodeA64_LDP_S_ldstpair_off,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_LDURB_32_ldst_unscaled,
        iemDecodeA64_LDRB_32_ldst_pos,
        iemDecodeA64_CCMN_32_condcmp_reg,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LDUR_B_ldst_unscaled,
        iemDecodeA64_LDR_B_ldst_pos,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_f7e0fc00_a0400000_2,
        iemDecodeA64_f7e0fc00_a1400000_2,
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_LDNP_Q_ldstnapair_offs,
        iemDecodeA64_LDP_Q_ldstpair_off,
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_LDUR_32_ldst_unscaled,
        iemDecodeA64_LDR_32_ldst_pos,
        iemDecodeA64_CCMN_64_condcmp_reg,
        iemDecodeA64_BFM_64M_bitfield,
        iemDecodeA64_LDUR_S_ldst_unscaled,
        iemDecodeA64_LDR_S_ldst_pos,
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x97000000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000007)) /* bit 24 L 3 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000008)) /* bit 28 L 1 -> 3 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000010)) /* bit 31 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20400400 level 1 - mask=0x86000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20400400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LDRB_32_ldst_immpost,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_LDR_B_ldst_immpost,
        iemDecodeA64_FMAXNMP_asimdsamefp16_only,
        iemDecodeA64_LDR_32_ldst_immpost,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDR_S_ldst_immpost,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x86000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 25) & UINT32_C(0x00000003)) /* bit 25 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20400800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20400800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38400800))
        return iemDecodeA64_LDTRB_32_ldst_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8400800))
        return iemDecodeA64_LDTR_32_ldst_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0x3a400800))
        return iemDecodeA64_CCMN_32_condcmp_imm(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0xba400800))
        return iemDecodeA64_CCMN_64_condcmp_imm(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20400c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20400c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38400c00))
        return iemDecodeA64_LDRB_32_ldst_immpre(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3c400c00))
        return iemDecodeA64_LDR_B_ldst_immpre(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8400c00))
        return iemDecodeA64_LDR_32_ldst_immpre(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xbc400c00))
        return iemDecodeA64_LDR_S_ldst_immpre(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20402000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20402000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0402000))
        return iemDecodeA64_ld1h_mz_p_bi_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0402001))
        return iemDecodeA64_ldnt1h_mz_p_bi_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1402000))
        return iemDecodeA64_ld1h_mzx_p_bi_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1402008))
        return iemDecodeA64_ldnt1h_mzx_p_bi_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc10/20404000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc10_20404000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0404000))
        return iemDecodeA64_ld1w_mz_p_bi_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0404001))
        return iemDecodeA64_ldnt1w_mz_p_bi_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc10/21404000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc10_21404000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1404000))
        return iemDecodeA64_ld1w_mzx_p_bi_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1404008))
        return iemDecodeA64_ldnt1w_mzx_p_bi_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc10/25404000 level 2 - mask=0x80180200 entries=0x10 valid=%31 (0x5) leaf=%31 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc10_25404000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ands_p_p_pp_z,
        iemDecodeA64_eors_p_p_pp_z,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_brkas_p_p_p_z,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_brkns_p_p_pp,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_ld1w_z_p_br_u32,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x80180200 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  9) & UINT32_C(0x00000001)) /* bit  9 L 1 -> 0 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000006)) /* bit 19 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20404000 level 1 - mask=0x5000010 entries=0x8 valid=%62 (0x5) leaf=%25 (0x2) multi-if=%25 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20404000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_65e0fc10_20404000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_65e0fc10_21404000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld1b_z_p_br_u32,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_65e0fc10_25404000_2,
        iemDecodeA64_bics_p_p_pp_z,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x05000010 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 65e0fc01/21406000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc01_21406000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1406000))
        return iemDecodeA64_ld1d_mzx_p_bi_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1406008))
        return iemDecodeA64_ldnt1d_mzx_p_bi_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20406000 level 1 - mask=0x5000001 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20406000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ld1d_mz_p_bi_2,
        iemDecodeA64_ldnt1d_mz_p_bi_2,
        iemDecodeA64_65e0fc01_21406000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ldff1b_z_p_br_u32,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_ldff1w_z_p_br_u32,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x05000001 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 63e0fc01/21408000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_63e0fc01_21408000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa1408000))
        return iemDecodeA64_ld1b_mzx_p_bi_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa1408008))
        return iemDecodeA64_ldnt1b_mzx_p_bi_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20408000 level 1 - mask=0x3000001 entries=0x8 valid=%50 (0x4) leaf=%38 (0x3) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20408000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ld1b_mz_p_bi_4,
        iemDecodeA64_ldnt1b_mz_p_bi_4,
        iemDecodeA64_63e0fc01_21408000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_FMLALLBT_asimdelem_J,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x03000001 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000006)) /* bit 24 L 2 -> 1 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 65f0fc00/2040a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65f0fc00_2040a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa040a000))
        return iemDecodeA64_ld1h_mz_p_bi_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa040a001))
        return iemDecodeA64_ldnt1h_mz_p_bi_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65f0fc00/2140a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65f0fc00_2140a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa140a000))
        return iemDecodeA64_ld1h_mzx_p_bi_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa140a008))
        return iemDecodeA64_ldnt1h_mzx_p_bi_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2040a000 level 1 - mask=0x5100000 entries=0x8 valid=%75 (0x6) leaf=%50 (0x4) multi-if=%25 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2040a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_65f0fc00_2040a000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_65f0fc00_2140a000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld1b_z_p_bi_u32,
        iemDecodeA64_ldnf1b_z_p_bi_u32,
        iemDecodeA64_ld1w_z_p_bi_u32,
        iemDecodeA64_ldnf1w_z_p_bi_u32,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x05100000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 20) & UINT32_C(0x00000001)) /* bit 20 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 65e0fc10/2040c000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc10_2040c000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa040c000))
        return iemDecodeA64_ld1w_mz_p_bi_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa040c001))
        return iemDecodeA64_ldnt1w_mz_p_bi_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc10/2140c000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc10_2140c000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa140c000))
        return iemDecodeA64_ld1w_mzx_p_bi_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa140c008))
        return iemDecodeA64_ldnt1w_mzx_p_bi_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc10/2540c000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc10_2540c000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa540c000))
        return iemDecodeA64_ld3w_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x2540c000))
        return iemDecodeA64_brkpas_p_p_pp(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffc21f)) == UINT32_C(0x2550c000))
        return iemDecodeA64_ptest__p_p(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffe10)) == UINT32_C(0x2558c000))
        return iemDecodeA64_pfirst_p_p_p(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2040c000 level 1 - mask=0x5000010 entries=0x8 valid=%62 (0x5) leaf=%25 (0x2) multi-if=%38 (0x3) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2040c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_65e0fc10_2040c000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_65e0fc10_2140c000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld3b_z_p_br_contiguous,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_65e0fc10_2540c000_2,
        iemDecodeA64_brkpbs_p_p_pp,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x05000010 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 65e0fc01/2140e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc01_2140e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa140e000))
        return iemDecodeA64_ld1d_mzx_p_bi_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa140e008))
        return iemDecodeA64_ldnt1d_mzx_p_bi_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2040e000 level 1 - mask=0x5000001 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2040e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ld1d_mz_p_bi_4,
        iemDecodeA64_ldnt1d_mz_p_bi_4,
        iemDecodeA64_65e0fc01_2140e000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld3b_z_p_bi_contiguous,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_ld3w_z_p_bi_contiguous,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x05000001 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* ece0fc00/a0600000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc00_a0600000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0600000))
        return iemDecodeA64_st1b_mz_p_bi_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0600001))
        return iemDecodeA64_stnt1b_mz_p_bi_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1600000))
        return iemDecodeA64_st1b_mzx_p_bi_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1600008))
        return iemDecodeA64_stnt1b_mzx_p_bi_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20600000 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20600000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_LDADDLB_32_memop,
        iemDecodeA64_LDBFADDL_16,
        iemDecodeA64_ece0fc00_a0600000_2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDADDL_32_memop,
        iemDecodeA64_LDFADDL_32,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20600800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20600800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38600800))
        return iemDecodeA64_LDRB_32B_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3c600800))
        return iemDecodeA64_LDR_B_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8600800))
        return iemDecodeA64_LDR_32_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xbc600800))
        return iemDecodeA64_LDR_S_ldst_regoff(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20601000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20601000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38601000))
        return iemDecodeA64_LDCLRLB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8601000))
        return iemDecodeA64_LDCLRL_32_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e9e0fc00/a0602000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e9e0fc00_a0602000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0602000))
        return iemDecodeA64_st1h_mz_p_bi_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0602001))
        return iemDecodeA64_stnt1h_mz_p_bi_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e9e0fc00/a1602000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e9e0fc00_a1602000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1602000))
        return iemDecodeA64_st1h_mzx_p_bi_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1602008))
        return iemDecodeA64_stnt1h_mzx_p_bi_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20602000 level 1 - mask=0x89000000 entries=0x8 valid=%50 (0x4) leaf=%25 (0x2) multi-if=%25 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20602000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_LDEORLB_32_memop,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_e9e0fc00_a0602000_2,
        iemDecodeA64_e9e0fc00_a1602000_2,
        iemDecodeA64_LDEORL_32_memop,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x89000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000002)) /* bit 27 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20603000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20603000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38603000))
        return iemDecodeA64_LDSETLB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8603000))
        return iemDecodeA64_LDSETL_32_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/a0604000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_a0604000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0604000))
        return iemDecodeA64_st1w_mz_p_bi_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0604001))
        return iemDecodeA64_stnt1w_mz_p_bi_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/a1604000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_a1604000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1604000))
        return iemDecodeA64_st1w_mzx_p_bi_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1604008))
        return iemDecodeA64_stnt1w_mzx_p_bi_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20604000 level 1 - mask=0x8d000000 entries=0x10 valid=%50 (0x8) leaf=%38 (0x6) multi-if=%12 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20604000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDSMAXLB_32_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDBFMAXL_16,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_ede0fc00_a0604000_2,
        iemDecodeA64_ede0fc00_a1604000_2,
        iemDecodeA64_ld1b_z_p_br_u64,
        iemDecodeA64_ld1w_z_p_br_u64,
        iemDecodeA64_LDSMAXL_32_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_LDFMAXL_32,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8d000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20605000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20605000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38605000))
        return iemDecodeA64_LDSMINLB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3c605000))
        return iemDecodeA64_LDBFMINL_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8605000))
        return iemDecodeA64_LDSMINL_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbc605000))
        return iemDecodeA64_LDFMINL_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/a0606000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_a0606000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0606000))
        return iemDecodeA64_st1d_mz_p_bi_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e001)) == UINT32_C(0xa0606001))
        return iemDecodeA64_stnt1d_mz_p_bi_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/a1606000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_a1606000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1606000))
        return iemDecodeA64_st1d_mzx_p_bi_2x8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e008)) == UINT32_C(0xa1606008))
        return iemDecodeA64_stnt1d_mzx_p_bi_2x8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20606000 level 1 - mask=0x8d000000 entries=0x10 valid=%50 (0x8) leaf=%38 (0x6) multi-if=%12 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20606000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDUMAXLB_32_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDBFMAXNML_16,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_ede0fc00_a0606000_2,
        iemDecodeA64_ede0fc00_a1606000_2,
        iemDecodeA64_ldff1b_z_p_br_u64,
        iemDecodeA64_ldff1w_z_p_br_u64,
        iemDecodeA64_LDUMAXL_32_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_LDFMAXNML_32,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8d000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20606800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20606800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2e616800))
        return iemDecodeA64_FCVTXN_asimdmisc_N(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0ec00)) == UINT32_C(0x38606800))
        return iemDecodeA64_LDRB_32BL_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0ec00)) == UINT32_C(0x3c606800))
        return iemDecodeA64_LDR_BL_ldst_regoff(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20607000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20607000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38607000))
        return iemDecodeA64_LDUMINLB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3c607000))
        return iemDecodeA64_LDBFMINNML_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8607000))
        return iemDecodeA64_LDUMINL_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbc607000))
        return iemDecodeA64_LDFMINNML_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc00/a0608000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc00_a0608000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa0608000))
        return iemDecodeA64_st1b_mz_p_bi_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa0608001))
        return iemDecodeA64_stnt1b_mz_p_bi_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa1608000))
        return iemDecodeA64_st1b_mzx_p_bi_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa1608008))
        return iemDecodeA64_stnt1b_mzx_p_bi_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20608000 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20608000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_SWPLB_32_memop,
        iemDecodeA64_STBFADDL_16,
        iemDecodeA64_ece0fc00_a0608000_2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_SWPL_32_memop,
        iemDecodeA64_STFADDL_32,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 65f0fc00/2060a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65f0fc00_2060a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3860a000))
        return iemDecodeA64_RCWSWPL_64_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa060a000))
        return iemDecodeA64_st1h_mz_p_bi_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e003)) == UINT32_C(0xa060a001))
        return iemDecodeA64_stnt1h_mz_p_bi_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65f0fc00/2160a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65f0fc00_2160a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa160a000))
        return iemDecodeA64_st1h_mzx_p_bi_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa160a008))
        return iemDecodeA64_stnt1h_mzx_p_bi_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2060a000 level 1 - mask=0x5100000 entries=0x8 valid=%75 (0x6) leaf=%50 (0x4) multi-if=%25 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2060a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_65f0fc00_2060a000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_65f0fc00_2160a000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld1b_z_p_bi_u64,
        iemDecodeA64_ldnf1b_z_p_bi_u64,
        iemDecodeA64_ld1w_z_p_bi_u64,
        iemDecodeA64_ldnf1w_z_p_bi_u64,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x05100000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 20) & UINT32_C(0x00000001)) /* bit 20 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 65e0fc01/2160c000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc01_2160c000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa160c000))
        return iemDecodeA64_st1w_mzx_p_bi_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa160c008))
        return iemDecodeA64_stnt1w_mzx_p_bi_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc01/2460c001 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc01_2460c001_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x3c60c01f))
        return iemDecodeA64_STBFMAXL_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xbc60c01f))
        return iemDecodeA64_STFMAXL_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2060c000 level 1 - mask=0x5000001 entries=0x8 valid=%75 (0x6) leaf=%50 (0x4) multi-if=%25 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2060c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_st1w_mz_p_bi_4,
        iemDecodeA64_stnt1w_mz_p_bi_4,
        iemDecodeA64_65e0fc01_2160c000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld4b_z_p_br_contiguous,
        iemDecodeA64_65e0fc01_2460c001_2,
        iemDecodeA64_ld4w_z_p_br_contiguous,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x05000001 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/2060d000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2060d000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x3c60d01f))
        return iemDecodeA64_STBFMINL_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xbc60d01f))
        return iemDecodeA64_STFMINL_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc01/2160e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc01_2160e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa160e000))
        return iemDecodeA64_st1d_mzx_p_bi_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e00c)) == UINT32_C(0xa160e008))
        return iemDecodeA64_stnt1d_mzx_p_bi_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc01/2460e001 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc01_2460e001_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x3c60e01f))
        return iemDecodeA64_STBFMAXNML_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xbc60e01f))
        return iemDecodeA64_STFMAXNML_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2060e000 level 1 - mask=0x5000001 entries=0x8 valid=%75 (0x6) leaf=%50 (0x4) multi-if=%25 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2060e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_st1d_mz_p_bi_4,
        iemDecodeA64_stnt1d_mz_p_bi_4,
        iemDecodeA64_65e0fc01_2160e000_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld4b_z_p_bi_contiguous,
        iemDecodeA64_65e0fc01_2460e001_2,
        iemDecodeA64_ld4w_z_p_bi_contiguous,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x05000001 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/2060f000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2060f000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x3c60f01f))
        return iemDecodeA64_STBFMINNML_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xbc60f01f))
        return iemDecodeA64_STFMINNML_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* fde0fc00/a0800000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_fde0fc00_a0800000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0xa0800000))
        return iemDecodeA64_smopa_za_pp_zz_32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0xa0800008))
        return iemDecodeA64_smopa_za32_pp_zz_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0xa0800010))
        return iemDecodeA64_smops_za_pp_zz_32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0xa0800018))
        return iemDecodeA64_smops_za32_pp_zz_16(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* fde0fc00/a1800000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_fde0fc00_a1800000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0xa1800000))
        return iemDecodeA64_usmopa_za_pp_zz_32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0xa1800008))
        return iemDecodeA64_umopa_za32_pp_zz_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0xa1800010))
        return iemDecodeA64_usmops_za_pp_zz_32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0xa1800018))
        return iemDecodeA64_umops_za32_pp_zz_16(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20800000 level 1 - mask=0x9d000000 entries=0x20 valid=%56 (0x12) leaf=%50 (0x10) multi-if=%6 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20800000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_STP_32_ldstpair_post,
        iemDecodeA64_STP_32_ldstpair_pre,
        iemDecodeA64_STP_S_ldstpair_post,
        iemDecodeA64_STP_S_ldstpair_pre,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LDURSB_64_ldst_unscaled,
        iemDecodeA64_LDRSB_64_ldst_pos,
        iemDecodeA64_STUR_Q_ldst_unscaled,
        iemDecodeA64_STR_Q_ldst_pos,
        iemDecodeA64_fde0fc00_a0800000_2,
        iemDecodeA64_fde0fc00_a1800000_2,
        iemDecodeA64_ld1rqh_z_p_br_contiguous,
        iemDecodeA64_ld1rqd_z_p_br_contiguous,
        iemDecodeA64_STP_64_ldstpair_post,
        iemDecodeA64_STP_64_ldstpair_pre,
        iemDecodeA64_STP_Q_ldstpair_post,
        iemDecodeA64_STP_Q_ldstpair_pre,
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_LDURSW_64_ldst_unscaled,
        iemDecodeA64_LDRSW_64_ldst_pos,
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x9d000000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x0000000e)) /* bit 26 L 3 -> 1 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000010)) /* bit 31 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20800400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20800400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38800400))
        return iemDecodeA64_LDRSB_64_ldst_immpost(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3c800400))
        return iemDecodeA64_STR_Q_ldst_immpost(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8800400))
        return iemDecodeA64_LDRSW_64_ldst_immpost(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20800800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20800800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38800800))
        return iemDecodeA64_LDTRSB_64_ldst_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8800800))
        return iemDecodeA64_LDTRSW_64_ldst_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20800c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20800c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38800c00))
        return iemDecodeA64_LDRSB_64_ldst_immpre(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3c800c00))
        return iemDecodeA64_STR_Q_ldst_immpre(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8800c00))
        return iemDecodeA64_LDRSW_64_ldst_immpre(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20802000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20802000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4802000))
        return iemDecodeA64_ld1rqh_z_p_bi_u16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5802000))
        return iemDecodeA64_ld1rqd_z_p_bi_u64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5902000))
        return iemDecodeA64_ld1d_z_p_bi_u128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f0fe10/20804000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f0fe10_20804000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4804000))
        return iemDecodeA64_ld1sw_z_p_br_s64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5804000))
        return iemDecodeA64_ld1sb_z_p_br_s64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25804000))
        return iemDecodeA64_orr_p_p_pp_z(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20804000 level 1 - mask=0x100210 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20804000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60f0fe10_20804000_2,
        iemDecodeA64_orn_p_p_pp_z,
        iemDecodeA64_nor_p_p_pp_z,
        iemDecodeA64_nand_p_p_pp_z,
        iemDecodeA64_brkb_p_p_p,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00100210 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >>  8) & UINT32_C(0x00000002)) /* bit  9 L 1 -> 1 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20806000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20806000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4806000))
        return iemDecodeA64_ldff1sw_z_p_br_s64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5806000))
        return iemDecodeA64_ldff1sb_z_p_br_s64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20808000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20808000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x2f808000))
        return iemDecodeA64_FMLAL2_asimdelem_LH(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5808000))
        return iemDecodeA64_ld1d_z_p_br_u128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2080a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2080a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa480a000))
        return iemDecodeA64_ld1sw_z_p_bi_s64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa490a000))
        return iemDecodeA64_ldnf1sw_z_p_bi_s64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa580a000))
        return iemDecodeA64_ld1sb_z_p_bi_s64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa590a000))
        return iemDecodeA64_ldnf1sb_z_p_bi_s64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2080c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2080c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfc0f400)) == UINT32_C(0x2f80c000))
        return iemDecodeA64_FMLSL2_asimdelem_LH(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa480c000))
        return iemDecodeA64_ldnt1h_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa580c000))
        return iemDecodeA64_ldnt1d_z_p_br_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/2080e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_2080e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa480e000))
        return iemDecodeA64_ldnt1h_z_p_bi_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa490e000))
        return iemDecodeA64_ld2q_z_p_bi_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa580e000))
        return iemDecodeA64_ldnt1d_z_p_bi_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa590e000))
        return iemDecodeA64_ld4q_z_p_bi_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/a0a00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_a0a00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0xa0a00000))
        return iemDecodeA64_sumopa_za_pp_zz_32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0xa0a00010))
        return iemDecodeA64_sumops_za_pp_zz_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/a1a00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_a1a00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0xa1a00000))
        return iemDecodeA64_umopa_za_pp_zz_32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001c)) == UINT32_C(0xa1a00010))
        return iemDecodeA64_umops_za_pp_zz_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20a00000 level 1 - mask=0x8d000000 entries=0x10 valid=%50 (0x8) leaf=%38 (0x6) multi-if=%12 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a00000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDADDAB_32_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDBFADDA_16,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_ede0fc00_a0a00000_2,
        iemDecodeA64_ede0fc00_a1a00000_2,
        iemDecodeA64_ld1roh_z_p_br_contiguous,
        iemDecodeA64_ld1rod_z_p_br_contiguous,
        iemDecodeA64_LDADDA_32_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_LDFADDA_32,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8d000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20a00800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a00800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38a00800))
        return iemDecodeA64_LDRSB_64B_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3ca00800))
        return iemDecodeA64_STR_Q_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xb8a00800))
        return iemDecodeA64_LDRSW_64_ldst_regoff(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20a01000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a01000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38a01000))
        return iemDecodeA64_LDCLRAB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8a01000))
        return iemDecodeA64_LDCLRA_32_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e1e0fc10/a0a02000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e1e0fc10_a0a02000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8a02000))
        return iemDecodeA64_LDEORA_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4a02000))
        return iemDecodeA64_ld1roh_z_p_bi_u16(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20a02000 level 1 - mask=0x81000010 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a02000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LDEORAB_32_memop,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_ctermeq_rr,
        iemDecodeA64_ctermne_rr,
        iemDecodeA64_e1e0fc10_a0a02000_2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_ld1rod_z_p_bi_u64,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x81000010 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20a03000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a03000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38a03000))
        return iemDecodeA64_LDSETAB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8a03000))
        return iemDecodeA64_LDSETA_32_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc00/a4a04000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc00_a4a04000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4a04000))
        return iemDecodeA64_ld1h_z_p_br_u16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5a04000))
        return iemDecodeA64_ld1sb_z_p_br_s32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20a04000 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a04000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_LDSMAXAB_32_memop,
        iemDecodeA64_LDBFMAXA_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_ece0fc00_a4a04000_2,
        iemDecodeA64_LDSMAXA_32_memop,
        iemDecodeA64_LDFMAXA_32,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20a05000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a05000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38a05000))
        return iemDecodeA64_LDSMINAB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3ca05000))
        return iemDecodeA64_LDBFMINA_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8a05000))
        return iemDecodeA64_LDSMINA_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbca05000))
        return iemDecodeA64_LDFMINA_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc00/a4a06000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc00_a4a06000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4a06000))
        return iemDecodeA64_ldff1h_z_p_br_u16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5a06000))
        return iemDecodeA64_ldff1sb_z_p_br_s32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20a06000 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a06000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_LDUMAXAB_32_memop,
        iemDecodeA64_LDBFMAXNMA_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_ece0fc00_a4a06000_2,
        iemDecodeA64_LDUMAXA_32_memop,
        iemDecodeA64_LDFMAXNMA_32,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20a07000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a07000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38a07000))
        return iemDecodeA64_LDUMINAB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3ca07000))
        return iemDecodeA64_LDBFMINNMA_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8a07000))
        return iemDecodeA64_LDUMINA_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbca07000))
        return iemDecodeA64_LDFMINNMA_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20a08000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a08000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4a08000))
        return iemDecodeA64_ld2q_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5a08000))
        return iemDecodeA64_ld4q_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38a08000))
        return iemDecodeA64_SWPAB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8a08000))
        return iemDecodeA64_SWPA_32_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20a0a000 level 1 - mask=0x5100000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a0a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_RCWSWPA_64_memop,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld1h_z_p_bi_u16,
        iemDecodeA64_ldnf1h_z_p_bi_u16,
        iemDecodeA64_ld1sb_z_p_bi_s32,
        iemDecodeA64_ldnf1sb_z_p_bi_s32,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x05100000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 20) & UINT32_C(0x00000001)) /* bit 20 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20a0c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a0c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4a0c000))
        return iemDecodeA64_ld2h_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5a0c000))
        return iemDecodeA64_ld2d_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x38bfc000))
        return iemDecodeA64_LDAPRB_32L_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xb8bfc000))
        return iemDecodeA64_LDAPR_32L_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20a0c800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a0c800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2ea0c800))
        return iemDecodeA64_FCMGE_asimdmisc_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2ea1c800))
        return iemDecodeA64_URSQRTE_asimdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20a0d800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a0d800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2ea0d800))
        return iemDecodeA64_FCMLE_asimdmisc_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2ea1d800))
        return iemDecodeA64_FRSQRTE_asimdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20a0e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a0e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4a0e000))
        return iemDecodeA64_ld2h_z_p_bi_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5a0e000))
        return iemDecodeA64_ld2d_z_p_bi_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20a0f800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20a0f800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2ea0f800))
        return iemDecodeA64_FNEG_asimdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbfbffc00)) == UINT32_C(0x2ea1f800))
        return iemDecodeA64_FSQRT_asimdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* fde0fc00/a0c00000 level 2 - mask=0x100218 entries=0x10 valid=%62 (0xa) leaf=%62 (0xa) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_fde0fc00_a0c00000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_smopa_za_pp_zz_64,
        iemDecodeA64_smop4a_za_zz_h1x1,
        iemDecodeA64_smops_za_pp_zz_64,
        iemDecodeA64_smop4s_za_zz_h1x1,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_smop4a_za_zz_h2x1,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_smop4s_za_zz_h2x1,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_smop4a_za_zz_h1x2,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_smop4s_za_zz_h1x2,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_smop4a_za_zz_h2x2,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_smop4s_za_zz_h2x2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00100218 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >>  7) & UINT32_C(0x00000004)) /* bit  9 L 1 -> 2 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* fde0fc00/a1c00000 level 2 - mask=0x100218 entries=0x10 valid=%62 (0xa) leaf=%62 (0xa) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_fde0fc00_a1c00000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_usmopa_za_pp_zz_64,
        iemDecodeA64_usmop4a_za_zz_h1x1,
        iemDecodeA64_usmops_za_pp_zz_64,
        iemDecodeA64_usmop4s_za_zz_h1x1,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_usmop4a_za_zz_h2x1,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_usmop4s_za_zz_h2x1,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_usmop4a_za_zz_h1x2,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_usmop4s_za_zz_h1x2,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_usmop4a_za_zz_h2x2,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_usmop4s_za_zz_h2x2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00100218 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >>  7) & UINT32_C(0x00000004)) /* bit  9 L 1 -> 2 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20c00000 level 1 - mask=0x9d000000 entries=0x20 valid=%47 (0xf) leaf=%41 (0xd) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20c00000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDP_32_ldstpair_post,
        iemDecodeA64_LDP_32_ldstpair_pre,
        iemDecodeA64_LDP_S_ldstpair_post,
        iemDecodeA64_LDP_S_ldstpair_pre,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LDURSB_32_ldst_unscaled,
        iemDecodeA64_LDRSB_32_ldst_pos,
        iemDecodeA64_LDUR_Q_ldst_unscaled,
        iemDecodeA64_LDR_Q_ldst_pos,
        iemDecodeA64_fde0fc00_a0c00000_2,
        iemDecodeA64_fde0fc00_a1c00000_2,
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_LDP_64_ldstpair_post,
        iemDecodeA64_LDP_64_ldstpair_pre,
        iemDecodeA64_LDP_Q_ldstpair_post,
        iemDecodeA64_LDP_Q_ldstpair_pre,
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_SUBPS_64S_dp_2src,
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x9d000000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x0000000e)) /* bit 26 L 3 -> 1 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000010)) /* bit 31 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20c00400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20c00400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbfe0fc00)) == UINT32_C(0x2ec00400))
        return iemDecodeA64_FMINNMP_asimdsamefp16_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38c00400))
        return iemDecodeA64_LDRSB_32_ldst_immpost(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3cc00400))
        return iemDecodeA64_LDR_Q_ldst_immpost(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20c00c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20c00c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38c00c00))
        return iemDecodeA64_LDRSB_32_ldst_immpre(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3cc00c00))
        return iemDecodeA64_LDR_Q_ldst_immpre(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f0fe10/20c04000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f0fe10_20c04000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4c04000))
        return iemDecodeA64_ld1h_z_p_br_u32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5c04000))
        return iemDecodeA64_ld1sb_z_p_br_s16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0c210)) == UINT32_C(0x25c04000))
        return iemDecodeA64_orrs_p_p_pp_z(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20c04000 level 1 - mask=0x100210 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20c04000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60f0fe10_20c04000_2,
        iemDecodeA64_orns_p_p_pp_z,
        iemDecodeA64_nors_p_p_pp_z,
        iemDecodeA64_nands_p_p_pp_z,
        iemDecodeA64_brkbs_p_p_p_z,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00100210 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >>  8) & UINT32_C(0x00000002)) /* bit  9 L 1 -> 1 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20c06000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20c06000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4c06000))
        return iemDecodeA64_ldff1h_z_p_br_u32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5c06000))
        return iemDecodeA64_ldff1sb_z_p_br_s16(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20c0a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20c0a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4c0a000))
        return iemDecodeA64_ld1h_z_p_bi_u32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4d0a000))
        return iemDecodeA64_ldnf1h_z_p_bi_u32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5c0a000))
        return iemDecodeA64_ld1sb_z_p_bi_s16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5d0a000))
        return iemDecodeA64_ldnf1sb_z_p_bi_s16(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20c0c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20c0c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4c0c000))
        return iemDecodeA64_ld3h_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5c0c000))
        return iemDecodeA64_ld3d_z_p_br_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20c0e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20c0e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4c0e000))
        return iemDecodeA64_ld3h_z_p_bi_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5c0e000))
        return iemDecodeA64_ld3d_z_p_bi_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc18/20e00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc18_20e00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00018)) == UINT32_C(0xa0e00000))
        return iemDecodeA64_sumopa_za_pp_zz_64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38e00000))
        return iemDecodeA64_LDADDALB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8e00000))
        return iemDecodeA64_LDADDAL_32_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc18/20e00008 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc18_20e00008_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0e00008))
        return iemDecodeA64_sumop4a_za_zz_h1x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0e00208))
        return iemDecodeA64_sumop4a_za_zz_h2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0f00008))
        return iemDecodeA64_sumop4a_za_zz_h1x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0f00208))
        return iemDecodeA64_sumop4a_za_zz_h2x2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc18/20e00018 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc18_20e00018_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0e00018))
        return iemDecodeA64_sumop4s_za_zz_h1x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0e00218))
        return iemDecodeA64_sumop4s_za_zz_h2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0f00018))
        return iemDecodeA64_sumop4s_za_zz_h1x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa0f00218))
        return iemDecodeA64_sumop4s_za_zz_h2x2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc18/21e00008 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc18_21e00008_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1e00008))
        return iemDecodeA64_umop4a_za_zz_h1x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1e00208))
        return iemDecodeA64_umop4a_za_zz_h2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1f00008))
        return iemDecodeA64_umop4a_za_zz_h1x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1f00208))
        return iemDecodeA64_umop4a_za_zz_h2x2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc18/21e00018 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc18_21e00018_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1e00018))
        return iemDecodeA64_umop4s_za_zz_h1x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1e00218))
        return iemDecodeA64_umop4s_za_zz_h2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1f00018))
        return iemDecodeA64_umop4s_za_zz_h1x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff1fe38)) == UINT32_C(0xa1f00218))
        return iemDecodeA64_umop4s_za_zz_h2x2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 65e0fc18/24e00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc18_24e00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3ce00000))
        return iemDecodeA64_LDBFADDAL_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbce00000))
        return iemDecodeA64_LDFADDAL_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20e00000 level 1 - mask=0x5000018 entries=0x10 valid=%56 (0x9) leaf=%19 (0x3) multi-if=%38 (0x6) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e00000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_65e0fc18_20e00000_2,
        iemDecodeA64_65e0fc18_20e00008_2,
        iemDecodeA64_sumops_za_pp_zz_64,
        iemDecodeA64_65e0fc18_20e00018_2,
        iemDecodeA64_umopa_za_pp_zz_64,
        iemDecodeA64_65e0fc18_21e00008_2,
        iemDecodeA64_umops_za_pp_zz_64,
        iemDecodeA64_65e0fc18_21e00018_2,
        iemDecodeA64_65e0fc18_24e00000_2,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x05000018 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000004)) /* bit 24 L 1 -> 2 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000008)) /* bit 26 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20e00800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e00800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x38e00800))
        return iemDecodeA64_LDRSB_32B_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x3ce00800))
        return iemDecodeA64_LDR_Q_ldst_regoff(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20e01000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e01000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38e01000))
        return iemDecodeA64_LDCLRALB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8e01000))
        return iemDecodeA64_LDCLRAL_32_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20e02000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e02000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38e02000))
        return iemDecodeA64_LDEORALB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8e02000))
        return iemDecodeA64_LDEORAL_32_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20e03000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e03000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38e03000))
        return iemDecodeA64_LDSETALB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8e03000))
        return iemDecodeA64_LDSETAL_32_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc00/a4e04000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc00_a4e04000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4e04000))
        return iemDecodeA64_ld1h_z_p_br_u64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5e04000))
        return iemDecodeA64_ld1d_z_p_br_u64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20e04000 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e04000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_LDSMAXALB_32_memop,
        iemDecodeA64_LDBFMAXAL_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_ece0fc00_a4e04000_2,
        iemDecodeA64_LDSMAXAL_32_memop,
        iemDecodeA64_LDFMAXAL_32,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20e05000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e05000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38e05000))
        return iemDecodeA64_LDSMINALB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3ce05000))
        return iemDecodeA64_LDBFMINAL_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8e05000))
        return iemDecodeA64_LDSMINAL_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbce05000))
        return iemDecodeA64_LDFMINAL_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc00/a4e06000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc00_a4e06000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4e06000))
        return iemDecodeA64_ldff1h_z_p_br_u64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5e06000))
        return iemDecodeA64_ldff1d_z_p_br_u64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20e06000 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e06000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_LDUMAXALB_32_memop,
        iemDecodeA64_LDBFMAXNMAL_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_ece0fc00_a4e06000_2,
        iemDecodeA64_LDUMAXAL_32_memop,
        iemDecodeA64_LDFMAXNMAL_32,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20e07000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e07000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38e07000))
        return iemDecodeA64_LDUMINALB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x3ce07000))
        return iemDecodeA64_LDBFMINNMAL_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8e07000))
        return iemDecodeA64_LDUMINAL_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xbce07000))
        return iemDecodeA64_LDFMINNMAL_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20e08000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e08000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x38e08000))
        return iemDecodeA64_SWPALB_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xb8e08000))
        return iemDecodeA64_SWPAL_32_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20e0a000 level 1 - mask=0x5100000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e0a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_RCWSWPAL_64_memop,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld1h_z_p_bi_u64,
        iemDecodeA64_ldnf1h_z_p_bi_u64,
        iemDecodeA64_ld1d_z_p_bi_u64,
        iemDecodeA64_ldnf1d_z_p_bi_u64,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x05100000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 20) & UINT32_C(0x00000001)) /* bit 20 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/20e0c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e0c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa4e0c000))
        return iemDecodeA64_ld4h_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xa5e0c000))
        return iemDecodeA64_ld4d_z_p_br_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20e0d800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e0d800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2ef8d800))
        return iemDecodeA64_FCMLE_asimdmiscfp16_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2ef9d800))
        return iemDecodeA64_FRSQRTE_asimdmiscfp16_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20e0e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e0e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa4e0e000))
        return iemDecodeA64_ld4h_z_p_bi_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xa5e0e000))
        return iemDecodeA64_ld4d_z_p_bi_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/20e0f800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_20e0f800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2ef8f800))
        return iemDecodeA64_FNEG_asimdmiscfp16_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xbffffc00)) == UINT32_C(0x2ef9f800))
        return iemDecodeA64_FSQRT_asimdmiscfp16_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* fffffc38/c0020000 level 4 */
FNIEMOP_DEF_1(iemDecodeA64_fffffc38_c0020000_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0200)) == UINT32_C(0xc0020000))
        return iemDecodeA64_mova_z_p_rza_b(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff1e00)) == UINT32_C(0xc0020200))
        return iemDecodeA64_movaz_z_rza_b(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* fffffc38/c0060000 level 4 */
FNIEMOP_DEF_1(iemDecodeA64_fffffc38_c0060000_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1f01)) == UINT32_C(0xc0060000))
        return iemDecodeA64_mova_mz2_za_b1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff1f01)) == UINT32_C(0xc0060200))
        return iemDecodeA64_movaz_mz2_za_b1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* fff0fc38/c0000000 level 3 - mask=0xf0000 entries=0x10 valid=%56 (0x9) leaf=%44 (0x7) multi-if=%12 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_fff0fc38_c0000000_3, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_mova_za_p_rz_b,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_fffffc38_c0020000_4,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_mova_za2_z_b1,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_fffffc38_c0060000_4,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_zero_za_i,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_zero_za1_ri_2,
        iemDecodeA64_zero_za2_ri_2,
        iemDecodeA64_zero_za1_ri_4,
        iemDecodeA64_zero_za4_ri_2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x000f0000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000000f)) /* bit 16 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* fff0fc38/c1000000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_fff0fc38_c1000000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0001c)) == UINT32_C(0xc1000000))
        return iemDecodeA64_smlall_za_zzi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0001c)) == UINT32_C(0xc1000004))
        return iemDecodeA64_usmlall_za_zzi_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 64f0fc38/40000000 level 2 - mask=0x9b000000 entries=0x20 valid=%53 (0x11) leaf=%47 (0xf) multi-if=%3 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_64f0fc38_40000000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_EOR_32_log_shift,
        iemDecodeA64_SUB_32_addsub_shift,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_SUB_32_addsub_imm,
        iemDecodeA64_EOR_32_log_imm,
        iemDecodeA64_UBFM_32M_bitfield,
        iemDecodeA64_LDR_64_loadlit,
        iemDecodeA64_STLURH_32_ldapstl_unscaled,
        iemDecodeA64_SBC_32_addsub_carry,
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_fff0fc38_c0000000_3,
        iemDecodeA64_fff0fc38_c1000000_3,
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_EOR_64_log_shift,
        iemDecodeA64_SUB_64_addsub_shift,
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_SUB_64_addsub_imm,
        iemDecodeA64_EOR_64_log_imm,
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_PRFM_P_loadlit,
        iemDecodeA64_STLUR_64_ldapstl_unscaled,
        iemDecodeA64_SBC_64_addsub_carry,
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x9b000000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x0000000c)) /* bit 27 L 2 -> 2 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000010)) /* bit 31 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 64f0fc38/40000010 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_64f0fc38_40000010_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0001c)) == UINT32_C(0xc1000010))
        return iemDecodeA64_umlall_za_zzi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0001c)) == UINT32_C(0xc1000014))
        return iemDecodeA64_sumlall_za_zzi_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* f7f0fc38/54000000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_f7f0fc38_54000000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff000000)) == UINT32_C(0x5c000000))
        return iemDecodeA64_LDR_D_loadlit(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff000010)) == UINT32_C(0x54000000))
        return iemDecodeA64_B_only_condbranch(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* f7f0fc38/d4000000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_f7f0fc38_d4000000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0xd4000001))
        return iemDecodeA64_SVC_EX_exception(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0xd4000002))
        return iemDecodeA64_HVC_EX_exception(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0xd4000003))
        return iemDecodeA64_SMC_EX_exception(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 64f0fc38/44000000 level 2 - mask=0x93000000 entries=0x10 valid=%50 (0x8) leaf=%38 (0x6) multi-if=%12 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_64f0fc38_44000000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_saddlb_z_zz,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_f7f0fc38_54000000_3,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_SHA1C_QSV_cryptosha3,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_ld1sb_z_p_bz_d_x32_unscaled,
        iemDecodeA64_ld1sw_z_p_bz_d_x32_unscaled,
        iemDecodeA64_EOR3_VVV16_crypto4,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_f7f0fc38_d4000000_3,
        iemDecodeA64_SYS_CR_systeminstrs,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x93000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000004)) /* bit 28 L 1 -> 2 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 64f0fc38/44100000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_64f0fc38_44100000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff00000)) == UINT32_C(0xd5100000))
        return iemDecodeA64_MSR_SR_systemmove(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0xd61f0000))
        return iemDecodeA64_BR_64_branch_reg(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40000000 level 1 - mask=0x4100038 entries=0x20 valid=%44 (0xe) leaf=%31 (0xa) multi-if=%6 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40000000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_64f0fc38_40000000_2,
        iemDecodeA64_smlsll_za_zzi_s,
        iemDecodeA64_64f0fc38_40000010_2,
        iemDecodeA64_umlsll_za_zzi_s,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_smlall_za_zzi_s2xi,
        iemDecodeA64_smlsll_za_zzi_s2xi,
        iemDecodeA64_umlall_za_zzi_s2xi,
        iemDecodeA64_umlsll_za_zzi_s2xi,
        iemDecodeA64_usmlall_za_zzi_s2xi,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_sumlall_za_zzi_s2xi,
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_64f0fc38_44000000_2,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_BC_only_condbranch,
        iemDecodeA64_RETAASPPC_only_miscbranch,
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_64f0fc38_44100000_2,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x04100038 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000007)) /* bit  3 L 3 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000010)) /* bit 26 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 63e0fe00/40000400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_63e0fe00_40000400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1c7c)) == UINT32_C(0xc0040400))
        return iemDecodeA64_mova_za4_z_b1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff1f83)) == UINT32_C(0xc0060400))
        return iemDecodeA64_mova_mz4_za_b1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40000400 level 1 - mask=0x3000200 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40000400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_63e0fe00_40000400_2,
        iemDecodeA64_movaz_mz4_za_b1,
        iemDecodeA64_saddlt_z_zz,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_DUP_asisdone_only,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_SSHR_asisdshf_R,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x03000200 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  9) & UINT32_C(0x00000001)) /* bit  9 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000006)) /* bit 24 L 2 -> 1 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* ede0fc00/c0000800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_c0000800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9c38)) == UINT32_C(0xc0040800))
        return iemDecodeA64_mova_za_mz2_1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff9f01)) == UINT32_C(0xc0060800))
        return iemDecodeA64_mova_mz_za2_1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff9f01)) == UINT32_C(0xc0060a00))
        return iemDecodeA64_movaz_mz_za2_1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40000800 level 1 - mask=0x8d000000 entries=0x10 valid=%50 (0x8) leaf=%44 (0x7) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40000800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_sqdmlalbt_z_zzz,
        iemDecodeA64_uaddlb_z_zz,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_STLUR_H_ldapstl_simd,
        iemDecodeA64_ede0fc00_c0000800_2,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_BRAAZ_64_branch_reg,
        iemDecodeA64_BRAA_64P_branch_reg,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_STILP_64SS_ldiappstilp,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_STLUR_D_ldapstl_simd,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8d000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 63e6fc00/40060c00 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_63e6fc00_40060c00_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9f03)) == UINT32_C(0xc0060c00))
        return iemDecodeA64_mova_mz_za4_1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff9f03)) == UINT32_C(0xc0060e00))
        return iemDecodeA64_movaz_mz_za4_1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40000c00 level 1 - mask=0x3060000 entries=0x10 valid=%44 (0x7) leaf=%38 (0x6) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40000c00_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sqdmlslbt_z_zzz,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_mova_za_mz4_1,
        iemDecodeA64_63e6fc00_40060c00_2,
        iemDecodeA64_uaddlt_z_zz,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_GCSSTR_64_ldst_gcs,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_BRABZ_64_branch_reg,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_BRAB_64P_branch_reg,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x03060000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 17) & UINT32_C(0x00000003)) /* bit 17 L 2 -> 0 */
                        | ((uOpcode >> 22) & UINT32_C(0x0000000c)) /* bit 24 L 2 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 67e0fc30/45001000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_67e0fc30_45001000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45001000))
        return iemDecodeA64_ssublb_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xd5031000))
        return iemDecodeA64_WFET_only_systeminstrswithreg(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40001000 level 1 - mask=0x7000030 entries=0x20 valid=%28 (0x9) leaf=%25 (0x8) multi-if=%3 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40001000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_fmla_za_zzi_h2xi,
        iemDecodeA64_fmls_za_zzi_h2xi,
        iemDecodeA64_bfmla_za_zzi_h2xi,
        iemDecodeA64_bfmls_za_zzi_h2xi,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_cdot_z_zzz,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_67e0fc30_45001000_2,
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_WFIT_only_systeminstrswithreg,
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_SHA1P_QSV_cryptosha3,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_FMLA_asisdelem_RH_H,
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x07000030 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000003)) /* bit  4 L 2 -> 0 */
                        | ((uOpcode >> 22) & UINT32_C(0x0000001c)) /* bit 24 L 3 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40001400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40001400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45001400))
        return iemDecodeA64_ssublt_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x5f001400))
        return iemDecodeA64_SSRA_asisdshf_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40001800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40001800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45001800))
        return iemDecodeA64_usublb_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xd9001800))
        return iemDecodeA64_STILP_64S_ldiappstilp(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40001c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40001c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45001c00))
        return iemDecodeA64_usublt_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4e001c00))
        return iemDecodeA64_INS_asimdins_IR_r(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xd91f1c00))
        return iemDecodeA64_GCSSTTR_64_ldst_gcs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fff0/40002000 level 2 - mask=0x83000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fff0_40002000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_cmla_z_zzz,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_SHA1M_QSV_cryptosha3,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ldff1sb_z_p_bz_d_x32_unscaled,
        iemDecodeA64_ldff1sw_z_p_bz_d_x32_unscaled,
        iemDecodeA64_SUBPT_64_addsub_pt,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x83000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fff0/40002010 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fff0_40002010_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffff01f)) == UINT32_C(0xd503201f))
        return iemDecodeA64_HINT_HM_hints(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd503201f))
        return iemDecodeA64_NOP_HI_hints(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40002000 level 1 - mask=0x3f0 entries=0x40 valid=%42 (0x1b) leaf=%39 (0x19) multi-if=%2 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40002000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e0fff0_40002000_2,
        iemDecodeA64_60e0fff0_40002010_2,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_YIELD_HI_hints,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_WFE_HI_hints,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_WFI_HI_hints,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_SEV_HI_hints,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_SEVL_HI_hints,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_DGH_HI_hints,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_XPACLRI_HI_hints,
        iemDecodeA64_Invalid, // 16
        iemDecodeA64_PACIA1716_HI_hints,
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_PACIB1716_HI_hints,
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_AUTIA1716_HI_hints,
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_AUTIB1716_HI_hints,
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
        iemDecodeA64_Invalid, // 32
        iemDecodeA64_ESB_HI_hints,
        iemDecodeA64_Invalid, // 34
        iemDecodeA64_PSB_HC_hints,
        iemDecodeA64_Invalid, // 36
        iemDecodeA64_TSB_HC_hints,
        iemDecodeA64_Invalid, // 38
        iemDecodeA64_GCSB_HD_hints,
        iemDecodeA64_Invalid, // 40
        iemDecodeA64_CSDB_HI_hints,
        iemDecodeA64_Invalid, // 42
        iemDecodeA64_Invalid, // 43
        iemDecodeA64_Invalid, // 44
        iemDecodeA64_CLRBHB_HI_hints,
        iemDecodeA64_Invalid, // 46
        iemDecodeA64_Invalid, // 47
        iemDecodeA64_Invalid, // 48
        iemDecodeA64_PACIAZ_HI_hints,
        iemDecodeA64_Invalid, // 50
        iemDecodeA64_PACIASP_HI_hints,
        iemDecodeA64_Invalid, // 52
        iemDecodeA64_PACIBZ_HI_hints,
        iemDecodeA64_Invalid, // 54
        iemDecodeA64_PACIBSP_HI_hints,
        iemDecodeA64_Invalid, // 56
        iemDecodeA64_AUTIAZ_HI_hints,
        iemDecodeA64_Invalid, // 58
        iemDecodeA64_AUTIASP_HI_hints,
        iemDecodeA64_Invalid, // 60
        iemDecodeA64_AUTIBZ_HI_hints,
        iemDecodeA64_Invalid, // 62
        iemDecodeA64_AUTIBSP_HI_hints,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x40);

    /* fMask=0x000003f0 -> 0x0000003f */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x0000003f)) /* bit  4 L 6 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40002400 level 1 - mask=0x330 entries=0x10 valid=%31 (0x5) leaf=%31 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40002400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_SRSHR_asisdshf_R,
        iemDecodeA64_BTI_HB_hints,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_PACM_HI_hints,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_CHKFEAT_HF_hints,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_STSHH_HI_hints,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00000330 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000003)) /* bit  4 L 2 -> 0 */
                        | ((uOpcode >>  6) & UINT32_C(0x0000000c)) /* bit  8 L 2 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40003000 level 1 - mask=0x30000e0 entries=0x20 valid=%34 (0xb) leaf=%34 (0xb) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40003000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sqrdcmlah_z_zzz,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_sabdlb_z_zz,
        iemDecodeA64_DSB_BOn_barriers,
        iemDecodeA64_CLREX_BN_barriers,
        iemDecodeA64_TCOMMIT_only_barriers,
        iemDecodeA64_DSB_BO_barriers,
        iemDecodeA64_DMB_BO_barriers,
        iemDecodeA64_ISB_BI_barriers,
        iemDecodeA64_SB_only_barriers,
        iemDecodeA64_SHA1SU0_VVV_cryptosha3,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_SQDMLAL_asisdelem_L,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x030000e0 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  5) & UINT32_C(0x00000007)) /* bit  5 L 3 -> 0 */
                        | ((uOpcode >> 21) & UINT32_C(0x00000018)) /* bit 24 L 2 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40003400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40003400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45003400))
        return iemDecodeA64_sabdlt_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x5f003400))
        return iemDecodeA64_SRSRA_asisdshf_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40003c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40003c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45003c00))
        return iemDecodeA64_uabdlt_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffeffc00)) == UINT32_C(0x4e083c00))
        return iemDecodeA64_UMOV_asimdins_X_x(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc70/40004000 level 2 - mask=0x83000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc70_40004000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_smlalb_z_zzz,
        iemDecodeA64_saddwb_z_zz,
        iemDecodeA64_SHA256H_QQV_cryptosha3,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ld1b_z_p_bz_d_x32_unscaled,
        iemDecodeA64_ld1w_z_p_bz_d_x32_unscaled,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x83000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc70/40004010 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc70_40004010_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff8f01f)) == UINT32_C(0xd500401f))
        return iemDecodeA64_MSR_SI_pstate(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd500401f))
        return iemDecodeA64_CFINV_M_pstate(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40004000 level 1 - mask=0x70 entries=0x8 valid=%50 (0x4) leaf=%25 (0x2) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40004000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e0fc70_40004000_2,
        iemDecodeA64_60e0fc70_40004010_2,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_XAFLAG_M_pstate,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_AXFLAG_M_pstate,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00000070 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000007)) /* bit  4 L 3 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40004400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40004400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44004400))
        return iemDecodeA64_smlalt_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45004400))
        return iemDecodeA64_saddwt_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40004800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40004800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44004800))
        return iemDecodeA64_umlalb_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45004800))
        return iemDecodeA64_uaddwb_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40004c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40004c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44004c00))
        return iemDecodeA64_umlalt_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45004c00))
        return iemDecodeA64_uaddwt_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40005000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40005000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44005000))
        return iemDecodeA64_smlslb_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45005000))
        return iemDecodeA64_ssubwb_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0f400)) == UINT32_C(0x5f005000))
        return iemDecodeA64_FMLS_asisdelem_RH_H(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5e005000))
        return iemDecodeA64_SHA256H2_QQV_cryptosha3(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40005400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40005400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44005400))
        return iemDecodeA64_smlslt_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45005400))
        return iemDecodeA64_ssubwt_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x5f005400))
        return iemDecodeA64_SHL_asisdshf_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40005800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40005800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44005800))
        return iemDecodeA64_umlslb_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45005800))
        return iemDecodeA64_usubwb_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40005c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40005c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44005c00))
        return iemDecodeA64_umlslt_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45005c00))
        return iemDecodeA64_usubwt_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40006000 level 1 - mask=0x83000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40006000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sqdmlalb_z_zzz,
        iemDecodeA64_sqdmullb_z_zz,
        iemDecodeA64_SHA256SU1_VVV_cryptosha3,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_ldff1b_z_p_bz_d_x32_unscaled,
        iemDecodeA64_ldff1w_z_p_bz_d_x32_unscaled,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x83000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40006400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40006400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44006400))
        return iemDecodeA64_sqdmlalt_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45006400))
        return iemDecodeA64_sqdmullt_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40006800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40006800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44006800))
        return iemDecodeA64_sqdmlslb_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45006800))
        return iemDecodeA64_pmullb_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x45006800))
        return iemDecodeA64_pmullb_z_zz_q(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40006c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40006c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44006c00))
        return iemDecodeA64_sqdmlslt_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45006c00))
        return iemDecodeA64_pmullt_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x45006c00))
        return iemDecodeA64_pmullt_z_zz_q(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40007000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40007000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff00f400)) == UINT32_C(0x5f007000))
        return iemDecodeA64_SQDMLSL_asisdelem_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44007000))
        return iemDecodeA64_sqrdmlah_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45007000))
        return iemDecodeA64_smullb_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40007400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40007400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x44007400))
        return iemDecodeA64_sqrdmlsh_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45007400))
        return iemDecodeA64_smullt_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x5f007400))
        return iemDecodeA64_SQSHL_asisdshf_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40007c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40007c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45007c00))
        return iemDecodeA64_umullt_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x48007c00))
        return iemDecodeA64_STXRH_SR32_ldstexclr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xc8007c00))
        return iemDecodeA64_STXR_SR64_ldstexclr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xc9007c00))
        return iemDecodeA64_STTXR_SR64_ldstexclr_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e0fffc00/c0008000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e0fffc00_c0008000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4008000))
        return iemDecodeA64_ldnt1sb_z_p_ar_d_64_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc5008000))
        return iemDecodeA64_ldnt1sw_z_p_ar_d_64_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e0fffc00/c0108000 level 2 - mask=0x78 entries=0x10 valid=%44 (0x7) leaf=%44 (0x7) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_e0fffc00_c0108000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_smlall_za_zzi_s4xi,
        iemDecodeA64_smlsll_za_zzi_s4xi,
        iemDecodeA64_umlall_za_zzi_s4xi,
        iemDecodeA64_umlsll_za_zzi_s4xi,
        iemDecodeA64_usmlall_za_zzi_s4xi,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_sumlall_za_zzi_s4xi,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_fmlall_za32_z8z8i_4xi,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00000078 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x0000000f)) /* bit  3 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40008000 level 1 - mask=0x801f0000 entries=0x40 valid=%55 (0x23) leaf=%52 (0x21) multi-if=%2 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40008000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_saddlbt_z_zz,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_srshl_z_p_zz,
        iemDecodeA64_urshl_z_p_zz,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_srshlr_z_p_zz,
        iemDecodeA64_urshlr_z_p_zz,
        iemDecodeA64_sqshl_z_p_zz,
        iemDecodeA64_uqshl_z_p_zz,
        iemDecodeA64_sqrshl_z_p_zz,
        iemDecodeA64_uqrshl_z_p_zz,
        iemDecodeA64_sqshlr_z_p_zz,
        iemDecodeA64_uqshlr_z_p_zz,
        iemDecodeA64_sqrshlr_z_p_zz,
        iemDecodeA64_uqrshlr_z_p_zz,
        iemDecodeA64_shadd_z_p_zz,
        iemDecodeA64_uhadd_z_p_zz,
        iemDecodeA64_shsub_z_p_zz,
        iemDecodeA64_uhsub_z_p_zz,
        iemDecodeA64_srhadd_z_p_zz,
        iemDecodeA64_urhadd_z_p_zz,
        iemDecodeA64_shsubr_z_p_zz,
        iemDecodeA64_uhsubr_z_p_zz,
        iemDecodeA64_sqadd_z_p_zz,
        iemDecodeA64_uqadd_z_p_zz,
        iemDecodeA64_sqsub_z_p_zz,
        iemDecodeA64_uqsub_z_p_zz,
        iemDecodeA64_suqadd_z_p_zz,
        iemDecodeA64_usqadd_z_p_zz,
        iemDecodeA64_sqsubr_z_p_zz,
        iemDecodeA64_uqsubr_z_p_zz,
        iemDecodeA64_e0fffc00_c0008000_2,
        iemDecodeA64_Invalid, // 33
        iemDecodeA64_Invalid, // 34
        iemDecodeA64_Invalid, // 35
        iemDecodeA64_Invalid, // 36
        iemDecodeA64_Invalid, // 37
        iemDecodeA64_Invalid, // 38
        iemDecodeA64_Invalid, // 39
        iemDecodeA64_Invalid, // 40
        iemDecodeA64_Invalid, // 41
        iemDecodeA64_Invalid, // 42
        iemDecodeA64_Invalid, // 43
        iemDecodeA64_zero_za2_ri_1,
        iemDecodeA64_zero_za2_ri_4,
        iemDecodeA64_zero_za4_ri_1,
        iemDecodeA64_zero_za4_ri_4,
        iemDecodeA64_e0fffc00_c0108000_2,
        iemDecodeA64_Invalid, // 49
        iemDecodeA64_Invalid, // 50
        iemDecodeA64_Invalid, // 51
        iemDecodeA64_Invalid, // 52
        iemDecodeA64_Invalid, // 53
        iemDecodeA64_Invalid, // 54
        iemDecodeA64_Invalid, // 55
        iemDecodeA64_Invalid, // 56
        iemDecodeA64_Invalid, // 57
        iemDecodeA64_Invalid, // 58
        iemDecodeA64_Invalid, // 59
        iemDecodeA64_Invalid, // 60
        iemDecodeA64_Invalid, // 61
        iemDecodeA64_Invalid, // 62
        iemDecodeA64_Invalid, // 63
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x40);

    /* fMask=0x801f0000 -> 0x0000003f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000020)) /* bit 31 L 1 -> 5 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60f0fc70/40009000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f0fc70_40009000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45009000))
        return iemDecodeA64_eorbt_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0f400)) == UINT32_C(0x5f009000))
        return iemDecodeA64_FMUL_asisdelem_RH_H(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40009000 level 1 - mask=0x100070 entries=0x10 valid=%38 (0x6) leaf=%31 (0x5) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40009000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60f0fc70_40009000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_fmla_za_zzi_h4xi,
        iemDecodeA64_fmls_za_zzi_h4xi,
        iemDecodeA64_bfmla_za_zzi_h4xi,
        iemDecodeA64_bfmls_za_zzi_h4xi,
        iemDecodeA64_fdot_za_z8z8i_4xi,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00100070 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000007)) /* bit  4 L 3 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40009400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40009400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45009400))
        return iemDecodeA64_eortb_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x5f009400))
        return iemDecodeA64_SQSHRN_asisdshf_N(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60fffc00/4000a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60fffc00_4000a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x4400a000))
        return iemDecodeA64_urecpe_z_p_z_m(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x4500a000))
        return iemDecodeA64_sshllb_z_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc400a000))
        return iemDecodeA64_ld1q_z_p_ar_d_64_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4000a000 level 1 - mask=0x1f0000 entries=0x20 valid=%47 (0xf) leaf=%44 (0xe) multi-if=%3 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60fffc00_4000a000_2,
        iemDecodeA64_ursqrte_z_p_z_m,
        iemDecodeA64_urecpe_z_p_z_z,
        iemDecodeA64_ursqrte_z_p_z_z,
        iemDecodeA64_sadalp_z_p_z,
        iemDecodeA64_uadalp_z_p_z,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_sqabs_z_p_z_m,
        iemDecodeA64_sqneg_z_p_z_m,
        iemDecodeA64_sqabs_z_p_z_z,
        iemDecodeA64_sqneg_z_p_z_z,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_Invalid, // 16
        iemDecodeA64_addp_z_p_zz,
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_smaxp_z_p_zz,
        iemDecodeA64_umaxp_z_p_zz,
        iemDecodeA64_sminp_z_p_zz,
        iemDecodeA64_uminp_z_p_zz,
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x001f0000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/4000b000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000b000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff00f400)) == UINT32_C(0x5f00b000))
        return iemDecodeA64_SQDMULL_asisdelem_L(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500b000))
        return iemDecodeA64_bext_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4000c000 level 1 - mask=0x83000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sclamp_z_zz,
        iemDecodeA64_sabalb_z_zzz,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_SQDMULH_asisdelem_R,
        iemDecodeA64_ldnt1b_z_p_ar_d_64_unscaled,
        iemDecodeA64_ldnt1w_z_p_ar_d_64_unscaled,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x83000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/4000c400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000c400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4400c400))
        return iemDecodeA64_uclamp_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500c400))
        return iemDecodeA64_sabalt_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4e00c400))
        return iemDecodeA64_FMLALLTB_asimdsame2_G(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4000c800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000c800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500c800))
        return iemDecodeA64_uabalb_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4400c800))
        return iemDecodeA64_sdot_z32_zzz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4000cc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000cc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500cc00))
        return iemDecodeA64_uabalt_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4400cc00))
        return iemDecodeA64_udot_z32_zzz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4000d000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000d000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff00f400)) == UINT32_C(0x5f00d000))
        return iemDecodeA64_SQRDMULH_asisdelem_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x4500d000))
        return iemDecodeA64_adclb_z_zzz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4000d800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000d800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ff800)) == UINT32_C(0x4500d800))
        return iemDecodeA64_cadd_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ff800)) == UINT32_C(0x4501d800))
        return iemDecodeA64_sqcadd_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4000e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4400e000))
        return iemDecodeA64_zipq1_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500e000))
        return iemDecodeA64_ssra_z_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0xc400e000))
        return iemDecodeA64_prfb_i_p_ai_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0xc500e000))
        return iemDecodeA64_prfw_i_p_ai_d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4000e400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000e400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4400e400))
        return iemDecodeA64_zipq2_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500e400))
        return iemDecodeA64_usra_z_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x5f00e400))
        return iemDecodeA64_SCVTF_asisdshf_C(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4000e800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000e800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4400e800))
        return iemDecodeA64_uzpq1_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500e800))
        return iemDecodeA64_srsra_z_zi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4000ec00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000ec00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4400ec00))
        return iemDecodeA64_uzpq2_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500ec00))
        return iemDecodeA64_ursra_z_zi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4000f800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000f800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4400f800))
        return iemDecodeA64_tblq_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4500f800))
        return iemDecodeA64_saba_z_zzz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4000fc00 level 1 - mask=0x83000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4000fc00_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_STLXRH_SR32_ldstexclr,
        iemDecodeA64_uaba_z_zzz,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_FCVTZS_asisdshf_C,
        iemDecodeA64_STLXR_SR64_ldstexclr,
        iemDecodeA64_STLTXR_SR64_ldstexclr_unpriv,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x83000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* f7f0fc1c/c1200000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_f7f0fc1c_c1200000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c1e)) == UINT32_C(0xc1200000))
        return iemDecodeA64_smlall_za_zzv_2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff09c1e)) == UINT32_C(0xc1200002))
        return iemDecodeA64_fmlall_za32_z8z8v_2x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f0fc1c/40200000 level 2 - mask=0x97000000 entries=0x20 valid=%41 (0xd) leaf=%38 (0xc) multi-if=%3 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60f0fc1c_40200000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_EON_32_log_shift,
        iemDecodeA64_SUB_32_addsub_ext,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_sqshrunb_z_zi,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_STXP_SP64_ldstexclp,
        iemDecodeA64_f7f0fc1c_c1200000_3,
        iemDecodeA64_EON_64_log_shift,
        iemDecodeA64_SUB_64_addsub_ext,
        iemDecodeA64_prfb_i_p_bz_d_x32_scaled,
        iemDecodeA64_ld1sw_z_p_bz_d_x32_scaled,
        iemDecodeA64_BCAX_VVV16_crypto4,
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_STZGM_64bulk_ldsttags,
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_BRK_EX_exception,
        iemDecodeA64_SYSL_RC_systeminstrs,
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x97000000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000007)) /* bit 24 L 3 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000008)) /* bit 28 L 1 -> 3 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000010)) /* bit 31 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60f0fc1c/40300000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f0fc1c_40300000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffb09c1e)) == UINT32_C(0xc1300000))
        return iemDecodeA64_smlall_za_zzv_4x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff00000)) == UINT32_C(0xd5300000))
        return iemDecodeA64_MRS_RS_systemmove(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff09c1e)) == UINT32_C(0xc1300002))
        return iemDecodeA64_fmlall_za32_z8z8v_4x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0xd63f0000))
        return iemDecodeA64_BLR_64_branch_reg(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40200000 level 1 - mask=0x10001c entries=0x10 valid=%81 (0xd) leaf=%69 (0xb) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40200000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60f0fc1c_40200000_2,
        iemDecodeA64_usmlall_za_zzv_s2x1,
        iemDecodeA64_smlsll_za_zzv_2x1,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_umlall_za_zzv_2x1,
        iemDecodeA64_sumlall_za_zzv_s2x1,
        iemDecodeA64_umlsll_za_zzv_2x1,
        iemDecodeA64_RETABSPPC_only_miscbranch,
        iemDecodeA64_60f0fc1c_40300000_2,
        iemDecodeA64_usmlall_za_zzv_s4x1,
        iemDecodeA64_smlsll_za_zzv_4x1,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_umlall_za_zzv_4x1,
        iemDecodeA64_sumlall_za_zzv_s4x1,
        iemDecodeA64_umlsll_za_zzv_4x1,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x0010001c -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  2) & UINT32_C(0x00000007)) /* bit  2 L 3 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc1c/40200400 level 2 - mask=0x88100000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc1c_40200400_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sqshrunt_z_zi,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_LDTADD_64_memop_unpriv,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_smlall_za_zzv_1,
        iemDecodeA64_fmlall_za32_z8z8v_1,
        iemDecodeA64_STG_64Spost_ldsttags,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x88100000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 20) & UINT32_C(0x00000001)) /* bit 20 L 1 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000002)) /* bit 27 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40200400 level 1 - mask=0x1c entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40200400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e0fc1c_40200400_2,
        iemDecodeA64_usmlall_za_zzv_s,
        iemDecodeA64_smlsll_za_zzv_1,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_umlall_za_zzv_1,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_umlsll_za_zzv_1,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x0000001c -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  2) & UINT32_C(0x00000007)) /* bit  2 L 3 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 69e1fc00/41200800 level 2 - mask=0x410001c entries=0x20 valid=%34 (0xb) leaf=%34 (0xb) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_69e1fc00_41200800_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmlal_za_zzv_2x1,
        iemDecodeA64_fmlal_za_z8z8v_2x1,
        iemDecodeA64_fmlsl_za_zzv_2x1,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_bfmlal_za_zzv_2x1,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_bfmlsl_za_zzv_2x1,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_fmlal_za_zzv_4x1,
        iemDecodeA64_fmlal_za_z8z8v_4x1,
        iemDecodeA64_fmlsl_za_zzv_4x1,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_bfmlal_za_zzv_4x1,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_bfmlsl_za_zzv_4x1,
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_sqrshrunb_z_zi,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x0410001c -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  2) & UINT32_C(0x00000007)) /* bit  2 L 3 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000010)) /* bit 26 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 69e1fc00/49200800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_69e1fc00_49200800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9200800))
        return iemDecodeA64_STG_64Soffset_ldsttags(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59200800))
        return iemDecodeA64_RCWSCAS_C64_rcwcomswap(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40200800 level 1 - mask=0x9010000 entries=0x8 valid=%75 (0x6) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40200800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_mla_z_zzzi_h,
        iemDecodeA64_BLRAAZ_64_branch_reg,
        iemDecodeA64_69e1fc00_41200800_2,
        iemDecodeA64_BLRAA_64P_branch_reg,
        iemDecodeA64_SHA1H_SS_cryptosha2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_69e1fc00_49200800_2,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x09010000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000001)) /* bit 16 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000004)) /* bit 27 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* ebe0fc00/c1200c00 level 2 - mask=0x100018 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_ebe0fc00_c1200c00_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmlal_za_zzv_1,
        iemDecodeA64_fmlsl_za_zzv_1,
        iemDecodeA64_bfmlal_za_zzv_1,
        iemDecodeA64_bfmlsl_za_zzv_1,
        iemDecodeA64_fmlal_za_z8z8v_1,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00100018 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40200c00 level 1 - mask=0x8b000000 entries=0x10 valid=%50 (0x8) leaf=%44 (0x7) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40200c00_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_mls_z_zzzi_h,
        iemDecodeA64_sqrshrunt_z_zi,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_RCWSCASP_C64_rcwcomswappr,
        iemDecodeA64_SQADD_asisdsame_only,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_ebe0fc00_c1200c00_2,
        iemDecodeA64_BLRABZ_64_branch_reg,
        iemDecodeA64_BLRAB_64P_branch_reg,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_STG_64Spre_ldsttags,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8b000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000004)) /* bit 27 L 1 -> 2 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 61f0fc18/41201000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61f0fc18_41201000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45201000))
        return iemDecodeA64_shrnb_z_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1201000))
        return iemDecodeA64_fdot_za_zzv_2x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40201000 level 1 - mask=0x1100018 entries=0x10 valid=%56 (0x9) leaf=%50 (0x8) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40201000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sqrdmlah_z_zzzi_h,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_61f0fc18_41201000_2,
        iemDecodeA64_fdot_za_z8z8v_2x1,
        iemDecodeA64_bfdot_za_zzv_2x1,
        iemDecodeA64_fdot_za32_z8z8v_2x1,
        iemDecodeA64_fdot_za_zzv_4x1,
        iemDecodeA64_fdot_za_z8z8v_4x1,
        iemDecodeA64_bfdot_za_zzv_4x1,
        iemDecodeA64_fdot_za32_z8z8v_4x1,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x01100018 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */
                        | ((uOpcode >> 21) & UINT32_C(0x00000008)) /* bit 24 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 6cf0fc18/44201400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6cf0fc18_44201400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x44201400))
        return iemDecodeA64_sqrdmlsh_z_zzzi_h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45201400))
        return iemDecodeA64_shrnt_z_zi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40201400 level 1 - mask=0xc100018 entries=0x20 valid=%31 (0xa) leaf=%28 (0x9) multi-if=%3 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40201400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sdot_za_zzv_2x1,
        iemDecodeA64_usdot_za_zzv_s2x1,
        iemDecodeA64_udot_za_zzv_2x1,
        iemDecodeA64_sudot_za_zzv_s2x1,
        iemDecodeA64_sdot_za_zzv_4x1,
        iemDecodeA64_usdot_za_zzv_s4x1,
        iemDecodeA64_udot_za_zzv_4x1,
        iemDecodeA64_sudot_za_zzv_s4x1,
        iemDecodeA64_6cf0fc18_44201400_2,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_LDTCLR_64_memop_unpriv,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x0c100018 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000018)) /* bit 26 L 2 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40201800 level 1 - mask=0x6100018 entries=0x20 valid=%31 (0xa) leaf=%31 (0xa) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40201800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmla_za_zzv_2x1,
        iemDecodeA64_fmls_za_zzv_2x1,
        iemDecodeA64_add_za_zzv_2x1,
        iemDecodeA64_sub_za_zzv_2x1,
        iemDecodeA64_fmla_za_zzv_4x1,
        iemDecodeA64_fmls_za_zzv_4x1,
        iemDecodeA64_add_za_zzv_4x1,
        iemDecodeA64_sub_za_zzv_4x1,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_rshrnb_z_zi,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_SHA1SU1_VV_cryptosha2,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x06100018 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000018)) /* bit 25 L 2 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40201c00 level 1 - mask=0x4100008 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40201c00_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmla_za_zzv_2x1_16,
        iemDecodeA64_fmls_za_zzv_2x1_16,
        iemDecodeA64_fmla_za_zzv_4x1_16,
        iemDecodeA64_fmls_za_zzv_4x1_16,
        iemDecodeA64_rshrnt_z_zi,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x04100008 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000001)) /* bit  3 L 1 -> 0 */
                        | ((uOpcode >> 19) & UINT32_C(0x00000002)) /* bit 20 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000004)) /* bit 26 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40202000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40202000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc5202000))
        return iemDecodeA64_ldff1sw_z_p_bz_d_x32_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0e010)) == UINT32_C(0xc4202000))
        return iemDecodeA64_prfh_i_p_bz_d_x32_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45202000))
        return iemDecodeA64_sqshrnb_z_zi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40202800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40202800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45202800))
        return iemDecodeA64_sqrshrnb_z_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5e282800))
        return iemDecodeA64_SHA256SU0_VV_cryptosha2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40202c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40202c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x5e202c00))
        return iemDecodeA64_SQSUB_asisdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45202c00))
        return iemDecodeA64_sqrshrnt_z_zi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40203000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40203000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45203000))
        return iemDecodeA64_uqshrnb_z_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xd5233060))
        return iemDecodeA64_TSTART_BR_systemresult(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xd5233160))
        return iemDecodeA64_TTEST_BR_systemresult(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40203400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40203400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45203400))
        return iemDecodeA64_uqshrnt_z_zi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59203400))
        return iemDecodeA64_LDTSET_64_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40203800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40203800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x5e203800))
        return iemDecodeA64_SUQADD_asisdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x45203800))
        return iemDecodeA64_uqrshrnb_z_zi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40204000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40204000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc5204000))
        return iemDecodeA64_ld1w_z_p_bz_d_x32_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0e010)) == UINT32_C(0xc4204000))
        return iemDecodeA64_prfw_i_p_bz_d_x32_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa7fc00)) == UINT32_C(0x45204000))
        return iemDecodeA64_sqxtnb_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0x45314000))
        return iemDecodeA64_sqcvtn_z_mz2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40204800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40204800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x5e214800))
        return iemDecodeA64_SQXTN_asisdmisc_N(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa7fc00)) == UINT32_C(0x45204800))
        return iemDecodeA64_uqxtnb_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x4e284800))
        return iemDecodeA64_AESE_B_cryptoaes(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0x45314800))
        return iemDecodeA64_uqcvtn_z_mz2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40204c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40204c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x5e204c00))
        return iemDecodeA64_SQSHL_asisdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa7fc00)) == UINT32_C(0x45204c00))
        return iemDecodeA64_uqxtnt_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40205000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40205000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa7fc00)) == UINT32_C(0x45205000))
        return iemDecodeA64_sqxtunb_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0x45315000))
        return iemDecodeA64_sqcvtun_z_mz2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40206000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40206000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45206000))
        return iemDecodeA64_addhnb_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc5206000))
        return iemDecodeA64_ldff1w_z_p_bz_d_x32_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0e010)) == UINT32_C(0xc4206000))
        return iemDecodeA64_prfd_i_p_bz_d_x32_scaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40206800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40206800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45206800))
        return iemDecodeA64_raddhnb_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x4e286800))
        return iemDecodeA64_AESMC_B_cryptoaes(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40207800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40207800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45207800))
        return iemDecodeA64_rsubhnb_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x5e207800))
        return iemDecodeA64_SQABS_asisdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x4e287800))
        return iemDecodeA64_AESIMC_B_cryptoaes(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40207c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40207c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x45207c00))
        return iemDecodeA64_rsubhnt_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x48207c00))
        return iemDecodeA64_CASP_CP64_comswappr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e5e0fc00/45208000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e5e0fc00_45208000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x45208000))
        return iemDecodeA64_match_p_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x45208010))
        return iemDecodeA64_nmatch_p_p_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e5e0fc00/c1208000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e5e0fc00_c1208000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21e021)) == UINT32_C(0xc1208000))
        return iemDecodeA64_sel_mz_p_zz_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff23e063)) == UINT32_C(0xc1218000))
        return iemDecodeA64_sel_mz_p_zz_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40208000 level 1 - mask=0x85000000 entries=0x8 valid=%62 (0x5) leaf=%38 (0x3) multi-if=%25 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40208000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_e5e0fc00_45208000_2,
        iemDecodeA64_STLXP_SP64_ldstexclp,
        iemDecodeA64_e5e0fc00_c1208000_2,
        iemDecodeA64_ld1sb_z_p_ai_d,
        iemDecodeA64_ld1sw_z_p_ai_d,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x85000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000002)) /* bit 26 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40209000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40209000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x5e209000))
        return iemDecodeA64_SQDMLAL_asisddiff_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59209000))
        return iemDecodeA64_RCWSCLRP_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff21/4020a000 level 2 - mask=0x85000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff21_4020a000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_RCWSSWPP_128_memop_128,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_histseg_z_zz,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_smax_mz_zzv_2x1,
        iemDecodeA64_ldff1sb_z_p_ai_d,
        iemDecodeA64_ldff1sw_z_p_ai_d,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x85000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000002)) /* bit 26 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0ff21/4020a100 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff21_4020a100_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a100))
        return iemDecodeA64_fmax_mz_zzv_2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a180))
        return iemDecodeA64_fscale_mz_zzv_2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0ffe1)) == UINT32_C(0xc120a100))
        return iemDecodeA64_bfmax_mz_zzv_2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0ffe1)) == UINT32_C(0xc120a180))
        return iemDecodeA64_bfscale_mz_zzv_2x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff21/4020a101 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff21_4020a101_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a101))
        return iemDecodeA64_fmin_mz_zzv_2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0ffe1)) == UINT32_C(0xc120a101))
        return iemDecodeA64_bfmin_mz_zzv_2x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff21/4020a120 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff21_4020a120_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a120))
        return iemDecodeA64_fmaxnm_mz_zzv_2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0ffe1)) == UINT32_C(0xc120a120))
        return iemDecodeA64_bfmaxnm_mz_zzv_2x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff21/4020a121 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff21_4020a121_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe1)) == UINT32_C(0xc120a121))
        return iemDecodeA64_fminnm_mz_zzv_2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0ffe1)) == UINT32_C(0xc120a121))
        return iemDecodeA64_bfminnm_mz_zzv_2x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020a000 level 1 - mask=0x321 entries=0x10 valid=%69 (0xb) leaf=%38 (0x6) multi-if=%25 (0x4) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e0ff21_4020a000_2,
        iemDecodeA64_umax_mz_zzv_2x1,
        iemDecodeA64_smin_mz_zzv_2x1,
        iemDecodeA64_umin_mz_zzv_2x1,
        iemDecodeA64_60e0ff21_4020a100_2,
        iemDecodeA64_60e0ff21_4020a101_2,
        iemDecodeA64_60e0ff21_4020a120_2,
        iemDecodeA64_60e0ff21_4020a121_2,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_srshl_mz_zzv_2x1,
        iemDecodeA64_urshl_mz_zzv_2x1,
        iemDecodeA64_add_mz_zzv_2x1,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00000321 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >>  4) & UINT32_C(0x00000002)) /* bit  5 L 1 -> 1 */
                        | ((uOpcode >>  6) & UINT32_C(0x0000000c)) /* bit  8 L 2 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0ff21/4020a800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff21_4020a800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20ec00)) == UINT32_C(0x4520a800))
        return iemDecodeA64_luti2_z_zz_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120a800))
        return iemDecodeA64_smax_mz_zzv_4x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x5e21a800))
        return iemDecodeA64_FCVTNS_asisdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff21/4020a900 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff21_4020a900_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120a900))
        return iemDecodeA64_fmax_mz_zzv_4x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120a980))
        return iemDecodeA64_fscale_mz_zzv_4x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0ffe3)) == UINT32_C(0xc120a900))
        return iemDecodeA64_bfmax_mz_zzv_4x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0ffe3)) == UINT32_C(0xc120a980))
        return iemDecodeA64_bfscale_mz_zzv_4x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff21/4020a901 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff21_4020a901_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120a901))
        return iemDecodeA64_fmin_mz_zzv_4x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0ffe3)) == UINT32_C(0xc120a901))
        return iemDecodeA64_bfmin_mz_zzv_4x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff21/4020a920 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff21_4020a920_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120a920))
        return iemDecodeA64_fmaxnm_mz_zzv_4x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0ffe3)) == UINT32_C(0xc120a920))
        return iemDecodeA64_bfmaxnm_mz_zzv_4x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff21/4020a921 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff21_4020a921_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff30ffe3)) == UINT32_C(0xc120a921))
        return iemDecodeA64_fminnm_mz_zzv_4x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0ffe3)) == UINT32_C(0xc120a921))
        return iemDecodeA64_bfminnm_mz_zzv_4x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020a800 level 1 - mask=0x321 entries=0x10 valid=%69 (0xb) leaf=%38 (0x6) multi-if=%31 (0x5) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020a800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e0ff21_4020a800_2,
        iemDecodeA64_umax_mz_zzv_4x1,
        iemDecodeA64_smin_mz_zzv_4x1,
        iemDecodeA64_umin_mz_zzv_4x1,
        iemDecodeA64_60e0ff21_4020a900_2,
        iemDecodeA64_60e0ff21_4020a901_2,
        iemDecodeA64_60e0ff21_4020a920_2,
        iemDecodeA64_60e0ff21_4020a921_2,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_srshl_mz_zzv_4x1,
        iemDecodeA64_urshl_mz_zzv_4x1,
        iemDecodeA64_add_mz_zzv_4x1,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00000321 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >>  4) & UINT32_C(0x00000002)) /* bit  5 L 1 -> 1 */
                        | ((uOpcode >>  6) & UINT32_C(0x0000000c)) /* bit  8 L 2 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0ff61/4020b000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff61_4020b000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4520b000))
        return iemDecodeA64_luti2_z_zz_8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x5e20b000))
        return iemDecodeA64_SQDMLSL_asisddiff_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b000))
        return iemDecodeA64_smax_mz_zzw_2x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5920b000))
        return iemDecodeA64_RCWSSETP_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff61/4020b100 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff61_4020b100_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b100))
        return iemDecodeA64_fmax_mz_zzw_2x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b180))
        return iemDecodeA64_fscale_mz_zzw_2x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe1ffe1)) == UINT32_C(0xc120b100))
        return iemDecodeA64_bfmax_mz_zzw_2x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe1ffe1)) == UINT32_C(0xc120b180))
        return iemDecodeA64_bfscale_mz_zzw_2x2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff61/4020b101 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff61_4020b101_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b101))
        return iemDecodeA64_fmin_mz_zzw_2x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe1ffe1)) == UINT32_C(0xc120b101))
        return iemDecodeA64_bfmin_mz_zzw_2x2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff61/4020b120 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff61_4020b120_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b120))
        return iemDecodeA64_fmaxnm_mz_zzw_2x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe1ffe1)) == UINT32_C(0xc120b120))
        return iemDecodeA64_bfmaxnm_mz_zzw_2x2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff61/4020b121 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff61_4020b121_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b121))
        return iemDecodeA64_fminnm_mz_zzw_2x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe1ffe1)) == UINT32_C(0xc120b121))
        return iemDecodeA64_bfminnm_mz_zzw_2x2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020b000 level 1 - mask=0x361 entries=0x20 valid=%38 (0xc) leaf=%22 (0x7) multi-if=%16 (0x5) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020b000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e0ff61_4020b000_2,
        iemDecodeA64_umax_mz_zzw_2x2,
        iemDecodeA64_smin_mz_zzw_2x2,
        iemDecodeA64_umin_mz_zzw_2x2,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_60e0ff61_4020b100_2,
        iemDecodeA64_60e0ff61_4020b101_2,
        iemDecodeA64_60e0ff61_4020b120_2,
        iemDecodeA64_60e0ff61_4020b121_2,
        iemDecodeA64_famax_mz_zzw_2x2,
        iemDecodeA64_famin_mz_zzw_2x2,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_Invalid, // 16
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_srshl_mz_zzw_2x2,
        iemDecodeA64_urshl_mz_zzw_2x2,
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x00000361 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >>  4) & UINT32_C(0x00000006)) /* bit  5 L 2 -> 1 */
                        | ((uOpcode >>  5) & UINT32_C(0x00000018)) /* bit  8 L 2 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/4020b400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020b400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4520b400))
        return iemDecodeA64_luti4_z_zz_2x16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x5e20b400))
        return iemDecodeA64_SQDMULH_asisdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff21ffe1)) == UINT32_C(0xc120b400))
        return iemDecodeA64_sqdmulh_mz_zzw_2x2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff61/4020b800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff61_4020b800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120b800))
        return iemDecodeA64_smax_mz_zzw_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x5e21b800))
        return iemDecodeA64_FCVTMS_asisdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff61/4020b900 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff61_4020b900_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120b900))
        return iemDecodeA64_fmax_mz_zzw_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120b980))
        return iemDecodeA64_fscale_mz_zzw_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe3ffe3)) == UINT32_C(0xc120b900))
        return iemDecodeA64_bfmax_mz_zzw_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe3ffe3)) == UINT32_C(0xc120b980))
        return iemDecodeA64_bfscale_mz_zzw_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff61/4020b901 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff61_4020b901_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120b901))
        return iemDecodeA64_fmin_mz_zzw_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe3ffe3)) == UINT32_C(0xc120b901))
        return iemDecodeA64_bfmin_mz_zzw_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff61/4020b920 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff61_4020b920_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120b920))
        return iemDecodeA64_fmaxnm_mz_zzw_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe3ffe3)) == UINT32_C(0xc120b920))
        return iemDecodeA64_bfmaxnm_mz_zzw_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0ff61/4020b921 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0ff61_4020b921_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120b921))
        return iemDecodeA64_fminnm_mz_zzw_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe3ffe3)) == UINT32_C(0xc120b921))
        return iemDecodeA64_bfminnm_mz_zzw_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020b800 level 1 - mask=0x361 entries=0x20 valid=%38 (0xc) leaf=%22 (0x7) multi-if=%16 (0x5) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020b800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e0ff61_4020b800_2,
        iemDecodeA64_umax_mz_zzw_4x4,
        iemDecodeA64_smin_mz_zzw_4x4,
        iemDecodeA64_umin_mz_zzw_4x4,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_60e0ff61_4020b900_2,
        iemDecodeA64_60e0ff61_4020b901_2,
        iemDecodeA64_60e0ff61_4020b920_2,
        iemDecodeA64_60e0ff61_4020b921_2,
        iemDecodeA64_famax_mz_zzw_4x4,
        iemDecodeA64_famin_mz_zzw_4x4,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_Invalid, // 16
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_srshl_mz_zzw_4x4,
        iemDecodeA64_urshl_mz_zzw_4x4,
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x00000361 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >>  4) & UINT32_C(0x00000006)) /* bit  5 L 2 -> 1 */
                        | ((uOpcode >>  5) & UINT32_C(0x00000018)) /* bit  8 L 2 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/4020bc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020bc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x4520bc00))
        return iemDecodeA64_luti4_z_zz_1x16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff23ffe3)) == UINT32_C(0xc120bc00))
        return iemDecodeA64_sqdmulh_mz_zzw_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e5e0fc00/c120c000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e5e0fc00_c120c000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc01)) == UINT32_C(0xc120c000))
        return iemDecodeA64_fclamp_mz_zz_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc01)) == UINT32_C(0xc120c000))
        return iemDecodeA64_bfclamp_mz_zz_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020c000 level 1 - mask=0x85000000 entries=0x8 valid=%50 (0x4) leaf=%38 (0x3) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_histcnt_z_p_zz,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_e5e0fc00_c120c000_2,
        iemDecodeA64_ld1b_z_p_ai_d,
        iemDecodeA64_ld1w_z_p_ai_d,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x85000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000002)) /* bit 26 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/4020c400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020c400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc01)) == UINT32_C(0xc120c400))
        return iemDecodeA64_sclamp_mz_zz_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc01)) == UINT32_C(0xc120c401))
        return iemDecodeA64_uclamp_mz_zz_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020c800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020c800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc03)) == UINT32_C(0xc120c800))
        return iemDecodeA64_fclamp_mz_zz_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x5e21c800))
        return iemDecodeA64_FCVTAS_asisdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc03)) == UINT32_C(0xc120c800))
        return iemDecodeA64_bfclamp_mz_zz_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5e30c800))
        return iemDecodeA64_FMAXNMP_asisdpair_only_H(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020cc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020cc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc03)) == UINT32_C(0xc120cc00))
        return iemDecodeA64_sclamp_mz_zz_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc03)) == UINT32_C(0xc120cc01))
        return iemDecodeA64_uclamp_mz_zz_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020d000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020d000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x5e20d000))
        return iemDecodeA64_SQDMULL_asisddiff_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc01)) == UINT32_C(0xc120d000))
        return iemDecodeA64_zip_mz_zz_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc01)) == UINT32_C(0xc120d001))
        return iemDecodeA64_uzp_mz_zz_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020d400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020d400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc01)) == UINT32_C(0xc120d400))
        return iemDecodeA64_zip_mz_zz_2q(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc01)) == UINT32_C(0xc120d401))
        return iemDecodeA64_uzp_mz_zz_2q(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61e0fc60/4020d800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61e0fc60_4020d800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x5e21d800))
        return iemDecodeA64_SCVTF_asisdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5e30d800))
        return iemDecodeA64_FADDP_asisdpair_only_H(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020d800 level 1 - mask=0x1000060 entries=0x8 valid=%50 (0x4) leaf=%38 (0x3) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020d800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_61e0fc60_4020d800_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_sqrshr_z_mz4,
        iemDecodeA64_uqrshr_z_mz4,
        iemDecodeA64_sqrshru_z_mz4,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x01000060 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  5) & UINT32_C(0x00000003)) /* bit  5 L 2 -> 0 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000004)) /* bit 24 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/4020dc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020dc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc60)) == UINT32_C(0xc120dc00))
        return iemDecodeA64_sqrshrn_z_mz4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc60)) == UINT32_C(0xc120dc20))
        return iemDecodeA64_uqrshrn_z_mz4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20fc60)) == UINT32_C(0xc120dc40))
        return iemDecodeA64_sqrshrun_z_mz4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x5e20dc00))
        return iemDecodeA64_FMULX_asisdsame_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc20/4020e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc20_4020e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc420e000))
        return iemDecodeA64_ldff1b_z_p_ai_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc520e000))
        return iemDecodeA64_ldff1w_z_p_ai_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0xc120e000))
        return iemDecodeA64_fcvt_z_mz2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0x4520e000))
        return iemDecodeA64_aesmc_z_z(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc20/4022e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc20_4022e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x4522e000))
        return iemDecodeA64_aese_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc21)) == UINT32_C(0xc122e000))
        return iemDecodeA64_scvtf_mz_z_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc20/4023e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc20_4023e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x4523e000))
        return iemDecodeA64_sm4e_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0xc123e000))
        return iemDecodeA64_sqcvt_z_mz2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc20/4025e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc20_4025e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc01)) == UINT32_C(0xc125e000))
        return iemDecodeA64_sunpk_mz_z_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffc01)) == UINT32_C(0xc125e001))
        return iemDecodeA64_uunpk_mz_z_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc20/4026e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc20_4026e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc01)) == UINT32_C(0xc126e000))
        return iemDecodeA64_f1cvt_mz2_z8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc01)) == UINT32_C(0xc126e001))
        return iemDecodeA64_f1cvtl_mz2_z8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc20/4033e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc20_4033e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff7ffc60)) == UINT32_C(0xc133e000))
        return iemDecodeA64_sqcvt_z_mz4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff7ffc60)) == UINT32_C(0xc133e040))
        return iemDecodeA64_sqcvtn_z_mz4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc20/4033e020 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc20_4033e020_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff7ffc60)) == UINT32_C(0xc133e020))
        return iemDecodeA64_uqcvt_z_mz4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff7ffc60)) == UINT32_C(0xc133e060))
        return iemDecodeA64_uqcvtn_z_mz4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc20/4035e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc20_4035e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc23)) == UINT32_C(0xc135e000))
        return iemDecodeA64_sunpk_mz_z_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffc23)) == UINT32_C(0xc135e001))
        return iemDecodeA64_uunpk_mz_z_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc20/4036e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc20_4036e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc63)) == UINT32_C(0xc136e000))
        return iemDecodeA64_zip_mz_z_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3ffc63)) == UINT32_C(0xc136e002))
        return iemDecodeA64_uzp_mz_z_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc20/4037e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc20_4037e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc63)) == UINT32_C(0xc137e000))
        return iemDecodeA64_zip_mz_z_4q(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc63)) == UINT32_C(0xc137e002))
        return iemDecodeA64_uzp_mz_z_4q(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020e000 level 1 - mask=0x170020 entries=0x20 valid=%69 (0x16) leaf=%38 (0xc) multi-if=%31 (0xa) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60f7fc20_4020e000_2,
        iemDecodeA64_fcvtn_z_mz2,
        iemDecodeA64_fcvtzs_mz_z_2,
        iemDecodeA64_fcvtzu_mz_z_2,
        iemDecodeA64_60f7fc20_4022e000_2,
        iemDecodeA64_ucvtf_mz_z_2,
        iemDecodeA64_60f7fc20_4023e000_2,
        iemDecodeA64_uqcvt_z_mz2,
        iemDecodeA64_fcvt_z8_mz2,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_60f7fc20_4025e000_2,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_60f7fc20_4026e000_2,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_Invalid, // 16
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_fcvtzs_mz_z_4,
        iemDecodeA64_fcvtzu_mz_z_4,
        iemDecodeA64_scvtf_mz_z_4,
        iemDecodeA64_ucvtf_mz_z_4,
        iemDecodeA64_60f7fc20_4033e000_2,
        iemDecodeA64_60f7fc20_4033e020_2,
        iemDecodeA64_fcvt_z8_mz4,
        iemDecodeA64_fcvtn_z8_mz4,
        iemDecodeA64_60f7fc20_4035e000_2,
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_60f7fc20_4036e000_2,
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_60f7fc20_4037e000_2,
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x00170020 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  5) & UINT32_C(0x00000001)) /* bit  5 L 1 -> 0 */
                        | ((uOpcode >> 15) & UINT32_C(0x0000000e)) /* bit 16 L 3 -> 1 */
                        | ((uOpcode >> 16) & UINT32_C(0x00000010)) /* bit 20 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 66e3fc00/4020e400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_66e3fc00_4020e400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21fc21)) == UINT32_C(0xc120e400))
        return iemDecodeA64_fmul_mz_zzw_2x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe1fc21)) == UINT32_C(0xc120e400))
        return iemDecodeA64_bfmul_mz_zzw_2x2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 66e3fc00/4021e400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_66e3fc00_4021e400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff23fc63)) == UINT32_C(0xc121e400))
        return iemDecodeA64_fmul_mz_zzw_4x4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe3fc63)) == UINT32_C(0xc121e400))
        return iemDecodeA64_bfmul_mz_zzw_4x4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020e400 level 1 - mask=0x6030000 entries=0x10 valid=%31 (0x5) leaf=%19 (0x3) multi-if=%12 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020e400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_66e3fc00_4020e400_2,
        iemDecodeA64_66e3fc00_4021e400_2,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_aesimc_z_z,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_aesd_z_zz,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_FCMEQ_asisdsame_only,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x06030000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000003)) /* bit 16 L 2 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x0000000c)) /* bit 25 L 2 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e7fc00/4020e800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e7fc00_4020e800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21fc21)) == UINT32_C(0xc120e800))
        return iemDecodeA64_fmul_mz_zzv_2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe1fc21)) == UINT32_C(0xc120e800))
        return iemDecodeA64_bfmul_mz_zzv_2x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e7fc00/4021e800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e7fc00_4021e800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff21fc63)) == UINT32_C(0xc121e800))
        return iemDecodeA64_fmul_mz_zzv_4x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe1fc63)) == UINT32_C(0xc121e800))
        return iemDecodeA64_bfmul_mz_zzv_4x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020e800 level 1 - mask=0x70000 entries=0x8 valid=%75 (0x6) leaf=%50 (0x4) multi-if=%25 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020e800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e7fc00_4020e800_2,
        iemDecodeA64_60e7fc00_4021e800_2,
        iemDecodeA64_aese_mz_zzi_2x1,
        iemDecodeA64_aesemc_mz_zzi_2x1,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_aese_mz_zzi_4x1,
        iemDecodeA64_aesemc_mz_zzi_4x1,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00070000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000007)) /* bit 16 L 3 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/4020ec00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020ec00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe7fc01)) == UINT32_C(0x4522ec00))
        return iemDecodeA64_aesd_mz_zzi_2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe7fc01)) == UINT32_C(0x4523ec00))
        return iemDecodeA64_aesdimc_mz_zzi_2x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe7fc03)) == UINT32_C(0x4526ec00))
        return iemDecodeA64_aesd_mz_zzi_4x1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe7fc03)) == UINT32_C(0x4527ec00))
        return iemDecodeA64_aesdimc_mz_zzi_4x1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020f000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020f000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x4420f000))
        return iemDecodeA64_sqdmulh_z_zzi_h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4520f000))
        return iemDecodeA64_sm4ekey_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020f400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020f400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x4420f400))
        return iemDecodeA64_sqrdmulh_z_zzi_h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4520f400))
        return iemDecodeA64_rax1_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020f800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020f800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x4420f800))
        return iemDecodeA64_mul_z_zzi_h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc01)) == UINT32_C(0x4520f800))
        return iemDecodeA64_pmull_mz_zzw_1x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5e30f800))
        return iemDecodeA64_FMAXP_asisdpair_only_H(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4020fc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4020fc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x5e20fc00))
        return iemDecodeA64_FRECPS_asisdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4820fc00))
        return iemDecodeA64_CASPL_CP64_comswappr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc01)) == UINT32_C(0x4520fc00))
        return iemDecodeA64_pmlal_mz_zzzw_1x2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6feefe00/404e0200 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_6feefe00_404e0200_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff8fe0)) == UINT32_C(0xc04e03e0))
        return iemDecodeA64_movt_zt_r(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffcfe0)) == UINT32_C(0xc04f03e0))
        return iemDecodeA64_movt_zt_z(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6fe0fc00/40400000 level 2 - mask=0xe0200 entries=0x10 valid=%56 (0x9) leaf=%50 (0x8) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_6fe0fc00_40400000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_mova_za_p_rz_h,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_mova_z_p_rza_h,
        iemDecodeA64_movaz_z_rza_h,
        iemDecodeA64_mova_za2_z_h1,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_mova_mz2_za_h1,
        iemDecodeA64_movaz_mz2_za_h1,
        iemDecodeA64_zero_zt_i,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_movt_r_zt,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_6feefe00_404e0200_3,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x000e0200 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  9) & UINT32_C(0x00000001)) /* bit  9 L 1 -> 0 */
                        | ((uOpcode >> 16) & UINT32_C(0x0000000e)) /* bit 17 L 3 -> 1 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 6fe0fc00/41400000 level 2 - mask=0x100038 entries=0x10 valid=%50 (0x8) leaf=%50 (0x8) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_6fe0fc00_41400000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmlall_za32_z8z8i_1,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_fmla_za_zzi_s2xi,
        iemDecodeA64_fvdot_za_zzi_2xi,
        iemDecodeA64_fmls_za_zzi_s2xi,
        iemDecodeA64_bfvdot_za_zzi_2xi,
        iemDecodeA64_svdot_za32_zzi_2xi,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_uvdot_za32_zzi_2xi,
        iemDecodeA64_fdot_za32_z8z8i_2xi,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00100038 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000007)) /* bit  3 L 3 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 6fe0fc00/45400000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6fe0fc00_45400000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff00000)) == UINT32_C(0xd5500000))
        return iemDecodeA64_MSRR_SR_systemmovepr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff80000)) == UINT32_C(0xd5480000))
        return iemDecodeA64_SYSP_CR_syspairinstrs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6fe0fc00/49400000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6fe0fc00_49400000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x59400000))
        return iemDecodeA64_LDAPURH_32_ldapstl_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9400000))
        return iemDecodeA64_LDAPUR_64_ldapstl_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40400000 level 1 - mask=0xf000000 entries=0x10 valid=%50 (0x8) leaf=%25 (0x4) multi-if=%12 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40400000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_6fe0fc00_40400000_2,
        iemDecodeA64_6fe0fc00_41400000_2,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_UBFM_64M_bitfield,
        iemDecodeA64_HLT_EX_exception,
        iemDecodeA64_6fe0fc00_45400000_2,
        iemDecodeA64_RET_64R_branch_reg,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_6fe0fc00_49400000_2,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_SM3SS1_VVV4_crypto4,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x0f000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x0000000f)) /* bit 24 L 4 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40400400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40400400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1c7c)) == UINT32_C(0xc0440400))
        return iemDecodeA64_mova_za4_z_h1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff1f83)) == UINT32_C(0xc0460400))
        return iemDecodeA64_mova_mz4_za_h1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff1f83)) == UINT32_C(0xc0460600))
        return iemDecodeA64_movaz_mz4_za_h1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e6e0fc00/c6400800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e6e0fc00_c6400800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xd65f0be0))
        return iemDecodeA64_RETAASPPCR_64M_branch_reg(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd65f0bff))
        return iemDecodeA64_RETAA_64E_branch_reg(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40400800 level 1 - mask=0x86000000 entries=0x8 valid=%50 (0x4) leaf=%38 (0x3) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40400800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_LDAPUR_H_ldapstl_simd,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDIAPP_64LS_ldiappstilp,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDAPUR_D_ldapstl_simd,
        iemDecodeA64_e6e0fc00_c6400800_2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x86000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 25) & UINT32_C(0x00000003)) /* bit 25 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40400c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40400c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xd65f0fe0))
        return iemDecodeA64_RETABSPPCR_64M_branch_reg(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd65f0fff))
        return iemDecodeA64_RETAB_64E_branch_reg(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40401000 level 1 - mask=0x100038 entries=0x10 valid=%56 (0x9) leaf=%56 (0x9) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40401000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LUTI4_asimdtbl_L7,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_sdot_za32_zzi_2xi,
        iemDecodeA64_fdot_za_zzi_2xi,
        iemDecodeA64_udot_za32_zzi_2xi,
        iemDecodeA64_bfdot_za_zzi_2xi,
        iemDecodeA64_sdot_za_zzi_s2xi,
        iemDecodeA64_usdot_za_zzi_s2xi,
        iemDecodeA64_udot_za_zzi_s2xi,
        iemDecodeA64_sudot_za_zzi_s2xi,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00100038 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000007)) /* bit  3 L 3 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40407c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40407c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x485f7c00))
        return iemDecodeA64_LDXRH_LR32_ldstexclr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xc85f7c00))
        return iemDecodeA64_LDXR_LR64_ldstexclr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xc95f7c00))
        return iemDecodeA64_LDTXR_LR64_ldstexclr_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f0fc38/40408000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f0fc38_40408000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0cc00)) == UINT32_C(0xce408000))
        return iemDecodeA64_SM3TT1A_VVV4_crypto3_imm2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4408000))
        return iemDecodeA64_ld1sb_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc5408000))
        return iemDecodeA64_ld1sw_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40408000 level 1 - mask=0x100038 entries=0x10 valid=%50 (0x8) leaf=%44 (0x7) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40408000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60f0fc38_40408000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_fmla_za_zzi_s4xi,
        iemDecodeA64_fdot_za32_z8z8i_4xi,
        iemDecodeA64_fmls_za_zzi_s4xi,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_svdot_za_zzi_s4xi,
        iemDecodeA64_usvdot_za_zzi_s4xi,
        iemDecodeA64_uvdot_za_zzi_s4xi,
        iemDecodeA64_suvdot_za_zzi_s4xi,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00100038 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000007)) /* bit  3 L 3 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40409000 level 1 - mask=0x38 entries=0x8 valid=%100 (0x8) leaf=%100 (0x8) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40409000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sdot_za32_zzi_4xi,
        iemDecodeA64_fdot_za_zzi_4xi,
        iemDecodeA64_udot_za32_zzi_4xi,
        iemDecodeA64_bfdot_za_zzi_4xi,
        iemDecodeA64_sdot_za_zzi_s4xi,
        iemDecodeA64_usdot_za_zzi_s4xi,
        iemDecodeA64_udot_za_zzi_s4xi,
        iemDecodeA64_sudot_za_zzi_s4xi,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00000038 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000007)) /* bit  3 L 3 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/4040a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4040a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc440a000))
        return iemDecodeA64_ldff1sb_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc540a000))
        return iemDecodeA64_ldff1sw_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4040c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4040c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc440c000))
        return iemDecodeA64_ld1b_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc540c000))
        return iemDecodeA64_ld1w_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4040e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4040e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc440e000))
        return iemDecodeA64_ldff1b_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc540e000))
        return iemDecodeA64_ldff1w_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4040fc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4040fc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x485ffc00))
        return iemDecodeA64_LDAXRH_LR32_ldstexclr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xc85ffc00))
        return iemDecodeA64_LDAXR_LR64_ldstexclr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xc95ffc00))
        return iemDecodeA64_LDATXR_LR64_ldstexclr_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40600000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40600000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0001f)) == UINT32_C(0xd4600000))
        return iemDecodeA64_TCANCEL_EX_exception(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9600000))
        return iemDecodeA64_LDG_64Loffset_ldsttags(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff00000)) == UINT32_C(0xd5700000))
        return iemDecodeA64_MRRS_RS_systemmovepr(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff8000)) == UINT32_C(0xc87f0000))
        return iemDecodeA64_LDXP_LP64_ldstexclp(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40600400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40600400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9600400))
        return iemDecodeA64_STZG_64Spost_ldsttags(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59600400))
        return iemDecodeA64_LDTADDL_64_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 68f0fc18/48600800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_68f0fc18_48600800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9600800))
        return iemDecodeA64_STZG_64Soffset_ldsttags(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59600800))
        return iemDecodeA64_RCWSCASL_C64_rcwcomswap(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40600800 level 1 - mask=0x8100018 entries=0x10 valid=%56 (0x9) leaf=%50 (0x8) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40600800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_smlal_za_zzv_2x1,
        iemDecodeA64_smlsl_za_zzv_2x1,
        iemDecodeA64_umlal_za_zzv_2x1,
        iemDecodeA64_umlsl_za_zzv_2x1,
        iemDecodeA64_smlal_za_zzv_4x1,
        iemDecodeA64_smlsl_za_zzv_4x1,
        iemDecodeA64_umlal_za_zzv_4x1,
        iemDecodeA64_umlsl_za_zzv_4x1,
        iemDecodeA64_68f0fc18_48600800_2,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x08100018 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000008)) /* bit 27 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 68e0fc18/48600c00 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_68e0fc18_48600c00_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9600c00))
        return iemDecodeA64_STZG_64Spre_ldsttags(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59600c00))
        return iemDecodeA64_RCWSCASPL_C64_rcwcomswappr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40600c00 level 1 - mask=0x8000018 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40600c00_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_smlal_za_zzv_1,
        iemDecodeA64_smlsl_za_zzv_1,
        iemDecodeA64_umlal_za_zzv_1,
        iemDecodeA64_umlsl_za_zzv_1,
        iemDecodeA64_68e0fc18_48600c00_2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x08000018 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000004)) /* bit 27 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40601400 level 1 - mask=0x100018 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40601400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LDTCLRL_64_memop_unpriv,
        iemDecodeA64_sdot_za32_zzv_2x1,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_udot_za32_zzv_2x1,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_sdot_za32_zzv_4x1,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_udot_za32_zzv_4x1,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00100018 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40601c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40601c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1601c00))
        return iemDecodeA64_bfmla_za_zzv_2x1_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1601c08))
        return iemDecodeA64_bfmls_za_zzv_2x1_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1701c00))
        return iemDecodeA64_bfmla_za_zzv_4x1_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff09c18)) == UINT32_C(0xc1701c08))
        return iemDecodeA64_bfmls_za_zzv_4x1_16(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40608000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40608000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc5608000))
        return iemDecodeA64_ld1sw_z_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0xc4608000))
        return iemDecodeA64_prfb_i_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xce608000))
        return iemDecodeA64_SHA512H_QQV_cryptosha512_3(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff8000)) == UINT32_C(0xc87f8000))
        return iemDecodeA64_LDAXP_LP64_ldstexclp(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40608400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40608400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59608400))
        return iemDecodeA64_SWPTL_64_memop_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xce608400))
        return iemDecodeA64_SHA512H2_QQV_cryptosha512_3(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4060a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4060a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc560a000))
        return iemDecodeA64_ldff1sw_z_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0xc460a000))
        return iemDecodeA64_prfh_i_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5960a000))
        return iemDecodeA64_RCWSSWPPL_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4060c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4060c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc560c000))
        return iemDecodeA64_ld1w_z_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0xc460c000))
        return iemDecodeA64_prfw_i_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xce60c000))
        return iemDecodeA64_SM3PARTW1_VVV4_cryptosha512_3(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4060c800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4060c800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xce60c800))
        return iemDecodeA64_SM4EKEY_VVV4_cryptosha512_3(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5e79c800))
        return iemDecodeA64_FCVTAS_asisdmiscfp16_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f6fc40/4060e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f6fc40_4060e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc560e000))
        return iemDecodeA64_ldff1w_z_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0xc460e000))
        return iemDecodeA64_prfd_i_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0xc160e000))
        return iemDecodeA64_bfcvt_z_mz2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0xc160e020))
        return iemDecodeA64_bfcvtn_z_mz2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f6fc40/4066e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f6fc40_4066e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc01)) == UINT32_C(0xc166e000))
        return iemDecodeA64_bf1cvt_mz2_z8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc01)) == UINT32_C(0xc166e001))
        return iemDecodeA64_bf1cvtl_mz2_z8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4060e000 level 1 - mask=0x160040 entries=0x10 valid=%38 (0x6) leaf=%25 (0x4) multi-if=%12 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4060e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60f6fc40_4060e000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_sqcvtu_z_mz2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_bfcvt_z8_mz2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_60f6fc40_4066e000_2,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_sqcvtu_z_mz4,
        iemDecodeA64_sqcvtun_z_mz4,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00160040 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  6) & UINT32_C(0x00000001)) /* bit  6 L 1 -> 0 */
                        | ((uOpcode >> 16) & UINT32_C(0x00000006)) /* bit 17 L 2 -> 1 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* effefe18/c1800000 level 4 */
FNIEMOP_DEF_1(iemDecodeA64_effefe18_c1800000_4, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffc0c000)) == UINT32_C(0xd1800000))
        return iemDecodeA64_SUBG_64_addsub_immtags(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0101c)) == UINT32_C(0xc1800000))
        return iemDecodeA64_smlall_za_zzi_d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* eef8fc18/c0800000 level 3 - mask=0x1060200 entries=0x10 valid=%44 (0x7) leaf=%38 (0x6) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_eef8fc18_c0800000_3, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_mova_za_p_rz_w,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_mova_z_p_rza_w,
        iemDecodeA64_movaz_z_rza_w,
        iemDecodeA64_mova_za2_z_w1,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_mova_mz2_za_w1,
        iemDecodeA64_movaz_mz2_za_w1,
        iemDecodeA64_effefe18_c1800000_4,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x01060200 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  9) & UINT32_C(0x00000001)) /* bit  9 L 1 -> 0 */
                        | ((uOpcode >> 16) & UINT32_C(0x00000006)) /* bit 17 L 2 -> 1 */
                        | ((uOpcode >> 21) & UINT32_C(0x00000008)) /* bit 24 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* eef8fc18/c0900000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_eef8fc18_c0900000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1900020))
        return iemDecodeA64_fmlall_za32_z8z8i_2xi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff09838)) == UINT32_C(0xc1900000))
        return iemDecodeA64_smlall_za_zzi_d2xi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff001c)) == UINT32_C(0xc0900000))
        return iemDecodeA64_addha_za_pp_z_32(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff001c)) == UINT32_C(0xc0910000))
        return iemDecodeA64_addva_za_pp_z_32(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* eee0fc00/c0800000 level 2 - mask=0x180018 entries=0x10 valid=%62 (0xa) leaf=%50 (0x8) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_eee0fc00_c0800000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_eef8fc18_c0800000_3,
        iemDecodeA64_smlsll_za_zzi_d,
        iemDecodeA64_umlall_za_zzi_d,
        iemDecodeA64_umlsll_za_zzi_d,
        iemDecodeA64_luti4_mz4_ztmz2_1,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_eef8fc18_c0900000_3,
        iemDecodeA64_smlsll_za_zzi_d2xi,
        iemDecodeA64_umlall_za_zzi_d2xi,
        iemDecodeA64_umlsll_za_zzi_d2xi,
        iemDecodeA64_luti4_mz4_ztmz2_4,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00180018 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x0000000c)) /* bit 19 L 2 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40800000 level 1 - mask=0x8e000000 entries=0x10 valid=%62 (0xa) leaf=%56 (0x9) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40800000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_MOVZ_32_movewide,
        iemDecodeA64_sdot_z_zzz,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDAPURSH_64_ldapstl_unscaled,
        iemDecodeA64_CSINV_32_condsel,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_eee0fc00_c0800000_2,
        iemDecodeA64_MOVZ_64_movewide,
        iemDecodeA64_ld1sh_z_p_bz_d_x32_unscaled,
        iemDecodeA64_ERET_64E_branch_reg,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_CSINV_64_condsel,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_XAR_VVV2_crypto3_imm6,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8e000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 25) & UINT32_C(0x00000007)) /* bit 25 L 3 -> 0 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e2e0fe00/c0800400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e2e0fe00_c0800400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1c7c)) == UINT32_C(0xc0840400))
        return iemDecodeA64_mova_za4_z_w1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff1f83)) == UINT32_C(0xc0860400))
        return iemDecodeA64_mova_mz4_za_w1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40800400 level 1 - mask=0x82000200 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40800400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_udot_z_zzz,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_CSNEG_32_condsel,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_e2e0fe00_c0800400_2,
        iemDecodeA64_movaz_mz4_za_w1,
        iemDecodeA64_CSNEG_64_condsel,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x82000200 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  9) & UINT32_C(0x00000001)) /* bit  9 L 1 -> 0 */
                        | ((uOpcode >> 24) & UINT32_C(0x00000002)) /* bit 25 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40800800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40800800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xd9800800))
        return iemDecodeA64_STLR_64S_ldapstl_writeback(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xd69f0bff))
        return iemDecodeA64_ERETAA_64E_branch_reg(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 63f0fc18/41901010 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_63f0fc18_41901010_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09030)) == UINT32_C(0xc1901030))
        return iemDecodeA64_fmlal_za_z8z8i_2xi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff09038)) == UINT32_C(0xc1901010))
        return iemDecodeA64_bfmlal_za_zzi_2xi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40801000 level 1 - mask=0x3100018 entries=0x20 valid=%31 (0xa) leaf=%28 (0x9) multi-if=%3 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40801000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_fmlal_za_zzi_1,
        iemDecodeA64_fmlsl_za_zzi_1,
        iemDecodeA64_bfmlal_za_zzi_1,
        iemDecodeA64_bfmlsl_za_zzi_1,
        iemDecodeA64_fmlal_za_zzi_2xi,
        iemDecodeA64_fmlsl_za_zzi_2xi,
        iemDecodeA64_63f0fc18_41901010_2,
        iemDecodeA64_bfmlsl_za_zzi_2xi,
        iemDecodeA64_LUTI2_asimdtbl_L5,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_FMLA_asisdelem_R_SD,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x03100018 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */
                        | ((uOpcode >> 21) & UINT32_C(0x00000018)) /* bit 24 L 2 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 65e0fc00/40804000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_65e0fc00_40804000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffc4c01)) == UINT32_C(0xc08c4000))
        return iemDecodeA64_luti2_mz2_ztz_1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffc4c08)) == UINT32_C(0xc09c4000))
        return iemDecodeA64_luti2_mz2_ztz_8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffe4c01)) == UINT32_C(0xc08a4000))
        return iemDecodeA64_luti4_mz2_ztz_1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffe4c08)) == UINT32_C(0xc09a4000))
        return iemDecodeA64_luti4_mz2_ztz_8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40804000 level 1 - mask=0x5000000 entries=0x4 valid=%75 (0x3) leaf=%50 (0x2) multi-if=%25 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40804000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_65e0fc00_40804000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_ld1h_z_p_bz_d_x32_unscaled,
        iemDecodeA64_ld1d_z_p_bz_d_x32_unscaled,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x4);

    /* fMask=0x05000000 -> 0x00000003 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000002)) /* bit 26 L 1 -> 1 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40806000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40806000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc4806000))
        return iemDecodeA64_ldff1h_z_p_bz_d_x32_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc5806000))
        return iemDecodeA64_ldff1d_z_p_bz_d_x32_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40807c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40807c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x49807c00))
        return iemDecodeA64_CASPT_CP64_comswappr_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xc9807c00))
        return iemDecodeA64_CAST_C64_comswap_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x489f7c00))
        return iemDecodeA64_STLLRH_SL32_ldstord(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xc89f7c00))
        return iemDecodeA64_STLLR_SL64_ldstord(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f0fc18/40808000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f0fc18_40808000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4808000))
        return iemDecodeA64_ldnt1sh_z_p_ar_d_64_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffccc03)) == UINT32_C(0xc08c8000))
        return iemDecodeA64_luti2_mz4_ztz_1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffecc03)) == UINT32_C(0xc08a8000))
        return iemDecodeA64_luti4_mz4_ztz_1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f0fc18/40908000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f0fc18_40908000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09878)) == UINT32_C(0xc1908000))
        return iemDecodeA64_smlall_za_zzi_d4xi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffccc0c)) == UINT32_C(0xc09c8000))
        return iemDecodeA64_luti2_mz4_ztz_4(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffecc0c)) == UINT32_C(0xc09a8000))
        return iemDecodeA64_luti4_mz4_ztz_4(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40808000 level 1 - mask=0x100018 entries=0x8 valid=%62 (0x5) leaf=%38 (0x3) multi-if=%25 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40808000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60f0fc18_40808000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_60f0fc18_40908000_2,
        iemDecodeA64_smlsll_za_zzi_d4xi,
        iemDecodeA64_umlall_za_zzi_d4xi,
        iemDecodeA64_umlsll_za_zzi_d4xi,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00100018 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc38/40809000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc38_40809000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80f400)) == UINT32_C(0x5f809000))
        return iemDecodeA64_FMUL_asisdelem_R_SD(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff09078)) == UINT32_C(0xc1909000))
        return iemDecodeA64_fmlal_za_zzi_4xi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40809000 level 1 - mask=0x38 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40809000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e0fc38_40809000_2,
        iemDecodeA64_fmlsl_za_zzi_4xi,
        iemDecodeA64_bfmlal_za_zzi_4xi,
        iemDecodeA64_bfmlsl_za_zzi_4xi,
        iemDecodeA64_fmlal_za_z8z8i_4xi,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00000038 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000007)) /* bit  3 L 3 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/4080c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4080c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc480c000))
        return iemDecodeA64_ldnt1h_z_p_ar_d_64_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc580c000))
        return iemDecodeA64_ldnt1d_z_p_ar_d_64_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4080e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4080e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0xc480e000))
        return iemDecodeA64_prfh_i_p_ai_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e010)) == UINT32_C(0xc580e000))
        return iemDecodeA64_prfd_i_p_ai_d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/4080fc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_4080fc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x4980fc00))
        return iemDecodeA64_CASPLT_CP64_comswappr_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xc980fc00))
        return iemDecodeA64_CASLT_C64_comswap_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x489ffc00))
        return iemDecodeA64_STLRH_SL32_ldstord(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xc89ffc00))
        return iemDecodeA64_STLR_SL64_ldstord(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 71e0fc03/40a00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_71e0fc03_40a00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc4a00000))
        return iemDecodeA64_ld1sh_z_p_bz_d_x32_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44a00000))
        return iemDecodeA64_sdot_z_zzzi_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 71e0fc03/41a00000 level 2 - mask=0x1003c entries=0x20 valid=%38 (0xc) leaf=%38 (0xc) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_71e0fc03_41a00000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_smlall_za_zzw_2x2,
        iemDecodeA64_usmlall_za_zzw_s2x2,
        iemDecodeA64_smlsll_za_zzw_2x2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_umlall_za_zzw_2x2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_umlsll_za_zzw_2x2,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_fmlall_za32_z8z8w_2x2,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_smlall_za_zzw_4x4,
        iemDecodeA64_usmlall_za_zzw_s4x4,
        iemDecodeA64_smlsll_za_zzw_4x4,
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_umlall_za_zzw_4x4,
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_umlsll_za_zzw_4x4,
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_fmlall_za32_z8z8w_4x4,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x0001003c -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  2) & UINT32_C(0x0000000f)) /* bit  2 L 4 -> 0 */
                        | ((uOpcode >> 12) & UINT32_C(0x00000010)) /* bit 16 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40a00000 level 1 - mask=0x11000003 entries=0x10 valid=%44 (0x7) leaf=%31 (0x5) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a00000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_71e0fc03_40a00000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_71e0fc03_41a00000_2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_DRPS_64E_branch_reg,
        iemDecodeA64_DCPS1_DC_exception,
        iemDecodeA64_DCPS2_DC_exception,
        iemDecodeA64_DCPS3_DC_exception,
        iemDecodeA64_STGM_64bulk_ldsttags,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x11000003 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000003)) /* bit  0 L 2 -> 0 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000004)) /* bit 24 L 1 -> 2 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000008)) /* bit 28 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40a00400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a00400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9a00400))
        return iemDecodeA64_ST2G_64Spost_ldsttags(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44a00400))
        return iemDecodeA64_udot_z_zzzi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59a00400))
        return iemDecodeA64_LDTADDA_64_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e1fc38/40a00800 level 2 - mask=0x89000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e1fc38_40a00800_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_mla_z_zzzi_s,
        iemDecodeA64_sqrshrun_z_mz2,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_RCWSCASA_C64_rcwcomswap,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_fmlal_za_zzw_2x2,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_ST2G_64Soffset_ldsttags,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x89000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000002)) /* bit 27 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40a00800 level 1 - mask=0x10038 entries=0x10 valid=%62 (0xa) leaf=%56 (0x9) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a00800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e1fc38_40a00800_2,
        iemDecodeA64_fmlsl_za_zzw_2x2,
        iemDecodeA64_bfmlal_za_zzw_2x2,
        iemDecodeA64_bfmlsl_za_zzw_2x2,
        iemDecodeA64_fmlal_za_z8z8w_2x2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_fmlal_za_zzw_4x4,
        iemDecodeA64_fmlsl_za_zzw_4x4,
        iemDecodeA64_bfmlal_za_zzw_4x4,
        iemDecodeA64_bfmlsl_za_zzw_4x4,
        iemDecodeA64_fmlal_za_z8z8w_4x4,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00010038 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000007)) /* bit  3 L 3 -> 0 */
                        | ((uOpcode >> 13) & UINT32_C(0x00000008)) /* bit 16 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40a00c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a00c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9a00c00))
        return iemDecodeA64_ST2G_64Spre_ldsttags(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44a00c00))
        return iemDecodeA64_mls_z_zzzi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59a00c00))
        return iemDecodeA64_RCWSCASPA_C64_rcwcomswappr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a01000 level 1 - mask=0x1010038 entries=0x20 valid=%41 (0xd) leaf=%41 (0xd) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a01000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sqrdmlah_z_zzzi_s,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_fdot_za_zzw_2x2,
        iemDecodeA64_fmla_za_zzw_2x2_16,
        iemDecodeA64_bfdot_za_zzw_2x2,
        iemDecodeA64_fmls_za_zzw_2x2_16,
        iemDecodeA64_fdot_za_z8z8w_2x2,
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_fdot_za32_z8z8w_2x2,
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_fdot_za_zzw_4x4,
        iemDecodeA64_fmla_za_zzw_4x4_16,
        iemDecodeA64_bfdot_za_zzw_4x4,
        iemDecodeA64_fmls_za_zzw_4x4_16,
        iemDecodeA64_fdot_za_z8z8w_4x4,
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_fdot_za32_z8z8w_4x4,
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x01010038 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000007)) /* bit  3 L 3 -> 0 */
                        | ((uOpcode >> 13) & UINT32_C(0x00000008)) /* bit 16 L 1 -> 3 */
                        | ((uOpcode >> 20) & UINT32_C(0x00000010)) /* bit 24 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 61e1fc18/41a01400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61e1fc18_41a01400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa19c38)) == UINT32_C(0xc1a01400))
        return iemDecodeA64_sdot_za_zzw_2x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59a01400))
        return iemDecodeA64_LDTCLRA_64_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a01400 level 1 - mask=0x1010018 entries=0x10 valid=%44 (0x7) leaf=%38 (0x6) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a01400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sqrdmlsh_z_zzzi_s,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_61e1fc18_41a01400_2,
        iemDecodeA64_usdot_za_zzw_s2x2,
        iemDecodeA64_udot_za_zzw_2x2,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_sdot_za_zzw_4x4,
        iemDecodeA64_usdot_za_zzw_s4x4,
        iemDecodeA64_udot_za_zzw_4x4,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x01010018 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 14) & UINT32_C(0x00000004)) /* bit 16 L 1 -> 2 */
                        | ((uOpcode >> 21) & UINT32_C(0x00000008)) /* bit 24 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40a01800 level 1 - mask=0x1010018 entries=0x10 valid=%56 (0x9) leaf=%56 (0x9) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a01800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_usdot_z_zzzi_s,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_fmla_za_zzw_2x2,
        iemDecodeA64_fmls_za_zzw_2x2,
        iemDecodeA64_add_za_zzw_2x2,
        iemDecodeA64_sub_za_zzw_2x2,
        iemDecodeA64_fmla_za_zzw_4x4,
        iemDecodeA64_fmls_za_zzw_4x4,
        iemDecodeA64_add_za_zzw_4x4,
        iemDecodeA64_sub_za_zzw_4x4,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x01010018 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 14) & UINT32_C(0x00000004)) /* bit 16 L 1 -> 2 */
                        | ((uOpcode >> 21) & UINT32_C(0x00000008)) /* bit 24 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e5fc18/40a01c00 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e5fc18_40a01c00_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbf9c38)) == UINT32_C(0xc1a01c00))
        return iemDecodeA64_fadd_za_zw_2x2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44a01c00))
        return iemDecodeA64_sudot_z_zzzi_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a01c00 level 1 - mask=0x50018 entries=0x10 valid=%75 (0xc) leaf=%69 (0xb) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a01c00_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e5fc18_40a01c00_2,
        iemDecodeA64_fsub_za_zw_2x2,
        iemDecodeA64_add_za_zw_2x2,
        iemDecodeA64_sub_za_zw_2x2,
        iemDecodeA64_fadd_za_zw_4x4,
        iemDecodeA64_fsub_za_zw_4x4,
        iemDecodeA64_add_za_zw_4x4,
        iemDecodeA64_sub_za_zw_4x4,
        iemDecodeA64_fadd_za_zw_2x2_16,
        iemDecodeA64_fsub_za_zw_2x2_16,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_fadd_za_zw_4x4_16,
        iemDecodeA64_fsub_za_zw_4x4_16,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00050018 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 14) & UINT32_C(0x00000004)) /* bit 16 L 1 -> 2 */
                        | ((uOpcode >> 15) & UINT32_C(0x00000008)) /* bit 18 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40a02000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a02000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc4a02000))
        return iemDecodeA64_ldff1sh_z_p_bz_d_x32_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a02000))
        return iemDecodeA64_sqdmlalb_z_zzzi_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a03400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a03400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a03400))
        return iemDecodeA64_sqdmlslt_z_zzzi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59a03400))
        return iemDecodeA64_LDTSETA_64_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a04000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a04000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc4a04000))
        return iemDecodeA64_ld1h_z_p_bz_d_x32_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc5a04000))
        return iemDecodeA64_ld1d_z_p_bz_d_x32_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x44a04000))
        return iemDecodeA64_cdot_z_zzzi_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a06000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a06000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc4a06000))
        return iemDecodeA64_ldff1h_z_p_bz_d_x32_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0e000)) == UINT32_C(0xc5a06000))
        return iemDecodeA64_ldff1d_z_p_bz_d_x32_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x44a06000))
        return iemDecodeA64_cmla_z_zzzi_h(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a07c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a07c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x48a07c00))
        return iemDecodeA64_CASH_C32_comswap(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xc8a07c00))
        return iemDecodeA64_CAS_C64_comswap(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a08000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a08000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4a08000))
        return iemDecodeA64_ld1sh_z_p_ai_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a08000))
        return iemDecodeA64_smlalb_z_zzzi_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a08400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a08400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a08400))
        return iemDecodeA64_smlalt_z_zzzi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59a08400))
        return iemDecodeA64_SWPTA_64_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a09000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a09000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a09000))
        return iemDecodeA64_umlalb_z_zzzi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59a09000))
        return iemDecodeA64_RCWSCLRPA_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a0a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a0a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4a0a000))
        return iemDecodeA64_ldff1sh_z_p_ai_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a0a000))
        return iemDecodeA64_smlslb_z_zzzi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59a0a000))
        return iemDecodeA64_RCWSSWPPA_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a0b000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a0b000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a0b000))
        return iemDecodeA64_umlslb_z_zzzi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59a0b000))
        return iemDecodeA64_RCWSSETPA_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a0c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a0c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4a0c000))
        return iemDecodeA64_ld1h_z_p_ai_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc5a0c000))
        return iemDecodeA64_ld1d_z_p_ai_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44a0c000))
        return iemDecodeA64_smullb_z_zzi_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a0c800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a0c800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x5ea0c800))
        return iemDecodeA64_FCMGT_asisdmisc_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5eb0c800))
        return iemDecodeA64_FMINNMP_asisdpair_only_H(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a0d800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a0d800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x5ea0d800))
        return iemDecodeA64_FCMEQ_asisdmisc_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x5ea1d800))
        return iemDecodeA64_FRECPE_asisdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e5f7fc00/c1a0e000 level 3 */
FNIEMOP_DEF_1(iemDecodeA64_e5f7fc00_c1a0e000_3, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc01)) == UINT32_C(0xc1a0e000))
        return iemDecodeA64_fcvt_mz2_z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc01)) == UINT32_C(0xc1a0e001))
        return iemDecodeA64_fcvtl_mz2_z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc21)) == UINT32_C(0xc1a8e000))
        return iemDecodeA64_frintn_mz_z_2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f7fc00/40a0e000 level 2 - mask=0x85000000 entries=0x8 valid=%50 (0x4) leaf=%38 (0x3) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc00_40a0e000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_sqdmullb_z_zzi_s,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_e5f7fc00_c1a0e000_3,
        iemDecodeA64_ldff1h_z_p_ai_d,
        iemDecodeA64_ldff1d_z_p_ai_d,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x85000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000002)) /* bit 26 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60f7fc00/40a6e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc00_40a6e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc01)) == UINT32_C(0xc1a6e000))
        return iemDecodeA64_f2cvt_mz2_z8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc01)) == UINT32_C(0xc1a6e001))
        return iemDecodeA64_f2cvtl_mz2_z8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a0e000 level 1 - mask=0x170000 entries=0x10 valid=%56 (0x9) leaf=%44 (0x7) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a0e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60f7fc00_40a0e000_2,
        iemDecodeA64_frintp_mz_z_2,
        iemDecodeA64_frintm_mz_z_2,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_frinta_mz_z_2,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_60f7fc00_40a6e000_2,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_frintn_mz_z_4,
        iemDecodeA64_frintp_mz_z_4,
        iemDecodeA64_frintm_mz_z_4,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_frinta_mz_z_4,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00170000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000007)) /* bit 16 L 3 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40a0f800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a0f800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x5ea1f800))
        return iemDecodeA64_FRECPX_asisdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44a0f800))
        return iemDecodeA64_mul_z_zzi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5eb0f800))
        return iemDecodeA64_FMINP_asisdpair_only_H(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40a0fc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40a0fc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x5ea0fc00))
        return iemDecodeA64_FRSQRTS_asisdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x48a0fc00))
        return iemDecodeA64_CASLH_C32_comswap(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xc8a0fc00))
        return iemDecodeA64_CASL_C64_comswap(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6df0fc00/40c00000 level 2 - mask=0xf0200 entries=0x20 valid=%34 (0xb) leaf=%34 (0xb) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_6df0fc00_40c00000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_mova_za_p_rz_d,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_mova_za_p_rz_q,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_mova_z_p_rza_d,
        iemDecodeA64_movaz_z_rza_d,
        iemDecodeA64_mova_z_p_rza_q,
        iemDecodeA64_movaz_z_rza_q,
        iemDecodeA64_mova_za2_z_d1,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_mova_mz2_za_d1,
        iemDecodeA64_movaz_mz2_za_d1,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_Invalid, // 16
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_luti4_z_ztz,
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_luti2_z_ztz,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x000f0200 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  9) & UINT32_C(0x00000001)) /* bit  9 L 1 -> 0 */
                        | ((uOpcode >> 15) & UINT32_C(0x0000001e)) /* bit 16 L 4 -> 1 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 6df0fc00/40d00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6df0fc00_40d00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff0018)) == UINT32_C(0xc0d00000))
        return iemDecodeA64_addha_za_pp_z_64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff0018)) == UINT32_C(0xc0d10000))
        return iemDecodeA64_addva_za_pp_z_64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6df0fc00/41d00000 level 2 - mask=0x38 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_6df0fc00_41d00000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmla_za_zzi_d2xi,
        iemDecodeA64_sdot_za_zzi_d2xi,
        iemDecodeA64_fmls_za_zzi_d2xi,
        iemDecodeA64_udot_za_zzi_d2xi,
        iemDecodeA64_fdot_za_z8z8i_2xi,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00000038 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000007)) /* bit  3 L 3 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 6df0fc00/48c00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6df0fc00_48c00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ac00000))
        return iemDecodeA64_RBIT_32_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac00000))
        return iemDecodeA64_RBIT_64_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac10000))
        return iemDecodeA64_PACIA_64P_dp_1src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c00000 level 1 - mask=0xd100000 entries=0x10 valid=%50 (0x8) leaf=%25 (0x4) multi-if=%12 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c00000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_6df0fc00_40c00000_2,
        iemDecodeA64_6df0fc00_40d00000_2,
        iemDecodeA64_fmlal_za_z8z8i_1,
        iemDecodeA64_6df0fc00_41d00000_2,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_6df0fc00_48c00000_2,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_LDAPURSH_32_ldapstl_unscaled,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LUTI2_asimdtbl_L6,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_FMLALT_asimdelem_H,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x0d100000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 20) & UINT32_C(0x00000001)) /* bit 20 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 24) & UINT32_C(0x0000000c)) /* bit 26 L 2 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e0e7fc00/c0c60400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e0e7fc00_c0c60400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff1f03)) == UINT32_C(0xc0c60400))
        return iemDecodeA64_mova_mz4_za_d1(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff1f03)) == UINT32_C(0xc0c60600))
        return iemDecodeA64_movaz_mz4_za_d1(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c00400 level 1 - mask=0x80070000 entries=0x10 valid=%31 (0x5) leaf=%25 (0x4) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c00400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_REV16_32_dp_1src,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_REV16_64_dp_1src,
        iemDecodeA64_PACIB_64P_dp_1src,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_mova_za4_z_d1,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_e0e7fc00_c0c60400_2,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x80070000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000007)) /* bit 16 L 3 -> 0 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 61f0fc10/40c00800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61f0fc10_40c00800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ac00800))
        return iemDecodeA64_REV_32_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac00800))
        return iemDecodeA64_REV32_64_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac10800))
        return iemDecodeA64_PACDA_64P_dp_1src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c00800 level 1 - mask=0x1100010 entries=0x8 valid=%50 (0x4) leaf=%38 (0x3) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c00800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_61f0fc10_40c00800_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDAPR_64L_ldapstl_writeback,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_fvdotb_za32_z8z8i_2xi,
        iemDecodeA64_fvdott_za32_z8z8i_2xi,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x01100010 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >> 19) & UINT32_C(0x00000002)) /* bit 20 L 1 -> 1 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000004)) /* bit 24 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40c00c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c00c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac00c00))
        return iemDecodeA64_REV_64_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac10c00))
        return iemDecodeA64_PACDB_64P_dp_1src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61f0fc38/40c01000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61f0fc38_40c01000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ac01000))
        return iemDecodeA64_CLZ_32_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac01000))
        return iemDecodeA64_CLZ_64_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac11000))
        return iemDecodeA64_AUTIA_64P_dp_1src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c01000 level 1 - mask=0x1100038 entries=0x20 valid=%31 (0xa) leaf=%28 (0x9) multi-if=%3 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c01000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_61f0fc38_40c01000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_smlal_za_zzi_1,
        iemDecodeA64_smlsl_za_zzi_1,
        iemDecodeA64_umlal_za_zzi_1,
        iemDecodeA64_umlsl_za_zzi_1,
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_smlal_za_zzi_2xi,
        iemDecodeA64_smlsl_za_zzi_2xi,
        iemDecodeA64_umlal_za_zzi_2xi,
        iemDecodeA64_umlsl_za_zzi_2xi,
        iemDecodeA64_fvdot_za_z8z8i_2xi,
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x01100038 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000007)) /* bit  3 L 3 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */
                        | ((uOpcode >> 20) & UINT32_C(0x00000010)) /* bit 24 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40c01400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c01400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ac01400))
        return iemDecodeA64_CLS_32_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac01400))
        return iemDecodeA64_CLS_64_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac11400))
        return iemDecodeA64_AUTIB_64P_dp_1src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c01800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c01800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ac01800))
        return iemDecodeA64_CTZ_32_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac01800))
        return iemDecodeA64_CTZ_64_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac11800))
        return iemDecodeA64_AUTDA_64P_dp_1src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c01c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c01c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ac01c00))
        return iemDecodeA64_CNT_32_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac01c00))
        return iemDecodeA64_CNT_64_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac11c00))
        return iemDecodeA64_AUTDB_64P_dp_1src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c02000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c02000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ac02000))
        return iemDecodeA64_ABS_32_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xdac02000))
        return iemDecodeA64_ABS_64_dp_1src(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xdac123e0))
        return iemDecodeA64_PACIZA_64Z_dp_1src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c03c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c03c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5ec03c00))
        return iemDecodeA64_FRSQRTS_asisdsamefp16_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffe0)) == UINT32_C(0xdac13fe0))
        return iemDecodeA64_AUTDZB_64Z_dp_1src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c07c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c07c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x49c07c00))
        return iemDecodeA64_CASPAT_CP64_comswappr_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xc9c07c00))
        return iemDecodeA64_CASAT_C64_comswap_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x48df7c00))
        return iemDecodeA64_LDLARH_LR32_ldstord(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xc8df7c00))
        return iemDecodeA64_LDLAR_LR64_ldstord(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c08000 level 1 - mask=0x3000018 entries=0x10 valid=%44 (0x7) leaf=%44 (0x7) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c08000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_ld1sh_z_p_bz_d_64_unscaled,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_fmla_za_zzi_d4xi,
        iemDecodeA64_sdot_za_zzi_d4xi,
        iemDecodeA64_fmls_za_zzi_d4xi,
        iemDecodeA64_udot_za_zzi_d4xi,
        iemDecodeA64_SHA512SU0_VV2_cryptosha512_2,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_PACNBIASPPC_64LR_dp_1src,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x03000018 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 22) & UINT32_C(0x0000000c)) /* bit 24 L 2 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40c08400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c08400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xcec08400))
        return iemDecodeA64_SM4E_VV4_cryptosha512_2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xdac187fe))
        return iemDecodeA64_PACNBIBSPPC_64LR_dp_1src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c08800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c08800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff09878)) == UINT32_C(0xc1d08808))
        return iemDecodeA64_svdot_za_zzi_d4xi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff09878)) == UINT32_C(0xc1d08818))
        return iemDecodeA64_uvdot_za_zzi_d4xi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xdac18bfe))
        return iemDecodeA64_PACIA171615_64LR_dp_1src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c09000 level 1 - mask=0x100018 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c09000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_AUTIASPPCR_64LRR_dp_1src,
        iemDecodeA64_smlal_za_zzi_4xi,
        iemDecodeA64_smlsl_za_zzi_4xi,
        iemDecodeA64_umlal_za_zzi_4xi,
        iemDecodeA64_umlsl_za_zzi_4xi,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00100018 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40c0a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c0a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4c0a000))
        return iemDecodeA64_ldff1sh_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffffff)) == UINT32_C(0xdac1a3fe))
        return iemDecodeA64_PACIASPPC_64LR_dp_1src(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c0c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c0c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4c0c000))
        return iemDecodeA64_ld1h_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc5c0c000))
        return iemDecodeA64_ld1d_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c0e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c0e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4c0e000))
        return iemDecodeA64_ldff1h_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc5c0e000))
        return iemDecodeA64_ldff1d_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40c0fc00 level 1 - mask=0x83000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40c0fc00_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LDARH_LR32_ldstord,
        iemDecodeA64_CASPALT_CP64_comswappr_unpriv,
        iemDecodeA64_FMLALT_asimdsame2_J,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDAR_LR64_ldstord,
        iemDecodeA64_CASALT_C64_comswap_unpriv,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x83000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000003)) /* bit 24 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40e00000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e00000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44e00000))
        return iemDecodeA64_sdot_z_zzzi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xd9e00000))
        return iemDecodeA64_LDGM_64bulk_ldsttags(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e00400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e00400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9e00400))
        return iemDecodeA64_STZ2G_64Spost_ldsttags(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44e00400))
        return iemDecodeA64_udot_z_zzzi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59e00400))
        return iemDecodeA64_LDTADDAL_64_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 6ce1fc18/48e00800 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_6ce1fc18_48e00800_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9e00800))
        return iemDecodeA64_STZ2G_64Soffset_ldsttags(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59e00800))
        return iemDecodeA64_RCWSCASAL_C64_rcwcomswap(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e00800 level 1 - mask=0xc010018 entries=0x20 valid=%31 (0xa) leaf=%28 (0x9) multi-if=%3 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e00800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_smlal_za_zzw_2x2,
        iemDecodeA64_smlsl_za_zzw_2x2,
        iemDecodeA64_umlal_za_zzw_2x2,
        iemDecodeA64_umlsl_za_zzw_2x2,
        iemDecodeA64_smlal_za_zzw_4x4,
        iemDecodeA64_smlsl_za_zzw_4x4,
        iemDecodeA64_umlal_za_zzw_4x4,
        iemDecodeA64_umlsl_za_zzw_4x4,
        iemDecodeA64_mla_z_zzzi_d,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_6ce1fc18_48e00800_2,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x0c010018 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 14) & UINT32_C(0x00000004)) /* bit 16 L 1 -> 2 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000018)) /* bit 26 L 2 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40e00c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e00c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xd9e00c00))
        return iemDecodeA64_STZ2G_64Spre_ldsttags(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44e00c00))
        return iemDecodeA64_mls_z_zzzi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59e00c00))
        return iemDecodeA64_RCWSCASPAL_C64_rcwcomswappr(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e01000 level 1 - mask=0x10018 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e01000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_sqrdmlah_z_zzzi_d,
        iemDecodeA64_bfmla_za_zzw_2x2_16,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_bfmls_za_zzw_2x2_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_bfmla_za_zzw_4x4_16,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_bfmls_za_zzw_4x4_16,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00010018 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 14) & UINT32_C(0x00000004)) /* bit 16 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e1fc18/40e01400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e1fc18_40e01400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44e01400))
        return iemDecodeA64_sqrdmlsh_z_zzzi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59e01400))
        return iemDecodeA64_LDTCLRAL_64_memop_unpriv(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e01400 level 1 - mask=0x10018 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e01400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e1fc18_40e01400_2,
        iemDecodeA64_sdot_za32_zzw_2x2,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_udot_za32_zzw_2x2,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_sdot_za32_zzw_4x4,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_udot_za32_zzw_4x4,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00010018 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  3) & UINT32_C(0x00000003)) /* bit  3 L 2 -> 0 */
                        | ((uOpcode >> 14) & UINT32_C(0x00000004)) /* bit 16 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40e01c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e01c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffff9c38)) == UINT32_C(0xc1e41c00))
        return iemDecodeA64_bfadd_za_zw_2x2_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff9c38)) == UINT32_C(0xc1e41c08))
        return iemDecodeA64_bfsub_za_zw_2x2_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff9c78)) == UINT32_C(0xc1e51c00))
        return iemDecodeA64_bfadd_za_zw_4x4_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffff9c78)) == UINT32_C(0xc1e51c08))
        return iemDecodeA64_bfsub_za_zw_4x4_16(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e03400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e03400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e03400))
        return iemDecodeA64_sqdmlslt_z_zzzi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59e03400))
        return iemDecodeA64_LDTSETAL_64_memop_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5ee03400))
        return iemDecodeA64_CMGT_asisdsame_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e07c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e07c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x48e07c00))
        return iemDecodeA64_CASAH_C32_comswap(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xc8e07c00))
        return iemDecodeA64_CASA_C64_comswap(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e08000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e08000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4e08000))
        return iemDecodeA64_ld1sh_z_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e08000))
        return iemDecodeA64_smlalb_z_zzzi_d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e08400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e08400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e08400))
        return iemDecodeA64_smlalt_z_zzzi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59e08400))
        return iemDecodeA64_SWPTAL_64_memop_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x5ee08400))
        return iemDecodeA64_ADD_asisdsame_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e09000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e09000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e09000))
        return iemDecodeA64_umlalb_z_zzzi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59e09000))
        return iemDecodeA64_RCWSCLRPAL_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e0a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e0a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4e0a000))
        return iemDecodeA64_ldff1sh_z_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e0a000))
        return iemDecodeA64_smlslb_z_zzzi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59e0a000))
        return iemDecodeA64_RCWSSWPPAL_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e0a800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e0a800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ee0a800))
        return iemDecodeA64_CMLT_asisdmisc_Z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ef9a800))
        return iemDecodeA64_FCVTPS_asisdmiscfp16_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e0b000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e0b000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e0b000))
        return iemDecodeA64_umlslb_z_zzzi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x59e0b000))
        return iemDecodeA64_RCWSSETPAL_128_memop_128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e0b800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e0b800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ee0b800))
        return iemDecodeA64_ABS_asisdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ef1b800))
        return iemDecodeA64_ADDP_asisdpair_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ef9b800))
        return iemDecodeA64_FCVTZS_asisdmiscfp16_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e0c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e0c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc4e0c000))
        return iemDecodeA64_ld1h_z_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xc5e0c000))
        return iemDecodeA64_ld1d_z_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e0c000))
        return iemDecodeA64_smullb_z_zzi_d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e0d400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e0d400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x44e0d400))
        return iemDecodeA64_umullt_z_zzi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc20)) == UINT32_C(0xc1e0d400))
        return iemDecodeA64_sqrshr_z_mz2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc20)) == UINT32_C(0xc1e0d420))
        return iemDecodeA64_uqrshr_z_mz2(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0fc20)) == UINT32_C(0xc1f0d400))
        return iemDecodeA64_sqrshru_z_mz2(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e0d800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e0d800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ef8d800))
        return iemDecodeA64_FCMEQ_asisdmiscfp16_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ef9d800))
        return iemDecodeA64_FRECPE_asisdmiscfp16_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e5e0fc00/c1e0e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e5e0fc00_c1e0e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc01)) == UINT32_C(0xc1e6e000))
        return iemDecodeA64_bf2cvt_mz2_z8(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc01)) == UINT32_C(0xc1e6e001))
        return iemDecodeA64_bf2cvtl_mz2_z8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e0e000 level 1 - mask=0x85000000 entries=0x8 valid=%50 (0x4) leaf=%38 (0x3) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e0e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_sqdmullb_z_zzi_d,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_e5e0fc00_c1e0e000_2,
        iemDecodeA64_ldff1h_z_p_bz_d_64_scaled,
        iemDecodeA64_ldff1d_z_p_bz_d_64_scaled,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x85000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000002)) /* bit 26 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/40e0f800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e0f800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x44e0f800))
        return iemDecodeA64_mul_z_zzi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x5ef9f800))
        return iemDecodeA64_FRECPX_asisdmiscfp16_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/40e0fc00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_40e0fc00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x48e0fc00))
        return iemDecodeA64_CASALH_C32_comswap(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xc8e0fc00))
        return iemDecodeA64_CASAL_C64_comswap(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ffe0fc00/65000000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ffe0fc00_65000000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x65000000))
        return iemDecodeA64_fadd_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x65000000))
        return iemDecodeA64_bfadd_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60000000 level 1 - mask=0x9f000000 entries=0x40 valid=%52 (0x21) leaf=%50 (0x20) multi-if=%2 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60000000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_fcmla_z_p_zzz,
        iemDecodeA64_ffe0fc00_65000000_2,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_STGP_64_ldstpair_off,
        iemDecodeA64_ANDS_32_log_shift,
        iemDecodeA64_SUBS_32_addsub_shift,
        iemDecodeA64_STNP_D_ldstnapair_offs,
        iemDecodeA64_STP_D_ldstpair_off,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_Invalid, // 16
        iemDecodeA64_SUBS_32S_addsub_imm,
        iemDecodeA64_ANDS_32S_log_imm,
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_CBGT_32_regs,
        iemDecodeA64_CBGT_32_imm,
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_STURH_32_ldst_unscaled,
        iemDecodeA64_STRH_32_ldst_pos,
        iemDecodeA64_SBCS_32_addsub_carry,
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_STUR_H_ldst_unscaled,
        iemDecodeA64_STR_H_ldst_pos,
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
        iemDecodeA64_ld1b_za_p_rrr,
        iemDecodeA64_ldr_za_ri,
        iemDecodeA64_Invalid, // 34
        iemDecodeA64_Invalid, // 35
        iemDecodeA64_Invalid, // 36
        iemDecodeA64_Invalid, // 37
        iemDecodeA64_Invalid, // 38
        iemDecodeA64_Invalid, // 39
        iemDecodeA64_STTNP_64_ldstnapair_offs,
        iemDecodeA64_STTP_64_ldstpair_off,
        iemDecodeA64_ANDS_64_log_shift,
        iemDecodeA64_SUBS_64_addsub_shift,
        iemDecodeA64_STTNP_Q_ldstnapair_offs,
        iemDecodeA64_STTP_Q_ldstpair_off,
        iemDecodeA64_Invalid, // 46
        iemDecodeA64_Invalid, // 47
        iemDecodeA64_Invalid, // 48
        iemDecodeA64_SUBS_64S_addsub_imm,
        iemDecodeA64_ANDS_64S_log_imm,
        iemDecodeA64_Invalid, // 51
        iemDecodeA64_CBGT_64_regs,
        iemDecodeA64_CBGT_64_imm,
        iemDecodeA64_Invalid, // 54
        iemDecodeA64_Invalid, // 55
        iemDecodeA64_STUR_64_ldst_unscaled,
        iemDecodeA64_STR_64_ldst_pos,
        iemDecodeA64_SBCS_64_addsub_carry,
        iemDecodeA64_Invalid, // 59
        iemDecodeA64_STUR_D_ldst_unscaled,
        iemDecodeA64_STR_D_ldst_pos,
        iemDecodeA64_Invalid, // 62
        iemDecodeA64_Invalid, // 63
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x40);

    /* fMask=0x9f000000 -> 0x0000003f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x0000001f)) /* bit 24 L 5 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000020)) /* bit 31 L 1 -> 5 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e7e0fc00/65000400 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e7e0fc00_65000400_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x65000400))
        return iemDecodeA64_fsub_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x65000400))
        return iemDecodeA64_bfsub_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60000400 level 1 - mask=0x87000000 entries=0x10 valid=%44 (0x7) leaf=%38 (0x6) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60000400_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_STRH_32_ldst_immpost,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_STR_H_ldst_immpost,
        iemDecodeA64_e7e0fc00_65000400_2,
        iemDecodeA64_INS_asimdins_IV_v,
        iemDecodeA64_USHR_asisdshf_R,
        iemDecodeA64_STR_64_ldst_immpost,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_STR_D_ldst_immpost,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x87000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000007)) /* bit 24 L 3 -> 0 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60000800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60000800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x65000800))
        return iemDecodeA64_fmul_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78000800))
        return iemDecodeA64_STTRH_32_ldst_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xf8000800))
        return iemDecodeA64_STTR_64_ldst_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x65000800))
        return iemDecodeA64_bfmul_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60000c00 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60000c00_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_ftsmul_z_zz,
        iemDecodeA64_STRH_32_ldst_immpre,
        iemDecodeA64_STR_H_ldst_immpre,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_STR_64_ldst_immpre,
        iemDecodeA64_STR_D_ldst_immpre,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e7fc10/60002000 level 2 - mask=0x81180000 entries=0x10 valid=%31 (0x5) leaf=%31 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e7fc10_60002000_2, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_faddv_v_p_z,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_fcmge_p_p_z0,
        iemDecodeA64_fadda_v_p_z,
        iemDecodeA64_stnt1b_z_p_ar_d_64_unscaled,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_stnt1w_z_p_ar_d_64_unscaled,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x81180000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 19) & UINT32_C(0x00000003)) /* bit 19 L 2 -> 0 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000004)) /* bit 24 L 1 -> 2 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60002000 level 1 - mask=0x70010 entries=0x10 valid=%62 (0xa) leaf=%56 (0x9) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60002000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e7fc10_60002000_2,
        iemDecodeA64_fcmgt_p_p_z0,
        iemDecodeA64_fcmlt_p_p_z0,
        iemDecodeA64_fcmle_p_p_z0,
        iemDecodeA64_fcmeq_p_p_z0,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_fcmne_p_p_z0,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_fmaxnmv_v_p_z,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_fminnmv_v_p_z,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_fmaxv_v_p_z,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_fminv_v_p_z,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00070010 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  4) & UINT32_C(0x00000001)) /* bit  4 L 1 -> 0 */
                        | ((uOpcode >> 15) & UINT32_C(0x0000000e)) /* bit 16 L 3 -> 1 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60003000 level 1 - mask=0x70000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60003000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_f1cvt_z_z8_b2h,
        iemDecodeA64_f1cvtlt_z_z8_b2h,
        iemDecodeA64_fcvtn_z8_mz2_h2b,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_frecpe_z_z,
        iemDecodeA64_frsqrte_z_z,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00070000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000007)) /* bit 16 L 3 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60003400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60003400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f003400))
        return iemDecodeA64_URSRA_asisdshf_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x65083400))
        return iemDecodeA64_f2cvt_z_z8_b2h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x65093400))
        return iemDecodeA64_f2cvtlt_z_z8_b2h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0x650a3400))
        return iemDecodeA64_fcvtnb_z8_mz2_s2b(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60003800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60003800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x65083800))
        return iemDecodeA64_bf1cvt_z_z8_b2bf(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x65093800))
        return iemDecodeA64_bf1cvtlt_z_z8_b2bf(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0x650a3800))
        return iemDecodeA64_bfcvtn_z8_mz2_bf2b(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60003c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60003c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x65083c00))
        return iemDecodeA64_bf2cvt_z_z8_b2bf(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x65093c00))
        return iemDecodeA64_bf2cvtlt_z_z8_b2bf(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc20)) == UINT32_C(0x650a3c00))
        return iemDecodeA64_fcvtnt_z8_mz2_s2b(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60004000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60004000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x65004000))
        return iemDecodeA64_fcmge_p_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x65004010))
        return iemDecodeA64_fcmgt_p_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff80e000)) == UINT32_C(0xe4004000))
        return iemDecodeA64_st1b_z_p_br(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5004000))
        return iemDecodeA64_st1w_z_p_br_u128(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60006000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60006000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x65006000))
        return iemDecodeA64_fcmeq_p_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x65006010))
        return iemDecodeA64_fcmne_p_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4006000))
        return iemDecodeA64_stnt1b_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5006000))
        return iemDecodeA64_stnt1w_z_p_br_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61fffc00/60008000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_60008000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ee000)) == UINT32_C(0x64008000))
        return iemDecodeA64_fcadd_z_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0a000)) == UINT32_C(0xe4008000))
        return iemDecodeA64_st1b_z_p_bz_d_x32_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74008000))
        return iemDecodeA64_CBBGT_8_regs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61fffc00/61008000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_61008000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65008000))
        return iemDecodeA64_fadd_z_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0f400)) == UINT32_C(0x6f008000))
        return iemDecodeA64_FMLALLTB_asimdelem_J(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0a000)) == UINT32_C(0xe5008000))
        return iemDecodeA64_st1w_z_p_bz_d_x32_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65008000))
        return iemDecodeA64_bfadd_z_p_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61fffc00/61018000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_61018000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65018000))
        return iemDecodeA64_fsub_z_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65018000))
        return iemDecodeA64_bfsub_z_p_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61fffc00/61028000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_61028000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65028000))
        return iemDecodeA64_fmul_z_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65028000))
        return iemDecodeA64_bfmul_z_p_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61fffc00/61048000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_61048000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65048000))
        return iemDecodeA64_fmaxnm_z_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65048000))
        return iemDecodeA64_bfmaxnm_z_p_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61fffc00/61058000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_61058000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65058000))
        return iemDecodeA64_fminnm_z_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65058000))
        return iemDecodeA64_bfminnm_z_p_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61fffc00/61068000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_61068000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65068000))
        return iemDecodeA64_fmax_z_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65068000))
        return iemDecodeA64_bfmax_z_p_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61fffc00/61078000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_61078000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65078000))
        return iemDecodeA64_fmin_z_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65078000))
        return iemDecodeA64_bfmin_z_p_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61fffc00/61098000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_61098000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x65098000))
        return iemDecodeA64_fscale_z_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x65098000))
        return iemDecodeA64_bfscale_z_p_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61fffc00/611f8000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_611f8000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe3c0)) == UINT32_C(0x651f8000))
        return iemDecodeA64_fmin_z_p_zs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc1f)) == UINT32_C(0xe11f8000))
        return iemDecodeA64_ldr_zt_br(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60008000 level 1 - mask=0x11f0000 entries=0x40 valid=%56 (0x24) leaf=%41 (0x1a) multi-if=%16 (0xa) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60008000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_61fffc00_60008000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_faddp_z_p_zz,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_fmaxnmp_z_p_zz,
        iemDecodeA64_fminnmp_z_p_zz,
        iemDecodeA64_fmaxp_z_p_zz,
        iemDecodeA64_fminp_z_p_zz,
        iemDecodeA64_frintn_z_p_z_z,
        iemDecodeA64_frinta_z_p_z_z,
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_frecpx_z_p_z_z,
        iemDecodeA64_frint32z_z_p_z_z,
        iemDecodeA64_frint64z_z_p_z_z,
        iemDecodeA64_flogb_z_p_z_z,
        iemDecodeA64_Invalid, // 31
        iemDecodeA64_61fffc00_61008000_2,
        iemDecodeA64_61fffc00_61018000_2,
        iemDecodeA64_61fffc00_61028000_2,
        iemDecodeA64_fsubr_z_p_zz,
        iemDecodeA64_61fffc00_61048000_2,
        iemDecodeA64_61fffc00_61058000_2,
        iemDecodeA64_61fffc00_61068000_2,
        iemDecodeA64_61fffc00_61078000_2,
        iemDecodeA64_fabd_z_p_zz,
        iemDecodeA64_61fffc00_61098000_2,
        iemDecodeA64_fmulx_z_p_zz,
        iemDecodeA64_Invalid, // 43
        iemDecodeA64_fdivr_z_p_zz,
        iemDecodeA64_fdiv_z_p_zz,
        iemDecodeA64_famax_z_p_zz,
        iemDecodeA64_famin_z_p_zz,
        iemDecodeA64_ftmad_z_zzi,
        iemDecodeA64_Invalid, // 49
        iemDecodeA64_Invalid, // 50
        iemDecodeA64_Invalid, // 51
        iemDecodeA64_Invalid, // 52
        iemDecodeA64_Invalid, // 53
        iemDecodeA64_Invalid, // 54
        iemDecodeA64_Invalid, // 55
        iemDecodeA64_fadd_z_p_zs,
        iemDecodeA64_fsub_z_p_zs,
        iemDecodeA64_fmul_z_p_zs,
        iemDecodeA64_fsubr_z_p_zs,
        iemDecodeA64_fmaxnm_z_p_zs,
        iemDecodeA64_fminnm_z_p_zs,
        iemDecodeA64_fmax_z_p_zs,
        iemDecodeA64_61fffc00_611f8000_2,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x40);

    /* fMask=0x011f0000 -> 0x0000003f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */
                        | ((uOpcode >> 19) & UINT32_C(0x00000020)) /* bit 24 L 1 -> 5 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60008400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60008400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x7e008400))
        return iemDecodeA64_SQRDMLAH_asisdsame2_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f008400))
        return iemDecodeA64_SQSHRUN_asisdshf_N(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60008c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60008c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x7e008c00))
        return iemDecodeA64_SQRDMLSH_asisdsame2_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f008c00))
        return iemDecodeA64_SQRSHRUN_asisdshf_N(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 61fffc00/6100a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fffc00_6100a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6500a000))
        return iemDecodeA64_frintn_z_p_z_m(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe500a000))
        return iemDecodeA64_st1w_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6000a000 level 1 - mask=0x11f0000 entries=0x40 valid=%42 (0x1b) leaf=%41 (0x1a) multi-if=%2 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6000a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_st1b_z_p_bz_d_64_unscaled,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_fcvtxnt_z_p_z_d2sz,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_fcvtxnt_z_p_z_d2s,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_faddqv_z_p_z,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_fmaxnmqv_z_p_z,
        iemDecodeA64_fminnmqv_z_p_z,
        iemDecodeA64_fmaxqv_z_p_z,
        iemDecodeA64_fminqv_z_p_z,
        iemDecodeA64_frintp_z_p_z_z,
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_fsqrt_z_p_z_z,
        iemDecodeA64_frint32x_z_p_z_z,
        iemDecodeA64_frint64x_z_p_z_z,
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
        iemDecodeA64_61fffc00_6100a000_2,
        iemDecodeA64_frintp_z_p_z_m,
        iemDecodeA64_frintm_z_p_z_m,
        iemDecodeA64_frintz_z_p_z_m,
        iemDecodeA64_frinta_z_p_z_m,
        iemDecodeA64_Invalid, // 37
        iemDecodeA64_frintx_z_p_z_m,
        iemDecodeA64_frinti_z_p_z_m,
        iemDecodeA64_Invalid, // 40
        iemDecodeA64_Invalid, // 41
        iemDecodeA64_fcvtx_z_p_z_d2s,
        iemDecodeA64_Invalid, // 43
        iemDecodeA64_frecpx_z_p_z_m,
        iemDecodeA64_fsqrt_z_p_z_m,
        iemDecodeA64_Invalid, // 46
        iemDecodeA64_Invalid, // 47
        iemDecodeA64_frint32z_z_p_z_m,
        iemDecodeA64_frint32x_z_p_z_m,
        iemDecodeA64_Invalid, // 50
        iemDecodeA64_Invalid, // 51
        iemDecodeA64_frint64z_z_p_z_m,
        iemDecodeA64_frint64x_z_p_z_m,
        iemDecodeA64_Invalid, // 54
        iemDecodeA64_Invalid, // 55
        iemDecodeA64_flogb_z_p_z_m,
        iemDecodeA64_Invalid, // 57
        iemDecodeA64_Invalid, // 58
        iemDecodeA64_Invalid, // 59
        iemDecodeA64_Invalid, // 60
        iemDecodeA64_Invalid, // 61
        iemDecodeA64_Invalid, // 62
        iemDecodeA64_Invalid, // 63
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x40);

    /* fMask=0x011f0000 -> 0x0000003f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */
                        | ((uOpcode >> 19) & UINT32_C(0x00000020)) /* bit 24 L 1 -> 5 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 61ebfc00/6100c000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61ebfc00_6100c000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x6500c000))
        return iemDecodeA64_fcmuo_p_p_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff20e010)) == UINT32_C(0x6500c010))
        return iemDecodeA64_facge_p_p_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6000c000 level 1 - mask=0x10b0000 entries=0x10 valid=%31 (0x5) leaf=%25 (0x4) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6000c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_CBHGT_16_regs,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_frintm_z_p_z_z,
        iemDecodeA64_frintx_z_p_z_z,
        iemDecodeA64_fcvtx_z_p_z_d2sz,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_61ebfc00_6100c000_2,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x010b0000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000003)) /* bit 16 L 2 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000004)) /* bit 19 L 1 -> 2 */
                        | ((uOpcode >> 21) & UINT32_C(0x00000008)) /* bit 24 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* e1f0fc00/6010e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e1f0fc00_6010e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6418e000))
        return iemDecodeA64_frintz_z_p_z_z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xff3fe000)) == UINT32_C(0x6419e000))
        return iemDecodeA64_frinti_z_p_z_z(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6000e000 level 1 - mask=0x81100000 entries=0x8 valid=%75 (0x6) leaf=%62 (0x5) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6000e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_e1f0fc00_6010e000_2,
        iemDecodeA64_facgt_p_p_zz,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_st1b_z_p_bi,
        iemDecodeA64_stnt1b_z_p_bi_contiguous,
        iemDecodeA64_st1w_z_p_bi_u128,
        iemDecodeA64_stnt1w_z_p_bi_contiguous,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x81100000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 20) & UINT32_C(0x00000001)) /* bit 20 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/6000e400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6000e400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80fc00)) == UINT32_C(0x7f00e400))
        return iemDecodeA64_UCVTF_asisdshf_C(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff8fc00)) == UINT32_C(0x6f00e400))
        return iemDecodeA64_MOVI_asimdimm_D2_d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* fde0fc00/65200000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_fde0fc00_65200000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x65200000))
        return iemDecodeA64_fmla_z_p_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x65200000))
        return iemDecodeA64_bfmla_z_p_zzz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60200000 level 1 - mask=0x9d000000 entries=0x20 valid=%50 (0x10) leaf=%47 (0xf) multi-if=%3 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60200000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_fmla_z_zzzi_h,
        iemDecodeA64_fde0fc00_65200000_2,
        iemDecodeA64_BICS_32_log_shift,
        iemDecodeA64_SUBS_32S_addsub_ext,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_CBGE_32_regs,
        iemDecodeA64_CBLT_32_imm,
        iemDecodeA64_LDADDH_32_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_LDFADD_16,
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_st1b_za_p_rrr,
        iemDecodeA64_str_za_ri,
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_BICS_64_log_shift,
        iemDecodeA64_SUBS_64S_addsub_ext,
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_CBGE_64_regs,
        iemDecodeA64_CBLT_64_imm,
        iemDecodeA64_LDADD_64_memop,
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_LDFADD_64,
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x9d000000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x0000000e)) /* bit 26 L 3 -> 1 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000010)) /* bit 31 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60200400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60200400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa00c00)) == UINT32_C(0xf8200400))
        return iemDecodeA64_LDRAA_64_ldst_pac(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x64200400))
        return iemDecodeA64_fmls_z_zzzi_h(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60200800 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60200800_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_bfmla_z_zzzi_h,
        iemDecodeA64_STRH_32_ldst_regoff,
        iemDecodeA64_STR_H_ldst_regoff,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_STR_64_ldst_regoff,
        iemDecodeA64_STR_D_ldst_regoff,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60200c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60200c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x7e200c00))
        return iemDecodeA64_UQADD_asisdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa00c00)) == UINT32_C(0xf8200c00))
        return iemDecodeA64_LDRAA_64W_ldst_pac(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x64200c00))
        return iemDecodeA64_bfmls_z_zzzi_h(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60201000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60201000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78201000))
        return iemDecodeA64_LDCLRH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8201000))
        return iemDecodeA64_LDCLR_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* e5e0fc00/65202000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_e5e0fc00_65202000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x65202000))
        return iemDecodeA64_fmls_z_p_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0x65202000))
        return iemDecodeA64_bfmls_z_p_zzz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60202000 level 1 - mask=0x85000000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60202000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_LDEORH_32_memop,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_fmul_z_zzi_h,
        iemDecodeA64_e5e0fc00_65202000_2,
        iemDecodeA64_LDEOR_64_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_st1q_z_p_ar_d_64_unscaled,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x85000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000002)) /* bit 26 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60202400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60202400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20fc00)) == UINT32_C(0x64202400))
        return iemDecodeA64_fclamp_z_zz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64202400))
        return iemDecodeA64_bfclamp_z_zz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60202800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60202800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff3ffc00)) == UINT32_C(0x7e212800))
        return iemDecodeA64_SQXTUN_asisdmisc_N(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x64202800))
        return iemDecodeA64_bfmul_z_zzi_h(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60203000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60203000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78203000))
        return iemDecodeA64_LDSETH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8203000))
        return iemDecodeA64_LDSET_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc00/64204000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc00_64204000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x65204000))
        return iemDecodeA64_fnmla_z_p_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64204000))
        return iemDecodeA64_fdot_z_zzzi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60204000 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60204000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_ece0fc00_64204000_2,
        iemDecodeA64_LDSMAXH_32_memop,
        iemDecodeA64_LDFMAX_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDSMAX_64_memop,
        iemDecodeA64_LDFMAX_64,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60205000 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60205000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_fmlalb_z_z8z8z8i,
        iemDecodeA64_LDSMINH_32_memop,
        iemDecodeA64_LDFMIN_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDSMIN_64_memop,
        iemDecodeA64_LDFMIN_64,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* ece0fc00/e4206000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc00_e4206000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4206000))
        return iemDecodeA64_st2b_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5206000))
        return iemDecodeA64_st2w_z_p_br_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60206000 level 1 - mask=0x8c000000 entries=0x8 valid=%75 (0x6) leaf=%62 (0x5) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60206000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_fnmls_z_p_zzz,
        iemDecodeA64_LDUMAXH_32_memop,
        iemDecodeA64_LDFMAXNM_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_ece0fc00_e4206000_2,
        iemDecodeA64_LDUMAX_64_memop,
        iemDecodeA64_LDFMAXNM_64,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60207000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60207000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78207000))
        return iemDecodeA64_LDUMINH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7c207000))
        return iemDecodeA64_LDFMINNM_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8207000))
        return iemDecodeA64_LDUMIN_64_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfc207000))
        return iemDecodeA64_LDFMINNM_64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* fce0fc00/64208000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_fce0fc00_64208000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x65208000))
        return iemDecodeA64_fmad_z_p_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64208000))
        return iemDecodeA64_fdot_z_zzz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60208000 level 1 - mask=0x9c000000 entries=0x10 valid=%50 (0x8) leaf=%44 (0x7) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60208000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_fce0fc00_64208000_2,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_CBBGE_8_regs,
        iemDecodeA64_SWPH_32_memop,
        iemDecodeA64_STFADD_16,
        iemDecodeA64_str_zt_br,
        iemDecodeA64_st1w_z_p_bz_d_x32_scaled,
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_SWP_64_memop,
        iemDecodeA64_STFADD_64,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x9c000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000007)) /* bit 26 L 3 -> 0 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60209000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60209000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78209000))
        return iemDecodeA64_RCWSCLR_64_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xf83f9000))
        return iemDecodeA64_ST64B_64L_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6020a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6020a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff20e000)) == UINT32_C(0x6520a000))
        return iemDecodeA64_fmsb_z_p_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe520a000))
        return iemDecodeA64_st1w_z_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7820a000))
        return iemDecodeA64_RCWSSWP_64_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf820a000))
        return iemDecodeA64_ST64BV0_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6020a800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6020a800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7e21a800))
        return iemDecodeA64_FCVTNU_asisdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x6420a800))
        return iemDecodeA64_fmlalltb_z32_z8z8z8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6020b000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6020b000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7820b000))
        return iemDecodeA64_RCWSSET_64_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf820b000))
        return iemDecodeA64_ST64BV_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6020b800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6020b800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7e21b800))
        return iemDecodeA64_FCVTMU_asisdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x6420b800))
        return iemDecodeA64_fmlalltt_z32_z8z8z8(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6020c000 level 1 - mask=0x99000000 entries=0x10 valid=%31 (0x5) leaf=%31 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6020c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmlallbb_z32_z8z8z8i,
        iemDecodeA64_fnmad_z_p_zzz,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_CBHGE_16_regs,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_STFMAX_16,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_STFMAX_64,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x99000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000006)) /* bit 27 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/6020c800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6020c800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7e21c800))
        return iemDecodeA64_FCVTAU_asisdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7e30c800))
        return iemDecodeA64_FMAXNMP_asisdpair_only_SD(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x6e30c800))
        return iemDecodeA64_FMAXNMV_asimdall_only_SD(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6020d000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6020d000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x7c20d01f))
        return iemDecodeA64_STFMIN_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xfc20d01f))
        return iemDecodeA64_STFMIN_64(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xf83fd000))
        return iemDecodeA64_LD64B_64L_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6020d800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6020d800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7e21d800))
        return iemDecodeA64_UCVTF_asisdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7e30d800))
        return iemDecodeA64_FADDP_asisdpair_only_SD(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6020e000 level 1 - mask=0x89000000 entries=0x8 valid=%75 (0x6) leaf=%75 (0x6) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6020e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmmla_z32_zz8z8,
        iemDecodeA64_fnmsb_z_p_zzz,
        iemDecodeA64_STFMAXNM_16,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_st2b_z_p_bi_contiguous,
        iemDecodeA64_st2w_z_p_bi_contiguous,
        iemDecodeA64_STFMAXNM_64,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x89000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000002)) /* bit 27 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/6020e400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6020e400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x7e20e400))
        return iemDecodeA64_FCMGE_asisdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x6420e400))
        return iemDecodeA64_fmmla_z32_zzz_h(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6020f000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6020f000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x7c20f01f))
        return iemDecodeA64_STFMINNM_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xfc20f01f))
        return iemDecodeA64_STFMINNM_64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6020f800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6020f800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7e30f800))
        return iemDecodeA64_FMAXP_asisdpair_only_SD(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x6e30f800))
        return iemDecodeA64_FMAXV_asimdall_only_SD(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* fde0fc00/78400000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_fde0fc00_78400000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78400000))
        return iemDecodeA64_LDURH_32_ldst_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0x7a400000))
        return iemDecodeA64_CCMP_32_condcmp_reg(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* fde0fc00/f8400000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_fde0fc00_f8400000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xf8400000))
        return iemDecodeA64_LDUR_64_ldst_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0xfa400000))
        return iemDecodeA64_CCMP_64_condcmp_reg(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60400000 level 1 - mask=0x9d000000 entries=0x20 valid=%66 (0x15) leaf=%59 (0x13) multi-if=%6 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60400000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_LDPSW_64_ldstpair_off,
        iemDecodeA64_LDNP_D_ldstnapair_offs,
        iemDecodeA64_LDP_D_ldstpair_off,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_CBHI_32_regs,
        iemDecodeA64_CBHI_32_imm,
        iemDecodeA64_fde0fc00_78400000_2,
        iemDecodeA64_LDRH_32_ldst_pos,
        iemDecodeA64_LDUR_H_ldst_unscaled,
        iemDecodeA64_LDR_H_ldst_pos,
        iemDecodeA64_ld1h_za_p_rrr,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_st2q_z_p_bi_contiguous,
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_LDTNP_64_ldstnapair_offs,
        iemDecodeA64_LDTP_64_ldstpair_off,
        iemDecodeA64_LDTNP_Q_ldstnapair_offs,
        iemDecodeA64_LDTP_Q_ldstpair_off,
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_CBHI_64_regs,
        iemDecodeA64_CBHI_64_imm,
        iemDecodeA64_fde0fc00_f8400000_2,
        iemDecodeA64_LDR_64_ldst_pos,
        iemDecodeA64_LDUR_D_ldst_unscaled,
        iemDecodeA64_LDR_D_ldst_pos,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x9d000000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x0000000e)) /* bit 26 L 3 -> 1 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000010)) /* bit 31 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60400400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60400400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78400400))
        return iemDecodeA64_LDRH_32_ldst_immpost(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x7c400400))
        return iemDecodeA64_LDR_H_ldst_immpost(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xf8400400))
        return iemDecodeA64_LDR_64_ldst_immpost(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xfc400400))
        return iemDecodeA64_LDR_D_ldst_immpost(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60400800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60400800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78400800))
        return iemDecodeA64_LDTRH_32_ldst_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xf8400800))
        return iemDecodeA64_LDTR_64_ldst_unpriv(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0x7a400800))
        return iemDecodeA64_CCMP_32_condcmp_imm(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c10)) == UINT32_C(0xfa400800))
        return iemDecodeA64_CCMP_64_condcmp_imm(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60400c00 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60400c00_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78400c00))
        return iemDecodeA64_LDRH_32_ldst_immpre(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x7c400c00))
        return iemDecodeA64_LDR_H_ldst_immpre(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xf8400c00))
        return iemDecodeA64_LDR_64_ldst_immpre(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xfc400c00))
        return iemDecodeA64_LDR_D_ldst_immpre(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60402000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60402000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4402000))
        return iemDecodeA64_stnt1b_z_p_ar_s_x32_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5402000))
        return iemDecodeA64_stnt1w_z_p_ar_s_x32_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60406000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60406000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4406000))
        return iemDecodeA64_st3b_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5406000))
        return iemDecodeA64_st3w_z_p_br_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* f1e0fc00/60408000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_f1e0fc00_60408000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x645d8000))
        return iemDecodeA64_scvtf_z_p_z_w2fp16z(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x645f8000))
        return iemDecodeA64_fcvtzs_z_p_z_fp162wz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60408000 level 1 - mask=0x91000000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60408000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_f1e0fc00_60408000_2,
        iemDecodeA64_FMLALLTT_asimdelem_J,
        iemDecodeA64_CBBHI_8_regs,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_st1b_z_p_bz_s_x32_unscaled,
        iemDecodeA64_st1w_z_p_bz_s_x32_unscaled,
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x91000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000002)) /* bit 28 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/6040a000 level 1 - mask=0x10f0000 entries=0x20 valid=%50 (0x10) leaf=%50 (0x10) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6040a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_st1b_z_p_ai_d,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_ucvtf_z_p_z_w2fp16z,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_fcvtzu_z_p_z_fp162wz,
        iemDecodeA64_st1w_z_p_ai_d,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_scvtf_z_p_z_h2fp16,
        iemDecodeA64_ucvtf_z_p_z_h2fp16,
        iemDecodeA64_scvtf_z_p_z_w2fp16,
        iemDecodeA64_ucvtf_z_p_z_w2fp16,
        iemDecodeA64_scvtf_z_p_z_x2fp16,
        iemDecodeA64_ucvtf_z_p_z_x2fp16,
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_fcvtzs_z_p_z_fp162h,
        iemDecodeA64_fcvtzu_z_p_z_fp162h,
        iemDecodeA64_fcvtzs_z_p_z_fp162w,
        iemDecodeA64_fcvtzu_z_p_z_fp162w,
        iemDecodeA64_fcvtzs_z_p_z_fp162x,
        iemDecodeA64_fcvtzu_z_p_z_fp162x,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x010f0000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000000f)) /* bit 16 L 4 -> 0 */
                        | ((uOpcode >> 20) & UINT32_C(0x00000010)) /* bit 24 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/6040c000 level 1 - mask=0x70000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6040c000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_CBHHI_16_regs,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_scvtf_z_p_z_h2fp16z,
        iemDecodeA64_scvtf_z_p_z_x2fp16z,
        iemDecodeA64_fcvtzs_z_p_z_fp162hz,
        iemDecodeA64_fcvtzs_z_p_z_fp162xz,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00070000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000007)) /* bit 16 L 3 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60f7fc00/6050e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f7fc00_6050e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe450e000))
        return iemDecodeA64_st3b_z_p_bi_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe550e000))
        return iemDecodeA64_st3w_z_p_bi_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6040e000 level 1 - mask=0x170000 entries=0x10 valid=%38 (0x6) leaf=%31 (0x5) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6040e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_st1w_z_p_bi,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_60f7fc00_6050e000_2,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_ucvtf_z_p_z_h2fp16z,
        iemDecodeA64_ucvtf_z_p_z_x2fp16z,
        iemDecodeA64_fcvtzu_z_p_z_fp162hz,
        iemDecodeA64_fcvtzu_z_p_z_fp162xz,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x00170000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000007)) /* bit 16 L 3 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x00000008)) /* bit 20 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* ede0fc00/e4600000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_e4600000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0xf4600000))
        return iemDecodeA64_CBHS_64_regs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4600000))
        return iemDecodeA64_st2q_z_p_br_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60600000 level 1 - mask=0x8d000000 entries=0x10 valid=%56 (0x9) leaf=%50 (0x8) multi-if=%6 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60600000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_CBHS_32_regs,
        iemDecodeA64_CBLO_32_imm,
        iemDecodeA64_LDADDLH_32_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDFADDL_16,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_st1h_za_p_rrr,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_ede0fc00_e4600000_2,
        iemDecodeA64_CBLO_64_imm,
        iemDecodeA64_LDADDL_64_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_LDFADDL_64,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8d000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60600800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60600800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78600800))
        return iemDecodeA64_LDRH_32_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x7c600800))
        return iemDecodeA64_LDR_H_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xf8600800))
        return iemDecodeA64_LDR_64_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xfc600800))
        return iemDecodeA64_LDR_D_ldst_regoff(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60601000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60601000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78601000))
        return iemDecodeA64_LDCLRLH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8601000))
        return iemDecodeA64_LDCLRL_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60602000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60602000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78602000))
        return iemDecodeA64_LDEORLH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8602000))
        return iemDecodeA64_LDEORL_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60603000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60603000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78603000))
        return iemDecodeA64_LDSETLH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8603000))
        return iemDecodeA64_LDSETL_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60604000 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60604000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_bfdot_z_zzzi,
        iemDecodeA64_LDSMAXLH_32_memop,
        iemDecodeA64_LDFMAXL_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDSMAXL_64_memop,
        iemDecodeA64_LDFMAXL_64,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60605000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60605000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78605000))
        return iemDecodeA64_LDSMINLH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7c605000))
        return iemDecodeA64_LDFMINL_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8605000))
        return iemDecodeA64_LDSMINL_64_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfc605000))
        return iemDecodeA64_LDFMINL_64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ece0fc00/e4606000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ece0fc00_e4606000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4606000))
        return iemDecodeA64_st4b_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5606000))
        return iemDecodeA64_st4w_z_p_br_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60606000 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60606000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_LDUMAXLH_32_memop,
        iemDecodeA64_LDFMAXNML_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_ece0fc00_e4606000_2,
        iemDecodeA64_LDUMAXL_64_memop,
        iemDecodeA64_LDFMAXNML_64,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60607000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60607000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78607000))
        return iemDecodeA64_LDUMINLH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7c607000))
        return iemDecodeA64_LDFMINNML_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8607000))
        return iemDecodeA64_LDUMINL_64_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfc607000))
        return iemDecodeA64_LDFMINNML_64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60608000 level 1 - mask=0x98000001 entries=0x10 valid=%44 (0x7) leaf=%44 (0x7) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60608000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_bfdot_z_zzz,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_CBBHS_8_regs,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_SWPLH_32_memop,
        iemDecodeA64_STFADDL_16,
        iemDecodeA64_st1w_z_p_bz_s_x32_scaled,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_SWPL_64_memop,
        iemDecodeA64_STFADDL_64,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x98000001 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >> 26) & UINT32_C(0x00000006)) /* bit 27 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/6060a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6060a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe460a000))
        return iemDecodeA64_st1b_z_p_ai_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe560a000))
        return iemDecodeA64_st1w_z_p_ai_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7860a000))
        return iemDecodeA64_RCWSSWPL_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6060c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6060c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x7460c000))
        return iemDecodeA64_CBHHS_16_regs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x6460c000))
        return iemDecodeA64_fmlallbt_z32_z8z8z8i(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x7c60c01f))
        return iemDecodeA64_STFMAXL_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xfc60c01f))
        return iemDecodeA64_STFMAXL_64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6060d000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6060d000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x7c60d01f))
        return iemDecodeA64_STFMINL_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xfc60d01f))
        return iemDecodeA64_STFMINL_64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6060e000 level 1 - mask=0x81000001 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6060e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_fmmla_z16_zz8z8,
        iemDecodeA64_STFMAXNML_16,
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_st4b_z_p_bi_contiguous,
        iemDecodeA64_STFMAXNML_64,
        iemDecodeA64_st4w_z_p_bi_contiguous,
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x81000001 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >>  0) & UINT32_C(0x00000001)) /* bit  0 L 1 -> 0 */
                        | ((uOpcode >> 23) & UINT32_C(0x00000002)) /* bit 24 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/6060f000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6060f000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0x7c60f01f))
        return iemDecodeA64_STFMINNML_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc1f)) == UINT32_C(0xfc60f01f))
        return iemDecodeA64_STFMINNML_64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60800000 level 1 - mask=0x9d000000 entries=0x20 valid=%56 (0x12) leaf=%56 (0x12) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60800000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_STGP_64_ldstpair_post,
        iemDecodeA64_STGP_64_ldstpair_pre,
        iemDecodeA64_STP_D_ldstpair_post,
        iemDecodeA64_STP_D_ldstpair_pre,
        iemDecodeA64_MOVK_32_movewide,
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LDURSH_64_ldst_unscaled,
        iemDecodeA64_LDRSH_64_ldst_pos,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_ld1w_za_p_rrr,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_st3q_z_p_bi_contiguous,
        iemDecodeA64_str_p_bi,
        iemDecodeA64_STTP_64_ldstpair_post,
        iemDecodeA64_STTP_64_ldstpair_pre,
        iemDecodeA64_STTP_Q_ldstpair_post,
        iemDecodeA64_STTP_Q_ldstpair_pre,
        iemDecodeA64_MOVK_64_movewide,
        iemDecodeA64_AUTIASPPC_only_dp_1src_imm,
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_PRFUM_P_ldst_unscaled,
        iemDecodeA64_PRFM_P_ldst_pos,
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x9d000000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x0000000e)) /* bit 26 L 3 -> 1 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000010)) /* bit 31 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60802000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60802000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4802000))
        return iemDecodeA64_stnt1h_z_p_ar_d_64_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5802000))
        return iemDecodeA64_stnt1d_z_p_ar_d_64_unscaled(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60804000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60804000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff80e000)) == UINT32_C(0xe4804000))
        return iemDecodeA64_st1h_z_p_br(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffc0e000)) == UINT32_C(0xe5804000))
        return iemDecodeA64_str_z_bi(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60806000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60806000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4806000))
        return iemDecodeA64_stnt1h_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5806000))
        return iemDecodeA64_stnt1d_z_p_br_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60808000 level 1 - mask=0x1030000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60808000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_st1h_z_p_bz_d_x32_unscaled,
        iemDecodeA64_scvtf_z_p_z_w2sz,
        iemDecodeA64_fcvt_z_p_z_s2hz,
        iemDecodeA64_fcvtzs_z_p_z_s2wz,
        iemDecodeA64_st1d_z_p_bz_d_x32_unscaled,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x01030000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000003)) /* bit 16 L 2 -> 0 */
                        | ((uOpcode >> 22) & UINT32_C(0x00000004)) /* bit 24 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 61fbfc00/6080a000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_61fbfc00_6080a000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe480a000))
        return iemDecodeA64_st1h_z_p_bz_d_64_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x6480a000))
        return iemDecodeA64_fcvtnt_z_p_z_s2hz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/6080a000 level 1 - mask=0x11b0000 entries=0x20 valid=%53 (0x11) leaf=%50 (0x10) multi-if=%3 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6080a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_61fbfc00_6080a000_2,
        iemDecodeA64_fcvtlt_z_p_z_h2sz,
        iemDecodeA64_bfcvtnt_z_p_z_s2bfz,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_fcvtnt_z_p_z_s2h,
        iemDecodeA64_fcvtlt_z_p_z_h2s,
        iemDecodeA64_bfcvtnt_z_p_z_s2bf,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_Invalid, // 10
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_ucvtf_z_p_z_w2sz,
        iemDecodeA64_fcvt_z_p_z_h2sz,
        iemDecodeA64_fcvtzu_z_p_z_s2wz,
        iemDecodeA64_st1d_z_p_bz_d_64_unscaled,
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_fcvt_z_p_z_s2h,
        iemDecodeA64_fcvt_z_p_z_h2s,
        iemDecodeA64_bfcvt_z_p_z_s2bf,
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_scvtf_z_p_z_w2s,
        iemDecodeA64_ucvtf_z_p_z_w2s,
        iemDecodeA64_Invalid, // 26
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_fcvtzs_z_p_z_s2w,
        iemDecodeA64_fcvtzu_z_p_z_s2w,
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x011b0000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000003)) /* bit 16 L 2 -> 0 */
                        | ((uOpcode >> 17) & UINT32_C(0x0000000c)) /* bit 19 L 2 -> 2 */
                        | ((uOpcode >> 20) & UINT32_C(0x00000010)) /* bit 24 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/6080e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_6080e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xff90e000)) == UINT32_C(0xe480e000))
        return iemDecodeA64_st1h_z_p_bi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe490e000))
        return iemDecodeA64_stnt1h_z_p_bi_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe590e000))
        return iemDecodeA64_stnt1d_z_p_bi_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a00000 level 1 - mask=0x8d000000 entries=0x10 valid=%50 (0x8) leaf=%50 (0x8) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a00000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_fmla_z_zzzi_s,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDADDAH_32_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDFADDA_16,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_st1w_za_p_rrr,
        iemDecodeA64_AUTIBSPPC_only_dp_1src_imm,
        iemDecodeA64_st3q_z_p_br_contiguous,
        iemDecodeA64_Invalid, // 11
        iemDecodeA64_LDADDA_64_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_LDFADDA_64,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8d000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60a00400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a00400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa00c00)) == UINT32_C(0xf8a00400))
        return iemDecodeA64_LDRAB_64_ldst_pac(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64a00400))
        return iemDecodeA64_fmls_z_zzzi_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a00800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a00800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0x78a00800))
        return iemDecodeA64_LDRSH_64_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xf8a00800))
        return iemDecodeA64_PRFM_P_ldst_regoff(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe00c00)) == UINT32_C(0xf8a00800))
        return iemDecodeA64_RPRFM_R_ldst_regoff(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a01000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a01000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x64a01000))
        return iemDecodeA64_fcmla_z_zzzi_h(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78a01000))
        return iemDecodeA64_LDCLRAH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8a01000))
        return iemDecodeA64_LDCLRA_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a02000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a02000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64a02000))
        return iemDecodeA64_fmul_z_zzi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78a02000))
        return iemDecodeA64_LDEORAH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8a02000))
        return iemDecodeA64_LDEORA_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a03000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a03000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78a03000))
        return iemDecodeA64_LDSETAH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8a03000))
        return iemDecodeA64_LDSETA_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a04000 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a04000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_fmlalb_z_zzzi_s,
        iemDecodeA64_LDSMAXAH_32_memop,
        iemDecodeA64_LDFMAXA_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDSMAXA_64_memop,
        iemDecodeA64_LDFMAXA_64,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60a05000 level 1 - mask=0x8c000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a05000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_fmlalt_z_z8z8z8i,
        iemDecodeA64_LDSMINAH_32_memop,
        iemDecodeA64_LDFMINA_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDSMINA_64_memop,
        iemDecodeA64_LDFMINA_64,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60a06000 level 1 - mask=0x8d000000 entries=0x10 valid=%44 (0x7) leaf=%44 (0x7) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a06000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_fmlslb_z_zzzi_s,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDUMAXAH_32_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDFMAXNMA_16,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_st2h_z_p_br_contiguous,
        iemDecodeA64_st2d_z_p_br_contiguous,
        iemDecodeA64_LDUMAXA_64_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_LDFMAXNMA_64,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8d000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60a07000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a07000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78a07000))
        return iemDecodeA64_LDUMINAH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ca07000))
        return iemDecodeA64_LDFMINNMA_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8a07000))
        return iemDecodeA64_LDUMINA_64_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfca07000))
        return iemDecodeA64_LDFMINNMA_64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a08000 level 1 - mask=0x85000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a08000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_SWPAH_32_memop,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_fmlalb_z_zzz,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_SWPA_64_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_st1h_z_p_bz_d_x32_scaled,
        iemDecodeA64_st1d_z_p_bz_d_x32_scaled,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x85000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000002)) /* bit 26 L 1 -> 1 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60a0a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a0a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4a0a000))
        return iemDecodeA64_st1h_z_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5a0a000))
        return iemDecodeA64_st1d_z_p_bz_d_64_scaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64a0a000))
        return iemDecodeA64_fmlslb_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78a0a000))
        return iemDecodeA64_RCWSSWPA_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a0c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a0c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x64a0c000))
        return iemDecodeA64_fmlalltb_z32_z8z8z8i(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x78bfc000))
        return iemDecodeA64_LDAPRH_32L_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0xf8bfc000))
        return iemDecodeA64_LDAPR_64L_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a0c800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a0c800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7ea0c800))
        return iemDecodeA64_FCMGE_asisdmisc_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7eb0c800))
        return iemDecodeA64_FMINNMP_asisdpair_only_SD(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x6eb0c800))
        return iemDecodeA64_FMINNMV_asimdall_only_SD(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a0d800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a0d800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7ea0d800))
        return iemDecodeA64_FCMLE_asisdmisc_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7ea1d800))
        return iemDecodeA64_FRSQRTE_asisdmisc_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a0e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a0e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe4b0e000))
        return iemDecodeA64_st2h_z_p_bi_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe5b0e000))
        return iemDecodeA64_st2d_z_p_bi_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a0e400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a0e400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffa0fc00)) == UINT32_C(0x7ea0e400))
        return iemDecodeA64_FCMGT_asisdsame_only(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64a0e400))
        return iemDecodeA64_fmmla_z_zzz_s(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60a0f800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60a0f800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffbffc00)) == UINT32_C(0x7eb0f800))
        return iemDecodeA64_FMINP_asisdpair_only_SD(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x6eb0f800))
        return iemDecodeA64_FMINV_asimdall_only_SD(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60c00000 level 1 - mask=0x9d000000 entries=0x20 valid=%53 (0x11) leaf=%53 (0x11) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60c00000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDPSW_64_ldstpair_post,
        iemDecodeA64_LDPSW_64_ldstpair_pre,
        iemDecodeA64_LDP_D_ldstpair_post,
        iemDecodeA64_LDP_D_ldstpair_pre,
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_CBEQ_32_regs,
        iemDecodeA64_CBEQ_32_imm,
        iemDecodeA64_LDURSH_32_ldst_unscaled,
        iemDecodeA64_LDRSH_32_ldst_pos,
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_ld1d_za_p_rrr,
        iemDecodeA64_ld1q_za_p_rrr,
        iemDecodeA64_st4q_z_p_bi_contiguous,
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_LDTP_64_ldstpair_post,
        iemDecodeA64_LDTP_64_ldstpair_pre,
        iemDecodeA64_LDTP_Q_ldstpair_post,
        iemDecodeA64_LDTP_Q_ldstpair_pre,
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_CBEQ_64_regs,
        iemDecodeA64_CBEQ_64_imm,
        iemDecodeA64_Invalid, // 28
        iemDecodeA64_Invalid, // 29
        iemDecodeA64_Invalid, // 30
        iemDecodeA64_Invalid, // 31
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x20);

    /* fMask=0x9d000000 -> 0x0000001f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x0000000e)) /* bit 26 L 3 -> 1 */
                        | ((uOpcode >> 27) & UINT32_C(0x00000010)) /* bit 31 L 1 -> 4 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60c06000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60c06000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4c06000))
        return iemDecodeA64_st3h_z_p_br_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe5c06000))
        return iemDecodeA64_st3d_z_p_br_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e7fc00/60c08000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60e7fc00_60c08000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0a000)) == UINT32_C(0xe4c08000))
        return iemDecodeA64_st1h_z_p_bz_s_x32_unscaled(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74c08000))
        return iemDecodeA64_CBBEQ_8_regs(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60c08000 level 1 - mask=0x70000 entries=0x8 valid=%75 (0x6) leaf=%62 (0x5) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60c08000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_60e7fc00_60c08000_2,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_fcvt_z_p_z_d2hz,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_scvtf_z_p_z_w2dz,
        iemDecodeA64_scvtf_z_p_z_x2sz,
        iemDecodeA64_fcvtzs_z_p_z_d2wz,
        iemDecodeA64_fcvtzs_z_p_z_s2xz,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00070000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000007)) /* bit 16 L 3 -> 0 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60c0a000 level 1 - mask=0x11f0000 entries=0x40 valid=%42 (0x1b) leaf=%42 (0x1b) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60c0a000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_st1h_z_p_ai_d,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_fcvtnt_z_p_z_d2sz,
        iemDecodeA64_fcvtlt_z_p_z_s2dz,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_fcvtnt_z_p_z_d2s,
        iemDecodeA64_fcvtlt_z_p_z_s2d,
        iemDecodeA64_Invalid, // 12
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_Invalid, // 14
        iemDecodeA64_Invalid, // 15
        iemDecodeA64_Invalid, // 16
        iemDecodeA64_Invalid, // 17
        iemDecodeA64_Invalid, // 18
        iemDecodeA64_Invalid, // 19
        iemDecodeA64_Invalid, // 20
        iemDecodeA64_Invalid, // 21
        iemDecodeA64_Invalid, // 22
        iemDecodeA64_Invalid, // 23
        iemDecodeA64_Invalid, // 24
        iemDecodeA64_Invalid, // 25
        iemDecodeA64_fcvt_z_p_z_h2dz,
        iemDecodeA64_Invalid, // 27
        iemDecodeA64_ucvtf_z_p_z_w2dz,
        iemDecodeA64_ucvtf_z_p_z_x2sz,
        iemDecodeA64_fcvtzu_z_p_z_d2wz,
        iemDecodeA64_fcvtzu_z_p_z_s2xz,
        iemDecodeA64_st1d_z_p_ai_d,
        iemDecodeA64_Invalid, // 33
        iemDecodeA64_Invalid, // 34
        iemDecodeA64_Invalid, // 35
        iemDecodeA64_Invalid, // 36
        iemDecodeA64_Invalid, // 37
        iemDecodeA64_Invalid, // 38
        iemDecodeA64_Invalid, // 39
        iemDecodeA64_fcvt_z_p_z_d2h,
        iemDecodeA64_fcvt_z_p_z_h2d,
        iemDecodeA64_fcvt_z_p_z_d2s,
        iemDecodeA64_fcvt_z_p_z_s2d,
        iemDecodeA64_Invalid, // 44
        iemDecodeA64_Invalid, // 45
        iemDecodeA64_Invalid, // 46
        iemDecodeA64_Invalid, // 47
        iemDecodeA64_scvtf_z_p_z_w2d,
        iemDecodeA64_ucvtf_z_p_z_w2d,
        iemDecodeA64_Invalid, // 50
        iemDecodeA64_Invalid, // 51
        iemDecodeA64_scvtf_z_p_z_x2s,
        iemDecodeA64_ucvtf_z_p_z_x2s,
        iemDecodeA64_scvtf_z_p_z_x2d,
        iemDecodeA64_ucvtf_z_p_z_x2d,
        iemDecodeA64_fcvtzs_z_p_z_d2w,
        iemDecodeA64_fcvtzu_z_p_z_d2w,
        iemDecodeA64_Invalid, // 58
        iemDecodeA64_Invalid, // 59
        iemDecodeA64_fcvtzs_z_p_z_s2x,
        iemDecodeA64_fcvtzu_z_p_z_s2x,
        iemDecodeA64_fcvtzs_z_p_z_d2x,
        iemDecodeA64_fcvtzu_z_p_z_d2x,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x40);

    /* fMask=0x011f0000 -> 0x0000003f */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x0000001f)) /* bit 16 L 5 -> 0 */
                        | ((uOpcode >> 19) & UINT32_C(0x00000020)) /* bit 24 L 1 -> 5 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60c0c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60c0c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74c0c000))
        return iemDecodeA64_CBHEQ_16_regs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64dac000))
        return iemDecodeA64_fcvt_z_p_z_d2sz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64ddc000))
        return iemDecodeA64_scvtf_z_p_z_x2dz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffffe000)) == UINT32_C(0x64dfc000))
        return iemDecodeA64_fcvtzs_z_p_z_d2xz(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60f3fc00/60d0e000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_60f3fc00_60d0e000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe4d0e000))
        return iemDecodeA64_st3h_z_p_bi_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe5d0e000))
        return iemDecodeA64_st3d_z_p_bi_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60c0e000 level 1 - mask=0x130000 entries=0x8 valid=%62 (0x5) leaf=%50 (0x4) multi-if=%12 (0x1) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60c0e000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_st1d_z_p_bi_u128,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_Invalid, // 2
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_60f3fc00_60d0e000_2,
        iemDecodeA64_ucvtf_z_p_z_x2dz,
        iemDecodeA64_fcvt_z_p_z_s2dz,
        iemDecodeA64_fcvtzu_z_p_z_d2xz,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x00130000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 16) & UINT32_C(0x00000003)) /* bit 16 L 2 -> 0 */
                        | ((uOpcode >> 18) & UINT32_C(0x00000004)) /* bit 20 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* ede0fc00/64e00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_64e00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74e00000))
        return iemDecodeA64_CBNE_32_regs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64e00000))
        return iemDecodeA64_fmla_z_zzzi_d(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* ede0fc00/e4e00000 level 2 */
FNIEMOP_DEF_1(iemDecodeA64_ede0fc00_e4e00000_2, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0xf4e00000))
        return iemDecodeA64_CBNE_64_regs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4e00000))
        return iemDecodeA64_st4q_z_p_br_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60e00000 level 1 - mask=0x8d000000 entries=0x10 valid=%62 (0xa) leaf=%50 (0x8) multi-if=%12 (0x2) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e00000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_ede0fc00_64e00000_2,
        iemDecodeA64_CBNE_32_imm,
        iemDecodeA64_LDADDALH_32_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDFADDAL_16,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_st1d_za_p_rrr,
        iemDecodeA64_st1q_za_p_rrr,
        iemDecodeA64_ede0fc00_e4e00000_2,
        iemDecodeA64_CBNE_64_imm,
        iemDecodeA64_LDADDAL_64_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_LDFADDAL_64,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8d000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60e01000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e01000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x64e01000))
        return iemDecodeA64_fcmla_z_zzzi_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78e01000))
        return iemDecodeA64_LDCLRALH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8e01000))
        return iemDecodeA64_LDCLRAL_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60e02000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e02000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64e02000))
        return iemDecodeA64_fmul_z_zzi_d(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78e02000))
        return iemDecodeA64_LDEORALH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8e02000))
        return iemDecodeA64_LDEORAL_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60e03000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e03000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78e03000))
        return iemDecodeA64_LDSETALH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8e03000))
        return iemDecodeA64_LDSETAL_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60e04000 level 1 - mask=0x8c000000 entries=0x8 valid=%75 (0x6) leaf=%75 (0x6) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e04000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_bfmlalb_z_zzzi,
        iemDecodeA64_LDSMAXALH_32_memop,
        iemDecodeA64_LDFMAXAL_16,
        iemDecodeA64_Invalid, // 4
        iemDecodeA64_st1d_z_p_br,
        iemDecodeA64_LDSMAXAL_64_memop,
        iemDecodeA64_LDFMAXAL_64,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x8c000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 26) & UINT32_C(0x00000003)) /* bit 26 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60e04400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e04400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0f400)) == UINT32_C(0x64e04400))
        return iemDecodeA64_bfmlalt_z_zzzi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ee04400))
        return iemDecodeA64_USHL_asisdsame_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60e05000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e05000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78e05000))
        return iemDecodeA64_LDSMINALH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ce05000))
        return iemDecodeA64_LDFMINAL_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8e05000))
        return iemDecodeA64_LDSMINAL_64_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfce05000))
        return iemDecodeA64_LDFMINAL_64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60e06000 level 1 - mask=0x8d000000 entries=0x10 valid=%44 (0x7) leaf=%44 (0x7) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e06000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_Invalid, // 0
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_bfmlslb_z_zzzi,
        iemDecodeA64_Invalid, // 3
        iemDecodeA64_LDUMAXALH_32_memop,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_LDFMAXNMAL_16,
        iemDecodeA64_Invalid, // 7
        iemDecodeA64_Invalid, // 8
        iemDecodeA64_Invalid, // 9
        iemDecodeA64_st4h_z_p_br_contiguous,
        iemDecodeA64_st4d_z_p_br_contiguous,
        iemDecodeA64_LDUMAXAL_64_memop,
        iemDecodeA64_Invalid, // 13
        iemDecodeA64_LDFMAXNMAL_64,
        iemDecodeA64_Invalid, // 15
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x10);

    /* fMask=0x8d000000 -> 0x0000000f */
    uintptr_t const idx = ((uOpcode >> 24) & UINT32_C(0x00000001)) /* bit 24 L 1 -> 0 */
                        | ((uOpcode >> 25) & UINT32_C(0x00000006)) /* bit 26 L 2 -> 1 */
                        | ((uOpcode >> 28) & UINT32_C(0x00000008)) /* bit 31 L 1 -> 3 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60e07000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e07000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78e07000))
        return iemDecodeA64_LDUMINALH_32_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ce07000))
        return iemDecodeA64_LDFMINNMAL_16(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xf8e07000))
        return iemDecodeA64_LDUMINAL_64_memop(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0xfce07000))
        return iemDecodeA64_LDFMINNMAL_64(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60e08000 level 1 - mask=0x98000000 entries=0x8 valid=%62 (0x5) leaf=%62 (0x5) multi-if=%0 (0x0) */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e08000_1, uint32_t, uOpcode)
{
    static PFIEMOPU32 const s_apfn[] =
    {
        iemDecodeA64_bfmlalb_z_zzz,
        iemDecodeA64_Invalid, // 1
        iemDecodeA64_CBBNE_8_regs,
        iemDecodeA64_SWPALH_32_memop,
        iemDecodeA64_st1h_z_p_bz_s_x32_scaled,
        iemDecodeA64_Invalid, // 5
        iemDecodeA64_Invalid, // 6
        iemDecodeA64_SWPAL_64_memop,
    };
    AssertCompile(RT_ELEMENTS(s_apfn) == 0x8);

    /* fMask=0x98000000 -> 0x00000007 */
    uintptr_t const idx = ((uOpcode >> 27) & UINT32_C(0x00000003)) /* bit 27 L 2 -> 0 */
                        | ((uOpcode >> 29) & UINT32_C(0x00000004)) /* bit 31 L 1 -> 2 */;
    return s_apfn[idx](pVCpu, uOpcode);
}

/* 60e0fc00/60e08400 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e08400_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64e08400))
        return iemDecodeA64_bfmlalt_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x7ee08400))
        return iemDecodeA64_SUB_asisdsame_only(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60e0a000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e0a000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0e000)) == UINT32_C(0xe4e0a000))
        return iemDecodeA64_st1h_z_p_ai_s(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x64e0a000))
        return iemDecodeA64_bfmlslb_z_zzz(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0fc00)) == UINT32_C(0x78e0a000))
        return iemDecodeA64_RCWSSWPAL_64_memop(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60e0b800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e0b800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7ee0b800))
        return iemDecodeA64_NEG_asisdmisc_R(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7ef9b800))
        return iemDecodeA64_FCVTZU_asisdmiscfp16_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60e0c000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e0c000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xffe0c000)) == UINT32_C(0x74e0c000))
        return iemDecodeA64_CBHNE_16_regs(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xffe0f000)) == UINT32_C(0x64e0c000))
        return iemDecodeA64_fmlalltt_z32_z8z8z8i(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60e0d800 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e0d800_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7ef8d800))
        return iemDecodeA64_FCMLE_asisdmiscfp16_FZ(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfffffc00)) == UINT32_C(0x7ef9d800))
        return iemDecodeA64_FRSQRTE_asisdmiscfp16_R(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 60e0fc00/60e0e000 level 1 */
FNIEMOP_DEF_1(iemDecodeA64_60e0fc00_60e0e000_1, uint32_t, uOpcode)
{
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe4f0e000))
        return iemDecodeA64_st4h_z_p_bi_contiguous(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe5e0e000))
        return iemDecodeA64_st1d_z_p_bi(pVCpu, uOpcode);
    if ((uOpcode & UINT32_C(0xfff0e000)) == UINT32_C(0xe5f0e000))
        return iemDecodeA64_st4d_z_p_bi_contiguous(pVCpu, uOpcode);
    return iemDecodeA64_Invalid(pVCpu, uOpcode);
}

/* 00000000/00000000 level 0 - mask=0x60e0fc00 entries=0x800 valid=%52 (0x433) leaf=%19 (0x18a) multi-if=%23 (0x1d5) */
PFIEMOPU32 const g_apfnIemInterpretOnlyA64[] =
{
    iemDecodeA64_60e0fc00_00000000_1,
    iemDecodeA64_60e0fc00_00000400_1,
    iemDecodeA64_60e0fc00_00000800_1,
    iemDecodeA64_DUP_asimdins_DR_r,
    iemDecodeA64_60e0fc00_00001000_1,
    iemDecodeA64_60e0fc00_00001400_1,
    iemDecodeA64_60e0fc00_00001800_1,
    iemDecodeA64_Invalid, // 7
    iemDecodeA64_60e0fc00_00002000_1,
    iemDecodeA64_60e0fc00_00002400_1,
    iemDecodeA64_TRN1_asimdperm_only,
    iemDecodeA64_SMOV_asimdins_W_w,
    iemDecodeA64_60e0fc00_00003000_1,
    iemDecodeA64_60e0fc00_00003400_1,
    iemDecodeA64_ZIP1_asimdperm_only,
    iemDecodeA64_UMOV_asimdins_W_w,
    iemDecodeA64_60e0fc00_00004000_1,
    iemDecodeA64_60e0fc00_00004400_1,
    iemDecodeA64_Invalid, // 18
    iemDecodeA64_Invalid, // 19
    iemDecodeA64_60e0fc00_00005000_1,
    iemDecodeA64_60e0fc00_00005400_1,
    iemDecodeA64_UZP2_asimdperm_only,
    iemDecodeA64_Invalid, // 23
    iemDecodeA64_60e0fc00_00006000_1,
    iemDecodeA64_60e0fc00_00006400_1,
    iemDecodeA64_TRN2_asimdperm_only,
    iemDecodeA64_Invalid, // 27
    iemDecodeA64_60e0fc00_00007000_1,
    iemDecodeA64_60e0fc00_00007400_1,
    iemDecodeA64_ZIP2_asimdperm_only,
    iemDecodeA64_60e0fc00_00007c00_1,
    iemDecodeA64_60e0fc00_00008000_1,
    iemDecodeA64_60e0fc00_00008400_1,
    iemDecodeA64_Invalid, // 34
    iemDecodeA64_RSHRN_asimdshf_N,
    iemDecodeA64_FMUL_asimdelem_RH_H,
    iemDecodeA64_60e0fc00_00009400_1,
    iemDecodeA64_Invalid, // 38
    iemDecodeA64_SQRSHRN_asimdshf_N,
    iemDecodeA64_60e0fc00_0000a000_1,
    iemDecodeA64_60e0fc00_0000a400_1,
    iemDecodeA64_Invalid, // 42
    iemDecodeA64_Invalid, // 43
    iemDecodeA64_SQDMULL_asimdelem_L,
    iemDecodeA64_60e0fc00_0000b400_1,
    iemDecodeA64_Invalid, // 46
    iemDecodeA64_Invalid, // 47
    iemDecodeA64_60e0fc00_0000c000_1,
    iemDecodeA64_60e0fc00_0000c400_1,
    iemDecodeA64_Invalid, // 50
    iemDecodeA64_Invalid, // 51
    iemDecodeA64_SQRDMULH_asimdelem_R,
    iemDecodeA64_60e0fc00_0000d400_1,
    iemDecodeA64_Invalid, // 54
    iemDecodeA64_Invalid, // 55
    iemDecodeA64_60e0fc00_0000e000_1,
    iemDecodeA64_60e0fc00_0000e400_1,
    iemDecodeA64_Invalid, // 58
    iemDecodeA64_Invalid, // 59
    iemDecodeA64_SUDOT_asimdelem_D,
    iemDecodeA64_60e0fc00_0000f400_1,
    iemDecodeA64_Invalid, // 62
    iemDecodeA64_60e0fc00_0000fc00_1,
    iemDecodeA64_60e0fc00_00200000_1,
    iemDecodeA64_60e0fc00_00200400_1,
    iemDecodeA64_60e0fc00_00200800_1,
    iemDecodeA64_60e0fc00_00200c00_1,
    iemDecodeA64_60e0fc00_00201000_1,
    iemDecodeA64_60e0fc00_00201400_1,
    iemDecodeA64_60e0fc00_00201800_1,
    iemDecodeA64_60e0fc00_00201c00_1,
    iemDecodeA64_60e0fc00_00202000_1,
    iemDecodeA64_60e0fc00_00202400_1,
    iemDecodeA64_60e0fc00_00202800_1,
    iemDecodeA64_60e0fc00_00202c00_1,
    iemDecodeA64_60e0fc00_00203000_1,
    iemDecodeA64_60e0fc00_00203400_1,
    iemDecodeA64_60e0fc00_00203800_1,
    iemDecodeA64_60e0fc00_00203c00_1,
    iemDecodeA64_60e0fc00_00204000_1,
    iemDecodeA64_60e0fc00_00204400_1,
    iemDecodeA64_60e0fc00_00204800_1,
    iemDecodeA64_60e0fc00_00204c00_1,
    iemDecodeA64_60e0fc00_00205000_1,
    iemDecodeA64_60e0fc00_00205400_1,
    iemDecodeA64_60e0fc00_00205800_1,
    iemDecodeA64_SQRSHL_asimdsame_only,
    iemDecodeA64_60e0fc00_00206000_1,
    iemDecodeA64_60e0fc00_00206400_1,
    iemDecodeA64_60e0fc00_00206800_1,
    iemDecodeA64_60e0fc00_00206c00_1,
    iemDecodeA64_60e0fc00_00207000_1,
    iemDecodeA64_60e0fc00_00207400_1,
    iemDecodeA64_60e0fc00_00207800_1,
    iemDecodeA64_60e0fc00_00207c00_1,
    iemDecodeA64_60e0fc00_00208000_1,
    iemDecodeA64_60e0fc00_00208400_1,
    iemDecodeA64_60e0fc00_00208800_1,
    iemDecodeA64_60e0fc00_00208c00_1,
    iemDecodeA64_60e0fc00_00209000_1,
    iemDecodeA64_60e0fc00_00209400_1,
    iemDecodeA64_60e0fc00_00209800_1,
    iemDecodeA64_60e0fc00_00209c00_1,
    iemDecodeA64_60e0fc00_0020a000_1,
    iemDecodeA64_60e0fc00_0020a400_1,
    iemDecodeA64_60e0fc00_0020a800_1,
    iemDecodeA64_SMINP_asimdsame_only,
    iemDecodeA64_60e0fc00_0020b000_1,
    iemDecodeA64_SQDMULH_asimdsame_only,
    iemDecodeA64_60e0fc00_0020b800_1,
    iemDecodeA64_60e0fc00_0020bc00_1,
    iemDecodeA64_60e0fc00_0020c000_1,
    iemDecodeA64_FMAXNM_asimdsame_only,
    iemDecodeA64_60e0fc00_0020c800_1,
    iemDecodeA64_FMLA_asimdsame_only,
    iemDecodeA64_SQDMULL_asimddiff_L,
    iemDecodeA64_FADD_asimdsame_only,
    iemDecodeA64_SCVTF_asimdmisc_R,
    iemDecodeA64_60e0fc00_0020dc00_1,
    iemDecodeA64_60e0fc00_0020e000_1,
    iemDecodeA64_60e0fc00_0020e400_1,
    iemDecodeA64_FRINT32Z_asimdmisc_R,
    iemDecodeA64_FMLAL_asimdsame_F,
    iemDecodeA64_60e0fc00_0020f000_1,
    iemDecodeA64_60e0fc00_0020f400_1,
    iemDecodeA64_60e0fc00_0020f800_1,
    iemDecodeA64_60e0fc00_0020fc00_1,
    iemDecodeA64_60e0fc00_00400000_1,
    iemDecodeA64_60e0fc00_00400400_1,
    iemDecodeA64_60e0fc00_00400800_1,
    iemDecodeA64_FMLA_asimdsamefp16_only,
    iemDecodeA64_Invalid, // 132
    iemDecodeA64_60e0fc00_00401400_1,
    iemDecodeA64_LDIAPP_32L_ldiappstilp,
    iemDecodeA64_FMULX_asimdsamefp16_only,
    iemDecodeA64_60e0fc00_00402000_1,
    iemDecodeA64_60e0fc00_00402400_1,
    iemDecodeA64_Invalid, // 138
    iemDecodeA64_Invalid, // 139
    iemDecodeA64_Invalid, // 140
    iemDecodeA64_60e0fc00_00403400_1,
    iemDecodeA64_Invalid, // 142
    iemDecodeA64_FRECPS_asimdsamefp16_only,
    iemDecodeA64_60e0fc00_00404000_1,
    iemDecodeA64_60e0fc00_00404400_1,
    iemDecodeA64_Invalid, // 146
    iemDecodeA64_Invalid, // 147
    iemDecodeA64_Invalid, // 148
    iemDecodeA64_60e0fc00_00405400_1,
    iemDecodeA64_Invalid, // 150
    iemDecodeA64_Invalid, // 151
    iemDecodeA64_60e0fc00_00406000_1,
    iemDecodeA64_60e0fc00_00406400_1,
    iemDecodeA64_Invalid, // 154
    iemDecodeA64_Invalid, // 155
    iemDecodeA64_LD1_asisdlse_R1_1v,
    iemDecodeA64_60e0fc00_00407400_1,
    iemDecodeA64_Invalid, // 158
    iemDecodeA64_60e0fc00_00407c00_1,
    iemDecodeA64_60e0fc00_00408000_1,
    iemDecodeA64_60e0fc00_00408400_1,
    iemDecodeA64_Invalid, // 162
    iemDecodeA64_Invalid, // 163
    iemDecodeA64_Invalid, // 164
    iemDecodeA64_60e0fc00_00409400_1,
    iemDecodeA64_Invalid, // 166
    iemDecodeA64_Invalid, // 167
    iemDecodeA64_60e0fc00_0040a000_1,
    iemDecodeA64_60e0fc00_0040a400_1,
    iemDecodeA64_Invalid, // 170
    iemDecodeA64_Invalid, // 171
    iemDecodeA64_Invalid, // 172
    iemDecodeA64_60e0fc00_0040b400_1,
    iemDecodeA64_Invalid, // 174
    iemDecodeA64_Invalid, // 175
    iemDecodeA64_60e0fc00_0040c000_1,
    iemDecodeA64_60e0fc00_0040c400_1,
    iemDecodeA64_Invalid, // 178
    iemDecodeA64_Invalid, // 179
    iemDecodeA64_Invalid, // 180
    iemDecodeA64_60e0fc00_0040d400_1,
    iemDecodeA64_Invalid, // 182
    iemDecodeA64_Invalid, // 183
    iemDecodeA64_60e0fc00_0040e000_1,
    iemDecodeA64_60e0fc00_0040e400_1,
    iemDecodeA64_Invalid, // 186
    iemDecodeA64_Invalid, // 187
    iemDecodeA64_BFDOT_asimdelem_E,
    iemDecodeA64_60e0fc00_0040f400_1,
    iemDecodeA64_Invalid, // 190
    iemDecodeA64_60e0fc00_0040fc00_1,
    iemDecodeA64_60e0fc00_00600000_1,
    iemDecodeA64_60e0fc00_00600400_1,
    iemDecodeA64_60e0fc00_00600800_1,
    iemDecodeA64_60e0fc00_00600c00_1,
    iemDecodeA64_60e0fc00_00601000_1,
    iemDecodeA64_LDTCLRL_32_memop_unpriv,
    iemDecodeA64_FDIV_D_floatdp2,
    iemDecodeA64_BIC_asimdsame_only,
    iemDecodeA64_60e0fc00_00602000_1,
    iemDecodeA64_extq_z_zi_des,
    iemDecodeA64_FADD_D_floatdp2,
    iemDecodeA64_Invalid, // 203
    iemDecodeA64_60e0fc00_00603000_1,
    iemDecodeA64_LDTSETL_32_memop_unpriv,
    iemDecodeA64_60e0fc00_00603800_1,
    iemDecodeA64_bsl1n_z_zzz,
    iemDecodeA64_60e0fc00_00604000_1,
    iemDecodeA64_Invalid, // 209
    iemDecodeA64_FMAX_D_floatdp2,
    iemDecodeA64_Invalid, // 211
    iemDecodeA64_addpl_r_ri,
    iemDecodeA64_Invalid, // 213
    iemDecodeA64_60e0fc00_00605800_1,
    iemDecodeA64_Invalid, // 215
    iemDecodeA64_LD4_asisdlso_H4_4h,
    iemDecodeA64_Invalid, // 217
    iemDecodeA64_FMAXNM_D_floatdp2,
    iemDecodeA64_Invalid, // 219
    iemDecodeA64_Invalid, // 220
    iemDecodeA64_Invalid, // 221
    iemDecodeA64_FMINNM_D_floatdp2,
    iemDecodeA64_CASPA_CP32_comswappr,
    iemDecodeA64_60e0fc00_00608000_1,
    iemDecodeA64_60e0fc00_00608400_1,
    iemDecodeA64_60e0fc00_00608800_1,
    iemDecodeA64_Invalid, // 227
    iemDecodeA64_RCWCLRPL_128_memop_128,
    iemDecodeA64_Invalid, // 229
    iemDecodeA64_FRINTM_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 231
    iemDecodeA64_60e0fc00_0060a000_1,
    iemDecodeA64_LD4_asisdlso_D4_4d,
    iemDecodeA64_FCVTNS_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 235
    iemDecodeA64_RCWSETPL_128_memop_128,
    iemDecodeA64_Invalid, // 237
    iemDecodeA64_FCVTMS_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 239
    iemDecodeA64_60e0fc00_0060c000_1,
    iemDecodeA64_60e0fc00_0060c400_1,
    iemDecodeA64_60e0fc00_0060c800_1,
    iemDecodeA64_uqdech_z_zs,
    iemDecodeA64_Invalid, // 244
    iemDecodeA64_Invalid, // 245
    iemDecodeA64_SCVTF_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 247
    iemDecodeA64_60e0fc00_0060e000_1,
    iemDecodeA64_dech_r_rs,
    iemDecodeA64_Invalid, // 250
    iemDecodeA64_Invalid, // 251
    iemDecodeA64_60e0fc00_0060f000_1,
    iemDecodeA64_60e0fc00_0060f400_1,
    iemDecodeA64_60e0fc00_0060f800_1,
    iemDecodeA64_60e0fc00_0060fc00_1,
    iemDecodeA64_60e0fc00_00800000_1,
    iemDecodeA64_60e0fc00_00800400_1,
    iemDecodeA64_60e0fc00_00800800_1,
    iemDecodeA64_Invalid, // 259
    iemDecodeA64_FMLA_asimdelem_R_SD,
    iemDecodeA64_60e0fc00_00801400_1,
    iemDecodeA64_Invalid, // 262
    iemDecodeA64_Invalid, // 263
    iemDecodeA64_60e0fc00_00802000_1,
    iemDecodeA64_60e0fc00_00802400_1,
    iemDecodeA64_Invalid, // 266
    iemDecodeA64_Invalid, // 267
    iemDecodeA64_Invalid, // 268
    iemDecodeA64_60e0fc00_00803400_1,
    iemDecodeA64_Invalid, // 270
    iemDecodeA64_Invalid, // 271
    iemDecodeA64_60e0fc00_00804000_1,
    iemDecodeA64_60e0fc00_00804400_1,
    iemDecodeA64_Invalid, // 274
    iemDecodeA64_Invalid, // 275
    iemDecodeA64_FMLS_asimdelem_R_SD,
    iemDecodeA64_60e0fc00_00805400_1,
    iemDecodeA64_Invalid, // 278
    iemDecodeA64_Invalid, // 279
    iemDecodeA64_60e0fc00_00806000_1,
    iemDecodeA64_60e0fc00_00806400_1,
    iemDecodeA64_Invalid, // 282
    iemDecodeA64_Invalid, // 283
    iemDecodeA64_60e0fc00_00807000_1,
    iemDecodeA64_60e0fc00_00807400_1,
    iemDecodeA64_Invalid, // 286
    iemDecodeA64_60e0fc00_00807c00_1,
    iemDecodeA64_60e0fc00_00808000_1,
    iemDecodeA64_60e0fc00_00808400_1,
    iemDecodeA64_Invalid, // 290
    iemDecodeA64_Invalid, // 291
    iemDecodeA64_FMUL_asimdelem_R_SD,
    iemDecodeA64_60e0fc00_00809400_1,
    iemDecodeA64_Invalid, // 294
    iemDecodeA64_USDOT_asimdsame2_D,
    iemDecodeA64_60e0fc00_0080a000_1,
    iemDecodeA64_60e0fc00_0080a400_1,
    iemDecodeA64_Invalid, // 298
    iemDecodeA64_Invalid, // 299
    iemDecodeA64_Invalid, // 300
    iemDecodeA64_60e0fc00_0080b400_1,
    iemDecodeA64_Invalid, // 302
    iemDecodeA64_Invalid, // 303
    iemDecodeA64_60e0fc00_0080c000_1,
    iemDecodeA64_60e0fc00_0080c400_1,
    iemDecodeA64_Invalid, // 306
    iemDecodeA64_Invalid, // 307
    iemDecodeA64_Invalid, // 308
    iemDecodeA64_60e0fc00_0080d400_1,
    iemDecodeA64_Invalid, // 310
    iemDecodeA64_Invalid, // 311
    iemDecodeA64_60e0fc00_0080e000_1,
    iemDecodeA64_60e0fc00_0080e400_1,
    iemDecodeA64_Invalid, // 314
    iemDecodeA64_Invalid, // 315
    iemDecodeA64_USDOT_asimdelem_D,
    iemDecodeA64_60e0fc00_0080f400_1,
    iemDecodeA64_Invalid, // 318
    iemDecodeA64_60e0fc00_0080fc00_1,
    iemDecodeA64_60e0fc00_00a00000_1,
    iemDecodeA64_60e0fc00_00a00400_1,
    iemDecodeA64_60e0fc00_00a00800_1,
    iemDecodeA64_60e0fc00_00a00c00_1,
    iemDecodeA64_LDCLRPA_128_memop_128,
    iemDecodeA64_LDTCLRA_32_memop_unpriv,
    iemDecodeA64_trn1_z_zz_q,
    iemDecodeA64_60e0fc00_00a01c00_1,
    iemDecodeA64_60e0fc00_00a02000_1,
    iemDecodeA64_Invalid, // 329
    iemDecodeA64_Invalid, // 330
    iemDecodeA64_Invalid, // 331
    iemDecodeA64_60e0fc00_00a03000_1,
    iemDecodeA64_LDTSETA_32_memop_unpriv,
    iemDecodeA64_60e0fc00_00a03800_1,
    iemDecodeA64_bsl2n_z_zzz,
    iemDecodeA64_60e0fc00_00a04000_1,
    iemDecodeA64_Invalid, // 337
    iemDecodeA64_Invalid, // 338
    iemDecodeA64_Invalid, // 339
    iemDecodeA64_rdvl_r_i,
    iemDecodeA64_Invalid, // 341
    iemDecodeA64_rdsvl_r_i,
    iemDecodeA64_Invalid, // 343
    iemDecodeA64_60e0fc00_00a06000_1,
    iemDecodeA64_Invalid, // 345
    iemDecodeA64_BFCVTN_asimdmisc_4S,
    iemDecodeA64_Invalid, // 347
    iemDecodeA64_Invalid, // 348
    iemDecodeA64_Invalid, // 349
    iemDecodeA64_Invalid, // 350
    iemDecodeA64_60e0fc00_00a07c00_1,
    iemDecodeA64_60e0fc00_00a08000_1,
    iemDecodeA64_60e0fc00_00a08400_1,
    iemDecodeA64_FRINTP_asimdmisc_R,
    iemDecodeA64_Invalid, // 355
    iemDecodeA64_RCWCLRPA_128_memop_128,
    iemDecodeA64_Invalid, // 357
    iemDecodeA64_FRINTZ_asimdmisc_R,
    iemDecodeA64_Invalid, // 359
    iemDecodeA64_60e0fc00_00a0a000_1,
    iemDecodeA64_60e0fc00_00a0a400_1,
    iemDecodeA64_FCVTPS_asimdmisc_R,
    iemDecodeA64_Invalid, // 363
    iemDecodeA64_RCWSETPA_128_memop_128,
    iemDecodeA64_Invalid, // 365
    iemDecodeA64_FCVTZS_asimdmisc_R,
    iemDecodeA64_Invalid, // 367
    iemDecodeA64_60e0fc00_00a0c000_1,
    iemDecodeA64_60e0fc00_00a0c400_1,
    iemDecodeA64_60e0fc00_00a0c800_1,
    iemDecodeA64_60e0fc00_00a0cc00_1,
    iemDecodeA64_Invalid, // 372
    iemDecodeA64_FSUB_asimdsame_only,
    iemDecodeA64_60e0fc00_00a0d800_1,
    iemDecodeA64_Invalid, // 375
    iemDecodeA64_60e0fc00_00a0e000_1,
    iemDecodeA64_decw_r_rs,
    iemDecodeA64_FCMLT_asimdmisc_FZ,
    iemDecodeA64_FMLSL_asimdsame_F,
    iemDecodeA64_60e0fc00_00a0f000_1,
    iemDecodeA64_60e0fc00_00a0f400_1,
    iemDecodeA64_60e0fc00_00a0f800_1,
    iemDecodeA64_60e0fc00_00a0fc00_1,
    iemDecodeA64_60e0fc00_00c00000_1,
    iemDecodeA64_60e0fc00_00c00400_1,
    iemDecodeA64_60e0fc00_00c00800_1,
    iemDecodeA64_60e0fc00_00c00c00_1,
    iemDecodeA64_IRG_64I_dp_2src,
    iemDecodeA64_60e0fc00_00c01400_1,
    iemDecodeA64_Invalid, // 390
    iemDecodeA64_FAMAX_asimdsamefp16_only,
    iemDecodeA64_60e0fc00_00c02000_1,
    iemDecodeA64_60e0fc00_00c02400_1,
    iemDecodeA64_60e0fc00_00c02800_1,
    iemDecodeA64_60e0fc00_00c02c00_1,
    iemDecodeA64_PACGA_64P_dp_2src,
    iemDecodeA64_60e0fc00_00c03400_1,
    iemDecodeA64_Invalid, // 398
    iemDecodeA64_FRSQRTS_asimdsamefp16_only,
    iemDecodeA64_60e0fc00_00c04000_1,
    iemDecodeA64_60e0fc00_00c04400_1,
    iemDecodeA64_CRC32W_32C_dp_2src,
    iemDecodeA64_CRC32X_64C_dp_2src,
    iemDecodeA64_CRC32CB_32C_dp_2src,
    iemDecodeA64_60e0fc00_00c05400_1,
    iemDecodeA64_CRC32CW_32C_dp_2src,
    iemDecodeA64_CRC32CX_64C_dp_2src,
    iemDecodeA64_60e0fc00_00c06000_1,
    iemDecodeA64_60e0fc00_00c06400_1,
    iemDecodeA64_60e0fc00_00c06800_1,
    iemDecodeA64_60e0fc00_00c06c00_1,
    iemDecodeA64_60e0fc00_00c07000_1,
    iemDecodeA64_60e0fc00_00c07400_1,
    iemDecodeA64_Invalid, // 414
    iemDecodeA64_60e0fc00_00c07c00_1,
    iemDecodeA64_60e0fc00_00c08000_1,
    iemDecodeA64_60e0fc00_00c08400_1,
    iemDecodeA64_Invalid, // 418
    iemDecodeA64_Invalid, // 419
    iemDecodeA64_Invalid, // 420
    iemDecodeA64_60e0fc00_00c09400_1,
    iemDecodeA64_Invalid, // 422
    iemDecodeA64_Invalid, // 423
    iemDecodeA64_60e0fc00_00c0a000_1,
    iemDecodeA64_60e0fc00_00c0a400_1,
    iemDecodeA64_Invalid, // 426
    iemDecodeA64_Invalid, // 427
    iemDecodeA64_Invalid, // 428
    iemDecodeA64_60e0fc00_00c0b400_1,
    iemDecodeA64_Invalid, // 430
    iemDecodeA64_Invalid, // 431
    iemDecodeA64_60e0fc00_00c0c000_1,
    iemDecodeA64_Invalid, // 433
    iemDecodeA64_Invalid, // 434
    iemDecodeA64_Invalid, // 435
    iemDecodeA64_Invalid, // 436
    iemDecodeA64_Invalid, // 437
    iemDecodeA64_Invalid, // 438
    iemDecodeA64_Invalid, // 439
    iemDecodeA64_60e0fc00_00c0e000_1,
    iemDecodeA64_Invalid, // 441
    iemDecodeA64_Invalid, // 442
    iemDecodeA64_Invalid, // 443
    iemDecodeA64_BFMLAL_asimdelem_F,
    iemDecodeA64_Invalid, // 445
    iemDecodeA64_Invalid, // 446
    iemDecodeA64_60e0fc00_00c0fc00_1,
    iemDecodeA64_60e0fc00_00e00000_1,
    iemDecodeA64_60e0fc00_00e00400_1,
    iemDecodeA64_60e0fc00_00e00800_1,
    iemDecodeA64_60e0fc00_00e00c00_1,
    iemDecodeA64_60e0fc00_00e01000_1,
    iemDecodeA64_LDTCLRAL_32_memop_unpriv,
    iemDecodeA64_FDIV_H_floatdp2,
    iemDecodeA64_ORN_asimdsame_only,
    iemDecodeA64_60e0fc00_00e02000_1,
    iemDecodeA64_Invalid, // 457
    iemDecodeA64_FADD_H_floatdp2,
    iemDecodeA64_Invalid, // 459
    iemDecodeA64_60e0fc00_00e03000_1,
    iemDecodeA64_LDTSETAL_32_memop_unpriv,
    iemDecodeA64_FSUB_H_floatdp2,
    iemDecodeA64_nbsl_z_zzz,
    iemDecodeA64_60e0fc00_00e04000_1,
    iemDecodeA64_Invalid, // 465
    iemDecodeA64_FMAX_H_floatdp2,
    iemDecodeA64_Invalid, // 467
    iemDecodeA64_Invalid, // 468
    iemDecodeA64_Invalid, // 469
    iemDecodeA64_FMIN_H_floatdp2,
    iemDecodeA64_Invalid, // 471
    iemDecodeA64_60e0fc00_00e06000_1,
    iemDecodeA64_Invalid, // 473
    iemDecodeA64_FMAXNM_H_floatdp2,
    iemDecodeA64_Invalid, // 475
    iemDecodeA64_Invalid, // 476
    iemDecodeA64_Invalid, // 477
    iemDecodeA64_FMINNM_H_floatdp2,
    iemDecodeA64_60e0fc00_00e07c00_1,
    iemDecodeA64_60e0fc00_00e08000_1,
    iemDecodeA64_60e0fc00_00e08400_1,
    iemDecodeA64_60e0fc00_00e08800_1,
    iemDecodeA64_Invalid, // 483
    iemDecodeA64_RCWCLRPAL_128_memop_128,
    iemDecodeA64_Invalid, // 485
    iemDecodeA64_FRINTZ_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 487
    iemDecodeA64_60e0fc00_00e0a000_1,
    iemDecodeA64_60e0fc00_00e0a400_1,
    iemDecodeA64_FCVTPS_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 491
    iemDecodeA64_RCWSETPAL_128_memop_128,
    iemDecodeA64_Invalid, // 493
    iemDecodeA64_FCVTZS_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 495
    iemDecodeA64_60e0fc00_00e0c000_1,
    iemDecodeA64_60e0fc00_00e0c400_1,
    iemDecodeA64_60e0fc00_00e0c800_1,
    iemDecodeA64_uqdecd_z_zs,
    iemDecodeA64_Invalid, // 500
    iemDecodeA64_Invalid, // 501
    iemDecodeA64_60e0fc00_00e0d800_1,
    iemDecodeA64_Invalid, // 503
    iemDecodeA64_60e0fc00_00e0e000_1,
    iemDecodeA64_decd_r_rs,
    iemDecodeA64_FCMLT_asimdmiscfp16_FZ,
    iemDecodeA64_Invalid, // 507
    iemDecodeA64_60e0fc00_00e0f000_1,
    iemDecodeA64_60e0fc00_00e0f400_1,
    iemDecodeA64_60e0fc00_00e0f800_1,
    iemDecodeA64_60e0fc00_00e0fc00_1,
    iemDecodeA64_60e0fc00_20000000_1,
    iemDecodeA64_60e0fc00_20000400_1,
    iemDecodeA64_60e0fc00_20000800_1,
    iemDecodeA64_60e0fc00_20000c00_1,
    iemDecodeA64_FCMLA_advsimd_elt,
    iemDecodeA64_60e0fc00_20001400_1,
    iemDecodeA64_Invalid, // 518
    iemDecodeA64_Invalid, // 519
    iemDecodeA64_60e0fc00_20002000_1,
    iemDecodeA64_URSHR_asimdshf_R,
    iemDecodeA64_Invalid, // 522
    iemDecodeA64_Invalid, // 523
    iemDecodeA64_Invalid, // 524
    iemDecodeA64_URSRA_asimdshf_R,
    iemDecodeA64_Invalid, // 526
    iemDecodeA64_Invalid, // 527
    iemDecodeA64_60e0fc00_20004000_1,
    iemDecodeA64_SRI_asimdshf_R,
    iemDecodeA64_SETF16_only_setf,
    iemDecodeA64_Invalid, // 531
    iemDecodeA64_Invalid, // 532
    iemDecodeA64_SLI_asimdshf_R,
    iemDecodeA64_Invalid, // 534
    iemDecodeA64_Invalid, // 535
    iemDecodeA64_60e0fc00_20006000_1,
    iemDecodeA64_SQSHLU_asimdshf_R,
    iemDecodeA64_Invalid, // 538
    iemDecodeA64_Invalid, // 539
    iemDecodeA64_Invalid, // 540
    iemDecodeA64_UQSHL_asimdshf_R,
    iemDecodeA64_Invalid, // 542
    iemDecodeA64_Invalid, // 543
    iemDecodeA64_60e0fc00_20008000_1,
    iemDecodeA64_60e0fc00_20008400_1,
    iemDecodeA64_Invalid, // 546
    iemDecodeA64_60e0fc00_20008c00_1,
    iemDecodeA64_FMULX_asimdelem_RH_H,
    iemDecodeA64_60e0fc00_20009400_1,
    iemDecodeA64_Invalid, // 550
    iemDecodeA64_UQRSHRN_asimdshf_N,
    iemDecodeA64_60e0fc00_2000a000_1,
    iemDecodeA64_USHLL_asimdshf_L,
    iemDecodeA64_Invalid, // 554
    iemDecodeA64_Invalid, // 555
    iemDecodeA64_Invalid, // 556
    iemDecodeA64_Invalid, // 557
    iemDecodeA64_Invalid, // 558
    iemDecodeA64_Invalid, // 559
    iemDecodeA64_60e0fc00_2000c000_1,
    iemDecodeA64_60e0fc00_2000c400_1,
    iemDecodeA64_Invalid, // 562
    iemDecodeA64_Invalid, // 563
    iemDecodeA64_SQRDMLAH_asimdelem_R,
    iemDecodeA64_Invalid, // 565
    iemDecodeA64_Invalid, // 566
    iemDecodeA64_Invalid, // 567
    iemDecodeA64_60e0fc00_2000e000_1,
    iemDecodeA64_60e0fc00_2000e400_1,
    iemDecodeA64_Invalid, // 570
    iemDecodeA64_Invalid, // 571
    iemDecodeA64_60e0fc00_2000f000_1,
    iemDecodeA64_Invalid, // 573
    iemDecodeA64_Invalid, // 574
    iemDecodeA64_FCVTZU_asimdshf_C,
    iemDecodeA64_60e0fc00_20200000_1,
    iemDecodeA64_60e0fc00_20200400_1,
    iemDecodeA64_60e0fc00_20200800_1,
    iemDecodeA64_60e0fc00_20200c00_1,
    iemDecodeA64_60e0fc00_20201000_1,
    iemDecodeA64_URHADD_asimdsame_only,
    iemDecodeA64_Invalid, // 582
    iemDecodeA64_EOR_asimdsame_only,
    iemDecodeA64_60e0fc00_20202000_1,
    iemDecodeA64_UHSUB_asimdsame_only,
    iemDecodeA64_60e0fc00_20202800_1,
    iemDecodeA64_UQSUB_asimdsame_only,
    iemDecodeA64_60e0fc00_20203000_1,
    iemDecodeA64_CMHI_asimdsame_only,
    iemDecodeA64_60e0fc00_20203800_1,
    iemDecodeA64_CMHS_asimdsame_only,
    iemDecodeA64_60e0fc00_20204000_1,
    iemDecodeA64_60e0fc00_20204400_1,
    iemDecodeA64_60e0fc00_20204800_1,
    iemDecodeA64_60e0fc00_20204c00_1,
    iemDecodeA64_60e0fc00_20205000_1,
    iemDecodeA64_60e0fc00_20205400_1,
    iemDecodeA64_60e0fc00_20205800_1,
    iemDecodeA64_60e0fc00_20205c00_1,
    iemDecodeA64_60e0fc00_20206000_1,
    iemDecodeA64_UMAX_asimdsame_only,
    iemDecodeA64_60e0fc00_20206800_1,
    iemDecodeA64_UMIN_asimdsame_only,
    iemDecodeA64_60e0fc00_20207000_1,
    iemDecodeA64_60e0fc00_20207400_1,
    iemDecodeA64_60e0fc00_20207800_1,
    iemDecodeA64_UABA_asimdsame_only,
    iemDecodeA64_60e0fc00_20208000_1,
    iemDecodeA64_SUB_asimdsame_only,
    iemDecodeA64_60e0fc00_20208800_1,
    iemDecodeA64_60e0fc00_20208c00_1,
    iemDecodeA64_60e0fc00_20209000_1,
    iemDecodeA64_MLS_asimdsame_only,
    iemDecodeA64_60e0fc00_20209800_1,
    iemDecodeA64_PMUL_asimdsame_only,
    iemDecodeA64_60e0fc00_2020a000_1,
    iemDecodeA64_UMAXP_asimdsame_only,
    iemDecodeA64_60e0fc00_2020a800_1,
    iemDecodeA64_UMINP_asimdsame_only,
    iemDecodeA64_RCWSET_64_memop,
    iemDecodeA64_SQRDMULH_asimdsame_only,
    iemDecodeA64_60e0fc00_2020b800_1,
    iemDecodeA64_Invalid, // 623
    iemDecodeA64_60e0fc00_2020c000_1,
    iemDecodeA64_FMAXNMP_asimdsame_only,
    iemDecodeA64_FCVTAU_asimdmisc_R,
    iemDecodeA64_FMLAL2_asimdsame_F,
    iemDecodeA64_60e0fc00_2020d000_1,
    iemDecodeA64_FADDP_asimdsame_only,
    iemDecodeA64_UCVTF_asimdmisc_R,
    iemDecodeA64_60e0fc00_2020dc00_1,
    iemDecodeA64_60e0fc00_2020e000_1,
    iemDecodeA64_FCMGE_asimdsame_only,
    iemDecodeA64_FRINT32X_asimdmisc_R,
    iemDecodeA64_FACGE_asimdsame_only,
    iemDecodeA64_60e0fc00_2020f000_1,
    iemDecodeA64_FMAXP_asimdsame_only,
    iemDecodeA64_FRINT64X_asimdmisc_R,
    iemDecodeA64_60e0fc00_2020fc00_1,
    iemDecodeA64_60e0fc00_20400000_1,
    iemDecodeA64_60e0fc00_20400400_1,
    iemDecodeA64_60e0fc00_20400800_1,
    iemDecodeA64_60e0fc00_20400c00_1,
    iemDecodeA64_Invalid, // 644
    iemDecodeA64_FADDP_asimdsamefp16_only,
    iemDecodeA64_Invalid, // 646
    iemDecodeA64_FMUL_asimdsamefp16_only,
    iemDecodeA64_60e0fc00_20402000_1,
    iemDecodeA64_FCMGE_asimdsamefp16_only,
    iemDecodeA64_Invalid, // 650
    iemDecodeA64_FACGE_asimdsamefp16_only,
    iemDecodeA64_Invalid, // 652
    iemDecodeA64_FMAXP_asimdsamefp16_only,
    iemDecodeA64_Invalid, // 654
    iemDecodeA64_FDIV_asimdsamefp16_only,
    iemDecodeA64_60e0fc00_20404000_1,
    iemDecodeA64_Invalid, // 657
    iemDecodeA64_Invalid, // 658
    iemDecodeA64_Invalid, // 659
    iemDecodeA64_Invalid, // 660
    iemDecodeA64_Invalid, // 661
    iemDecodeA64_Invalid, // 662
    iemDecodeA64_Invalid, // 663
    iemDecodeA64_60e0fc00_20406000_1,
    iemDecodeA64_Invalid, // 665
    iemDecodeA64_Invalid, // 666
    iemDecodeA64_Invalid, // 667
    iemDecodeA64_Invalid, // 668
    iemDecodeA64_Invalid, // 669
    iemDecodeA64_Invalid, // 670
    iemDecodeA64_Invalid, // 671
    iemDecodeA64_60e0fc00_20408000_1,
    iemDecodeA64_Invalid, // 673
    iemDecodeA64_Invalid, // 674
    iemDecodeA64_Invalid, // 675
    iemDecodeA64_Invalid, // 676
    iemDecodeA64_Invalid, // 677
    iemDecodeA64_Invalid, // 678
    iemDecodeA64_Invalid, // 679
    iemDecodeA64_60e0fc00_2040a000_1,
    iemDecodeA64_Invalid, // 681
    iemDecodeA64_Invalid, // 682
    iemDecodeA64_Invalid, // 683
    iemDecodeA64_Invalid, // 684
    iemDecodeA64_Invalid, // 685
    iemDecodeA64_Invalid, // 686
    iemDecodeA64_Invalid, // 687
    iemDecodeA64_60e0fc00_2040c000_1,
    iemDecodeA64_Invalid, // 689
    iemDecodeA64_Invalid, // 690
    iemDecodeA64_Invalid, // 691
    iemDecodeA64_Invalid, // 692
    iemDecodeA64_Invalid, // 693
    iemDecodeA64_Invalid, // 694
    iemDecodeA64_Invalid, // 695
    iemDecodeA64_60e0fc00_2040e000_1,
    iemDecodeA64_Invalid, // 697
    iemDecodeA64_Invalid, // 698
    iemDecodeA64_Invalid, // 699
    iemDecodeA64_rdffrs_p_p_f,
    iemDecodeA64_Invalid, // 701
    iemDecodeA64_Invalid, // 702
    iemDecodeA64_BFDOT_asimdsame2_D,
    iemDecodeA64_60e0fc00_20600000_1,
    iemDecodeA64_Invalid, // 705
    iemDecodeA64_60e0fc00_20600800_1,
    iemDecodeA64_Invalid, // 707
    iemDecodeA64_60e0fc00_20601000_1,
    iemDecodeA64_Invalid, // 709
    iemDecodeA64_Invalid, // 710
    iemDecodeA64_BSL_asimdsame_only,
    iemDecodeA64_60e0fc00_20602000_1,
    iemDecodeA64_Invalid, // 713
    iemDecodeA64_Invalid, // 714
    iemDecodeA64_Invalid, // 715
    iemDecodeA64_60e0fc00_20603000_1,
    iemDecodeA64_Invalid, // 717
    iemDecodeA64_Invalid, // 718
    iemDecodeA64_Invalid, // 719
    iemDecodeA64_60e0fc00_20604000_1,
    iemDecodeA64_Invalid, // 721
    iemDecodeA64_Invalid, // 722
    iemDecodeA64_Invalid, // 723
    iemDecodeA64_60e0fc00_20605000_1,
    iemDecodeA64_Invalid, // 725
    iemDecodeA64_RBIT_asimdmisc_R,
    iemDecodeA64_Invalid, // 727
    iemDecodeA64_60e0fc00_20606000_1,
    iemDecodeA64_Invalid, // 729
    iemDecodeA64_60e0fc00_20606800_1,
    iemDecodeA64_Invalid, // 731
    iemDecodeA64_60e0fc00_20607000_1,
    iemDecodeA64_Invalid, // 733
    iemDecodeA64_F2CVTL_asimdmisc_V,
    iemDecodeA64_Invalid, // 735
    iemDecodeA64_60e0fc00_20608000_1,
    iemDecodeA64_Invalid, // 737
    iemDecodeA64_FRINTA_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 739
    iemDecodeA64_RCWCLRL_64_memop,
    iemDecodeA64_Invalid, // 741
    iemDecodeA64_FRINTX_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 743
    iemDecodeA64_60e0fc00_2060a000_1,
    iemDecodeA64_Invalid, // 745
    iemDecodeA64_FCVTNU_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 747
    iemDecodeA64_RCWSETL_64_memop,
    iemDecodeA64_Invalid, // 749
    iemDecodeA64_FCVTMU_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 751
    iemDecodeA64_60e0fc00_2060c000_1,
    iemDecodeA64_Invalid, // 753
    iemDecodeA64_FCVTAU_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 755
    iemDecodeA64_60e0fc00_2060d000_1,
    iemDecodeA64_Invalid, // 757
    iemDecodeA64_UCVTF_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 759
    iemDecodeA64_60e0fc00_2060e000_1,
    iemDecodeA64_Invalid, // 761
    iemDecodeA64_Invalid, // 762
    iemDecodeA64_Invalid, // 763
    iemDecodeA64_60e0fc00_2060f000_1,
    iemDecodeA64_Invalid, // 765
    iemDecodeA64_Invalid, // 766
    iemDecodeA64_Invalid, // 767
    iemDecodeA64_60e0fc00_20800000_1,
    iemDecodeA64_60e0fc00_20800400_1,
    iemDecodeA64_60e0fc00_20800800_1,
    iemDecodeA64_60e0fc00_20800c00_1,
    iemDecodeA64_Invalid, // 772
    iemDecodeA64_Invalid, // 773
    iemDecodeA64_Invalid, // 774
    iemDecodeA64_Invalid, // 775
    iemDecodeA64_60e0fc00_20802000_1,
    iemDecodeA64_Invalid, // 777
    iemDecodeA64_Invalid, // 778
    iemDecodeA64_Invalid, // 779
    iemDecodeA64_Invalid, // 780
    iemDecodeA64_Invalid, // 781
    iemDecodeA64_Invalid, // 782
    iemDecodeA64_Invalid, // 783
    iemDecodeA64_60e0fc00_20804000_1,
    iemDecodeA64_Invalid, // 785
    iemDecodeA64_Invalid, // 786
    iemDecodeA64_Invalid, // 787
    iemDecodeA64_Invalid, // 788
    iemDecodeA64_Invalid, // 789
    iemDecodeA64_Invalid, // 790
    iemDecodeA64_Invalid, // 791
    iemDecodeA64_60e0fc00_20806000_1,
    iemDecodeA64_Invalid, // 793
    iemDecodeA64_Invalid, // 794
    iemDecodeA64_Invalid, // 795
    iemDecodeA64_Invalid, // 796
    iemDecodeA64_Invalid, // 797
    iemDecodeA64_Invalid, // 798
    iemDecodeA64_Invalid, // 799
    iemDecodeA64_60e0fc00_20808000_1,
    iemDecodeA64_Invalid, // 801
    iemDecodeA64_Invalid, // 802
    iemDecodeA64_Invalid, // 803
    iemDecodeA64_FMULX_asimdelem_R_SD,
    iemDecodeA64_Invalid, // 805
    iemDecodeA64_Invalid, // 806
    iemDecodeA64_Invalid, // 807
    iemDecodeA64_60e0fc00_2080a000_1,
    iemDecodeA64_Invalid, // 809
    iemDecodeA64_Invalid, // 810
    iemDecodeA64_Invalid, // 811
    iemDecodeA64_Invalid, // 812
    iemDecodeA64_Invalid, // 813
    iemDecodeA64_Invalid, // 814
    iemDecodeA64_Invalid, // 815
    iemDecodeA64_60e0fc00_2080c000_1,
    iemDecodeA64_Invalid, // 817
    iemDecodeA64_Invalid, // 818
    iemDecodeA64_Invalid, // 819
    iemDecodeA64_Invalid, // 820
    iemDecodeA64_Invalid, // 821
    iemDecodeA64_Invalid, // 822
    iemDecodeA64_Invalid, // 823
    iemDecodeA64_60e0fc00_2080e000_1,
    iemDecodeA64_Invalid, // 825
    iemDecodeA64_Invalid, // 826
    iemDecodeA64_Invalid, // 827
    iemDecodeA64_Invalid, // 828
    iemDecodeA64_Invalid, // 829
    iemDecodeA64_Invalid, // 830
    iemDecodeA64_Invalid, // 831
    iemDecodeA64_60e0fc00_20a00000_1,
    iemDecodeA64_Invalid, // 833
    iemDecodeA64_60e0fc00_20a00800_1,
    iemDecodeA64_Invalid, // 835
    iemDecodeA64_60e0fc00_20a01000_1,
    iemDecodeA64_Invalid, // 837
    iemDecodeA64_Invalid, // 838
    iemDecodeA64_BIT_asimdsame_only,
    iemDecodeA64_60e0fc00_20a02000_1,
    iemDecodeA64_Invalid, // 841
    iemDecodeA64_Invalid, // 842
    iemDecodeA64_Invalid, // 843
    iemDecodeA64_60e0fc00_20a03000_1,
    iemDecodeA64_Invalid, // 845
    iemDecodeA64_Invalid, // 846
    iemDecodeA64_Invalid, // 847
    iemDecodeA64_60e0fc00_20a04000_1,
    iemDecodeA64_Invalid, // 849
    iemDecodeA64_Invalid, // 850
    iemDecodeA64_Invalid, // 851
    iemDecodeA64_60e0fc00_20a05000_1,
    iemDecodeA64_Invalid, // 853
    iemDecodeA64_Invalid, // 854
    iemDecodeA64_Invalid, // 855
    iemDecodeA64_60e0fc00_20a06000_1,
    iemDecodeA64_Invalid, // 857
    iemDecodeA64_LDRSB_64BL_ldst_regoff,
    iemDecodeA64_Invalid, // 859
    iemDecodeA64_60e0fc00_20a07000_1,
    iemDecodeA64_Invalid, // 861
    iemDecodeA64_BF1CVTL_asimdmisc_V,
    iemDecodeA64_Invalid, // 863
    iemDecodeA64_60e0fc00_20a08000_1,
    iemDecodeA64_Invalid, // 865
    iemDecodeA64_Invalid, // 866
    iemDecodeA64_Invalid, // 867
    iemDecodeA64_RCWCLRA_64_memop,
    iemDecodeA64_Invalid, // 869
    iemDecodeA64_FRINTI_asimdmisc_R,
    iemDecodeA64_Invalid, // 871
    iemDecodeA64_60e0fc00_20a0a000_1,
    iemDecodeA64_Invalid, // 873
    iemDecodeA64_FCVTPU_asimdmisc_R,
    iemDecodeA64_Invalid, // 875
    iemDecodeA64_RCWSETA_64_memop,
    iemDecodeA64_Invalid, // 877
    iemDecodeA64_FCVTZU_asimdmisc_R,
    iemDecodeA64_Invalid, // 879
    iemDecodeA64_60e0fc00_20a0c000_1,
    iemDecodeA64_FMINNMP_asimdsame_only,
    iemDecodeA64_60e0fc00_20a0c800_1,
    iemDecodeA64_FMLSL2_asimdsame_F,
    iemDecodeA64_Invalid, // 884
    iemDecodeA64_FABD_asimdsame_only,
    iemDecodeA64_60e0fc00_20a0d800_1,
    iemDecodeA64_Invalid, // 887
    iemDecodeA64_60e0fc00_20a0e000_1,
    iemDecodeA64_FCMGT_asimdsame_only,
    iemDecodeA64_Invalid, // 890
    iemDecodeA64_FACGT_asimdsame_only,
    iemDecodeA64_Invalid, // 892
    iemDecodeA64_FMINP_asimdsame_only,
    iemDecodeA64_60e0fc00_20a0f800_1,
    iemDecodeA64_Invalid, // 895
    iemDecodeA64_60e0fc00_20c00000_1,
    iemDecodeA64_60e0fc00_20c00400_1,
    iemDecodeA64_LDTRSB_32_ldst_unpriv,
    iemDecodeA64_60e0fc00_20c00c00_1,
    iemDecodeA64_Invalid, // 900
    iemDecodeA64_FABD_asimdsamefp16_only,
    iemDecodeA64_Invalid, // 902
    iemDecodeA64_FAMIN_asimdsamefp16_only,
    iemDecodeA64_Invalid, // 904
    iemDecodeA64_FCMGT_asimdsamefp16_only,
    iemDecodeA64_Invalid, // 906
    iemDecodeA64_FACGT_asimdsamefp16_only,
    iemDecodeA64_Invalid, // 908
    iemDecodeA64_FMINP_asimdsamefp16_only,
    iemDecodeA64_Invalid, // 910
    iemDecodeA64_FSCALE_asimdsamefp16_only,
    iemDecodeA64_60e0fc00_20c04000_1,
    iemDecodeA64_Invalid, // 913
    iemDecodeA64_Invalid, // 914
    iemDecodeA64_Invalid, // 915
    iemDecodeA64_Invalid, // 916
    iemDecodeA64_Invalid, // 917
    iemDecodeA64_Invalid, // 918
    iemDecodeA64_Invalid, // 919
    iemDecodeA64_60e0fc00_20c06000_1,
    iemDecodeA64_Invalid, // 921
    iemDecodeA64_Invalid, // 922
    iemDecodeA64_Invalid, // 923
    iemDecodeA64_Invalid, // 924
    iemDecodeA64_Invalid, // 925
    iemDecodeA64_Invalid, // 926
    iemDecodeA64_Invalid, // 927
    iemDecodeA64_Invalid, // 928
    iemDecodeA64_Invalid, // 929
    iemDecodeA64_Invalid, // 930
    iemDecodeA64_Invalid, // 931
    iemDecodeA64_Invalid, // 932
    iemDecodeA64_Invalid, // 933
    iemDecodeA64_Invalid, // 934
    iemDecodeA64_Invalid, // 935
    iemDecodeA64_60e0fc00_20c0a000_1,
    iemDecodeA64_Invalid, // 937
    iemDecodeA64_Invalid, // 938
    iemDecodeA64_Invalid, // 939
    iemDecodeA64_Invalid, // 940
    iemDecodeA64_Invalid, // 941
    iemDecodeA64_Invalid, // 942
    iemDecodeA64_Invalid, // 943
    iemDecodeA64_60e0fc00_20c0c000_1,
    iemDecodeA64_Invalid, // 945
    iemDecodeA64_Invalid, // 946
    iemDecodeA64_Invalid, // 947
    iemDecodeA64_Invalid, // 948
    iemDecodeA64_Invalid, // 949
    iemDecodeA64_Invalid, // 950
    iemDecodeA64_Invalid, // 951
    iemDecodeA64_60e0fc00_20c0e000_1,
    iemDecodeA64_Invalid, // 953
    iemDecodeA64_Invalid, // 954
    iemDecodeA64_Invalid, // 955
    iemDecodeA64_Invalid, // 956
    iemDecodeA64_Invalid, // 957
    iemDecodeA64_Invalid, // 958
    iemDecodeA64_BFMLAL_asimdsame2_F,
    iemDecodeA64_60e0fc00_20e00000_1,
    iemDecodeA64_Invalid, // 961
    iemDecodeA64_60e0fc00_20e00800_1,
    iemDecodeA64_Invalid, // 963
    iemDecodeA64_60e0fc00_20e01000_1,
    iemDecodeA64_Invalid, // 965
    iemDecodeA64_Invalid, // 966
    iemDecodeA64_BIF_asimdsame_only,
    iemDecodeA64_60e0fc00_20e02000_1,
    iemDecodeA64_Invalid, // 969
    iemDecodeA64_Invalid, // 970
    iemDecodeA64_Invalid, // 971
    iemDecodeA64_60e0fc00_20e03000_1,
    iemDecodeA64_Invalid, // 973
    iemDecodeA64_Invalid, // 974
    iemDecodeA64_Invalid, // 975
    iemDecodeA64_60e0fc00_20e04000_1,
    iemDecodeA64_Invalid, // 977
    iemDecodeA64_Invalid, // 978
    iemDecodeA64_Invalid, // 979
    iemDecodeA64_60e0fc00_20e05000_1,
    iemDecodeA64_Invalid, // 981
    iemDecodeA64_Invalid, // 982
    iemDecodeA64_Invalid, // 983
    iemDecodeA64_60e0fc00_20e06000_1,
    iemDecodeA64_Invalid, // 985
    iemDecodeA64_LDRSB_32BL_ldst_regoff,
    iemDecodeA64_Invalid, // 987
    iemDecodeA64_60e0fc00_20e07000_1,
    iemDecodeA64_Invalid, // 989
    iemDecodeA64_BF2CVTL_asimdmisc_V,
    iemDecodeA64_Invalid, // 991
    iemDecodeA64_60e0fc00_20e08000_1,
    iemDecodeA64_Invalid, // 993
    iemDecodeA64_Invalid, // 994
    iemDecodeA64_Invalid, // 995
    iemDecodeA64_RCWCLRAL_64_memop,
    iemDecodeA64_Invalid, // 997
    iemDecodeA64_FRINTI_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 999
    iemDecodeA64_60e0fc00_20e0a000_1,
    iemDecodeA64_Invalid, // 1001
    iemDecodeA64_FCVTPU_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 1003
    iemDecodeA64_RCWSETAL_64_memop,
    iemDecodeA64_Invalid, // 1005
    iemDecodeA64_FCVTZU_asimdmiscfp16_R,
    iemDecodeA64_Invalid, // 1007
    iemDecodeA64_60e0fc00_20e0c000_1,
    iemDecodeA64_Invalid, // 1009
    iemDecodeA64_FCMGE_asimdmiscfp16_FZ,
    iemDecodeA64_Invalid, // 1011
    iemDecodeA64_Invalid, // 1012
    iemDecodeA64_Invalid, // 1013
    iemDecodeA64_60e0fc00_20e0d800_1,
    iemDecodeA64_Invalid, // 1015
    iemDecodeA64_60e0fc00_20e0e000_1,
    iemDecodeA64_Invalid, // 1017
    iemDecodeA64_Invalid, // 1018
    iemDecodeA64_Invalid, // 1019
    iemDecodeA64_Invalid, // 1020
    iemDecodeA64_Invalid, // 1021
    iemDecodeA64_60e0fc00_20e0f800_1,
    iemDecodeA64_Invalid, // 1023
    iemDecodeA64_60e0fc00_40000000_1,
    iemDecodeA64_60e0fc00_40000400_1,
    iemDecodeA64_60e0fc00_40000800_1,
    iemDecodeA64_60e0fc00_40000c00_1,
    iemDecodeA64_60e0fc00_40001000_1,
    iemDecodeA64_60e0fc00_40001400_1,
    iemDecodeA64_60e0fc00_40001800_1,
    iemDecodeA64_60e0fc00_40001c00_1,
    iemDecodeA64_60e0fc00_40002000_1,
    iemDecodeA64_60e0fc00_40002400_1,
    iemDecodeA64_Invalid, // 1034
    iemDecodeA64_SMOV_asimdins_X_x,
    iemDecodeA64_60e0fc00_40003000_1,
    iemDecodeA64_60e0fc00_40003400_1,
    iemDecodeA64_uabdlb_z_zz,
    iemDecodeA64_60e0fc00_40003c00_1,
    iemDecodeA64_60e0fc00_40004000_1,
    iemDecodeA64_60e0fc00_40004400_1,
    iemDecodeA64_60e0fc00_40004800_1,
    iemDecodeA64_60e0fc00_40004c00_1,
    iemDecodeA64_60e0fc00_40005000_1,
    iemDecodeA64_60e0fc00_40005400_1,
    iemDecodeA64_60e0fc00_40005800_1,
    iemDecodeA64_60e0fc00_40005c00_1,
    iemDecodeA64_60e0fc00_40006000_1,
    iemDecodeA64_60e0fc00_40006400_1,
    iemDecodeA64_60e0fc00_40006800_1,
    iemDecodeA64_60e0fc00_40006c00_1,
    iemDecodeA64_60e0fc00_40007000_1,
    iemDecodeA64_60e0fc00_40007400_1,
    iemDecodeA64_umullb_z_zz,
    iemDecodeA64_60e0fc00_40007c00_1,
    iemDecodeA64_60e0fc00_40008000_1,
    iemDecodeA64_Invalid, // 1057
    iemDecodeA64_ssublbt_z_zz,
    iemDecodeA64_ssubltb_z_zz,
    iemDecodeA64_60e0fc00_40009000_1,
    iemDecodeA64_60e0fc00_40009400_1,
    iemDecodeA64_smmla_z_zzz,
    iemDecodeA64_SQRSHRN_asisdshf_N,
    iemDecodeA64_60e0fc00_4000a000_1,
    iemDecodeA64_sshllt_z_zi,
    iemDecodeA64_ushllb_z_zi,
    iemDecodeA64_ushllt_z_zi,
    iemDecodeA64_60e0fc00_4000b000_1,
    iemDecodeA64_bdep_z_zz,
    iemDecodeA64_bgrp_z_zz,
    iemDecodeA64_Invalid, // 1071
    iemDecodeA64_60e0fc00_4000c000_1,
    iemDecodeA64_60e0fc00_4000c400_1,
    iemDecodeA64_60e0fc00_4000c800_1,
    iemDecodeA64_60e0fc00_4000cc00_1,
    iemDecodeA64_60e0fc00_4000d000_1,
    iemDecodeA64_adclt_z_zzz,
    iemDecodeA64_60e0fc00_4000d800_1,
    iemDecodeA64_Invalid, // 1079
    iemDecodeA64_60e0fc00_4000e000_1,
    iemDecodeA64_60e0fc00_4000e400_1,
    iemDecodeA64_60e0fc00_4000e800_1,
    iemDecodeA64_60e0fc00_4000ec00_1,
    iemDecodeA64_sri_z_zzi,
    iemDecodeA64_sli_z_zzi,
    iemDecodeA64_60e0fc00_4000f800_1,
    iemDecodeA64_60e0fc00_4000fc00_1,
    iemDecodeA64_60e0fc00_40200000_1,
    iemDecodeA64_60e0fc00_40200400_1,
    iemDecodeA64_60e0fc00_40200800_1,
    iemDecodeA64_60e0fc00_40200c00_1,
    iemDecodeA64_60e0fc00_40201000_1,
    iemDecodeA64_60e0fc00_40201400_1,
    iemDecodeA64_60e0fc00_40201800_1,
    iemDecodeA64_60e0fc00_40201c00_1,
    iemDecodeA64_60e0fc00_40202000_1,
    iemDecodeA64_sqshrnt_z_zi,
    iemDecodeA64_60e0fc00_40202800_1,
    iemDecodeA64_60e0fc00_40202c00_1,
    iemDecodeA64_60e0fc00_40203000_1,
    iemDecodeA64_60e0fc00_40203400_1,
    iemDecodeA64_60e0fc00_40203800_1,
    iemDecodeA64_uqrshrnt_z_zi,
    iemDecodeA64_60e0fc00_40204000_1,
    iemDecodeA64_sqxtnt_z_zz,
    iemDecodeA64_60e0fc00_40204800_1,
    iemDecodeA64_60e0fc00_40204c00_1,
    iemDecodeA64_60e0fc00_40205000_1,
    iemDecodeA64_sqxtunt_z_zz,
    iemDecodeA64_AESD_B_cryptoaes,
    iemDecodeA64_SQRSHL_asisdsame_only,
    iemDecodeA64_60e0fc00_40206000_1,
    iemDecodeA64_addhnt_z_zz,
    iemDecodeA64_60e0fc00_40206800_1,
    iemDecodeA64_raddhnt_z_zz,
    iemDecodeA64_subhnb_z_zz,
    iemDecodeA64_subhnt_z_zz,
    iemDecodeA64_60e0fc00_40207800_1,
    iemDecodeA64_60e0fc00_40207c00_1,
    iemDecodeA64_60e0fc00_40208000_1,
    iemDecodeA64_SWPT_64_memop_unpriv,
    iemDecodeA64_Invalid, // 1122
    iemDecodeA64_Invalid, // 1123
    iemDecodeA64_60e0fc00_40209000_1,
    iemDecodeA64_Invalid, // 1125
    iemDecodeA64_Invalid, // 1126
    iemDecodeA64_Invalid, // 1127
    iemDecodeA64_60e0fc00_4020a000_1,
    iemDecodeA64_sqdmulh_mz_zzv_2x1,
    iemDecodeA64_60e0fc00_4020a800_1,
    iemDecodeA64_sqdmulh_mz_zzv_4x1,
    iemDecodeA64_60e0fc00_4020b000_1,
    iemDecodeA64_60e0fc00_4020b400_1,
    iemDecodeA64_60e0fc00_4020b800_1,
    iemDecodeA64_60e0fc00_4020bc00_1,
    iemDecodeA64_60e0fc00_4020c000_1,
    iemDecodeA64_60e0fc00_4020c400_1,
    iemDecodeA64_60e0fc00_4020c800_1,
    iemDecodeA64_60e0fc00_4020cc00_1,
    iemDecodeA64_60e0fc00_4020d000_1,
    iemDecodeA64_60e0fc00_4020d400_1,
    iemDecodeA64_60e0fc00_4020d800_1,
    iemDecodeA64_60e0fc00_4020dc00_1,
    iemDecodeA64_60e0fc00_4020e000_1,
    iemDecodeA64_60e0fc00_4020e400_1,
    iemDecodeA64_60e0fc00_4020e800_1,
    iemDecodeA64_60e0fc00_4020ec00_1,
    iemDecodeA64_60e0fc00_4020f000_1,
    iemDecodeA64_60e0fc00_4020f400_1,
    iemDecodeA64_60e0fc00_4020f800_1,
    iemDecodeA64_60e0fc00_4020fc00_1,
    iemDecodeA64_60e0fc00_40400000_1,
    iemDecodeA64_60e0fc00_40400400_1,
    iemDecodeA64_60e0fc00_40400800_1,
    iemDecodeA64_60e0fc00_40400c00_1,
    iemDecodeA64_60e0fc00_40401000_1,
    iemDecodeA64_Invalid, // 1157
    iemDecodeA64_LDIAPP_64L_ldiappstilp,
    iemDecodeA64_FMULX_asisdsamefp16_only,
    iemDecodeA64_LUTI4_asimdtbl_L5,
    iemDecodeA64_FCMEQ_asisdsamefp16_only,
    iemDecodeA64_Invalid, // 1162
    iemDecodeA64_Invalid, // 1163
    iemDecodeA64_Invalid, // 1164
    iemDecodeA64_Invalid, // 1165
    iemDecodeA64_Invalid, // 1166
    iemDecodeA64_FRECPS_asisdsamefp16_only,
    iemDecodeA64_Invalid, // 1168
    iemDecodeA64_Invalid, // 1169
    iemDecodeA64_Invalid, // 1170
    iemDecodeA64_Invalid, // 1171
    iemDecodeA64_Invalid, // 1172
    iemDecodeA64_Invalid, // 1173
    iemDecodeA64_Invalid, // 1174
    iemDecodeA64_Invalid, // 1175
    iemDecodeA64_Invalid, // 1176
    iemDecodeA64_Invalid, // 1177
    iemDecodeA64_Invalid, // 1178
    iemDecodeA64_Invalid, // 1179
    iemDecodeA64_Invalid, // 1180
    iemDecodeA64_Invalid, // 1181
    iemDecodeA64_Invalid, // 1182
    iemDecodeA64_60e0fc00_40407c00_1,
    iemDecodeA64_60e0fc00_40408000_1,
    iemDecodeA64_SM3TT1B_VVV4_crypto3_imm2,
    iemDecodeA64_SM3TT2A_VVV4_crypto3_imm2,
    iemDecodeA64_SM3TT2B_VVV_crypto3_imm2,
    iemDecodeA64_60e0fc00_40409000_1,
    iemDecodeA64_Invalid, // 1189
    iemDecodeA64_Invalid, // 1190
    iemDecodeA64_Invalid, // 1191
    iemDecodeA64_60e0fc00_4040a000_1,
    iemDecodeA64_Invalid, // 1193
    iemDecodeA64_Invalid, // 1194
    iemDecodeA64_Invalid, // 1195
    iemDecodeA64_Invalid, // 1196
    iemDecodeA64_Invalid, // 1197
    iemDecodeA64_Invalid, // 1198
    iemDecodeA64_Invalid, // 1199
    iemDecodeA64_60e0fc00_4040c000_1,
    iemDecodeA64_FMLALLTT_asimdsame2_G,
    iemDecodeA64_Invalid, // 1202
    iemDecodeA64_Invalid, // 1203
    iemDecodeA64_Invalid, // 1204
    iemDecodeA64_Invalid, // 1205
    iemDecodeA64_Invalid, // 1206
    iemDecodeA64_Invalid, // 1207
    iemDecodeA64_60e0fc00_4040e000_1,
    iemDecodeA64_Invalid, // 1209
    iemDecodeA64_Invalid, // 1210
    iemDecodeA64_Invalid, // 1211
    iemDecodeA64_Invalid, // 1212
    iemDecodeA64_Invalid, // 1213
    iemDecodeA64_Invalid, // 1214
    iemDecodeA64_60e0fc00_4040fc00_1,
    iemDecodeA64_60e0fc00_40600000_1,
    iemDecodeA64_60e0fc00_40600400_1,
    iemDecodeA64_60e0fc00_40600800_1,
    iemDecodeA64_60e0fc00_40600c00_1,
    iemDecodeA64_Invalid, // 1220
    iemDecodeA64_60e0fc00_40601400_1,
    iemDecodeA64_Invalid, // 1222
    iemDecodeA64_60e0fc00_40601c00_1,
    iemDecodeA64_Invalid, // 1224
    iemDecodeA64_Invalid, // 1225
    iemDecodeA64_Invalid, // 1226
    iemDecodeA64_Invalid, // 1227
    iemDecodeA64_Invalid, // 1228
    iemDecodeA64_LDTSETL_64_memop_unpriv,
    iemDecodeA64_Invalid, // 1230
    iemDecodeA64_Invalid, // 1231
    iemDecodeA64_Invalid, // 1232
    iemDecodeA64_Invalid, // 1233
    iemDecodeA64_Invalid, // 1234
    iemDecodeA64_Invalid, // 1235
    iemDecodeA64_Invalid, // 1236
    iemDecodeA64_Invalid, // 1237
    iemDecodeA64_Invalid, // 1238
    iemDecodeA64_Invalid, // 1239
    iemDecodeA64_Invalid, // 1240
    iemDecodeA64_Invalid, // 1241
    iemDecodeA64_Invalid, // 1242
    iemDecodeA64_Invalid, // 1243
    iemDecodeA64_Invalid, // 1244
    iemDecodeA64_Invalid, // 1245
    iemDecodeA64_Invalid, // 1246
    iemDecodeA64_CASPA_CP64_comswappr,
    iemDecodeA64_60e0fc00_40608000_1,
    iemDecodeA64_60e0fc00_40608400_1,
    iemDecodeA64_SHA512SU1_VVV2_cryptosha512_3,
    iemDecodeA64_RAX1_VVV2_cryptosha512_3,
    iemDecodeA64_RCWSCLRPL_128_memop_128,
    iemDecodeA64_Invalid, // 1253
    iemDecodeA64_Invalid, // 1254
    iemDecodeA64_Invalid, // 1255
    iemDecodeA64_60e0fc00_4060a000_1,
    iemDecodeA64_luti4_z_zz_8,
    iemDecodeA64_FCVTNS_asisdmiscfp16_R,
    iemDecodeA64_Invalid, // 1259
    iemDecodeA64_RCWSSETPL_128_memop_128,
    iemDecodeA64_Invalid, // 1261
    iemDecodeA64_FCVTMS_asisdmiscfp16_R,
    iemDecodeA64_Invalid, // 1263
    iemDecodeA64_60e0fc00_4060c000_1,
    iemDecodeA64_SM3PARTW2_VVV4_cryptosha512_3,
    iemDecodeA64_60e0fc00_4060c800_1,
    iemDecodeA64_Invalid, // 1267
    iemDecodeA64_Invalid, // 1268
    iemDecodeA64_Invalid, // 1269
    iemDecodeA64_SCVTF_asisdmiscfp16_R,
    iemDecodeA64_Invalid, // 1271
    iemDecodeA64_60e0fc00_4060e000_1,
    iemDecodeA64_Invalid, // 1273
    iemDecodeA64_Invalid, // 1274
    iemDecodeA64_Invalid, // 1275
    iemDecodeA64_Invalid, // 1276
    iemDecodeA64_Invalid, // 1277
    iemDecodeA64_Invalid, // 1278
    iemDecodeA64_CASPAL_CP64_comswappr,
    iemDecodeA64_60e0fc00_40800000_1,
    iemDecodeA64_60e0fc00_40800400_1,
    iemDecodeA64_60e0fc00_40800800_1,
    iemDecodeA64_ERETAB_64E_branch_reg,
    iemDecodeA64_60e0fc00_40801000_1,
    iemDecodeA64_Invalid, // 1285
    iemDecodeA64_Invalid, // 1286
    iemDecodeA64_Invalid, // 1287
    iemDecodeA64_ldff1sh_z_p_bz_d_x32_unscaled,
    iemDecodeA64_Invalid, // 1289
    iemDecodeA64_Invalid, // 1290
    iemDecodeA64_Invalid, // 1291
    iemDecodeA64_Invalid, // 1292
    iemDecodeA64_Invalid, // 1293
    iemDecodeA64_Invalid, // 1294
    iemDecodeA64_Invalid, // 1295
    iemDecodeA64_60e0fc00_40804000_1,
    iemDecodeA64_Invalid, // 1297
    iemDecodeA64_Invalid, // 1298
    iemDecodeA64_Invalid, // 1299
    iemDecodeA64_FMLS_asisdelem_R_SD,
    iemDecodeA64_Invalid, // 1301
    iemDecodeA64_Invalid, // 1302
    iemDecodeA64_Invalid, // 1303
    iemDecodeA64_60e0fc00_40806000_1,
    iemDecodeA64_Invalid, // 1305
    iemDecodeA64_Invalid, // 1306
    iemDecodeA64_Invalid, // 1307
    iemDecodeA64_Invalid, // 1308
    iemDecodeA64_Invalid, // 1309
    iemDecodeA64_usdot_z_zzz_s,
    iemDecodeA64_60e0fc00_40807c00_1,
    iemDecodeA64_60e0fc00_40808000_1,
    iemDecodeA64_Invalid, // 1313
    iemDecodeA64_Invalid, // 1314
    iemDecodeA64_Invalid, // 1315
    iemDecodeA64_60e0fc00_40809000_1,
    iemDecodeA64_Invalid, // 1317
    iemDecodeA64_usmmla_z_zzz,
    iemDecodeA64_Invalid, // 1319
    iemDecodeA64_Invalid, // 1320
    iemDecodeA64_SMMLA_asimdsame2_G,
    iemDecodeA64_Invalid, // 1322
    iemDecodeA64_USMMLA_asimdsame2_G,
    iemDecodeA64_Invalid, // 1324
    iemDecodeA64_Invalid, // 1325
    iemDecodeA64_Invalid, // 1326
    iemDecodeA64_Invalid, // 1327
    iemDecodeA64_60e0fc00_4080c000_1,
    iemDecodeA64_Invalid, // 1329
    iemDecodeA64_sdot_z32_zzzi,
    iemDecodeA64_udot_z32_zzzi,
    iemDecodeA64_sbclb_z_zzz,
    iemDecodeA64_sbclt_z_zzz,
    iemDecodeA64_Invalid, // 1334
    iemDecodeA64_Invalid, // 1335
    iemDecodeA64_60e0fc00_4080e000_1,
    iemDecodeA64_Invalid, // 1337
    iemDecodeA64_Invalid, // 1338
    iemDecodeA64_Invalid, // 1339
    iemDecodeA64_Invalid, // 1340
    iemDecodeA64_Invalid, // 1341
    iemDecodeA64_Invalid, // 1342
    iemDecodeA64_60e0fc00_4080fc00_1,
    iemDecodeA64_60e0fc00_40a00000_1,
    iemDecodeA64_60e0fc00_40a00400_1,
    iemDecodeA64_60e0fc00_40a00800_1,
    iemDecodeA64_60e0fc00_40a00c00_1,
    iemDecodeA64_60e0fc00_40a01000_1,
    iemDecodeA64_60e0fc00_40a01400_1,
    iemDecodeA64_60e0fc00_40a01800_1,
    iemDecodeA64_60e0fc00_40a01c00_1,
    iemDecodeA64_60e0fc00_40a02000_1,
    iemDecodeA64_sqdmlalt_z_zzzi_s,
    iemDecodeA64_sqrshrn_z_mz2,
    iemDecodeA64_Invalid, // 1355
    iemDecodeA64_sqdmlslb_z_zzzi_s,
    iemDecodeA64_60e0fc00_40a03400_1,
    iemDecodeA64_uqrshrn_z_mz2,
    iemDecodeA64_Invalid, // 1359
    iemDecodeA64_60e0fc00_40a04000_1,
    iemDecodeA64_Invalid, // 1361
    iemDecodeA64_Invalid, // 1362
    iemDecodeA64_Invalid, // 1363
    iemDecodeA64_Invalid, // 1364
    iemDecodeA64_Invalid, // 1365
    iemDecodeA64_Invalid, // 1366
    iemDecodeA64_Invalid, // 1367
    iemDecodeA64_60e0fc00_40a06000_1,
    iemDecodeA64_Invalid, // 1369
    iemDecodeA64_Invalid, // 1370
    iemDecodeA64_Invalid, // 1371
    iemDecodeA64_sqrdcmlah_z_zzzi_h,
    iemDecodeA64_Invalid, // 1373
    iemDecodeA64_Invalid, // 1374
    iemDecodeA64_60e0fc00_40a07c00_1,
    iemDecodeA64_60e0fc00_40a08000_1,
    iemDecodeA64_60e0fc00_40a08400_1,
    iemDecodeA64_Invalid, // 1378
    iemDecodeA64_Invalid, // 1379
    iemDecodeA64_60e0fc00_40a09000_1,
    iemDecodeA64_umlalt_z_zzzi_s,
    iemDecodeA64_Invalid, // 1382
    iemDecodeA64_Invalid, // 1383
    iemDecodeA64_60e0fc00_40a0a000_1,
    iemDecodeA64_smlslt_z_zzzi_s,
    iemDecodeA64_FCVTPS_asisdmisc_R,
    iemDecodeA64_Invalid, // 1387
    iemDecodeA64_60e0fc00_40a0b000_1,
    iemDecodeA64_umlslt_z_zzzi_s,
    iemDecodeA64_FCVTZS_asisdmisc_R,
    iemDecodeA64_Invalid, // 1391
    iemDecodeA64_60e0fc00_40a0c000_1,
    iemDecodeA64_smullt_z_zzi_s,
    iemDecodeA64_60e0fc00_40a0c800_1,
    iemDecodeA64_Invalid, // 1395
    iemDecodeA64_umullb_z_zzi_s,
    iemDecodeA64_umullt_z_zzi_s,
    iemDecodeA64_60e0fc00_40a0d800_1,
    iemDecodeA64_Invalid, // 1399
    iemDecodeA64_60e0fc00_40a0e000_1,
    iemDecodeA64_sqdmullt_z_zzi_s,
    iemDecodeA64_FCMLT_asisdmisc_FZ,
    iemDecodeA64_Invalid, // 1403
    iemDecodeA64_sqdmulh_z_zzi_s,
    iemDecodeA64_sqrdmulh_z_zzi_s,
    iemDecodeA64_60e0fc00_40a0f800_1,
    iemDecodeA64_60e0fc00_40a0fc00_1,
    iemDecodeA64_60e0fc00_40c00000_1,
    iemDecodeA64_60e0fc00_40c00400_1,
    iemDecodeA64_60e0fc00_40c00800_1,
    iemDecodeA64_60e0fc00_40c00c00_1,
    iemDecodeA64_60e0fc00_40c01000_1,
    iemDecodeA64_60e0fc00_40c01400_1,
    iemDecodeA64_60e0fc00_40c01800_1,
    iemDecodeA64_60e0fc00_40c01c00_1,
    iemDecodeA64_60e0fc00_40c02000_1,
    iemDecodeA64_PACIZB_64Z_dp_1src,
    iemDecodeA64_PACDZA_64Z_dp_1src,
    iemDecodeA64_PACDZB_64Z_dp_1src,
    iemDecodeA64_AUTIZA_64Z_dp_1src,
    iemDecodeA64_AUTIZB_64Z_dp_1src,
    iemDecodeA64_AUTDZA_64Z_dp_1src,
    iemDecodeA64_60e0fc00_40c03c00_1,
    iemDecodeA64_XPACI_64Z_dp_1src,
    iemDecodeA64_XPACD_64Z_dp_1src,
    iemDecodeA64_Invalid, // 1426
    iemDecodeA64_Invalid, // 1427
    iemDecodeA64_Invalid, // 1428
    iemDecodeA64_Invalid, // 1429
    iemDecodeA64_Invalid, // 1430
    iemDecodeA64_Invalid, // 1431
    iemDecodeA64_Invalid, // 1432
    iemDecodeA64_Invalid, // 1433
    iemDecodeA64_Invalid, // 1434
    iemDecodeA64_Invalid, // 1435
    iemDecodeA64_Invalid, // 1436
    iemDecodeA64_Invalid, // 1437
    iemDecodeA64_Invalid, // 1438
    iemDecodeA64_60e0fc00_40c07c00_1,
    iemDecodeA64_60e0fc00_40c08000_1,
    iemDecodeA64_60e0fc00_40c08400_1,
    iemDecodeA64_60e0fc00_40c08800_1,
    iemDecodeA64_PACIB171615_64LR_dp_1src,
    iemDecodeA64_60e0fc00_40c09000_1,
    iemDecodeA64_AUTIBSPPCR_64LRR_dp_1src,
    iemDecodeA64_ummla_z_zzz,
    iemDecodeA64_Invalid, // 1447
    iemDecodeA64_60e0fc00_40c0a000_1,
    iemDecodeA64_PACIBSPPC_64LR_dp_1src,
    iemDecodeA64_Invalid, // 1450
    iemDecodeA64_Invalid, // 1451
    iemDecodeA64_Invalid, // 1452
    iemDecodeA64_Invalid, // 1453
    iemDecodeA64_AUTIA171615_64LR_dp_1src,
    iemDecodeA64_AUTIB171615_64LR_dp_1src,
    iemDecodeA64_60e0fc00_40c0c000_1,
    iemDecodeA64_Invalid, // 1457
    iemDecodeA64_Invalid, // 1458
    iemDecodeA64_Invalid, // 1459
    iemDecodeA64_mlapt_z_zzz,
    iemDecodeA64_Invalid, // 1461
    iemDecodeA64_madpt_z_zzz,
    iemDecodeA64_Invalid, // 1463
    iemDecodeA64_60e0fc00_40c0e000_1,
    iemDecodeA64_Invalid, // 1465
    iemDecodeA64_Invalid, // 1466
    iemDecodeA64_Invalid, // 1467
    iemDecodeA64_Invalid, // 1468
    iemDecodeA64_Invalid, // 1469
    iemDecodeA64_Invalid, // 1470
    iemDecodeA64_60e0fc00_40c0fc00_1,
    iemDecodeA64_60e0fc00_40e00000_1,
    iemDecodeA64_60e0fc00_40e00400_1,
    iemDecodeA64_60e0fc00_40e00800_1,
    iemDecodeA64_60e0fc00_40e00c00_1,
    iemDecodeA64_60e0fc00_40e01000_1,
    iemDecodeA64_60e0fc00_40e01400_1,
    iemDecodeA64_Invalid, // 1478
    iemDecodeA64_60e0fc00_40e01c00_1,
    iemDecodeA64_sqdmlalb_z_zzzi_d,
    iemDecodeA64_sqdmlalt_z_zzzi_d,
    iemDecodeA64_Invalid, // 1482
    iemDecodeA64_Invalid, // 1483
    iemDecodeA64_sqdmlslb_z_zzzi_d,
    iemDecodeA64_60e0fc00_40e03400_1,
    iemDecodeA64_Invalid, // 1486
    iemDecodeA64_CMGE_asisdsame_only,
    iemDecodeA64_cdot_z_zzzi_d,
    iemDecodeA64_SSHL_asisdsame_only,
    iemDecodeA64_Invalid, // 1490
    iemDecodeA64_Invalid, // 1491
    iemDecodeA64_Invalid, // 1492
    iemDecodeA64_SRSHL_asisdsame_only,
    iemDecodeA64_Invalid, // 1494
    iemDecodeA64_Invalid, // 1495
    iemDecodeA64_cmla_z_zzzi_s,
    iemDecodeA64_Invalid, // 1497
    iemDecodeA64_Invalid, // 1498
    iemDecodeA64_Invalid, // 1499
    iemDecodeA64_sqrdcmlah_z_zzzi_s,
    iemDecodeA64_Invalid, // 1501
    iemDecodeA64_Invalid, // 1502
    iemDecodeA64_60e0fc00_40e07c00_1,
    iemDecodeA64_60e0fc00_40e08000_1,
    iemDecodeA64_60e0fc00_40e08400_1,
    iemDecodeA64_CMGT_asisdmisc_Z,
    iemDecodeA64_CMTST_asisdsame_only,
    iemDecodeA64_60e0fc00_40e09000_1,
    iemDecodeA64_umlalt_z_zzzi_d,
    iemDecodeA64_CMEQ_asisdmisc_Z,
    iemDecodeA64_Invalid, // 1511
    iemDecodeA64_60e0fc00_40e0a000_1,
    iemDecodeA64_smlslt_z_zzzi_d,
    iemDecodeA64_60e0fc00_40e0a800_1,
    iemDecodeA64_Invalid, // 1515
    iemDecodeA64_60e0fc00_40e0b000_1,
    iemDecodeA64_umlslt_z_zzzi_d,
    iemDecodeA64_60e0fc00_40e0b800_1,
    iemDecodeA64_Invalid, // 1519
    iemDecodeA64_60e0fc00_40e0c000_1,
    iemDecodeA64_smullt_z_zzi_d,
    iemDecodeA64_FCMGT_asisdmiscfp16_FZ,
    iemDecodeA64_Invalid, // 1523
    iemDecodeA64_umullb_z_zzi_d,
    iemDecodeA64_60e0fc00_40e0d400_1,
    iemDecodeA64_60e0fc00_40e0d800_1,
    iemDecodeA64_Invalid, // 1527
    iemDecodeA64_60e0fc00_40e0e000_1,
    iemDecodeA64_sqdmullt_z_zzi_d,
    iemDecodeA64_FCMLT_asisdmiscfp16_FZ,
    iemDecodeA64_Invalid, // 1531
    iemDecodeA64_sqdmulh_z_zzi_d,
    iemDecodeA64_sqrdmulh_z_zzi_d,
    iemDecodeA64_60e0fc00_40e0f800_1,
    iemDecodeA64_60e0fc00_40e0fc00_1,
    iemDecodeA64_60e0fc00_60000000_1,
    iemDecodeA64_60e0fc00_60000400_1,
    iemDecodeA64_60e0fc00_60000800_1,
    iemDecodeA64_60e0fc00_60000c00_1,
    iemDecodeA64_Invalid, // 1540
    iemDecodeA64_USRA_asisdshf_R,
    iemDecodeA64_frecps_z_zz,
    iemDecodeA64_frsqrts_z_zz,
    iemDecodeA64_60e0fc00_60002000_1,
    iemDecodeA64_URSHR_asisdshf_R,
    iemDecodeA64_Invalid, // 1546
    iemDecodeA64_Invalid, // 1547
    iemDecodeA64_60e0fc00_60003000_1,
    iemDecodeA64_60e0fc00_60003400_1,
    iemDecodeA64_60e0fc00_60003800_1,
    iemDecodeA64_60e0fc00_60003c00_1,
    iemDecodeA64_60e0fc00_60004000_1,
    iemDecodeA64_SRI_asisdshf_R,
    iemDecodeA64_Invalid, // 1554
    iemDecodeA64_Invalid, // 1555
    iemDecodeA64_Invalid, // 1556
    iemDecodeA64_SLI_asisdshf_R,
    iemDecodeA64_Invalid, // 1558
    iemDecodeA64_Invalid, // 1559
    iemDecodeA64_60e0fc00_60006000_1,
    iemDecodeA64_SQSHLU_asisdshf_R,
    iemDecodeA64_Invalid, // 1562
    iemDecodeA64_Invalid, // 1563
    iemDecodeA64_Invalid, // 1564
    iemDecodeA64_UQSHL_asisdshf_R,
    iemDecodeA64_Invalid, // 1566
    iemDecodeA64_Invalid, // 1567
    iemDecodeA64_60e0fc00_60008000_1,
    iemDecodeA64_60e0fc00_60008400_1,
    iemDecodeA64_Invalid, // 1570
    iemDecodeA64_60e0fc00_60008c00_1,
    iemDecodeA64_FMULX_asisdelem_RH_H,
    iemDecodeA64_UQSHRN_asisdshf_N,
    iemDecodeA64_Invalid, // 1574
    iemDecodeA64_UQRSHRN_asisdshf_N,
    iemDecodeA64_60e0fc00_6000a000_1,
    iemDecodeA64_Invalid, // 1577
    iemDecodeA64_Invalid, // 1578
    iemDecodeA64_Invalid, // 1579
    iemDecodeA64_Invalid, // 1580
    iemDecodeA64_Invalid, // 1581
    iemDecodeA64_Invalid, // 1582
    iemDecodeA64_Invalid, // 1583
    iemDecodeA64_60e0fc00_6000c000_1,
    iemDecodeA64_Invalid, // 1585
    iemDecodeA64_Invalid, // 1586
    iemDecodeA64_Invalid, // 1587
    iemDecodeA64_SQRDMLAH_asisdelem_R,
    iemDecodeA64_Invalid, // 1589
    iemDecodeA64_Invalid, // 1590
    iemDecodeA64_Invalid, // 1591
    iemDecodeA64_60e0fc00_6000e000_1,
    iemDecodeA64_60e0fc00_6000e400_1,
    iemDecodeA64_Invalid, // 1594
    iemDecodeA64_FMMLA_asimd_FP8FP16,
    iemDecodeA64_SQRDMLSH_asisdelem_R,
    iemDecodeA64_FMOV_asimdimm_D2_d,
    iemDecodeA64_Invalid, // 1598
    iemDecodeA64_FCVTZU_asisdshf_C,
    iemDecodeA64_60e0fc00_60200000_1,
    iemDecodeA64_60e0fc00_60200400_1,
    iemDecodeA64_60e0fc00_60200800_1,
    iemDecodeA64_60e0fc00_60200c00_1,
    iemDecodeA64_60e0fc00_60201000_1,
    iemDecodeA64_Invalid, // 1605
    iemDecodeA64_Invalid, // 1606
    iemDecodeA64_Invalid, // 1607
    iemDecodeA64_60e0fc00_60202000_1,
    iemDecodeA64_60e0fc00_60202400_1,
    iemDecodeA64_60e0fc00_60202800_1,
    iemDecodeA64_UQSUB_asisdsame_only,
    iemDecodeA64_60e0fc00_60203000_1,
    iemDecodeA64_Invalid, // 1613
    iemDecodeA64_USQADD_asisdmisc_R,
    iemDecodeA64_Invalid, // 1615
    iemDecodeA64_60e0fc00_60204000_1,
    iemDecodeA64_fdot_z_zz8z8i,
    iemDecodeA64_UQXTN_asisdmisc_N,
    iemDecodeA64_UQSHL_asisdsame_only,
    iemDecodeA64_60e0fc00_60205000_1,
    iemDecodeA64_Invalid, // 1621
    iemDecodeA64_Invalid, // 1622
    iemDecodeA64_UQRSHL_asisdsame_only,
    iemDecodeA64_60e0fc00_60206000_1,
    iemDecodeA64_Invalid, // 1625
    iemDecodeA64_Invalid, // 1626
    iemDecodeA64_Invalid, // 1627
    iemDecodeA64_60e0fc00_60207000_1,
    iemDecodeA64_Invalid, // 1629
    iemDecodeA64_SQNEG_asisdmisc_R,
    iemDecodeA64_Invalid, // 1631
    iemDecodeA64_60e0fc00_60208000_1,
    iemDecodeA64_fdot_z_zz8z8,
    iemDecodeA64_fmlallbb_z32_z8z8z8,
    iemDecodeA64_Invalid, // 1635
    iemDecodeA64_60e0fc00_60209000_1,
    iemDecodeA64_Invalid, // 1637
    iemDecodeA64_fmlallbt_z32_z8z8z8,
    iemDecodeA64_Invalid, // 1639
    iemDecodeA64_60e0fc00_6020a000_1,
    iemDecodeA64_Invalid, // 1641
    iemDecodeA64_60e0fc00_6020a800_1,
    iemDecodeA64_Invalid, // 1643
    iemDecodeA64_60e0fc00_6020b000_1,
    iemDecodeA64_SQRDMULH_asisdsame_only,
    iemDecodeA64_60e0fc00_6020b800_1,
    iemDecodeA64_Invalid, // 1647
    iemDecodeA64_60e0fc00_6020c000_1,
    iemDecodeA64_Invalid, // 1649
    iemDecodeA64_60e0fc00_6020c800_1,
    iemDecodeA64_Invalid, // 1651
    iemDecodeA64_60e0fc00_6020d000_1,
    iemDecodeA64_Invalid, // 1653
    iemDecodeA64_60e0fc00_6020d800_1,
    iemDecodeA64_Invalid, // 1655
    iemDecodeA64_60e0fc00_6020e000_1,
    iemDecodeA64_60e0fc00_6020e400_1,
    iemDecodeA64_Invalid, // 1658
    iemDecodeA64_FACGE_asisdsame_only,
    iemDecodeA64_60e0fc00_6020f000_1,
    iemDecodeA64_Invalid, // 1661
    iemDecodeA64_60e0fc00_6020f800_1,
    iemDecodeA64_Invalid, // 1663
    iemDecodeA64_60e0fc00_60400000_1,
    iemDecodeA64_60e0fc00_60400400_1,
    iemDecodeA64_60e0fc00_60400800_1,
    iemDecodeA64_60e0fc00_60400c00_1,
    iemDecodeA64_Invalid, // 1668
    iemDecodeA64_Invalid, // 1669
    iemDecodeA64_Invalid, // 1670
    iemDecodeA64_Invalid, // 1671
    iemDecodeA64_60e0fc00_60402000_1,
    iemDecodeA64_FCMGE_asisdsamefp16_only,
    iemDecodeA64_Invalid, // 1674
    iemDecodeA64_FACGE_asisdsamefp16_only,
    iemDecodeA64_Invalid, // 1676
    iemDecodeA64_Invalid, // 1677
    iemDecodeA64_Invalid, // 1678
    iemDecodeA64_Invalid, // 1679
    iemDecodeA64_st1w_z_p_br,
    iemDecodeA64_Invalid, // 1681
    iemDecodeA64_Invalid, // 1682
    iemDecodeA64_Invalid, // 1683
    iemDecodeA64_Invalid, // 1684
    iemDecodeA64_Invalid, // 1685
    iemDecodeA64_Invalid, // 1686
    iemDecodeA64_Invalid, // 1687
    iemDecodeA64_60e0fc00_60406000_1,
    iemDecodeA64_Invalid, // 1689
    iemDecodeA64_Invalid, // 1690
    iemDecodeA64_Invalid, // 1691
    iemDecodeA64_Invalid, // 1692
    iemDecodeA64_Invalid, // 1693
    iemDecodeA64_Invalid, // 1694
    iemDecodeA64_Invalid, // 1695
    iemDecodeA64_60e0fc00_60408000_1,
    iemDecodeA64_Invalid, // 1697
    iemDecodeA64_Invalid, // 1698
    iemDecodeA64_Invalid, // 1699
    iemDecodeA64_Invalid, // 1700
    iemDecodeA64_Invalid, // 1701
    iemDecodeA64_Invalid, // 1702
    iemDecodeA64_Invalid, // 1703
    iemDecodeA64_60e0fc00_6040a000_1,
    iemDecodeA64_Invalid, // 1705
    iemDecodeA64_Invalid, // 1706
    iemDecodeA64_Invalid, // 1707
    iemDecodeA64_Invalid, // 1708
    iemDecodeA64_Invalid, // 1709
    iemDecodeA64_Invalid, // 1710
    iemDecodeA64_Invalid, // 1711
    iemDecodeA64_60e0fc00_6040c000_1,
    iemDecodeA64_Invalid, // 1713
    iemDecodeA64_Invalid, // 1714
    iemDecodeA64_Invalid, // 1715
    iemDecodeA64_Invalid, // 1716
    iemDecodeA64_Invalid, // 1717
    iemDecodeA64_Invalid, // 1718
    iemDecodeA64_Invalid, // 1719
    iemDecodeA64_60e0fc00_6040e000_1,
    iemDecodeA64_Invalid, // 1721
    iemDecodeA64_Invalid, // 1722
    iemDecodeA64_BFMMLA_asimdsame2_E,
    iemDecodeA64_Invalid, // 1724
    iemDecodeA64_Invalid, // 1725
    iemDecodeA64_Invalid, // 1726
    iemDecodeA64_Invalid, // 1727
    iemDecodeA64_60e0fc00_60600000_1,
    iemDecodeA64_Invalid, // 1729
    iemDecodeA64_60e0fc00_60600800_1,
    iemDecodeA64_Invalid, // 1731
    iemDecodeA64_60e0fc00_60601000_1,
    iemDecodeA64_Invalid, // 1733
    iemDecodeA64_Invalid, // 1734
    iemDecodeA64_Invalid, // 1735
    iemDecodeA64_60e0fc00_60602000_1,
    iemDecodeA64_Invalid, // 1737
    iemDecodeA64_Invalid, // 1738
    iemDecodeA64_Invalid, // 1739
    iemDecodeA64_60e0fc00_60603000_1,
    iemDecodeA64_Invalid, // 1741
    iemDecodeA64_Invalid, // 1742
    iemDecodeA64_Invalid, // 1743
    iemDecodeA64_60e0fc00_60604000_1,
    iemDecodeA64_fdot_z32_zz8z8i,
    iemDecodeA64_Invalid, // 1746
    iemDecodeA64_Invalid, // 1747
    iemDecodeA64_60e0fc00_60605000_1,
    iemDecodeA64_Invalid, // 1749
    iemDecodeA64_Invalid, // 1750
    iemDecodeA64_Invalid, // 1751
    iemDecodeA64_60e0fc00_60606000_1,
    iemDecodeA64_Invalid, // 1753
    iemDecodeA64_FCVTXN_asisdmisc_N,
    iemDecodeA64_Invalid, // 1755
    iemDecodeA64_60e0fc00_60607000_1,
    iemDecodeA64_Invalid, // 1757
    iemDecodeA64_Invalid, // 1758
    iemDecodeA64_Invalid, // 1759
    iemDecodeA64_60e0fc00_60608000_1,
    iemDecodeA64_fdot_z32_zz8z8,
    iemDecodeA64_Invalid, // 1762
    iemDecodeA64_Invalid, // 1763
    iemDecodeA64_RCWSCLRL_64_memop,
    iemDecodeA64_Invalid, // 1765
    iemDecodeA64_Invalid, // 1766
    iemDecodeA64_Invalid, // 1767
    iemDecodeA64_60e0fc00_6060a000_1,
    iemDecodeA64_Invalid, // 1769
    iemDecodeA64_FCVTNU_asisdmiscfp16_R,
    iemDecodeA64_Invalid, // 1771
    iemDecodeA64_RCWSSETL_64_memop,
    iemDecodeA64_Invalid, // 1773
    iemDecodeA64_FCVTMU_asisdmiscfp16_R,
    iemDecodeA64_Invalid, // 1775
    iemDecodeA64_60e0fc00_6060c000_1,
    iemDecodeA64_Invalid, // 1777
    iemDecodeA64_FCVTAU_asisdmiscfp16_R,
    iemDecodeA64_Invalid, // 1779
    iemDecodeA64_60e0fc00_6060d000_1,
    iemDecodeA64_Invalid, // 1781
    iemDecodeA64_UCVTF_asisdmiscfp16_R,
    iemDecodeA64_Invalid, // 1783
    iemDecodeA64_60e0fc00_6060e000_1,
    iemDecodeA64_bfmmla_z_zzz,
    iemDecodeA64_Invalid, // 1786
    iemDecodeA64_Invalid, // 1787
    iemDecodeA64_60e0fc00_6060f000_1,
    iemDecodeA64_Invalid, // 1789
    iemDecodeA64_Invalid, // 1790
    iemDecodeA64_Invalid, // 1791
    iemDecodeA64_60e0fc00_60800000_1,
    iemDecodeA64_LDRSH_64_ldst_immpost,
    iemDecodeA64_LDTRSH_64_ldst_unpriv,
    iemDecodeA64_LDRSH_64_ldst_immpre,
    iemDecodeA64_Invalid, // 1796
    iemDecodeA64_Invalid, // 1797
    iemDecodeA64_Invalid, // 1798
    iemDecodeA64_Invalid, // 1799
    iemDecodeA64_60e0fc00_60802000_1,
    iemDecodeA64_Invalid, // 1801
    iemDecodeA64_Invalid, // 1802
    iemDecodeA64_Invalid, // 1803
    iemDecodeA64_Invalid, // 1804
    iemDecodeA64_Invalid, // 1805
    iemDecodeA64_Invalid, // 1806
    iemDecodeA64_Invalid, // 1807
    iemDecodeA64_60e0fc00_60804000_1,
    iemDecodeA64_Invalid, // 1809
    iemDecodeA64_Invalid, // 1810
    iemDecodeA64_Invalid, // 1811
    iemDecodeA64_Invalid, // 1812
    iemDecodeA64_Invalid, // 1813
    iemDecodeA64_Invalid, // 1814
    iemDecodeA64_Invalid, // 1815
    iemDecodeA64_60e0fc00_60806000_1,
    iemDecodeA64_Invalid, // 1817
    iemDecodeA64_Invalid, // 1818
    iemDecodeA64_Invalid, // 1819
    iemDecodeA64_Invalid, // 1820
    iemDecodeA64_Invalid, // 1821
    iemDecodeA64_Invalid, // 1822
    iemDecodeA64_Invalid, // 1823
    iemDecodeA64_60e0fc00_60808000_1,
    iemDecodeA64_Invalid, // 1825
    iemDecodeA64_Invalid, // 1826
    iemDecodeA64_Invalid, // 1827
    iemDecodeA64_FMULX_asisdelem_R_SD,
    iemDecodeA64_Invalid, // 1829
    iemDecodeA64_Invalid, // 1830
    iemDecodeA64_Invalid, // 1831
    iemDecodeA64_60e0fc00_6080a000_1,
    iemDecodeA64_UMMLA_asimdsame2_G,
    iemDecodeA64_Invalid, // 1834
    iemDecodeA64_Invalid, // 1835
    iemDecodeA64_Invalid, // 1836
    iemDecodeA64_Invalid, // 1837
    iemDecodeA64_Invalid, // 1838
    iemDecodeA64_Invalid, // 1839
    iemDecodeA64_bfcvt_z_p_z_s2bfz,
    iemDecodeA64_Invalid, // 1841
    iemDecodeA64_Invalid, // 1842
    iemDecodeA64_Invalid, // 1843
    iemDecodeA64_Invalid, // 1844
    iemDecodeA64_Invalid, // 1845
    iemDecodeA64_Invalid, // 1846
    iemDecodeA64_Invalid, // 1847
    iemDecodeA64_60e0fc00_6080e000_1,
    iemDecodeA64_Invalid, // 1849
    iemDecodeA64_Invalid, // 1850
    iemDecodeA64_FMMLA_asimd_FP8FP32,
    iemDecodeA64_Invalid, // 1852
    iemDecodeA64_Invalid, // 1853
    iemDecodeA64_Invalid, // 1854
    iemDecodeA64_Invalid, // 1855
    iemDecodeA64_60e0fc00_60a00000_1,
    iemDecodeA64_60e0fc00_60a00400_1,
    iemDecodeA64_60e0fc00_60a00800_1,
    iemDecodeA64_LDRAB_64W_ldst_pac,
    iemDecodeA64_60e0fc00_60a01000_1,
    iemDecodeA64_Invalid, // 1861
    iemDecodeA64_Invalid, // 1862
    iemDecodeA64_Invalid, // 1863
    iemDecodeA64_60e0fc00_60a02000_1,
    iemDecodeA64_Invalid, // 1865
    iemDecodeA64_Invalid, // 1866
    iemDecodeA64_Invalid, // 1867
    iemDecodeA64_60e0fc00_60a03000_1,
    iemDecodeA64_Invalid, // 1869
    iemDecodeA64_Invalid, // 1870
    iemDecodeA64_Invalid, // 1871
    iemDecodeA64_60e0fc00_60a04000_1,
    iemDecodeA64_fmlalt_z_zzzi_s,
    iemDecodeA64_Invalid, // 1874
    iemDecodeA64_Invalid, // 1875
    iemDecodeA64_60e0fc00_60a05000_1,
    iemDecodeA64_Invalid, // 1877
    iemDecodeA64_Invalid, // 1878
    iemDecodeA64_Invalid, // 1879
    iemDecodeA64_60e0fc00_60a06000_1,
    iemDecodeA64_fmlslt_z_zzzi_s,
    iemDecodeA64_Invalid, // 1882
    iemDecodeA64_Invalid, // 1883
    iemDecodeA64_60e0fc00_60a07000_1,
    iemDecodeA64_Invalid, // 1885
    iemDecodeA64_Invalid, // 1886
    iemDecodeA64_Invalid, // 1887
    iemDecodeA64_60e0fc00_60a08000_1,
    iemDecodeA64_fmlalt_z_zzz,
    iemDecodeA64_fmlalb_z_z8z8z8,
    iemDecodeA64_Invalid, // 1891
    iemDecodeA64_RCWSCLRA_64_memop,
    iemDecodeA64_Invalid, // 1893
    iemDecodeA64_fmlalt_z_z8z8z8,
    iemDecodeA64_Invalid, // 1895
    iemDecodeA64_60e0fc00_60a0a000_1,
    iemDecodeA64_fmlslt_z_zzz,
    iemDecodeA64_FCVTPU_asisdmisc_R,
    iemDecodeA64_Invalid, // 1899
    iemDecodeA64_RCWSSETA_64_memop,
    iemDecodeA64_Invalid, // 1901
    iemDecodeA64_FCVTZU_asisdmisc_R,
    iemDecodeA64_Invalid, // 1903
    iemDecodeA64_60e0fc00_60a0c000_1,
    iemDecodeA64_Invalid, // 1905
    iemDecodeA64_60e0fc00_60a0c800_1,
    iemDecodeA64_Invalid, // 1907
    iemDecodeA64_Invalid, // 1908
    iemDecodeA64_FABD_asisdsame_only,
    iemDecodeA64_60e0fc00_60a0d800_1,
    iemDecodeA64_Invalid, // 1911
    iemDecodeA64_60e0fc00_60a0e000_1,
    iemDecodeA64_60e0fc00_60a0e400_1,
    iemDecodeA64_Invalid, // 1914
    iemDecodeA64_FACGT_asisdsame_only,
    iemDecodeA64_Invalid, // 1916
    iemDecodeA64_Invalid, // 1917
    iemDecodeA64_60e0fc00_60a0f800_1,
    iemDecodeA64_Invalid, // 1919
    iemDecodeA64_60e0fc00_60c00000_1,
    iemDecodeA64_LDRSH_32_ldst_immpost,
    iemDecodeA64_LDTRSH_32_ldst_unpriv,
    iemDecodeA64_LDRSH_32_ldst_immpre,
    iemDecodeA64_Invalid, // 1924
    iemDecodeA64_FABD_asisdsamefp16_only,
    iemDecodeA64_Invalid, // 1926
    iemDecodeA64_Invalid, // 1927
    iemDecodeA64_stnt1h_z_p_ar_s_x32_unscaled,
    iemDecodeA64_FCMGT_asisdsamefp16_only,
    iemDecodeA64_Invalid, // 1930
    iemDecodeA64_FACGT_asisdsamefp16_only,
    iemDecodeA64_Invalid, // 1932
    iemDecodeA64_Invalid, // 1933
    iemDecodeA64_Invalid, // 1934
    iemDecodeA64_Invalid, // 1935
    iemDecodeA64_st1d_z_p_br_u128,
    iemDecodeA64_Invalid, // 1937
    iemDecodeA64_Invalid, // 1938
    iemDecodeA64_Invalid, // 1939
    iemDecodeA64_Invalid, // 1940
    iemDecodeA64_Invalid, // 1941
    iemDecodeA64_Invalid, // 1942
    iemDecodeA64_Invalid, // 1943
    iemDecodeA64_60e0fc00_60c06000_1,
    iemDecodeA64_Invalid, // 1945
    iemDecodeA64_Invalid, // 1946
    iemDecodeA64_Invalid, // 1947
    iemDecodeA64_Invalid, // 1948
    iemDecodeA64_Invalid, // 1949
    iemDecodeA64_Invalid, // 1950
    iemDecodeA64_Invalid, // 1951
    iemDecodeA64_60e0fc00_60c08000_1,
    iemDecodeA64_Invalid, // 1953
    iemDecodeA64_Invalid, // 1954
    iemDecodeA64_Invalid, // 1955
    iemDecodeA64_Invalid, // 1956
    iemDecodeA64_Invalid, // 1957
    iemDecodeA64_Invalid, // 1958
    iemDecodeA64_Invalid, // 1959
    iemDecodeA64_60e0fc00_60c0a000_1,
    iemDecodeA64_Invalid, // 1961
    iemDecodeA64_Invalid, // 1962
    iemDecodeA64_Invalid, // 1963
    iemDecodeA64_Invalid, // 1964
    iemDecodeA64_Invalid, // 1965
    iemDecodeA64_Invalid, // 1966
    iemDecodeA64_Invalid, // 1967
    iemDecodeA64_60e0fc00_60c0c000_1,
    iemDecodeA64_Invalid, // 1969
    iemDecodeA64_Invalid, // 1970
    iemDecodeA64_Invalid, // 1971
    iemDecodeA64_Invalid, // 1972
    iemDecodeA64_Invalid, // 1973
    iemDecodeA64_Invalid, // 1974
    iemDecodeA64_Invalid, // 1975
    iemDecodeA64_60e0fc00_60c0e000_1,
    iemDecodeA64_Invalid, // 1977
    iemDecodeA64_Invalid, // 1978
    iemDecodeA64_Invalid, // 1979
    iemDecodeA64_Invalid, // 1980
    iemDecodeA64_Invalid, // 1981
    iemDecodeA64_Invalid, // 1982
    iemDecodeA64_Invalid, // 1983
    iemDecodeA64_60e0fc00_60e00000_1,
    iemDecodeA64_fmls_z_zzzi_d,
    iemDecodeA64_LDRSH_32_ldst_regoff,
    iemDecodeA64_Invalid, // 1987
    iemDecodeA64_60e0fc00_60e01000_1,
    iemDecodeA64_Invalid, // 1989
    iemDecodeA64_Invalid, // 1990
    iemDecodeA64_Invalid, // 1991
    iemDecodeA64_60e0fc00_60e02000_1,
    iemDecodeA64_Invalid, // 1993
    iemDecodeA64_Invalid, // 1994
    iemDecodeA64_Invalid, // 1995
    iemDecodeA64_60e0fc00_60e03000_1,
    iemDecodeA64_CMHI_asisdsame_only,
    iemDecodeA64_Invalid, // 1998
    iemDecodeA64_CMHS_asisdsame_only,
    iemDecodeA64_60e0fc00_60e04000_1,
    iemDecodeA64_60e0fc00_60e04400_1,
    iemDecodeA64_Invalid, // 2002
    iemDecodeA64_Invalid, // 2003
    iemDecodeA64_60e0fc00_60e05000_1,
    iemDecodeA64_URSHL_asisdsame_only,
    iemDecodeA64_Invalid, // 2006
    iemDecodeA64_Invalid, // 2007
    iemDecodeA64_60e0fc00_60e06000_1,
    iemDecodeA64_bfmlslt_z_zzzi,
    iemDecodeA64_Invalid, // 2010
    iemDecodeA64_Invalid, // 2011
    iemDecodeA64_60e0fc00_60e07000_1,
    iemDecodeA64_Invalid, // 2013
    iemDecodeA64_Invalid, // 2014
    iemDecodeA64_Invalid, // 2015
    iemDecodeA64_60e0fc00_60e08000_1,
    iemDecodeA64_60e0fc00_60e08400_1,
    iemDecodeA64_CMGE_asisdmisc_Z,
    iemDecodeA64_CMEQ_asisdsame_only,
    iemDecodeA64_RCWSCLRAL_64_memop,
    iemDecodeA64_Invalid, // 2021
    iemDecodeA64_CMLE_asisdmisc_Z,
    iemDecodeA64_Invalid, // 2023
    iemDecodeA64_60e0fc00_60e0a000_1,
    iemDecodeA64_bfmlslt_z_zzz,
    iemDecodeA64_FCVTPU_asisdmiscfp16_R,
    iemDecodeA64_Invalid, // 2027
    iemDecodeA64_RCWSSETAL_64_memop,
    iemDecodeA64_Invalid, // 2029
    iemDecodeA64_60e0fc00_60e0b800_1,
    iemDecodeA64_Invalid, // 2031
    iemDecodeA64_60e0fc00_60e0c000_1,
    iemDecodeA64_Invalid, // 2033
    iemDecodeA64_FCMGE_asisdmiscfp16_FZ,
    iemDecodeA64_Invalid, // 2035
    iemDecodeA64_Invalid, // 2036
    iemDecodeA64_Invalid, // 2037
    iemDecodeA64_60e0fc00_60e0d800_1,
    iemDecodeA64_Invalid, // 2039
    iemDecodeA64_60e0fc00_60e0e000_1,
    iemDecodeA64_fmmla_z_zzz_d,
    iemDecodeA64_Invalid, // 2042
    iemDecodeA64_Invalid, // 2043
    iemDecodeA64_Invalid, // 2044
    iemDecodeA64_Invalid, // 2045
    iemDecodeA64_Invalid, // 2046
    iemDecodeA64_Invalid, // 2047
};
AssertCompile(RT_ELEMENTS(g_apfnIemInterpretOnlyA64) == 0x800);