IEMAllN8veEmit-x86.h@ 103682

Last change on this file since 103682 was 103682, checked in by vboxsync, 13 months ago
VMM/IEM: Cleaning up IEMAllN8veEmit-x86.h a little. bugref:10376
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1	/* $Id: IEMAllN8veEmit-x86.h 103682 2024-03-05 14:23:15Z vboxsync $ */
2	/** @file
3	* IEM - Native Recompiler, x86 Target - Code Emitters.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_VMMAll_target_x86_IEMAllN8veEmit_x86_h
29	#define VMM_INCLUDED_SRC_VMMAll_target_x86_IEMAllN8veEmit_x86_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34
35	#ifdef RT_ARCH_AMD64
36	DECL_FORCE_INLINE(uint32_t)
37	iemNativeEmitAmd64ModRmInstrRREx(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t bOpcode8, uint8_t bOpcodeOther,
38	uint8_t cOpBits, uint8_t idxRegReg, uint8_t idxRegRm)
39	{
40	Assert(idxRegReg < 16); Assert(idxRegRm < 16);
41	switch (cOpBits)
42	{
43	case 16:
44	pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
45	RT_FALL_THRU();
46	case 32:
47	if (idxRegReg >= 8 \|\| idxRegRm >= 8)
48	pCodeBuf[off++] = (idxRegReg >= 8 ? X86_OP_REX_R : 0) \| (idxRegRm >= 8 ? X86_OP_REX_B : 0);
49	pCodeBuf[off++] = bOpcodeOther;
50	break;
51
52	default: AssertFailed(); RT_FALL_THRU();
53	case 64:
54	pCodeBuf[off++] = X86_OP_REX_W \| (idxRegReg >= 8 ? X86_OP_REX_R : 0) \| (idxRegRm >= 8 ? X86_OP_REX_B : 0);
55	pCodeBuf[off++] = bOpcodeOther;
56	break;
57
58	case 8:
59	if (idxRegReg >= 8 \|\| idxRegRm >= 8)
60	pCodeBuf[off++] = (idxRegReg >= 8 ? X86_OP_REX_R : 0) \| (idxRegRm >= 8 ? X86_OP_REX_B : 0);
61	else if (idxRegReg >= 4 \|\| idxRegRm >= 4)
62	pCodeBuf[off++] = X86_OP_REX;
63	pCodeBuf[off++] = bOpcode8;
64	break;
65	}
66	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxRegReg & 7, idxRegRm & 7);
67	return off;
68	}
69	#endif /* RT_ARCH_AMD64 */
70
71
72	/**
73	* This is an implementation of IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL.
74	*
75	* It takes liveness stuff into account.
76	*/
77	DECL_INLINE_THROW(uint32_t)
78	iemNativeEmitEFlagsForLogical(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarEfl,
79	uint8_t cOpBits, uint8_t idxRegResult)
80	{
81	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
82	if (1) /** @todo check if all bits are clobbered. */
83	#endif
84	{
85	#ifdef RT_ARCH_AMD64
86	/*
87	* Collect flags and merge them with eflags.
88	*/
89	/** @todo we could alternatively use SAHF here when host rax is free since,
90	* OF is cleared. */
91	PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
92	/* pushf - do this before any reg allocations as they may emit instructions too. */
93	pCodeBuf[off++] = 0x9c;
94
95	uint8_t const idxRegEfl = iemNativeVarRegisterAcquire(pReNative, idxVarEfl, &off, true /fInitialized/);
96	uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
97	pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2 + 7 + 7 + 3);
98	/* pop tmp */
99	if (idxTmpReg >= 8)
100	pCodeBuf[off++] = X86_OP_REX_B;
101	pCodeBuf[off++] = 0x58 + (idxTmpReg & 7);
102	/* and tmp, X86_EFL_PF \| X86_EFL_ZF \| X86_EFL_SF */
103	off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxTmpReg, X86_EFL_PF \| X86_EFL_ZF \| X86_EFL_SF);
104	/* Clear the status bits in EFLs. */
105	off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxRegEfl, ~X86_EFL_STATUS_BITS);
106	/* OR in the flags we collected. */
107	off = iemNativeEmitOrGpr32ByGprEx(pCodeBuf, off, idxRegEfl, idxTmpReg);
108	iemNativeVarRegisterRelease(pReNative, idxVarEfl);
109	iemNativeRegFreeTmp(pReNative, idxTmpReg);
110	RT_NOREF(cOpBits, idxRegResult);
111
112	#elif defined(RT_ARCH_ARM64)
113	/*
114	* Calculate flags.
115	*/
116	uint8_t const idxRegEfl = iemNativeVarRegisterAcquire(pReNative, idxVarEfl, &off, true /fInitialized/);
117	uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
118	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 15);
119
120	/* Clear the status bits. ~0x8D5 (or ~0x8FD) can't be AND immediate, so use idxTmpReg for constant. */
121	off = iemNativeEmitLoadGpr32ImmEx(pCodeBuf, off, idxTmpReg, ~X86_EFL_STATUS_BITS);
122	off = iemNativeEmitAndGpr32ByGpr32Ex(pCodeBuf, off, idxRegEfl, idxTmpReg);
123
124	/* Calculate zero: mov tmp, zf; cmp result,zero; csel.eq tmp,tmp,wxr */
125	if (cOpBits > 32)
126	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, idxRegResult, ARMV8_A64_REG_XZR);
127	else
128	off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, idxRegResult, ARMV8_A64_REG_XZR);
129	pCodeBuf[off++] = Armv8A64MkInstrCSet(idxTmpReg, kArmv8InstrCond_Eq, false /f64Bit/);
130	pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegEfl, idxRegEfl, idxTmpReg, false /f64Bit/, X86_EFL_ZF_BIT);
131
132	/* Calculate signed: We could use the native SF flag, but it's just as simple to calculate it by shifting. */
133	pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxRegResult, cOpBits - 1, cOpBits > 32 /f64Bit/);
134	# if 0 /* BFI and ORR hsould have the same performance characteristics, so use BFI like we'll have to do for SUB/ADD/++. */
135	pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegEfl, idxRegEfl, idxTmpReg, false /f64Bit/, X86_EFL_SF_BIT);
136	# else
137	pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_SF_BIT, 1, false /f64Bit/);
138	# endif
139
140	/* Calculate 8-bit parity of the result. */
141	pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxRegResult, idxRegResult, false /f64Bit/,
142	4 /offShift6/, kArmv8A64InstrShift_Lsr);
143	pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxTmpReg, idxTmpReg, false /f64Bit/,
144	2 /offShift6/, kArmv8A64InstrShift_Lsr);
145	pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxTmpReg, idxTmpReg, false /f64Bit/,
146	1 /offShift6/, kArmv8A64InstrShift_Lsr);
147	Assert(Armv8A64ConvertImmRImmS2Mask32(0, 0) == 1);
148	pCodeBuf[off++] = Armv8A64MkInstrEorImm(idxTmpReg, idxTmpReg, 0, 0, false /f64Bit/);
149	pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_PF_BIT, 1, false /f64Bit/);
150
151	iemNativeVarRegisterRelease(pReNative, idxVarEfl);
152	iemNativeRegFreeTmp(pReNative, idxTmpReg);
153	#else
154	# error "port me"
155	#endif
156	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
157	}
158	return off;
159	}
160
161
162	/**
163	* This is an implementation of IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC.
164	*
165	* It takes liveness stuff into account.
166	*/
167	DECL_FORCE_INLINE_THROW(uint32_t)
168	iemNativeEmitEFlagsForArithmetic(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarEfl
169	#ifndef RT_ARCH_AMD64
170	, uint8_t cOpBits, uint8_t idxRegResult, uint8_t idxRegDstIn, uint8_t idxRegSrc, bool fNativeFlags
171	#endif
172	)
173	{
174	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
175	if (1) /** @todo check if all bits are clobbered. */
176	#endif
177	{
178	#ifdef RT_ARCH_AMD64
179	/*
180	* Collect flags and merge them with eflags.
181	*/
182	PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
183	/* pushf - do this before any reg allocations as they may emit instructions too. */
184	pCodeBuf[off++] = 0x9c;
185
186	uint8_t const idxRegEfl = iemNativeVarRegisterAcquire(pReNative, idxVarEfl, &off, true /fInitialized/);
187	uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
188	pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2 + 7 + 7 + 3);
189	/* pop tmp */
190	if (idxTmpReg >= 8)
191	pCodeBuf[off++] = X86_OP_REX_B;
192	pCodeBuf[off++] = 0x58 + (idxTmpReg & 7);
193	/* Isolate the flags we want. */
194	off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxTmpReg, X86_EFL_STATUS_BITS);
195	/* Clear the status bits in EFLs. */
196	off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxRegEfl, ~X86_EFL_STATUS_BITS);
197	/* OR in the flags we collected. */
198	off = iemNativeEmitOrGpr32ByGprEx(pCodeBuf, off, idxRegEfl, idxTmpReg);
199	iemNativeVarRegisterRelease(pReNative, idxVarEfl);
200	iemNativeRegFreeTmp(pReNative, idxTmpReg);
201
202	#elif defined(RT_ARCH_ARM64)
203	/*
204	* Calculate flags.
205	*/
206	uint8_t const idxRegEfl = iemNativeVarRegisterAcquire(pReNative, idxVarEfl, &off, true /fInitialized/);
207	uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
208	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 18);
209
210	if (fNativeFlags && cOpBits >= 32)
211	{
212	/* Invert CF (stored inved on ARM) and load the flags into the temporary register. */
213	pCodeBuf[off++] = ARMV8_A64_INSTR_CFINV;
214	pCodeBuf[off++] = Armv8A64MkInstrMrs(idxTmpReg, ARMV8_AARCH64_SYSREG_NZCV); /* Bits: 31=N; 30=Z; 29=C; 28=V; */
215
216	/* V -> OF */
217	pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxTmpReg, 28);
218	pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_OF_BIT, 1, false /f64Bit/);
219
220	/* C -> CF */
221	pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxTmpReg, 1);
222	pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_CF_BIT, 1, false /f64Bit/);
223
224	/* N,Z -> SF,ZF */
225	pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxTmpReg, 1);
226	pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_ZF_BIT, 2, false /f64Bit/);
227	}
228	else
229	{
230	#if 0
231	pCodeBuf[off++] = Armv8A64MkInstrSetF8SetF16(idxRegResult, cOpBits > 8);
232	pCodeBuf[off++] = Armv8A64MkInstrMrs(idxTmpReg, ARMV8_AARCH64_SYSREG_NZCV); /* Bits: 31=N; 30=Z; 29=C; 28=V; */
233
234	/* V -> OF */
235	pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxTmpReg, 28);
236	pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_OF_BIT, 1, false /f64Bit/);
237
238	/* N,Z -> SF,ZF */
239	pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxTmpReg, 2);
240	pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_ZF_BIT, 2, false /f64Bit/);
241	#else
242	pCodeBuf[off++] = Armv8A64MkInstrBrk(0x1010);
243	#endif
244	}
245
246	/* Calculate 8-bit parity of the result. */
247	pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxRegResult, idxRegResult, false /f64Bit/,
248	4 /offShift6/, kArmv8A64InstrShift_Lsr);
249	pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxTmpReg, idxTmpReg, false /f64Bit/,
250	2 /offShift6/, kArmv8A64InstrShift_Lsr);
251	pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxTmpReg, idxTmpReg, false /f64Bit/,
252	1 /offShift6/, kArmv8A64InstrShift_Lsr);
253	Assert(Armv8A64ConvertImmRImmS2Mask32(0, 0) == 1);
254	pCodeBuf[off++] = Armv8A64MkInstrEorImm(idxTmpReg, idxTmpReg, 0, 0, false /f64Bit/);
255	pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_PF_BIT, 1, false /f64Bit/);
256
257	/* Calculate auxilary carry/borrow. This is related to 8-bit BCD.*/
258	pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxRegDstIn, idxRegSrc, false /f64Bit/);
259	pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxTmpReg, idxRegResult, false /f64Bit/);
260	pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxTmpReg, X86_EFL_AF_BIT, false /f64Bit/);
261	pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_AF_BIT, 1, false /f64Bit/);
262
263	iemNativeVarRegisterRelease(pReNative, idxVarEfl);
264	iemNativeRegFreeTmp(pReNative, idxTmpReg);
265	#else
266	# error "port me"
267	#endif
268	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
269	}
270	return off;
271
272	}
273
274
275	/**
276	* The AND instruction will clear OF, CF and AF (latter is undefined) and
277	* set the other flags according to the result.
278	*/
279	DECL_INLINE_THROW(uint32_t)
280	iemNativeEmit_and_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
281	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
282	{
283	uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /fInitialized/);
284	uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /fInitialized/);
285	#ifdef RT_ARCH_AMD64
286	/* On AMD64 we just use the correctly size AND instruction harvest the EFLAGS. */
287	off = iemNativeEmitAmd64ModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
288	0x22, 0x23, cOpBits, idxRegDst, idxRegSrc);
289	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
290
291	#elif defined(RT_ARCH_ARM64)
292	/* On ARM64 we use 32-bit AND for the 8-bit and 16-bit bit ones. */
293	/** @todo we should use ANDS on ARM64 and get the ZF for free for all
294	* variants, and SF for 32-bit and 64-bit. */
295	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
296	pCodeBuf[off++] = Armv8A64MkInstrAnd(idxRegDst, idxRegDst, idxRegSrc, cOpBits > 32 /f64Bit/);
297	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
298
299	#else
300	# error "Port me"
301	#endif
302	iemNativeVarRegisterRelease(pReNative, idxVarSrc);
303
304	off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
305	iemNativeVarRegisterRelease(pReNative, idxVarDst);
306	return off;
307	}
308
309
310	/**
311	* The TEST instruction will clear OF, CF and AF (latter is undefined) and
312	* set the other flags according to the result.
313	*/
314	DECL_INLINE_THROW(uint32_t)
315	iemNativeEmit_test_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
316	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
317	{
318	uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /fInitialized/);
319	uint8_t const idxRegSrc = idxVarSrc == idxVarDst ? idxRegDst /* special case of 'test samereg,samereg' */
320	: iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /fInitialized/);
321	#ifdef RT_ARCH_AMD64
322	/* On AMD64 we just use the correctly size TEST instruction harvest the EFLAGS. */
323	off = iemNativeEmitAmd64ModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
324	0x84, 0x85, cOpBits, idxRegSrc, idxRegDst);
325	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
326
327	#elif defined(RT_ARCH_ARM64)
328	/* On ARM64 we use 32-bit AND for the 8-bit and 16-bit bit ones. We also
329	need to keep the result in order to calculate the flags. */
330	/** @todo we should use ANDS on ARM64 and get the ZF for free for all
331	* variants, and SF for 32-bit and 64-bit. */
332	uint8_t const idxRegResult = iemNativeRegAllocTmp(pReNative, &off);
333	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
334	pCodeBuf[off++] = Armv8A64MkInstrAnd(idxRegResult, idxRegDst, idxRegSrc, cOpBits > 32 /f64Bit/);
335	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
336
337	#else
338	# error "Port me"
339	#endif
340	if (idxVarSrc != idxVarDst)
341	iemNativeVarRegisterRelease(pReNative, idxVarSrc);
342	iemNativeVarRegisterRelease(pReNative, idxVarDst);
343
344	#ifdef RT_ARCH_AMD64
345	off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl, cOpBits, UINT8_MAX);
346	#else
347	off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl, cOpBits, idxRegResult);
348	iemNativeRegFreeTmp(pReNative, idxRegResult);
349	#endif
350	return off;
351	}
352
353
354	/**
355	* The OR instruction will clear OF, CF and AF (latter is undefined) and
356	* set the other flags according to the result.
357	*/
358	DECL_INLINE_THROW(uint32_t)
359	iemNativeEmit_or_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
360	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
361	{
362	uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /fInitialized/);
363	uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /fInitialized/);
364	#ifdef RT_ARCH_AMD64
365	/* On AMD64 we just use the correctly size OR instruction harvest the EFLAGS. */
366	off = iemNativeEmitAmd64ModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
367	0x0a, 0x0b, cOpBits, idxRegDst, idxRegSrc);
368	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
369
370	#elif defined(RT_ARCH_ARM64)
371	/* On ARM64 we use 32-bit OR for the 8-bit and 16-bit bit ones. */
372	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
373	pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegDst, idxRegDst, idxRegSrc, cOpBits > 32 /f64Bit/);
374	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
375
376	#else
377	# error "Port me"
378	#endif
379	iemNativeVarRegisterRelease(pReNative, idxVarSrc);
380
381	off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
382	iemNativeVarRegisterRelease(pReNative, idxVarDst);
383	return off;
384	}
385
386
387	/**
388	* The XOR instruction will clear OF, CF and AF (latter is undefined) and
389	* set the other flags according to the result.
390	*/
391	DECL_INLINE_THROW(uint32_t)
392	iemNativeEmit_xor_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
393	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
394	{
395	uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /fInitialized/);
396	uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /fInitialized/);
397	#ifdef RT_ARCH_AMD64
398	/* On AMD64 we just use the correctly size OR instruction harvest the EFLAGS. */
399	off = iemNativeEmitAmd64ModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
400	0x32, 0x33, cOpBits, idxRegDst, idxRegSrc);
401	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
402
403	#elif defined(RT_ARCH_ARM64)
404	/* On ARM64 we use 32-bit OR for the 8-bit and 16-bit bit ones. */
405	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
406	pCodeBuf[off++] = Armv8A64MkInstrEor(idxRegDst, idxRegDst, idxRegSrc, cOpBits > 32 /f64Bit/);
407	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
408
409	#else
410	# error "Port me"
411	#endif
412	iemNativeVarRegisterRelease(pReNative, idxVarSrc);
413
414	off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
415	iemNativeVarRegisterRelease(pReNative, idxVarDst);
416	return off;
417	}
418
419
420	DECL_INLINE_THROW(uint32_t)
421	iemNativeEmit_add_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
422	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
423	{
424	RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
425	AssertFailed();
426	return iemNativeEmitBrk(pReNative, off, 0x666);
427	}
428
429
430	DECL_INLINE_THROW(uint32_t)
431	iemNativeEmit_adc_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
432	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
433	{
434	RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
435	AssertFailed();
436	return iemNativeEmitBrk(pReNative, off, 0x666);
437	}
438
439
440	DECL_INLINE_THROW(uint32_t)
441	iemNativeEmit_sub_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
442	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
443	{
444	/*
445	* The SUB instruction will set all flags.
446	*/
447	uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /fInitialized/);
448	uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /fInitialized/);
449
450	#ifdef RT_ARCH_AMD64
451	/* On AMD64 we just use the correctly sized SUB instruction to get the right EFLAGS.SF value. */
452	off = iemNativeEmitAmd64ModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
453	0x2a, 0x2b, cOpBits, idxRegDst, idxRegSrc);
454	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
455
456	iemNativeVarRegisterRelease(pReNative, idxVarSrc);
457	iemNativeVarRegisterRelease(pReNative, idxVarDst);
458
459	off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl);
460
461	#elif defined(RT_ARCH_ARM64)
462	/* On ARM64 we'll need the two input operands as well as the result in order
463	to calculate the right flags, even if we use SUBS and translates NZCV into
464	OF, CF, ZF and SF. */
465	uint8_t const idxRegDstIn = iemNativeRegAllocTmp(pReNative, &off);
466	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 4);
467	if (cOpBits >= 32)
468	{
469	off = iemNativeEmitLoadGprFromGprEx(pCodeBuf, off, idxRegDstIn, idxRegDst);
470	pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegDst, idxRegDst, idxRegSrc, cOpBits > 32 /f64Bit/, true /fSetFlags/);
471	}
472	else
473	{
474	/* Shift the operands up so we can perform a 32-bit operation and get all four flags. */
475	uint32_t const cShift = 32 - cOpBits;
476	pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegDstIn, ARMV8_A64_REG_XZR, idxRegDst, false /f64Bit/, cShift);
477	pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegDst, idxRegDstIn, idxRegSrc, cOpBits > 32 /f64Bit/,
478	true /fSetFlags/, cShift);
479	pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegDstIn, idxRegDstIn, cShift, false /f64Bit/);
480	pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegDst, idxRegDst, cShift, false /f64Bit/);
481	cOpBits = 32;
482	}
483	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
484
485	off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl, cOpBits, idxRegDst,
486	idxRegDstIn, idxRegSrc, true /fNativeFlags/);
487
488	iemNativeRegFreeTmp(pReNative, idxRegDstIn);
489	iemNativeVarRegisterRelease(pReNative, idxVarSrc);
490	iemNativeVarRegisterRelease(pReNative, idxVarDst);
491
492	#else
493	# error "port me"
494	#endif
495	return off;
496	}
497
498
499	DECL_INLINE_THROW(uint32_t)
500	iemNativeEmit_cmp_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
501	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
502	{
503	/*
504	* The SUB instruction will set all flags.
505	*/
506	uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /fInitialized/);
507	uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /fInitialized/);
508
509	#ifdef RT_ARCH_AMD64
510	/* On AMD64 we just use the correctly sized CMP instruction to get the right EFLAGS.SF value. */
511	off = iemNativeEmitAmd64ModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
512	0x3a, 0x3b, cOpBits, idxRegDst, idxRegSrc);
513	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
514
515	iemNativeVarRegisterRelease(pReNative, idxVarSrc);
516	iemNativeVarRegisterRelease(pReNative, idxVarDst);
517
518	off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl);
519
520	#elif defined(RT_ARCH_ARM64)
521	/* On ARM64 we'll need the actual result as well as both input operands in order
522	to calculate the right flags, even if we use SUBS and translates NZCV into
523	OF, CF, ZF and SF. */
524	uint8_t const idxRegResult = iemNativeRegAllocTmp(pReNative, &off);
525	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
526	if (cOpBits >= 32)
527	pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegResult, idxRegDst, idxRegSrc, cOpBits > 32 /f64Bit/, true /fSetFlags/);
528	else
529	{
530	/* Shift the operands up so we can perform a 32-bit operation and get all four flags. */
531	uint32_t const cShift = 32 - cOpBits;
532	pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegResult, ARMV8_A64_REG_XZR, idxRegDst, false /f64Bit/, cShift);
533	pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegResult, idxRegResult, idxRegSrc, cOpBits > 32 /f64Bit/,
534	true /fSetFlags/, cShift);
535	pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegResult, idxRegResult, cShift, false /f64Bit/);
536	cOpBits = 32;
537	}
538	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
539
540	off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl, cOpBits, idxRegResult,
541	idxRegDst, idxRegSrc, true /fNativeFlags/);
542
543	iemNativeRegFreeTmp(pReNative, idxRegResult);
544	iemNativeVarRegisterRelease(pReNative, idxVarSrc);
545	iemNativeVarRegisterRelease(pReNative, idxVarDst);
546
547	#else
548	# error "port me"
549	#endif
550	return off;
551	}
552
553
554	DECL_INLINE_THROW(uint32_t)
555	iemNativeEmit_sbb_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
556	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
557	{
558	RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
559	AssertFailed();
560	return iemNativeEmitBrk(pReNative, off, 0x666);
561	}
562
563
564	DECL_INLINE_THROW(uint32_t)
565	iemNativeEmit_imul_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
566	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
567	{
568	RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
569	AssertFailed();
570	return iemNativeEmitBrk(pReNative, off, 0x666);
571	}
572
573
574	DECL_INLINE_THROW(uint32_t)
575	iemNativeEmit_popcnt_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
576	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
577	{
578	RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
579	AssertFailed();
580	return iemNativeEmitBrk(pReNative, off, 0x666);
581	}
582
583
584	DECL_INLINE_THROW(uint32_t)
585	iemNativeEmit_tzcnt_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
586	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
587	{
588	RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
589	AssertFailed();
590	return iemNativeEmitBrk(pReNative, off, 0x666);
591	}
592
593
594	DECL_INLINE_THROW(uint32_t)
595	iemNativeEmit_lzcnt_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
596	uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
597	{
598	RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
599	AssertFailed();
600	return iemNativeEmitBrk(pReNative, off, 0x666);
601	}
602
603
604	#endif /* !VMM_INCLUDED_SRC_VMMAll_target_x86_IEMAllN8veEmit_x86_h */

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source: vbox/trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h@ 103682

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