IEMAllThrdFuncs-x86.cpp@ 108226

Last change on this file since 108226 was 108204, checked in by vboxsync, 3 months ago
VMM/IEM: Moving x86 target specific files to VMMAll/target-x86/... jiraref:VBP-1531
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 49.7 KB

Line
1	/* $Id: IEMAllThrdFuncs-x86.cpp 108204 2025-02-13 16:26:48Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, Threaded Functions, x86 target.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#ifndef LOG_GROUP /* defined when included by tstIEMCheckMc.cpp */
33	# define LOG_GROUP LOG_GROUP_IEM
34	#endif
35	#define VMCPU_INCL_CPUM_GST_CTX
36	#define IEM_WITH_OPAQUE_DECODER_STATE
37	#ifdef IN_RING0
38	# define VBOX_VMM_TARGET_X86
39	#endif
40	#include <VBox/vmm/iem.h>
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/pdmapic.h>
43	#include <VBox/vmm/pdm.h>
44	#include <VBox/vmm/pgm.h>
45	#include <VBox/vmm/iom.h>
46	#include <VBox/vmm/em.h>
47	#include <VBox/vmm/hm.h>
48	#include <VBox/vmm/nem.h>
49	#include <VBox/vmm/gim.h>
50	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
51	# include <VBox/vmm/em.h>
52	# include <VBox/vmm/hm_svm.h>
53	#endif
54	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
55	# include <VBox/vmm/hmvmxinline.h>
56	#endif
57	#include <VBox/vmm/tm.h>
58	#include <VBox/vmm/dbgf.h>
59	#include <VBox/vmm/dbgftrace.h>
60	#include "IEMInternal.h"
61	#include <VBox/vmm/vmcc.h>
62	#include <VBox/log.h>
63	#include <VBox/err.h>
64	#include <VBox/param.h>
65	#include <VBox/dis.h>
66	#include <VBox/disopcode-x86-amd64.h>
67	#include <iprt/asm-math.h>
68	#include <iprt/assert.h>
69	#include <iprt/string.h>
70	#include <iprt/x86.h>
71
72	#include "IEMInline.h"
73	#include "IEMMc.h"
74
75	#include "IEMThreadedFunctions.h"
76
77
78	/*********************************************************************************************************************************
79	* Defined Constants And Macros *
80	*********************************************************************************************************************************/
81
82	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
83	* and only used when we're in 16-bit code on a pre-386 CPU. */
84	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16(a_cbInstr, a_rcNormal) \
85	return iemRegAddToIp16AndFinishingNoFlags(pVCpu, a_cbInstr, a_rcNormal)
86
87	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
88	* and used for 16-bit and 32-bit code on 386 and later CPUs. */
89	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32(a_cbInstr, a_rcNormal) \
90	return iemRegAddToEip32AndFinishingNoFlags(pVCpu, a_cbInstr, a_rcNormal)
91
92	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
93	* and only used when we're in 64-bit code. */
94	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64(a_cbInstr, a_rcNormal) \
95	return iemRegAddToRip64AndFinishingNoFlags(pVCpu, a_cbInstr, a_rcNormal)
96
97
98	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
99	* and only used when we're in 16-bit code on a pre-386 CPU and we need to
100	* check and clear flags. */
101	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_cbInstr, a_rcNormal) \
102	return iemRegAddToIp16AndFinishingClearingRF(pVCpu, a_cbInstr, a_rcNormal)
103
104	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
105	* and used for 16-bit and 32-bit code on 386 and later CPUs and we need to
106	* check and clear flags. */
107	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_cbInstr, a_rcNormal) \
108	return iemRegAddToEip32AndFinishingClearingRF(pVCpu, a_cbInstr, a_rcNormal)
109
110	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
111	* and only used when we're in 64-bit code and we need to check and clear
112	* flags. */
113	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_cbInstr, a_rcNormal) \
114	return iemRegAddToRip64AndFinishingClearingRF(pVCpu, a_cbInstr, a_rcNormal)
115
116	#undef IEM_MC_ADVANCE_RIP_AND_FINISH
117
118
119	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length as extra
120	* parameter, for use in 16-bit code on a pre-386 CPU. */
121	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16(a_i8, a_cbInstr, a_rcNormal) \
122	return iemRegIp16RelativeJumpS8AndFinishNoFlags(pVCpu, a_cbInstr, (a_i8), a_rcNormal)
123
124	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
125	* size as extra parameters, for use in 16-bit and 32-bit code on 386 and
126	* later CPUs. */
127	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
128	return iemRegEip32RelativeJumpS8AndFinishNoFlags(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize, a_rcNormal)
129
130	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
131	* size as extra parameters, for use in flat 32-bit code on 386 and later
132	* CPUs. */
133	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32_FLAT(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
134	return iemRegEip32RelativeJumpS8FlatAndFinishNoFlags(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize, a_rcNormal)
135
136	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
137	* size as extra parameters, for use in 64-bit code. */
138	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
139	return iemRegRip64RelativeJumpS8AndFinishNoFlags(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize, a_rcNormal)
140
141	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
142	* size as extra parameters, for use in 64-bit code jumping within a page. */
143	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64_INTRAPG(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
144	return iemRegRip64RelativeJumpS8IntraPgAndFinishNoFlags(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize, a_rcNormal)
145
146
147	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length as extra
148	* parameter, for use in 16-bit code on a pre-386 CPU and we need to check and
149	* clear flags. */
150	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i8, a_cbInstr, a_rcNormal) \
151	return iemRegIp16RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_rcNormal)
152
153	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
154	* size as extra parameters, for use in 16-bit and 32-bit code on 386 and
155	* later CPUs and we need to check and clear flags. */
156	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
157	return iemRegEip32RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize, a_rcNormal)
158
159	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
160	* size as extra parameters, for use in flat 32-bit code on 386 and later
161	* CPUs and we need to check and clear flags. */
162	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32_FLAT_WITH_FLAGS(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
163	return iemRegEip32RelativeJumpS8FlatAndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize, a_rcNormal)
164
165	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
166	* size as extra parameters, for use in 64-bit code and we need to check and
167	* clear flags. */
168	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
169	return iemRegRip64RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize, a_rcNormal)
170
171	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
172	* size as extra parameters, for use in 64-bit code jumping within a page and we
173	* need to check and clear flags. */
174	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64_INTRAPG_WITH_FLAGS(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
175	return iemRegRip64RelativeJumpS8IntraPgAndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize, a_rcNormal)
176
177	#undef IEM_MC_REL_JMP_S8_AND_FINISH
178
179
180	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
181	* param, for use in 16-bit code on a pre-386 CPU. */
182	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16(a_i16, a_cbInstr, a_rcNormal) \
183	return iemRegEip32RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
184
185	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
186	* param, for use in 16-bit and 32-bit code on 386 and later CPUs. */
187	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32(a_i16, a_cbInstr, a_rcNormal) \
188	return iemRegEip32RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
189
190	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
191	* param, for use in flat 32-bit code on 386 and later CPUs. */
192	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32_FLAT(a_i16, a_cbInstr, a_rcNormal) \
193	return iemRegEip32RelativeJumpS16FlatAndFinishNoFlags(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
194
195	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
196	* param, for use in 64-bit code. */
197	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64(a_i16, a_cbInstr, a_rcNormal) \
198	return iemRegRip64RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
199
200	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
201	* param, for use in 64-bit code jumping with a page.
202	* @note No special function for this, there is nothing to save here. */
203	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64_INTRAPG(a_i16, a_cbInstr, a_rcNormal) \
204	return iemRegRip64RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
205
206
207	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
208	* param, for use in 16-bit code on a pre-386 CPU and we need to check and
209	* clear flags. */
210	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i16, a_cbInstr, a_rcNormal) \
211	return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
212
213	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
214	* param, for use in 16-bit and 32-bit code on 386 and later CPUs and we need
215	* to check and clear flags. */
216	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i16, a_cbInstr, a_rcNormal) \
217	return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
218
219	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
220	* param, for use in flat 32-bit code on 386 and later CPUs and we need
221	* to check and clear flags. */
222	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32_FLAT_WITH_FLAGS(a_i16, a_cbInstr, a_rcNormal) \
223	return iemRegEip32RelativeJumpS16FlatAndFinishClearingRF(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
224
225	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
226	* param, for use in 64-bit code and we need to check and clear flags. */
227	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i16, a_cbInstr, a_rcNormal) \
228	return iemRegRip64RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
229
230	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
231	* param, for use in 64-bit code jumping within a page and we need to check and
232	* clear flags.
233	* @note No special function for this, there is nothing to save here. */
234	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64_INTRAPG_WITH_FLAGS(a_i16, a_cbInstr, a_rcNormal) \
235	return iemRegRip64RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16), a_rcNormal)
236
237	#undef IEM_MC_REL_JMP_S16_AND_FINISH
238
239
240	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
241	* an extra parameter - dummy for pre-386 variations not eliminated by the
242	* python script. */
243	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC16(a_i32, a_cbInstr, a_rcNormal) \
244	do { RT_NOREF(pVCpu, a_i32, a_cbInstr, a_rcNormal); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
245
246	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
247	* an extra parameter, for use in 16-bit and 32-bit code on 386+. */
248	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32(a_i32, a_cbInstr, a_rcNormal) \
249	return iemRegEip32RelativeJumpS32AndFinishNoFlags(pVCpu, a_cbInstr, (a_i32), a_rcNormal)
250
251	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
252	* an extra parameter, for use in flat 32-bit code on 386+. */
253	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32_FLAT(a_i32, a_cbInstr, a_rcNormal) \
254	return iemRegEip32RelativeJumpS32FlatAndFinishNoFlags(pVCpu, a_cbInstr, (a_i32), a_rcNormal)
255
256	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
257	* an extra parameter, for use in 64-bit code. */
258	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64(a_i32, a_cbInstr, a_rcNormal) \
259	return iemRegRip64RelativeJumpS32AndFinishNoFlags(pVCpu, a_cbInstr, (a_i32), a_rcNormal)
260
261	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
262	* an extra parameter, for use in 64-bit code jumping within a page. */
263	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64_INTRAPG(a_i32, a_cbInstr, a_rcNormal) \
264	return iemRegRip64RelativeJumpS32IntraPgAndFinishNoFlags(pVCpu, a_cbInstr, (a_i32), a_rcNormal)
265
266
267	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
268	* an extra parameter - dummy for pre-386 variations not eliminated by the
269	* python script. */
270	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i32, a_cbInstr, a_rcNormal) \
271	do { RT_NOREF(pVCpu, a_i32, a_cbInstr, a_rcNormal); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
272
273	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
274	* an extra parameter, for use in 16-bit and 32-bit code on 386+ and we need
275	* to check and clear flags. */
276	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i32, a_cbInstr, a_rcNormal) \
277	return iemRegEip32RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32), a_rcNormal)
278
279	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
280	* an extra parameter, for use in flat 32-bit code on 386+ and we need
281	* to check and clear flags. */
282	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32_FLAT_WITH_FLAGS(a_i32, a_cbInstr, a_rcNormal) \
283	return iemRegEip32RelativeJumpS32FlatAndFinishClearingRF(pVCpu, a_cbInstr, (a_i32), a_rcNormal)
284
285	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
286	* an extra parameter, for use in 64-bit code and we need to check and clear
287	* flags. */
288	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i32, a_cbInstr, a_rcNormal) \
289	return iemRegRip64RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32), a_rcNormal)
290
291	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
292	* an extra parameter, for use in 64-bit code jumping within a page and we need
293	* to check and clear flags. */
294	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64_INTRAPG_WITH_FLAGS(a_i32, a_cbInstr, a_rcNormal) \
295	return iemRegRip64RelativeJumpS32IntraPgAndFinishClearingRF(pVCpu, a_cbInstr, (a_i32), a_rcNormal)
296
297	#undef IEM_MC_REL_JMP_S32_AND_FINISH
298
299
300
301	/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for pre-386 targets. */
302	#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC16(a_u16NewIP) \
303	return iemRegRipJumpU16AndFinishNoFlags((pVCpu), (a_u16NewIP))
304
305	/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for 386+ targets. */
306	#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC32(a_u16NewIP) \
307	return iemRegRipJumpU16AndFinishNoFlags((pVCpu), (a_u16NewIP))
308
309	/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for use in 64-bit code. */
310	#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC64(a_u16NewIP) \
311	return iemRegRipJumpU16AndFinishNoFlags((pVCpu), (a_u16NewIP))
312
313	/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for pre-386 targets that checks and
314	* clears flags. */
315	#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_u16NewIP) \
316	return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP), 0 /* cbInstr - not used */)
317
318	/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for 386+ targets that checks and
319	* clears flags. */
320	#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_u16NewIP) \
321	return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP), 0 /* cbInstr - not used */)
322
323	/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for use in 64-bit code that checks and
324	* clears flags. */
325	#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u16NewIP) \
326	return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP), 0 /* cbInstr - not used */)
327
328	#undef IEM_MC_SET_RIP_U16_AND_FINISH
329
330
331	/** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for 386+ targets. */
332	#define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC32(a_u32NewEIP) \
333	return iemRegRipJumpU32AndFinishNoFlags((pVCpu), (a_u32NewEIP))
334
335	/** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for use in 64-bit code. */
336	#define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC64(a_u32NewEIP) \
337	return iemRegRipJumpU32AndFinishNoFlags((pVCpu), (a_u32NewEIP))
338
339	/** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for 386+ targets that checks and
340	* clears flags. */
341	#define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_u32NewEIP) \
342	return iemRegRipJumpU32AndFinishClearingRF((pVCpu), (a_u32NewEIP), 0 /* cbInstr - not used */)
343
344	/** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for use in 64-bit code that checks
345	* and clears flags. */
346	#define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u32NewEIP) \
347	return iemRegRipJumpU32AndFinishClearingRF((pVCpu), (a_u32NewEIP), 0 /* cbInstr - not used */)
348
349	#undef IEM_MC_SET_RIP_U32_AND_FINISH
350
351
352	/** Variant of IEM_MC_SET_RIP_U64_AND_FINISH for use in 64-bit code. */
353	#define IEM_MC_SET_RIP_U64_AND_FINISH_THREADED_PC64(a_u32NewEIP) \
354	return iemRegRipJumpU64AndFinishNoFlags((pVCpu), (a_u32NewEIP))
355
356	/** Variant of IEM_MC_SET_RIP_U64_AND_FINISH for use in 64-bit code that checks
357	* and clears flags. */
358	#define IEM_MC_SET_RIP_U64_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u32NewEIP) \
359	return iemRegRipJumpU64AndFinishClearingRF((pVCpu), (a_u32NewEIP), 0 /* cbInstr - not used */)
360
361	#undef IEM_MC_SET_RIP_U64_AND_FINISH
362
363
364	/** Variant of IEM_MC_REL_CALL_S16_AND_FINISH with instruction length as
365	* param, for use in 16-bit code on a pre-386 CPU. */
366	#define IEM_MC_REL_CALL_S16_AND_FINISH_THREADED_PC16(a_i16, a_cbInstr) \
367	return iemRegRipRelativeCallS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16))
368
369	/** Variant of IEM_MC_REL_CALL_S16_AND_FINISH with instruction length as
370	* param, for use in 16-bit and 32-bit code on 386 and later CPUs. */
371	#define IEM_MC_REL_CALL_S16_AND_FINISH_THREADED_PC32(a_i16, a_cbInstr) \
372	return iemRegRipRelativeCallS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16))
373
374	/** Variant of IEM_MC_REL_CALL_S16_AND_FINISH with instruction length as
375	* param, for use in 64-bit code. */
376	#define IEM_MC_REL_CALL_S16_AND_FINISH_THREADED_PC64(a_i16, a_cbInstr) \
377	return iemRegRipRelativeCallS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16))
378
379
380	/** Variant of IEM_MC_REL_CALL_S16_AND_FINISH with instruction length as
381	* param, for use in 16-bit code on a pre-386 CPU and we need to check and
382	* clear flags. */
383	#define IEM_MC_REL_CALL_S16_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i16, a_cbInstr) \
384	return iemRegRipRelativeCallS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
385
386	/** Variant of IEM_MC_REL_CALL_S16_AND_FINISH with instruction length as
387	* param, for use in 16-bit and 32-bit code on 386 and later CPUs and we need
388	* to check and clear flags. */
389	#define IEM_MC_REL_CALL_S16_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i16, a_cbInstr) \
390	return iemRegRipRelativeCallS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
391
392	/** Variant of IEM_MC_REL_CALL_S16_AND_FINISH with instruction length as
393	* param, for use in 64-bit code and we need to check and clear flags. */
394	#define IEM_MC_REL_CALL_S16_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i16, a_cbInstr) \
395	return iemRegRipRelativeCallS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
396
397	#undef IEM_MC_REL_CALL_S16_AND_FINISH
398
399
400	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
401	* an extra parameter - dummy for pre-386 variations not eliminated by the
402	* python script. */
403	#define IEM_MC_REL_CALL_S32_AND_FINISH_THREADED_PC16(a_i32, a_cbInstr) \
404	do { RT_NOREF(pVCpu, a_i32, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
405
406	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
407	* an extra parameter, for use in 16-bit and 32-bit code on 386+. */
408	#define IEM_MC_REL_CALL_S32_AND_FINISH_THREADED_PC32(a_i32, a_cbInstr) \
409	return iemRegEip32RelativeCallS32AndFinishNoFlags(pVCpu, a_cbInstr, (a_i32))
410
411	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
412	* an extra parameter, for use in 64-bit code on 386+. */
413	#define IEM_MC_REL_CALL_S32_AND_FINISH_THREADED_PC64(a_i32, a_cbInstr) \
414	do { RT_NOREF(pVCpu, a_i32, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
415
416	/** Variant of IEM_MC_REL_CALL_S32_AND_FINISH with instruction length as
417	* an extra parameter - dummy for pre-386 variations not eliminated by the
418	* python script. */
419	#define IEM_MC_REL_CALL_S32_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i32, a_cbInstr) \
420	do { RT_NOREF(pVCpu, a_i32, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
421
422	/** Variant of IEM_MC_REL_CALL_S32_AND_FINISH with instruction length as
423	* an extra parameter, for use in 16-bit and 32-bit code on 386+ and we need
424	* to check and clear flags. */
425	#define IEM_MC_REL_CALL_S32_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i32, a_cbInstr) \
426	return iemRegEip32RelativeCallS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32))
427
428	/** Variant of IEM_MC_REL_CALL_S32_AND_FINISH with instruction length as
429	* an extra parameter, for use in 64-bit code on 386+ and we need
430	* to check and clear flags - dummy for variations not eliminated by the python script. */
431	#define IEM_MC_REL_CALL_S32_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i32, a_cbInstr) \
432	do { RT_NOREF(pVCpu, a_i32, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
433
434
435	#undef IEM_MC_REL_CALL_S32_AND_FINISH
436
437
438	/** Variant of IEM_MC_REL_CALL_S64_AND_FINISH with instruction length as
439	* an extra parameter, for use in 32-bit code. */
440	#define IEM_MC_REL_CALL_S64_AND_FINISH_THREADED_PC32(a_i64, a_cbInstr) \
441	do { RT_NOREF(pVCpu, a_i64, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
442
443	/** Variant of IEM_MC_REL_CALL_S64_AND_FINISH with instruction length as
444	* an extra parameter, for use in 64-bit code. */
445	#define IEM_MC_REL_CALL_S64_AND_FINISH_THREADED_PC64(a_i64, a_cbInstr) \
446	return iemRegRip64RelativeCallS64AndFinishNoFlags(pVCpu, a_cbInstr, (a_i64))
447
448
449	/** Variant of IEM_MC_REL_CALL_S64_AND_FINISH with instruction length as
450	* an extra parameter, for use in 16-bit and 32-bit code on 386+ and we need
451	* to check and clear flags - dummy for variations not eliminated by the python script. */
452	#define IEM_MC_REL_CALL_S64_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i64, a_cbInstr) \
453	do { RT_NOREF(pVCpu, a_i64, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
454
455	/** Variant of IEM_MC_REL_CALL_S64_AND_FINISH with instruction length as
456	* an extra parameter, for use in 64-bit code and we need to check and clear
457	* flags. */
458	#define IEM_MC_REL_CALL_S64_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i64, a_cbInstr) \
459	return iemRegRip64RelativeCallS64AndFinishClearingRF(pVCpu, a_cbInstr, (a_i64))
460
461	#undef IEM_MC_REL_CALL_S64_AND_FINISH
462
463
464	/** Variant of IEM_MC_IND_CALL_U16_AND_FINISH for pre-386 targets. */
465	#define IEM_MC_IND_CALL_U16_AND_FINISH_THREADED_PC16(a_u16NewIP, a_cbInstr) \
466	return iemRegIp16IndirectCallU16AndFinishNoFlags((pVCpu), a_cbInstr, (a_u16NewIP))
467
468	/** Variant of IEM_MC_IND_CALL_U16_AND_FINISH for 386+ targets. */
469	#define IEM_MC_IND_CALL_U16_AND_FINISH_THREADED_PC32(a_u16NewIP, a_cbInstr) \
470	return iemRegEip32IndirectCallU16AndFinishNoFlags((pVCpu), a_cbInstr, (a_u16NewIP))
471
472	/** Variant of IEM_MC_IND_CALL_U16_AND_FINISH for use in 64-bit code. */
473	#define IEM_MC_IND_CALL_U16_AND_FINISH_THREADED_PC64(a_u16NewIP, a_cbInstr) \
474	do { RT_NOREF(pVCpu, a_u16NewIP, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
475
476	/** Variant of IEM_MC_IND_CALL_U16_AND_FINISH for pre-386 targets that checks and
477	* clears flags. */
478	#define IEM_MC_IND_CALL_U16_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_u16NewIP, a_cbInstr) \
479	return iemRegIp16IndirectCallU16AndFinishClearingRF((pVCpu), a_cbInstr, (a_u16NewIP))
480
481	/** Variant of IEM_MC_IND_CALL_U16_AND_FINISH for 386+ targets that checks and
482	* clears flags. */
483	#define IEM_MC_IND_CALL_U16_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_u16NewIP, a_cbInstr) \
484	return iemRegEip32IndirectCallU16AndFinishClearingRF((pVCpu), a_cbInstr, (a_u16NewIP))
485
486	/** Variant of IEM_MC_IND_CALL_U16_AND_FINISH for use in 64-bit code that checks and
487	* clears flags. */
488	#define IEM_MC_IND_CALL_U16_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u16NewIP, a_cbInstr) \
489	do { RT_NOREF(pVCpu, a_u16NewIP, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
490
491	#undef IEM_MC_IND_CALL_U16_AND_FINISH
492
493
494	/** Variant of IEM_MC_IND_CALL_U32_AND_FINISH for 386+ targets. */
495	#define IEM_MC_IND_CALL_U32_AND_FINISH_THREADED_PC32(a_u32NewEIP, a_cbInstr) \
496	return iemRegEip32IndirectCallU32AndFinishNoFlags((pVCpu), a_cbInstr, (a_u32NewEIP))
497
498	/** Variant of IEM_MC_IND_CALL_U32_AND_FINISH for use in 64-bit code. */
499	#define IEM_MC_IND_CALL_U32_AND_FINISH_THREADED_PC64(a_u32NewEIP, a_cbInstr) \
500	do { RT_NOREF(pVCpu, a_u32NewEIP, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
501
502	/** Variant of IEM_MC_IND_CALL_U32_AND_FINISH for 386+ targets that checks and
503	* clears flags. */
504	#define IEM_MC_IND_CALL_U32_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_u32NewEIP, a_cbInstr) \
505	return iemRegEip32IndirectCallU32AndFinishClearingRF((pVCpu), a_cbInstr, (a_u32NewEIP))
506
507	/** Variant of IEM_MC_IND_CALL_U32_AND_FINISH for use in 64-bit code that checks
508	* and clears flags. */
509	#define IEM_MC_IND_CALL_U32_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u32NewEIP, a_cbInstr) \
510	do { RT_NOREF(pVCpu, a_u32NewEIP, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
511
512	#undef IEM_MC_IND_CALL_U32_AND_FINISH
513
514
515	/** Variant of IEM_MC_IND_CALL_U64_AND_FINISH for use in 64-bit code. */
516	#define IEM_MC_IND_CALL_U64_AND_FINISH_THREADED_PC64(a_u32NewRIP, a_cbInstr) \
517	return iemRegRip64IndirectCallU64AndFinishNoFlags((pVCpu), a_cbInstr, (a_u32NewRIP))
518
519	/** Variant of IEM_MC_IND_CALL_U64_AND_FINISH for use in 64-bit code that checks
520	* and clears flags. */
521	#define IEM_MC_IND_CALL_U64_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u32NewRIP, a_cbInstr) \
522	return iemRegRip64IndirectCallU64AndFinishClearingRF((pVCpu), a_cbInstr, (a_u32NewRIP))
523
524	#undef IEM_MC_IND_CALL_U64_AND_FINISH
525
526
527	/** Variant of IEM_MC_RETN_AND_FINISH for pre-386 targets. */
528	#define IEM_MC_RETN_AND_FINISH_THREADED_PC16(a_cbPopArgs, a_cbInstr) \
529	return iemRegRipNearReturnAndFinishNoFlags((pVCpu), a_cbInstr, (a_cbPopArgs), IEMMODE_16BIT)
530
531	/** Variant of IEM_MC_RETN_AND_FINISH for 386+ targets. */
532	#define IEM_MC_RETN_AND_FINISH_THREADED_PC32(a_cbPopArgs, a_cbInstr, a_enmEffOpSize) \
533	return iemRegRipNearReturnAndFinishNoFlags((pVCpu), a_cbInstr, (a_cbPopArgs), (a_enmEffOpSize))
534
535	/** Variant of IEM_MC_RETN_AND_FINISH for use in 64-bit code. */
536	#define IEM_MC_RETN_AND_FINISH_THREADED_PC64(a_cbPopArgs, a_cbInstr, a_enmEffOpSize) \
537	return iemRegRipNearReturnAndFinishNoFlags((pVCpu), a_cbInstr, (a_cbPopArgs), (a_enmEffOpSize))
538
539	/** Variant of IEM_MC_RETN_AND_FINISH for pre-386 targets that checks and
540	* clears flags. */
541	#define IEM_MC_RETN_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_cbPopArgs, a_cbInstr) \
542	return iemRegRipNearReturnAndFinishClearingRF((pVCpu), a_cbInstr, (a_cbPopArgs), IEMMODE_16BIT)
543
544	/** Variant of IEM_MC_RETN_AND_FINISH for 386+ targets that checks and
545	* clears flags. */
546	#define IEM_MC_RETN_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_cbPopArgs, a_cbInstr, a_enmEffOpSize) \
547	return iemRegRipNearReturnAndFinishClearingRF((pVCpu), a_cbInstr, (a_cbPopArgs), (a_enmEffOpSize))
548
549	/** Variant of IEM_MC_RETN_AND_FINISH for use in 64-bit code that checks and
550	* clears flags. */
551	#define IEM_MC_RETN_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_cbPopArgs, a_cbInstr, a_enmEffOpSize) \
552	return iemRegRipNearReturnAndFinishClearingRF((pVCpu), a_cbInstr, (a_cbPopArgs), (a_enmEffOpSize))
553
554	#undef IEM_MC_RETN_AND_FINISH
555
556
557	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 16-bit. */
558	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp) \
559	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr16(pVCpu, a_bRm, a_u16Disp)
560
561	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit. */
562	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32(a_GCPtrEff, a_bRm, a_uSibAndRspOffset, a_u32Disp) \
563	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_uSibAndRspOffset, a_u32Disp)
564
565	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
566	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
567	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm)
568
569	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
570	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_FSGS(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
571	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm)
572
573	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters.
574	* @todo How did that address prefix thing work for 64-bit code again? */
575	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_ADDR32(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
576	(a_GCPtrEff) = (uint32_t)iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm)
577
578	#undef IEM_MC_CALC_RM_EFF_ADDR
579
580
581	/** Variant of IEM_MC_CALL_CIMPL_1 with explicit instruction length parameter. */
582	#define IEM_MC_CALL_CIMPL_1_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \
583	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0)
584	#undef IEM_MC_CALL_CIMPL_1
585
586	/** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */
587	#define IEM_MC_CALL_CIMPL_2_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \
588	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1)
589	#undef IEM_MC_CALL_CIMPL_2
590
591	/** Variant of IEM_MC_CALL_CIMPL_3 with explicit instruction length parameter. */
592	#define IEM_MC_CALL_CIMPL_3_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \
593	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2)
594	#undef IEM_MC_CALL_CIMPL_3
595
596	/** Variant of IEM_MC_CALL_CIMPL_4 with explicit instruction length parameter. */
597	#define IEM_MC_CALL_CIMPL_4_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3) \
598	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3)
599	#undef IEM_MC_CALL_CIMPL_4
600
601	/** Variant of IEM_MC_CALL_CIMPL_5 with explicit instruction length parameter. */
602	#define IEM_MC_CALL_CIMPL_5_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3, a4) \
603	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4)
604	#undef IEM_MC_CALL_CIMPL_5
605
606
607	/** Variant of IEM_MC_DEFER_TO_CIMPL_0_RET with explicit instruction
608	* length parameter. */
609	#define IEM_MC_DEFER_TO_CIMPL_0_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl) \
610	return (a_pfnCImpl)(pVCpu, (a_cbInstr))
611	#undef IEM_MC_DEFER_TO_CIMPL_0_RET
612
613	/** Variant of IEM_MC_DEFER_TO_CIMPL_1_RET with explicit instruction
614	* length parameter. */
615	#define IEM_MC_DEFER_TO_CIMPL_1_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \
616	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0)
617	#undef IEM_MC_DEFER_TO_CIMPL_1_RET
618
619	/** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */
620	#define IEM_MC_DEFER_TO_CIMPL_2_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \
621	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1)
622	#undef IEM_MC_DEFER_TO_CIMPL_2_RET
623
624	/** Variant of IEM_MC_DEFER_TO_CIMPL_3 with explicit instruction length
625	* parameter. */
626	#define IEM_MC_DEFER_TO_CIMPL_3_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \
627	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2)
628	#undef IEM_MC_DEFER_TO_CIMPL_3_RET
629
630	/** Variant of IEM_MC_DEFER_TO_CIMPL_4 with explicit instruction length
631	* parameter. */
632	#define IEM_MC_DEFER_TO_CIMPL_4_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3) \
633	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3)
634	#undef IEM_MC_DEFER_TO_CIMPL_4_RET
635
636	/** Variant of IEM_MC_DEFER_TO_CIMPL_5 with explicit instruction length
637	* parameter. */
638	#define IEM_MC_DEFER_TO_CIMPL_5_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3, a4) \
639	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4)
640	#undef IEM_MC_DEFER_TO_CIMPL_5_RET
641
642
643	/** Variant of IEM_MC_FETCH_GREG_U8 with extended (20) register index. */
644	#define IEM_MC_FETCH_GREG_U8_THREADED(a_u8Dst, a_iGRegEx) \
645	(a_u8Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
646
647	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U16 with extended (20) register index. */
648	#define IEM_MC_FETCH_GREG_U8_ZX_U16_THREADED(a_u16Dst, a_iGRegEx) \
649	(a_u16Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
650
651	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U32 with extended (20) register index. */
652	#define IEM_MC_FETCH_GREG_U8_ZX_U32_THREADED(a_u32Dst, a_iGRegEx) \
653	(a_u32Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
654
655	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U64 with extended (20) register index. */
656	#define IEM_MC_FETCH_GREG_U8_ZX_U64_THREADED(a_u64Dst, a_iGRegEx) \
657	(a_u64Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
658
659	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U16 with extended (20) register index. */
660	#define IEM_MC_FETCH_GREG_U8_SX_U16_THREADED(a_u16Dst, a_iGRegEx) \
661	(a_u16Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
662
663	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U32 with extended (20) register index. */
664	#define IEM_MC_FETCH_GREG_U8_SX_U32_THREADED(a_u32Dst, a_iGRegEx) \
665	(a_u32Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
666	#undef IEM_MC_FETCH_GREG_U8_SX_U32
667
668	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U64 with extended (20) register index. */
669	#define IEM_MC_FETCH_GREG_U8_SX_U64_THREADED(a_u64Dst, a_iGRegEx) \
670	(a_u64Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
671	#undef IEM_MC_FETCH_GREG_U8_SX_U64
672
673	/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
674	#define IEM_MC_STORE_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
675	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
676	#undef IEM_MC_STORE_GREG_U8
677
678	/** Variant of IEM_MC_STORE_GREG_U8_CONST with extended (20) register index. */
679	#define IEM_MC_STORE_GREG_U8_CONST_THREADED(a_iGRegEx, a_u8Value) \
680	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
681	#undef IEM_MC_STORE_GREG_U8
682
683	/** Variant of IEM_MC_REF_GREG_U8 with extended (20) register index. */
684	#define IEM_MC_REF_GREG_U8_THREADED(a_pu8Dst, a_iGRegEx) \
685	(a_pu8Dst) = iemGRegRefU8Ex(pVCpu, (a_iGRegEx))
686	#undef IEM_MC_REF_GREG_U8
687
688	/** Variant of IEM_MC_REF_GREG_U8_CONST with extended (20) register index. */
689	#define IEM_MC_REF_GREG_U8_CONST_THREADED(a_pu8Dst, a_iGRegEx) \
690	(a_pu8Dst) = iemGRegRefU8Ex(pVCpu, (a_iGRegEx))
691	#undef IEM_MC_REF_GREG_U8
692
693	/** Variant of IEM_MC_ADD_GREG_U8_TO_LOCAL with extended (20) register index. */
694	#define IEM_MC_ADD_GREG_U8_TO_LOCAL_THREADED(a_u8Value, a_iGRegEx) \
695	do { (a_u8Value) += iemGRegFetchU8Ex(pVCpu, (a_iGRegEx)); } while (0)
696	#undef IEM_MC_ADD_GREG_U8_TO_LOCAL
697
698	/** Variant of IEM_MC_AND_GREG_U8 with extended (20) register index. */
699	#define IEM_MC_AND_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
700	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) &= (a_u8Value)
701	#undef IEM_MC_AND_GREG_U8
702
703	/** Variant of IEM_MC_OR_GREG_U8 with extended (20) register index. */
704	#define IEM_MC_OR_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
705	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) \|= (a_u8Value)
706	#undef IEM_MC_OR_GREG_U8
707
708
709	/** For asserting that only declared output flags changed. */
710	#ifndef VBOX_STRICT
711	# define IEM_MC_ASSERT_EFLAGS(a_fEflInput, a_fEflOutput) ((void)0)
712	#else
713	# undef IEM_MC_REF_EFLAGS_EX
714	# define IEM_MC_REF_EFLAGS_EX(a_pEFlags, a_fEflInput, a_fEflOutput) \
715	uint32_t const fEflAssert = pVCpu->cpum.GstCtx.eflags.uBoth; \
716	IEM_MC_REF_EFLAGS(a_pEFlags)
717	# define IEM_MC_ASSERT_EFLAGS(a_fEflInput, a_fEflOutput) \
718	AssertMsg((pVCpu->cpum.GstCtx.eflags.uBoth & ~(a_fEflOutput)) == (fEflAssert & ~(a_fEflOutput)), \
719	("now %#x (%#x), was %#x (%#x) - diff %#x; a_fEflOutput=%#x\n", \
720	(pVCpu->cpum.GstCtx.eflags.uBoth & ~(a_fEflOutput)), pVCpu->cpum.GstCtx.eflags.uBoth, \
721	(fEflAssert & ~(a_fEflOutput)), fEflAssert, \
722	(pVCpu->cpum.GstCtx.eflags.uBoth ^ fEflAssert) & ~(a_fEflOutput), a_fEflOutput))
723	#endif
724
725
726
727	/**
728	* Calculates the effective address of a ModR/M memory operand, 16-bit
729	* addressing variant.
730	*
731	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR16.
732	*
733	* @returns The effective address.
734	* @param pVCpu The cross context virtual CPU structure of the calling thread.
735	* @param bRm The ModRM byte.
736	* @param u16Disp The displacement byte/word, if any.
737	* RIP relative addressing.
738	*/
739	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr16(PVMCPUCC pVCpu, uint8_t bRm, uint16_t u16Disp) RT_NOEXCEPT
740	{
741	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: bRm=%#x u16Disp=%#x\n", bRm, u16Disp));
742	Assert(!IEM_IS_64BIT_CODE(pVCpu));
743
744	/* Handle the disp16 form with no registers first. */
745	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 6)
746	{
747	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16Disp));
748	return u16Disp;
749	}
750
751	/* Get the displacment. */
752	/** @todo we can eliminate this step by making u16Disp have this value
753	* already! */
754	uint16_t u16EffAddr;
755	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
756	{
757	case 0: u16EffAddr = 0; break;
758	case 1: u16EffAddr = (int16_t)(int8_t)u16Disp; break;
759	case 2: u16EffAddr = u16Disp; break;
760	default: AssertFailedStmt(u16EffAddr = 0);
761	}
762
763	/* Add the base and index registers to the disp. */
764	switch (bRm & X86_MODRM_RM_MASK)
765	{
766	case 0: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.si; break;
767	case 1: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.di; break;
768	case 2: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.si; break;
769	case 3: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.di; break;
770	case 4: u16EffAddr += pVCpu->cpum.GstCtx.si; break;
771	case 5: u16EffAddr += pVCpu->cpum.GstCtx.di; break;
772	case 6: u16EffAddr += pVCpu->cpum.GstCtx.bp; break;
773	case 7: u16EffAddr += pVCpu->cpum.GstCtx.bx; break;
774	}
775
776	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16EffAddr));
777	return u16EffAddr;
778	}
779
780
781	/**
782	* Calculates the effective address of a ModR/M memory operand, 32-bit
783	* addressing variant.
784	*
785	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32 and
786	* IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32FLAT.
787	*
788	* @returns The effective address.
789	* @param pVCpu The cross context virtual CPU structure of the
790	* calling thread.
791	* @param bRm The ModRM byte.
792	* @param uSibAndRspOffset Two parts:
793	* - The first 8 bits make up the SIB byte.
794	* - The next 8 bits are the fixed RSP/ESP offse
795	* in case of a pop [xSP].
796	* @param u32Disp The displacement byte/dword, if any.
797	*/
798	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr32(PVMCPUCC pVCpu, uint8_t bRm, uint32_t uSibAndRspOffset,
799	uint32_t u32Disp) RT_NOEXCEPT
800	{
801	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: bRm=%#x uSibAndRspOffset=%#x u32Disp=%#x\n", bRm, uSibAndRspOffset, u32Disp));
802
803	/* Handle the disp32 form with no registers first. */
804	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
805	{
806	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32Disp));
807	return u32Disp;
808	}
809
810	/* Get the register (or SIB) value. */
811	uint32_t u32EffAddr;
812	#ifdef _MSC_VER
813	u32EffAddr = 0;/* MSC uninitialized variable analysis is too simple, it seems. */
814	#endif
815	switch (bRm & X86_MODRM_RM_MASK)
816	{
817	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
818	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
819	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
820	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
821	case 4: /* SIB */
822	{
823	/* Get the index and scale it. */
824	switch ((uSibAndRspOffset >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
825	{
826	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
827	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
828	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
829	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
830	case 4: u32EffAddr = 0; /none / break;
831	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
832	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
833	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
834	}
835	u32EffAddr <<= (uSibAndRspOffset >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
836
837	/* add base */
838	switch (uSibAndRspOffset & X86_SIB_BASE_MASK)
839	{
840	case 0: u32EffAddr += pVCpu->cpum.GstCtx.eax; break;
841	case 1: u32EffAddr += pVCpu->cpum.GstCtx.ecx; break;
842	case 2: u32EffAddr += pVCpu->cpum.GstCtx.edx; break;
843	case 3: u32EffAddr += pVCpu->cpum.GstCtx.ebx; break;
844	case 4:
845	u32EffAddr += pVCpu->cpum.GstCtx.esp;
846	u32EffAddr += uSibAndRspOffset >> 8;
847	break;
848	case 5:
849	if ((bRm & X86_MODRM_MOD_MASK) != 0)
850	u32EffAddr += pVCpu->cpum.GstCtx.ebp;
851	else
852	u32EffAddr += u32Disp;
853	break;
854	case 6: u32EffAddr += pVCpu->cpum.GstCtx.esi; break;
855	case 7: u32EffAddr += pVCpu->cpum.GstCtx.edi; break;
856	}
857	break;
858	}
859	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
860	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
861	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
862	}
863
864	/* Get and add the displacement. */
865	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
866	{
867	case 0: break;
868	case 1: u32EffAddr += (int8_t)u32Disp; break;
869	case 2: u32EffAddr += u32Disp; break;
870	default: AssertFailed();
871	}
872
873	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32EffAddr));
874	return u32EffAddr;
875	}
876
877
878	/**
879	* Calculates the effective address of a ModR/M memory operand.
880	*
881	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR64.
882	*
883	* @returns The effective address.
884	* @param pVCpu The cross context virtual CPU structure of the
885	* calling thread.
886	* @param bRmEx The ModRM byte but with bit 3 set to REX.B and
887	* bit 4 to REX.X. The two bits are part of the
888	* REG sub-field, which isn't needed in this
889	* function.
890	* @param uSibAndRspOffset Two parts:
891	* - The first 8 bits make up the SIB byte.
892	* - The next 8 bits are the fixed RSP/ESP offset
893	* in case of a pop [xSP].
894	* @param u32Disp The displacement byte/word/dword, if any.
895	* @param cbInstr The size of the fully decoded instruction. Used
896	* for RIP relative addressing.
897	* @todo combine cbInstr and cbImm!
898	*/
899	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr64(PVMCPUCC pVCpu, uint8_t bRmEx, uint32_t uSibAndRspOffset,
900	uint32_t u32Disp, uint8_t cbInstr) RT_NOEXCEPT
901	{
902	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: bRmEx=%#x\n", bRmEx));
903	Assert(IEM_IS_64BIT_CODE(pVCpu));
904
905	uint64_t u64EffAddr;
906
907	/* Handle the rip+disp32 form with no registers first. */
908	if ((bRmEx & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
909	{
910	u64EffAddr = (int32_t)u32Disp;
911	u64EffAddr += pVCpu->cpum.GstCtx.rip + cbInstr;
912	}
913	else
914	{
915	/* Get the register (or SIB) value. */
916	#ifdef _MSC_VER
917	u64EffAddr = 0; /* MSC uninitialized variable analysis is too simple, it seems. */
918	#endif
919	switch (bRmEx & (X86_MODRM_RM_MASK \| 0x8)) /* bRmEx[bit 3] = REX.B */
920	{
921	default:
922	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
923	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
924	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
925	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
926	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
927	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
928	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
929	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
930	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
931	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
932	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
933	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
934	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
935	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
936	/* SIB */
937	case 4:
938	case 12:
939	{
940	/* Get the index and scale it. */
941	switch ( ((uSibAndRspOffset >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
942	\| ((bRmEx & 0x10) >> 1)) /* bRmEx[bit 4] = REX.X */
943	{
944	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
945	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
946	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
947	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
948	case 4: u64EffAddr = 0; /none / break;
949	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
950	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
951	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
952	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
953	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
954	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
955	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
956	case 12: u64EffAddr = pVCpu->cpum.GstCtx.r12; break;
957	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
958	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
959	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
960	}
961	u64EffAddr <<= (uSibAndRspOffset >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
962
963	/* add base */
964	switch ((uSibAndRspOffset & X86_SIB_BASE_MASK) \| (bRmEx & 0x8)) /* bRmEx[bit 3] = REX.B */
965	{
966	case 0: u64EffAddr += pVCpu->cpum.GstCtx.rax; break;
967	case 1: u64EffAddr += pVCpu->cpum.GstCtx.rcx; break;
968	case 2: u64EffAddr += pVCpu->cpum.GstCtx.rdx; break;
969	case 3: u64EffAddr += pVCpu->cpum.GstCtx.rbx; break;
970	case 4:
971	u64EffAddr += pVCpu->cpum.GstCtx.rsp;
972	u64EffAddr += uSibAndRspOffset >> 8;
973	break;
974	case 6: u64EffAddr += pVCpu->cpum.GstCtx.rsi; break;
975	case 7: u64EffAddr += pVCpu->cpum.GstCtx.rdi; break;
976	case 8: u64EffAddr += pVCpu->cpum.GstCtx.r8; break;
977	case 9: u64EffAddr += pVCpu->cpum.GstCtx.r9; break;
978	case 10: u64EffAddr += pVCpu->cpum.GstCtx.r10; break;
979	case 11: u64EffAddr += pVCpu->cpum.GstCtx.r11; break;
980	case 12: u64EffAddr += pVCpu->cpum.GstCtx.r12; break;
981	case 14: u64EffAddr += pVCpu->cpum.GstCtx.r14; break;
982	case 15: u64EffAddr += pVCpu->cpum.GstCtx.r15; break;
983	/* complicated encodings */
984	case 5:
985	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
986	u64EffAddr += pVCpu->cpum.GstCtx.rbp;
987	else
988	u64EffAddr += (int32_t)u32Disp;
989	break;
990	case 13:
991	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
992	u64EffAddr += pVCpu->cpum.GstCtx.r13;
993	else
994	u64EffAddr += (int32_t)u32Disp;
995	break;
996	}
997	break;
998	}
999	}
1000
1001	/* Get and add the displacement. */
1002	switch ((bRmEx >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1003	{
1004	case 0: break;
1005	case 1: u64EffAddr += (int8_t)u32Disp; break;
1006	case 2: u64EffAddr += (int32_t)u32Disp; break;
1007	default: AssertFailed();
1008	}
1009	}
1010
1011	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: EffAddr=%#010RGv\n", u64EffAddr));
1012	return u64EffAddr;
1013	}
1014
1015
1016	/*
1017	* The threaded functions.
1018	*/
1019	#include "IEMThreadedFunctions.cpp.h"
1020

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllThrdFuncs-x86.cpp@ 108226

Download in other formats: