VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/target-x86/IEMMc-x86.h@ 108732

Last change on this file since 108732 was 108312, checked in by vboxsync, 2 months ago

VMM/IEM: Split out the x86 specific MC codes into IEMMc-x86.h. jiraref:VBP-1531
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1/* $Id: IEMMc-x86.h 108312 2025-02-20 15:34:57Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX, x86 target.
4 */
5
6/*
7 * Copyright (C) 2011-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_VMMAll_target_x86_IEMMc_x86_h
29#define VMM_INCLUDED_SRC_VMMAll_target_x86_IEMMc_x86_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros, x86 specifics and overrides.
36 * @{
37 */
38
39/*
40 * We override all the PC updating MCs:
41 */
42
43#undef IEM_MC_ADVANCE_PC_AND_FINISH
44#define IEM_MC_ADVANCE_PC_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
45
46#undef IEM_MC_REL_JMP_S8_AND_FINISH
47#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
48 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
49
50/** @note X86: only usable in 16-bit op size mode. */
51#undef IEM_MC_REL_JMP_S16_AND_FINISH
52#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
53 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
54
55#undef IEM_MC_REL_JMP_S32_AND_FINISH
56#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
57 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
58
59#undef IEM_MC_IND_JMP_U16_AND_FINISH
60#define IEM_MC_IND_JMP_U16_AND_FINISH(a_u16NewIP) \
61 return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP), IEM_GET_INSTR_LEN(pVCpu))
62
63#undef IEM_MC_IND_JMP_U32_AND_FINISH
64#define IEM_MC_IND_JMP_U32_AND_FINISH(a_u32NewIP) \
65 return iemRegRipJumpU32AndFinishClearingRF((pVCpu), (a_u32NewIP), IEM_GET_INSTR_LEN(pVCpu))
66
67#undef IEM_MC_IND_JMP_U64_AND_FINISH
68#define IEM_MC_IND_JMP_U64_AND_FINISH(a_u64NewIP) \
69 return iemRegRipJumpU64AndFinishClearingRF((pVCpu), (a_u64NewIP), IEM_GET_INSTR_LEN(pVCpu))
70
71/** @note only usable in 16-bit op size mode. */
72#undef IEM_MC_REL_CALL_S16_AND_FINISH
73#define IEM_MC_REL_CALL_S16_AND_FINISH(a_i16) \
74 return iemRegRipRelativeCallS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
75
76#undef IEM_MC_REL_CALL_S32_AND_FINISH
77#define IEM_MC_REL_CALL_S32_AND_FINISH(a_i32) \
78 return iemRegEip32RelativeCallS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32))
79
80#undef IEM_MC_REL_CALL_S64_AND_FINISH
81#define IEM_MC_REL_CALL_S64_AND_FINISH(a_i64) \
82 return iemRegRip64RelativeCallS64AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i64))
83
84#undef IEM_MC_IND_CALL_U16_AND_FINISH
85#define IEM_MC_IND_CALL_U16_AND_FINISH(a_u16NewIP) \
86 return iemRegIp16IndirectCallU16AndFinishClearingRF((pVCpu), IEM_GET_INSTR_LEN(pVCpu), (a_u16NewIP))
87
88#undef IEM_MC_IND_CALL_U32_AND_FINISH
89#define IEM_MC_IND_CALL_U32_AND_FINISH(a_u32NewIP) \
90 return iemRegEip32IndirectCallU32AndFinishClearingRF((pVCpu), IEM_GET_INSTR_LEN(pVCpu), (a_u32NewIP))
91
92#undef IEM_MC_IND_CALL_U64_AND_FINISH
93#define IEM_MC_IND_CALL_U64_AND_FINISH(a_u64NewIP) \
94 return iemRegRip64IndirectCallU64AndFinishClearingRF((pVCpu), IEM_GET_INSTR_LEN(pVCpu), (a_u64NewIP))
95
96
97/** Fetches the near return address from the stack, sets RIP and RSP (may trigger
98 * \#GP or \#SS), finishes the instruction and returns. */
99#define IEM_MC_RETN_AND_FINISH(a_cbPopArgs) \
100 return iemRegRipNearReturnAndFinishClearingRF((pVCpu), IEM_GET_INSTR_LEN(pVCpu), (a_cbPopArgs), pVCpu->iem.s.enmEffOpSize)
101
102
103#define IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(a_uVar) \
104 do { \
105 if (RT_LIKELY((a_uVar) != 0)) \
106 { /* probable */ } \
107 else return iemRaiseDivideError(pVCpu); \
108 } while (0)
109#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
110 do { \
111 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)))) \
112 { /* probable */ } \
113 else return iemRaiseDeviceNotAvailable(pVCpu); \
114 } while (0)
115#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
116 do { \
117 if (RT_LIKELY(!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)))) \
118 { /* probable */ } \
119 else return iemRaiseDeviceNotAvailable(pVCpu); \
120 } while (0)
121#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
122 do { \
123 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES))) \
124 { /* probable */ } \
125 else return iemRaiseMathFault(pVCpu); \
126 } while (0)
127#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
128 do { \
129 /* Since none of the bits we compare from XCR0, CR4 and CR0 overlap, it can \
130 be reduced to a single compare branch in the more probably code path. */ \
131 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) \
132 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
133 | (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)) \
134 == (XSAVE_C_YMM | XSAVE_C_SSE | X86_CR4_OSXSAVE))) \
135 { /* probable */ } \
136 else if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
137 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
138 return iemRaiseUndefinedOpcode(pVCpu); \
139 else \
140 return iemRaiseDeviceNotAvailable(pVCpu); \
141 } while (0)
142AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR4_OSXSAVE));
143AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR0_TS));
144AssertCompile(!(X86_CR4_OSXSAVE & X86_CR0_TS));
145#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
146 do { \
147 /* Since the CR4 and CR0 bits doesn't overlap, it can be reduced to a
148 single compare branch in the more probable code path. */ \
149 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
150 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
151 == X86_CR4_OSFXSR)) \
152 { /* likely */ } \
153 else if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
154 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
155 return iemRaiseUndefinedOpcode(pVCpu); \
156 else \
157 return iemRaiseDeviceNotAvailable(pVCpu); \
158 } while (0)
159AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_CR4_OSFXSR));
160#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
161 do { \
162 /* Since the two CR0 bits doesn't overlap with FSW.ES, this can be reduced to a
163 single compare branch in the more probable code path. */ \
164 if (RT_LIKELY(!( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
165 | (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)))) \
166 { /* probable */ } \
167 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
168 return iemRaiseUndefinedOpcode(pVCpu); \
169 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
170 return iemRaiseDeviceNotAvailable(pVCpu); \
171 else \
172 return iemRaiseMathFault(pVCpu); \
173 } while (0)
174AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_FSW_ES));
175/** @todo recomp: this one is slightly problematic as the recompiler doesn't
176 * count the CPL into the TB key. However it is safe enough for now, as
177 * it calls iemRaiseGeneralProtectionFault0 directly so no calls will be
178 * emitted for it. */
179#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
180 do { \
181 if (RT_LIKELY(IEM_GET_CPL(pVCpu) == 0)) { /* probable */ } \
182 else return iemRaiseGeneralProtectionFault0(pVCpu); \
183 } while (0)
184#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
185 do { \
186 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
187 else return iemRaiseGeneralProtectionFault0(pVCpu); \
188 } while (0)
189#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
190 do { \
191 if (RT_LIKELY( ((pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE) | IEM_GET_CPU_MODE(pVCpu)) \
192 == (X86_CR4_FSGSBASE | IEMMODE_64BIT))) \
193 { /* probable */ } \
194 else return iemRaiseUndefinedOpcode(pVCpu); \
195 } while (0)
196AssertCompile(X86_CR4_FSGSBASE > UINT8_MAX);
197#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
198 do { \
199 if (RT_LIKELY(IEM_IS_CANONICAL(a_u64Addr))) { /* likely */ } \
200 else return iemRaiseGeneralProtectionFault0(pVCpu); \
201 } while (0)
202
203
204/** @note IEMAllInstPython.py duplicates the expansion. */
205#define IEM_MC_ARG_EFLAGS(a_Name, a_iArg) uint32_t const a_Name = pVCpu->cpum.GstCtx.eflags.u
206/** @note IEMAllInstPython.py duplicates the expansion. */
207#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
208 uint32_t a_Name = pVCpu->cpum.GstCtx.eflags.u; \
209 uint32_t *a_pName = &a_Name
210/** @note IEMAllInstPython.py duplicates the expansion. */
211#define IEM_MC_LOCAL_EFLAGS(a_Name) uint32_t a_Name = pVCpu->cpum.GstCtx.eflags.u
212#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
213 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
214#define IEM_MC_COMMIT_EFLAGS_EX(a_EFlags, a_fEflInput, a_fEflOutput) do { \
215 AssertMsg((pVCpu->cpum.GstCtx.eflags.u & ~(a_fEflOutput)) == ((a_EFlags) & ~(a_fEflOutput)), \
216 ("eflags.u=%#x (%#x) vs %s=%#x (%#x) - diff %#x (a_fEflOutput=%#x)\n", \
217 pVCpu->cpum.GstCtx.eflags.u & ~(a_fEflOutput), pVCpu->cpum.GstCtx.eflags.u, #a_EFlags, \
218 (a_EFlags) & ~(a_fEflOutput), (a_EFlags), \
219 (pVCpu->cpum.GstCtx.eflags.u & ~(a_fEflOutput)) ^ ((a_EFlags) & ~(a_fEflOutput)), a_fEflOutput)); \
220 pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); \
221 Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); \
222 } while (0)
223#define IEM_MC_COMMIT_EFLAGS_OPT(a_EFlags) IEM_MC_COMMIT_EFLAGS(a_EFlags)
224#define IEM_MC_COMMIT_EFLAGS_OPT_EX(a_EFlags, a_fEflInput, a_fEflOutput) IEM_MC_COMMIT_EFLAGS_EX(a_EFlags, a_fEflInput, a_fEflOutput)
225
226
227#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
228 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
229 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
230 } while (0)
231#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
232 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
233 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
234 } while (0)
235#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
236 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
237 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
238 } while (0)
239/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
240#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
241 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
242 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
243 } while (0)
244#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
245 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
246 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
247 } while (0)
248
249/** @note Not for IOPL or IF testing or modification. */
250#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
251#define IEM_MC_FETCH_EFLAGS_EX(a_EFlags, a_fEflInput, a_fEflOutput) IEM_MC_FETCH_EFLAGS(a_EFlags)
252#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u /* (only LAHF) */
253#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
254#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
255
256#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
257#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
258#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
259#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
260
261/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
262#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
263 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
264 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
265 } while (0)
266#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
267 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
268 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
269 } while (0)
270
271#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
272 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
273
274
275#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
276#define IEM_MC_REF_GREG_U8_CONST(a_pu8Dst, a_iGReg) (a_pu8Dst) = (uint8_t const *)iemGRegRefU8( pVCpu, (a_iGReg))
277#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
278#define IEM_MC_REF_GREG_U16_CONST(a_pu16Dst, a_iGReg) (a_pu16Dst) = (uint16_t const *)iemGRegRefU16(pVCpu, (a_iGReg))
279/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
280 * Use IEM_MC_CLEAR_HIGH_GREG_U64! */
281#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
282#define IEM_MC_REF_GREG_U32_CONST(a_pu32Dst, a_iGReg) (a_pu32Dst) = (uint32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
283#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
284#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
285#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
286#define IEM_MC_REF_GREG_U64_CONST(a_pu64Dst, a_iGReg) (a_pu64Dst) = (uint64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
287#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
288#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
289/** @note Not for IOPL or IF testing or modification.
290 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
291#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
292#define IEM_MC_REF_EFLAGS_EX(a_pEFlags, a_fEflInput, a_fEflOutput) IEM_MC_REF_EFLAGS(a_pEFlags)
293
294/** x86: preserve upper register bits. */
295#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
296
297/** x86: preserve upper register bits. */
298#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u8Const) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u8Const)
299#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
300
301/** x86: preserve upper register bits. */
302#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
303/** x86: preserve upper register bits. */
304#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
305
306/** x86: preserve upper register bits. */
307#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
308/** x86: preserve upper register bits. */
309#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
310
311/** @note Not for IOPL or IF modification. */
312#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
313/** @note Not for IOPL or IF modification. */
314#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
315/** @note Not for IOPL or IF modification. */
316#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
317
318#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
319
320/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
321#define IEM_MC_FPU_TO_MMX_MODE() do { \
322 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
323 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
324 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
325 } while (0)
326
327/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
328#define IEM_MC_FPU_FROM_MMX_MODE() do { \
329 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
330 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
331 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
332 } while (0)
333
334#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
335 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
336#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg, a_iDWord) \
337 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[a_iDWord]; } while (0)
338#define IEM_MC_FETCH_MREG_U16(a_u16Value, a_iMReg, a_iWord) \
339 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au16[a_iWord]; } while (0)
340#define IEM_MC_FETCH_MREG_U8(a_u8Value, a_iMReg, a_iByte) \
341 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au8[a_iByte]; } while (0)
342#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) \
343 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
344 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
345 } while (0)
346#define IEM_MC_STORE_MREG_U32(a_iMReg, a_iDword, a_u32Value) \
347 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[(a_iDword)] = (a_u32Value); \
348 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
349 } while (0)
350#define IEM_MC_STORE_MREG_U16(a_iMReg, a_iWord, a_u16Value) \
351 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au16[(a_iWord)] = (a_u16Value); \
352 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
353 } while (0)
354#define IEM_MC_STORE_MREG_U8(a_iMReg, a_iByte, a_u8Value) \
355 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au8[(a_iByte)] = (a_u8Value); \
356 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
357 } while (0)
358#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) \
359 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
360 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
361 } while (0)
362#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
363 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
364#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
365 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
366#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
367 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
368#define IEM_MC_MODIFIED_MREG(a_iMReg) \
369 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
370#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
371 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
372
373#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
374 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
375 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
376 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
377 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
378 } while (0)
379#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
380 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
381 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
382 } while (0)
383#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
384 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
385 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
386 } while (0)
387#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
388 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
389#define IEM_MC_FETCH_XREG_R64(a_r64Value, a_iXReg, a_iQWord) \
390 do { (a_r64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[(a_iQWord)]; } while (0)
391#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
392 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
393#define IEM_MC_FETCH_XREG_R32(a_r32Value, a_iXReg, a_iDWord) \
394 do { (a_r32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[(a_iDWord)]; } while (0)
395#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
396 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
397#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
398 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au8[(a_iByte)]; } while (0)
399#define IEM_MC_FETCH_XREG_PAIR_U128(a_Dst, a_iXReg1, a_iXReg2) \
400 do { (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
401 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
402 (a_Dst).uSrc2.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[0]; \
403 (a_Dst).uSrc2.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[1]; \
404 } while (0)
405#define IEM_MC_FETCH_XREG_PAIR_XMM(a_Dst, a_iXReg1, a_iXReg2) \
406 do { (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
407 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
408 (a_Dst).uSrc2.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[0]; \
409 (a_Dst).uSrc2.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[1]; \
410 } while (0)
411#define IEM_MC_FETCH_XREG_PAIR_U128_AND_RAX_RDX_U64(a_Dst, a_iXReg1, a_iXReg2) \
412 do { (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
413 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
414 (a_Dst).uSrc2.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[0]; \
415 (a_Dst).uSrc2.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[1]; \
416 (a_Dst).u64Rax = pVCpu->cpum.GstCtx.rax; \
417 (a_Dst).u64Rdx = pVCpu->cpum.GstCtx.rdx; \
418 } while (0)
419#define IEM_MC_FETCH_XREG_PAIR_U128_AND_EAX_EDX_U32_SX_U64(a_Dst, a_iXReg1, a_iXReg2) \
420 do { (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
421 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
422 (a_Dst).uSrc2.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[0]; \
423 (a_Dst).uSrc2.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[1]; \
424 (a_Dst).u64Rax = (int64_t)(int32_t)pVCpu->cpum.GstCtx.eax; \
425 (a_Dst).u64Rdx = (int64_t)(int32_t)pVCpu->cpum.GstCtx.edx; \
426 } while (0)
427#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
428 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
429 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
430 } while (0)
431#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
432 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
433 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
434 } while (0)
435#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
436 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
437#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
438 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
439#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
440 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
441#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
442 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
443#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
444 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)] = (a_u16Value); } while (0)
445#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
446 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au8[(a_iByte)] = (a_u8Value); } while (0)
447
448#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
449 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
450 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
451 } while (0)
452
453#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
454 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
455#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
456 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
457#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
458 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
459#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
460 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
461 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
462 } while (0)
463
464#define IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(a_iXRegDst, a_u8Src) \
465 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
466 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[0] = (a_u8Src); \
467 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[1] = (a_u8Src); \
468 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[2] = (a_u8Src); \
469 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[3] = (a_u8Src); \
470 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[4] = (a_u8Src); \
471 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[5] = (a_u8Src); \
472 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[6] = (a_u8Src); \
473 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[7] = (a_u8Src); \
474 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[8] = (a_u8Src); \
475 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[9] = (a_u8Src); \
476 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[10] = (a_u8Src); \
477 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[11] = (a_u8Src); \
478 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[12] = (a_u8Src); \
479 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[13] = (a_u8Src); \
480 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[14] = (a_u8Src); \
481 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[15] = (a_u8Src); \
482 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
483 } while (0)
484#define IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(a_iXRegDst, a_u16Src) \
485 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
486 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[0] = (a_u16Src); \
487 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[1] = (a_u16Src); \
488 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[2] = (a_u16Src); \
489 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[3] = (a_u16Src); \
490 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[4] = (a_u16Src); \
491 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[5] = (a_u16Src); \
492 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[6] = (a_u16Src); \
493 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[7] = (a_u16Src); \
494 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
495 } while (0)
496#define IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(a_iXRegDst, a_u32Src) \
497 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
498 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[0] = (a_u32Src); \
499 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[1] = (a_u32Src); \
500 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[2] = (a_u32Src); \
501 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[3] = (a_u32Src); \
502 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
503 } while (0)
504#define IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(a_iXRegDst, a_u64Src) \
505 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
506 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au64[0] = (a_u64Src); \
507 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au64[1] = (a_u64Src); \
508 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
509 } while (0)
510
511#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
512 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
513#define IEM_MC_REF_XREG_XMM(a_pXmmDst, a_iXReg) \
514 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
515#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
516 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
517#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
518 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
519#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
520 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
521#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
522 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
523#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
524 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
525#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
526 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
527#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
528 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
529 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
530 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
531 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
532 } while (0)
533
534#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
535 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
536 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
537 } while (0)
538#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc, a_iQWord) \
539 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
540 if ((a_iQWord) < 2) \
541 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[(a_iQWord)]; \
542 else \
543 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[(a_iQWord) - 2]; \
544 } while (0)
545#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc, a_iDQword) \
546 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
547 if ((a_iDQword) == 0) \
548 { \
549 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegSrcTmp)].au64[0]; \
550 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegSrcTmp)].au64[1]; \
551 } \
552 else \
553 { \
554 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegSrcTmp)].au64[0]; \
555 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegSrcTmp)].au64[1]; \
556 } \
557 } while (0)
558#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
559 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
560 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
561 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
562 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
563 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
564 } while (0)
565#define IEM_MC_FETCH_YREG_YMM(a_uYmmDst, a_iYRegSrc) \
566 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
567 (a_uYmmDst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
568 (a_uYmmDst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
569 (a_uYmmDst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
570 (a_uYmmDst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
571 } while (0)
572#define IEM_MC_FETCH_YREG_PAIR_YMM(a_uYmmDst, a_iYRegSrc1, a_iYRegSrc2) \
573 do { uintptr_t const iYRegSrc1Tmp = (a_iYRegSrc1); \
574 uintptr_t const iYRegSrc2Tmp = (a_iYRegSrc2); \
575 (a_uYmmDst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc1Tmp].au64[0]; \
576 (a_uYmmDst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc1Tmp].au64[1]; \
577 (a_uYmmDst).uSrc1.au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrc1Tmp].au64[0]; \
578 (a_uYmmDst).uSrc1.au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrc1Tmp].au64[1]; \
579 (a_uYmmDst).uSrc2.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc2Tmp].au64[0]; \
580 (a_uYmmDst).uSrc2.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc2Tmp].au64[1]; \
581 (a_uYmmDst).uSrc2.au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrc2Tmp].au64[0]; \
582 (a_uYmmDst).uSrc2.au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrc2Tmp].au64[1]; \
583 } while (0)
584
585#define IEM_MC_STORE_YREG_U128(a_iYRegDst, a_iDQword, a_u128Value) \
586 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
587 if ((a_iDQword) == 0) \
588 { \
589 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au64[0] = (a_u128Value).au64[0]; \
590 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au64[1] = (a_u128Value).au64[1]; \
591 } \
592 else \
593 { \
594 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au64[0] = (a_u128Value).au64[0]; \
595 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au64[1] = (a_u128Value).au64[1]; \
596 } \
597 } while (0)
598
599#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
600#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
601 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
602 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
603 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
604 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
605 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
606 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
607 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
608 } while (0)
609#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
610 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
611 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
612 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
613 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
614 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
615 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
616 } while (0)
617#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
618 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
619 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
620 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
621 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
622 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
623 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
624 } while (0)
625#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
626 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
627 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
628 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
629 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
630 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
631 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
632 } while (0)
633#define IEM_MC_STORE_YREG_YMM_ZX_VLMAX(a_iYRegDst, a_uYmmSrc) \
634 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
635 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_uYmmSrc).au64[0]; \
636 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_uYmmSrc).au64[1]; \
637 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_uYmmSrc).au64[2]; \
638 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_uYmmSrc).au64[3]; \
639 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
640 } while (0)
641#define IEM_MC_STORE_YREG_U32_U256(a_iYRegDst, a_iDwDst, a_u256Value, a_iDwSrc) \
642 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
643 if ((a_iDwDst) < 4) \
644 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au32[(a_iDwDst)] = (a_u256Value).au32[(a_iDwSrc)]; \
645 else \
646 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au32[(a_iDwDst) - 4] = (a_u256Value).au32[(a_iDwSrc)]; \
647 } while (0)
648#define IEM_MC_STORE_YREG_U64_U256(a_iYRegDst, a_iQwDst, a_u256Value, a_iQwSrc) \
649 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
650 if ((a_iQwDst) < 2) \
651 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au64[(a_iQwDst)] = (a_u256Value).au64[(a_iQwSrc)]; \
652 else \
653 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au64[(a_iQwDst) - 2] = (a_u256Value).au64[(a_iQwSrc)]; \
654 } while (0)
655#define IEM_MC_STORE_YREG_U64(a_iYRegDst, a_iQword, a_u64Value) \
656 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
657 if ((a_iQword) < 2) \
658 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au64[(a_iQword)] = (a_u64Value); \
659 else \
660 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au64[(a_iQword) - 2] = (a_u64Value); \
661 } while (0)
662
663#define IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(a_iYRegDst, a_u8Src) \
664 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
665 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[0] = (a_u8Src); \
666 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[1] = (a_u8Src); \
667 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[2] = (a_u8Src); \
668 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[3] = (a_u8Src); \
669 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[4] = (a_u8Src); \
670 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[5] = (a_u8Src); \
671 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[6] = (a_u8Src); \
672 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[7] = (a_u8Src); \
673 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[8] = (a_u8Src); \
674 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[9] = (a_u8Src); \
675 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[10] = (a_u8Src); \
676 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[11] = (a_u8Src); \
677 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[12] = (a_u8Src); \
678 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[13] = (a_u8Src); \
679 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[14] = (a_u8Src); \
680 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[15] = (a_u8Src); \
681 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[0] = (a_u8Src); \
682 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[1] = (a_u8Src); \
683 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[2] = (a_u8Src); \
684 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[3] = (a_u8Src); \
685 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[4] = (a_u8Src); \
686 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[5] = (a_u8Src); \
687 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[6] = (a_u8Src); \
688 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[7] = (a_u8Src); \
689 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[8] = (a_u8Src); \
690 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[9] = (a_u8Src); \
691 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[10] = (a_u8Src); \
692 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[11] = (a_u8Src); \
693 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[12] = (a_u8Src); \
694 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[13] = (a_u8Src); \
695 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[14] = (a_u8Src); \
696 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[15] = (a_u8Src); \
697 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
698 } while (0)
699#define IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(a_iYRegDst, a_u16Src) \
700 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
701 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[0] = (a_u16Src); \
702 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[1] = (a_u16Src); \
703 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[2] = (a_u16Src); \
704 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[3] = (a_u16Src); \
705 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[4] = (a_u16Src); \
706 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[5] = (a_u16Src); \
707 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[6] = (a_u16Src); \
708 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[7] = (a_u16Src); \
709 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[0] = (a_u16Src); \
710 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[1] = (a_u16Src); \
711 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[2] = (a_u16Src); \
712 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[3] = (a_u16Src); \
713 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[4] = (a_u16Src); \
714 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[5] = (a_u16Src); \
715 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[6] = (a_u16Src); \
716 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[7] = (a_u16Src); \
717 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
718 } while (0)
719#define IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
720 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
721 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
722 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = (a_u32Src); \
723 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[2] = (a_u32Src); \
724 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[3] = (a_u32Src); \
725 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[0] = (a_u32Src); \
726 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[1] = (a_u32Src); \
727 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[2] = (a_u32Src); \
728 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[3] = (a_u32Src); \
729 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
730 } while (0)
731#define IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
732 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
733 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
734 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Src); \
735 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u64Src); \
736 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u64Src); \
737 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
738 } while (0)
739#define IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
740 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
741 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
742 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
743 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
744 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
745 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
746 } while (0)
747
748#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
749 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
750#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
751 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
752#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
753 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
754#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
755 do { uintptr_t const iYRegTmp = (a_iYReg); \
756 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
757 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
758 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
759 } while (0)
760
761#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
762 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
763 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
764 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
765 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
766 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
767 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
768 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
769 } while (0)
770#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
771 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
772 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
773 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
774 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
775 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
776 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
777 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
778 } while (0)
779#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
780 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
781 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
782 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
783 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
784 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
785 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
786 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
787 } while (0)
788
789#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
790 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
791 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
792 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
793 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
794 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
795 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
796 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
797 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
798 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
799 } while (0)
800#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
801 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
802 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
803 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
804 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
805 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
806 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
807 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
808 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
809 } while (0)
810#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovlhps */ \
811 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
812 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
813 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
814 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
815 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
816 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
817 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
818 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
819 } while (0)
820#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
821 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
822 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
823 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
824 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
825 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
826 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
827 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
828 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
829 } while (0)
830#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
831 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
832 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
833 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
834 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
835 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
836 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
837 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
838 } while (0)
839#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
840 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
841 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
842 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
843 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
844 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
845 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
846 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
847 } while (0)
848
849#define IEM_MC_CLEAR_ZREG_256_UP(a_iYReg) \
850 do { IEM_MC_INT_CLEAR_ZMM_256_UP(a_iYReg); } while (0)
851
852#define IEM_MC_FETCH_MEM_SEG_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
853 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
854#define IEM_MC_FETCH_MEM_SEG_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
855 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
856
857#define IEM_MC_FETCH_MEM_FLAT_R80(a_r80Dst, a_GCPtrMem) \
858 iemMemFlatFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_GCPtrMem))
859#define IEM_MC_FETCH_MEM_FLAT_D80(a_d80Dst, a_GCPtrMem) \
860 iemMemFlatFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_GCPtrMem))
861
862#define IEM_MC_FETCH_MEM_SEG_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
863 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
864#define IEM_MC_FETCH_MEM_SEG_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
865 iemMemFetchDataU128NoAcJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
866#define IEM_MC_FETCH_MEM_SEG_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
867 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
868
869#define IEM_MC_FETCH_MEM_FLAT_XMM(a_XmmDst, a_GCPtrMem) \
870 iemMemFlatFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_GCPtrMem))
871#define IEM_MC_FETCH_MEM_FLAT_XMM_NO_AC(a_XmmDst, a_GCPtrMem) \
872 iemMemFlatFetchDataU128NoAcJmp(pVCpu, &(a_XmmDst).uXmm, (a_GCPtrMem))
873#define IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE(a_XmmDst, a_GCPtrMem) \
874 iemMemFlatFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_GCPtrMem))
875
876#define IEM_MC_FETCH_MEM_SEG_U128_AND_XREG_U128(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
877 iemMemFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2)); \
878 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
879 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
880 } while (0)
881#define IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
882 iemMemFlatFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_GCPtrMem2)); \
883 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
884 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
885 } while (0)
886
887#define IEM_MC_FETCH_MEM_SEG_XMM_ALIGN_SSE_AND_XREG_XMM(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
888 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_Dst).uSrc2.uXmm, (a_iSeg2), (a_GCPtrMem2)); \
889 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
890 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
891 } while (0)
892
893#define IEM_MC_FETCH_MEM_SEG_XMM_NO_AC_AND_XREG_XMM(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
894 iemMemFetchDataU128NoAcJmp(pVCpu, &(a_Dst).uSrc2.uXmm, (a_iSeg2), (a_GCPtrMem2)); \
895 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
896 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
897 } while (0)
898
899#define IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE_AND_XREG_XMM(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
900 iemMemFlatFetchDataU128AlignedSseJmp(pVCpu, &(a_Dst).uSrc2.uXmm, (a_GCPtrMem2)); \
901 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
902 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
903 } while (0)
904
905#define IEM_MC_FETCH_MEM_FLAT_XMM_NO_AC_AND_XREG_XMM(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
906 iemMemFlatFetchDataU128NoAcJmp(pVCpu, &(a_Dst).uSrc2.uXmm, (a_GCPtrMem2)); \
907 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
908 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
909 } while (0)
910
911#define IEM_MC_FETCH_MEM_SEG_XMM_U32_AND_XREG_XMM(a_Dst, a_iXReg1, a_iDWord2, a_iSeg2, a_GCPtrMem2) do { \
912 (a_Dst).uSrc2.uXmm.au64[0] = 0; \
913 (a_Dst).uSrc2.uXmm.au64[1] = 0; \
914 (a_Dst).uSrc2.uXmm.au32[(a_iDWord2)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg2), (a_GCPtrMem2)); \
915 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
916 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
917 } while (0)
918#define IEM_MC_FETCH_MEM_FLAT_XMM_U32_AND_XREG_XMM(a_Dst, a_iXReg1, a_iDWord2, a_GCPtrMem2) do { \
919 (a_Dst).uSrc2.uXmm.au64[0] = 0; \
920 (a_Dst).uSrc2.uXmm.au64[1] = 0; \
921 (a_Dst).uSrc2.uXmm.au32[(a_iDWord2)] = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem2)); \
922 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
923 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
924 } while (0)
925
926#define IEM_MC_FETCH_MEM_SEG_XMM_U64_AND_XREG_XMM(a_Dst, a_iXReg1, a_iQWord2, a_iSeg2, a_GCPtrMem2) do { \
927 (a_Dst).uSrc2.uXmm.au64[!(a_iQWord2)] = 0; \
928 (a_Dst).uSrc2.uXmm.au64[(a_iQWord2)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg2), (a_GCPtrMem2)); \
929 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
930 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
931 } while (0)
932#define IEM_MC_FETCH_MEM_FLAT_XMM_U64_AND_XREG_XMM(a_Dst, a_iXReg1, a_iQWord2, a_GCPtrMem2) do { \
933 (a_Dst).uSrc2.uXmm.au64[1] = 0; \
934 (a_Dst).uSrc2.uXmm.au64[(a_iQWord2)] = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem2)); \
935 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
936 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
937 } while (0)
938
939
940#define IEM_MC_FETCH_MEM_SEG_U128_AND_XREG_U128_AND_RAX_RDX_U64(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
941 iemMemFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2)); \
942 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
943 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
944 (a_Dst).u64Rax = pVCpu->cpum.GstCtx.rax; \
945 (a_Dst).u64Rdx = pVCpu->cpum.GstCtx.rdx; \
946 } while (0)
947#define IEM_MC_FETCH_MEM_SEG_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
948 iemMemFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2)); \
949 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
950 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
951 (a_Dst).u64Rax = (int64_t)(int32_t)pVCpu->cpum.GstCtx.eax; \
952 (a_Dst).u64Rdx = (int64_t)(int32_t)pVCpu->cpum.GstCtx.edx; \
953 } while (0)
954
955#define IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128_AND_RAX_RDX_U64(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
956 iemMemFlatFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_GCPtrMem2)); \
957 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
958 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
959 (a_Dst).u64Rax = pVCpu->cpum.GstCtx.rax; \
960 (a_Dst).u64Rdx = pVCpu->cpum.GstCtx.rdx; \
961 } while (0)
962#define IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
963 iemMemFlatFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_GCPtrMem2)); \
964 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
965 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
966 (a_Dst).u64Rax = (int64_t)(int32_t)pVCpu->cpum.GstCtx.eax; \
967 (a_Dst).u64Rdx = (int64_t)(int32_t)pVCpu->cpum.GstCtx.edx; \
968 } while (0)
969
970
971#define IEM_MC_FETCH_MEM_SEG_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
972 iemMemFetchDataU256NoAcJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
973#define IEM_MC_FETCH_MEM_SEG_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
974 iemMemFetchDataU256NoAcJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
975#define IEM_MC_FETCH_MEM_SEG_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
976 iemMemFetchDataU256AlignedAvxJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
977
978#define IEM_MC_FETCH_MEM_SEG_YMM_NO_AC_AND_YREG_YMM(a_uYmmDst, a_iYRegSrc1, a_iSeg2, a_GCPtrMem2) do { \
979 uintptr_t const a_iYRegSrc1Tmp = (a_iYRegSrc1); \
980 iemMemFetchDataU256NoAcJmp(pVCpu, &(a_uYmmDst).uSrc2.ymm, (a_iSeg2), (a_GCPtrMem2)); \
981 (a_uYmmDst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[a_iYRegSrc1Tmp].au64[0]; \
982 (a_uYmmDst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[a_iYRegSrc1Tmp].au64[1]; \
983 (a_uYmmDst).uSrc1.au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[a_iYRegSrc1Tmp].au64[0]; \
984 (a_uYmmDst).uSrc1.au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[a_iYRegSrc1Tmp].au64[1]; \
985 } while (0)
986
987#define IEM_MC_FETCH_MEM_FLAT_YMM(a_YmmDst, a_GCPtrMem) \
988 iemMemFlatFetchDataU256NoAcJmp(pVCpu, &(a_YmmDst).ymm, (a_GCPtrMem))
989#define IEM_MC_FETCH_MEM_FLAT_YMM_NO_AC(a_YmmDst, a_GCPtrMem) \
990 iemMemFlatFetchDataU256NoAcJmp(pVCpu, &(a_YmmDst).ymm, (a_GCPtrMem))
991#define IEM_MC_FETCH_MEM_FLAT_YMM_ALIGN_AVX(a_YmmDst, a_GCPtrMem) \
992 iemMemFlatFetchDataU256AlignedAvxJmp(pVCpu, &(a_YmmDst).ymm, (a_GCPtrMem))
993
994#define IEM_MC_FETCH_MEM_FLAT_YMM_ALIGN_AVX_AND_YREG_YMM(a_uYmmDst, a_iYRegSrc1, a_GCPtrMem2) do { \
995 uintptr_t const a_iYRegSrc1Tmp = (a_iYRegSrc1); \
996 iemMemFlatFetchDataU256AlignedAvxJmp(pVCpu, &(a_uYmmDst).uSrc2.ymm, (a_GCPtrMem2)); \
997 (a_uYmmDst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[a_iYRegSrc1Tmp].au64[0]; \
998 (a_uYmmDst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[a_iYRegSrc1Tmp].au64[1]; \
999 (a_uYmmDst).uSrc1.au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[a_iYRegSrc1Tmp].au64[0]; \
1000 (a_uYmmDst).uSrc1.au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[a_iYRegSrc1Tmp].au64[1]; \
1001 } while (0)
1002
1003
1004
1005#define IEM_MC_FETCH_MEM_SEG_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1006 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1007#define IEM_MC_FETCH_MEM_SEG_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1008 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1009#define IEM_MC_FETCH_MEM_SEG_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1010 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1011#define IEM_MC_FETCH_MEM_SEG_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1012 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1013#define IEM_MC_FETCH_MEM_SEG_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1014 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1015#define IEM_MC_FETCH_MEM_SEG_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1016 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1017
1018#define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U16(a_u16Dst, a_GCPtrMem) \
1019 ((a_u16Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1020#define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U32(a_u32Dst, a_GCPtrMem) \
1021 ((a_u32Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1022#define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U64(a_u64Dst, a_GCPtrMem) \
1023 ((a_u64Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1024#define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U32(a_u32Dst, a_GCPtrMem) \
1025 ((a_u32Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1026#define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U64(a_u64Dst, a_GCPtrMem) \
1027 ((a_u64Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1028#define IEM_MC_FETCH_MEM_FLAT_U32_ZX_U64(a_u64Dst, a_GCPtrMem) \
1029 ((a_u64Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
1030
1031#define IEM_MC_FETCH_MEM_SEG_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1032 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1033#define IEM_MC_FETCH_MEM_SEG_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1034 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1035#define IEM_MC_FETCH_MEM_SEG_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1036 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1037#define IEM_MC_FETCH_MEM_SEG_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1038 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1039#define IEM_MC_FETCH_MEM_SEG_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1040 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1041#define IEM_MC_FETCH_MEM_SEG_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1042 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1043
1044#define IEM_MC_FETCH_MEM_FLAT_U8_SX_U16(a_u16Dst, a_GCPtrMem) \
1045 ((a_u16Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1046#define IEM_MC_FETCH_MEM_FLAT_U8_SX_U32(a_u32Dst, a_GCPtrMem) \
1047 ((a_u32Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1048#define IEM_MC_FETCH_MEM_FLAT_U8_SX_U64(a_u64Dst, a_GCPtrMem) \
1049 ((a_u64Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1050#define IEM_MC_FETCH_MEM_FLAT_U16_SX_U32(a_u32Dst, a_GCPtrMem) \
1051 ((a_u32Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1052#define IEM_MC_FETCH_MEM_FLAT_U16_SX_U64(a_u64Dst, a_GCPtrMem) \
1053 ((a_u64Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1054#define IEM_MC_FETCH_MEM_FLAT_U32_SX_U64(a_u64Dst, a_GCPtrMem) \
1055 ((a_u64Dst) = (int32_t)iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
1056
1057#define IEM_MC_STORE_MEM_BY_REF_R80_NEG_QNAN(a_pr80Dst) \
1058 do { \
1059 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1060 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1061 } while (0)
1062#define IEM_MC_STORE_MEM_BY_REF_D80_INDEF(a_pd80Dst) \
1063 do { \
1064 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1065 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1066 } while (0)
1067
1068#define IEM_MC_STORE_MEM_SEG_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1069 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1070
1071#define IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE(a_GCPtrMem, a_u128Value) \
1072 iemMemStoreDataU128AlignedSseJmp(pVCpu, UINT8_MAX, (a_GCPtrMem), (a_u128Value))
1073
1074#define IEM_MC_STORE_MEM_SEG_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1075 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1076
1077#define IEM_MC_STORE_MEM_FLAT_U256_ALIGN_AVX(a_GCPtrMem, a_u256Value) \
1078 iemMemFlatStoreDataU256AlignedAvxJmp(pVCpu, (a_GCPtrMem), &(a_u256Value))
1079
1080
1081/* Regular stack push and pop: */
1082#define IEM_MC_PUSH_U16(a_u16Value) iemMemStackPushU16Jmp(pVCpu, (a_u16Value))
1083#define IEM_MC_PUSH_U32(a_u32Value) iemMemStackPushU32Jmp(pVCpu, (a_u32Value))
1084#define IEM_MC_PUSH_U32_SREG(a_uSegVal) iemMemStackPushU32SRegJmp(pVCpu, (a_uSegVal))
1085#define IEM_MC_PUSH_U64(a_u64Value) iemMemStackPushU64Jmp(pVCpu, (a_u64Value))
1086
1087#define IEM_MC_POP_GREG_U16(a_iGReg) iemMemStackPopGRegU16Jmp(pVCpu, (a_iGReg))
1088#define IEM_MC_POP_GREG_U32(a_iGReg) iemMemStackPopGRegU32Jmp(pVCpu, (a_iGReg))
1089#define IEM_MC_POP_GREG_U64(a_iGReg) iemMemStackPopGRegU64Jmp(pVCpu, (a_iGReg))
1090
1091/* 32-bit flat stack push and pop: */
1092#define IEM_MC_FLAT32_PUSH_U16(a_u16Value) iemMemFlat32StackPushU16Jmp(pVCpu, (a_u16Value))
1093#define IEM_MC_FLAT32_PUSH_U32(a_u32Value) iemMemFlat32StackPushU32Jmp(pVCpu, (a_u32Value))
1094#define IEM_MC_FLAT32_PUSH_U32_SREG(a_uSegVal) iemMemFlat32StackPushU32SRegJmp(pVCpu, (a_uSegVal))
1095
1096#define IEM_MC_FLAT32_POP_GREG_U16(a_iGReg) iemMemFlat32StackPopGRegU16Jmp(pVCpu, a_iGReg))
1097#define IEM_MC_FLAT32_POP_GREG_U32(a_iGReg) iemMemFlat32StackPopGRegU32Jmp(pVCpu, a_iGReg))
1098
1099/* 64-bit flat stack push and pop: */
1100#define IEM_MC_FLAT64_PUSH_U16(a_u16Value) iemMemFlat64StackPushU16Jmp(pVCpu, (a_u16Value))
1101#define IEM_MC_FLAT64_PUSH_U64(a_u64Value) iemMemFlat64StackPushU64Jmp(pVCpu, (a_u64Value))
1102
1103#define IEM_MC_FLAT64_POP_GREG_U16(a_iGReg) iemMemFlat64StackPopGRegU16Jmp(pVCpu, (a_iGReg))
1104#define IEM_MC_FLAT64_POP_GREG_U64(a_iGReg) iemMemFlat64StackPopGRegU64Jmp(pVCpu, (a_iGReg))
1105
1106
1107/* misc */
1108
1109/**
1110 * Maps guest memory for 80-bit float writeonly direct (or bounce) buffer acccess.
1111 *
1112 * @param[out] a_pr80Mem Where to return the pointer to the mapping.
1113 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1114 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1115 * @param[in] a_GCPtrMem The memory address.
1116 * @remarks Will return/long jump on errors.
1117 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1118 */
1119#define IEM_MC_MEM_SEG_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1120 (a_pr80Mem) = iemMemMapDataR80WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1121
1122/**
1123 * Maps guest memory for 80-bit float writeonly direct (or bounce) buffer acccess.
1124 *
1125 * @param[out] a_pr80Mem Where to return the pointer to the mapping.
1126 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1127 * @param[in] a_GCPtrMem The memory address.
1128 * @remarks Will return/long jump on errors.
1129 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1130 */
1131#define IEM_MC_MEM_FLAT_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_GCPtrMem) \
1132 (a_pr80Mem) = iemMemFlatMapDataR80WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1133
1134
1135/**
1136 * Maps guest memory for 80-bit BCD writeonly direct (or bounce) buffer acccess.
1137 *
1138 * @param[out] a_pd80Mem Where to return the pointer to the mapping.
1139 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1140 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1141 * @param[in] a_GCPtrMem The memory address.
1142 * @remarks Will return/long jump on errors.
1143 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1144 */
1145#define IEM_MC_MEM_SEG_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1146 (a_pd80Mem) = iemMemMapDataD80WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1147
1148/**
1149 * Maps guest memory for 80-bit BCD writeonly direct (or bounce) buffer acccess.
1150 *
1151 * @param[out] a_pd80Mem Where to return the pointer to the mapping.
1152 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1153 * @param[in] a_GCPtrMem The memory address.
1154 * @remarks Will return/long jump on errors.
1155 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1156 */
1157#define IEM_MC_MEM_FLAT_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_GCPtrMem) \
1158 (a_pd80Mem) = iemMemFlatMapDataD80WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1159
1160
1161/** Commits the memory and unmaps the guest memory unless the FPU status word
1162 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1163 * that would cause FLD not to store.
1164 *
1165 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1166 * store, while \#P will not.
1167 *
1168 * @remarks May in theory return - for now.
1169 * @note Implictly frees both the a_bMapInfo and a_u16FSW variables.
1170 */
1171#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE_WO(a_bMapInfo, a_u16FSW) do { \
1172 if ( !(a_u16FSW & X86_FSW_ES) \
1173 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1174 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1175 iemMemCommitAndUnmapWoJmp(pVCpu, a_bMapInfo); \
1176 else \
1177 iemMemRollbackAndUnmapWo(pVCpu, a_bMapInfo); \
1178 } while (0)
1179
1180
1181
1182/** Calculate efficient address from R/M. */
1183#define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
1184 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (a_bRm), (a_cbImmAndRspOffset)))
1185
1186
1187/**
1188 * Calls a FPU assembly implementation taking one visible argument.
1189 *
1190 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1191 * @param a0 The first extra argument.
1192 */
1193#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1194 do { \
1195 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1196 } while (0)
1197
1198/**
1199 * Calls a FPU assembly implementation taking two visible arguments.
1200 *
1201 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1202 * @param a0 The first extra argument.
1203 * @param a1 The second extra argument.
1204 */
1205#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1206 do { \
1207 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1208 } while (0)
1209
1210/**
1211 * Calls a FPU assembly implementation taking three visible arguments.
1212 *
1213 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1214 * @param a0 The first extra argument.
1215 * @param a1 The second extra argument.
1216 * @param a2 The third extra argument.
1217 */
1218#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1219 do { \
1220 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1221 } while (0)
1222
1223#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1224 do { \
1225 (a_FpuData).FSW = (a_FSW); \
1226 (a_FpuData).r80Result = *(a_pr80Value); \
1227 } while (0)
1228
1229/** Pushes FPU result onto the stack. */
1230#define IEM_MC_PUSH_FPU_RESULT(a_FpuData, a_uFpuOpcode) \
1231 iemFpuPushResult(pVCpu, &a_FpuData, a_uFpuOpcode)
1232/** Pushes FPU result onto the stack and sets the FPUDP. */
1233#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
1234 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
1235
1236/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1237#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo, a_uFpuOpcode) \
1238 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo, a_uFpuOpcode)
1239
1240/** Stores FPU result in a stack register. */
1241#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg, a_uFpuOpcode) \
1242 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg, a_uFpuOpcode)
1243/** Stores FPU result in a stack register and pops the stack. */
1244#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg, a_uFpuOpcode) \
1245 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg, a_uFpuOpcode)
1246/** Stores FPU result in a stack register and sets the FPUDP. */
1247#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
1248 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
1249/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1250 * stack. */
1251#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
1252 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
1253
1254/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1255#define IEM_MC_UPDATE_FPU_OPCODE_IP(a_uFpuOpcode) \
1256 iemFpuUpdateOpcodeAndIp(pVCpu, a_uFpuOpcode)
1257/** Free a stack register (for FFREE and FFREEP). */
1258#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1259 iemFpuStackFree(pVCpu, a_iStReg)
1260/** Increment the FPU stack pointer. */
1261#define IEM_MC_FPU_STACK_INC_TOP() \
1262 iemFpuStackIncTop(pVCpu)
1263/** Decrement the FPU stack pointer. */
1264#define IEM_MC_FPU_STACK_DEC_TOP() \
1265 iemFpuStackDecTop(pVCpu)
1266
1267/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1268#define IEM_MC_UPDATE_FSW(a_u16FSW, a_uFpuOpcode) \
1269 iemFpuUpdateFSW(pVCpu, a_u16FSW, a_uFpuOpcode)
1270/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1271#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW, a_uFpuOpcode) \
1272 iemFpuUpdateFSW(pVCpu, a_u16FSW, a_uFpuOpcode)
1273/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1274#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
1275 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
1276/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1277#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW, a_uFpuOpcode) \
1278 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW, a_uFpuOpcode)
1279/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1280 * stack. */
1281#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
1282 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
1283/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1284#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW, a_uFpuOpcode) \
1285 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW, a_uFpuOpcode)
1286
1287/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1288#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst, a_uFpuOpcode) \
1289 iemFpuStackUnderflow(pVCpu, a_iStDst, a_uFpuOpcode)
1290/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1291 * stack. */
1292#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst, a_uFpuOpcode) \
1293 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst, a_uFpuOpcode)
1294/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1295 * FPUDS. */
1296#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
1297 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
1298/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1299 * FPUDS. Pops stack. */
1300#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
1301 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
1302/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1303 * stack twice. */
1304#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP(a_uFpuOpcode) \
1305 iemFpuStackUnderflowThenPopPop(pVCpu, a_uFpuOpcode)
1306/** Raises a FPU stack underflow exception for an instruction pushing a result
1307 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1308#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW(a_uFpuOpcode) \
1309 iemFpuStackPushUnderflow(pVCpu, a_uFpuOpcode)
1310/** Raises a FPU stack underflow exception for an instruction pushing a result
1311 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1312#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO(a_uFpuOpcode) \
1313 iemFpuStackPushUnderflowTwo(pVCpu, a_uFpuOpcode)
1314
1315/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1316 * FPUIP, FPUCS and FOP. */
1317#define IEM_MC_FPU_STACK_PUSH_OVERFLOW(a_uFpuOpcode) \
1318 iemFpuStackPushOverflow(pVCpu, a_uFpuOpcode)
1319/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1320 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1321#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
1322 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
1323/** Prepares for using the FPU state.
1324 * Ensures that we can use the host FPU in the current context (RC+R0.
1325 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1326#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1327/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1328#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1329/** Actualizes the guest FPU state so it can be accessed and modified. */
1330#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1331
1332/** Prepares for using the SSE state.
1333 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1334 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1335#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1336/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1337#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1338/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1339#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1340
1341/** Prepares for using the AVX state.
1342 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1343 * Ensures the guest AVX state in the CPUMCTX is up to date.
1344 * @note This will include the AVX512 state too when support for it is added
1345 * due to the zero extending feature of VEX instruction. */
1346#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1347/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1348#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1349/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1350#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1351
1352/**
1353 * Calls a MMX assembly implementation taking two visible arguments.
1354 *
1355 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1356 * @param a0 The first extra argument.
1357 * @param a1 The second extra argument.
1358 */
1359#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1360 do { \
1361 IEM_MC_PREPARE_FPU_USAGE(); \
1362 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1363 } while (0)
1364
1365/**
1366 * Calls a MMX assembly implementation taking three visible arguments.
1367 *
1368 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1369 * @param a0 The first extra argument.
1370 * @param a1 The second extra argument.
1371 * @param a2 The third extra argument.
1372 */
1373#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1374 do { \
1375 IEM_MC_PREPARE_FPU_USAGE(); \
1376 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1377 } while (0)
1378
1379
1380/**
1381 * Calls a SSE assembly implementation taking two visible arguments.
1382 *
1383 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1384 * @param a0 The first extra argument.
1385 * @param a1 The second extra argument.
1386 *
1387 * @note This throws an \#XF/\#UD exception if the helper indicates an exception
1388 * which is unmasked in the guest's MXCSR.
1389 */
1390#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1391 do { \
1392 IEM_MC_PREPARE_SSE_USAGE(); \
1393 const uint32_t fMxcsrOld = pVCpu->cpum.GstCtx.XState.x87.MXCSR; \
1394 const uint32_t fMxcsrNew = a_pfnAImpl(fMxcsrOld & ~X86_MXCSR_XCPT_FLAGS, \
1395 (a0), (a1)); \
1396 pVCpu->cpum.GstCtx.XState.x87.MXCSR |= fMxcsrNew; \
1397 if (RT_LIKELY(( ~((fMxcsrOld & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1398 & (fMxcsrNew & X86_MXCSR_XCPT_FLAGS)) == 0)) \
1399 { /* probable */ } \
1400 else \
1401 { \
1402 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT) \
1403 return iemRaiseSimdFpException(pVCpu); \
1404 return iemRaiseUndefinedOpcode(pVCpu); \
1405 } \
1406 } while (0)
1407
1408/**
1409 * Calls a SSE assembly implementation taking three visible arguments.
1410 *
1411 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1412 * @param a0 The first extra argument.
1413 * @param a1 The second extra argument.
1414 * @param a2 The third extra argument.
1415 *
1416 * @note This throws an \#XF/\#UD exception if the helper indicates an exception
1417 * which is unmasked in the guest's MXCSR.
1418 */
1419#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1420 do { \
1421 IEM_MC_PREPARE_SSE_USAGE(); \
1422 const uint32_t fMxcsrOld = pVCpu->cpum.GstCtx.XState.x87.MXCSR; \
1423 const uint32_t fMxcsrNew = a_pfnAImpl(fMxcsrOld & ~X86_MXCSR_XCPT_FLAGS, \
1424 (a0), (a1), (a2)); \
1425 pVCpu->cpum.GstCtx.XState.x87.MXCSR |= fMxcsrNew; \
1426 if (RT_LIKELY(( ~((fMxcsrOld & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1427 & (fMxcsrNew & X86_MXCSR_XCPT_FLAGS)) == 0)) \
1428 { /* probable */ } \
1429 else \
1430 { \
1431 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT) \
1432 return iemRaiseSimdFpException(pVCpu); \
1433 return iemRaiseUndefinedOpcode(pVCpu); \
1434 } \
1435 } while (0)
1436
1437
1438/**
1439 * Calls a AVX assembly implementation taking two visible arguments.
1440 *
1441 * There is one implicit zero'th argument, a pointer to the extended state.
1442 *
1443 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1444 * @param a0 The first extra argument.
1445 * @param a1 The second extra argument.
1446 *
1447 * @note This throws an \#XF/\#UD exception if the helper indicates an exception
1448 * which is unmasked in the guest's MXCSR.
1449 */
1450#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a0, a1) \
1451 do { \
1452 IEM_MC_PREPARE_AVX_USAGE(); \
1453 const uint32_t fMxcsrOld = pVCpu->cpum.GstCtx.XState.x87.MXCSR; \
1454 const uint32_t fMxcsrNew = a_pfnAImpl(fMxcsrOld & ~X86_MXCSR_XCPT_FLAGS, \
1455 (a0), (a1)); \
1456 pVCpu->cpum.GstCtx.XState.x87.MXCSR |= fMxcsrNew; \
1457 if (RT_LIKELY(( ~((fMxcsrOld & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1458 & (fMxcsrNew & X86_MXCSR_XCPT_FLAGS)) == 0)) \
1459 { /* probable */ } \
1460 else \
1461 { \
1462 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT) \
1463 return iemRaiseSimdFpException(pVCpu); \
1464 return iemRaiseUndefinedOpcode(pVCpu); \
1465 } \
1466 } while (0)
1467
1468/**
1469 * Calls a AVX assembly implementation taking three visible arguments.
1470 *
1471 * There is one implicit zero'th argument, a pointer to the extended state.
1472 *
1473 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1474 * @param a0 The first extra argument.
1475 * @param a1 The second extra argument.
1476 * @param a2 The third extra argument.
1477 *
1478 * @note This throws an \#XF/\#UD exception if the helper indicates an exception
1479 * which is unmasked in the guest's MXCSR.
1480 */
1481#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1482 do { \
1483 IEM_MC_PREPARE_AVX_USAGE(); \
1484 const uint32_t fMxcsrOld = pVCpu->cpum.GstCtx.XState.x87.MXCSR; \
1485 const uint32_t fMxcsrNew = a_pfnAImpl(fMxcsrOld & ~X86_MXCSR_XCPT_FLAGS, \
1486 (a0), (a1), (a2)); \
1487 pVCpu->cpum.GstCtx.XState.x87.MXCSR |= fMxcsrNew; \
1488 if (RT_LIKELY(( ~((fMxcsrOld & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1489 & (fMxcsrNew & X86_MXCSR_XCPT_FLAGS)) == 0)) \
1490 { /* probable */ } \
1491 else \
1492 { \
1493 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT) \
1494 return iemRaiseSimdFpException(pVCpu); \
1495 return iemRaiseUndefinedOpcode(pVCpu); \
1496 } \
1497 } while (0)
1498
1499#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1500#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1501#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1502#define IEM_MC_IF_CX_IS_NOT_ONE() if (pVCpu->cpum.GstCtx.cx != 1) {
1503#define IEM_MC_IF_ECX_IS_NOT_ONE() if (pVCpu->cpum.GstCtx.ecx != 1) {
1504#define IEM_MC_IF_RCX_IS_NOT_ONE() if (pVCpu->cpum.GstCtx.rcx != 1) {
1505/** @note Not for IOPL or IF testing. */
1506#define IEM_MC_IF_CX_IS_NOT_ONE_AND_EFL_BIT_SET(a_fBit) \
1507 if ( pVCpu->cpum.GstCtx.cx != 1 \
1508 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1509/** @note Not for IOPL or IF testing. */
1510#define IEM_MC_IF_ECX_IS_NOT_ONE_AND_EFL_BIT_SET(a_fBit) \
1511 if ( pVCpu->cpum.GstCtx.ecx != 1 \
1512 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1513/** @note Not for IOPL or IF testing. */
1514#define IEM_MC_IF_RCX_IS_NOT_ONE_AND_EFL_BIT_SET(a_fBit) \
1515 if ( pVCpu->cpum.GstCtx.rcx != 1 \
1516 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1517/** @note Not for IOPL or IF testing. */
1518#define IEM_MC_IF_CX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET(a_fBit) \
1519 if ( pVCpu->cpum.GstCtx.cx != 1 \
1520 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1521/** @note Not for IOPL or IF testing. */
1522#define IEM_MC_IF_ECX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET(a_fBit) \
1523 if ( pVCpu->cpum.GstCtx.ecx != 1 \
1524 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1525/** @note Not for IOPL or IF testing. */
1526#define IEM_MC_IF_RCX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET(a_fBit) \
1527 if ( pVCpu->cpum.GstCtx.rcx != 1 \
1528 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1529
1530#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1531 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80; } while (0)
1532#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1533 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1534#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1535 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1536#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1537 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1538#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1539 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1540#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1541 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1542#define IEM_MC_IF_FCW_IM() \
1543 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1544
1545/** @} */
1546
1547#endif /* !VMM_INCLUDED_SRC_VMMAll_target_x86_IEMMc_x86_h */
1548
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