VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMGC/CPUMGCA.asm@ 9176

Last change on this file since 9176 was 8155, checked in by vboxsync, 17 years ago

The Big Sun Rebranding Header Change
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1; $Id: CPUMGCA.asm 8155 2008-04-18 15:16:47Z vboxsync $
2;; @file
3;
4; CPUM - Guest Context Assembly Routines.
5
6; Copyright (C) 2006-2007 Sun Microsystems, Inc.
7;
8; This file is part of VirtualBox Open Source Edition (OSE), as
9; available from http://www.virtualbox.org. This file is free software;
10; you can redistribute it and/or modify it under the terms of the GNU
11; General Public License (GPL) as published by the Free Software
12; Foundation, in version 2 as it comes in the "COPYING" file of the
13; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15;
16; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
17; Clara, CA 95054 USA or visit http://www.sun.com if you need
18; additional information or have any questions.
19;
20
21;*******************************************************************************
22;* Header Files *
23;*******************************************************************************
24%include "VMMGC.mac"
25%include "VBox/vm.mac"
26%include "VBox/err.mac"
27%include "VBox/stam.mac"
28%include "CPUMInternal.mac"
29%include "VBox/x86.mac"
30%include "VBox/cpum.mac"
31
32
33;*******************************************************************************
34;* External Symbols *
35;*******************************************************************************
36extern IMPNAME(g_CPUM) ; VMM GC Builtin import
37extern IMPNAME(g_VM) ; VMM GC Builtin import
38extern NAME(cpumGCHandleNPAndGP) ; CPUMGC.cpp
39
40;
41; Enables write protection of Hypervisor memory pages.
42; !note! Must be commented out for Trap8 debug handler.
43;
44%define ENABLE_WRITE_PROTECTION 1
45
46BEGINCODE
47
48
49;;
50; Restores GC context before doing iret.
51;
52; @param [esp + 4] Pointer to interrupt stack frame, i.e. pointer
53; to the a struct with this layout:
54; 00h eip
55; 04h cs
56; 08h eflags
57; 0ch esp
58; 10h ss
59; 14h es (V86 only)
60; 18h ds (V86 only)
61; 1Ch fs (V86 only)
62; 20h gs (V86 only)
63;
64; @uses everything but cs, ss, esp, and eflags.
65;
66; @remark Assumes we're restoring in Ring-0 a context which is not Ring-0.
67; Further assumes flat stack and valid ds.
68
69BEGINPROC CPUMGCRestoreInt
70 ;
71 ; Update iret frame.
72 ;
73 mov eax, [esp + 4] ; get argument
74 mov edx, IMP(g_CPUM)
75
76 mov ecx, [edx + CPUM.Guest.eip]
77 mov [eax + 0h], ecx
78 mov ecx, [edx + CPUM.Guest.cs]
79 mov [eax + 4h], ecx
80 mov ecx, [edx + CPUM.Guest.eflags]
81 mov [eax + 8h], ecx
82 mov ecx, [edx + CPUM.Guest.esp]
83 mov [eax + 0ch], ecx
84 mov ecx, [edx + CPUM.Guest.ss]
85 mov [eax + 10h], ecx
86
87 test dword [edx + CPUM.Guest.eflags], X86_EFL_VM
88 jnz short CPUMGCRestoreInt_V86
89
90 ;
91 ; Load registers.
92 ;
93 ; todo: potential trouble loading invalid es,fs,gs,ds because
94 ; of a VMM imposed exception?
95 mov es, [edx + CPUM.Guest.es]
96 mov fs, [edx + CPUM.Guest.fs]
97 mov gs, [edx + CPUM.Guest.gs]
98 mov esi, [edx + CPUM.Guest.esi]
99 mov edi, [edx + CPUM.Guest.edi]
100 mov ebp, [edx + CPUM.Guest.ebp]
101 mov ebx, [edx + CPUM.Guest.ebx]
102 mov ecx, [edx + CPUM.Guest.ecx]
103 mov eax, [edx + CPUM.Guest.eax]
104 push dword [edx + CPUM.Guest.ds]
105 mov edx, [edx + CPUM.Guest.edx]
106 pop ds
107
108 ret
109
110CPUMGCRestoreInt_V86:
111 ; iret restores ds, es, fs & gs
112 mov ecx, [edx + CPUM.Guest.es]
113 mov [eax + 14h], ecx
114 mov ecx, [edx + CPUM.Guest.ds]
115 mov [eax + 18h], ecx
116 mov ecx, [edx + CPUM.Guest.fs]
117 mov [eax + 1Ch], ecx
118 mov ecx, [edx + CPUM.Guest.gs]
119 mov [eax + 20h], ecx
120 mov esi, [edx + CPUM.Guest.esi]
121 mov edi, [edx + CPUM.Guest.edi]
122 mov ebp, [edx + CPUM.Guest.ebp]
123 mov ebx, [edx + CPUM.Guest.ebx]
124 mov ecx, [edx + CPUM.Guest.ecx]
125 mov eax, [edx + CPUM.Guest.eax]
126 mov edx, [edx + CPUM.Guest.edx]
127 ret
128
129ENDPROC CPUMGCRestoreInt
130
131
132;;
133; Calls a guest trap/interrupt handler directly
134; Assumes a trap stack frame has already been setup on the guest's stack!
135;
136; @param pRegFrame [esp + 4] Original trap/interrupt context
137; @param selCS [esp + 8] Code selector of handler
138; @param pHandler [esp + 12] GC virtual address of handler
139; @param eflags [esp + 16] Callee's EFLAGS
140; @param selSS [esp + 20] Stack selector for handler
141; @param pEsp [esp + 24] Stack address for handler
142;
143; @remark This call never returns!
144;
145; CPUMGCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
146align 16
147BEGINPROC_EXPORTED CPUMGCCallGuestTrapHandler
148 mov ebp, esp
149
150 ; construct iret stack frame
151 push dword [ebp + 20] ; SS
152 push dword [ebp + 24] ; ESP
153 push dword [ebp + 16] ; EFLAGS
154 push dword [ebp + 8] ; CS
155 push dword [ebp + 12] ; EIP
156
157 ;
158 ; enable WP
159 ;
160%ifdef ENABLE_WRITE_PROTECTION
161 mov eax, cr0
162 or eax, X86_CR0_WRITE_PROTECT
163 mov cr0, eax
164%endif
165
166 ; restore CPU context (all except cs, eip, ss, esp & eflags; which are restored or overwritten by iret)
167 mov ebp, [ebp + 4] ; pRegFrame
168 mov ebx, [ebp + CPUMCTXCORE.ebx]
169 mov ecx, [ebp + CPUMCTXCORE.ecx]
170 mov edx, [ebp + CPUMCTXCORE.edx]
171 mov esi, [ebp + CPUMCTXCORE.esi]
172 mov edi, [ebp + CPUMCTXCORE.edi]
173
174 ;; @todo load segment registers *before* enabling WP.
175 TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_GS | CPUM_HANDLER_CTXCORE_IN_EBP
176 mov gs, [ebp + CPUMCTXCORE.gs]
177 TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_FS | CPUM_HANDLER_CTXCORE_IN_EBP
178 mov fs, [ebp + CPUMCTXCORE.fs]
179 TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_ES | CPUM_HANDLER_CTXCORE_IN_EBP
180 mov es, [ebp + CPUMCTXCORE.es]
181 TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_DS | CPUM_HANDLER_CTXCORE_IN_EBP
182 mov ds, [ebp + CPUMCTXCORE.ds]
183
184 mov eax, [ebp + CPUMCTXCORE.eax]
185 mov ebp, [ebp + CPUMCTXCORE.ebp]
186
187 TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
188 iret
189
190ENDPROC CPUMGCCallGuestTrapHandler
191
192;;
193; Performs an iret to V86 code
194; Assumes a trap stack frame has already been setup on the guest's stack!
195;
196; @param pRegFrame Original trap/interrupt context
197;
198; This function does not return!
199;
200;CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
201align 16
202BEGINPROC CPUMGCCallV86Code
203 mov ebp, [esp + 4] ; pRegFrame
204
205 ; construct iret stack frame
206 push dword [ebp + CPUMCTXCORE.gs]
207 push dword [ebp + CPUMCTXCORE.fs]
208 push dword [ebp + CPUMCTXCORE.ds]
209 push dword [ebp + CPUMCTXCORE.es]
210 push dword [ebp + CPUMCTXCORE.ss]
211 push dword [ebp + CPUMCTXCORE.esp]
212 push dword [ebp + CPUMCTXCORE.eflags]
213 push dword [ebp + CPUMCTXCORE.cs]
214 push dword [ebp + CPUMCTXCORE.eip]
215
216 ;
217 ; enable WP
218 ;
219%ifdef ENABLE_WRITE_PROTECTION
220 mov eax, cr0
221 or eax, X86_CR0_WRITE_PROTECT
222 mov cr0, eax
223%endif
224
225 ; restore CPU context (all except cs, eip, ss, esp, eflags, ds, es, fs & gs; which are restored or overwritten by iret)
226 mov eax, [ebp + CPUMCTXCORE.eax]
227 mov ebx, [ebp + CPUMCTXCORE.ebx]
228 mov ecx, [ebp + CPUMCTXCORE.ecx]
229 mov edx, [ebp + CPUMCTXCORE.edx]
230 mov esi, [ebp + CPUMCTXCORE.esi]
231 mov edi, [ebp + CPUMCTXCORE.edi]
232 mov ebp, [ebp + CPUMCTXCORE.ebp]
233
234 TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
235 iret
236ENDPROC CPUMGCCallV86Code
237
238;;
239; This is a main entry point for resuming (or starting) guest
240; code execution.
241;
242; We get here directly from VMMSwitcher.asm (jmp at the end
243; of VMMSwitcher_HostToGuest).
244;
245; This call never returns!
246;
247; @param edx Pointer to CPUM structure.
248;
249align 16
250BEGINPROC_EXPORTED CPUMGCResumeGuest
251 ;
252 ; Setup iretd
253 ;
254 push dword [edx + CPUM.Guest.ss]
255 push dword [edx + CPUM.Guest.esp]
256 push dword [edx + CPUM.Guest.eflags]
257 push dword [edx + CPUM.Guest.cs]
258 push dword [edx + CPUM.Guest.eip]
259
260 ;
261 ; Restore registers.
262 ;
263 TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_ES
264 mov es, [edx + CPUM.Guest.es]
265 TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_FS
266 mov fs, [edx + CPUM.Guest.fs]
267 TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_GS
268 mov gs, [edx + CPUM.Guest.gs]
269
270%ifdef VBOX_WITH_STATISTICS
271 ;
272 ; Statistics.
273 ;
274 push edx
275 mov edx, IMP(g_VM)
276 lea edx, [edx + VM.StatTotalQemuToGC]
277 STAM_PROFILE_ADV_STOP edx
278
279 mov edx, IMP(g_VM)
280 lea edx, [edx + VM.StatTotalInGC]
281 STAM_PROFILE_ADV_START edx
282 pop edx
283%endif
284
285 ;
286 ; enable WP
287 ;
288%ifdef ENABLE_WRITE_PROTECTION
289 mov eax, cr0
290 or eax, X86_CR0_WRITE_PROTECT
291 mov cr0, eax
292%endif
293
294 ;
295 ; Continue restore.
296 ;
297 mov esi, [edx + CPUM.Guest.esi]
298 mov edi, [edx + CPUM.Guest.edi]
299 mov ebp, [edx + CPUM.Guest.ebp]
300 mov ebx, [edx + CPUM.Guest.ebx]
301 mov ecx, [edx + CPUM.Guest.ecx]
302 mov eax, [edx + CPUM.Guest.eax]
303 push dword [edx + CPUM.Guest.ds]
304 mov edx, [edx + CPUM.Guest.edx]
305 TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_DS
306 pop ds
307
308 ; restart execution.
309 TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
310 iretd
311ENDPROC CPUMGCResumeGuest
312
313
314;;
315; This is a main entry point for resuming (or starting) guest
316; code execution for raw V86 mode
317;
318; We get here directly from VMMSwitcher.asm (jmp at the end
319; of VMMSwitcher_HostToGuest).
320;
321; This call never returns!
322;
323; @param edx Pointer to CPUM structure.
324;
325align 16
326BEGINPROC_EXPORTED CPUMGCResumeGuestV86
327 ;
328 ; Setup iretd
329 ;
330 push dword [edx + CPUM.Guest.gs]
331 push dword [edx + CPUM.Guest.fs]
332 push dword [edx + CPUM.Guest.ds]
333 push dword [edx + CPUM.Guest.es]
334
335 push dword [edx + CPUM.Guest.ss]
336 push dword [edx + CPUM.Guest.esp]
337
338 push dword [edx + CPUM.Guest.eflags]
339 push dword [edx + CPUM.Guest.cs]
340 push dword [edx + CPUM.Guest.eip]
341
342 ;
343 ; Restore registers.
344 ;
345
346%ifdef VBOX_WITH_STATISTICS
347 ;
348 ; Statistics.
349 ;
350 push edx
351 mov edx, IMP(g_VM)
352 lea edx, [edx + VM.StatTotalQemuToGC]
353 STAM_PROFILE_ADV_STOP edx
354
355 mov edx, IMP(g_VM)
356 lea edx, [edx + VM.StatTotalInGC]
357 STAM_PROFILE_ADV_START edx
358 pop edx
359%endif
360
361 ;
362 ; enable WP
363 ;
364%ifdef ENABLE_WRITE_PROTECTION
365 mov eax, cr0
366 or eax, X86_CR0_WRITE_PROTECT
367 mov cr0, eax
368%endif
369
370 ;
371 ; Continue restore.
372 ;
373 mov esi, [edx + CPUM.Guest.esi]
374 mov edi, [edx + CPUM.Guest.edi]
375 mov ebp, [edx + CPUM.Guest.ebp]
376 mov ecx, [edx + CPUM.Guest.ecx]
377 mov ebx, [edx + CPUM.Guest.ebx]
378 mov eax, [edx + CPUM.Guest.eax]
379 mov edx, [edx + CPUM.Guest.edx]
380
381 ; restart execution.
382 TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
383 iretd
384ENDPROC CPUMGCResumeGuestV86
385
386
387;;
388; Set the Guest CPU CR2 register.
389;
390; @param eax cr2
391; @uses edx
392;
393align 16
394BEGINPROC CPUMGCSetGuestCR2Asm
395 mov edx, IMP(g_CPUM)
396 mov [edx + CPUM.Guest.cr2], eax
397 ret
398ENDPROC CPUMGCSetGuestCR2Asm
399
400
401;;
402; Get the Guest CPU CR0 register.
403;
404; @returns cr0 in eax
405; @uses eax
406;
407align 16
408BEGINPROC CPUMGCGetGuestCR0
409 mov eax, IMP(g_CPUM)
410 mov eax, [eax + CPUM.Guest.cr0]
411 ret
412ENDPROC CPUMGCGetGuestCR0
413
414
415
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