VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMGC/PDMGCDevice.cpp@ 24138

Last change on this file since 24138 was 24138, checked in by vboxsync, 15 years ago

Missing Set/ClearInterruptFF cases for R0 & RC.
  • Property svn:eol-style set to native
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File size: 22.8 KB
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1/* $Id: PDMGCDevice.cpp 24138 2009-10-28 13:18:51Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, GC Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PDM_DEVICE
27#include "PDMInternal.h"
28#include <VBox/pdm.h>
29#include <VBox/pgm.h>
30#include <VBox/mm.h>
31#include <VBox/vm.h>
32#include <VBox/vmm.h>
33#include <VBox/patm.h>
34
35#include <VBox/log.h>
36#include <VBox/err.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/string.h>
40
41
42/*******************************************************************************
43* Global Variables *
44*******************************************************************************/
45RT_C_DECLS_BEGIN
46extern DECLEXPORT(const PDMDEVHLPRC) g_pdmRCDevHlp;
47extern DECLEXPORT(const PDMPICHLPRC) g_pdmRCPicHlp;
48extern DECLEXPORT(const PDMAPICHLPRC) g_pdmRCApicHlp;
49extern DECLEXPORT(const PDMIOAPICHLPRC) g_pdmRCIoApicHlp;
50extern DECLEXPORT(const PDMPCIHLPRC) g_pdmRCPciHlp;
51RT_C_DECLS_END
52
53
54/*******************************************************************************
55* Internal Functions *
56*******************************************************************************/
57/** @name GC Device Helpers
58 * @{
59 */
60static DECLCALLBACK(void) pdmGCDevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
61static DECLCALLBACK(void) pdmGCDevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
62static DECLCALLBACK(int) pdmGCDevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
63static DECLCALLBACK(int) pdmGCDevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
64static DECLCALLBACK(bool) pdmGCDevHlp_A20IsEnabled(PPDMDEVINS pDevIns);
65static DECLCALLBACK(int) pdmGCDevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...);
66static DECLCALLBACK(int) pdmGCDevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va);
67static DECLCALLBACK(int) pdmGCDevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...);
68static DECLCALLBACK(int) pdmGCDevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va);
69static DECLCALLBACK(int) pdmGCDevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData);
70static DECLCALLBACK(PVM) pdmGCDevHlp_GetVM(PPDMDEVINS pDevIns);
71static DECLCALLBACK(PVMCPU) pdmGCDevHlp_GetVMCPU(PPDMDEVINS pDevIns);
72/** @} */
73
74
75/** @name PIC GC Helpers
76 * @{
77 */
78static DECLCALLBACK(void) pdmRCPicHlp_SetInterruptFF(PPDMDEVINS pDevIns);
79static DECLCALLBACK(void) pdmRCPicHlp_ClearInterruptFF(PPDMDEVINS pDevIns);
80static DECLCALLBACK(int) pdmRCPicHlp_Lock(PPDMDEVINS pDevIns, int rc);
81static DECLCALLBACK(void) pdmRCPicHlp_Unlock(PPDMDEVINS pDevIns);
82/** @} */
83
84
85/** @name APIC RC Helpers
86 * @{
87 */
88static DECLCALLBACK(void) pdmRCApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu);
89static DECLCALLBACK(void) pdmRCApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu);
90static DECLCALLBACK(void) pdmRCApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion);
91static DECLCALLBACK(int) pdmRCApicHlp_Lock(PPDMDEVINS pDevIns, int rc);
92static DECLCALLBACK(void) pdmRCApicHlp_Unlock(PPDMDEVINS pDevIns);
93static DECLCALLBACK(VMCPUID) pdmRCApicHlp_GetCpuId(PPDMDEVINS pDevIns);
94/** @} */
95
96
97/** @name I/O APIC RC Helpers
98 * @{
99 */
100static DECLCALLBACK(int) pdmRCIoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
101 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode);
102static DECLCALLBACK(int) pdmRCIoApicHlp_Lock(PPDMDEVINS pDevIns, int rc);
103static DECLCALLBACK(void) pdmRCIoApicHlp_Unlock(PPDMDEVINS pDevIns);
104/** @} */
105
106
107/** @name PCI Bus RC Helpers
108 * @{
109 */
110static DECLCALLBACK(void) pdmRCPciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
111static DECLCALLBACK(void) pdmRCPciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
112static DECLCALLBACK(int) pdmRCPciHlp_Lock(PPDMDEVINS pDevIns, int rc);
113static DECLCALLBACK(void) pdmRCPciHlp_Unlock(PPDMDEVINS pDevIns);
114/** @} */
115
116
117static void pdmGCIsaSetIrq(PVM pVM, int iIrq, int iLevel);
118static void pdmGCIoApicSetIrq(PVM pVM, int iIrq, int iLevel);
119
120
121
122/**
123 * The Guest Context Device Helper Callbacks.
124 */
125extern DECLEXPORT(const PDMDEVHLPRC) g_pdmRCDevHlp =
126{
127 PDM_DEVHLPRC_VERSION,
128 pdmGCDevHlp_PCISetIrq,
129 pdmGCDevHlp_ISASetIrq,
130 pdmGCDevHlp_PhysRead,
131 pdmGCDevHlp_PhysWrite,
132 pdmGCDevHlp_A20IsEnabled,
133 pdmGCDevHlp_VMSetError,
134 pdmGCDevHlp_VMSetErrorV,
135 pdmGCDevHlp_VMSetRuntimeError,
136 pdmGCDevHlp_VMSetRuntimeErrorV,
137 pdmGCDevHlp_PATMSetMMIOPatchInfo,
138 pdmGCDevHlp_GetVM,
139 pdmGCDevHlp_GetVMCPU,
140 PDM_DEVHLPRC_VERSION
141};
142
143/**
144 * The Raw-Mode Context PIC Helper Callbacks.
145 */
146extern DECLEXPORT(const PDMPICHLPRC) g_pdmRCPicHlp =
147{
148 PDM_PICHLPRC_VERSION,
149 pdmRCPicHlp_SetInterruptFF,
150 pdmRCPicHlp_ClearInterruptFF,
151 pdmRCPicHlp_Lock,
152 pdmRCPicHlp_Unlock,
153 PDM_PICHLPRC_VERSION
154};
155
156
157/**
158 * The Raw-Mode Context APIC Helper Callbacks.
159 */
160extern DECLEXPORT(const PDMAPICHLPRC) g_pdmRCApicHlp =
161{
162 PDM_APICHLPRC_VERSION,
163 pdmRCApicHlp_SetInterruptFF,
164 pdmRCApicHlp_ClearInterruptFF,
165 pdmRCApicHlp_ChangeFeature,
166 pdmRCApicHlp_Lock,
167 pdmRCApicHlp_Unlock,
168 pdmRCApicHlp_GetCpuId,
169 PDM_APICHLPRC_VERSION
170};
171
172
173/**
174 * The Raw-Mode Context I/O APIC Helper Callbacks.
175 */
176extern DECLEXPORT(const PDMIOAPICHLPRC) g_pdmRCIoApicHlp =
177{
178 PDM_IOAPICHLPRC_VERSION,
179 pdmRCIoApicHlp_ApicBusDeliver,
180 pdmRCIoApicHlp_Lock,
181 pdmRCIoApicHlp_Unlock,
182 PDM_IOAPICHLPRC_VERSION
183};
184
185
186/**
187 * The Raw-Mode Context PCI Bus Helper Callbacks.
188 */
189extern DECLEXPORT(const PDMPCIHLPRC) g_pdmRCPciHlp =
190{
191 PDM_PCIHLPRC_VERSION,
192 pdmRCPciHlp_IsaSetIrq,
193 pdmRCPciHlp_IoApicSetIrq,
194 pdmRCPciHlp_Lock,
195 pdmRCPciHlp_Unlock,
196 PDM_PCIHLPRC_VERSION, /* the end */
197};
198
199
200
201
202/** @copydoc PDMDEVHLPRC::pfnPCISetIrq */
203static DECLCALLBACK(void) pdmGCDevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
204{
205 PDMDEV_ASSERT_DEVINS(pDevIns);
206 LogFlow(("pdmGCDevHlp_PCISetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
207
208 PVM pVM = pDevIns->Internal.s.pVMRC;
209 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceRC;
210 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBusRC;
211 if ( pPciDev
212 && pPciBus
213 && pPciBus->pDevInsRC)
214 {
215 pdmLock(pVM);
216 pPciBus->pfnSetIrqRC(pPciBus->pDevInsRC, pPciDev, iIrq, iLevel);
217 pdmUnlock(pVM);
218 }
219 else
220 {
221 /* queue for ring-3 execution. */
222 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueRC);
223 if (pTask)
224 {
225 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
226 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
227 pTask->u.SetIRQ.iIrq = iIrq;
228 pTask->u.SetIRQ.iLevel = iLevel;
229
230 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueRC, &pTask->Core, 0);
231 }
232 else
233 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
234 }
235
236 LogFlow(("pdmGCDevHlp_PCISetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance));
237}
238
239
240/** @copydoc PDMDEVHLPRC::pfnPCISetIrq */
241static DECLCALLBACK(void) pdmGCDevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
242{
243 PDMDEV_ASSERT_DEVINS(pDevIns);
244 LogFlow(("pdmGCDevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
245
246 pdmGCIsaSetIrq(pDevIns->Internal.s.pVMRC, iIrq, iLevel);
247
248 LogFlow(("pdmGCDevHlp_ISASetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance));
249}
250
251
252/** @copydoc PDMDEVHLPRC::pfnPhysRead */
253static DECLCALLBACK(int) pdmGCDevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
254{
255 PDMDEV_ASSERT_DEVINS(pDevIns);
256 LogFlow(("pdmGCDevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
257 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
258
259 int rc = PGMPhysRead(pDevIns->Internal.s.pVMRC, GCPhys, pvBuf, cbRead);
260 AssertRC(rc); /** @todo track down the users for this bugger. */
261
262 Log(("pdmGCDevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
263 return rc;
264}
265
266
267/** @copydoc PDMDEVHLPRC::pfnPhysWrite */
268static DECLCALLBACK(int) pdmGCDevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
269{
270 PDMDEV_ASSERT_DEVINS(pDevIns);
271 LogFlow(("pdmGCDevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
272 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
273
274 int rc = PGMPhysWrite(pDevIns->Internal.s.pVMRC, GCPhys, pvBuf, cbWrite);
275 AssertRC(rc); /** @todo track down the users for this bugger. */
276
277 Log(("pdmGCDevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
278 return rc;
279}
280
281
282/** @copydoc PDMDEVHLPRC::pfnA20IsEnabled */
283static DECLCALLBACK(bool) pdmGCDevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
284{
285 PDMDEV_ASSERT_DEVINS(pDevIns);
286 LogFlow(("pdmGCDevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
287
288 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu0(pDevIns->Internal.s.pVMRC));
289
290 Log(("pdmGCDevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
291 return fEnabled;
292}
293
294
295/** @copydoc PDMDEVHLPRC::pfnVMSetError */
296static DECLCALLBACK(int) pdmGCDevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
297{
298 PDMDEV_ASSERT_DEVINS(pDevIns);
299 va_list args;
300 va_start(args, pszFormat);
301 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMRC, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
302 va_end(args);
303 return rc;
304}
305
306
307/** @copydoc PDMDEVHLPRC::pfnVMSetErrorV */
308static DECLCALLBACK(int) pdmGCDevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
309{
310 PDMDEV_ASSERT_DEVINS(pDevIns);
311 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMRC, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
312 return rc;
313}
314
315
316/** @copydoc PDMDEVHLPRC::pfnVMSetRuntimeError */
317static DECLCALLBACK(int) pdmGCDevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
318{
319 PDMDEV_ASSERT_DEVINS(pDevIns);
320 va_list va;
321 va_start(va, pszFormat);
322 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMRC, fFlags, pszErrorId, pszFormat, va);
323 va_end(va);
324 return rc;
325}
326
327
328/** @copydoc PDMDEVHLPRC::pfnVMSetErrorV */
329static DECLCALLBACK(int) pdmGCDevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
330{
331 PDMDEV_ASSERT_DEVINS(pDevIns);
332 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMRC, fFlags, pszErrorId, pszFormat, va);
333 return rc;
334}
335
336
337/** @copydoc PDMDEVHLPRC::pfnPATMSetMMIOPatchInfo */
338static DECLCALLBACK(int) pdmGCDevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData)
339{
340 PDMDEV_ASSERT_DEVINS(pDevIns);
341 LogFlow(("pdmGCDevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
342
343 return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMRC, GCPhys, (RTRCPTR)pCachedData);
344}
345
346
347/** @copydoc PDMDEVHLPRC::pfnGetVM */
348static DECLCALLBACK(PVM) pdmGCDevHlp_GetVM(PPDMDEVINS pDevIns)
349{
350 PDMDEV_ASSERT_DEVINS(pDevIns);
351 LogFlow(("pdmGCDevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
352 return pDevIns->Internal.s.pVMRC;
353}
354
355
356/** @copydoc PDMDEVHLPRC::pfnGetVMCPU */
357static DECLCALLBACK(PVMCPU) pdmGCDevHlp_GetVMCPU(PPDMDEVINS pDevIns)
358{
359 PDMDEV_ASSERT_DEVINS(pDevIns);
360 LogFlow(("pdmGCDevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
361 return VMMGetCpu(pDevIns->Internal.s.pVMRC);
362}
363
364
365
366
367/** @copydoc PDMPICHLPGC::pfnSetInterruptFF */
368static DECLCALLBACK(void) pdmRCPicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
369{
370 PDMDEV_ASSERT_DEVINS(pDevIns);
371 PVM pVM = pDevIns->Internal.s.pVMRC;
372
373 if (pVM->pdm.s.Apic.pfnLocalInterruptRC)
374 {
375 LogFlow(("pdmRCPicHlp_SetInterruptFF: caller='%p'/%d: Setting local interrupt on LAPIC\n",
376 pDevIns, pDevIns->iInstance));
377 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
378 pVM->pdm.s.Apic.pfnLocalInterruptRC(pVM->pdm.s.Apic.pDevInsRC, 0, 1);
379 return;
380 }
381
382 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
383
384 LogFlow(("pdmRCPicHlp_SetInterruptFF: caller=%p/%d: VMMCPU_FF_INTERRUPT_PIC %d -> 1\n",
385 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
386
387 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
388}
389
390
391/** @copydoc PDMPICHLPGC::pfnClearInterruptFF */
392static DECLCALLBACK(void) pdmRCPicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
393{
394 PDMDEV_ASSERT_DEVINS(pDevIns);
395 PVM pVM = pDevIns->Internal.s.CTX_SUFF(pVM);
396
397 if (pVM->pdm.s.Apic.pfnLocalInterruptRC)
398 {
399 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
400 LogFlow(("pdmRCPicHlp_ClearInterruptFF: caller='%s'/%d: Clearing local interrupt on LAPIC\n",
401 pDevIns, pDevIns->iInstance));
402 /* Lower the LAPIC's LINT0 line instead of signaling the CPU directly. */
403 pVM->pdm.s.Apic.pfnLocalInterruptRC(pVM->pdm.s.Apic.pDevInsRC, 0, 0);
404 return;
405 }
406
407 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
408
409 LogFlow(("pdmRCPicHlp_ClearInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 0\n",
410 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
411
412 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
413}
414
415
416/** @copydoc PDMPICHLPGC::pfnLock */
417static DECLCALLBACK(int) pdmRCPicHlp_Lock(PPDMDEVINS pDevIns, int rc)
418{
419 PDMDEV_ASSERT_DEVINS(pDevIns);
420 return pdmLockEx(pDevIns->Internal.s.pVMRC, rc);
421}
422
423
424/** @copydoc PDMPICHLPGC::pfnUnlock */
425static DECLCALLBACK(void) pdmRCPicHlp_Unlock(PPDMDEVINS pDevIns)
426{
427 PDMDEV_ASSERT_DEVINS(pDevIns);
428 pdmUnlock(pDevIns->Internal.s.pVMRC);
429}
430
431
432
433
434/** @copydoc PDMAPICHLPRC::pfnSetInterruptFF */
435static DECLCALLBACK(void) pdmRCApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
436{
437 PDMDEV_ASSERT_DEVINS(pDevIns);
438 PVM pVM = pDevIns->Internal.s.pVMRC;
439 PVMCPU pVCpu = &pVM->aCpus[idCpu];
440
441 AssertReturnVoid(idCpu < pVM->cCpus);
442
443 LogFlow(("pdmRCApicHlp_SetInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 1\n",
444 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
445 switch (enmType)
446 {
447 case PDMAPICIRQ_HARDWARE:
448 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC);
449 break;
450 case PDMAPICIRQ_NMI:
451 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI);
452 break;
453 case PDMAPICIRQ_SMI:
454 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI);
455 break;
456 default:
457 AssertMsgFailed(("enmType=%d\n", enmType));
458 break;
459 }
460}
461
462
463/** @copydoc PDMAPICHLPRC::pfnClearInterruptFF */
464static DECLCALLBACK(void) pdmRCApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
465{
466 PDMDEV_ASSERT_DEVINS(pDevIns);
467 PVM pVM = pDevIns->Internal.s.pVMRC;
468 PVMCPU pVCpu = &pVM->aCpus[idCpu];
469
470 AssertReturnVoid(idCpu < pVM->cCpus);
471
472 LogFlow(("pdmRCApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n",
473 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
474
475 /* Note: NMI/SMI can't be cleared. */
476 switch (enmType)
477 {
478 case PDMAPICIRQ_HARDWARE:
479 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
480 break;
481 case PDMAPICIRQ_EXTINT:
482 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
483 break;
484 default:
485 AssertMsgFailed(("enmType=%d\n", enmType));
486 break;
487 }
488}
489
490
491/** @copydoc PDMAPICHLPRC::pfnChangeFeature */
492static DECLCALLBACK(void) pdmRCApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion)
493{
494 PDMDEV_ASSERT_DEVINS(pDevIns);
495 LogFlow(("pdmRCApicHlp_ChangeFeature: caller=%p/%d: version=%d\n", pDevIns, pDevIns->iInstance, (int)enmVersion));
496 switch (enmVersion)
497 {
498 case PDMAPICVERSION_NONE:
499 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_APIC);
500 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_X2APIC);
501 break;
502 case PDMAPICVERSION_APIC:
503 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_APIC);
504 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_X2APIC);
505 break;
506 case PDMAPICVERSION_X2APIC:
507 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_X2APIC);
508 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_APIC);
509 break;
510 default:
511 AssertMsgFailed(("Unknown APIC version: %d\n", (int)enmVersion));
512 }
513}
514
515
516/** @copydoc PDMAPICHLPRC::pfnLock */
517static DECLCALLBACK(int) pdmRCApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
518{
519 PDMDEV_ASSERT_DEVINS(pDevIns);
520 return pdmLockEx(pDevIns->Internal.s.pVMRC, rc);
521}
522
523
524/** @copydoc PDMAPICHLPRC::pfnUnlock */
525static DECLCALLBACK(void) pdmRCApicHlp_Unlock(PPDMDEVINS pDevIns)
526{
527 PDMDEV_ASSERT_DEVINS(pDevIns);
528 pdmUnlock(pDevIns->Internal.s.pVMRC);
529}
530
531
532/** @copydoc PDMAPICHLPRC::pfnGetCpuId */
533static DECLCALLBACK(VMCPUID) pdmRCApicHlp_GetCpuId(PPDMDEVINS pDevIns)
534{
535 PDMDEV_ASSERT_DEVINS(pDevIns);
536 return VMMGetCpuId(pDevIns->Internal.s.pVMRC);
537}
538
539
540
541
542/** @copydoc PDMIOAPICHLPRC::pfnApicBusDeliver */
543static DECLCALLBACK(int) pdmRCIoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
544 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode)
545{
546 PDMDEV_ASSERT_DEVINS(pDevIns);
547 PVM pVM = pDevIns->Internal.s.pVMRC;
548 LogFlow(("pdmRCIoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8\n",
549 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
550 if (pVM->pdm.s.Apic.pfnBusDeliverRC)
551 return pVM->pdm.s.Apic.pfnBusDeliverRC(pVM->pdm.s.Apic.pDevInsRC, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
552 return VINF_SUCCESS;
553}
554
555
556/** @copydoc PDMIOAPICHLPRC::pfnLock */
557static DECLCALLBACK(int) pdmRCIoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
558{
559 PDMDEV_ASSERT_DEVINS(pDevIns);
560 return pdmLockEx(pDevIns->Internal.s.pVMRC, rc);
561}
562
563
564/** @copydoc PDMIOAPICHLPRC::pfnUnlock */
565static DECLCALLBACK(void) pdmRCIoApicHlp_Unlock(PPDMDEVINS pDevIns)
566{
567 PDMDEV_ASSERT_DEVINS(pDevIns);
568 pdmUnlock(pDevIns->Internal.s.pVMRC);
569}
570
571
572
573
574/** @copydoc PDMPCIHLPRC::pfnIsaSetIrq */
575static DECLCALLBACK(void) pdmRCPciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
576{
577 PDMDEV_ASSERT_DEVINS(pDevIns);
578 Log4(("pdmRCPciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
579 pdmGCIsaSetIrq(pDevIns->Internal.s.pVMRC, iIrq, iLevel);
580}
581
582
583/** @copydoc PDMPCIHLPRC::pfnIoApicSetIrq */
584static DECLCALLBACK(void) pdmRCPciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
585{
586 PDMDEV_ASSERT_DEVINS(pDevIns);
587 Log4(("pdmRCPciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
588 pdmGCIoApicSetIrq(pDevIns->Internal.s.pVMRC, iIrq, iLevel);
589}
590
591
592/** @copydoc PDMPCIHLPRC::pfnLock */
593static DECLCALLBACK(int) pdmRCPciHlp_Lock(PPDMDEVINS pDevIns, int rc)
594{
595 PDMDEV_ASSERT_DEVINS(pDevIns);
596 return pdmLockEx(pDevIns->Internal.s.pVMRC, rc);
597}
598
599
600/** @copydoc PDMPCIHLPRC::pfnUnlock */
601static DECLCALLBACK(void) pdmRCPciHlp_Unlock(PPDMDEVINS pDevIns)
602{
603 PDMDEV_ASSERT_DEVINS(pDevIns);
604 pdmUnlock(pDevIns->Internal.s.pVMRC);
605}
606
607
608
609
610/**
611 * Sets an irq on the I/O APIC.
612 *
613 * @param pVM The VM handle.
614 * @param iIrq The irq.
615 * @param iLevel The new level.
616 */
617static void pdmGCIsaSetIrq(PVM pVM, int iIrq, int iLevel)
618{
619 if ( ( pVM->pdm.s.IoApic.pDevInsRC
620 || !pVM->pdm.s.IoApic.pDevInsR3)
621 && ( pVM->pdm.s.Pic.pDevInsRC
622 || !pVM->pdm.s.Pic.pDevInsR3))
623 {
624 pdmLock(pVM);
625 if (pVM->pdm.s.Pic.pDevInsRC)
626 pVM->pdm.s.Pic.pfnSetIrqRC(pVM->pdm.s.Pic.pDevInsRC, iIrq, iLevel);
627 if (pVM->pdm.s.IoApic.pDevInsRC)
628 pVM->pdm.s.IoApic.pfnSetIrqRC(pVM->pdm.s.IoApic.pDevInsRC, iIrq, iLevel);
629 pdmUnlock(pVM);
630 }
631 else
632 {
633 /* queue for ring-3 execution. */
634 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueRC);
635 if (pTask)
636 {
637 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
638 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
639 pTask->u.SetIRQ.iIrq = iIrq;
640 pTask->u.SetIRQ.iLevel = iLevel;
641
642 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueRC, &pTask->Core, 0);
643 }
644 else
645 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
646 }
647}
648
649
650/**
651 * Sets an irq on the I/O APIC.
652 *
653 * @param pVM The VM handle.
654 * @param iIrq The irq.
655 * @param iLevel The new level.
656 */
657static void pdmGCIoApicSetIrq(PVM pVM, int iIrq, int iLevel)
658{
659 if (pVM->pdm.s.IoApic.pDevInsRC)
660 {
661 pdmLock(pVM);
662 pVM->pdm.s.IoApic.pfnSetIrqRC(pVM->pdm.s.IoApic.pDevInsRC, iIrq, iLevel);
663 pdmUnlock(pVM);
664 }
665 else if (pVM->pdm.s.IoApic.pDevInsR3)
666 {
667 /* queue for ring-3 execution. */
668 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueRC);
669 if (pTask)
670 {
671 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
672 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
673 pTask->u.SetIRQ.iIrq = iIrq;
674 pTask->u.SetIRQ.iLevel = iLevel;
675
676 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueRC, &pTask->Core, 0);
677 }
678 else
679 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
680 }
681}
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