SELMGC.cpp@ 1868

Last change on this file since 1868 was 1822, checked in by vboxsync, 18 years ago
Log writes to shadow tables (gdt, idt, ldt, tss)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 16.2 KB

Line
1	/* $Id: SELMGC.cpp 1822 2007-03-30 11:15:23Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager, Guest Context.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_SELM
26	#include <VBox/selm.h>
27	#include <VBox/mm.h>
28	#include <VBox/em.h>
29	#include <VBox/trpm.h>
30	#include "SELMInternal.h"
31	#include <VBox/vm.h>
32	#include <VBox/pgm.h>
33
34	#include <VBox/param.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <iprt/assert.h>
38	#include <iprt/asm.h>
39
40
41	/**
42	* Synchronizes one GDT entry (guest -> shadow).
43	*
44	* @returns VBox status code (appropriate for trap handling and GC return).
45	* @param pVM VM Handle.
46	* @param pRegFrame Trap register frame.
47	* @param iGDTEntry The GDT entry to sync.
48	*/
49	static int selmGCSyncGDTEntry(PVM pVM, PCPUMCTXCORE pRegFrame, unsigned iGDTEntry)
50	{
51	Log2(("GDT %04X LDTR=%04X\n", iGDTEntry, CPUMGetGuestLDTR(pVM)));
52
53	/*
54	* Validate the offset.
55	*/
56	VBOXGDTR GdtrGuest;
57	CPUMGetGuestGDTR(pVM, &GdtrGuest);
58	unsigned offEntry = iGDTEntry * sizeof(VBOXDESC);
59	if ( iGDTEntry >= SELM_GDT_ELEMENTS
60	\|\| offEntry > GdtrGuest.cbGdt)
61	return VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
62
63	/*
64	* Read the guest descriptor.
65	*/
66	VBOXDESC Desc;
67	int rc = MMGCRamRead(pVM, &Desc, (uint8_t *)GdtrGuest.pGdt + offEntry, sizeof(VBOXDESC));
68	if (VBOX_FAILURE(rc))
69	return VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
70
71	/*
72	* Check for conflicts.
73	*/
74	RTSEL Sel = iGDTEntry << X86_SEL_SHIFT;
75	Assert( !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] & ~X86_SEL_MASK)
76	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] & ~X86_SEL_MASK)
77	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] & ~X86_SEL_MASK)
78	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] & ~X86_SEL_MASK)
79	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] & ~X86_SEL_MASK));
80	if ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == Sel
81	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == Sel
82	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == Sel
83	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == Sel
84	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == Sel)
85	{
86	if (Desc.Gen.u1Present)
87	{
88	Log(("selmGCSyncGDTEntry: Sel=%d Desc=%.8Vhxs: detected conflict!!\n", Sel, &Desc));
89	return VINF_SELM_SYNC_GDT;
90	}
91	Log(("selmGCSyncGDTEntry: Sel=%d Desc=%.8Vhxs: potential conflict (still not present)!\n", Sel, &Desc));
92
93	/* Note: we can't continue below or else we'll change the shadow descriptor!! */
94	/* When the guest makes the selector present, then we'll do a GDT sync. */
95	return VINF_SUCCESS;
96	}
97
98	/*
99	* Code and data selectors are generally 1:1, with the
100	* 'little' adjustment we do for DPL 0 selectors.
101	*/
102	PVBOXDESC pShadowDescr = &pVM->selm.s.paGdtGC[iGDTEntry];
103	if (Desc.Gen.u1DescType)
104	{
105	/*
106	* Hack for A-bit against Trap E on read-only GDT.
107	*/
108	/** @todo Fix this by loading ds and cs before turning off WP. */
109	Desc.Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
110
111	/*
112	* All DPL 0 code and data segments are squeezed into DPL 1.
113	*
114	* We're skipping conforming segments here because those
115	* cannot give us any trouble.
116	*/
117	if ( Desc.Gen.u2Dpl == 0
118	&& (Desc.Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
119	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF) )
120	Desc.Gen.u2Dpl = 1;
121	}
122	else
123	{
124	/*
125	* System type selectors are marked not present.
126	* Recompiler or special handling is required for these.
127	*/
128	/** @todo what about interrupt gates and rawr0? */
129	Desc.Gen.u1Present = 0;
130	}
131	//Log(("O: base=%08X limit=%08X attr=%04X\n", pShadowDescr->Gen.u16BaseLow \| (pShadowDescr->Gen.u8BaseHigh1 << 16) \| (pShadowDescr->Gen.u8BaseHigh2 << 24), pShadowDescr->Gen.u16LimitLow \| (pShadowDescr->Gen.u4LimitHigh << 16), (pShadowDescr->au32[1] >> 8) & 0xFFFF ));
132	//Log(("N: base=%08X limit=%08X attr=%04X\n", Desc.Gen.u16BaseLow \| (Desc.Gen.u8BaseHigh1 << 16) \| (Desc.Gen.u8BaseHigh2 << 24), Desc.Gen.u16LimitLow \| (Desc.Gen.u4LimitHigh << 16), (Desc.au32[1] >> 8) & 0xFFFF ));
133	*pShadowDescr = Desc;
134
135	/* Check if we change the LDT selector */
136	if (Sel == CPUMGetGuestLDTR(pVM))
137	{
138	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
139	return VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT;
140	}
141
142	/* Or the TR selector */
143	if (Sel == CPUMGetGuestTR(pVM))
144	{
145	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
146	return VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT;
147	}
148
149	return VINF_SUCCESS;
150	}
151
152
153	/**
154	* \#PF Virtual Handler callback for Guest write access to the Guest's own GDT.
155	*
156	* @returns VBox status code (appropriate for trap handling and GC return).
157	* @param pVM VM Handle.
158	* @param uErrorCode CPU Error code.
159	* @param pRegFrame Trap register frame.
160	* @param pvFault The fault address (cr2).
161	* @param pvRange The base address of the handled virtual range.
162	* @param offRange The offset of the access into this range.
163	* (If it's a EIP range this's the EIP, if not it's pvFault.)
164	*/
165	SELMGCDECL(int) selmgcGuestGDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, void pvRange, uintptr_t offRange)
166	{
167	LogFlow(("selmgcGuestGDTWriteHandler errcode=%x fault=%08x offRange=%08x\n", uErrorCode, pvFault, offRange));
168
169	/*
170	* First check if this is the LDT entry.
171	* LDT updates are problemous since an invalid LDT entry will cause trouble during worldswitch.
172	*/
173	int rc;
174	if (CPUMGetGuestLDTR(pVM) / sizeof(VBOXDESC) == offRange / sizeof(VBOXDESC))
175	{
176	Log(("LDTR selector change -> fall back to HC!!\n"));
177	rc = VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
178	/** @todo We're not handling changed to the selectors in LDTR and TR correctly at all.
179	* We should ignore any changes to those and sync them only when they are loaded by the guest! */
180	}
181	else
182	{
183	/*
184	* Attempt to emulate the instruction and sync the affected entries.
185	*/
186	/** @todo should check if any affected selectors are loaded. */
187	uint32_t cb;
188	rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
189	if (VBOX_SUCCESS(rc) && cb)
190	{
191	unsigned iGDTE1 = offRange / sizeof(VBOXDESC);
192	int rc2 = selmGCSyncGDTEntry(pVM, pRegFrame, iGDTE1);
193	if (rc2 == VINF_SUCCESS)
194	{
195	Assert(cb);
196	unsigned iGDTE2 = (offRange + cb - 1) / sizeof(VBOXDESC);
197	if (iGDTE1 != iGDTE2)
198	rc2 = selmGCSyncGDTEntry(pVM, pRegFrame, iGDTE2);
199	if (rc2 == VINF_SUCCESS)
200	{
201	STAM_COUNTER_INC(&pVM->selm.s.StatGCWriteGuestGDTHandled);
202	return rc;
203	}
204	}
205	if (rc == VINF_SUCCESS \|\| VBOX_FAILURE(rc2))
206	rc = rc2;
207	}
208	else
209	{
210	Assert(VBOX_FAILURE(rc));
211	if (rc == VERR_EM_INTERPRETER)
212	rc = VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
213	}
214	}
215	if ( rc != VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT
216	&& rc != VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT)
217	{
218	/* Not necessary when we need to go back to the host context to sync the LDT or TSS. */
219	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
220	}
221	STAM_COUNTER_INC(&pVM->selm.s.StatGCWriteGuestGDTUnhandled);
222	return rc;
223	}
224
225
226	/**
227	* \#PF Virtual Handler callback for Guest write access to the Guest's own LDT.
228	*
229	* @returns VBox status code (appropriate for trap handling and GC return).
230	* @param pVM VM Handle.
231	* @param uErrorCode CPU Error code.
232	* @param pRegFrame Trap register frame.
233	* @param pvFault The fault address (cr2).
234	* @param pvRange The base address of the handled virtual range.
235	* @param offRange The offset of the access into this range.
236	* (If it's a EIP range this's the EIP, if not it's pvFault.)
237	*/
238	SELMGCDECL(int) selmgcGuestLDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, void pvRange, uintptr_t offRange)
239	{
240	/** @todo To be implemented. */
241	////LogCom(("selmgcGuestLDTWriteHandler: eip=%08X pvFault=%08X pvRange=%08X\r\n", pRegFrame->eip, pvFault, pvRange));
242
243	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
244	STAM_COUNTER_INC(&pVM->selm.s.StatGCWriteGuestLDT);
245	return VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT;
246	}
247
248
249	/**
250	* \#PF Virtual Handler callback for Guest write access to the Guest's own current TSS.
251	*
252	* @returns VBox status code (appropriate for trap handling and GC return).
253	* @param pVM VM Handle.
254	* @param uErrorCode CPU Error code.
255	* @param pRegFrame Trap register frame.
256	* @param pvFault The fault address (cr2).
257	* @param pvRange The base address of the handled virtual range.
258	* @param offRange The offset of the access into this range.
259	* (If it's a EIP range this's the EIP, if not it's pvFault.)
260	*/
261	SELMGCDECL(int) selmgcGuestTSSWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, void pvRange, uintptr_t offRange)
262	{
263	LogFlow(("selmgcGuestTSSWriteHandler errcode=%x fault=%08x offRange=%08x\n", uErrorCode, pvFault, offRange));
264
265	/*
266	* Try emulate the access and compare the R0 ss:esp with the shadow tss values.
267	*
268	* Note, that it's safe to access the TSS after a successfull instruction emulation,
269	* even if the stuff that was changed wasn't the ss0 or esp0 bits. The CPU insists
270	* on the TSS being all one physical page, so ASSUMING that we're not trapping
271	* I/O map accesses this is safe.
272	*/
273	uint32_t cb;
274	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
275	if (VBOX_SUCCESS(rc) && cb)
276	{
277	PCVBOXTSS pGuestTSS = (PVBOXTSS)pVM->selm.s.GCPtrGuestTss;
278	if ( pGuestTSS->esp0 != pVM->selm.s.Tss.esp1
279	\|\| pGuestTSS->ss0 != (pVM->selm.s.Tss.ss1 & ~1)) /* undo raw-r0 */
280	{
281	Log(("selmgcGuestTSSWriteHandler: R0 stack: %RTsel:%VGv -> %RTsel:%VGv\n",
282	(RTSEL)(pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1, (RTSEL)pGuestTSS->ss0, pGuestTSS->esp0));
283	pVM->selm.s.Tss.esp1 = pGuestTSS->esp0;
284	pVM->selm.s.Tss.ss1 = pGuestTSS->ss0 \| 1;
285	STAM_COUNTER_INC(&pVM->selm.s.StatGCWriteGuestTSSHandledChanged);
286	}
287	if (CPUMGetGuestCR4(pVM) & X86_CR4_VME)
288	{
289	uint32_t offIntRedirBitmap = pGuestTSS->offIoBitmap - sizeof(pVM->selm.s.Tss.IntRedirBitmap);
290
291	/** @todo not sure how the partial case is handled; probably not allowed */
292	if ( offIntRedirBitmap <= offRange
293	&& offIntRedirBitmap + sizeof(pVM->selm.s.Tss.IntRedirBitmap) >= offRange + cb
294	&& offIntRedirBitmap + sizeof(pVM->selm.s.Tss.IntRedirBitmap) <= pVM->selm.s.cbGuestTss)
295	{
296	Log(("offIoBitmap=%x offIntRedirBitmap=%x cbTSS=%x\n", pGuestTSS->offIoBitmap, offIntRedirBitmap, pVM->selm.s.cbGuestTss));
297	/** @todo only update the changed part. */
298	for (uint32_t i = 0; i < sizeof(pVM->selm.s.Tss.IntRedirBitmap) / 8;i++)
299	{
300	rc = MMGCRamRead(pVM, &pVM->selm.s.Tss.IntRedirBitmap[i * 8], (uint8_t )pGuestTSS + offIntRedirBitmap + i 8, 8);
301	if (VBOX_FAILURE(rc))
302	{
303	/* Shadow page table might be out of sync */
304	rc = PGMPrefetchPage(pVM, (uint8_t )pGuestTSS + offIntRedirBitmap + i8);
305	if (VBOX_FAILURE(rc))
306	{
307	AssertMsg(rc == VINF_SUCCESS, ("PGMPrefetchPage %VGv failed with %Vrc\n", (uint8_t )pGuestTSS + offIntRedirBitmap + i8, rc));
308	break;
309	}
310	rc = MMGCRamRead(pVM, &pVM->selm.s.Tss.IntRedirBitmap[i * 8], (uint8_t )pGuestTSS + offIntRedirBitmap + i 8, 8);
311	}
312	AssertMsg(rc == VINF_SUCCESS, ("MMGCRamRead %VGv failed with %Vrc\n", (uint8_t )pGuestTSS + offIntRedirBitmap + i 8, rc));
313	}
314	STAM_COUNTER_INC(&pVM->selm.s.StatGCWriteGuestTSSRedir);
315	}
316	}
317	STAM_COUNTER_INC(&pVM->selm.s.StatGCWriteGuestTSSHandled);
318	}
319	else
320	{
321	Assert(VBOX_FAILURE(rc));
322	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
323	STAM_COUNTER_INC(&pVM->selm.s.StatGCWriteGuestTSSUnhandled);
324	if (rc == VERR_EM_INTERPRETER)
325	rc = VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT;
326	}
327	return rc;
328	}
329
330
331
332	/**
333	* \#PF Virtual Handler callback for Guest write access to the VBox shadow GDT.
334	*
335	* @returns VBox status code (appropriate for trap handling and GC return).
336	* @param pVM VM Handle.
337	* @param uErrorCode CPU Error code.
338	* @param pRegFrame Trap register frame.
339	* @param pvFault The fault address (cr2).
340	* @param pvRange The base address of the handled virtual range.
341	* @param offRange The offset of the access into this range.
342	* (If it's a EIP range this's the EIP, if not it's pvFault.)
343	*/
344	SELMGCDECL(int) selmgcShadowGDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, void pvRange, uintptr_t offRange)
345	{
346	LogRel(("FATAL ERROR: selmgcShadowGDTWriteHandler: eip=%08X pvFault=%08X pvRange=%08X\r\n", pRegFrame->eip, pvFault, pvRange));
347	return VERR_SELM_SHADOW_GDT_WRITE;
348	}
349
350	/**
351	* \#PF Virtual Handler callback for Guest write access to the VBox shadow LDT.
352	*
353	* @returns VBox status code (appropriate for trap handling and GC return).
354	* @param pVM VM Handle.
355	* @param uErrorCode CPU Error code.
356	* @param pRegFrame Trap register frame.
357	* @param pvFault The fault address (cr2).
358	* @param pvRange The base address of the handled virtual range.
359	* @param offRange The offset of the access into this range.
360	* (If it's a EIP range this's the EIP, if not it's pvFault.)
361	*/
362	SELMGCDECL(int) selmgcShadowLDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, void pvRange, uintptr_t offRange)
363	{
364	LogRel(("FATAL ERROR: selmgcShadowLDTWriteHandler: eip=%08X pvFault=%08X pvRange=%08X\r\n", pRegFrame->eip, pvFault, pvRange));
365	Assert(pvFault >= pVM->selm.s.GCPtrLdt && (uintptr_t)pvFault < (uintptr_t)pVM->selm.s.GCPtrLdt + 65536 + PAGE_SIZE);
366	return VERR_SELM_SHADOW_LDT_WRITE;
367	}
368
369	/**
370	* \#PF Virtual Handler callback for Guest write access to the VBox shadow TSS.
371	*
372	* @returns VBox status code (appropriate for trap handling and GC return).
373	* @param pVM VM Handle.
374	* @param uErrorCode CPU Error code.
375	* @param pRegFrame Trap register frame.
376	* @param pvFault The fault address (cr2).
377	* @param pvRange The base address of the handled virtual range.
378	* @param offRange The offset of the access into this range.
379	* (If it's a EIP range this's the EIP, if not it's pvFault.)
380	*/
381	SELMGCDECL(int) selmgcShadowTSSWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, void pvRange, uintptr_t offRange)
382	{
383	LogRel(("FATAL ERROR: selmgcShadowTSSWriteHandler: eip=%08X pvFault=%08X pvRange=%08X\r\n", pRegFrame->eip, pvFault, pvRange));
384	return VERR_SELM_SHADOW_TSS_WRITE;
385	}
386

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMGC/SELMGC.cpp@ 1868

Download in other formats: