SELMGC.cpp@ 29676

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1	/* $Id: SELMGC.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager, Guest Context.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_SELM
22	#include <VBox/selm.h>
23	#include <VBox/mm.h>
24	#include <VBox/em.h>
25	#include <VBox/trpm.h>
26	#include "SELMInternal.h"
27	#include <VBox/vm.h>
28	#include <VBox/vmm.h>
29	#include <VBox/pgm.h>
30
31	#include <VBox/param.h>
32	#include <VBox/err.h>
33	#include <VBox/log.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36
37
38	/**
39	* Synchronizes one GDT entry (guest -> shadow).
40	*
41	* @returns VBox status code (appropriate for trap handling and GC return).
42	* @param pVM VM Handle.
43	* @param pRegFrame Trap register frame.
44	* @param iGDTEntry The GDT entry to sync.
45	*/
46	static int selmGCSyncGDTEntry(PVM pVM, PCPUMCTXCORE pRegFrame, unsigned iGDTEntry)
47	{
48	PVMCPU pVCpu = VMMGetCpu0(pVM);
49
50	Log2(("GDT %04X LDTR=%04X\n", iGDTEntry, CPUMGetGuestLDTR(pVCpu)));
51
52	/*
53	* Validate the offset.
54	*/
55	VBOXGDTR GdtrGuest;
56	CPUMGetGuestGDTR(pVCpu, &GdtrGuest);
57	unsigned offEntry = iGDTEntry * sizeof(X86DESC);
58	if ( iGDTEntry >= SELM_GDT_ELEMENTS
59	\|\| offEntry > GdtrGuest.cbGdt)
60	return VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
61
62	/*
63	* Read the guest descriptor.
64	*/
65	X86DESC Desc;
66	int rc = MMGCRamRead(pVM, &Desc, (uint8_t *)(uintptr_t)GdtrGuest.pGdt + offEntry, sizeof(X86DESC));
67	if (RT_FAILURE(rc))
68	return VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
69
70	/*
71	* Check for conflicts.
72	*/
73	RTSEL Sel = iGDTEntry << X86_SEL_SHIFT;
74	Assert( !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] & ~X86_SEL_MASK)
75	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] & ~X86_SEL_MASK)
76	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] & ~X86_SEL_MASK)
77	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] & ~X86_SEL_MASK)
78	&& !(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] & ~X86_SEL_MASK));
79	if ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == Sel
80	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == Sel
81	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == Sel
82	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == Sel
83	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == Sel)
84	{
85	if (Desc.Gen.u1Present)
86	{
87	Log(("selmGCSyncGDTEntry: Sel=%d Desc=%.8Rhxs: detected conflict!!\n", Sel, &Desc));
88	return VINF_SELM_SYNC_GDT;
89	}
90	Log(("selmGCSyncGDTEntry: Sel=%d Desc=%.8Rhxs: potential conflict (still not present)!\n", Sel, &Desc));
91
92	/* Note: we can't continue below or else we'll change the shadow descriptor!! */
93	/* When the guest makes the selector present, then we'll do a GDT sync. */
94	return VINF_SUCCESS;
95	}
96
97	/*
98	* Code and data selectors are generally 1:1, with the
99	* 'little' adjustment we do for DPL 0 selectors.
100	*/
101	PX86DESC pShadowDescr = &pVM->selm.s.paGdtRC[iGDTEntry];
102	if (Desc.Gen.u1DescType)
103	{
104	/*
105	* Hack for A-bit against Trap E on read-only GDT.
106	*/
107	/** @todo Fix this by loading ds and cs before turning off WP. */
108	Desc.Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
109
110	/*
111	* All DPL 0 code and data segments are squeezed into DPL 1.
112	*
113	* We're skipping conforming segments here because those
114	* cannot give us any trouble.
115	*/
116	if ( Desc.Gen.u2Dpl == 0
117	&& (Desc.Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
118	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF) )
119	Desc.Gen.u2Dpl = 1;
120	}
121	else
122	{
123	/*
124	* System type selectors are marked not present.
125	* Recompiler or special handling is required for these.
126	*/
127	/** @todo what about interrupt gates and rawr0? */
128	Desc.Gen.u1Present = 0;
129	}
130	//Log(("O: base=%08X limit=%08X attr=%04X\n", X86DESC_BASE(pShadowDescr)), X86DESC_LIMIT(pShadowDescr), (pShadowDescr->au32[1] >> 8) & 0xFFFF ));
131	//Log(("N: base=%08X limit=%08X attr=%04X\n", X86DESC_BASE(Desc)), X86DESC_LIMIT(Desc), (Desc.au32[1] >> 8) & 0xFFFF ));
132	*pShadowDescr = Desc;
133
134	/* Check if we change the LDT selector */
135	if (Sel == CPUMGetGuestLDTR(pVCpu)) /** @todo this isn't correct in two(+) ways! 1. It shouldn't be done until the LDTR is reloaded. 2. It caused the next instruction to be emulated. */
136	{
137	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
138	return VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT;
139	}
140
141	#ifdef LOG_ENABLED
142	if (Sel == (pRegFrame->cs & X86_SEL_MASK))
143	Log(("GDT write to selector in CS register %04X\n", pRegFrame->cs));
144	else if (Sel == (pRegFrame->ds & X86_SEL_MASK))
145	Log(("GDT write to selector in DS register %04X\n", pRegFrame->ds));
146	else if (Sel == (pRegFrame->es & X86_SEL_MASK))
147	Log(("GDT write to selector in ES register %04X\n", pRegFrame->es));
148	else if (Sel == (pRegFrame->fs & X86_SEL_MASK))
149	Log(("GDT write to selector in FS register %04X\n", pRegFrame->fs));
150	else if (Sel == (pRegFrame->gs & X86_SEL_MASK))
151	Log(("GDT write to selector in GS register %04X\n", pRegFrame->gs));
152	else if (Sel == (pRegFrame->ss & X86_SEL_MASK))
153	Log(("GDT write to selector in SS register %04X\n", pRegFrame->ss));
154	#endif
155	return VINF_SUCCESS;
156	}
157
158
159	/**
160	* \#PF Virtual Handler callback for Guest write access to the Guest's own GDT.
161	*
162	* @returns VBox status code (appropriate for trap handling and GC return).
163	* @param pVM VM Handle.
164	* @param uErrorCode CPU Error code.
165	* @param pRegFrame Trap register frame.
166	* @param pvFault The fault address (cr2).
167	* @param pvRange The base address of the handled virtual range.
168	* @param offRange The offset of the access into this range.
169	* (If it's a EIP range this's the EIP, if not it's pvFault.)
170	*/
171	VMMRCDECL(int) selmRCGuestGDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
172	{
173	PVMCPU pVCpu = VMMGetCpu0(pVM);
174
175	LogFlow(("selmRCGuestGDTWriteHandler errcode=%x fault=%RGv offRange=%08x\n", (uint32_t)uErrorCode, pvFault, offRange));
176
177	/*
178	* First check if this is the LDT entry.
179	* LDT updates are problemous since an invalid LDT entry will cause trouble during worldswitch.
180	*/
181	int rc;
182	if (CPUMGetGuestLDTR(pVCpu) / sizeof(X86DESC) == offRange / sizeof(X86DESC))
183	{
184	Log(("LDTR selector change -> fall back to HC!!\n"));
185	rc = VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
186	/** @todo We're not handling changed to the selectors in LDTR and TR correctly at all.
187	* We should ignore any changes to those and sync them only when they are loaded by the guest! */
188	}
189	else
190	{
191	/*
192	* Attempt to emulate the instruction and sync the affected entries.
193	*/
194	/** @todo should check if any affected selectors are loaded. */
195	uint32_t cb;
196	rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, (RTGCPTR)(RTRCUINTPTR)pvFault, &cb);
197	if (RT_SUCCESS(rc) && cb)
198	{
199	unsigned iGDTE1 = offRange / sizeof(X86DESC);
200	int rc2 = selmGCSyncGDTEntry(pVM, pRegFrame, iGDTE1);
201	if (rc2 == VINF_SUCCESS)
202	{
203	Assert(cb);
204	unsigned iGDTE2 = (offRange + cb - 1) / sizeof(X86DESC);
205	if (iGDTE1 != iGDTE2)
206	rc2 = selmGCSyncGDTEntry(pVM, pRegFrame, iGDTE2);
207	if (rc2 == VINF_SUCCESS)
208	{
209	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestGDTHandled);
210	return rc;
211	}
212	}
213	if (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2))
214	rc = rc2;
215	}
216	else
217	{
218	Assert(RT_FAILURE(rc));
219	if (rc == VERR_EM_INTERPRETER)
220	rc = VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT;
221	}
222	}
223	if ( rc != VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT
224	&& rc != VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT)
225	{
226	/* Not necessary when we need to go back to the host context to sync the LDT or TSS. */
227	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
228	}
229	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestGDTUnhandled);
230	return rc;
231	}
232
233
234	/**
235	* \#PF Virtual Handler callback for Guest write access to the Guest's own LDT.
236	*
237	* @returns VBox status code (appropriate for trap handling and GC return).
238	* @param pVM VM Handle.
239	* @param uErrorCode CPU Error code.
240	* @param pRegFrame Trap register frame.
241	* @param pvFault The fault address (cr2).
242	* @param pvRange The base address of the handled virtual range.
243	* @param offRange The offset of the access into this range.
244	* (If it's a EIP range this's the EIP, if not it's pvFault.)
245	*/
246	VMMRCDECL(int) selmRCGuestLDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
247	{
248	/** @todo To be implemented. */
249	////LogCom(("selmRCGuestLDTWriteHandler: eip=%08X pvFault=%RGv pvRange=%RGv\r\n", pRegFrame->eip, pvFault, pvRange));
250
251	VMCPU_FF_SET(VMMGetCpu0(pVM), VMCPU_FF_SELM_SYNC_LDT);
252	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestLDT);
253	return VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT;
254	}
255
256
257	/**
258	* Read wrapper used by selmRCGuestTSSWriteHandler.
259	* @returns VBox status code (appropriate for trap handling and GC return).
260	* @param pVM The VM handle
261	* @param pvDst Where to put the bits we read.
262	* @param pvSrc Guest address to read from.
263	* @param cb The number of bytes to read.
264	*/
265	DECLINLINE(int) selmRCReadTssBits(PVM pVM, void pvDst, void const pvSrc, size_t cb)
266	{
267	PVMCPU pVCpu = VMMGetCpu0(pVM);
268
269	int rc = MMGCRamRead(pVM, pvDst, (void *)pvSrc, cb);
270	if (RT_SUCCESS(rc))
271	return VINF_SUCCESS;
272
273	/** @todo use different fallback? */
274	rc = PGMPrefetchPage(pVCpu, (uintptr_t)pvSrc);
275	AssertMsg(rc == VINF_SUCCESS, ("PGMPrefetchPage %p failed with %Rrc\n", &pvSrc, rc));
276	if (rc == VINF_SUCCESS)
277	{
278	rc = MMGCRamRead(pVM, pvDst, (void *)pvSrc, cb);
279	AssertMsg(rc == VINF_SUCCESS, ("MMGCRamRead %p failed with %Rrc\n", &pvSrc, rc));
280	}
281	return rc;
282	}
283
284	/**
285	* \#PF Virtual Handler callback for Guest write access to the Guest's own current TSS.
286	*
287	* @returns VBox status code (appropriate for trap handling and GC return).
288	* @param pVM VM Handle.
289	* @param uErrorCode CPU Error code.
290	* @param pRegFrame Trap register frame.
291	* @param pvFault The fault address (cr2).
292	* @param pvRange The base address of the handled virtual range.
293	* @param offRange The offset of the access into this range.
294	* (If it's a EIP range this's the EIP, if not it's pvFault.)
295	*/
296	VMMRCDECL(int) selmRCGuestTSSWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
297	{
298	PVMCPU pVCpu = VMMGetCpu0(pVM);
299
300	LogFlow(("selmRCGuestTSSWriteHandler errcode=%x fault=%RGv offRange=%08x\n", (uint32_t)uErrorCode, pvFault, offRange));
301
302	/*
303	* Try emulate the access.
304	*/
305	uint32_t cb;
306	int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, (RTGCPTR)(RTRCUINTPTR)pvFault, &cb);
307	if (RT_SUCCESS(rc) && cb)
308	{
309	rc = VINF_SUCCESS;
310
311	/*
312	* If it's on the same page as the esp0 and ss0 fields or actually one of them,
313	* then check if any of these has changed.
314	*/
315	PCVBOXTSS pGuestTss = (PVBOXTSS)(uintptr_t)pVM->selm.s.GCPtrGuestTss;
316	if ( PAGE_ADDRESS(&pGuestTss->esp0) == PAGE_ADDRESS(&pGuestTss->padding_ss0)
317	&& PAGE_ADDRESS(&pGuestTss->esp0) == PAGE_ADDRESS((uint8_t *)pGuestTss + offRange)
318	&& ( pGuestTss->esp0 != pVM->selm.s.Tss.esp1
319	\|\| pGuestTss->ss0 != (pVM->selm.s.Tss.ss1 & ~1)) /* undo raw-r0 */
320	)
321	{
322	Log(("selmRCGuestTSSWriteHandler: R0 stack: %RTsel:%RGv -> %RTsel:%RGv\n",
323	(RTSEL)(pVM->selm.s.Tss.ss1 & ~1), (RTGCPTR)pVM->selm.s.Tss.esp1, (RTSEL)pGuestTss->ss0, (RTGCPTR)pGuestTss->esp0));
324	pVM->selm.s.Tss.esp1 = pGuestTss->esp0;
325	pVM->selm.s.Tss.ss1 = pGuestTss->ss0 \| 1;
326	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSHandledChanged);
327	}
328	/* Handle misaligned TSS in a safe manner (just in case). */
329	else if ( offRange >= RT_UOFFSETOF(VBOXTSS, esp0)
330	&& offRange < RT_UOFFSETOF(VBOXTSS, padding_ss0))
331	{
332	struct
333	{
334	uint32_t esp0;
335	uint16_t ss0;
336	uint16_t padding_ss0;
337	} s;
338	AssertCompileSize(s, 8);
339	rc = selmRCReadTssBits(pVM, &s, &pGuestTss->esp0, sizeof(s));
340	if ( rc == VINF_SUCCESS
341	&& ( s.esp0 != pVM->selm.s.Tss.esp1
342	\|\| s.ss0 != (pVM->selm.s.Tss.ss1 & ~1)) /* undo raw-r0 */
343	)
344	{
345	Log(("selmRCGuestTSSWriteHandler: R0 stack: %RTsel:%RGv -> %RTsel:%RGv [x-page]\n",
346	(RTSEL)(pVM->selm.s.Tss.ss1 & ~1), (RTGCPTR)pVM->selm.s.Tss.esp1, (RTSEL)s.ss0, (RTGCPTR)s.esp0));
347	pVM->selm.s.Tss.esp1 = s.esp0;
348	pVM->selm.s.Tss.ss1 = s.ss0 \| 1;
349	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSHandledChanged);
350	}
351	}
352
353	/*
354	* If VME is enabled we need to check if the interrupt redirection bitmap
355	* needs updating.
356	*/
357	if ( offRange >= RT_UOFFSETOF(VBOXTSS, offIoBitmap)
358	&& (CPUMGetGuestCR4(pVCpu) & X86_CR4_VME))
359	{
360	if (offRange - RT_UOFFSETOF(VBOXTSS, offIoBitmap) < sizeof(pGuestTss->offIoBitmap))
361	{
362	uint16_t offIoBitmap = pGuestTss->offIoBitmap;
363	if (offIoBitmap != pVM->selm.s.offGuestIoBitmap)
364	{
365	Log(("TSS offIoBitmap changed: old=%#x new=%#x -> resync in ring-3\n", pVM->selm.s.offGuestIoBitmap, offIoBitmap));
366	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
367	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
368	}
369	else
370	Log(("TSS offIoBitmap: old=%#x new=%#x [unchanged]\n", pVM->selm.s.offGuestIoBitmap, offIoBitmap));
371	}
372	else
373	{
374	/** @todo not sure how the partial case is handled; probably not allowed */
375	uint32_t offIntRedirBitmap = pVM->selm.s.offGuestIoBitmap - sizeof(pVM->selm.s.Tss.IntRedirBitmap);
376	if ( offIntRedirBitmap <= offRange
377	&& offIntRedirBitmap + sizeof(pVM->selm.s.Tss.IntRedirBitmap) >= offRange + cb
378	&& offIntRedirBitmap + sizeof(pVM->selm.s.Tss.IntRedirBitmap) <= pVM->selm.s.cbGuestTss)
379	{
380	Log(("TSS IntRedirBitmap Changed: offIoBitmap=%x offIntRedirBitmap=%x cbTSS=%x offRange=%x cb=%x\n",
381	pVM->selm.s.offGuestIoBitmap, offIntRedirBitmap, pVM->selm.s.cbGuestTss, offRange, cb));
382
383	/** @todo only update the changed part. */
384	for (uint32_t i = 0; i < sizeof(pVM->selm.s.Tss.IntRedirBitmap) / 8; i++)
385	{
386	rc = selmRCReadTssBits(pVM, &pVM->selm.s.Tss.IntRedirBitmap[i * 8],
387	(uint8_t )pGuestTss + offIntRedirBitmap + i 8, 8);
388	if (rc != VINF_SUCCESS)
389	break;
390	}
391	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSRedir);
392	}
393	}
394	}
395
396	/* Return to ring-3 for a full resync if any of the above fails... (?) */
397	if (rc != VINF_SUCCESS)
398	{
399	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
400	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
401	if (RT_SUCCESS(rc))
402	rc = VINF_SUCCESS;
403	}
404
405	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSHandled);
406	}
407	else
408	{
409	Assert(RT_FAILURE(rc));
410	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
411	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestTSSUnhandled);
412	if (rc == VERR_EM_INTERPRETER)
413	rc = VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT;
414	}
415	return rc;
416	}
417
418
419	/**
420	* \#PF Virtual Handler callback for Guest write access to the VBox shadow GDT.
421	*
422	* @returns VBox status code (appropriate for trap handling and GC return).
423	* @param pVM VM Handle.
424	* @param uErrorCode CPU Error code.
425	* @param pRegFrame Trap register frame.
426	* @param pvFault The fault address (cr2).
427	* @param pvRange The base address of the handled virtual range.
428	* @param offRange The offset of the access into this range.
429	* (If it's a EIP range this's the EIP, if not it's pvFault.)
430	*/
431	VMMRCDECL(int) selmRCShadowGDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
432	{
433	LogRel(("FATAL ERROR: selmRCShadowGDTWriteHandler: eip=%08X pvFault=%RGv pvRange=%RGv\r\n", pRegFrame->eip, pvFault, pvRange));
434	return VERR_SELM_SHADOW_GDT_WRITE;
435	}
436
437
438	/**
439	* \#PF Virtual Handler callback for Guest write access to the VBox shadow LDT.
440	*
441	* @returns VBox status code (appropriate for trap handling and GC return).
442	* @param pVM VM Handle.
443	* @param uErrorCode CPU Error code.
444	* @param pRegFrame Trap register frame.
445	* @param pvFault The fault address (cr2).
446	* @param pvRange The base address of the handled virtual range.
447	* @param offRange The offset of the access into this range.
448	* (If it's a EIP range this's the EIP, if not it's pvFault.)
449	*/
450	VMMRCDECL(int) selmRCShadowLDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
451	{
452	LogRel(("FATAL ERROR: selmRCShadowLDTWriteHandler: eip=%08X pvFault=%RGv pvRange=%RGv\r\n", pRegFrame->eip, pvFault, pvRange));
453	Assert(pvFault - (uintptr_t)pVM->selm.s.pvLdtRC < (unsigned)(65536U + PAGE_SIZE));
454	return VERR_SELM_SHADOW_LDT_WRITE;
455	}
456
457
458	/**
459	* \#PF Virtual Handler callback for Guest write access to the VBox shadow TSS.
460	*
461	* @returns VBox status code (appropriate for trap handling and GC return).
462	* @param pVM VM Handle.
463	* @param uErrorCode CPU Error code.
464	* @param pRegFrame Trap register frame.
465	* @param pvFault The fault address (cr2).
466	* @param pvRange The base address of the handled virtual range.
467	* @param offRange The offset of the access into this range.
468	* (If it's a EIP range this's the EIP, if not it's pvFault.)
469	*/
470	VMMRCDECL(int) selmRCShadowTSSWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
471	{
472	LogRel(("FATAL ERROR: selmRCShadowTSSWriteHandler: eip=%08X pvFault=%RGv pvRange=%RGv\r\n", pRegFrame->eip, pvFault, pvRange));
473	return VERR_SELM_SHADOW_TSS_WRITE;
474	}
475

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source: vbox/trunk/src/VBox/VMM/VMMGC/SELMGC.cpp@ 29676

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