TRPMGCHandlers.cpp@ 31604

Last change on this file since 31604 was 31402, checked in by vboxsync, 14 years ago
PGM: Replaced the hazzardous raw-mode context dynamic mapping code with the PGMR0DynMap code used by darwin/x86. This is a risky change but it should pay off once stable by providing 100% certainty that dynamically mapped pages aren't resued behind our back (this has been observed in seemingly benign code paths recently).
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File size: 50.4 KB

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1	/* $Id: TRPMGCHandlers.cpp 31402 2010-08-05 12:28:18Z vboxsync $ */
2	/** @file
3	* TRPM - Guest Context Trap Handlers, CPP part
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_TRPM
23	#include <VBox/selm.h>
24	#include <VBox/iom.h>
25	#include <VBox/pgm.h>
26	#include <VBox/pdmapi.h>
27	#include <VBox/dbgf.h>
28	#include <VBox/em.h>
29	#include <VBox/csam.h>
30	#include <VBox/patm.h>
31	#include <VBox/mm.h>
32	#include <VBox/cpum.h>
33	#include "TRPMInternal.h"
34	#include <VBox/vm.h>
35	#include <VBox/vmm.h>
36	#include <VBox/param.h>
37
38	#include <VBox/err.h>
39	#include <VBox/dis.h>
40	#include <VBox/disopcode.h>
41	#include <VBox/x86.h>
42	#include <VBox/log.h>
43	#include <VBox/tm.h>
44	#include <iprt/asm.h>
45	#include <iprt/asm-amd64-x86.h>
46	#include <iprt/assert.h>
47
48
49	/*******************************************************************************
50	* Defined Constants And Macros *
51	*******************************************************************************/
52	/* still here. MODR/M byte parsing */
53	#define X86_OPCODE_MODRM_MOD_MASK 0xc0
54	#define X86_OPCODE_MODRM_REG_MASK 0x38
55	#define X86_OPCODE_MODRM_RM_MASK 0x07
56
57	/** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
58	#define DTRACE_EXPERIMENT
59
60
61	/*******************************************************************************
62	* Structures and Typedefs *
63	*******************************************************************************/
64	/** Pointer to a readonly hypervisor trap record. */
65	typedef const struct TRPMGCHYPER *PCTRPMGCHYPER;
66
67	/**
68	* A hypervisor trap record.
69	* This contains information about a handler for a instruction range.
70	*
71	* @remark This must match what TRPM_HANDLER outputs.
72	*/
73	typedef struct TRPMGCHYPER
74	{
75	/** The start address. */
76	uintptr_t uStartEIP;
77	/** The end address. (exclusive)
78	* If NULL the it's only for the instruction at pvStartEIP. */
79	uintptr_t uEndEIP;
80	/**
81	* The handler.
82	*
83	* @returns VBox status code
84	* VINF_SUCCESS means we've handled the trap.
85	* Any other error code means returning to the host context.
86	* @param pVM The VM handle.
87	* @param pRegFrame The register frame.
88	* @param uUser The user argument.
89	*/
90	DECLRCCALLBACKMEMBER(int, pfnHandler, (PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser));
91	/** Whatever the handler desires to put here. */
92	uintptr_t uUser;
93	} TRPMGCHYPER;
94
95
96	/*******************************************************************************
97	* Global Variables *
98	*******************************************************************************/
99	RT_C_DECLS_BEGIN
100	/** Defined in VMMGC0.asm or VMMGC99.asm.
101	* @{ */
102	extern const TRPMGCHYPER g_aTrap0bHandlers[1];
103	extern const TRPMGCHYPER g_aTrap0bHandlersEnd[1];
104	extern const TRPMGCHYPER g_aTrap0dHandlers[1];
105	extern const TRPMGCHYPER g_aTrap0dHandlersEnd[1];
106	extern const TRPMGCHYPER g_aTrap0eHandlers[1];
107	extern const TRPMGCHYPER g_aTrap0eHandlersEnd[1];
108	/** @} */
109	RT_C_DECLS_END
110
111
112	/*******************************************************************************
113	* Internal Functions *
114	*******************************************************************************/
115	RT_C_DECLS_BEGIN /* addressed from asm (not called so no DECLASM). */
116	DECLCALLBACK(int) trpmGCTrapInGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser);
117	RT_C_DECLS_END
118
119
120
121	/**
122	* Exits the trap, called when exiting a trap handler.
123	*
124	* Will reset the trap if it's not a guest trap or the trap
125	* is already handled. Will process resume guest FFs.
126	*
127	* @returns rc, can be adjusted if its VINF_SUCCESS or something really bad
128	* happened.
129	* @param pVM VM handle.
130	* @param pVCpu The virtual CPU handle.
131	* @param rc The VBox status code to return.
132	* @param pRegFrame Pointer to the register frame for the trap.
133	*
134	* @remarks This must not be used for hypervisor traps, only guest traps.
135	*/
136	static int trpmGCExitTrap(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTXCORE pRegFrame)
137	{
138	uint32_t uOldActiveVector = pVCpu->trpm.s.uActiveVector;
139	NOREF(uOldActiveVector);
140
141	/* Reset trap? */
142	if ( rc != VINF_EM_RAW_GUEST_TRAP
143	&& rc != VINF_EM_RAW_RING_SWITCH_INT)
144	pVCpu->trpm.s.uActiveVector = ~0;
145
146	#ifdef VBOX_HIGH_RES_TIMERS_HACK
147	/*
148	* We should poll the timers occationally.
149	* We must NOT do this too frequently as it adds a significant overhead
150	* and it'll kill us if the trap load is high. (See #1354.)
151	* (The heuristic is not very intelligent, we should really check trap
152	* frequency etc. here, but alas, we lack any such information atm.)
153	*/
154	static unsigned s_iTimerPoll = 0;
155	if (rc == VINF_SUCCESS)
156	{
157	if (!(++s_iTimerPoll & 0xf))
158	{
159	TMTimerPollVoid(pVM, pVCpu);
160	Log2(("TMTimerPoll at %08RX32 - VM_FF_TM_VIRTUAL_SYNC=%d VM_FF_TM_VIRTUAL_SYNC=%d\n", pRegFrame->eip,
161	VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC), VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)));
162	}
163	}
164	else
165	s_iTimerPoll = 0;
166	#endif
167
168	/* Clear pending inhibit interrupt state if required. (necessary for dispatching interrupts later on) */
169	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
170	{
171	Log2(("VM_FF_INHIBIT_INTERRUPTS at %08RX32 successor %RGv\n", pRegFrame->eip, EMGetInhibitInterruptsPC(pVCpu)));
172	if (pRegFrame->eip != EMGetInhibitInterruptsPC(pVCpu))
173	{
174	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
175	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
176	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
177	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
178	*/
179	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
180	}
181	}
182
183	/*
184	* Pending resume-guest-FF?
185	* Or pending (A)PIC interrupt? Windows XP will crash if we delay APIC interrupts.
186	*/
187	if ( rc == VINF_SUCCESS
188	&& ( VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC \| VM_FF_REQUEST \| VM_FF_PGM_NO_MEMORY)
189	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER \| VMCPU_FF_TO_R3 \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_REQUEST \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
190	)
191	)
192	{
193	/* The out of memory condition naturally outrang the others. */
194	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
195	rc = VINF_EM_NO_MEMORY;
196	/* Pending Ring-3 action. */
197	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TO_R3))
198	{
199	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
200	rc = VINF_EM_RAW_TO_R3;
201	}
202	/* Pending timer action. */
203	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER))
204	rc = VINF_EM_RAW_TIMER_PENDING;
205	/* The Virtual Sync clock has stopped. */
206	else if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
207	rc = VINF_EM_RAW_TO_R3;
208	/* Pending interrupt: dispatch it. */
209	else if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
210	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
211	&& PATMAreInterruptsEnabledByCtxCore(pVM, pRegFrame)
212	)
213	{
214	uint8_t u8Interrupt;
215	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
216	Log(("trpmGCExitTrap: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
217	AssertFatalMsgRC(rc, ("PDMGetInterrupt failed with %Rrc\n", rc));
218	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_HARDWARE_INT, uOldActiveVector);
219	/* can't return if successful */
220	Assert(rc != VINF_SUCCESS);
221
222	/* Stop the profile counter that was started in TRPMGCHandlersA.asm */
223	Assert(uOldActiveVector <= 16);
224	STAM_PROFILE_ADV_STOP(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
225
226	/* Assert the trap and go to the recompiler to dispatch it. */
227	TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
228
229	STAM_PROFILE_ADV_START(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
230	rc = VINF_EM_RAW_INTERRUPT_PENDING;
231	}
232	/*
233	* Try sync CR3?
234	*/
235	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
236	{
237	#if 1
238	PGMRZDynMapReleaseAutoSet(pVCpu);
239	PGMRZDynMapStartAutoSet(pVCpu);
240	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
241	#else
242	rc = VINF_PGM_SYNC_CR3;
243	#endif
244	}
245	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
246	else if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
247	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
248	rc = VINF_EM_PENDING_REQUEST;
249	}
250
251	AssertMsg( rc != VINF_SUCCESS
252	\|\| ( pRegFrame->eflags.Bits.u1IF
253	&& ( pRegFrame->eflags.Bits.u2IOPL < (unsigned)(pRegFrame->ss & X86_SEL_RPL) \|\| pRegFrame->eflags.Bits.u1VM))
254	, ("rc=%Rrc\neflags=%RX32 ss=%RTsel IOPL=%d\n", rc, pRegFrame->eflags.u32, pRegFrame->ss, pRegFrame->eflags.Bits.u2IOPL));
255	PGMRZDynMapReleaseAutoSet(pVCpu);
256	return rc;
257	}
258
259
260	/**
261	* \#DB (Debug event) handler.
262	*
263	* @returns VBox status code.
264	* VINF_SUCCESS means we completely handled this trap,
265	* other codes are passed execution to host context.
266	*
267	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
268	* @param pRegFrame Pointer to the register frame for the trap.
269	* @internal
270	*/
271	DECLASM(int) TRPMGCTrap01Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
272	{
273	RTGCUINTREG uDr6 = ASMGetAndClearDR6();
274	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
275	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
276
277	LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs, pRegFrame->eip, uDr6));
278
279	/*
280	* We currently don't make use of the X86_DR7_GD bit, but
281	* there might come a time when we do.
282	*/
283	AssertReleaseMsgReturn((uDr6 & X86_DR6_BD) != X86_DR6_BD,
284	("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
285	ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
286	VERR_NOT_IMPLEMENTED);
287	AssertReleaseMsg(!(uDr6 & X86_DR6_BT), ("X86_DR6_BT is impossible!\n"));
288
289	/*
290	* Now leave the rest to the DBGF.
291	*/
292	PGMRZDynMapStartAutoSet(pVCpu);
293	int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6);
294	if (rc == VINF_EM_RAW_GUEST_TRAP)
295	CPUMSetGuestDR6(pVCpu, uDr6);
296
297	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
298	Log6(("TRPMGC01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs, pRegFrame->eip, uDr6));
299	return rc;
300	}
301
302
303	/**
304	* \#DB (Debug event) handler for the hypervisor code.
305	*
306	* This is mostly the same as TRPMGCTrap01Handler, but we skip the PGM auto
307	* mapping set as well as the default trap exit path since they are both really
308	* bad ideas in this context.
309	*
310	* @returns VBox status code.
311	* VINF_SUCCESS means we completely handled this trap,
312	* other codes are passed execution to host context.
313	*
314	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
315	* @param pRegFrame Pointer to the register frame for the trap.
316	* @internal
317	*/
318	DECLASM(int) TRPMGCHyperTrap01Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
319	{
320	RTGCUINTREG uDr6 = ASMGetAndClearDR6();
321	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
322	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
323
324	LogFlow(("TRPMGCHyper01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs, pRegFrame->eip, uDr6));
325
326	/*
327	* We currently don't make use of the X86_DR7_GD bit, but
328	* there might come a time when we do.
329	*/
330	AssertReleaseMsgReturn((uDr6 & X86_DR6_BD) != X86_DR6_BD,
331	("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
332	ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
333	VERR_NOT_IMPLEMENTED);
334	AssertReleaseMsg(!(uDr6 & X86_DR6_BT), ("X86_DR6_BT is impossible!\n"));
335
336	/*
337	* Now leave the rest to the DBGF.
338	*/
339	int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6);
340	AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_INTERNAL_ERROR_3);
341
342	Log6(("TRPMGCHyper01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs, pRegFrame->eip, uDr6));
343	return rc;
344	}
345
346
347	/**
348	* NMI handler, for when we are using NMIs to debug things.
349	*
350	* @returns VBox status code.
351	* VINF_SUCCESS means we completely handled this trap,
352	* other codes are passed execution to host context.
353	*
354	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
355	* @param pRegFrame Pointer to the register frame for the trap.
356	* @internal
357	* @remark This is not hooked up unless you're building with VBOX_WITH_NMI defined.
358	*/
359	DECLASM(int) TRPMGCTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
360	{
361	LogFlow(("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
362	RTLogComPrintf("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip);
363	return VERR_TRPM_DONT_PANIC;
364	}
365
366
367	/**
368	* NMI handler, for when we are using NMIs to debug things.
369	*
370	* This is the handler we're most likely to hit when the NMI fires (it is
371	* unlikely that we'll be stuck in guest code).
372	*
373	* @returns VBox status code.
374	* VINF_SUCCESS means we completely handled this trap,
375	* other codes are passed execution to host context.
376	*
377	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
378	* @param pRegFrame Pointer to the register frame for the trap.
379	* @internal
380	* @remark This is not hooked up unless you're building with VBOX_WITH_NMI defined.
381	*/
382	DECLASM(int) TRPMGCHyperTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
383	{
384	LogFlow(("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
385	RTLogComPrintf("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip);
386	return VERR_TRPM_DONT_PANIC;
387	}
388
389
390	/**
391	* \#BP (Breakpoint) handler.
392	*
393	* @returns VBox status code.
394	* VINF_SUCCESS means we completely handled this trap,
395	* other codes are passed execution to host context.
396	*
397	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
398	* @param pRegFrame Pointer to the register frame for the trap.
399	* @internal
400	*/
401	DECLASM(int) TRPMGCTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
402	{
403	LogFlow(("TRPMGC03: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
404	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
405	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
406	int rc;
407	PGMRZDynMapStartAutoSet(pVCpu);
408
409	/*
410	* PATM is using INT3s, let them have a go first.
411	*/
412	if ( (pRegFrame->ss & X86_SEL_RPL) == 1
413	&& !pRegFrame->eflags.Bits.u1VM)
414	{
415	rc = PATMHandleInt3PatchTrap(pVM, pRegFrame);
416	if (rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_PATM_PATCH_INT3 \|\| rc == VINF_PATM_DUPLICATE_FUNCTION)
417	{
418	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
419	Log6(("TRPMGC03: %Rrc (%04x:%08x) (PATM)\n", rc, pRegFrame->cs, pRegFrame->eip));
420	return rc;
421	}
422	}
423	rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
424
425	/* anything we should do with this? Schedule it in GC? */
426	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
427	Log6(("TRPMGC03: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
428	return rc;
429	}
430
431
432	/**
433	* \#BP (Breakpoint) handler.
434	*
435	* This is similar to TRPMGCTrap03Handler but we bits which are potentially
436	* harmful to us (common trap exit and the auto mapping set).
437	*
438	* @returns VBox status code.
439	* VINF_SUCCESS means we completely handled this trap,
440	* other codes are passed execution to host context.
441	*
442	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
443	* @param pRegFrame Pointer to the register frame for the trap.
444	* @internal
445	*/
446	DECLASM(int) TRPMGCHyperTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
447	{
448	LogFlow(("TRPMGCHyper03: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
449	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
450	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
451
452	/*
453	* Hand it over to DBGF.
454	*/
455	int rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
456	AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_INTERNAL_ERROR_3);
457
458	Log6(("TRPMGCHyper03: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
459	return rc;
460	}
461
462
463	/**
464	* Trap handler for illegal opcode fault (\#UD).
465	*
466	* @returns VBox status code.
467	* VINF_SUCCESS means we completely handled this trap,
468	* other codes are passed execution to host context.
469	*
470	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
471	* @param pRegFrame Pointer to the register frame for the trap.
472	* @internal
473	*/
474	DECLASM(int) TRPMGCTrap06Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
475	{
476	LogFlow(("TRPMGC06: %04x:%08x efl=%x\n", pRegFrame->cs, pRegFrame->eip, pRegFrame->eflags.u32));
477	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
478	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
479	int rc;
480	PGMRZDynMapStartAutoSet(pVCpu);
481
482	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
483	{
484	/*
485	* Decode the instruction.
486	*/
487	RTGCPTR PC;
488	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid,
489	(RTGCPTR)pRegFrame->eip, &PC);
490	if (RT_FAILURE(rc))
491	{
492	Log(("TRPMGCTrap06Handler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n", pRegFrame->cs, pRegFrame->eip, pRegFrame->ss & X86_SEL_RPL, rc));
493	rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
494	Log6(("TRPMGC06: %Rrc (%04x:%08x) (SELM)\n", rc, pRegFrame->cs, pRegFrame->eip));
495	return rc;
496	}
497
498	DISCPUSTATE Cpu;
499	uint32_t cbOp;
500	rc = EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
501	if (RT_FAILURE(rc))
502	{
503	rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
504	Log6(("TRPMGC06: %Rrc (%04x:%08x) (EM)\n", rc, pRegFrame->cs, pRegFrame->eip));
505	return rc;
506	}
507
508	/*
509	* UD2 in a patch?
510	* Note! PATMGCHandleIllegalInstrTrap doesn't always return.
511	*/
512	if ( Cpu.pCurInstr->opcode == OP_ILLUD2
513	&& PATMIsPatchGCAddr(pVM, pRegFrame->eip))
514	{
515	LogFlow(("TRPMGCTrap06Handler: -> PATMGCHandleIllegalInstrTrap\n"));
516	rc = PATMGCHandleIllegalInstrTrap(pVM, pRegFrame);
517	/** @todo These tests are completely unnecessary, should just follow the
518	* flow and return at the end of the function. */
519	if ( rc == VINF_SUCCESS
520	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
521	\|\| rc == VINF_PATM_DUPLICATE_FUNCTION
522	\|\| rc == VINF_PATM_PENDING_IRQ_AFTER_IRET
523	\|\| rc == VINF_EM_RESCHEDULE)
524	{
525	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
526	Log6(("TRPMGC06: %Rrc (%04x:%08x) (PATM)\n", rc, pRegFrame->cs, pRegFrame->eip));
527	return rc;
528	}
529	}
530	/*
531	* Speed up dtrace and don't entrust invalid lock sequences to the recompiler.
532	*/
533	else if (Cpu.prefix & PREFIX_LOCK)
534	{
535	Log(("TRPMGCTrap06Handler: pc=%08x op=%d\n", pRegFrame->eip, Cpu.pCurInstr->opcode));
536	#ifdef DTRACE_EXPERIMENT /** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
537	Assert(!PATMIsPatchGCAddr(pVM, pRegFrame->eip));
538	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0x6, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, 0x6);
539	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
540	#else
541	rc = VINF_EM_RAW_EMULATE_INSTR;
542	#endif
543	}
544	/*
545	* Handle MONITOR - it causes an #UD exception instead of #GP when not executed in ring 0.
546	*/
547	else if (Cpu.pCurInstr->opcode == OP_MONITOR)
548	{
549	LogFlow(("TRPMGCTrap06Handler: -> EMInterpretInstructionCPU\n"));
550	uint32_t cbIgnored;
551	rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, pRegFrame, PC, &cbIgnored);
552	if (RT_SUCCESS(rc))
553	pRegFrame->eip += Cpu.opsize;
554	}
555	/* Never generate a raw trap here; it might be an instruction, that requires emulation. */
556	else
557	{
558	LogFlow(("TRPMGCTrap06Handler: -> VINF_EM_RAW_EMULATE_INSTR\n"));
559	rc = VINF_EM_RAW_EMULATE_INSTR;
560	}
561	}
562	else
563	{
564	LogFlow(("TRPMGCTrap06Handler: -> TRPMForwardTrap\n"));
565	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0x6, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, 0x6);
566	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
567	}
568
569	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
570	Log6(("TRPMGC06: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
571	return rc;
572	}
573
574
575	/**
576	* Trap handler for device not present fault (\#NM).
577	*
578	* Device not available, FP or (F)WAIT instruction.
579	*
580	* @returns VBox status code.
581	* VINF_SUCCESS means we completely handled this trap,
582	* other codes are passed execution to host context.
583	*
584	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
585	* @param pRegFrame Pointer to the register frame for the trap.
586	* @internal
587	*/
588	DECLASM(int) TRPMGCTrap07Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
589	{
590	LogFlow(("TRPMGC07: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
591	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
592	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
593	PGMRZDynMapStartAutoSet(pVCpu);
594
595	int rc = CPUMHandleLazyFPU(pVCpu);
596	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
597	Log6(("TRPMGC07: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
598	return rc;
599	}
600
601
602	/**
603	* \#NP ((segment) Not Present) handler.
604	*
605	* @returns VBox status code.
606	* VINF_SUCCESS means we completely handled this trap,
607	* other codes are passed execution to host context.
608	*
609	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
610	* @param pRegFrame Pointer to the register frame for the trap.
611	* @internal
612	*/
613	DECLASM(int) TRPMGCTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
614	{
615	LogFlow(("TRPMGC0b: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
616	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
617	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
618	PGMRZDynMapStartAutoSet(pVCpu);
619
620	/*
621	* Try to detect instruction by opcode which caused trap.
622	* XXX note: this code may cause \#PF (trap e) or \#GP (trap d) while
623	* accessing user code. need to handle it somehow in future!
624	*/
625	RTGCPTR GCPtr;
626	if ( SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid,
627	(RTGCPTR)pRegFrame->eip, &GCPtr)
628	== VINF_SUCCESS)
629	{
630	uint8_t pu8Code = (uint8_t )(uintptr_t)GCPtr;
631
632	/*
633	* First skip possible instruction prefixes, such as:
634	* OS, AS
635	* CS:, DS:, ES:, SS:, FS:, GS:
636	* REPE, REPNE
637	*
638	* note: Currently we supports only up to 4 prefixes per opcode, more
639	* prefixes (normally not used anyway) will cause trap d in guest.
640	* note: Instruction length in IA-32 may be up to 15 bytes, we dont
641	* check this issue, its too hard.
642	*/
643	for (unsigned i = 0; i < 4; i++)
644	{
645	if ( pu8Code[0] != 0xf2 /* REPNE/REPNZ */
646	&& pu8Code[0] != 0xf3 /* REP/REPE/REPZ */
647	&& pu8Code[0] != 0x2e /* CS: */
648	&& pu8Code[0] != 0x36 /* SS: */
649	&& pu8Code[0] != 0x3e /* DS: */
650	&& pu8Code[0] != 0x26 /* ES: */
651	&& pu8Code[0] != 0x64 /* FS: */
652	&& pu8Code[0] != 0x65 /* GS: */
653	&& pu8Code[0] != 0x66 /* OS */
654	&& pu8Code[0] != 0x67 /* AS */
655	)
656	break;
657	pu8Code++;
658	}
659
660	/*
661	* Detect right switch using a callgate.
662	*
663	* We recognize the following causes for the trap 0b:
664	* CALL FAR, CALL FAR []
665	* JMP FAR, JMP FAR []
666	* IRET (may cause a task switch)
667	*
668	* Note: we can't detect whether the trap was caused by a call to a
669	* callgate descriptor or it is a real trap 0b due to a bad selector.
670	* In both situations we'll pass execution to our recompiler so we don't
671	* have to worry.
672	* If we wanted to do better detection, we have set GDT entries to callgate
673	* descriptors pointing to our own handlers.
674	*/
675	/** @todo not sure about IRET, may generate Trap 0d (\#GP), NEED TO CHECK! */
676	if ( pu8Code[0] == 0x9a /* CALL FAR */
677	\|\| ( pu8Code[0] == 0xff /* CALL FAR [] */
678	&& (pu8Code[1] & X86_OPCODE_MODRM_REG_MASK) == 0x18)
679	\|\| pu8Code[0] == 0xea /* JMP FAR */
680	\|\| ( pu8Code[0] == 0xff /* JMP FAR [] */
681	&& (pu8Code[1] & X86_OPCODE_MODRM_REG_MASK) == 0x28)
682	\|\| pu8Code[0] == 0xcf /* IRET */
683	)
684	{
685	/*
686	* Got potential call to callgate.
687	* We simply return execution to the recompiler to do emulation
688	* starting from the instruction which caused the trap.
689	*/
690	pTrpmCpu->uActiveVector = ~0;
691	Log6(("TRPMGC0b: %Rrc (%04x:%08x) (CG)\n", VINF_EM_RAW_RING_SWITCH, pRegFrame->cs, pRegFrame->eip));
692	PGMRZDynMapReleaseAutoSet(pVCpu);
693	return VINF_EM_RAW_RING_SWITCH;
694	}
695	}
696
697	/*
698	* Pass trap 0b as is to the recompiler in all other cases.
699	*/
700	Log6(("TRPMGC0b: %Rrc (%04x:%08x)\n", VINF_EM_RAW_GUEST_TRAP, pRegFrame->cs, pRegFrame->eip));
701	PGMRZDynMapReleaseAutoSet(pVCpu);
702	return VINF_EM_RAW_GUEST_TRAP;
703	}
704
705
706	/**
707	* \#GP (General Protection Fault) handler for Ring-0 privileged instructions.
708	*
709	* @returns VBox status code.
710	* VINF_SUCCESS means we completely handled this trap,
711	* other codes are passed execution to host context.
712	*
713	* @param pVM The VM handle.
714	* @param pVCpu The virtual CPU handle.
715	* @param pRegFrame Pointer to the register frame for the trap.
716	* @param pCpu The opcode info.
717	* @param PC The program counter corresponding to cs:eip in pRegFrame.
718	*/
719	static int trpmGCTrap0dHandlerRing0(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
720	{
721	int rc;
722
723	/*
724	* Try handle it here, if not return to HC and emulate/interpret it there.
725	*/
726	switch (pCpu->pCurInstr->opcode)
727	{
728	case OP_INT3:
729	/*
730	* Little hack to make the code below not fail
731	*/
732	pCpu->param1.flags = USE_IMMEDIATE8;
733	pCpu->param1.parval = 3;
734	/* fallthru */
735	case OP_INT:
736	{
737	Assert(pCpu->param1.flags & USE_IMMEDIATE8);
738	Assert(!(PATMIsPatchGCAddr(pVM, PC)));
739	if (pCpu->param1.parval == 3)
740	{
741	/* Int 3 replacement patch? */
742	if (PATMHandleInt3PatchTrap(pVM, pRegFrame) == VINF_SUCCESS)
743	{
744	AssertFailed();
745	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
746	}
747	}
748	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->param1.parval, pCpu->opsize, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
749	if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
750	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
751
752	pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
753	pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
754	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
755	}
756
757	#ifdef PATM_EMULATE_SYSENTER
758	case OP_SYSEXIT:
759	case OP_SYSRET:
760	rc = PATMSysCall(pVM, pRegFrame, pCpu);
761	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
762	#endif
763
764	case OP_HLT:
765	/* If it's in patch code, defer to ring-3. */
766	if (PATMIsPatchGCAddr(pVM, PC))
767	break;
768
769	pRegFrame->eip += pCpu->opsize;
770	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_HALT, pRegFrame);
771
772
773	/*
774	* These instructions are used by PATM and CASM for finding
775	* dangerous non-trapping instructions. Thus, since all
776	* scanning and patching is done in ring-3 we'll have to
777	* return to ring-3 on the first encounter of these instructions.
778	*/
779	case OP_MOV_CR:
780	case OP_MOV_DR:
781	/* We can safely emulate control/debug register move instructions in patched code. */
782	if ( !PATMIsPatchGCAddr(pVM, PC)
783	&& !CSAMIsKnownDangerousInstr(pVM, PC))
784	break;
785	case OP_INVLPG:
786	case OP_LLDT:
787	case OP_STI:
788	case OP_RDTSC: /* just in case */
789	case OP_RDPMC:
790	case OP_CLTS:
791	case OP_WBINVD: /* nop */
792	case OP_RDMSR:
793	case OP_WRMSR:
794	{
795	uint32_t cbIgnored;
796	rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, &cbIgnored);
797	if (RT_SUCCESS(rc))
798	pRegFrame->eip += pCpu->opsize;
799	else if (rc == VERR_EM_INTERPRETER)
800	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
801	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
802	}
803	}
804
805	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EXCEPTION_PRIVILEGED, pRegFrame);
806	}
807
808
809	/**
810	* \#GP (General Protection Fault) handler for Ring-3.
811	*
812	* @returns VBox status code.
813	* VINF_SUCCESS means we completely handled this trap,
814	* other codes are passed execution to host context.
815	*
816	* @param pVM The VM handle.
817	* @param pVCpu The virtual CPU handle.
818	* @param pRegFrame Pointer to the register frame for the trap.
819	* @param pCpu The opcode info.
820	* @param PC The program counter corresponding to cs:eip in pRegFrame.
821	*/
822	static int trpmGCTrap0dHandlerRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
823	{
824	int rc;
825	Assert(!pRegFrame->eflags.Bits.u1VM);
826
827	switch (pCpu->pCurInstr->opcode)
828	{
829	/*
830	* INT3 and INT xx are ring-switching.
831	* (The shadow IDT will have set the entries to DPL=0, that's why we're here.)
832	*/
833	case OP_INT3:
834	/*
835	* Little hack to make the code below not fail
836	*/
837	pCpu->param1.flags = USE_IMMEDIATE8;
838	pCpu->param1.parval = 3;
839	/* fall thru */
840	case OP_INT:
841	{
842	Assert(pCpu->param1.flags & USE_IMMEDIATE8);
843	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->param1.parval, pCpu->opsize, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
844	if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
845	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
846
847	pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
848	pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
849	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
850	}
851
852	/*
853	* SYSCALL, SYSENTER, INTO and BOUND are also ring-switchers.
854	*/
855	case OP_SYSCALL:
856	case OP_SYSENTER:
857	#ifdef PATM_EMULATE_SYSENTER
858	rc = PATMSysCall(pVM, pRegFrame, pCpu);
859	if (rc == VINF_SUCCESS)
860	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
861	/* else no break; */
862	#endif
863	case OP_BOUND:
864	case OP_INTO:
865	pVCpu->trpm.s.uActiveVector = ~0;
866	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH, pRegFrame);
867
868	/*
869	* Handle virtualized TSC & PMC reads, just in case.
870	*/
871	case OP_RDTSC:
872	case OP_RDPMC:
873	{
874	uint32_t cbIgnored;
875	rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, &cbIgnored);
876	if (RT_SUCCESS(rc))
877	pRegFrame->eip += pCpu->opsize;
878	else if (rc == VERR_EM_INTERPRETER)
879	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
880	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
881	}
882
883	/*
884	* STI and CLI are I/O privileged, i.e. if IOPL
885	*/
886	case OP_STI:
887	case OP_CLI:
888	{
889	uint32_t efl = CPUMRawGetEFlags(pVCpu, pRegFrame);
890	if (X86_EFL_GET_IOPL(efl) >= (unsigned)(pRegFrame->ss & X86_SEL_RPL))
891	{
892	LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> REM\n"));
893	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RESCHEDULE_REM, pRegFrame);
894	}
895	LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> #GP(0)\n"));
896	break;
897	}
898	}
899
900	/*
901	* A genuine guest fault.
902	*/
903	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
904	}
905
906
907	/**
908	* Emulates RDTSC for the \#GP handler.
909	*
910	* @returns VINF_SUCCESS or VINF_EM_RAW_EMULATE_INSTR.
911	*
912	* @param pVM Pointer to the shared VM structure.
913	* @param pVCpu The virtual CPU handle.
914	* @param pRegFrame Pointer to the registre frame for the trap.
915	* This will be updated on successful return.
916	*/
917	DECLINLINE(int) trpmGCTrap0dHandlerRdTsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
918	{
919	STAM_COUNTER_INC(&pVM->trpm.s.StatTrap0dRdTsc);
920
921	if (CPUMGetGuestCR4(pVCpu) & X86_CR4_TSD)
922	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame); /* will trap (optimize later). */
923
924	uint64_t uTicks = TMCpuTickGet(pVCpu);
925	pRegFrame->eax = uTicks;
926	pRegFrame->edx = uTicks >> 32;
927	pRegFrame->eip += 2;
928	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
929	}
930
931
932	/**
933	* \#GP (General Protection Fault) handler.
934	*
935	* @returns VBox status code.
936	* VINF_SUCCESS means we completely handled this trap,
937	* other codes are passed execution to host context.
938	*
939	* @param pVM The VM handle.
940	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
941	* @param pRegFrame Pointer to the register frame for the trap.
942	*/
943	static int trpmGCTrap0dHandler(PVM pVM, PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
944	{
945	LogFlow(("trpmGCTrap0dHandler: cs:eip=%RTsel:%08RX32 uErr=%RGv\n", pRegFrame->ss, pRegFrame->eip, pTrpmCpu->uActiveErrorCode));
946	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
947
948	/*
949	* Convert and validate CS.
950	*/
951	STAM_PROFILE_START(&pVM->trpm.s.StatTrap0dDisasm, a);
952	RTGCPTR PC;
953	uint32_t cBits;
954	int rc = SELMValidateAndConvertCSAddrGCTrap(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
955	(RTGCPTR)pRegFrame->eip, &PC, &cBits);
956	if (RT_FAILURE(rc))
957	{
958	Log(("trpmGCTrap0dHandler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n",
959	pRegFrame->cs, pRegFrame->eip, pRegFrame->ss & X86_SEL_RPL, rc));
960	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
961	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
962	}
963
964	/*
965	* Disassemble the instruction.
966	*/
967	DISCPUSTATE Cpu;
968	uint32_t cbOp;
969	rc = EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
970	if (RT_FAILURE(rc))
971	{
972	AssertMsgFailed(("DISCoreOneEx failed to PC=%RGv rc=%Rrc\n", PC, rc));
973	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
974	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
975	}
976	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
977
978	/*
979	* Optimize RDTSC traps.
980	* Some guests (like Solaris) are using RDTSC all over the place and
981	* will end up trapping a lot because of that.
982	*
983	* Note: it's no longer safe to access the instruction opcode directly due to possible stale code TLB entries
984	*/
985	if (Cpu.pCurInstr->opcode == OP_RDTSC)
986	return trpmGCTrap0dHandlerRdTsc(pVM, pVCpu, pRegFrame);
987
988	/*
989	* Deal with I/O port access.
990	*/
991	if ( pVCpu->trpm.s.uActiveErrorCode == 0
992	&& (Cpu.pCurInstr->optype & OPTYPE_PORTIO))
993	{
994	VBOXSTRICTRC rcStrict = EMInterpretPortIO(pVM, pVCpu, pRegFrame, &Cpu, cbOp);
995	rc = VBOXSTRICTRC_TODO(rcStrict);
996	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
997	}
998
999	/*
1000	* Deal with Ring-0 (privileged instructions)
1001	*/
1002	if ( (pRegFrame->ss & X86_SEL_RPL) <= 1
1003	&& !pRegFrame->eflags.Bits.u1VM)
1004	return trpmGCTrap0dHandlerRing0(pVM, pVCpu, pRegFrame, &Cpu, PC);
1005
1006	/*
1007	* Deal with Ring-3 GPs.
1008	*/
1009	if (!pRegFrame->eflags.Bits.u1VM)
1010	return trpmGCTrap0dHandlerRing3(pVM, pVCpu, pRegFrame, &Cpu, PC);
1011
1012	/*
1013	* Deal with v86 code.
1014	*
1015	* We always set IOPL to zero which makes e.g. pushf fault in V86
1016	* mode. The guest might use IOPL=3 and therefore not expect a #GP.
1017	* Simply fall back to the recompiler to emulate this instruction if
1018	* that's the case. To get the correct we must use CPUMRawGetEFlags.
1019	*/
1020	X86EFLAGS eflags;
1021	eflags.u32 = CPUMRawGetEFlags(pVCpu, pRegFrame); /* Get the correct value. */
1022	Log3(("TRPM #GP V86: cs:eip=%04x:%08x IOPL=%d efl=%08x\n", pRegFrame->cs, pRegFrame->eip, eflags.Bits.u2IOPL, eflags.u));
1023	if (eflags.Bits.u2IOPL != 3)
1024	{
1025	Assert(eflags.Bits.u2IOPL == 0);
1026
1027	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xD, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xd);
1028	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
1029	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1030	}
1031	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1032	}
1033
1034
1035	/**
1036	* \#GP (General Protection Fault) handler.
1037	*
1038	* @returns VBox status code.
1039	* VINF_SUCCESS means we completely handled this trap,
1040	* other codes are passed execution to host context.
1041	*
1042	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1043	* @param pRegFrame Pointer to the register frame for the trap.
1044	* @internal
1045	*/
1046	DECLASM(int) TRPMGCTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1047	{
1048	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
1049	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1050
1051	LogFlow(("TRPMGC0d: %04x:%08x err=%x\n", pRegFrame->cs, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode));
1052
1053	PGMRZDynMapStartAutoSet(pVCpu);
1054	int rc = trpmGCTrap0dHandler(pVM, pTrpmCpu, pRegFrame);
1055	switch (rc)
1056	{
1057	case VINF_EM_RAW_GUEST_TRAP:
1058	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1059	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1060	rc = VINF_PATM_PATCH_TRAP_GP;
1061	break;
1062
1063	case VINF_EM_RAW_INTERRUPT_PENDING:
1064	Assert(TRPMHasTrap(pVCpu));
1065	/* no break; */
1066	case VINF_PGM_SYNC_CR3: /** @todo Check this with Sander. */
1067	case VINF_EM_RAW_EMULATE_INSTR:
1068	case VINF_IOM_HC_IOPORT_READ:
1069	case VINF_IOM_HC_IOPORT_WRITE:
1070	case VINF_IOM_HC_MMIO_WRITE:
1071	case VINF_IOM_HC_MMIO_READ:
1072	case VINF_IOM_HC_MMIO_READ_WRITE:
1073	case VINF_PATM_PATCH_INT3:
1074	case VINF_EM_NO_MEMORY:
1075	case VINF_EM_RAW_TO_R3:
1076	case VINF_EM_RAW_TIMER_PENDING:
1077	case VINF_EM_PENDING_REQUEST:
1078	case VINF_EM_HALT:
1079	case VINF_SUCCESS:
1080	break;
1081
1082	default:
1083	AssertMsg(PATMIsPatchGCAddr(pVM, pRegFrame->eip) == false, ("return code %d\n", rc));
1084	break;
1085	}
1086	Log6(("TRPMGC0d: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
1087	return rc;
1088	}
1089
1090
1091	/**
1092	* \#PF (Page Fault) handler.
1093	*
1094	* Calls PGM which does the actual handling.
1095	*
1096	*
1097	* @returns VBox status code.
1098	* VINF_SUCCESS means we completely handled this trap,
1099	* other codes are passed execution to host context.
1100	*
1101	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1102	* @param pRegFrame Pointer to the register frame for the trap.
1103	* @internal
1104	*/
1105	DECLASM(int) TRPMGCTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1106	{
1107	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
1108	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1109
1110	LogFlow(("TRPMGC0e: %04x:%08x err=%x cr2=%08x\n", pRegFrame->cs, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, (uint32_t)pVCpu->trpm.s.uActiveCR2));
1111
1112	/*
1113	* This is all PGM stuff.
1114	*/
1115	PGMRZDynMapStartAutoSet(pVCpu);
1116	int rc = PGMTrap0eHandler(pVCpu, pVCpu->trpm.s.uActiveErrorCode, pRegFrame, (RTGCPTR)pVCpu->trpm.s.uActiveCR2);
1117	switch (rc)
1118	{
1119	case VINF_EM_RAW_EMULATE_INSTR:
1120	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
1121	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
1122	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
1123	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
1124	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
1125	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1126	rc = VINF_PATCH_EMULATE_INSTR;
1127	break;
1128
1129	case VINF_EM_RAW_GUEST_TRAP:
1130	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1131	{
1132	PGMRZDynMapReleaseAutoSet(pVCpu);
1133	return VINF_PATM_PATCH_TRAP_PF;
1134	}
1135
1136	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xE, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xe);
1137	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
1138	break;
1139
1140	case VINF_EM_RAW_INTERRUPT_PENDING:
1141	Assert(TRPMHasTrap(pVCpu));
1142	/* no break; */
1143	case VINF_IOM_HC_MMIO_READ:
1144	case VINF_IOM_HC_MMIO_WRITE:
1145	case VINF_IOM_HC_MMIO_READ_WRITE:
1146	case VINF_PATM_HC_MMIO_PATCH_READ:
1147	case VINF_PATM_HC_MMIO_PATCH_WRITE:
1148	case VINF_SUCCESS:
1149	case VINF_EM_RAW_TO_R3:
1150	case VINF_EM_PENDING_REQUEST:
1151	case VINF_EM_RAW_TIMER_PENDING:
1152	case VINF_EM_NO_MEMORY:
1153	case VINF_CSAM_PENDING_ACTION:
1154	case VINF_PGM_SYNC_CR3: /** @todo Check this with Sander. */
1155	break;
1156
1157	default:
1158	AssertMsg(PATMIsPatchGCAddr(pVM, pRegFrame->eip) == false, ("Patch address for return code %d. eip=%08x\n", rc, pRegFrame->eip));
1159	break;
1160	}
1161	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1162	Log6(("TRPMGC0e: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
1163	return rc;
1164	}
1165
1166
1167	/**
1168	* Scans for the EIP in the specified array of trap handlers.
1169	*
1170	* If we don't fine the EIP, we'll panic.
1171	*
1172	* @returns VBox status code.
1173	*
1174	* @param pVM The VM handle.
1175	* @param pRegFrame Pointer to the register frame for the trap.
1176	* @param paHandlers The array of trap handler records.
1177	* @param pEndRecord The end record (exclusive).
1178	*/
1179	static int trpmGCHyperGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, PCTRPMGCHYPER paHandlers, PCTRPMGCHYPER pEndRecord)
1180	{
1181	uintptr_t uEip = (uintptr_t)pRegFrame->eip;
1182	Assert(paHandlers <= pEndRecord);
1183
1184	Log(("trpmGCHyperGeneric: uEip=%x %p-%p\n", uEip, paHandlers, pEndRecord));
1185
1186	#if 0 /// @todo later
1187	/*
1188	* Start by doing a kind of binary search.
1189	*/
1190	unsigned iStart = 0;
1191	unsigned iEnd = pEndRecord - paHandlers;
1192	unsigned i = iEnd / 2;
1193	#endif
1194
1195	/*
1196	* Do a linear search now (in case the array wasn't properly sorted).
1197	*/
1198	for (PCTRPMGCHYPER pCur = paHandlers; pCur < pEndRecord; pCur++)
1199	{
1200	if ( pCur->uStartEIP <= uEip
1201	&& (pCur->uEndEIP ? pCur->uEndEIP > uEip : pCur->uStartEIP == uEip))
1202	return pCur->pfnHandler(pVM, pRegFrame, pCur->uUser);
1203	}
1204
1205	return VERR_TRPM_DONT_PANIC;
1206	}
1207
1208
1209	/**
1210	* Hypervisor \#NP ((segment) Not Present) handler.
1211	*
1212	* Scans for the EIP in the registered trap handlers.
1213	*
1214	* @returns VBox status code.
1215	* VINF_SUCCESS means we completely handled this trap,
1216	* other codes are passed back to host context.
1217	*
1218	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1219	* @param pRegFrame Pointer to the register frame for the trap.
1220	* @internal
1221	*/
1222	DECLASM(int) TRPMGCHyperTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1223	{
1224	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0bHandlers, g_aTrap0bHandlersEnd);
1225	}
1226
1227
1228	/**
1229	* Hypervisor \#GP (General Protection Fault) handler.
1230	*
1231	* Scans for the EIP in the registered trap handlers.
1232	*
1233	* @returns VBox status code.
1234	* VINF_SUCCESS means we completely handled this trap,
1235	* other codes are passed back to host context.
1236	*
1237	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1238	* @param pRegFrame Pointer to the register frame for the trap.
1239	* @internal
1240	*/
1241	DECLASM(int) TRPMGCHyperTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1242	{
1243	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);
1244	}
1245
1246
1247	/**
1248	* Hypervisor \#PF (Page Fault) handler.
1249	*
1250	* Scans for the EIP in the registered trap handlers.
1251	*
1252	* @returns VBox status code.
1253	* VINF_SUCCESS means we completely handled this trap,
1254	* other codes are passed back to host context.
1255	*
1256	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1257	* @param pRegFrame Pointer to the register frame for the trap.
1258	* @internal
1259	*/
1260	DECLASM(int) TRPMGCHyperTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1261	{
1262	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);
1263	}
1264
1265
1266	/**
1267	* Deal with hypervisor traps occuring when resuming execution on a trap.
1268	*
1269	* @returns VBox status code.
1270	* @param pVM The VM handle.
1271	* @param pRegFrame Register frame.
1272	* @param uUser User arg.
1273	*/
1274	DECLCALLBACK(int) trpmGCTrapInGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser)
1275	{
1276	Log(("********************************************************\n"));
1277	Log(("trpmGCTrapInGeneric: eip=%RX32 uUser=%#x\n", pRegFrame->eip, uUser));
1278	Log(("********************************************************\n"));
1279
1280	if (uUser & TRPM_TRAP_IN_HYPER)
1281	{
1282	/*
1283	* Check that there is still some stack left, if not we'll flag
1284	* a guru meditation (the alternative is a triple fault).
1285	*/
1286	RTRCUINTPTR cbStackUsed = (RTRCUINTPTR)VMMGetStackRC(VMMGetCpu(pVM)) - pRegFrame->esp;
1287	if (cbStackUsed > VMM_STACK_SIZE - _1K)
1288	{
1289	LogRel(("trpmGCTrapInGeneric: ran out of stack: esp=#x cbStackUsed=%#x\n", pRegFrame->esp, cbStackUsed));
1290	return VERR_TRPM_DONT_PANIC;
1291	}
1292
1293	/*
1294	* Just zero the register containing the selector in question.
1295	* We'll deal with the actual stale or troublesome selector value in
1296	* the outermost trap frame.
1297	*/
1298	switch (uUser & TRPM_TRAP_IN_OP_MASK)
1299	{
1300	case TRPM_TRAP_IN_MOV_GS:
1301	pRegFrame->eax = 0;
1302	pRegFrame->gs = 0; /* prevent recursive trouble. */
1303	break;
1304	case TRPM_TRAP_IN_MOV_FS:
1305	pRegFrame->eax = 0;
1306	pRegFrame->fs = 0; /* prevent recursive trouble. */
1307	return VINF_SUCCESS;
1308
1309	default:
1310	AssertMsgFailed(("Invalid uUser=%#x\n", uUser));
1311	return VERR_INTERNAL_ERROR;
1312	}
1313	}
1314	else
1315	{
1316	/*
1317	* Reconstruct the guest context and switch to the recompiler.
1318	* We ASSUME we're only at
1319	*/
1320	CPUMCTXCORE CtxCore = *pRegFrame;
1321	uint32_t pEsp = (uint32_t )pRegFrame->esp;
1322	int rc;
1323
1324	switch (uUser)
1325	{
1326	/*
1327	* This will only occur when resuming guest code in a trap handler!
1328	*/
1329	/* @note ASSUMES esp points to the temporary guest CPUMCTXCORE!!! */
1330	case TRPM_TRAP_IN_MOV_GS:
1331	case TRPM_TRAP_IN_MOV_FS:
1332	case TRPM_TRAP_IN_MOV_ES:
1333	case TRPM_TRAP_IN_MOV_DS:
1334	{
1335	PCPUMCTXCORE pTempGuestCtx = (PCPUMCTXCORE)pEsp;
1336
1337	/* Just copy the whole thing; several selector registers, eip (etc) and eax are not yet in pRegFrame. */
1338	CtxCore = *pTempGuestCtx;
1339	rc = VINF_EM_RAW_STALE_SELECTOR;
1340	break;
1341	}
1342
1343	/*
1344	* This will only occur when resuming guest code!
1345	*/
1346	case TRPM_TRAP_IN_IRET:
1347	CtxCore.eip = *pEsp++;
1348	CtxCore.cs = (RTSEL)*pEsp++;
1349	CtxCore.eflags.u32 = *pEsp++;
1350	CtxCore.esp = *pEsp++;
1351	CtxCore.ss = (RTSEL)*pEsp++;
1352	rc = VINF_EM_RAW_IRET_TRAP;
1353	break;
1354
1355	/*
1356	* This will only occur when resuming V86 guest code!
1357	*/
1358	case TRPM_TRAP_IN_IRET \| TRPM_TRAP_IN_V86:
1359	CtxCore.eip = *pEsp++;
1360	CtxCore.cs = (RTSEL)*pEsp++;
1361	CtxCore.eflags.u32 = *pEsp++;
1362	CtxCore.esp = *pEsp++;
1363	CtxCore.ss = (RTSEL)*pEsp++;
1364	CtxCore.es = (RTSEL)*pEsp++;
1365	CtxCore.ds = (RTSEL)*pEsp++;
1366	CtxCore.fs = (RTSEL)*pEsp++;
1367	CtxCore.gs = (RTSEL)*pEsp++;
1368	rc = VINF_EM_RAW_IRET_TRAP;
1369	break;
1370
1371	default:
1372	AssertMsgFailed(("Invalid uUser=%#x\n", uUser));
1373	return VERR_INTERNAL_ERROR;
1374	}
1375
1376
1377	CPUMSetGuestCtxCore(VMMGetCpu0(pVM), &CtxCore);
1378	TRPMGCHyperReturnToHost(pVM, rc);
1379	}
1380
1381	AssertMsgFailed(("Impossible!\n"));
1382	return VERR_INTERNAL_ERROR;
1383	}
1384

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source: vbox/trunk/src/VBox/VMM/VMMGC/TRPMGCHandlers.cpp@ 31604

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