CPUMR0.cpp@ 107611

Last change on this file since 107611 was 107389, checked in by vboxsync, 3 months ago
VMM/CPUM: The CPUMFEATURE structures can't be in target specific headers, since we need them for the host CPU as well. jiraref:VBP-1470
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1	/* $Id: CPUMR0.cpp 107389 2024-12-19 15:55:08Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0, only targeting x86.
4	*/
5
6	/*
7	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#define VBOX_VMM_TARGET_X86
34	#define CPUM_WITH_NONCONST_HOST_FEATURES
35	#include <VBox/vmm/cpum.h>
36	#include <VBox/vmm/hm.h>
37	#include "CPUMInternal.h"
38	#include <VBox/vmm/vmcc.h>
39	#include <VBox/vmm/gvm.h>
40	#include <VBox/err.h>
41	#include <VBox/log.h>
42	#include <VBox/vmm/hm.h>
43	#include <iprt/assert.h>
44	#include <iprt/asm-amd64-x86.h>
45	#include <iprt/mem.h>
46	#include <iprt/x86.h>
47
48
49	/*********************************************************************************************************************************
50	* Global Variables *
51	*********************************************************************************************************************************/
52	/** Host CPU features. */
53	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
54	/** Static storage for host MSRs. */
55	static CPUMMSRS g_CpumHostMsrs;
56
57	/**
58	* CPUID bits to unify among all cores.
59	*/
60	static struct
61	{
62	uint32_t uLeaf; /*< Leaf to check. /
63	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
64	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
65	}
66	const g_aCpuidUnifyBits[] =
67	{
68	{
69	0x00000001,
70	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
71	X86_CPUID_FEATURE_EDX_CX8
72	}
73	};
74
75
76
77	/*********************************************************************************************************************************
78	* Internal Functions *
79	*********************************************************************************************************************************/
80	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu);
81
82
83	/**
84	* Check the CPUID features of this particular CPU and disable relevant features
85	* for the guest which do not exist on this CPU.
86	*
87	* We have seen systems where the X86_CPUID_FEATURE_ECX_MONITOR feature flag is
88	* only set on some host CPUs, see @bugref{5436}.
89	*
90	* @note This function might be called simultaneously on more than one CPU!
91	*
92	* @param idCpu The identifier for the CPU the function is called on.
93	* @param pvUser1 Leaf array.
94	* @param pvUser2 Number of leaves.
95	*/
96	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
97	{
98	PCPUMCPUIDLEAF const paLeaves = (PCPUMCPUIDLEAF)pvUser1;
99	uint32_t const cLeaves = (uint32_t)(uintptr_t)pvUser2;
100	RT_NOREF(idCpu);
101
102	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
103	{
104	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, g_aCpuidUnifyBits[i].uLeaf, 0);
105	if (pLeaf)
106	{
107	uint32_t uEax, uEbx, uEcx, uEdx;
108	ASMCpuIdExSlow(g_aCpuidUnifyBits[i].uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
109
110	ASMAtomicAndU32(&pLeaf->uEcx, uEcx \| ~g_aCpuidUnifyBits[i].uEcx);
111	ASMAtomicAndU32(&pLeaf->uEdx, uEdx \| ~g_aCpuidUnifyBits[i].uEdx);
112	}
113	}
114	}
115
116
117	/**
118	* Does the Ring-0 CPU initialization once during module load.
119	* XXX Host-CPU hot-plugging?
120	*/
121	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
122	{
123	/*
124	* Query the hardware virtualization capabilities of the host CPU first.
125	*/
126	uint32_t fHwCaps = 0;
127	int rc = SUPR0GetVTSupport(&fHwCaps);
128	AssertLogRelMsg(RT_SUCCESS(rc) \|\| rc == VERR_UNSUPPORTED_CPU \|\| rc == VERR_SVM_NO_SVM \|\| rc == VERR_VMX_NO_VMX,
129	("SUPR0GetHwvirtMsrs -> %Rrc\n", rc));
130	if (RT_SUCCESS(rc))
131	{
132	SUPHWVIRTMSRS HwvirtMsrs;
133	rc = SUPR0GetHwvirtMsrs(&HwvirtMsrs, fHwCaps, false /fIgnored/);
134	AssertLogRelRC(rc);
135	if (RT_SUCCESS(rc))
136	{
137	if (fHwCaps & SUPVTCAPS_VT_X)
138	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.vmx);
139	else
140	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.svm);
141	}
142	}
143
144	/*
145	* Collect CPUID leaves.
146	*/
147	PCPUMCPUIDLEAF paLeaves;
148	uint32_t cLeaves;
149	rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
150	AssertLogRelRCReturn(rc, rc);
151
152	/*
153	* Unify/cross check some CPUID feature bits on all available CPU cores
154	* and threads. We've seen CPUs where the monitor support differed.
155	*/
156	RTMpOnAll(cpumR0CheckCpuid, paLeaves, (void *)(uintptr_t)cLeaves);
157
158	/*
159	* Populate the host CPU feature global variable.
160	*/
161	rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &g_CpumHostMsrs, &g_CpumHostFeatures.s);
162	RTMemFree(paLeaves);
163	AssertLogRelRCReturn(rc, rc);
164
165	/*
166	* Get MSR_IA32_ARCH_CAPABILITIES and expand it into the host feature structure.
167	*/
168	if (ASMHasCpuId())
169	{
170	/** @todo Should add this MSR to CPUMMSRS and expose it via SUPDrv... */
171	g_CpumHostFeatures.s.fArchRdclNo = 0;
172	g_CpumHostFeatures.s.fArchIbrsAll = 0;
173	g_CpumHostFeatures.s.fArchRsbOverride = 0;
174	g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = 0;
175	g_CpumHostFeatures.s.fArchMdsNo = 0;
176	uint32_t const cStdRange = ASMCpuId_EAX(0);
177	if ( RTX86IsValidStdRange(cStdRange)
178	&& cStdRange >= 7)
179	{
180	uint32_t const fStdFeaturesEdx = ASMCpuId_EDX(1);
181	uint32_t fStdExtFeaturesEdx;
182	ASMCpuIdExSlow(7, 0, 0, 0, NULL, NULL, NULL, &fStdExtFeaturesEdx);
183	if ( (fStdExtFeaturesEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
184	&& (fStdFeaturesEdx & X86_CPUID_FEATURE_EDX_MSR))
185	{
186	uint64_t fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
187	g_CpumHostFeatures.s.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
188	g_CpumHostFeatures.s.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
189	g_CpumHostFeatures.s.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
190	g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
191	g_CpumHostFeatures.s.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
192	}
193	else
194	g_CpumHostFeatures.s.fArchCap = 0;
195	}
196	}
197
198	return VINF_SUCCESS;
199	}
200
201
202	/**
203	* Terminate the module.
204	*/
205	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
206	{
207	return VINF_SUCCESS;
208	}
209
210
211	/**
212	* Initializes the CPUM data in the VM structure.
213	*
214	* @param pGVM The global VM structure.
215	*/
216	VMMR0_INT_DECL(void) CPUMR0InitPerVMData(PGVM pGVM)
217	{
218	/* Copy the ring-0 host feature set to the shared part so ring-3 can pick it up. */
219	pGVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
220	}
221
222
223	/**
224	* Check the CPUID features of this particular CPU and disable relevant features
225	* for the guest which do not exist on this CPU. We have seen systems where the
226	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
227	* @bugref{5436}.
228	*
229	* @note This function might be called simultaneously on more than one CPU!
230	*
231	* @param idCpu The identifier for the CPU the function is called on.
232	* @param pvUser1 Pointer to the VM structure.
233	* @param pvUser2 Ignored.
234	*/
235	static DECLCALLBACK(void) cpumR0CheckCpuidLegacy(RTCPUID idCpu, void pvUser1, void pvUser2)
236	{
237	PVMCC pVM = (PVMCC)pvUser1;
238
239	NOREF(idCpu); NOREF(pvUser2);
240	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
241	{
242	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
243	necessarily in the VM process context. So, we using the
244	legacy arrays as temporary storage. */
245
246	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
247	PCPUMCPUID pLegacyLeaf;
248	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
249	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
250	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
251	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
252	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
253	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
254	else
255	continue;
256
257	uint32_t eax, ebx, ecx, edx;
258	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
259
260	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
261	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
262	}
263	}
264
265
266	/**
267	* Does Ring-0 CPUM initialization.
268	*
269	* This is mainly to check that the Host CPU mode is compatible
270	* with VBox.
271	*
272	* @returns VBox status code.
273	* @param pVM The cross context VM structure.
274	*/
275	VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM)
276	{
277	LogFlow(("CPUMR0Init: %p\n", pVM));
278	AssertCompile(sizeof(pVM->aCpus[0].cpum.s.Host.abXState) >= sizeof(pVM->aCpus[0].cpum.s.Guest.abXState));
279
280	/*
281	* Check CR0 & CR4 flags.
282	*/
283	uint32_t u32CR0 = ASMGetCR0();
284	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
285	{
286	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
287	return VERR_UNSUPPORTED_CPU_MODE;
288	}
289
290	/*
291	* Check for sysenter and syscall usage.
292	*/
293	if (ASMHasCpuId())
294	{
295	/*
296	* SYSENTER/SYSEXIT
297	*
298	* Intel docs claim you should test both the flag and family, model &
299	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
300	* but don't support it. AMD CPUs may support this feature in legacy
301	* mode, they've banned it from long mode. Since we switch to 32-bit
302	* mode when entering raw-mode context the feature would become
303	* accessible again on AMD CPUs, so we have to check regardless of
304	* host bitness.
305	*/
306	uint32_t u32CpuVersion;
307	uint32_t u32Dummy;
308	uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
309	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
310	uint32_t const u32Family = u32CpuVersion >> 8;
311	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
312	uint32_t const u32Stepping = u32CpuVersion & 0xF;
313	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
314	&& ( u32Family != 6 /* (> pentium pro) */
315	\|\| u32Model >= 3
316	\|\| u32Stepping >= 3
317	\|\| !ASMIsIntelCpu())
318	)
319	{
320	/*
321	* Read the MSR and see if it's in use or not.
322	*/
323	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
324	if (u32)
325	{
326	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
327	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
328	}
329	}
330
331	/*
332	* SYSCALL/SYSRET
333	*
334	* This feature is indicated by the SEP bit returned in EDX by CPUID
335	* function 0x80000001. Intel CPUs only supports this feature in
336	* long mode. Since we're not running 64-bit guests in raw-mode there
337	* are no issues with 32-bit intel hosts.
338	*/
339	uint32_t cExt = 0;
340	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
341	if (RTX86IsValidExtRange(cExt))
342	{
343	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
344	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
345	{
346	#ifdef RT_ARCH_X86
347	if (!ASMIsIntelCpu())
348	#endif
349	{
350	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
351	if (fEfer & MSR_K6_EFER_SCE)
352	{
353	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
354	Log(("CPUMR0Init: host uses syscall\n"));
355	}
356	}
357	}
358	}
359
360	/*
361	* Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host and guest feature
362	* structure and as well as the guest MSR.
363	* Note! we assume this happens after the CPUMR3Init is done, so CPUID bits are settled.
364	*/
365	pVM->cpum.s.HostFeatures.fArchRdclNo = 0;
366	pVM->cpum.s.HostFeatures.fArchIbrsAll = 0;
367	pVM->cpum.s.HostFeatures.fArchRsbOverride = 0;
368	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
369	pVM->cpum.s.HostFeatures.fArchMdsNo = 0;
370	uint32_t const cStdRange = ASMCpuId_EAX(0);
371	if ( RTX86IsValidStdRange(cStdRange)
372	&& cStdRange >= 7)
373	{
374	uint32_t fEdxFeatures;
375	ASMCpuId_Idx_ECX(7, 0, &u32Dummy, &u32Dummy, &u32Dummy, &fEdxFeatures);
376	if ( (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
377	&& (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
378	{
379	/* Host: */
380	uint64_t const fHostArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
381	uint64_t fArchVal = fHostArchVal;
382	pVM->cpum.s.HostFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
383	pVM->cpum.s.HostFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
384	pVM->cpum.s.HostFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
385	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
386	pVM->cpum.s.HostFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
387
388	/* guest: */
389	if (!pVM->cpum.s.GuestFeatures.fArchCap)
390	fArchVal = 0;
391	else if (!pVM->cpum.s.GuestFeatures.fIbrs)
392	fArchVal &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL;
393	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps = fArchVal);
394	pVM->cpum.s.GuestFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
395	pVM->cpum.s.GuestFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
396	pVM->cpum.s.GuestFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
397	pVM->cpum.s.GuestFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
398	pVM->cpum.s.GuestFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
399	LogRel(("CPUM: IA32_ARCH_CAPABILITIES (Host=%#RX64 Guest=%#RX64)\n", fHostArchVal, fArchVal));
400	}
401	else
402	{
403	pVM->cpum.s.HostFeatures.fArchCap = 0;
404	LogRel(("CPUM: IA32_ARCH_CAPABILITIES unsupported\n"));
405	}
406	}
407
408	/*
409	* Unify/cross check some CPUID feature bits on all available CPU cores
410	* and threads. We've seen CPUs where the monitor support differed.
411	*
412	* Because the hyper heap isn't always mapped into ring-0, we cannot
413	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
414	* as temp ring-0 accessible memory instead, ASSUMING that they're all
415	* up to date when we get here.
416	*/
417	RTMpOnAll(cpumR0CheckCpuidLegacy, pVM, NULL);
418
419	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
420	{
421	bool fIgnored;
422	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
423	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
424	if (pLeaf)
425	{
426	PCPUMCPUID pLegacyLeaf;
427	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
428	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
429	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
430	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
431	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
432	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
433	else
434	continue;
435
436	pLeaf->uEcx = pLegacyLeaf->uEcx;
437	pLeaf->uEdx = pLegacyLeaf->uEdx;
438	}
439	}
440
441	}
442
443
444	/*
445	* Check if debug registers are armed.
446	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
447	*/
448	uint32_t u32DR7 = ASMGetDR7();
449	if (u32DR7 & X86_DR7_ENABLED_MASK)
450	{
451	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST);
452	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
453	}
454
455	return VINF_SUCCESS;
456	}
457
458
459	/**
460	* Trap handler for device-not-available fault (\#NM).
461	* Device not available, FP or (F)WAIT instruction.
462	*
463	* @returns VBox status code.
464	* @retval VINF_SUCCESS if the guest FPU state is loaded.
465	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
466	* @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
467	*
468	* @param pVM The cross context VM structure.
469	* @param pVCpu The cross context virtual CPU structure.
470	*/
471	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu)
472	{
473	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
474	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
475
476	/* If the FPU state has already been loaded, then it's a guest trap. */
477	if (CPUMIsGuestFPUStateActive(pVCpu))
478	{
479	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
480	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
481	return VINF_EM_RAW_GUEST_TRAP;
482	}
483
484	/*
485	* There are two basic actions:
486	* 1. Save host fpu and restore guest fpu.
487	* 2. Generate guest trap.
488	*
489	* When entering the hypervisor we'll always enable MP (for proper wait
490	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
491	* is taken from the guest OS in order to get proper SSE handling.
492	*
493	*
494	* Actions taken depending on the guest CR0 flags:
495	*
496	* 3 2 1
497	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
498	* ------------------------------------------------------------------------
499	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
500	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
501	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
502	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
503	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
504	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
505	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
506	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
507	*/
508
509	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
510	{
511	case X86_CR0_MP \| X86_CR0_TS:
512	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
513	return VINF_EM_RAW_GUEST_TRAP;
514	default:
515	break;
516	}
517
518	return CPUMR0LoadGuestFPU(pVM, pVCpu);
519	}
520
521
522	/**
523	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
524	* state into the CPU.
525	*
526	* @returns VINF_SUCCESS on success, host CR0 unmodified.
527	* @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
528	* modified and VT-x needs to update the value in the VMCS.
529	*
530	* @param pVM The cross context VM structure.
531	* @param pVCpu The cross context virtual CPU structure.
532	*/
533	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu)
534	{
535	int rc;
536	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
537	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
538
539	/* Notify the support driver prior to loading the guest-FPU register state. */
540	SUPR0FpuBegin(VMMR0ThreadCtxHookIsEnabled(pVCpu));
541	/** @todo use return value? Currently skipping that to be on the safe side
542	* wrt. extended state (linux). */
543
544	if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
545	{
546	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
547	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
548	}
549	else
550	{
551	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
552	/** @todo r=ramshankar: Can't we used a cached value here
553	* instead of reading the MSR? host EFER doesn't usually
554	* change. */
555	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
556	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
557	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
558	else
559	{
560	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
561	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
562	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
563	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
564	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
565	ASMSetFlags(uSavedFlags);
566	}
567	}
568	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
569	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
570	Assert(pVCpu->cpum.s.Guest.fUsedFpuGuest);
571	return rc;
572	}
573
574
575	/**
576	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
577	* needed.
578	*
579	* @returns true if we saved the guest state.
580	* @param pVCpu The cross context virtual CPU structure.
581	*/
582	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu)
583	{
584	bool fSavedGuest;
585	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
586	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
587	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
588	{
589	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
590	Assert(fSavedGuest == pVCpu->cpum.s.Guest.fUsedFpuGuest);
591	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
592	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
593	else
594	{
595	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
596	save/restore the XMM state with fxsave/fxrstor. */
597	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
598	if (uHostEfer & MSR_K6_EFER_FFXSR)
599	{
600	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
601	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
602	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
603	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
604	ASMSetFlags(uSavedFlags);
605	}
606	else
607	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
608	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
609	}
610
611	/* Notify the support driver after loading the host-FPU register state. */
612	SUPR0FpuEnd(VMMR0ThreadCtxHookIsEnabled(pVCpu));
613	}
614	else
615	fSavedGuest = false;
616	Assert(!( pVCpu->cpum.s.fUseFlags
617	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_MANUAL_XMM_RESTORE)));
618	Assert(!pVCpu->cpum.s.Guest.fUsedFpuGuest);
619	return fSavedGuest;
620	}
621
622
623	/**
624	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
625	* DR7 with safe values.
626	*
627	* @returns VBox status code.
628	* @param pVCpu The cross context virtual CPU structure.
629	*/
630	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu)
631	{
632	/*
633	* Save the host state.
634	*/
635	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
636	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
637	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
638	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
639	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
640	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
641	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
642
643	/* Preemption paranoia. */
644	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
645
646	/*
647	* Make sure DR7 is harmless or else we could trigger breakpoints when
648	* load guest or hypervisor DRx values later.
649	*/
650	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
651	ASMSetDR7(X86_DR7_INIT_VAL);
652
653	return VINF_SUCCESS;
654	}
655
656
657	/**
658	* Saves the guest DRx state residing in host registers and restore the host
659	* register values.
660	*
661	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
662	* since it's assumed that we're shadowing the guest DRx register values
663	* accurately when using the combined hypervisor debug register values
664	* (CPUMR0LoadHyperDebugState).
665	*
666	* @returns true if either guest or hypervisor debug registers were loaded.
667	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
668	* @param fDr6 Whether to include DR6 or not.
669	* @thread EMT(pVCpu)
670	*/
671	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6)
672	{
673	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
674	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
675
676	/*
677	* Do we need to save the guest DRx registered loaded into host registers?
678	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
679	*/
680	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
681	{
682	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
683	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
684	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
685	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
686	if (fDr6)
687	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6() \| X86_DR6_RA1_MASK; /* ASSUMES no guest supprot for TSX-NI / RTM. */
688	}
689	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~(CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
690
691	/*
692	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
693	*/
694	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
695	{
696	/* A bit of paranoia first... */
697	uint64_t uCurDR7 = ASMGetDR7();
698	if (uCurDR7 != X86_DR7_INIT_VAL)
699	ASMSetDR7(X86_DR7_INIT_VAL);
700
701	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
702	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
703	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
704	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
705	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
706	* expensive DRx reads are over DRx writes. */
707	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
708	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
709
710	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
711	}
712
713	return fDrXLoaded;
714	}
715
716
717	/**
718	* Saves the guest DRx state if it resides host registers.
719	*
720	* This does NOT clear any use flags, so the host registers remains loaded with
721	* the guest DRx state upon return. The purpose is only to make sure the values
722	* in the CPU context structure is up to date.
723	*
724	* @returns true if the host registers contains guest values, false if not.
725	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
726	* @param fDr6 Whether to include DR6 or not.
727	* @thread EMT(pVCpu)
728	*/
729	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6)
730	{
731	/*
732	* Do we need to save the guest DRx registered loaded into host registers?
733	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
734	*/
735	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
736	{
737	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
738	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
739	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
740	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
741	if (fDr6)
742	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
743	return true;
744	}
745	return false;
746	}
747
748
749	/**
750	* Lazily sync in the debug state.
751	*
752	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
753	* @param fDr6 Whether to include DR6 or not.
754	* @thread EMT(pVCpu)
755	*/
756	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6)
757	{
758	/*
759	* Save the host state and disarm all host BPs.
760	*/
761	cpumR0SaveHostDebugState(pVCpu);
762	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
763
764	/*
765	* Activate the guest state DR0-3.
766	* DR7 and DR6 (if fDr6 is true) are left to the caller.
767	*/
768	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
769	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
770	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
771	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
772	if (fDr6)
773	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
774
775	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
776	}
777
778
779	/**
780	* Lazily sync in the hypervisor debug state
781	*
782	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
783	* @param fDr6 Whether to include DR6 or not.
784	* @thread EMT(pVCpu)
785	*/
786	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6)
787	{
788	/*
789	* Save the host state and disarm all host BPs.
790	*/
791	cpumR0SaveHostDebugState(pVCpu);
792	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
793
794	/*
795	* Make sure the hypervisor values are up to date.
796	*/
797	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
798
799	/*
800	* Activate the guest state DR0-3.
801	* DR7 and DR6 (if fDr6 is true) are left to the caller.
802	*/
803	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
804	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
805	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
806	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
807	if (fDr6)
808	ASMSetDR6(X86_DR6_INIT_VAL);
809
810	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
811	}
812

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 107611

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