CPUMR0.cpp@ 21667

Last change on this file since 21667 was 21562, checked in by vboxsync, 16 years ago
Paranoia
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 18.8 KB

Line
1	/* $Id: CPUMR0.cpp 21562 2009-07-14 08:24:42Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_CPUM
27	#include <VBox/cpum.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <VBox/hwaccm.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36
37
38
39	/**
40	* Does Ring-0 CPUM initialization.
41	*
42	* This is mainly to check that the Host CPU mode is compatible
43	* with VBox.
44	*
45	* @returns VBox status code.
46	* @param pVM The VM to operate on.
47	*/
48	VMMR0DECL(int) CPUMR0Init(PVM pVM)
49	{
50	LogFlow(("CPUMR0Init: %p\n", pVM));
51
52	/*
53	* Check CR0 & CR4 flags.
54	*/
55	uint32_t u32CR0 = ASMGetCR0();
56	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
57	{
58	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
59	return VERR_UNSUPPORTED_CPU_MODE;
60	}
61
62	/*
63	* Check for sysenter if it's used.
64	*/
65	if (ASMHasCpuId())
66	{
67	uint32_t u32CpuVersion;
68	uint32_t u32Dummy;
69	uint32_t u32Features;
70	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &u32Features);
71	uint32_t u32Family = u32CpuVersion >> 8;
72	uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
73	uint32_t u32Stepping = u32CpuVersion & 0xF;
74
75	/*
76	* Intel docs claim you should test both the flag and family, model & stepping.
77	* Some Pentium Pro cpus have the SEP cpuid flag set, but don't support it.
78	*/
79	if ( (u32Features & X86_CPUID_FEATURE_EDX_SEP)
80	&& !(u32Family == 6 && u32Model < 3 && u32Stepping < 3))
81	{
82	/*
83	* Read the MSR and see if it's in use or not.
84	*/
85	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
86	if (u32)
87	{
88	for (unsigned i=0;i<pVM->cCPUs;i++)
89	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_SYSENTER;
90
91	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
92	}
93	}
94
95	/** @todo check for AMD and syscall!!!!!! */
96	}
97
98
99	/*
100	* Check if debug registers are armed.
101	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
102	*/
103	uint32_t u32DR7 = ASMGetDR7();
104	if (u32DR7 & X86_DR7_ENABLED_MASK)
105	{
106	for (unsigned i=0;i<pVM->cCPUs;i++)
107	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
108	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
109	}
110
111	return VINF_SUCCESS;
112	}
113
114
115	/**
116	* Lazily sync in the FPU/XMM state
117	*
118	* @returns VBox status code.
119	* @param pVM VM handle.
120	* @param pVCpu VMCPU handle.
121	* @param pCtx CPU context
122	*/
123	VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
124	{
125	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
126	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
127
128	/* If the FPU state has already been loaded, then it's a guest trap. */
129	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU)
130	{
131	Assert( ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
132	\|\| ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS)));
133	return VINF_EM_RAW_GUEST_TRAP;
134	}
135
136	/*
137	* There are two basic actions:
138	* 1. Save host fpu and restore guest fpu.
139	* 2. Generate guest trap.
140	*
141	* When entering the hypervisor we'll always enable MP (for proper wait
142	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
143	* is taken from the guest OS in order to get proper SSE handling.
144	*
145	*
146	* Actions taken depending on the guest CR0 flags:
147	*
148	* 3 2 1
149	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
150	* ------------------------------------------------------------------------
151	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
152	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
153	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
154	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
155	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
156	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
157	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
158	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
159	*/
160
161	switch (pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
162	{
163	case X86_CR0_MP \| X86_CR0_TS:
164	case X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS:
165	return VINF_EM_RAW_GUEST_TRAP;
166	default:
167	break;
168	}
169
170	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
171	if (CPUMIsGuestInLongModeEx(pCtx))
172	{
173	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
174
175	/* Save the host state and record the fact (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM). */
176	cpumR0SaveHostFPUState(&pVCpu->cpum.s);
177
178	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
179	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
180	}
181	else
182	#endif
183	{
184	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
185	# if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined(VBOX_WITH_KERNEL_USING_XMM) /** @todo remove the #else here and move cpumHandleLazyFPUAsm back to VMMGC after branching out 3.0!!. */
186	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE));
187	/** @todo Move the FFXR handling down into
188	* cpumR0SaveHostRestoreguestFPUState to optimize the
189	* VBOX_WITH_KERNEL_USING_XMM handling. */
190	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
191	uint64_t SavedEFER = 0;
192	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
193	{
194	SavedEFER = ASMRdMsr(MSR_K6_EFER);
195	if (SavedEFER & MSR_K6_EFER_FFXSR)
196	{
197	ASMWrMsr(MSR_K6_EFER, SavedEFER & ~MSR_K6_EFER_FFXSR);
198	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
199	}
200	}
201
202	/* Do the job and record that we've switched FPU state. */
203	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
204
205	/* Restore EFER. */
206	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
207	ASMWrMsr(MSR_K6_EFER, SavedEFER);
208
209	# else
210	uint64_t oldMsrEFERHost = 0;
211	uint32_t oldCR0 = ASMGetCR0();
212
213	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
214	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
215	{
216	/** @todo Do we really need to read this every time?? The host could change this on the fly though.
217	* bird: what about starting by skipping the ASMWrMsr below if we didn't
218	* change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
219	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
220	if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
221	{
222	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
223	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
224	}
225	}
226
227	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
228	int rc = CPUMHandleLazyFPU(pVCpu);
229	AssertRC(rc);
230	Assert(CPUMIsGuestFPUStateActive(pVCpu));
231
232	/* Restore EFER MSR */
233	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
234	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
235
236	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
237	ASMSetCR0(oldCR0);
238	# endif
239
240	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
241
242	/*
243	* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
244	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
245	*/
246	pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
247	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
248	pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
249
250	cpumR0LoadFPU(pCtx);
251
252	/*
253	* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
254	*
255	* MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
256	*/
257	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
258	{
259	/** @todo Do we really need to read this every time?? The host could change this on the fly though. */
260	uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
261
262	if (msrEFERHost & MSR_K6_EFER_FFXSR)
263	{
264	/* fxrstor doesn't restore the XMM state! */
265	cpumR0LoadXMM(pCtx);
266	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
267	}
268	}
269
270	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
271	}
272
273	Assert((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM)) == (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM));
274	return VINF_SUCCESS;
275	}
276
277
278	/**
279	* Save guest FPU/XMM state
280	*
281	* @returns VBox status code.
282	* @param pVM VM handle.
283	* @param pVCpu VMCPU handle.
284	* @param pCtx CPU context
285	*/
286	VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
287	{
288	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
289	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
290	AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
291
292	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
293	if (CPUMIsGuestInLongModeEx(pCtx))
294	{
295	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
296	{
297	HWACCMR0SaveFPUState(pVM, pVCpu, pCtx);
298	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
299	}
300	/* else nothing to do; we didn't perform a world switch */
301	}
302	else
303	#endif
304	{
305	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
306	# ifdef VBOX_WITH_KERNEL_USING_XMM
307	/*
308	* We've already saved the XMM registers in the assembly wrapper, so
309	* we have to save them before saving the entire FPU state and put them
310	* back afterwards.
311	*/
312	/** @todo This could be skipped if MSR_K6_EFER_FFXSR is set, but
313	* I'm not able to test such an optimization tonight.
314	* We could just all this in assembly. */
315	uint128_t aGuestXmmRegs[16];
316	memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.fpu.aXMM[0], sizeof(aGuestXmmRegs));
317	# endif
318
319	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
320	uint64_t oldMsrEFERHost = 0;
321	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
322	{
323	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
324	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
325	}
326	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
327
328	/* Restore EFER MSR */
329	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
330	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost \| MSR_K6_EFER_FFXSR);
331
332	# ifdef VBOX_WITH_KERNEL_USING_XMM
333	memcpy(&pVCpu->cpum.s.Guest.fpu.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
334	# endif
335
336	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
337	# ifdef VBOX_WITH_KERNEL_USING_XMM
338	# error "Fix all the NM_TRAPS_IN_KERNEL_MODE code path. I'm not going to fix unused code now."
339	# endif
340	cpumR0SaveFPU(pCtx);
341	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
342	{
343	/* fxsave doesn't save the XMM state! */
344	cpumR0SaveXMM(pCtx);
345	}
346
347	/*
348	* Restore the original FPU control word and MXCSR.
349	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
350	*/
351	cpumR0SetFCW(pVCpu->cpum.s.Host.fpu.FCW);
352	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
353	cpumR0SetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
354	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
355	}
356
357	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU \| CPUM_SYNC_FPU_STATE \| CPUM_MANUAL_XMM_RESTORE);
358	return VINF_SUCCESS;
359	}
360
361
362	/**
363	* Save guest debug state
364	*
365	* @returns VBox status code.
366	* @param pVM VM handle.
367	* @param pVCpu VMCPU handle.
368	* @param pCtx CPU context
369	* @param fDR6 Include DR6 or not
370	*/
371	VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
372	{
373	Assert(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
374
375	/* Save the guest's debug state. The caller is responsible for DR7. */
376	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
377	if (CPUMIsGuestInLongModeEx(pCtx))
378	{
379	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_STATE))
380	{
381	uint64_t dr6 = pCtx->dr[6];
382
383	HWACCMR0SaveDebugState(pVM, pVCpu, pCtx);
384	if (!fDR6) /* dr6 was already up-to-date */
385	pCtx->dr[6] = dr6;
386	}
387	}
388	else
389	#endif
390	{
391	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
392	cpumR0SaveDRx(&pCtx->dr[0]);
393	#else
394	pCtx->dr[0] = ASMGetDR0();
395	pCtx->dr[1] = ASMGetDR1();
396	pCtx->dr[2] = ASMGetDR2();
397	pCtx->dr[3] = ASMGetDR3();
398	#endif
399	if (fDR6)
400	pCtx->dr[6] = ASMGetDR6();
401	}
402
403	/*
404	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
405	* DR7 contains 0x400 right now.
406	*/
407	CPUMR0LoadHostDebugState(pVM, pVCpu);
408	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS));
409	return VINF_SUCCESS;
410	}
411
412
413	/**
414	* Lazily sync in the debug state
415	*
416	* @returns VBox status code.
417	* @param pVM VM handle.
418	* @param pVCpu VMCPU handle.
419	* @param pCtx CPU context
420	* @param fDR6 Include DR6 or not
421	*/
422	VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
423	{
424	/* Save the host state. */
425	CPUMR0SaveHostDebugState(pVM, pVCpu);
426	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
427
428	/* Activate the guest state DR0-3; DR7 is left to the caller. */
429	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
430	if (CPUMIsGuestInLongModeEx(pCtx))
431	{
432	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
433	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_DEBUG_STATE;
434	}
435	else
436	#endif
437	{
438	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
439	cpumR0LoadDRx(&pCtx->dr[0]);
440	#else
441	ASMSetDR0(pCtx->dr[0]);
442	ASMSetDR1(pCtx->dr[1]);
443	ASMSetDR2(pCtx->dr[2]);
444	ASMSetDR3(pCtx->dr[3]);
445	#endif
446	if (fDR6)
447	ASMSetDR6(pCtx->dr[6]);
448	}
449
450	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS;
451	return VINF_SUCCESS;
452	}
453
454	/**
455	* Save the host debug state
456	*
457	* @returns VBox status code.
458	* @param pVM VM handle.
459	* @param pVCpu VMCPU handle.
460	*/
461	VMMR0DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu)
462	{
463	/* Save the host state. */
464	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
465	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
466	cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
467	#else
468	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
469	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
470	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
471	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
472	#endif
473	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
474	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
475	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
476	/* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
477	ASMSetDR7(X86_DR7_INIT_VAL);
478
479	return VINF_SUCCESS;
480	}
481
482	/**
483	* Load the host debug state
484	*
485	* @returns VBox status code.
486	* @param pVM VM handle.
487	* @param pVCpu VMCPU handle.
488	*/
489	VMMR0DECL(int) CPUMR0LoadHostDebugState(PVM pVM, PVMCPU pVCpu)
490	{
491	Assert(pVCpu->cpum.s.fUseFlags & (CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HYPER));
492
493	/*
494	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
495	* DR7 contains 0x400 right now.
496	*/
497	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
498	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
499	cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
500	#else
501	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
502	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
503	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
504	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
505	#endif
506	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
507	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
508
509	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HYPER);
510	return VINF_SUCCESS;
511	}
512
513
514	/**
515	* Lazily sync in the hypervisor debug state
516	*
517	* @returns VBox status code.
518	* @param pVM VM handle.
519	* @param pVCpu VMCPU handle.
520	* @param pCtx CPU context
521	* @param fDR6 Include DR6 or not
522	*/
523	VMMR0DECL(int) CPUMR0LoadHyperDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
524	{
525	/* Save the host state. */
526	CPUMR0SaveHostDebugState(pVM, pVCpu);
527	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
528
529	/* Activate the guest state DR0-3; DR7 is left to the caller. */
530	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
531	if (CPUMIsGuestInLongModeEx(pCtx))
532	{
533	AssertFailed();
534	return VERR_NOT_IMPLEMENTED;
535	}
536	else
537	#endif
538	{
539	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
540	AssertFailed();
541	return VERR_NOT_IMPLEMENTED;
542	#else
543	ASMSetDR0(CPUMGetHyperDR0(pVCpu));
544	ASMSetDR1(CPUMGetHyperDR1(pVCpu));
545	ASMSetDR2(CPUMGetHyperDR2(pVCpu));
546	ASMSetDR3(CPUMGetHyperDR3(pVCpu));
547	#endif
548	if (fDR6)
549	ASMSetDR6(CPUMGetHyperDR6(pVCpu));
550	}
551
552	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HYPER;
553	return VINF_SUCCESS;
554	}
555
556

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 21667

Download in other formats: