CPUMR0.cpp@ 25659

Last change on this file since 25659 was 22890, checked in by vboxsync, 15 years ago
VM::cCPUs -> VM::cCpus so it matches all the other cCpus and aCpus members.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 20.3 KB

Line
1	/* $Id: CPUMR0.cpp 22890 2009-09-09 23:11:31Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_CPUM
27	#include <VBox/cpum.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <VBox/hwaccm.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36
37
38
39	/**
40	* Does Ring-0 CPUM initialization.
41	*
42	* This is mainly to check that the Host CPU mode is compatible
43	* with VBox.
44	*
45	* @returns VBox status code.
46	* @param pVM The VM to operate on.
47	*/
48	VMMR0DECL(int) CPUMR0Init(PVM pVM)
49	{
50	LogFlow(("CPUMR0Init: %p\n", pVM));
51
52	/*
53	* Check CR0 & CR4 flags.
54	*/
55	uint32_t u32CR0 = ASMGetCR0();
56	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
57	{
58	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
59	return VERR_UNSUPPORTED_CPU_MODE;
60	}
61
62	/*
63	* Check for sysenter and syscall usage.
64	*/
65	if (ASMHasCpuId())
66	{
67	/*
68	* SYSENTER/SYSEXIT
69	*
70	* Intel docs claim you should test both the flag and family, model &
71	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
72	* but don't support it. AMD CPUs may support this feature in legacy
73	* mode, they've banned it from long mode. Since we switch to 32-bit
74	* mode when entering raw-mode context the feature would become
75	* accessible again on AMD CPUs, so we have to check regardless of
76	* host bitness.
77	*/
78	uint32_t u32CpuVersion;
79	uint32_t u32Dummy;
80	uint32_t fFeatures;
81	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
82	uint32_t u32Family = u32CpuVersion >> 8;
83	uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
84	uint32_t u32Stepping = u32CpuVersion & 0xF;
85	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
86	&& ( u32Family != 6 /* (> pentium pro) */
87	\|\| u32Model >= 3
88	\|\| u32Stepping >= 3
89	\|\| !ASMIsIntelCpu())
90	)
91	{
92	/*
93	* Read the MSR and see if it's in use or not.
94	*/
95	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
96	if (u32)
97	{
98	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
99	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
100	}
101	}
102
103	/*
104	* SYSCALL/SYSRET
105	*
106	* This feature is indicated by the SEP bit returned in EDX by CPUID
107	* function 0x80000001. Intel CPUs only supports this feature in
108	* long mode. Since we're not running 64-bit guests in raw-mode there
109	* are no issues with 32-bit intel hosts.
110	*/
111	uint32_t cExt = 0;
112	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
113	if ( cExt >= 0x80000001
114	&& cExt <= 0x8000ffff)
115	{
116	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
117	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_SEP)
118	{
119	#ifdef RT_ARCH_X86
120	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
121	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
122	# else
123	if (!ASMIsIntelCpu())
124	# endif
125	#endif
126	{
127	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
128	if (fEfer & MSR_K6_EFER_SCE)
129	{
130	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
131	Log(("CPUMR0Init: host uses syscall\n"));
132	}
133	}
134	}
135	}
136	}
137
138
139	/*
140	* Check if debug registers are armed.
141	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
142	*/
143	uint32_t u32DR7 = ASMGetDR7();
144	if (u32DR7 & X86_DR7_ENABLED_MASK)
145	{
146	for (VMCPUID i = 0; i < pVM->cCpus; i++)
147	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
148	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
149	}
150
151	return VINF_SUCCESS;
152	}
153
154
155	/**
156	* Lazily sync in the FPU/XMM state
157	*
158	* @returns VBox status code.
159	* @param pVM VM handle.
160	* @param pVCpu VMCPU handle.
161	* @param pCtx CPU context
162	*/
163	VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
164	{
165	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
166	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
167
168	/* If the FPU state has already been loaded, then it's a guest trap. */
169	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU)
170	{
171	Assert( ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
172	\|\| ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS)));
173	return VINF_EM_RAW_GUEST_TRAP;
174	}
175
176	/*
177	* There are two basic actions:
178	* 1. Save host fpu and restore guest fpu.
179	* 2. Generate guest trap.
180	*
181	* When entering the hypervisor we'll always enable MP (for proper wait
182	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
183	* is taken from the guest OS in order to get proper SSE handling.
184	*
185	*
186	* Actions taken depending on the guest CR0 flags:
187	*
188	* 3 2 1
189	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
190	* ------------------------------------------------------------------------
191	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
192	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
193	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
194	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
195	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
196	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
197	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
198	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
199	*/
200
201	switch (pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
202	{
203	case X86_CR0_MP \| X86_CR0_TS:
204	case X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS:
205	return VINF_EM_RAW_GUEST_TRAP;
206	default:
207	break;
208	}
209
210	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
211	if (CPUMIsGuestInLongModeEx(pCtx))
212	{
213	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
214
215	/* Save the host state and record the fact (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM). */
216	cpumR0SaveHostFPUState(&pVCpu->cpum.s);
217
218	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
219	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
220	}
221	else
222	#endif
223	{
224	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
225	# if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined(VBOX_WITH_KERNEL_USING_XMM) /** @todo remove the #else here and move cpumHandleLazyFPUAsm back to VMMGC after branching out 3.0!!. */
226	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE));
227	/** @todo Move the FFXR handling down into
228	* cpumR0SaveHostRestoreguestFPUState to optimize the
229	* VBOX_WITH_KERNEL_USING_XMM handling. */
230	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
231	uint64_t SavedEFER = 0;
232	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
233	{
234	SavedEFER = ASMRdMsr(MSR_K6_EFER);
235	if (SavedEFER & MSR_K6_EFER_FFXSR)
236	{
237	ASMWrMsr(MSR_K6_EFER, SavedEFER & ~MSR_K6_EFER_FFXSR);
238	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
239	}
240	}
241
242	/* Do the job and record that we've switched FPU state. */
243	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
244
245	/* Restore EFER. */
246	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
247	ASMWrMsr(MSR_K6_EFER, SavedEFER);
248
249	# else
250	uint64_t oldMsrEFERHost = 0;
251	uint32_t oldCR0 = ASMGetCR0();
252
253	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
254	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
255	{
256	/** @todo Do we really need to read this every time?? The host could change this on the fly though.
257	* bird: what about starting by skipping the ASMWrMsr below if we didn't
258	* change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
259	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
260	if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
261	{
262	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
263	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
264	}
265	}
266
267	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
268	int rc = CPUMHandleLazyFPU(pVCpu);
269	AssertRC(rc);
270	Assert(CPUMIsGuestFPUStateActive(pVCpu));
271
272	/* Restore EFER MSR */
273	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
274	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
275
276	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
277	ASMSetCR0(oldCR0);
278	# endif
279
280	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
281
282	/*
283	* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
284	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
285	*/
286	pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
287	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
288	pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
289
290	cpumR0LoadFPU(pCtx);
291
292	/*
293	* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
294	*
295	* MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
296	*/
297	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
298	{
299	/** @todo Do we really need to read this every time?? The host could change this on the fly though. */
300	uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
301
302	if (msrEFERHost & MSR_K6_EFER_FFXSR)
303	{
304	/* fxrstor doesn't restore the XMM state! */
305	cpumR0LoadXMM(pCtx);
306	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
307	}
308	}
309
310	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
311	}
312
313	Assert((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM)) == (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM));
314	return VINF_SUCCESS;
315	}
316
317
318	/**
319	* Save guest FPU/XMM state
320	*
321	* @returns VBox status code.
322	* @param pVM VM handle.
323	* @param pVCpu VMCPU handle.
324	* @param pCtx CPU context
325	*/
326	VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
327	{
328	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
329	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
330	AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
331
332	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
333	if (CPUMIsGuestInLongModeEx(pCtx))
334	{
335	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
336	{
337	HWACCMR0SaveFPUState(pVM, pVCpu, pCtx);
338	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
339	}
340	/* else nothing to do; we didn't perform a world switch */
341	}
342	else
343	#endif
344	{
345	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
346	# ifdef VBOX_WITH_KERNEL_USING_XMM
347	/*
348	* We've already saved the XMM registers in the assembly wrapper, so
349	* we have to save them before saving the entire FPU state and put them
350	* back afterwards.
351	*/
352	/** @todo This could be skipped if MSR_K6_EFER_FFXSR is set, but
353	* I'm not able to test such an optimization tonight.
354	* We could just all this in assembly. */
355	uint128_t aGuestXmmRegs[16];
356	memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.fpu.aXMM[0], sizeof(aGuestXmmRegs));
357	# endif
358
359	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
360	uint64_t oldMsrEFERHost = 0;
361	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
362	{
363	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
364	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
365	}
366	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
367
368	/* Restore EFER MSR */
369	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
370	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost \| MSR_K6_EFER_FFXSR);
371
372	# ifdef VBOX_WITH_KERNEL_USING_XMM
373	memcpy(&pVCpu->cpum.s.Guest.fpu.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
374	# endif
375
376	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
377	# ifdef VBOX_WITH_KERNEL_USING_XMM
378	# error "Fix all the NM_TRAPS_IN_KERNEL_MODE code path. I'm not going to fix unused code now."
379	# endif
380	cpumR0SaveFPU(pCtx);
381	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
382	{
383	/* fxsave doesn't save the XMM state! */
384	cpumR0SaveXMM(pCtx);
385	}
386
387	/*
388	* Restore the original FPU control word and MXCSR.
389	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
390	*/
391	cpumR0SetFCW(pVCpu->cpum.s.Host.fpu.FCW);
392	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
393	cpumR0SetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
394	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
395	}
396
397	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU \| CPUM_SYNC_FPU_STATE \| CPUM_MANUAL_XMM_RESTORE);
398	return VINF_SUCCESS;
399	}
400
401
402	/**
403	* Save guest debug state
404	*
405	* @returns VBox status code.
406	* @param pVM VM handle.
407	* @param pVCpu VMCPU handle.
408	* @param pCtx CPU context
409	* @param fDR6 Include DR6 or not
410	*/
411	VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
412	{
413	Assert(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
414
415	/* Save the guest's debug state. The caller is responsible for DR7. */
416	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
417	if (CPUMIsGuestInLongModeEx(pCtx))
418	{
419	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_STATE))
420	{
421	uint64_t dr6 = pCtx->dr[6];
422
423	HWACCMR0SaveDebugState(pVM, pVCpu, pCtx);
424	if (!fDR6) /* dr6 was already up-to-date */
425	pCtx->dr[6] = dr6;
426	}
427	}
428	else
429	#endif
430	{
431	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
432	cpumR0SaveDRx(&pCtx->dr[0]);
433	#else
434	pCtx->dr[0] = ASMGetDR0();
435	pCtx->dr[1] = ASMGetDR1();
436	pCtx->dr[2] = ASMGetDR2();
437	pCtx->dr[3] = ASMGetDR3();
438	#endif
439	if (fDR6)
440	pCtx->dr[6] = ASMGetDR6();
441	}
442
443	/*
444	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
445	* DR7 contains 0x400 right now.
446	*/
447	CPUMR0LoadHostDebugState(pVM, pVCpu);
448	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS));
449	return VINF_SUCCESS;
450	}
451
452
453	/**
454	* Lazily sync in the debug state
455	*
456	* @returns VBox status code.
457	* @param pVM VM handle.
458	* @param pVCpu VMCPU handle.
459	* @param pCtx CPU context
460	* @param fDR6 Include DR6 or not
461	*/
462	VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
463	{
464	/* Save the host state. */
465	CPUMR0SaveHostDebugState(pVM, pVCpu);
466	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
467
468	/* Activate the guest state DR0-3; DR7 is left to the caller. */
469	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
470	if (CPUMIsGuestInLongModeEx(pCtx))
471	{
472	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
473	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_DEBUG_STATE;
474	}
475	else
476	#endif
477	{
478	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
479	cpumR0LoadDRx(&pCtx->dr[0]);
480	#else
481	ASMSetDR0(pCtx->dr[0]);
482	ASMSetDR1(pCtx->dr[1]);
483	ASMSetDR2(pCtx->dr[2]);
484	ASMSetDR3(pCtx->dr[3]);
485	#endif
486	if (fDR6)
487	ASMSetDR6(pCtx->dr[6]);
488	}
489
490	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS;
491	return VINF_SUCCESS;
492	}
493
494	/**
495	* Save the host debug state
496	*
497	* @returns VBox status code.
498	* @param pVM VM handle.
499	* @param pVCpu VMCPU handle.
500	*/
501	VMMR0DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu)
502	{
503	/* Save the host state. */
504	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
505	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
506	cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
507	#else
508	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
509	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
510	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
511	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
512	#endif
513	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
514	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
515	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
516	/* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
517	ASMSetDR7(X86_DR7_INIT_VAL);
518
519	return VINF_SUCCESS;
520	}
521
522	/**
523	* Load the host debug state
524	*
525	* @returns VBox status code.
526	* @param pVM VM handle.
527	* @param pVCpu VMCPU handle.
528	*/
529	VMMR0DECL(int) CPUMR0LoadHostDebugState(PVM pVM, PVMCPU pVCpu)
530	{
531	Assert(pVCpu->cpum.s.fUseFlags & (CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HYPER));
532
533	/*
534	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
535	* DR7 contains 0x400 right now.
536	*/
537	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
538	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
539	cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
540	#else
541	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
542	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
543	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
544	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
545	#endif
546	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
547	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
548
549	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HYPER);
550	return VINF_SUCCESS;
551	}
552
553
554	/**
555	* Lazily sync in the hypervisor debug state
556	*
557	* @returns VBox status code.
558	* @param pVM VM handle.
559	* @param pVCpu VMCPU handle.
560	* @param pCtx CPU context
561	* @param fDR6 Include DR6 or not
562	*/
563	VMMR0DECL(int) CPUMR0LoadHyperDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
564	{
565	/* Save the host state. */
566	CPUMR0SaveHostDebugState(pVM, pVCpu);
567	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
568
569	/* Activate the guest state DR0-3; DR7 is left to the caller. */
570	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
571	if (CPUMIsGuestInLongModeEx(pCtx))
572	{
573	AssertFailed();
574	return VERR_NOT_IMPLEMENTED;
575	}
576	else
577	#endif
578	{
579	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
580	AssertFailed();
581	return VERR_NOT_IMPLEMENTED;
582	#else
583	ASMSetDR0(CPUMGetHyperDR0(pVCpu));
584	ASMSetDR1(CPUMGetHyperDR1(pVCpu));
585	ASMSetDR2(CPUMGetHyperDR2(pVCpu));
586	ASMSetDR3(CPUMGetHyperDR3(pVCpu));
587	#endif
588	if (fDR6)
589	ASMSetDR6(CPUMGetHyperDR6(pVCpu));
590	}
591
592	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HYPER;
593	return VINF_SUCCESS;
594	}
595
596

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 25659

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