CPUMR0.cpp@ 106628

Last change on this file since 106628 was 106628, checked in by vboxsync, 4 months ago
VMM/CPUMR0: bugref:10794 Fix logging of IA32_ARCH_CAPABILITIES MSR in r165448 (which assumed fArchVal wasn't changed to guest value).
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 30.8 KB

Line
1	/* $Id: CPUMR0.cpp 106628 2024-10-23 17:28:44Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#define CPUM_WITH_NONCONST_HOST_FEATURES
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/hm.h>
36	#include "CPUMInternal.h"
37	#include <VBox/vmm/vmcc.h>
38	#include <VBox/vmm/gvm.h>
39	#include <VBox/err.h>
40	#include <VBox/log.h>
41	#include <VBox/vmm/hm.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm-amd64-x86.h>
44	#include <iprt/mem.h>
45	#include <iprt/x86.h>
46
47
48	/*********************************************************************************************************************************
49	* Global Variables *
50	*********************************************************************************************************************************/
51	/** Host CPU features. */
52	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
53	/** Static storage for host MSRs. */
54	static CPUMMSRS g_CpumHostMsrs;
55
56	/**
57	* CPUID bits to unify among all cores.
58	*/
59	static struct
60	{
61	uint32_t uLeaf; /*< Leaf to check. /
62	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
63	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
64	}
65	const g_aCpuidUnifyBits[] =
66	{
67	{
68	0x00000001,
69	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
70	X86_CPUID_FEATURE_EDX_CX8
71	}
72	};
73
74
75
76	/*********************************************************************************************************************************
77	* Internal Functions *
78	*********************************************************************************************************************************/
79	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu);
80
81
82	/**
83	* Check the CPUID features of this particular CPU and disable relevant features
84	* for the guest which do not exist on this CPU.
85	*
86	* We have seen systems where the X86_CPUID_FEATURE_ECX_MONITOR feature flag is
87	* only set on some host CPUs, see @bugref{5436}.
88	*
89	* @note This function might be called simultaneously on more than one CPU!
90	*
91	* @param idCpu The identifier for the CPU the function is called on.
92	* @param pvUser1 Leaf array.
93	* @param pvUser2 Number of leaves.
94	*/
95	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
96	{
97	PCPUMCPUIDLEAF const paLeaves = (PCPUMCPUIDLEAF)pvUser1;
98	uint32_t const cLeaves = (uint32_t)(uintptr_t)pvUser2;
99	RT_NOREF(idCpu);
100
101	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
102	{
103	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, g_aCpuidUnifyBits[i].uLeaf, 0);
104	if (pLeaf)
105	{
106	uint32_t uEax, uEbx, uEcx, uEdx;
107	ASMCpuIdExSlow(g_aCpuidUnifyBits[i].uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
108
109	ASMAtomicAndU32(&pLeaf->uEcx, uEcx \| ~g_aCpuidUnifyBits[i].uEcx);
110	ASMAtomicAndU32(&pLeaf->uEdx, uEdx \| ~g_aCpuidUnifyBits[i].uEdx);
111	}
112	}
113	}
114
115
116	/**
117	* Does the Ring-0 CPU initialization once during module load.
118	* XXX Host-CPU hot-plugging?
119	*/
120	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
121	{
122	/*
123	* Query the hardware virtualization capabilities of the host CPU first.
124	*/
125	uint32_t fHwCaps = 0;
126	int rc = SUPR0GetVTSupport(&fHwCaps);
127	AssertLogRelMsg(RT_SUCCESS(rc) \|\| rc == VERR_UNSUPPORTED_CPU \|\| rc == VERR_SVM_NO_SVM \|\| rc == VERR_VMX_NO_VMX,
128	("SUPR0GetHwvirtMsrs -> %Rrc\n", rc));
129	if (RT_SUCCESS(rc))
130	{
131	SUPHWVIRTMSRS HwvirtMsrs;
132	rc = SUPR0GetHwvirtMsrs(&HwvirtMsrs, fHwCaps, false /fIgnored/);
133	AssertLogRelRC(rc);
134	if (RT_SUCCESS(rc))
135	{
136	if (fHwCaps & SUPVTCAPS_VT_X)
137	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.vmx);
138	else
139	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.svm);
140	}
141	}
142
143	/*
144	* Collect CPUID leaves.
145	*/
146	PCPUMCPUIDLEAF paLeaves;
147	uint32_t cLeaves;
148	rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
149	AssertLogRelRCReturn(rc, rc);
150
151	/*
152	* Unify/cross check some CPUID feature bits on all available CPU cores
153	* and threads. We've seen CPUs where the monitor support differed.
154	*/
155	RTMpOnAll(cpumR0CheckCpuid, paLeaves, (void *)(uintptr_t)cLeaves);
156
157	/*
158	* Populate the host CPU feature global variable.
159	*/
160	rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &g_CpumHostMsrs, &g_CpumHostFeatures.s);
161	RTMemFree(paLeaves);
162	AssertLogRelRCReturn(rc, rc);
163
164	/*
165	* Get MSR_IA32_ARCH_CAPABILITIES and expand it into the host feature structure.
166	*/
167	if (ASMHasCpuId())
168	{
169	/** @todo Should add this MSR to CPUMMSRS and expose it via SUPDrv... */
170	g_CpumHostFeatures.s.fArchRdclNo = 0;
171	g_CpumHostFeatures.s.fArchIbrsAll = 0;
172	g_CpumHostFeatures.s.fArchRsbOverride = 0;
173	g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = 0;
174	g_CpumHostFeatures.s.fArchMdsNo = 0;
175	uint32_t const cStdRange = ASMCpuId_EAX(0);
176	if ( RTX86IsValidStdRange(cStdRange)
177	&& cStdRange >= 7)
178	{
179	uint32_t const fStdFeaturesEdx = ASMCpuId_EDX(1);
180	uint32_t fStdExtFeaturesEdx;
181	ASMCpuIdExSlow(7, 0, 0, 0, NULL, NULL, NULL, &fStdExtFeaturesEdx);
182	if ( (fStdExtFeaturesEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
183	&& (fStdFeaturesEdx & X86_CPUID_FEATURE_EDX_MSR))
184	{
185	uint64_t fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
186	g_CpumHostFeatures.s.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
187	g_CpumHostFeatures.s.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
188	g_CpumHostFeatures.s.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
189	g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
190	g_CpumHostFeatures.s.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
191	}
192	else
193	g_CpumHostFeatures.s.fArchCap = 0;
194	}
195	}
196
197	return VINF_SUCCESS;
198	}
199
200
201	/**
202	* Terminate the module.
203	*/
204	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
205	{
206	return VINF_SUCCESS;
207	}
208
209
210	/**
211	* Initializes the CPUM data in the VM structure.
212	*
213	* @param pGVM The global VM structure.
214	*/
215	VMMR0_INT_DECL(void) CPUMR0InitPerVMData(PGVM pGVM)
216	{
217	/* Copy the ring-0 host feature set to the shared part so ring-3 can pick it up. */
218	pGVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
219	}
220
221
222	/**
223	* Check the CPUID features of this particular CPU and disable relevant features
224	* for the guest which do not exist on this CPU. We have seen systems where the
225	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
226	* @bugref{5436}.
227	*
228	* @note This function might be called simultaneously on more than one CPU!
229	*
230	* @param idCpu The identifier for the CPU the function is called on.
231	* @param pvUser1 Pointer to the VM structure.
232	* @param pvUser2 Ignored.
233	*/
234	static DECLCALLBACK(void) cpumR0CheckCpuidLegacy(RTCPUID idCpu, void pvUser1, void pvUser2)
235	{
236	PVMCC pVM = (PVMCC)pvUser1;
237
238	NOREF(idCpu); NOREF(pvUser2);
239	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
240	{
241	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
242	necessarily in the VM process context. So, we using the
243	legacy arrays as temporary storage. */
244
245	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
246	PCPUMCPUID pLegacyLeaf;
247	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
248	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
249	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
250	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
251	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
252	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
253	else
254	continue;
255
256	uint32_t eax, ebx, ecx, edx;
257	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
258
259	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
260	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
261	}
262	}
263
264
265	/**
266	* Does Ring-0 CPUM initialization.
267	*
268	* This is mainly to check that the Host CPU mode is compatible
269	* with VBox.
270	*
271	* @returns VBox status code.
272	* @param pVM The cross context VM structure.
273	*/
274	VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM)
275	{
276	LogFlow(("CPUMR0Init: %p\n", pVM));
277	AssertCompile(sizeof(pVM->aCpus[0].cpum.s.Host.abXState) >= sizeof(pVM->aCpus[0].cpum.s.Guest.abXState));
278
279	/*
280	* Check CR0 & CR4 flags.
281	*/
282	uint32_t u32CR0 = ASMGetCR0();
283	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
284	{
285	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
286	return VERR_UNSUPPORTED_CPU_MODE;
287	}
288
289	/*
290	* Check for sysenter and syscall usage.
291	*/
292	if (ASMHasCpuId())
293	{
294	/*
295	* SYSENTER/SYSEXIT
296	*
297	* Intel docs claim you should test both the flag and family, model &
298	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
299	* but don't support it. AMD CPUs may support this feature in legacy
300	* mode, they've banned it from long mode. Since we switch to 32-bit
301	* mode when entering raw-mode context the feature would become
302	* accessible again on AMD CPUs, so we have to check regardless of
303	* host bitness.
304	*/
305	uint32_t u32CpuVersion;
306	uint32_t u32Dummy;
307	uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
308	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
309	uint32_t const u32Family = u32CpuVersion >> 8;
310	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
311	uint32_t const u32Stepping = u32CpuVersion & 0xF;
312	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
313	&& ( u32Family != 6 /* (> pentium pro) */
314	\|\| u32Model >= 3
315	\|\| u32Stepping >= 3
316	\|\| !ASMIsIntelCpu())
317	)
318	{
319	/*
320	* Read the MSR and see if it's in use or not.
321	*/
322	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
323	if (u32)
324	{
325	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
326	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
327	}
328	}
329
330	/*
331	* SYSCALL/SYSRET
332	*
333	* This feature is indicated by the SEP bit returned in EDX by CPUID
334	* function 0x80000001. Intel CPUs only supports this feature in
335	* long mode. Since we're not running 64-bit guests in raw-mode there
336	* are no issues with 32-bit intel hosts.
337	*/
338	uint32_t cExt = 0;
339	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
340	if (RTX86IsValidExtRange(cExt))
341	{
342	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
343	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
344	{
345	#ifdef RT_ARCH_X86
346	if (!ASMIsIntelCpu())
347	#endif
348	{
349	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
350	if (fEfer & MSR_K6_EFER_SCE)
351	{
352	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
353	Log(("CPUMR0Init: host uses syscall\n"));
354	}
355	}
356	}
357	}
358
359	/*
360	* Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host and guest feature
361	* structure and as well as the guest MSR.
362	* Note! we assume this happens after the CPUMR3Init is done, so CPUID bits are settled.
363	*/
364	pVM->cpum.s.HostFeatures.fArchRdclNo = 0;
365	pVM->cpum.s.HostFeatures.fArchIbrsAll = 0;
366	pVM->cpum.s.HostFeatures.fArchRsbOverride = 0;
367	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
368	pVM->cpum.s.HostFeatures.fArchMdsNo = 0;
369	uint32_t const cStdRange = ASMCpuId_EAX(0);
370	if ( RTX86IsValidStdRange(cStdRange)
371	&& cStdRange >= 7)
372	{
373	uint32_t fEdxFeatures = ASMCpuId_EDX(7);
374	if ( (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
375	&& (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
376	{
377	/* Host: */
378	uint64_t const fHostArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
379	uint64_t fArchVal = fHostArchVal;
380	pVM->cpum.s.HostFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
381	pVM->cpum.s.HostFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
382	pVM->cpum.s.HostFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
383	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
384	pVM->cpum.s.HostFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
385
386	/* guest: */
387	if (!pVM->cpum.s.GuestFeatures.fArchCap)
388	fArchVal = 0;
389	else if (!pVM->cpum.s.GuestFeatures.fIbrs)
390	fArchVal &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL;
391	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps = fArchVal);
392	pVM->cpum.s.GuestFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
393	pVM->cpum.s.GuestFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
394	pVM->cpum.s.GuestFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
395	pVM->cpum.s.GuestFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
396	pVM->cpum.s.GuestFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
397	LogRel(("CPUM: IA32_ARCH_CAPABILITIES (Host=%#RX64 Guest=%#RX64)\n", fHostArchVal, fArchVal));
398	}
399	else
400	{
401	pVM->cpum.s.HostFeatures.fArchCap = 0;
402	LogRel(("CPUM: IA32_ARCH_CAPABILITIES unsupported\n"));
403	}
404	}
405
406	/*
407	* Unify/cross check some CPUID feature bits on all available CPU cores
408	* and threads. We've seen CPUs where the monitor support differed.
409	*
410	* Because the hyper heap isn't always mapped into ring-0, we cannot
411	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
412	* as temp ring-0 accessible memory instead, ASSUMING that they're all
413	* up to date when we get here.
414	*/
415	RTMpOnAll(cpumR0CheckCpuidLegacy, pVM, NULL);
416
417	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
418	{
419	bool fIgnored;
420	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
421	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
422	if (pLeaf)
423	{
424	PCPUMCPUID pLegacyLeaf;
425	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
426	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
427	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
428	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
429	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
430	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
431	else
432	continue;
433
434	pLeaf->uEcx = pLegacyLeaf->uEcx;
435	pLeaf->uEdx = pLegacyLeaf->uEdx;
436	}
437	}
438
439	}
440
441
442	/*
443	* Check if debug registers are armed.
444	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
445	*/
446	uint32_t u32DR7 = ASMGetDR7();
447	if (u32DR7 & X86_DR7_ENABLED_MASK)
448	{
449	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST);
450	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
451	}
452
453	return VINF_SUCCESS;
454	}
455
456
457	/**
458	* Trap handler for device-not-available fault (\#NM).
459	* Device not available, FP or (F)WAIT instruction.
460	*
461	* @returns VBox status code.
462	* @retval VINF_SUCCESS if the guest FPU state is loaded.
463	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
464	* @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
465	*
466	* @param pVM The cross context VM structure.
467	* @param pVCpu The cross context virtual CPU structure.
468	*/
469	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu)
470	{
471	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
472	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
473
474	/* If the FPU state has already been loaded, then it's a guest trap. */
475	if (CPUMIsGuestFPUStateActive(pVCpu))
476	{
477	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
478	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
479	return VINF_EM_RAW_GUEST_TRAP;
480	}
481
482	/*
483	* There are two basic actions:
484	* 1. Save host fpu and restore guest fpu.
485	* 2. Generate guest trap.
486	*
487	* When entering the hypervisor we'll always enable MP (for proper wait
488	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
489	* is taken from the guest OS in order to get proper SSE handling.
490	*
491	*
492	* Actions taken depending on the guest CR0 flags:
493	*
494	* 3 2 1
495	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
496	* ------------------------------------------------------------------------
497	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
498	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
499	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
500	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
501	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
502	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
503	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
504	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
505	*/
506
507	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
508	{
509	case X86_CR0_MP \| X86_CR0_TS:
510	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
511	return VINF_EM_RAW_GUEST_TRAP;
512	default:
513	break;
514	}
515
516	return CPUMR0LoadGuestFPU(pVM, pVCpu);
517	}
518
519
520	/**
521	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
522	* state into the CPU.
523	*
524	* @returns VINF_SUCCESS on success, host CR0 unmodified.
525	* @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
526	* modified and VT-x needs to update the value in the VMCS.
527	*
528	* @param pVM The cross context VM structure.
529	* @param pVCpu The cross context virtual CPU structure.
530	*/
531	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu)
532	{
533	int rc;
534	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
535	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
536
537	/* Notify the support driver prior to loading the guest-FPU register state. */
538	SUPR0FpuBegin(VMMR0ThreadCtxHookIsEnabled(pVCpu));
539	/** @todo use return value? Currently skipping that to be on the safe side
540	* wrt. extended state (linux). */
541
542	if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
543	{
544	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
545	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
546	}
547	else
548	{
549	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
550	/** @todo r=ramshankar: Can't we used a cached value here
551	* instead of reading the MSR? host EFER doesn't usually
552	* change. */
553	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
554	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
555	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
556	else
557	{
558	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
559	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
560	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
561	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
562	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
563	ASMSetFlags(uSavedFlags);
564	}
565	}
566	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
567	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
568	Assert(pVCpu->cpum.s.Guest.fUsedFpuGuest);
569	return rc;
570	}
571
572
573	/**
574	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
575	* needed.
576	*
577	* @returns true if we saved the guest state.
578	* @param pVCpu The cross context virtual CPU structure.
579	*/
580	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu)
581	{
582	bool fSavedGuest;
583	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
584	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
585	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
586	{
587	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
588	Assert(fSavedGuest == pVCpu->cpum.s.Guest.fUsedFpuGuest);
589	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
590	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
591	else
592	{
593	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
594	save/restore the XMM state with fxsave/fxrstor. */
595	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
596	if (uHostEfer & MSR_K6_EFER_FFXSR)
597	{
598	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
599	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
600	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
601	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
602	ASMSetFlags(uSavedFlags);
603	}
604	else
605	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
606	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
607	}
608
609	/* Notify the support driver after loading the host-FPU register state. */
610	SUPR0FpuEnd(VMMR0ThreadCtxHookIsEnabled(pVCpu));
611	}
612	else
613	fSavedGuest = false;
614	Assert(!( pVCpu->cpum.s.fUseFlags
615	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_MANUAL_XMM_RESTORE)));
616	Assert(!pVCpu->cpum.s.Guest.fUsedFpuGuest);
617	return fSavedGuest;
618	}
619
620
621	/**
622	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
623	* DR7 with safe values.
624	*
625	* @returns VBox status code.
626	* @param pVCpu The cross context virtual CPU structure.
627	*/
628	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu)
629	{
630	/*
631	* Save the host state.
632	*/
633	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
634	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
635	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
636	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
637	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
638	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
639	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
640
641	/* Preemption paranoia. */
642	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
643
644	/*
645	* Make sure DR7 is harmless or else we could trigger breakpoints when
646	* load guest or hypervisor DRx values later.
647	*/
648	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
649	ASMSetDR7(X86_DR7_INIT_VAL);
650
651	return VINF_SUCCESS;
652	}
653
654
655	/**
656	* Saves the guest DRx state residing in host registers and restore the host
657	* register values.
658	*
659	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
660	* since it's assumed that we're shadowing the guest DRx register values
661	* accurately when using the combined hypervisor debug register values
662	* (CPUMR0LoadHyperDebugState).
663	*
664	* @returns true if either guest or hypervisor debug registers were loaded.
665	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
666	* @param fDr6 Whether to include DR6 or not.
667	* @thread EMT(pVCpu)
668	*/
669	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6)
670	{
671	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
672	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
673
674	/*
675	* Do we need to save the guest DRx registered loaded into host registers?
676	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
677	*/
678	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
679	{
680	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
681	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
682	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
683	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
684	if (fDr6)
685	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6() \| X86_DR6_RA1_MASK; /* ASSUMES no guest supprot for TSX-NI / RTM. */
686	}
687	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~(CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
688
689	/*
690	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
691	*/
692	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
693	{
694	/* A bit of paranoia first... */
695	uint64_t uCurDR7 = ASMGetDR7();
696	if (uCurDR7 != X86_DR7_INIT_VAL)
697	ASMSetDR7(X86_DR7_INIT_VAL);
698
699	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
700	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
701	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
702	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
703	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
704	* expensive DRx reads are over DRx writes. */
705	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
706	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
707
708	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
709	}
710
711	return fDrXLoaded;
712	}
713
714
715	/**
716	* Saves the guest DRx state if it resides host registers.
717	*
718	* This does NOT clear any use flags, so the host registers remains loaded with
719	* the guest DRx state upon return. The purpose is only to make sure the values
720	* in the CPU context structure is up to date.
721	*
722	* @returns true if the host registers contains guest values, false if not.
723	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
724	* @param fDr6 Whether to include DR6 or not.
725	* @thread EMT(pVCpu)
726	*/
727	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6)
728	{
729	/*
730	* Do we need to save the guest DRx registered loaded into host registers?
731	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
732	*/
733	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
734	{
735	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
736	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
737	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
738	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
739	if (fDr6)
740	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
741	return true;
742	}
743	return false;
744	}
745
746
747	/**
748	* Lazily sync in the debug state.
749	*
750	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
751	* @param fDr6 Whether to include DR6 or not.
752	* @thread EMT(pVCpu)
753	*/
754	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6)
755	{
756	/*
757	* Save the host state and disarm all host BPs.
758	*/
759	cpumR0SaveHostDebugState(pVCpu);
760	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
761
762	/*
763	* Activate the guest state DR0-3.
764	* DR7 and DR6 (if fDr6 is true) are left to the caller.
765	*/
766	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
767	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
768	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
769	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
770	if (fDr6)
771	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
772
773	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
774	}
775
776
777	/**
778	* Lazily sync in the hypervisor debug state
779	*
780	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
781	* @param fDr6 Whether to include DR6 or not.
782	* @thread EMT(pVCpu)
783	*/
784	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6)
785	{
786	/*
787	* Save the host state and disarm all host BPs.
788	*/
789	cpumR0SaveHostDebugState(pVCpu);
790	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
791
792	/*
793	* Make sure the hypervisor values are up to date.
794	*/
795	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
796
797	/*
798	* Activate the guest state DR0-3.
799	* DR7 and DR6 (if fDr6 is true) are left to the caller.
800	*/
801	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
802	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
803	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
804	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
805	if (fDr6)
806	ASMSetDR6(X86_DR6_INIT_VAL);
807
808	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
809	}
810

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 106628

Download in other formats: