CPUMR0.cpp@ 107703

Last change on this file since 107703 was 107703, checked in by vboxsync, 3 weeks ago
VMM/CPUM: Try consolidate the MSR_IA32_ARCH_CAPABILITIES handling in CPUM and do better sanitizing of what's exposed to the guest. jiraref:VBP-947
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1	/* $Id: CPUMR0.cpp 107703 2025-01-11 22:55:53Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0, only targeting x86.
4	*/
5
6	/*
7	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#define VBOX_VMM_TARGET_X86
34	#define CPUM_WITH_NONCONST_HOST_FEATURES
35	#include <VBox/vmm/cpum.h>
36	#include <VBox/vmm/hm.h>
37	#include "CPUMInternal.h"
38	#include <VBox/vmm/vmcc.h>
39	#include <VBox/vmm/gvm.h>
40	#include <VBox/err.h>
41	#include <VBox/log.h>
42	#include <VBox/vmm/hm.h>
43	#include <iprt/assert.h>
44	#include <iprt/asm-amd64-x86.h>
45	#include <iprt/mem.h>
46	#include <iprt/x86.h>
47
48
49	/*********************************************************************************************************************************
50	* Global Variables *
51	*********************************************************************************************************************************/
52	/** Host CPU features. */
53	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
54	/** Static storage for host MSRs. */
55	static CPUMMSRS g_CpumHostMsrs;
56
57	/**
58	* CPUID bits to unify among all cores.
59	*/
60	static struct
61	{
62	uint32_t uLeaf; /*< Leaf to check. /
63	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
64	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
65	}
66	const g_aCpuidUnifyBits[] =
67	{
68	{
69	0x00000001,
70	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
71	X86_CPUID_FEATURE_EDX_CX8
72	}
73	};
74
75
76
77	/*********************************************************************************************************************************
78	* Internal Functions *
79	*********************************************************************************************************************************/
80	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu);
81
82
83	/**
84	* Check the CPUID features of this particular CPU and disable relevant features
85	* for the guest which do not exist on this CPU.
86	*
87	* We have seen systems where the X86_CPUID_FEATURE_ECX_MONITOR feature flag is
88	* only set on some host CPUs, see @bugref{5436}.
89	*
90	* @note This function might be called simultaneously on more than one CPU!
91	*
92	* @param idCpu The identifier for the CPU the function is called on.
93	* @param pvUser1 Leaf array.
94	* @param pvUser2 Number of leaves.
95	*/
96	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
97	{
98	PCPUMCPUIDLEAF const paLeaves = (PCPUMCPUIDLEAF)pvUser1;
99	uint32_t const cLeaves = (uint32_t)(uintptr_t)pvUser2;
100	RT_NOREF(idCpu);
101
102	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
103	{
104	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, g_aCpuidUnifyBits[i].uLeaf, 0);
105	if (pLeaf)
106	{
107	uint32_t uEax, uEbx, uEcx, uEdx;
108	ASMCpuIdExSlow(g_aCpuidUnifyBits[i].uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
109
110	ASMAtomicAndU32(&pLeaf->uEcx, uEcx \| ~g_aCpuidUnifyBits[i].uEcx);
111	ASMAtomicAndU32(&pLeaf->uEdx, uEdx \| ~g_aCpuidUnifyBits[i].uEdx);
112	}
113	}
114	}
115
116
117	/**
118	* Does the Ring-0 CPU initialization once during module load.
119	* XXX Host-CPU hot-plugging?
120	*/
121	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
122	{
123	/*
124	* Query the hardware virtualization capabilities of the host CPU first.
125	*/
126	uint32_t fHwCaps = 0;
127	int rc = SUPR0GetVTSupport(&fHwCaps);
128	AssertLogRelMsg(RT_SUCCESS(rc) \|\| rc == VERR_UNSUPPORTED_CPU \|\| rc == VERR_SVM_NO_SVM \|\| rc == VERR_VMX_NO_VMX,
129	("SUPR0GetHwvirtMsrs -> %Rrc\n", rc));
130	if (RT_SUCCESS(rc))
131	{
132	SUPHWVIRTMSRS HwvirtMsrs;
133	rc = SUPR0GetHwvirtMsrs(&HwvirtMsrs, fHwCaps, false /fIgnored/);
134	AssertLogRelRC(rc);
135	if (RT_SUCCESS(rc))
136	{
137	if (fHwCaps & SUPVTCAPS_VT_X)
138	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.vmx);
139	else
140	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.svm);
141	}
142	}
143
144	/*
145	* Collect CPUID leaves.
146	*/
147	PCPUMCPUIDLEAF paLeaves;
148	uint32_t cLeaves;
149	rc = CPUMCpuIdCollectLeavesFromX86Host(&paLeaves, &cLeaves);
150	AssertLogRelRCReturn(rc, rc);
151
152	/*
153	* Unify/cross check some CPUID feature bits on all available CPU cores
154	* and threads. We've seen CPUs where the monitor support differed.
155	*/
156	RTMpOnAll(cpumR0CheckCpuid, paLeaves, (void *)(uintptr_t)cLeaves);
157
158	/*
159	* Populate the host CPU feature global variable.
160	*/
161	rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &g_CpumHostMsrs, &g_CpumHostFeatures.s);
162	RTMemFree(paLeaves);
163	AssertLogRelRCReturn(rc, rc);
164
165	/*
166	* Get MSR_IA32_ARCH_CAPABILITIES and expand it into the host feature structure.
167	*/
168	if (ASMHasCpuId())
169	{
170	/** @todo Should add this MSR to CPUMMSRS and expose it via SUPDrv... */
171	g_CpumHostFeatures.s.fArchRdclNo = 0;
172	g_CpumHostFeatures.s.fArchIbrsAll = 0;
173	g_CpumHostFeatures.s.fArchRsbOverride = 0;
174	g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = 0;
175	g_CpumHostFeatures.s.fArchMdsNo = 0;
176	uint32_t const cStdRange = ASMCpuId_EAX(0);
177	if ( RTX86IsValidStdRange(cStdRange)
178	&& cStdRange >= 7)
179	{
180	uint32_t const fStdFeaturesEdx = ASMCpuId_EDX(1);
181	uint32_t fStdExtFeaturesEdx;
182	ASMCpuIdExSlow(7, 0, 0, 0, NULL, NULL, NULL, &fStdExtFeaturesEdx);
183	if ( (fStdExtFeaturesEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
184	&& (fStdFeaturesEdx & X86_CPUID_FEATURE_EDX_MSR))
185	{
186	uint64_t fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
187	g_CpumHostFeatures.s.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
188	g_CpumHostFeatures.s.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
189	g_CpumHostFeatures.s.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
190	g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
191	g_CpumHostFeatures.s.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
192	}
193	else
194	g_CpumHostFeatures.s.fArchCap = 0;
195	}
196	}
197
198	return VINF_SUCCESS;
199	}
200
201
202	/**
203	* Terminate the module.
204	*/
205	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
206	{
207	return VINF_SUCCESS;
208	}
209
210
211	/**
212	* Initializes the CPUM data in the VM structure.
213	*
214	* @param pGVM The global VM structure.
215	*/
216	VMMR0_INT_DECL(void) CPUMR0InitPerVMData(PGVM pGVM)
217	{
218	/* Copy the ring-0 host feature set to the shared part so ring-3 can pick it up. */
219	pGVM->cpum.s.HostFeatures.s = g_CpumHostFeatures.s;
220	}
221
222
223	/**
224	* Check the CPUID features of this particular CPU and disable relevant features
225	* for the guest which do not exist on this CPU. We have seen systems where the
226	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
227	* @bugref{5436}.
228	*
229	* @note This function might be called simultaneously on more than one CPU!
230	*
231	* @param idCpu The identifier for the CPU the function is called on.
232	* @param pvUser1 Pointer to the VM structure.
233	* @param pvUser2 Ignored.
234	*/
235	static DECLCALLBACK(void) cpumR0CheckCpuidLegacy(RTCPUID idCpu, void pvUser1, void pvUser2)
236	{
237	PVMCC pVM = (PVMCC)pvUser1;
238
239	NOREF(idCpu); NOREF(pvUser2);
240	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
241	{
242	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
243	necessarily in the VM process context. So, we using the
244	legacy arrays as temporary storage. */
245
246	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
247	PCPUMCPUID pLegacyLeaf;
248	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
249	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
250	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
251	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
252	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
253	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
254	else
255	continue;
256
257	uint32_t eax, ebx, ecx, edx;
258	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
259
260	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
261	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
262	}
263	}
264
265
266	/**
267	* Does Ring-0 CPUM initialization.
268	*
269	* This is mainly to check that the Host CPU mode is compatible
270	* with VBox.
271	*
272	* @returns VBox status code.
273	* @param pVM The cross context VM structure.
274	*/
275	VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM)
276	{
277	LogFlow(("CPUMR0Init: %p\n", pVM));
278	AssertCompile(sizeof(pVM->aCpus[0].cpum.s.Host.abXState) >= sizeof(pVM->aCpus[0].cpum.s.Guest.abXState));
279
280	/*
281	* Check CR0 & CR4 flags.
282	*/
283	uint32_t u32CR0 = ASMGetCR0();
284	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
285	{
286	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
287	return VERR_UNSUPPORTED_CPU_MODE;
288	}
289
290	/*
291	* Check for sysenter and syscall usage.
292	*/
293	if (ASMHasCpuId())
294	{
295	/*
296	* SYSENTER/SYSEXIT
297	*
298	* Intel docs claim you should test both the flag and family, model &
299	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
300	* but don't support it. AMD CPUs may support this feature in legacy
301	* mode, they've banned it from long mode. Since we switch to 32-bit
302	* mode when entering raw-mode context the feature would become
303	* accessible again on AMD CPUs, so we have to check regardless of
304	* host bitness.
305	*/
306	uint32_t u32CpuVersion;
307	uint32_t u32Dummy;
308	uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
309	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
310	uint32_t const u32Family = u32CpuVersion >> 8;
311	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
312	uint32_t const u32Stepping = u32CpuVersion & 0xF;
313	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
314	&& ( u32Family != 6 /* (> pentium pro) */
315	\|\| u32Model >= 3
316	\|\| u32Stepping >= 3
317	\|\| !ASMIsIntelCpu())
318	)
319	{
320	/*
321	* Read the MSR and see if it's in use or not.
322	*/
323	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
324	if (u32)
325	{
326	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
327	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
328	}
329	}
330
331	/*
332	* SYSCALL/SYSRET
333	*
334	* This feature is indicated by the SEP bit returned in EDX by CPUID
335	* function 0x80000001. Intel CPUs only supports this feature in
336	* long mode. Since we're not running 64-bit guests in raw-mode there
337	* are no issues with 32-bit intel hosts.
338	*/
339	uint32_t cExt = 0;
340	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
341	if (RTX86IsValidExtRange(cExt))
342	{
343	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
344	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
345	{
346	#ifdef RT_ARCH_X86
347	if (!ASMIsIntelCpu())
348	#endif
349	{
350	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
351	if (fEfer & MSR_K6_EFER_SCE)
352	{
353	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
354	Log(("CPUMR0Init: host uses syscall\n"));
355	}
356	}
357	}
358	}
359
360	/*
361	* Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host and guest feature
362	* structure and as well as the guest MSR.
363	* Note! We assume this happens after the CPUMR3Init is done, so CPUID bits are settled.
364	*/
365	uint64_t fHostArchVal = 0;
366	bool fHasArchCap = false;
367	uint32_t const cStdRange = ASMCpuId_EAX(0);
368	if ( RTX86IsValidStdRange(cStdRange)
369	&& cStdRange >= 7)
370	{
371	uint32_t fEdxFeatures;
372	ASMCpuId_Idx_ECX(7, 0, &u32Dummy, &u32Dummy, &u32Dummy, &fEdxFeatures);
373	if ( (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
374	&& (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
375	{
376	fHostArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
377	fHasArchCap = true;
378	}
379	}
380	CPUMCpuIdApplyX86HostArchCapabilities(pVM, fHasArchCap, fHostArchVal);
381
382	/*
383	* Unify/cross check some CPUID feature bits on all available CPU cores
384	* and threads. We've seen CPUs where the monitor support differed.
385	*
386	* Because the hyper heap isn't always mapped into ring-0, we cannot
387	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
388	* as temp ring-0 accessible memory instead, ASSUMING that they're all
389	* up to date when we get here.
390	*/
391	RTMpOnAll(cpumR0CheckCpuidLegacy, pVM, NULL);
392
393	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
394	{
395	bool fIgnored;
396	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
397	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
398	if (pLeaf)
399	{
400	PCPUMCPUID pLegacyLeaf;
401	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
402	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
403	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
404	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
405	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
406	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
407	else
408	continue;
409
410	pLeaf->uEcx = pLegacyLeaf->uEcx;
411	pLeaf->uEdx = pLegacyLeaf->uEdx;
412	}
413	}
414
415	}
416
417
418	/*
419	* Check if debug registers are armed.
420	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
421	*/
422	uint32_t u32DR7 = ASMGetDR7();
423	if (u32DR7 & X86_DR7_ENABLED_MASK)
424	{
425	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST);
426	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
427	}
428
429	return VINF_SUCCESS;
430	}
431
432
433	/**
434	* Trap handler for device-not-available fault (\#NM).
435	* Device not available, FP or (F)WAIT instruction.
436	*
437	* @returns VBox status code.
438	* @retval VINF_SUCCESS if the guest FPU state is loaded.
439	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
440	* @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
441	*
442	* @param pVM The cross context VM structure.
443	* @param pVCpu The cross context virtual CPU structure.
444	*/
445	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu)
446	{
447	Assert(pVM->cpum.s.HostFeatures.s.fFxSaveRstor);
448	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
449
450	/* If the FPU state has already been loaded, then it's a guest trap. */
451	if (CPUMIsGuestFPUStateActive(pVCpu))
452	{
453	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
454	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
455	return VINF_EM_RAW_GUEST_TRAP;
456	}
457
458	/*
459	* There are two basic actions:
460	* 1. Save host fpu and restore guest fpu.
461	* 2. Generate guest trap.
462	*
463	* When entering the hypervisor we'll always enable MP (for proper wait
464	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
465	* is taken from the guest OS in order to get proper SSE handling.
466	*
467	*
468	* Actions taken depending on the guest CR0 flags:
469	*
470	* 3 2 1
471	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
472	* ------------------------------------------------------------------------
473	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
474	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
475	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
476	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
477	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
478	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
479	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
480	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
481	*/
482
483	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
484	{
485	case X86_CR0_MP \| X86_CR0_TS:
486	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
487	return VINF_EM_RAW_GUEST_TRAP;
488	default:
489	break;
490	}
491
492	return CPUMR0LoadGuestFPU(pVM, pVCpu);
493	}
494
495
496	/**
497	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
498	* state into the CPU.
499	*
500	* @returns VINF_SUCCESS on success, host CR0 unmodified.
501	* @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
502	* modified and VT-x needs to update the value in the VMCS.
503	*
504	* @param pVM The cross context VM structure.
505	* @param pVCpu The cross context virtual CPU structure.
506	*/
507	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu)
508	{
509	int rc;
510	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
511	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
512
513	/* Notify the support driver prior to loading the guest-FPU register state. */
514	SUPR0FpuBegin(VMMR0ThreadCtxHookIsEnabled(pVCpu));
515	/** @todo use return value? Currently skipping that to be on the safe side
516	* wrt. extended state (linux). */
517
518	if (!pVM->cpum.s.HostFeatures.s.fLeakyFxSR)
519	{
520	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
521	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
522	}
523	else
524	{
525	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
526	/** @todo r=ramshankar: Can't we used a cached value here
527	* instead of reading the MSR? host EFER doesn't usually
528	* change. */
529	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
530	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
531	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
532	else
533	{
534	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
535	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
536	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
537	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
538	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
539	ASMSetFlags(uSavedFlags);
540	}
541	}
542	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
543	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
544	Assert(pVCpu->cpum.s.Guest.fUsedFpuGuest);
545	return rc;
546	}
547
548
549	/**
550	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
551	* needed.
552	*
553	* @returns true if we saved the guest state.
554	* @param pVCpu The cross context virtual CPU structure.
555	*/
556	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu)
557	{
558	bool fSavedGuest;
559	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.s.fFxSaveRstor);
560	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
561	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
562	{
563	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
564	Assert(fSavedGuest == pVCpu->cpum.s.Guest.fUsedFpuGuest);
565	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
566	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
567	else
568	{
569	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
570	save/restore the XMM state with fxsave/fxrstor. */
571	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
572	if (uHostEfer & MSR_K6_EFER_FFXSR)
573	{
574	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
575	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
576	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
577	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
578	ASMSetFlags(uSavedFlags);
579	}
580	else
581	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
582	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
583	}
584
585	/* Notify the support driver after loading the host-FPU register state. */
586	SUPR0FpuEnd(VMMR0ThreadCtxHookIsEnabled(pVCpu));
587	}
588	else
589	fSavedGuest = false;
590	AssertMsg(!( pVCpu->cpum.s.fUseFlags
591	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_MANUAL_XMM_RESTORE)), ("%#x\n", pVCpu->cpum.s.fUseFlags));
592	Assert(!pVCpu->cpum.s.Guest.fUsedFpuGuest);
593	return fSavedGuest;
594	}
595
596
597	/**
598	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
599	* DR7 with safe values.
600	*
601	* @returns VBox status code.
602	* @param pVCpu The cross context virtual CPU structure.
603	*/
604	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu)
605	{
606	/*
607	* Save the host state.
608	*/
609	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
610	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
611	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
612	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
613	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
614	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
615	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
616
617	/* Preemption paranoia. */
618	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
619
620	/*
621	* Make sure DR7 is harmless or else we could trigger breakpoints when
622	* load guest or hypervisor DRx values later.
623	*/
624	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
625	ASMSetDR7(X86_DR7_INIT_VAL);
626
627	return VINF_SUCCESS;
628	}
629
630
631	/**
632	* Saves the guest DRx state residing in host registers and restore the host
633	* register values.
634	*
635	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
636	* since it's assumed that we're shadowing the guest DRx register values
637	* accurately when using the combined hypervisor debug register values
638	* (CPUMR0LoadHyperDebugState).
639	*
640	* @returns true if either guest or hypervisor debug registers were loaded.
641	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
642	* @param fDr6 Whether to include DR6 or not.
643	* @thread EMT(pVCpu)
644	*/
645	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6)
646	{
647	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
648	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
649
650	/*
651	* Do we need to save the guest DRx registered loaded into host registers?
652	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
653	*/
654	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
655	{
656	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
657	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
658	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
659	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
660	if (fDr6)
661	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6() \| X86_DR6_RA1_MASK; /* ASSUMES no guest supprot for TSX-NI / RTM. */
662	}
663	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~(CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
664
665	/*
666	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
667	*/
668	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
669	{
670	/* A bit of paranoia first... */
671	uint64_t uCurDR7 = ASMGetDR7();
672	if (uCurDR7 != X86_DR7_INIT_VAL)
673	ASMSetDR7(X86_DR7_INIT_VAL);
674
675	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
676	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
677	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
678	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
679	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
680	* expensive DRx reads are over DRx writes. */
681	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
682	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
683
684	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
685	}
686
687	return fDrXLoaded;
688	}
689
690
691	/**
692	* Saves the guest DRx state if it resides host registers.
693	*
694	* This does NOT clear any use flags, so the host registers remains loaded with
695	* the guest DRx state upon return. The purpose is only to make sure the values
696	* in the CPU context structure is up to date.
697	*
698	* @returns true if the host registers contains guest values, false if not.
699	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
700	* @param fDr6 Whether to include DR6 or not.
701	* @thread EMT(pVCpu)
702	*/
703	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6)
704	{
705	/*
706	* Do we need to save the guest DRx registered loaded into host registers?
707	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
708	*/
709	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
710	{
711	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
712	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
713	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
714	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
715	if (fDr6)
716	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
717	return true;
718	}
719	return false;
720	}
721
722
723	/**
724	* Lazily sync in the debug state.
725	*
726	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
727	* @param fDr6 Whether to include DR6 or not.
728	* @thread EMT(pVCpu)
729	*/
730	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6)
731	{
732	/*
733	* Save the host state and disarm all host BPs.
734	*/
735	cpumR0SaveHostDebugState(pVCpu);
736	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
737
738	/*
739	* Activate the guest state DR0-3.
740	* DR7 and DR6 (if fDr6 is true) are left to the caller.
741	*/
742	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
743	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
744	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
745	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
746	if (fDr6)
747	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
748
749	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
750	}
751
752
753	/**
754	* Lazily sync in the hypervisor debug state
755	*
756	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
757	* @param fDr6 Whether to include DR6 or not.
758	* @thread EMT(pVCpu)
759	*/
760	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6)
761	{
762	/*
763	* Save the host state and disarm all host BPs.
764	*/
765	cpumR0SaveHostDebugState(pVCpu);
766	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
767
768	/*
769	* Make sure the hypervisor values are up to date.
770	*/
771	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
772
773	/*
774	* Activate the guest state DR0-3.
775	* DR7 and DR6 (if fDr6 is true) are left to the caller.
776	*/
777	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
778	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
779	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
780	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
781	if (fDr6)
782	ASMSetDR6(X86_DR6_INIT_VAL);
783
784	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
785	}
786

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 107703

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