CPUMR0.cpp@ 14871

Last change on this file since 14871 was 14871, checked in by vboxsync, 16 years ago
Removed assertions that will trigger.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 13.2 KB

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1	/* $Id: CPUMR0.cpp 14871 2008-12-01 15:36:48Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_CPUM
27	#include <VBox/cpum.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <iprt/assert.h>
34	#include <iprt/asm.h>
35
36
37
38	/**
39	* Does Ring-0 CPUM initialization.
40	*
41	* This is mainly to check that the Host CPU mode is compatible
42	* with VBox.
43	*
44	* @returns VBox status code.
45	* @param pVM The VM to operate on.
46	*/
47	VMMR0DECL(int) CPUMR0Init(PVM pVM)
48	{
49	LogFlow(("CPUMR0Init: %p\n", pVM));
50
51	/*
52	* Check CR0 & CR4 flags.
53	*/
54	uint32_t u32CR0 = ASMGetCR0();
55	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
56	{
57	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
58	return VERR_UNSUPPORTED_CPU_MODE;
59	}
60
61	/*
62	* Check for sysenter if it's used.
63	*/
64	if (ASMHasCpuId())
65	{
66	uint32_t u32CpuVersion;
67	uint32_t u32Dummy;
68	uint32_t u32Features;
69	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &u32Features);
70	uint32_t u32Family = u32CpuVersion >> 8;
71	uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
72	uint32_t u32Stepping = u32CpuVersion & 0xF;
73
74	/*
75	* Intel docs claim you should test both the flag and family, model & stepping.
76	* Some Pentium Pro cpus have the SEP cpuid flag set, but don't support it.
77	*/
78	if ( (u32Features & X86_CPUID_FEATURE_EDX_SEP)
79	&& !(u32Family == 6 && u32Model < 3 && u32Stepping < 3))
80	{
81	/*
82	* Read the MSR and see if it's in use or not.
83	*/
84	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
85	if (u32)
86	{
87	for (unsigned i=0;i<pVM->cCPUs;i++)
88	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_SYSENTER;
89
90	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
91	}
92	}
93
94	/** @todo check for AMD and syscall!!!!!! */
95	}
96
97
98	/*
99	* Check if debug registers are armed.
100	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
101	*/
102	uint32_t u32DR7 = ASMGetDR7();
103	if (u32DR7 & X86_DR7_ENABLED_MASK)
104	{
105	for (unsigned i=0;i<pVM->cCPUs;i++)
106	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
107	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
108	}
109
110	return VINF_SUCCESS;
111	}
112
113
114	/**
115	* Lazily sync in the FPU/XMM state
116	*
117	* @returns VBox status code.
118	* @param pVM VM handle.
119	* @param pVCpu VMCPU handle.
120	* @param pCtx CPU context
121	*/
122	VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
123	{
124	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
125	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
126
127	/* If the FPU state has already been loaded, then it's a guest trap. */
128	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU)
129	{
130	Assert( ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
131	\|\| ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS)));
132	return VINF_EM_RAW_GUEST_TRAP;
133	}
134
135	/*
136	* There are two basic actions:
137	* 1. Save host fpu and restore guest fpu.
138	* 2. Generate guest trap.
139	*
140	* When entering the hypervisor we'll always enable MP (for proper wait
141	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
142	* is taken from the guest OS in order to get proper SSE handling.
143	*
144	*
145	* Actions taken depending on the guest CR0 flags:
146	*
147	* 3 2 1
148	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
149	* ------------------------------------------------------------------------
150	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
151	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
152	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
153	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
154	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
155	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
156	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
157	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
158	*/
159
160	switch (pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
161	{
162	case X86_CR0_MP \| X86_CR0_TS:
163	case X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS:
164	return VINF_EM_RAW_GUEST_TRAP;
165	default:
166	break;
167	}
168
169	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
170	if (CPUMIsGuestInLongModeEx(pCtx))
171	{
172	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
173	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
174	}
175	else
176	#endif
177	{
178	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
179	uint64_t oldMsrEFERHost;
180	uint32_t oldCR0 = ASMGetCR0();
181
182	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
183	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
184	{
185	/** @todo Do we really need to read this every time?? The host could change this on the fly though.
186	* bird: what about starting by skipping the ASMWrMsr below if we didn't
187	* change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
188	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
189	if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
190	{
191	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
192	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
193	}
194	}
195
196	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
197	int rc = CPUMHandleLazyFPU(pVM, pVCpu);
198	AssertRC(rc);
199	Assert(CPUMIsGuestFPUStateActive(pVCpu));
200
201	/* Restore EFER MSR */
202	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
203	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
204
205	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
206	ASMSetCR0(oldCR0);
207
208	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
209
210	/*
211	* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
212	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
213	*/
214	pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
215	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
216	pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
217
218	CPUMR0LoadFPU(pCtx);
219
220	/*
221	* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
222	*
223	* MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
224	*/
225	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
226	{
227	/** @todo Do we really need to read this every time?? The host could change this on the fly though. */
228	uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
229
230	if (msrEFERHost & MSR_K6_EFER_FFXSR)
231	{
232	/* fxrstor doesn't restore the XMM state! */
233	CPUMR0LoadXMM(pCtx);
234	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
235	}
236	}
237	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
238	}
239
240	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_FPU;
241	return VINF_SUCCESS;
242	}
243
244
245	/**
246	* Save guest FPU/XMM state
247	*
248	* @returns VBox status code.
249	* @param pVM VM handle.
250	* @param pVCpu VMCPU handle.
251	* @param pCtx CPU context
252	*/
253	VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
254	{
255	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
256	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
257	AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
258
259	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
260	if (CPUMIsGuestInLongModeEx(pCtx))
261	{
262	HWACCMR0SaveFPUState(pVM, pVCpu, pCtx);
263	CPUMR0RestoreHostFPUState(&pVCpu->cpum.s);
264	}
265	else
266	#endif
267	{
268	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
269	uint64_t oldMsrEFERHost;
270
271	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
272	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
273	{
274	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
275	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
276	}
277	CPUMR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
278
279	/* Restore EFER MSR */
280	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
281	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost \| MSR_K6_EFER_FFXSR);
282
283	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
284	CPUMR0SaveFPU(pCtx);
285	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
286	{
287	/* fxsave doesn't save the XMM state! */
288	CPUMR0SaveXMM(pCtx);
289	}
290
291	/*
292	* Restore the original FPU control word and MXCSR.
293	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
294	*/
295	CPUMR0SetFCW(pVCpu->cpum.s.Host.fpu.FCW);
296	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
297	CPUMR0SetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
298	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
299	}
300
301	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU \| CPUM_MANUAL_XMM_RESTORE);
302	return VINF_SUCCESS;
303	}
304
305
306	/**
307	* Save guest debug state
308	*
309	* @returns VBox status code.
310	* @param pVM VM handle.
311	* @param pVCpu VMCPU handle.
312	* @param pCtx CPU context
313	* @param fDR6 Include DR6 or not
314	*/
315	VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
316	{
317	Assert(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
318
319	/* Save the guest's debug state. The caller is responsible for DR7. */
320	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
321	if (CPUMIsGuestInLongModeEx(pCtx))
322	{
323	HWACCMR0SaveDebugState(pVM, pVCpu, pCtx, fDR6);
324	}
325	else
326	#endif
327	{
328	pCtx->dr[0] = ASMGetDR0();
329	pCtx->dr[1] = ASMGetDR1();
330	pCtx->dr[2] = ASMGetDR2();
331	pCtx->dr[3] = ASMGetDR3();
332	if (fDR6)
333	pCtx->dr[6] = ASMGetDR6();
334	}
335
336	/*
337	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
338	* DR7 contains 0x400 right now.
339	*/
340	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
341	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
342	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
343	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
344	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
345	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
346
347	pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
348	return VINF_SUCCESS;
349	}
350
351
352	/**
353	* Lazily sync in the debug state
354	*
355	* @returns VBox status code.
356	* @param pVM VM handle.
357	* @param pVCpu VMCPU handle.
358	* @param pCtx CPU context
359	* @param fDR6 Include DR6 or not
360	*/
361	VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
362	{
363	/* Save the host state. */
364	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
365	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
366	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
367	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
368	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
369	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
370	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
371	/* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
372	ASMSetDR7(X86_DR7_INIT_VAL);
373
374	/* Activate the guest state DR0-3; DR7 is left to the caller. */
375	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
376	if (CPUMIsGuestInLongModeEx(pCtx))
377	{
378	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
379	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_DEBUG_STATE;
380	}
381	else
382	#endif
383	{
384	ASMSetDR0(pCtx->dr[0]);
385	ASMSetDR1(pCtx->dr[1]);
386	ASMSetDR2(pCtx->dr[2]);
387	ASMSetDR3(pCtx->dr[3]);
388	if (fDR6)
389	ASMSetDR6(pCtx->dr[6]);
390	}
391
392	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS;
393	return VINF_SUCCESS;
394	}
395
396

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 14871

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