CPUMR0.cpp@ 16111

Last change on this file since 16111 was 16111, checked in by vboxsync, 16 years ago
cpumR0SaveHostRestoreGuestFPUState sets CPUM_USED_FPU, unnecessary to set it a third time.
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1	/* $Id: CPUMR0.cpp 16111 2009-01-21 01:42:23Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_CPUM
27	#include <VBox/cpum.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <VBox/hwaccm.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36
37
38
39	/**
40	* Does Ring-0 CPUM initialization.
41	*
42	* This is mainly to check that the Host CPU mode is compatible
43	* with VBox.
44	*
45	* @returns VBox status code.
46	* @param pVM The VM to operate on.
47	*/
48	VMMR0DECL(int) CPUMR0Init(PVM pVM)
49	{
50	LogFlow(("CPUMR0Init: %p\n", pVM));
51
52	/*
53	* Check CR0 & CR4 flags.
54	*/
55	uint32_t u32CR0 = ASMGetCR0();
56	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
57	{
58	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
59	return VERR_UNSUPPORTED_CPU_MODE;
60	}
61
62	/*
63	* Check for sysenter if it's used.
64	*/
65	if (ASMHasCpuId())
66	{
67	uint32_t u32CpuVersion;
68	uint32_t u32Dummy;
69	uint32_t u32Features;
70	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &u32Features);
71	uint32_t u32Family = u32CpuVersion >> 8;
72	uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
73	uint32_t u32Stepping = u32CpuVersion & 0xF;
74
75	/*
76	* Intel docs claim you should test both the flag and family, model & stepping.
77	* Some Pentium Pro cpus have the SEP cpuid flag set, but don't support it.
78	*/
79	if ( (u32Features & X86_CPUID_FEATURE_EDX_SEP)
80	&& !(u32Family == 6 && u32Model < 3 && u32Stepping < 3))
81	{
82	/*
83	* Read the MSR and see if it's in use or not.
84	*/
85	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
86	if (u32)
87	{
88	for (unsigned i=0;i<pVM->cCPUs;i++)
89	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_SYSENTER;
90
91	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
92	}
93	}
94
95	/** @todo check for AMD and syscall!!!!!! */
96	}
97
98
99	/*
100	* Check if debug registers are armed.
101	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
102	*/
103	uint32_t u32DR7 = ASMGetDR7();
104	if (u32DR7 & X86_DR7_ENABLED_MASK)
105	{
106	for (unsigned i=0;i<pVM->cCPUs;i++)
107	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
108	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
109	}
110
111	return VINF_SUCCESS;
112	}
113
114
115	/**
116	* Lazily sync in the FPU/XMM state
117	*
118	* @returns VBox status code.
119	* @param pVM VM handle.
120	* @param pVCpu VMCPU handle.
121	* @param pCtx CPU context
122	*/
123	VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
124	{
125	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
126	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
127
128	/* If the FPU state has already been loaded, then it's a guest trap. */
129	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU)
130	{
131	Assert( ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
132	\|\| ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS)));
133	return VINF_EM_RAW_GUEST_TRAP;
134	}
135
136	/*
137	* There are two basic actions:
138	* 1. Save host fpu and restore guest fpu.
139	* 2. Generate guest trap.
140	*
141	* When entering the hypervisor we'll always enable MP (for proper wait
142	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
143	* is taken from the guest OS in order to get proper SSE handling.
144	*
145	*
146	* Actions taken depending on the guest CR0 flags:
147	*
148	* 3 2 1
149	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
150	* ------------------------------------------------------------------------
151	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
152	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
153	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
154	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
155	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
156	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
157	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
158	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
159	*/
160
161	switch (pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
162	{
163	case X86_CR0_MP \| X86_CR0_TS:
164	case X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS:
165	return VINF_EM_RAW_GUEST_TRAP;
166	default:
167	break;
168	}
169
170	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
171	if (CPUMIsGuestInLongModeEx(pCtx))
172	{
173	/* Save/Restore the state on entry as we need to be in 64 bits mode to access the full state. */
174	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE \| CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM;
175	/** @todo who is saving the host state?? */
176	}
177	else
178	#endif
179	{
180	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
181	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL /** @todo remove the #else here and move cpumHandleLazyFPUAsm back to VMMGC after branching out 2.1. */
182	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
183	uint64_t SavedEFER = 0;
184	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
185	{
186	SavedEFER = ASMRdMsr(MSR_K6_EFER);
187	if (SavedEFER & MSR_K6_EFER_FFXSR)
188	{
189	ASMWrMsr(MSR_K6_EFER, SavedEFER & ~MSR_K6_EFER_FFXSR);
190	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
191	}
192	}
193
194	/* Do the job and record that we've switched FPU state. */
195	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
196
197	/* Restore EFER. */
198	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
199	ASMWrMsr(MSR_K6_EFER, SavedEFER);
200
201	# else
202	uint64_t oldMsrEFERHost = 0;
203	uint32_t oldCR0 = ASMGetCR0();
204
205	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
206	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
207	{
208	/** @todo Do we really need to read this every time?? The host could change this on the fly though.
209	* bird: what about starting by skipping the ASMWrMsr below if we didn't
210	* change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
211	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
212	if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
213	{
214	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
215	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
216	}
217	}
218
219	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
220	int rc = CPUMHandleLazyFPU(pVM, pVCpu);
221	AssertRC(rc);
222	Assert(CPUMIsGuestFPUStateActive(pVCpu));
223
224	/* Restore EFER MSR */
225	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
226	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
227
228	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
229	ASMSetCR0(oldCR0);
230	# endif
231
232	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
233
234	/*
235	* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
236	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
237	*/
238	pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
239	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
240	pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
241
242	cpumR0LoadFPU(pCtx);
243
244	/*
245	* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
246	*
247	* MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
248	*/
249	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
250	{
251	/** @todo Do we really need to read this every time?? The host could change this on the fly though. */
252	uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
253
254	if (msrEFERHost & MSR_K6_EFER_FFXSR)
255	{
256	/* fxrstor doesn't restore the XMM state! */
257	cpumR0LoadXMM(pCtx);
258	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
259	}
260	}
261
262	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
263	}
264
265	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM; /** @todo clean up, this is done above by the ASM worker. */
266	return VINF_SUCCESS;
267	}
268
269
270	/**
271	* Save guest FPU/XMM state
272	*
273	* @returns VBox status code.
274	* @param pVM VM handle.
275	* @param pVCpu VMCPU handle.
276	* @param pCtx CPU context
277	*/
278	VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
279	{
280	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
281	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
282	AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
283
284	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
285	if (CPUMIsGuestInLongModeEx(pCtx))
286	{
287	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
288	HWACCMR0SaveFPUState(pVM, pVCpu, pCtx);
289	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
290	}
291	else
292	#endif
293	{
294	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
295	uint64_t oldMsrEFERHost = 0;
296
297	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
298	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
299	{
300	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
301	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
302	}
303	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
304
305	/* Restore EFER MSR */
306	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
307	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost \| MSR_K6_EFER_FFXSR);
308
309	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
310	cpumR0SaveFPU(pCtx);
311	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
312	{
313	/* fxsave doesn't save the XMM state! */
314	cpumR0SaveXMM(pCtx);
315	}
316
317	/*
318	* Restore the original FPU control word and MXCSR.
319	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
320	*/
321	cpumR0SetFCW(pVCpu->cpum.s.Host.fpu.FCW);
322	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
323	cpumR0SetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
324	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
325	}
326
327	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU \| CPUM_MANUAL_XMM_RESTORE);
328	return VINF_SUCCESS;
329	}
330
331
332	/**
333	* Save guest debug state
334	*
335	* @returns VBox status code.
336	* @param pVM VM handle.
337	* @param pVCpu VMCPU handle.
338	* @param pCtx CPU context
339	* @param fDR6 Include DR6 or not
340	*/
341	VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
342	{
343	Assert(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
344
345	/* Save the guest's debug state. The caller is responsible for DR7. */
346	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
347	if (CPUMIsGuestInLongModeEx(pCtx))
348	{
349	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_STATE))
350	{
351	uint64_t dr6 = pCtx->dr[6];
352
353	HWACCMR0SaveDebugState(pVM, pVCpu, pCtx);
354	if (!fDR6) /* dr6 was already up-to-date */
355	pCtx->dr[6] = dr6;
356	}
357	}
358	else
359	#endif
360	{
361	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
362	cpumR0SaveDRx(&pCtx->dr[0]);
363	#else
364	pCtx->dr[0] = ASMGetDR0();
365	pCtx->dr[1] = ASMGetDR1();
366	pCtx->dr[2] = ASMGetDR2();
367	pCtx->dr[3] = ASMGetDR3();
368	#endif
369	if (fDR6)
370	pCtx->dr[6] = ASMGetDR6();
371	}
372
373	/*
374	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
375	* DR7 contains 0x400 right now.
376	*/
377	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
378	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
379	cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
380	#else
381	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
382	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
383	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
384	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
385	#endif
386	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
387	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
388
389	pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
390	return VINF_SUCCESS;
391	}
392
393
394	/**
395	* Lazily sync in the debug state
396	*
397	* @returns VBox status code.
398	* @param pVM VM handle.
399	* @param pVCpu VMCPU handle.
400	* @param pCtx CPU context
401	* @param fDR6 Include DR6 or not
402	*/
403	VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
404	{
405	/* Save the host state. */
406	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
407	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
408	cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
409	#else
410	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
411	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
412	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
413	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
414	#endif
415	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
416	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
417	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
418	/* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
419	ASMSetDR7(X86_DR7_INIT_VAL);
420
421	/* Activate the guest state DR0-3; DR7 is left to the caller. */
422	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
423	if (CPUMIsGuestInLongModeEx(pCtx))
424	{
425	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
426	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_DEBUG_STATE;
427	}
428	else
429	#endif
430	{
431	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
432	cpumR0LoadDRx(&pCtx->dr[0]);
433	#else
434	ASMSetDR0(pCtx->dr[0]);
435	ASMSetDR1(pCtx->dr[1]);
436	ASMSetDR2(pCtx->dr[2]);
437	ASMSetDR3(pCtx->dr[3]);
438	#endif
439	if (fDR6)
440	ASMSetDR6(pCtx->dr[6]);
441	}
442
443	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS;
444	return VINF_SUCCESS;
445	}
446
447

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 16111

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