CPUMR0.cpp@ 16119

Last change on this file since 16119 was 16119, checked in by vboxsync, 16 years ago
Clear CPUM_SYNC_FPU_STATE in CPUMR0SaveGuestFPU.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 15.5 KB

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1	/* $Id: CPUMR0.cpp 16119 2009-01-21 10:19:34Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_CPUM
27	#include <VBox/cpum.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <VBox/hwaccm.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36
37
38
39	/**
40	* Does Ring-0 CPUM initialization.
41	*
42	* This is mainly to check that the Host CPU mode is compatible
43	* with VBox.
44	*
45	* @returns VBox status code.
46	* @param pVM The VM to operate on.
47	*/
48	VMMR0DECL(int) CPUMR0Init(PVM pVM)
49	{
50	LogFlow(("CPUMR0Init: %p\n", pVM));
51
52	/*
53	* Check CR0 & CR4 flags.
54	*/
55	uint32_t u32CR0 = ASMGetCR0();
56	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
57	{
58	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
59	return VERR_UNSUPPORTED_CPU_MODE;
60	}
61
62	/*
63	* Check for sysenter if it's used.
64	*/
65	if (ASMHasCpuId())
66	{
67	uint32_t u32CpuVersion;
68	uint32_t u32Dummy;
69	uint32_t u32Features;
70	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &u32Features);
71	uint32_t u32Family = u32CpuVersion >> 8;
72	uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
73	uint32_t u32Stepping = u32CpuVersion & 0xF;
74
75	/*
76	* Intel docs claim you should test both the flag and family, model & stepping.
77	* Some Pentium Pro cpus have the SEP cpuid flag set, but don't support it.
78	*/
79	if ( (u32Features & X86_CPUID_FEATURE_EDX_SEP)
80	&& !(u32Family == 6 && u32Model < 3 && u32Stepping < 3))
81	{
82	/*
83	* Read the MSR and see if it's in use or not.
84	*/
85	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
86	if (u32)
87	{
88	for (unsigned i=0;i<pVM->cCPUs;i++)
89	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_SYSENTER;
90
91	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
92	}
93	}
94
95	/** @todo check for AMD and syscall!!!!!! */
96	}
97
98
99	/*
100	* Check if debug registers are armed.
101	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
102	*/
103	uint32_t u32DR7 = ASMGetDR7();
104	if (u32DR7 & X86_DR7_ENABLED_MASK)
105	{
106	for (unsigned i=0;i<pVM->cCPUs;i++)
107	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
108	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
109	}
110
111	return VINF_SUCCESS;
112	}
113
114
115	/**
116	* Lazily sync in the FPU/XMM state
117	*
118	* @returns VBox status code.
119	* @param pVM VM handle.
120	* @param pVCpu VMCPU handle.
121	* @param pCtx CPU context
122	*/
123	VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
124	{
125	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
126	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
127
128	/* If the FPU state has already been loaded, then it's a guest trap. */
129	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU)
130	{
131	Assert( ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
132	\|\| ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS)));
133	return VINF_EM_RAW_GUEST_TRAP;
134	}
135
136	/*
137	* There are two basic actions:
138	* 1. Save host fpu and restore guest fpu.
139	* 2. Generate guest trap.
140	*
141	* When entering the hypervisor we'll always enable MP (for proper wait
142	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
143	* is taken from the guest OS in order to get proper SSE handling.
144	*
145	*
146	* Actions taken depending on the guest CR0 flags:
147	*
148	* 3 2 1
149	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
150	* ------------------------------------------------------------------------
151	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
152	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
153	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
154	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
155	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
156	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
157	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
158	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
159	*/
160
161	switch (pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
162	{
163	case X86_CR0_MP \| X86_CR0_TS:
164	case X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS:
165	return VINF_EM_RAW_GUEST_TRAP;
166	default:
167	break;
168	}
169
170	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
171	if (CPUMIsGuestInLongModeEx(pCtx))
172	{
173	/* Save the host state and record the fact (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM). */
174	cpumR0SaveHostFPUState(&pVCpu->cpum.s);
175
176	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
177	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
178	}
179	else
180	#endif
181	{
182	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
183	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL /** @todo remove the #else here and move cpumHandleLazyFPUAsm back to VMMGC after branching out 2.1. */
184	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
185	uint64_t SavedEFER = 0;
186	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
187	{
188	SavedEFER = ASMRdMsr(MSR_K6_EFER);
189	if (SavedEFER & MSR_K6_EFER_FFXSR)
190	{
191	ASMWrMsr(MSR_K6_EFER, SavedEFER & ~MSR_K6_EFER_FFXSR);
192	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
193	}
194	}
195
196	/* Do the job and record that we've switched FPU state. */
197	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
198
199	/* Restore EFER. */
200	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
201	ASMWrMsr(MSR_K6_EFER, SavedEFER);
202
203	# else
204	uint64_t oldMsrEFERHost = 0;
205	uint32_t oldCR0 = ASMGetCR0();
206
207	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
208	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
209	{
210	/** @todo Do we really need to read this every time?? The host could change this on the fly though.
211	* bird: what about starting by skipping the ASMWrMsr below if we didn't
212	* change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
213	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
214	if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
215	{
216	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
217	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
218	}
219	}
220
221	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
222	int rc = CPUMHandleLazyFPU(pVM, pVCpu);
223	AssertRC(rc);
224	Assert(CPUMIsGuestFPUStateActive(pVCpu));
225
226	/* Restore EFER MSR */
227	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
228	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
229
230	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
231	ASMSetCR0(oldCR0);
232	# endif
233
234	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
235
236	/*
237	* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
238	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
239	*/
240	pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
241	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
242	pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
243
244	cpumR0LoadFPU(pCtx);
245
246	/*
247	* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
248	*
249	* MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
250	*/
251	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
252	{
253	/** @todo Do we really need to read this every time?? The host could change this on the fly though. */
254	uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
255
256	if (msrEFERHost & MSR_K6_EFER_FFXSR)
257	{
258	/* fxrstor doesn't restore the XMM state! */
259	cpumR0LoadXMM(pCtx);
260	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
261	}
262	}
263
264	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
265	}
266
267	Assert(pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM) == (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM));
268	return VINF_SUCCESS;
269	}
270
271
272	/**
273	* Save guest FPU/XMM state
274	*
275	* @returns VBox status code.
276	* @param pVM VM handle.
277	* @param pVCpu VMCPU handle.
278	* @param pCtx CPU context
279	*/
280	VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
281	{
282	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
283	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
284	AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
285
286	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
287	if (CPUMIsGuestInLongModeEx(pCtx))
288	{
289	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
290	{
291	HWACCMR0SaveFPUState(pVM, pVCpu, pCtx);
292	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
293	}
294	/* else nothing to do; we didn't perform a world switch */
295	}
296	else
297	#endif
298	{
299	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
300	uint64_t oldMsrEFERHost = 0;
301
302	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
303	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
304	{
305	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
306	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
307	}
308	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
309
310	/* Restore EFER MSR */
311	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
312	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost \| MSR_K6_EFER_FFXSR);
313
314	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
315	cpumR0SaveFPU(pCtx);
316	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
317	{
318	/* fxsave doesn't save the XMM state! */
319	cpumR0SaveXMM(pCtx);
320	}
321
322	/*
323	* Restore the original FPU control word and MXCSR.
324	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
325	*/
326	cpumR0SetFCW(pVCpu->cpum.s.Host.fpu.FCW);
327	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
328	cpumR0SetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
329	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
330	}
331
332	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU \| CPUM_SYNC_FPU_STATE \| CPUM_MANUAL_XMM_RESTORE);
333	return VINF_SUCCESS;
334	}
335
336
337	/**
338	* Save guest debug state
339	*
340	* @returns VBox status code.
341	* @param pVM VM handle.
342	* @param pVCpu VMCPU handle.
343	* @param pCtx CPU context
344	* @param fDR6 Include DR6 or not
345	*/
346	VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
347	{
348	Assert(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
349
350	/* Save the guest's debug state. The caller is responsible for DR7. */
351	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
352	if (CPUMIsGuestInLongModeEx(pCtx))
353	{
354	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_STATE))
355	{
356	uint64_t dr6 = pCtx->dr[6];
357
358	HWACCMR0SaveDebugState(pVM, pVCpu, pCtx);
359	if (!fDR6) /* dr6 was already up-to-date */
360	pCtx->dr[6] = dr6;
361	}
362	}
363	else
364	#endif
365	{
366	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
367	cpumR0SaveDRx(&pCtx->dr[0]);
368	#else
369	pCtx->dr[0] = ASMGetDR0();
370	pCtx->dr[1] = ASMGetDR1();
371	pCtx->dr[2] = ASMGetDR2();
372	pCtx->dr[3] = ASMGetDR3();
373	#endif
374	if (fDR6)
375	pCtx->dr[6] = ASMGetDR6();
376	}
377
378	/*
379	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
380	* DR7 contains 0x400 right now.
381	*/
382	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
383	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
384	cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
385	#else
386	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
387	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
388	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
389	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
390	#endif
391	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
392	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
393
394	pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
395	return VINF_SUCCESS;
396	}
397
398
399	/**
400	* Lazily sync in the debug state
401	*
402	* @returns VBox status code.
403	* @param pVM VM handle.
404	* @param pVCpu VMCPU handle.
405	* @param pCtx CPU context
406	* @param fDR6 Include DR6 or not
407	*/
408	VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
409	{
410	/* Save the host state. */
411	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
412	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
413	cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
414	#else
415	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
416	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
417	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
418	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
419	#endif
420	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
421	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
422	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
423	/* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
424	ASMSetDR7(X86_DR7_INIT_VAL);
425
426	/* Activate the guest state DR0-3; DR7 is left to the caller. */
427	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
428	if (CPUMIsGuestInLongModeEx(pCtx))
429	{
430	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
431	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_DEBUG_STATE;
432	}
433	else
434	#endif
435	{
436	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
437	cpumR0LoadDRx(&pCtx->dr[0]);
438	#else
439	ASMSetDR0(pCtx->dr[0]);
440	ASMSetDR1(pCtx->dr[1]);
441	ASMSetDR2(pCtx->dr[2]);
442	ASMSetDR3(pCtx->dr[3]);
443	#endif
444	if (fDR6)
445	ASMSetDR6(pCtx->dr[6]);
446	}
447
448	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS;
449	return VINF_SUCCESS;
450	}
451
452

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 16119

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