CPUMR0.cpp@ 33936

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1	/* $Id: CPUMR0.cpp 33936 2010-11-10 15:41:04Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vm.h>
26	#include <VBox/x86.h>
27	#include <VBox/err.h>
28	#include <VBox/log.h>
29	#include <VBox/hwaccm.h>
30	#include <iprt/assert.h>
31	#include <iprt/asm-amd64-x86.h>
32	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
33	# include <iprt/mem.h>
34	# include <iprt/memobj.h>
35	# include <VBox/apic.h>
36	#endif
37
38
39	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
40	/** Local APIC mappings */
41	typedef struct
42	{
43	bool fEnabled;
44	uint64_t PhysBase;
45	RTR0MEMOBJ hMemObj;
46	RTR0MEMOBJ hMapObj;
47	void *pv;
48	uint32_t fHasThermal;
49	} CPUMHOSTLAPIC;
50
51	static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
52	static int cpumR0MapLocalApics(void);
53	static void cpumR0UnmapLocalApics(void);
54	#endif
55
56
57	/**
58	* Does the Ring-0 CPU initialization once during module load.
59	* XXX Host-CPU hot-plugging?
60	*/
61	VMMR0DECL(int) CPUMR0ModuleInit(void)
62	{
63	int rc = VINF_SUCCESS;
64	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
65	rc = cpumR0MapLocalApics();
66	#endif
67	return rc;
68	}
69
70
71	/**
72	* Terminate the module.
73	*/
74	VMMR0DECL(int) CPUMR0ModuleTerm(void)
75	{
76	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
77	cpumR0UnmapLocalApics();
78	#endif
79	return VINF_SUCCESS;
80	}
81
82
83	/**
84	* Does Ring-0 CPUM initialization.
85	*
86	* This is mainly to check that the Host CPU mode is compatible
87	* with VBox.
88	*
89	* @returns VBox status code.
90	* @param pVM The VM to operate on.
91	*/
92	VMMR0DECL(int) CPUMR0Init(PVM pVM)
93	{
94	LogFlow(("CPUMR0Init: %p\n", pVM));
95
96	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
97	for (unsigned i = 0; i < RT_ELEMENTS(g_aLApics); i++)
98	if (g_aLApics[i].pv)
99	SUPR0Printf(" CPU%d: %llx => %llx\n", i, g_aLApics[i].PhysBase, (uint64_t)g_aLApics[i].pv);
100	#endif
101
102	/*
103	* Check CR0 & CR4 flags.
104	*/
105	uint32_t u32CR0 = ASMGetCR0();
106	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
107	{
108	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
109	return VERR_UNSUPPORTED_CPU_MODE;
110	}
111
112	/*
113	* Check for sysenter and syscall usage.
114	*/
115	if (ASMHasCpuId())
116	{
117	/*
118	* SYSENTER/SYSEXIT
119	*
120	* Intel docs claim you should test both the flag and family, model &
121	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
122	* but don't support it. AMD CPUs may support this feature in legacy
123	* mode, they've banned it from long mode. Since we switch to 32-bit
124	* mode when entering raw-mode context the feature would become
125	* accessible again on AMD CPUs, so we have to check regardless of
126	* host bitness.
127	*/
128	uint32_t u32CpuVersion;
129	uint32_t u32Dummy;
130	uint32_t fFeatures;
131	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
132	uint32_t u32Family = u32CpuVersion >> 8;
133	uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
134	uint32_t u32Stepping = u32CpuVersion & 0xF;
135	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
136	&& ( u32Family != 6 /* (> pentium pro) */
137	\|\| u32Model >= 3
138	\|\| u32Stepping >= 3
139	\|\| !ASMIsIntelCpu())
140	)
141	{
142	/*
143	* Read the MSR and see if it's in use or not.
144	*/
145	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
146	if (u32)
147	{
148	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
149	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
150	}
151	}
152
153	/*
154	* SYSCALL/SYSRET
155	*
156	* This feature is indicated by the SEP bit returned in EDX by CPUID
157	* function 0x80000001. Intel CPUs only supports this feature in
158	* long mode. Since we're not running 64-bit guests in raw-mode there
159	* are no issues with 32-bit intel hosts.
160	*/
161	uint32_t cExt = 0;
162	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
163	if ( cExt >= 0x80000001
164	&& cExt <= 0x8000ffff)
165	{
166	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
167	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_SEP)
168	{
169	#ifdef RT_ARCH_X86
170	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
171	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
172	# else
173	if (!ASMIsIntelCpu())
174	# endif
175	#endif
176	{
177	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
178	if (fEfer & MSR_K6_EFER_SCE)
179	{
180	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
181	Log(("CPUMR0Init: host uses syscall\n"));
182	}
183	}
184	}
185	}
186	}
187
188
189	/*
190	* Check if debug registers are armed.
191	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
192	*/
193	uint32_t u32DR7 = ASMGetDR7();
194	if (u32DR7 & X86_DR7_ENABLED_MASK)
195	{
196	for (VMCPUID i = 0; i < pVM->cCpus; i++)
197	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
198	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
199	}
200
201	return VINF_SUCCESS;
202	}
203
204
205	/**
206	* Lazily sync in the FPU/XMM state
207	*
208	* @returns VBox status code.
209	* @param pVM VM handle.
210	* @param pVCpu VMCPU handle.
211	* @param pCtx CPU context
212	*/
213	VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
214	{
215	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
216	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
217
218	/* If the FPU state has already been loaded, then it's a guest trap. */
219	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU)
220	{
221	Assert( ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
222	\|\| ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS)));
223	return VINF_EM_RAW_GUEST_TRAP;
224	}
225
226	/*
227	* There are two basic actions:
228	* 1. Save host fpu and restore guest fpu.
229	* 2. Generate guest trap.
230	*
231	* When entering the hypervisor we'll always enable MP (for proper wait
232	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
233	* is taken from the guest OS in order to get proper SSE handling.
234	*
235	*
236	* Actions taken depending on the guest CR0 flags:
237	*
238	* 3 2 1
239	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
240	* ------------------------------------------------------------------------
241	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
242	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
243	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
244	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
245	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
246	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
247	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
248	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
249	*/
250
251	switch (pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
252	{
253	case X86_CR0_MP \| X86_CR0_TS:
254	case X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS:
255	return VINF_EM_RAW_GUEST_TRAP;
256	default:
257	break;
258	}
259
260	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
261	if (CPUMIsGuestInLongModeEx(pCtx))
262	{
263	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
264
265	/* Save the host state and record the fact (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM). */
266	cpumR0SaveHostFPUState(&pVCpu->cpum.s);
267
268	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
269	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
270	}
271	else
272	#endif
273	{
274	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
275	# if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined(VBOX_WITH_KERNEL_USING_XMM) /** @todo remove the #else here and move cpumHandleLazyFPUAsm back to VMMGC after branching out 3.0!!. */
276	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE));
277	/** @todo Move the FFXR handling down into
278	* cpumR0SaveHostRestoreguestFPUState to optimize the
279	* VBOX_WITH_KERNEL_USING_XMM handling. */
280	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
281	uint64_t SavedEFER = 0;
282	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
283	{
284	SavedEFER = ASMRdMsr(MSR_K6_EFER);
285	if (SavedEFER & MSR_K6_EFER_FFXSR)
286	{
287	ASMWrMsr(MSR_K6_EFER, SavedEFER & ~MSR_K6_EFER_FFXSR);
288	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
289	}
290	}
291
292	/* Do the job and record that we've switched FPU state. */
293	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
294
295	/* Restore EFER. */
296	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
297	ASMWrMsr(MSR_K6_EFER, SavedEFER);
298
299	# else
300	uint64_t oldMsrEFERHost = 0;
301	uint32_t oldCR0 = ASMGetCR0();
302
303	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
304	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
305	{
306	/** @todo Do we really need to read this every time?? The host could change this on the fly though.
307	* bird: what about starting by skipping the ASMWrMsr below if we didn't
308	* change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
309	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
310	if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
311	{
312	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
313	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
314	}
315	}
316
317	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
318	int rc = CPUMHandleLazyFPU(pVCpu);
319	AssertRC(rc);
320	Assert(CPUMIsGuestFPUStateActive(pVCpu));
321
322	/* Restore EFER MSR */
323	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
324	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
325
326	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
327	ASMSetCR0(oldCR0);
328	# endif
329
330	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
331
332	/*
333	* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
334	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
335	*/
336	pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
337	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
338	pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
339
340	cpumR0LoadFPU(pCtx);
341
342	/*
343	* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
344	*
345	* MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
346	*/
347	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
348	{
349	/** @todo Do we really need to read this every time?? The host could change this on the fly though. */
350	uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
351
352	if (msrEFERHost & MSR_K6_EFER_FFXSR)
353	{
354	/* fxrstor doesn't restore the XMM state! */
355	cpumR0LoadXMM(pCtx);
356	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
357	}
358	}
359
360	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
361	}
362
363	Assert((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM)) == (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM));
364	return VINF_SUCCESS;
365	}
366
367
368	/**
369	* Save guest FPU/XMM state
370	*
371	* @returns VBox status code.
372	* @param pVM VM handle.
373	* @param pVCpu VMCPU handle.
374	* @param pCtx CPU context
375	*/
376	VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
377	{
378	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
379	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
380	AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
381
382	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
383	if (CPUMIsGuestInLongModeEx(pCtx))
384	{
385	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
386	{
387	HWACCMR0SaveFPUState(pVM, pVCpu, pCtx);
388	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
389	}
390	/* else nothing to do; we didn't perform a world switch */
391	}
392	else
393	#endif
394	{
395	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
396	# ifdef VBOX_WITH_KERNEL_USING_XMM
397	/*
398	* We've already saved the XMM registers in the assembly wrapper, so
399	* we have to save them before saving the entire FPU state and put them
400	* back afterwards.
401	*/
402	/** @todo This could be skipped if MSR_K6_EFER_FFXSR is set, but
403	* I'm not able to test such an optimization tonight.
404	* We could just all this in assembly. */
405	uint128_t aGuestXmmRegs[16];
406	memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.fpu.aXMM[0], sizeof(aGuestXmmRegs));
407	# endif
408
409	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
410	uint64_t oldMsrEFERHost = 0;
411	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
412	{
413	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
414	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
415	}
416	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
417
418	/* Restore EFER MSR */
419	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
420	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost \| MSR_K6_EFER_FFXSR);
421
422	# ifdef VBOX_WITH_KERNEL_USING_XMM
423	memcpy(&pVCpu->cpum.s.Guest.fpu.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
424	# endif
425
426	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
427	# ifdef VBOX_WITH_KERNEL_USING_XMM
428	# error "Fix all the NM_TRAPS_IN_KERNEL_MODE code path. I'm not going to fix unused code now."
429	# endif
430	cpumR0SaveFPU(pCtx);
431	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
432	{
433	/* fxsave doesn't save the XMM state! */
434	cpumR0SaveXMM(pCtx);
435	}
436
437	/*
438	* Restore the original FPU control word and MXCSR.
439	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
440	*/
441	cpumR0SetFCW(pVCpu->cpum.s.Host.fpu.FCW);
442	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
443	cpumR0SetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
444	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
445	}
446
447	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU \| CPUM_SYNC_FPU_STATE \| CPUM_MANUAL_XMM_RESTORE);
448	return VINF_SUCCESS;
449	}
450
451
452	/**
453	* Save guest debug state
454	*
455	* @returns VBox status code.
456	* @param pVM VM handle.
457	* @param pVCpu VMCPU handle.
458	* @param pCtx CPU context
459	* @param fDR6 Include DR6 or not
460	*/
461	VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
462	{
463	Assert(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
464
465	/* Save the guest's debug state. The caller is responsible for DR7. */
466	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
467	if (CPUMIsGuestInLongModeEx(pCtx))
468	{
469	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_STATE))
470	{
471	uint64_t dr6 = pCtx->dr[6];
472
473	HWACCMR0SaveDebugState(pVM, pVCpu, pCtx);
474	if (!fDR6) /* dr6 was already up-to-date */
475	pCtx->dr[6] = dr6;
476	}
477	}
478	else
479	#endif
480	{
481	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
482	cpumR0SaveDRx(&pCtx->dr[0]);
483	#else
484	pCtx->dr[0] = ASMGetDR0();
485	pCtx->dr[1] = ASMGetDR1();
486	pCtx->dr[2] = ASMGetDR2();
487	pCtx->dr[3] = ASMGetDR3();
488	#endif
489	if (fDR6)
490	pCtx->dr[6] = ASMGetDR6();
491	}
492
493	/*
494	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
495	* DR7 contains 0x400 right now.
496	*/
497	CPUMR0LoadHostDebugState(pVM, pVCpu);
498	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS));
499	return VINF_SUCCESS;
500	}
501
502
503	/**
504	* Lazily sync in the debug state
505	*
506	* @returns VBox status code.
507	* @param pVM VM handle.
508	* @param pVCpu VMCPU handle.
509	* @param pCtx CPU context
510	* @param fDR6 Include DR6 or not
511	*/
512	VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
513	{
514	/* Save the host state. */
515	CPUMR0SaveHostDebugState(pVM, pVCpu);
516	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
517
518	/* Activate the guest state DR0-3; DR7 is left to the caller. */
519	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
520	if (CPUMIsGuestInLongModeEx(pCtx))
521	{
522	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
523	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_DEBUG_STATE;
524	}
525	else
526	#endif
527	{
528	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
529	cpumR0LoadDRx(&pCtx->dr[0]);
530	#else
531	ASMSetDR0(pCtx->dr[0]);
532	ASMSetDR1(pCtx->dr[1]);
533	ASMSetDR2(pCtx->dr[2]);
534	ASMSetDR3(pCtx->dr[3]);
535	#endif
536	if (fDR6)
537	ASMSetDR6(pCtx->dr[6]);
538	}
539
540	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS;
541	return VINF_SUCCESS;
542	}
543
544	/**
545	* Save the host debug state
546	*
547	* @returns VBox status code.
548	* @param pVM VM handle.
549	* @param pVCpu VMCPU handle.
550	*/
551	VMMR0DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu)
552	{
553	/* Save the host state. */
554	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
555	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
556	cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
557	#else
558	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
559	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
560	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
561	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
562	#endif
563	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
564	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
565	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
566	/* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
567	ASMSetDR7(X86_DR7_INIT_VAL);
568
569	return VINF_SUCCESS;
570	}
571
572	/**
573	* Load the host debug state
574	*
575	* @returns VBox status code.
576	* @param pVM VM handle.
577	* @param pVCpu VMCPU handle.
578	*/
579	VMMR0DECL(int) CPUMR0LoadHostDebugState(PVM pVM, PVMCPU pVCpu)
580	{
581	Assert(pVCpu->cpum.s.fUseFlags & (CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HYPER));
582
583	/*
584	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
585	* DR7 contains 0x400 right now.
586	*/
587	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
588	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
589	cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
590	#else
591	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
592	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
593	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
594	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
595	#endif
596	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
597	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
598
599	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HYPER);
600	return VINF_SUCCESS;
601	}
602
603
604	/**
605	* Lazily sync in the hypervisor debug state
606	*
607	* @returns VBox status code.
608	* @param pVM VM handle.
609	* @param pVCpu VMCPU handle.
610	* @param pCtx CPU context
611	* @param fDR6 Include DR6 or not
612	*/
613	VMMR0DECL(int) CPUMR0LoadHyperDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
614	{
615	/* Save the host state. */
616	CPUMR0SaveHostDebugState(pVM, pVCpu);
617	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
618
619	/* Activate the guest state DR0-3; DR7 is left to the caller. */
620	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
621	if (CPUMIsGuestInLongModeEx(pCtx))
622	{
623	AssertFailed();
624	return VERR_NOT_IMPLEMENTED;
625	}
626	else
627	#endif
628	{
629	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
630	AssertFailed();
631	return VERR_NOT_IMPLEMENTED;
632	#else
633	ASMSetDR0(CPUMGetHyperDR0(pVCpu));
634	ASMSetDR1(CPUMGetHyperDR1(pVCpu));
635	ASMSetDR2(CPUMGetHyperDR2(pVCpu));
636	ASMSetDR3(CPUMGetHyperDR3(pVCpu));
637	#endif
638	if (fDR6)
639	ASMSetDR6(CPUMGetHyperDR6(pVCpu));
640	}
641
642	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HYPER;
643	return VINF_SUCCESS;
644	}
645
646
647	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
648	/**
649	* Worker for cpumR0MapLocalApics. Check each CPU for a present Local APIC.
650	* Play safe and treat each CPU separate.
651	*/
652	static void cpumR0MapLocalApicWorker(RTCPUID idCpu, void pvUser1, void pvUser2)
653	{
654	uint32_t u32MaxIdx;
655	uint32_t u32EBX, u32ECX, u32EDX;
656	int iCpu = RTMpCpuIdToSetIndex(idCpu);
657	Assert(iCpu < RTCPUSET_MAX_CPUS);
658	ASMCpuId(0, &u32MaxIdx, &u32EBX, &u32ECX, &u32EDX);
659	if ( ( ( u32EBX == X86_CPUID_VENDOR_INTEL_EBX
660	&& u32ECX == X86_CPUID_VENDOR_INTEL_ECX
661	&& u32EDX == X86_CPUID_VENDOR_INTEL_EDX)
662	\|\| ( u32EBX == X86_CPUID_VENDOR_AMD_EBX
663	&& u32ECX == X86_CPUID_VENDOR_AMD_ECX
664	&& u32EDX == X86_CPUID_VENDOR_AMD_EDX))
665	&& u32MaxIdx >= 1)
666	{
667	ASMCpuId(1, &u32MaxIdx, &u32EBX, &u32ECX, &u32EDX);
668	if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
669	&& (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
670	{
671	uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
672	uint32_t u32MaxExtIdx;
673	/* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
674	uint64_t u64Mask = UINT64_C(0x0000000ffffff000);
675	ASMCpuId(0x80000000, &u32MaxExtIdx, &u32EBX, &u32ECX, &u32EDX);
676	if ( u32MaxExtIdx >= 0x80000008
677	&& u32MaxExtIdx < 0x8000ffff)
678	{
679	uint32_t u32PhysBits;
680	ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
681	u32PhysBits &= 0xff;
682	u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
683	}
684	g_aLApics[iCpu].fEnabled = true;
685	g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
686	}
687	}
688	}
689
690
691	/**
692	* Map the MMIO page of each local APIC in the system.
693	*/
694	static int cpumR0MapLocalApics(void)
695	{
696	int rc = RTMpOnAll(cpumR0MapLocalApicWorker, NULL, NULL);
697	for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
698	{
699	if (g_aLApics[iCpu].fEnabled)
700	{
701	rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
702	PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
703	if (RT_SUCCESS(rc))
704	rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void*)-1,
705	PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
706	if (RT_SUCCESS(rc))
707	{
708	void *pApicBase = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
709	uint32_t ApicVersion = ApicRegRead(pApicBase, APIC_REG_VERSION);
710	/*
711	* 0x0X 82489 external APIC
712	* 0x1X Local APIC
713	* 0x2X..0xFF reserved
714	*/
715	if ((APIC_REG_VERSION_GET_VER(ApicVersion) & 0xF0) != 0x10)
716	{
717	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
718	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
719	g_aLApics[iCpu].fEnabled = false;
720	continue;
721	}
722	g_aLApics[iCpu].fHasThermal = APIC_REG_VERSION_GET_MAX_LVT(ApicVersion) >= 5;
723	g_aLApics[iCpu].pv = pApicBase;
724	}
725	}
726	}
727	if (RT_FAILURE(rc))
728	{
729	cpumR0UnmapLocalApics();
730	return rc;
731	}
732
733	return VINF_SUCCESS;
734	}
735
736
737	/**
738	* Unmap the Local APIC of all host CPUs.
739	*/
740	static void cpumR0UnmapLocalApics(void)
741	{
742	for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
743	{
744	if (g_aLApics[iCpu].pv)
745	{
746	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
747	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
748	g_aLApics[iCpu].fEnabled = false;
749	g_aLApics[iCpu].pv = NULL;
750	}
751	}
752	}
753
754
755	/**
756	* Write the Local APIC mapping address of the current host CPU to CPUM to be
757	* able to access the APIC registers in the raw mode switcher for disabling/
758	* re-enabling the NMI. Must be called with disabled preemption or disabled
759	* interrupts!
760	*
761	* @param pVM VM handle.
762	* @param idHostCpu The ID of the current host CPU.
763	*/
764	VMMR0DECL(void) CPUMR0SetLApic(PVM pVM, RTCPUID idHostCpu)
765	{
766	pVM->cpum.s.pvApicBase = g_aLApics[RTMpCpuIdToSetIndex(idHostCpu)].pv;
767	}
768
769	#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 33936

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