VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 57211

Last change on this file since 57211 was 55062, checked in by vboxsync, 10 years ago

Remove CPUFeatures and CPUFeaturesExt from CPUM, use HostFeatures instead. Extended HostFeatures.

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File size: 35.8 KB
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1/* $Id: CPUMR0.cpp 55062 2015-04-01 00:45:12Z vboxsync $ */
2/** @file
3 * CPUM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include "CPUMInternal.h"
25#include <VBox/vmm/vm.h>
26#include <VBox/err.h>
27#include <VBox/log.h>
28#include <VBox/vmm/hm.h>
29#include <iprt/assert.h>
30#include <iprt/asm-amd64-x86.h>
31#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
32# include <iprt/mem.h>
33# include <iprt/memobj.h>
34# include <VBox/apic.h>
35#endif
36#include <iprt/x86.h>
37
38
39/*******************************************************************************
40* Structures and Typedefs *
41*******************************************************************************/
42#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
43/**
44 * Local APIC mappings.
45 */
46typedef struct CPUMHOSTLAPIC
47{
48 /** Indicates that the entry is in use and have valid data. */
49 bool fEnabled;
50 /** Whether it's operating in X2APIC mode (EXTD). */
51 bool fX2Apic;
52 /** The APIC version number. */
53 uint32_t uVersion;
54 /** The physical address of the APIC registers. */
55 RTHCPHYS PhysBase;
56 /** The memory object entering the physical address. */
57 RTR0MEMOBJ hMemObj;
58 /** The mapping object for hMemObj. */
59 RTR0MEMOBJ hMapObj;
60 /** The mapping address APIC registers.
61 * @remarks Different CPUs may use the same physical address to map their
62 * APICs, so this pointer is only valid when on the CPU owning the
63 * APIC. */
64 void *pv;
65} CPUMHOSTLAPIC;
66#endif
67
68
69/*******************************************************************************
70* Global Variables *
71*******************************************************************************/
72#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
73static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
74#endif
75
76/**
77 * CPUID bits to unify among all cores.
78 */
79static struct
80{
81 uint32_t uLeaf; /**< Leaf to check. */
82 uint32_t uEcx; /**< which bits in ecx to unify between CPUs. */
83 uint32_t uEdx; /**< which bits in edx to unify between CPUs. */
84}
85const g_aCpuidUnifyBits[] =
86{
87 {
88 0x00000001,
89 X86_CPUID_FEATURE_ECX_CX16 | X86_CPUID_FEATURE_ECX_MONITOR,
90 X86_CPUID_FEATURE_EDX_CX8
91 }
92};
93
94
95
96/*******************************************************************************
97* Internal Functions *
98*******************************************************************************/
99#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
100static int cpumR0MapLocalApics(void);
101static void cpumR0UnmapLocalApics(void);
102#endif
103static int cpumR0SaveHostDebugState(PVMCPU pVCpu);
104
105
106/**
107 * Does the Ring-0 CPU initialization once during module load.
108 * XXX Host-CPU hot-plugging?
109 */
110VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
111{
112 int rc = VINF_SUCCESS;
113#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
114 rc = cpumR0MapLocalApics();
115#endif
116 return rc;
117}
118
119
120/**
121 * Terminate the module.
122 */
123VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
124{
125#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
126 cpumR0UnmapLocalApics();
127#endif
128 return VINF_SUCCESS;
129}
130
131
132/**
133 *
134 *
135 * Check the CPUID features of this particular CPU and disable relevant features
136 * for the guest which do not exist on this CPU. We have seen systems where the
137 * X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
138 * @bugref{5436}.
139 *
140 * @note This function might be called simultaneously on more than one CPU!
141 *
142 * @param idCpu The identifier for the CPU the function is called on.
143 * @param pvUser1 Pointer to the VM structure.
144 * @param pvUser2 Ignored.
145 */
146static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void *pvUser1, void *pvUser2)
147{
148 PVM pVM = (PVM)pvUser1;
149 PCPUM pCPUM = &pVM->cpum.s;
150
151 NOREF(idCpu); NOREF(pvUser2);
152 for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
153 {
154 /* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
155 necessarily in the VM process context. So, we using the
156 legacy arrays as temporary storage. */
157
158 uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
159 PCPUMCPUID pLegacyLeaf;
160 if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
161 pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
162 else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
163 pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
164 else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
165 pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
166 else
167 continue;
168
169 uint32_t eax, ebx, ecx, edx;
170 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
171
172 ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx | ~g_aCpuidUnifyBits[i].uEcx);
173 ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx | ~g_aCpuidUnifyBits[i].uEdx);
174 }
175}
176
177
178/**
179 * Does Ring-0 CPUM initialization.
180 *
181 * This is mainly to check that the Host CPU mode is compatible
182 * with VBox.
183 *
184 * @returns VBox status code.
185 * @param pVM Pointer to the VM.
186 */
187VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM)
188{
189 LogFlow(("CPUMR0Init: %p\n", pVM));
190
191 /*
192 * Check CR0 & CR4 flags.
193 */
194 uint32_t u32CR0 = ASMGetCR0();
195 if ((u32CR0 & (X86_CR0_PE | X86_CR0_PG)) != (X86_CR0_PE | X86_CR0_PG)) /* a bit paranoid perhaps.. */
196 {
197 Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
198 return VERR_UNSUPPORTED_CPU_MODE;
199 }
200
201 /*
202 * Check for sysenter and syscall usage.
203 */
204 if (ASMHasCpuId())
205 {
206 /*
207 * SYSENTER/SYSEXIT
208 *
209 * Intel docs claim you should test both the flag and family, model &
210 * stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
211 * but don't support it. AMD CPUs may support this feature in legacy
212 * mode, they've banned it from long mode. Since we switch to 32-bit
213 * mode when entering raw-mode context the feature would become
214 * accessible again on AMD CPUs, so we have to check regardless of
215 * host bitness.
216 */
217 uint32_t u32CpuVersion;
218 uint32_t u32Dummy;
219 uint32_t fFeatures;
220 ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
221 uint32_t const u32Family = u32CpuVersion >> 8;
222 uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
223 uint32_t const u32Stepping = u32CpuVersion & 0xF;
224 if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
225 && ( u32Family != 6 /* (> pentium pro) */
226 || u32Model >= 3
227 || u32Stepping >= 3
228 || !ASMIsIntelCpu())
229 )
230 {
231 /*
232 * Read the MSR and see if it's in use or not.
233 */
234 uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
235 if (u32)
236 {
237 pVM->cpum.s.fHostUseFlags |= CPUM_USE_SYSENTER;
238 Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
239 }
240 }
241
242 /*
243 * SYSCALL/SYSRET
244 *
245 * This feature is indicated by the SEP bit returned in EDX by CPUID
246 * function 0x80000001. Intel CPUs only supports this feature in
247 * long mode. Since we're not running 64-bit guests in raw-mode there
248 * are no issues with 32-bit intel hosts.
249 */
250 uint32_t cExt = 0;
251 ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
252 if (ASMIsValidExtRange(cExt))
253 {
254 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
255 if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
256 {
257#ifdef RT_ARCH_X86
258# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
259 if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
260# else
261 if (!ASMIsIntelCpu())
262# endif
263#endif
264 {
265 uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
266 if (fEfer & MSR_K6_EFER_SCE)
267 {
268 pVM->cpum.s.fHostUseFlags |= CPUM_USE_SYSCALL;
269 Log(("CPUMR0Init: host uses syscall\n"));
270 }
271 }
272 }
273 }
274
275 /*
276 * Unify/cross check some CPUID feature bits on all available CPU cores
277 * and threads. We've seen CPUs where the monitor support differed.
278 *
279 * Because the hyper heap isn't always mapped into ring-0, we cannot
280 * access it from a RTMpOnAll callback. We use the legacy CPUID arrays
281 * as temp ring-0 accessible memory instead, ASSUMING that they're all
282 * up to date when we get here.
283 */
284 RTMpOnAll(cpumR0CheckCpuid, pVM, NULL);
285
286 for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
287 {
288 bool fIgnored;
289 uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
290 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
291 if (pLeaf)
292 {
293 PCPUMCPUID pLegacyLeaf;
294 if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
295 pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
296 else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
297 pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
298 else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
299 pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
300 else
301 continue;
302
303 pLeaf->uEcx = pLegacyLeaf->uEcx;
304 pLeaf->uEdx = pLegacyLeaf->uEdx;
305 }
306 }
307
308 }
309
310
311 /*
312 * Check if debug registers are armed.
313 * This ASSUMES that DR7.GD is not set, or that it's handled transparently!
314 */
315 uint32_t u32DR7 = ASMGetDR7();
316 if (u32DR7 & X86_DR7_ENABLED_MASK)
317 {
318 for (VMCPUID i = 0; i < pVM->cCpus; i++)
319 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
320 Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
321 }
322
323 return VINF_SUCCESS;
324}
325
326
327/**
328 * Trap handler for device-not-available fault (#NM).
329 * Device not available, FP or (F)WAIT instruction.
330 *
331 * @returns VBox status code.
332 * @retval VINF_SUCCESS if the guest FPU state is loaded.
333 * @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
334 *
335 * @param pVM Pointer to the VM.
336 * @param pVCpu Pointer to the VMCPU.
337 * @param pCtx Pointer to the guest-CPU context.
338 */
339VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
340{
341 Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
342 Assert(ASMGetCR4() & X86_CR4_OSFXSR);
343
344 /* If the FPU state has already been loaded, then it's a guest trap. */
345 if (CPUMIsGuestFPUStateActive(pVCpu))
346 {
347 Assert( ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS))
348 || ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS | X86_CR0_EM)));
349 return VINF_EM_RAW_GUEST_TRAP;
350 }
351
352 /*
353 * There are two basic actions:
354 * 1. Save host fpu and restore guest fpu.
355 * 2. Generate guest trap.
356 *
357 * When entering the hypervisor we'll always enable MP (for proper wait
358 * trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
359 * is taken from the guest OS in order to get proper SSE handling.
360 *
361 *
362 * Actions taken depending on the guest CR0 flags:
363 *
364 * 3 2 1
365 * TS | EM | MP | FPUInstr | WAIT :: VMM Action
366 * ------------------------------------------------------------------------
367 * 0 | 0 | 0 | Exec | Exec :: Clear TS & MP, Save HC, Load GC.
368 * 0 | 0 | 1 | Exec | Exec :: Clear TS, Save HC, Load GC.
369 * 0 | 1 | 0 | #NM | Exec :: Clear TS & MP, Save HC, Load GC.
370 * 0 | 1 | 1 | #NM | Exec :: Clear TS, Save HC, Load GC.
371 * 1 | 0 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
372 * 1 | 0 | 1 | #NM | #NM :: Go to guest taking trap there.
373 * 1 | 1 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
374 * 1 | 1 | 1 | #NM | #NM :: Go to guest taking trap there.
375 */
376
377 switch (pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
378 {
379 case X86_CR0_MP | X86_CR0_TS:
380 case X86_CR0_MP | X86_CR0_TS | X86_CR0_EM:
381 return VINF_EM_RAW_GUEST_TRAP;
382 default:
383 break;
384 }
385
386 return CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
387}
388
389
390/**
391 * Saves the host-FPU/XMM state and loads the guest-FPU state into the CPU.
392 *
393 * @returns VBox status code.
394 *
395 * @param pVM Pointer to the VM.
396 * @param pVCpu Pointer to the VMCPU.
397 * @param pCtx Pointer to the guest-CPU context.
398 */
399VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
400{
401 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
402#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
403 if (CPUMIsGuestInLongModeEx(pCtx))
404 {
405 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
406
407 /* Save the host state and record the fact (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM). */
408 cpumR0SaveHostFPUState(&pVCpu->cpum.s);
409
410 /* Restore the state on entry as we need to be in 64-bit mode to access the full state. */
411 pVCpu->cpum.s.fUseFlags |= CPUM_SYNC_FPU_STATE;
412 }
413 else
414#endif
415 {
416 NOREF(pCtx);
417 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
418 /** @todo Move the FFXR handling down into
419 * cpumR0SaveHostRestoreGuestFPUState to optimize the
420 * VBOX_WITH_KERNEL_USING_XMM handling. */
421 /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
422 uint64_t uHostEfer = 0;
423 bool fRestoreEfer = false;
424 if (pVM->cpum.s.HostFeatures.fLeakyFxSR)
425 {
426 /** @todo r=ramshankar: Can't we used a cached value here
427 * instead of reading the MSR? host EFER doesn't usually
428 * change. */
429 uHostEfer = ASMRdMsr(MSR_K6_EFER);
430 if (uHostEfer & MSR_K6_EFER_FFXSR)
431 {
432 ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
433 pVCpu->cpum.s.fUseFlags |= CPUM_USED_MANUAL_XMM_RESTORE;
434 fRestoreEfer = true;
435 }
436 }
437
438 /* Do the job and record that we've switched FPU state. */
439 cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
440
441 /* Restore EFER. */
442 if (fRestoreEfer)
443 ASMWrMsr(MSR_K6_EFER, uHostEfer);
444 }
445
446 Assert((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM)) == (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM));
447 return VINF_SUCCESS;
448}
449
450
451/**
452 * Save guest FPU/XMM state
453 *
454 * @returns VBox status code.
455 * @param pVM Pointer to the VM.
456 * @param pVCpu Pointer to the VMCPU.
457 * @param pCtx Pointer to the guest CPU context.
458 */
459VMMR0_INT_DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
460{
461 Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
462 Assert(ASMGetCR4() & X86_CR4_OSFXSR);
463 AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
464 NOREF(pVM); NOREF(pCtx);
465
466#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
467 if (CPUMIsGuestInLongModeEx(pCtx))
468 {
469 if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
470 {
471 HMR0SaveFPUState(pVM, pVCpu, pCtx);
472 cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
473 }
474 /* else nothing to do; we didn't perform a world switch */
475 }
476 else
477#endif
478 {
479#ifdef VBOX_WITH_KERNEL_USING_XMM
480 /*
481 * We've already saved the XMM registers in the assembly wrapper, so
482 * we have to save them before saving the entire FPU state and put them
483 * back afterwards.
484 */
485 /** @todo This could be skipped if MSR_K6_EFER_FFXSR is set, but
486 * I'm not able to test such an optimization tonight.
487 * We could just all this in assembly. */
488 uint128_t aGuestXmmRegs[16];
489 memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.CTX_SUFF(pXState)->x87.aXMM[0], sizeof(aGuestXmmRegs));
490#endif
491
492 /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
493 uint64_t uHostEfer = 0;
494 bool fRestoreEfer = false;
495 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE)
496 {
497 uHostEfer = ASMRdMsr(MSR_K6_EFER);
498 if (uHostEfer & MSR_K6_EFER_FFXSR)
499 {
500 ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
501 fRestoreEfer = true;
502 }
503 }
504
505 cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
506
507 /* Restore EFER MSR */
508 if (fRestoreEfer)
509 ASMWrMsr(MSR_K6_EFER, uHostEfer | MSR_K6_EFER_FFXSR);
510
511#ifdef VBOX_WITH_KERNEL_USING_XMM
512 memcpy(&pVCpu->cpum.s.Guest.CTX_SUFF(pXState)->x87.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
513#endif
514 }
515
516 pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU | CPUM_SYNC_FPU_STATE | CPUM_USED_MANUAL_XMM_RESTORE);
517 return VINF_SUCCESS;
518}
519
520
521/**
522 * Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
523 * DR7 with safe values.
524 *
525 * @returns VBox status code.
526 * @param pVCpu Pointer to the VMCPU.
527 */
528static int cpumR0SaveHostDebugState(PVMCPU pVCpu)
529{
530 /*
531 * Save the host state.
532 */
533#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
534 AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
535 cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
536#else
537 pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
538 pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
539 pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
540 pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
541#endif
542 pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
543 /** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
544 pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
545
546 /* Preemption paranoia. */
547 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
548
549 /*
550 * Make sure DR7 is harmless or else we could trigger breakpoints when
551 * load guest or hypervisor DRx values later.
552 */
553 if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
554 ASMSetDR7(X86_DR7_INIT_VAL);
555
556 return VINF_SUCCESS;
557}
558
559
560/**
561 * Saves the guest DRx state residing in host registers and restore the host
562 * register values.
563 *
564 * The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
565 * since it's assumed that we're shadowing the guest DRx register values
566 * accurately when using the combined hypervisor debug register values
567 * (CPUMR0LoadHyperDebugState).
568 *
569 * @returns true if either guest or hypervisor debug registers were loaded.
570 * @param pVCpu The cross context CPU structure for the calling EMT.
571 * @param fDr6 Whether to include DR6 or not.
572 * @thread EMT(pVCpu)
573 */
574VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6)
575{
576 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
577 bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER));
578
579 /*
580 * Do we need to save the guest DRx registered loaded into host registers?
581 * (DR7 and DR6 (if fDr6 is true) are left to the caller.)
582 */
583 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
584 {
585#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
586 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
587 {
588 uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
589 HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
590 if (!fDr6)
591 pVCpu->cpum.s.Guest.dr[6] = uDr6;
592 }
593 else
594#endif
595 {
596#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
597 cpumR0SaveDRx(&pVCpu->cpum.s.Guest.dr[0]);
598#else
599 pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
600 pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
601 pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
602 pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
603#endif
604 if (fDr6)
605 pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
606 }
607 }
608 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~( CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER
609 | CPUM_SYNC_DEBUG_REGS_GUEST | CPUM_SYNC_DEBUG_REGS_HYPER));
610
611 /*
612 * Restore the host's debug state. DR0-3, DR6 and only then DR7!
613 */
614 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
615 {
616 /* A bit of paranoia first... */
617 uint64_t uCurDR7 = ASMGetDR7();
618 if (uCurDR7 != X86_DR7_INIT_VAL)
619 ASMSetDR7(X86_DR7_INIT_VAL);
620
621#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
622 AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
623 cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
624#else
625 ASMSetDR0(pVCpu->cpum.s.Host.dr0);
626 ASMSetDR1(pVCpu->cpum.s.Host.dr1);
627 ASMSetDR2(pVCpu->cpum.s.Host.dr2);
628 ASMSetDR3(pVCpu->cpum.s.Host.dr3);
629#endif
630 /** @todo consider only updating if they differ, esp. DR6. Need to figure how
631 * expensive DRx reads are over DRx writes. */
632 ASMSetDR6(pVCpu->cpum.s.Host.dr6);
633 ASMSetDR7(pVCpu->cpum.s.Host.dr7);
634
635 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
636 }
637
638 return fDrXLoaded;
639}
640
641
642/**
643 * Saves the guest DRx state if it resides host registers.
644 *
645 * This does NOT clear any use flags, so the host registers remains loaded with
646 * the guest DRx state upon return. The purpose is only to make sure the values
647 * in the CPU context structure is up to date.
648 *
649 * @returns true if the host registers contains guest values, false if not.
650 * @param pVCpu The cross context CPU structure for the calling EMT.
651 * @param fDr6 Whether to include DR6 or not.
652 * @thread EMT(pVCpu)
653 */
654VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6)
655{
656 /*
657 * Do we need to save the guest DRx registered loaded into host registers?
658 * (DR7 and DR6 (if fDr6 is true) are left to the caller.)
659 */
660 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
661 {
662#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
663 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
664 {
665 uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
666 HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
667 if (!fDr6)
668 pVCpu->cpum.s.Guest.dr[6] = uDr6;
669 }
670 else
671#endif
672 {
673#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
674 cpumR0SaveDRx(&pVCpu->cpum.s.Guest.dr[0]);
675#else
676 pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
677 pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
678 pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
679 pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
680#endif
681 if (fDr6)
682 pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
683 }
684 return true;
685 }
686 return false;
687}
688
689
690/**
691 * Lazily sync in the debug state.
692 *
693 * @param pVCpu The cross context CPU structure for the calling EMT.
694 * @param fDr6 Whether to include DR6 or not.
695 * @thread EMT(pVCpu)
696 */
697VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6)
698{
699 /*
700 * Save the host state and disarm all host BPs.
701 */
702 cpumR0SaveHostDebugState(pVCpu);
703 Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
704
705 /*
706 * Activate the guest state DR0-3.
707 * DR7 and DR6 (if fDr6 is true) are left to the caller.
708 */
709#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
710 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
711 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_GUEST); /* Postpone it to the world switch. */
712 else
713#endif
714 {
715#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
716 cpumR0LoadDRx(&pVCpu->cpum.s.Guest.dr[0]);
717#else
718 ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
719 ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
720 ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
721 ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
722#endif
723 if (fDr6)
724 ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
725
726 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
727 }
728}
729
730
731/**
732 * Lazily sync in the hypervisor debug state
733 *
734 * @returns VBox status code.
735 * @param pVCpu The cross context CPU structure for the calling EMT.
736 * @param fDr6 Whether to include DR6 or not.
737 * @thread EMT(pVCpu)
738 */
739VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6)
740{
741 /*
742 * Save the host state and disarm all host BPs.
743 */
744 cpumR0SaveHostDebugState(pVCpu);
745 Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
746
747 /*
748 * Make sure the hypervisor values are up to date.
749 */
750 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */, true);
751
752 /*
753 * Activate the guest state DR0-3.
754 * DR7 and DR6 (if fDr6 is true) are left to the caller.
755 */
756#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
757 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
758 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_HYPER); /* Postpone it. */
759 else
760#endif
761 {
762#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
763 cpumR0LoadDRx(&pVCpu->cpum.s.Hyper.dr[0]);
764#else
765 ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
766 ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
767 ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
768 ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
769#endif
770 if (fDr6)
771 ASMSetDR6(X86_DR6_INIT_VAL);
772
773 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
774 }
775}
776
777#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
778
779/**
780 * Per-CPU callback that probes the CPU for APIC support.
781 *
782 * @param idCpu The identifier for the CPU the function is called on.
783 * @param pvUser1 Ignored.
784 * @param pvUser2 Ignored.
785 */
786static DECLCALLBACK(void) cpumR0MapLocalApicCpuProber(RTCPUID idCpu, void *pvUser1, void *pvUser2)
787{
788 NOREF(pvUser1); NOREF(pvUser2);
789 int iCpu = RTMpCpuIdToSetIndex(idCpu);
790 AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
791
792 /*
793 * Check for APIC support.
794 */
795 uint32_t uMaxLeaf, u32EBX, u32ECX, u32EDX;
796 ASMCpuId(0, &uMaxLeaf, &u32EBX, &u32ECX, &u32EDX);
797 if ( ( ASMIsIntelCpuEx(u32EBX, u32ECX, u32EDX)
798 || ASMIsAmdCpuEx(u32EBX, u32ECX, u32EDX)
799 || ASMIsViaCentaurCpuEx(u32EBX, u32ECX, u32EDX))
800 && ASMIsValidStdRange(uMaxLeaf))
801 {
802 uint32_t uDummy;
803 ASMCpuId(1, &uDummy, &u32EBX, &u32ECX, &u32EDX);
804 if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
805 && (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
806 {
807 /*
808 * Safe to access the MSR. Read it and calc the BASE (a little complicated).
809 */
810 uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
811 uint64_t u64Mask = MSR_IA32_APICBASE_BASE_MIN;
812
813 /* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
814 uint32_t uMaxExtLeaf;
815 ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX);
816 if ( uMaxExtLeaf >= UINT32_C(0x80000008)
817 && ASMIsValidExtRange(uMaxExtLeaf))
818 {
819 uint32_t u32PhysBits;
820 ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
821 u32PhysBits &= 0xff;
822 u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
823 }
824
825 AssertCompile(sizeof(g_aLApics[iCpu].PhysBase) == sizeof(u64ApicBase));
826 g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
827 g_aLApics[iCpu].fEnabled = RT_BOOL(u64ApicBase & MSR_IA32_APICBASE_EN);
828 g_aLApics[iCpu].fX2Apic = (u64ApicBase & (MSR_IA32_APICBASE_EXTD | MSR_IA32_APICBASE_EN))
829 == (MSR_IA32_APICBASE_EXTD | MSR_IA32_APICBASE_EN);
830 }
831 }
832}
833
834
835
836/**
837 * Per-CPU callback that verifies our APIC expectations.
838 *
839 * @param idCpu The identifier for the CPU the function is called on.
840 * @param pvUser1 Ignored.
841 * @param pvUser2 Ignored.
842 */
843static DECLCALLBACK(void) cpumR0MapLocalApicCpuChecker(RTCPUID idCpu, void *pvUser1, void *pvUser2)
844{
845 NOREF(pvUser1); NOREF(pvUser2);
846
847 int iCpu = RTMpCpuIdToSetIndex(idCpu);
848 AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
849 if (!g_aLApics[iCpu].fEnabled)
850 return;
851
852 /*
853 * 0x0X 82489 external APIC
854 * 0x1X Local APIC
855 * 0x2X..0xFF reserved
856 */
857 uint32_t uApicVersion;
858 if (g_aLApics[iCpu].fX2Apic)
859 uApicVersion = ApicX2RegRead32(APIC_REG_VERSION);
860 else
861 uApicVersion = ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_VERSION);
862 if ((APIC_REG_VERSION_GET_VER(uApicVersion) & 0xF0) == 0x10)
863 {
864 g_aLApics[iCpu].uVersion = uApicVersion;
865
866#if 0 /* enable if you need it. */
867 if (g_aLApics[iCpu].fX2Apic)
868 SUPR0Printf("CPUM: X2APIC %02u - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
869 iCpu, uApicVersion,
870 ApicX2RegRead32(APIC_REG_LVT_LINT0), ApicX2RegRead32(APIC_REG_LVT_LINT1),
871 ApicX2RegRead32(APIC_REG_LVT_PC), ApicX2RegRead32(APIC_REG_LVT_THMR),
872 ApicX2RegRead32(APIC_REG_LVT_CMCI));
873 else
874 {
875 SUPR0Printf("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
876 iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, uApicVersion,
877 ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT0), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT1),
878 ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_PC), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_THMR),
879 ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_CMCI));
880 if (uApicVersion & 0x80000000)
881 {
882 uint32_t uExtFeatures = ApicRegRead(g_aLApics[iCpu].pv, 0x400);
883 uint32_t cEiLvt = (uExtFeatures >> 16) & 0xff;
884 SUPR0Printf("CPUM: APIC %02u: ExtSpace available. extfeat=%08x eilvt[0..3]=%08x %08x %08x %08x\n",
885 iCpu,
886 ApicRegRead(g_aLApics[iCpu].pv, 0x400),
887 cEiLvt >= 1 ? ApicRegRead(g_aLApics[iCpu].pv, 0x500) : 0,
888 cEiLvt >= 2 ? ApicRegRead(g_aLApics[iCpu].pv, 0x510) : 0,
889 cEiLvt >= 3 ? ApicRegRead(g_aLApics[iCpu].pv, 0x520) : 0,
890 cEiLvt >= 4 ? ApicRegRead(g_aLApics[iCpu].pv, 0x530) : 0);
891 }
892 }
893#endif
894 }
895 else
896 {
897 g_aLApics[iCpu].fEnabled = false;
898 g_aLApics[iCpu].fX2Apic = false;
899 SUPR0Printf("VBox/CPUM: Unsupported APIC version %#x (iCpu=%d)\n", uApicVersion, iCpu);
900 }
901}
902
903
904/**
905 * Map the MMIO page of each local APIC in the system.
906 */
907static int cpumR0MapLocalApics(void)
908{
909 /*
910 * Check that we'll always stay within the array bounds.
911 */
912 if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
913 {
914 LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
915 return VERR_TOO_MANY_CPUS;
916 }
917
918 /*
919 * Create mappings for all online CPUs we think have legacy APICs.
920 */
921 int rc = RTMpOnAll(cpumR0MapLocalApicCpuProber, NULL, NULL);
922
923 for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
924 {
925 if (g_aLApics[iCpu].fEnabled && !g_aLApics[iCpu].fX2Apic)
926 {
927 rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
928 PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
929 if (RT_SUCCESS(rc))
930 {
931 rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
932 PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
933 if (RT_SUCCESS(rc))
934 {
935 g_aLApics[iCpu].pv = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
936 continue;
937 }
938 RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
939 }
940 g_aLApics[iCpu].fEnabled = false;
941 }
942 g_aLApics[iCpu].pv = NULL;
943 }
944
945 /*
946 * Check the APICs.
947 */
948 if (RT_SUCCESS(rc))
949 rc = RTMpOnAll(cpumR0MapLocalApicCpuChecker, NULL, NULL);
950
951 if (RT_FAILURE(rc))
952 {
953 cpumR0UnmapLocalApics();
954 return rc;
955 }
956
957#ifdef LOG_ENABLED
958 /*
959 * Log the result (pretty useless, requires enabling CPUM in VBoxDrv
960 * and !VBOX_WITH_R0_LOGGING).
961 */
962 if (LogIsEnabled())
963 {
964 uint32_t cEnabled = 0;
965 uint32_t cX2Apics = 0;
966 for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
967 if (g_aLApics[iCpu].fEnabled)
968 {
969 cEnabled++;
970 cX2Apics += g_aLApics[iCpu].fX2Apic;
971 }
972 Log(("CPUM: %u APICs, %u X2APICs\n", cEnabled, cX2Apics));
973 }
974#endif
975
976 return VINF_SUCCESS;
977}
978
979
980/**
981 * Unmap the Local APIC of all host CPUs.
982 */
983static void cpumR0UnmapLocalApics(void)
984{
985 for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
986 {
987 if (g_aLApics[iCpu].pv)
988 {
989 RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
990 RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
991 g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
992 g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
993 g_aLApics[iCpu].fEnabled = false;
994 g_aLApics[iCpu].fX2Apic = false;
995 g_aLApics[iCpu].pv = NULL;
996 }
997 }
998}
999
1000
1001/**
1002 * Updates CPUMCPU::pvApicBase and CPUMCPU::fX2Apic prior to world switch.
1003 *
1004 * Writes the Local APIC mapping address of the current host CPU to CPUMCPU so
1005 * the world switchers can access the APIC registers for the purpose of
1006 * disabling and re-enabling the NMIs. Must be called with disabled preemption
1007 * or disabled interrupts!
1008 *
1009 * @param pVCpu Pointer to the cross context CPU structure of the
1010 * calling EMT.
1011 * @param iHostCpuSet The CPU set index of the current host CPU.
1012 */
1013VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet)
1014{
1015 Assert(iHostCpuSet <= RT_ELEMENTS(g_aLApics));
1016 pVCpu->cpum.s.pvApicBase = g_aLApics[iHostCpuSet].pv;
1017 pVCpu->cpum.s.fX2Apic = g_aLApics[iHostCpuSet].fX2Apic;
1018// Log6(("CPUMR0SetLApic: pvApicBase=%p fX2Apic=%d\n", g_aLApics[idxCpu].pv, g_aLApics[idxCpu].fX2Apic));
1019}
1020
1021#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */
1022
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