CPUMR0.cpp@ 57493

Last change on this file since 57493 was 57446, checked in by vboxsync, 9 years ago
VMM: Removing VBOX_WITH_HYBRID_32BIT_KERNEL and other 32-bit darwin fun.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 35.2 KB

Line
1	/* $Id: CPUMR0.cpp 57446 2015-08-18 17:33:53Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/err.h>
27	#include <VBox/log.h>
28	#include <VBox/vmm/hm.h>
29	#include <iprt/assert.h>
30	#include <iprt/asm-amd64-x86.h>
31	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
32	# include <iprt/mem.h>
33	# include <iprt/memobj.h>
34	# include <VBox/apic.h>
35	#endif
36	#include <iprt/x86.h>
37
38
39	/*********************************************************************************************************************************
40	* Structures and Typedefs *
41	*********************************************************************************************************************************/
42	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
43	/**
44	* Local APIC mappings.
45	*/
46	typedef struct CPUMHOSTLAPIC
47	{
48	/** Indicates that the entry is in use and have valid data. */
49	bool fEnabled;
50	/** Whether it's operating in X2APIC mode (EXTD). */
51	bool fX2Apic;
52	/** The APIC version number. */
53	uint32_t uVersion;
54	/** The physical address of the APIC registers. */
55	RTHCPHYS PhysBase;
56	/** The memory object entering the physical address. */
57	RTR0MEMOBJ hMemObj;
58	/** The mapping object for hMemObj. */
59	RTR0MEMOBJ hMapObj;
60	/** The mapping address APIC registers.
61	* @remarks Different CPUs may use the same physical address to map their
62	* APICs, so this pointer is only valid when on the CPU owning the
63	* APIC. */
64	void *pv;
65	} CPUMHOSTLAPIC;
66	#endif
67
68
69	/*********************************************************************************************************************************
70	* Global Variables *
71	*********************************************************************************************************************************/
72	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
73	static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
74	#endif
75
76	/**
77	* CPUID bits to unify among all cores.
78	*/
79	static struct
80	{
81	uint32_t uLeaf; /*< Leaf to check. /
82	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
83	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
84	}
85	const g_aCpuidUnifyBits[] =
86	{
87	{
88	0x00000001,
89	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
90	X86_CPUID_FEATURE_EDX_CX8
91	}
92	};
93
94
95
96	/*********************************************************************************************************************************
97	* Internal Functions *
98	*********************************************************************************************************************************/
99	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
100	static int cpumR0MapLocalApics(void);
101	static void cpumR0UnmapLocalApics(void);
102	#endif
103	static int cpumR0SaveHostDebugState(PVMCPU pVCpu);
104
105
106	/**
107	* Does the Ring-0 CPU initialization once during module load.
108	* XXX Host-CPU hot-plugging?
109	*/
110	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
111	{
112	int rc = VINF_SUCCESS;
113	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
114	rc = cpumR0MapLocalApics();
115	#endif
116	return rc;
117	}
118
119
120	/**
121	* Terminate the module.
122	*/
123	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
124	{
125	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
126	cpumR0UnmapLocalApics();
127	#endif
128	return VINF_SUCCESS;
129	}
130
131
132	/**
133	*
134	*
135	* Check the CPUID features of this particular CPU and disable relevant features
136	* for the guest which do not exist on this CPU. We have seen systems where the
137	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
138	* @bugref{5436}.
139	*
140	* @note This function might be called simultaneously on more than one CPU!
141	*
142	* @param idCpu The identifier for the CPU the function is called on.
143	* @param pvUser1 Pointer to the VM structure.
144	* @param pvUser2 Ignored.
145	*/
146	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
147	{
148	PVM pVM = (PVM)pvUser1;
149	PCPUM pCPUM = &pVM->cpum.s;
150
151	NOREF(idCpu); NOREF(pvUser2);
152	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
153	{
154	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
155	necessarily in the VM process context. So, we using the
156	legacy arrays as temporary storage. */
157
158	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
159	PCPUMCPUID pLegacyLeaf;
160	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
161	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
162	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
163	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
164	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
165	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
166	else
167	continue;
168
169	uint32_t eax, ebx, ecx, edx;
170	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
171
172	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
173	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
174	}
175	}
176
177
178	/**
179	* Does Ring-0 CPUM initialization.
180	*
181	* This is mainly to check that the Host CPU mode is compatible
182	* with VBox.
183	*
184	* @returns VBox status code.
185	* @param pVM Pointer to the VM.
186	*/
187	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM)
188	{
189	LogFlow(("CPUMR0Init: %p\n", pVM));
190
191	/*
192	* Check CR0 & CR4 flags.
193	*/
194	uint32_t u32CR0 = ASMGetCR0();
195	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
196	{
197	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
198	return VERR_UNSUPPORTED_CPU_MODE;
199	}
200
201	/*
202	* Check for sysenter and syscall usage.
203	*/
204	if (ASMHasCpuId())
205	{
206	/*
207	* SYSENTER/SYSEXIT
208	*
209	* Intel docs claim you should test both the flag and family, model &
210	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
211	* but don't support it. AMD CPUs may support this feature in legacy
212	* mode, they've banned it from long mode. Since we switch to 32-bit
213	* mode when entering raw-mode context the feature would become
214	* accessible again on AMD CPUs, so we have to check regardless of
215	* host bitness.
216	*/
217	uint32_t u32CpuVersion;
218	uint32_t u32Dummy;
219	uint32_t fFeatures;
220	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
221	uint32_t const u32Family = u32CpuVersion >> 8;
222	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
223	uint32_t const u32Stepping = u32CpuVersion & 0xF;
224	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
225	&& ( u32Family != 6 /* (> pentium pro) */
226	\|\| u32Model >= 3
227	\|\| u32Stepping >= 3
228	\|\| !ASMIsIntelCpu())
229	)
230	{
231	/*
232	* Read the MSR and see if it's in use or not.
233	*/
234	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
235	if (u32)
236	{
237	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
238	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
239	}
240	}
241
242	/*
243	* SYSCALL/SYSRET
244	*
245	* This feature is indicated by the SEP bit returned in EDX by CPUID
246	* function 0x80000001. Intel CPUs only supports this feature in
247	* long mode. Since we're not running 64-bit guests in raw-mode there
248	* are no issues with 32-bit intel hosts.
249	*/
250	uint32_t cExt = 0;
251	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
252	if (ASMIsValidExtRange(cExt))
253	{
254	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
255	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
256	{
257	#ifdef RT_ARCH_X86
258	if (!ASMIsIntelCpu())
259	#endif
260	{
261	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
262	if (fEfer & MSR_K6_EFER_SCE)
263	{
264	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
265	Log(("CPUMR0Init: host uses syscall\n"));
266	}
267	}
268	}
269	}
270
271	/*
272	* Unify/cross check some CPUID feature bits on all available CPU cores
273	* and threads. We've seen CPUs where the monitor support differed.
274	*
275	* Because the hyper heap isn't always mapped into ring-0, we cannot
276	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
277	* as temp ring-0 accessible memory instead, ASSUMING that they're all
278	* up to date when we get here.
279	*/
280	RTMpOnAll(cpumR0CheckCpuid, pVM, NULL);
281
282	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
283	{
284	bool fIgnored;
285	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
286	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
287	if (pLeaf)
288	{
289	PCPUMCPUID pLegacyLeaf;
290	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
291	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
292	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
293	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
294	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
295	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
296	else
297	continue;
298
299	pLeaf->uEcx = pLegacyLeaf->uEcx;
300	pLeaf->uEdx = pLegacyLeaf->uEdx;
301	}
302	}
303
304	}
305
306
307	/*
308	* Check if debug registers are armed.
309	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
310	*/
311	uint32_t u32DR7 = ASMGetDR7();
312	if (u32DR7 & X86_DR7_ENABLED_MASK)
313	{
314	for (VMCPUID i = 0; i < pVM->cCpus; i++)
315	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
316	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
317	}
318
319	return VINF_SUCCESS;
320	}
321
322
323	/**
324	* Trap handler for device-not-available fault (#NM).
325	* Device not available, FP or (F)WAIT instruction.
326	*
327	* @returns VBox status code.
328	* @retval VINF_SUCCESS if the guest FPU state is loaded.
329	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
330	*
331	* @param pVM Pointer to the VM.
332	* @param pVCpu Pointer to the VMCPU.
333	* @param pCtx Pointer to the guest-CPU context.
334	*/
335	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
336	{
337	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
338	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
339
340	/* If the FPU state has already been loaded, then it's a guest trap. */
341	if (CPUMIsGuestFPUStateActive(pVCpu))
342	{
343	Assert( ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
344	\|\| ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
345	return VINF_EM_RAW_GUEST_TRAP;
346	}
347
348	/*
349	* There are two basic actions:
350	* 1. Save host fpu and restore guest fpu.
351	* 2. Generate guest trap.
352	*
353	* When entering the hypervisor we'll always enable MP (for proper wait
354	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
355	* is taken from the guest OS in order to get proper SSE handling.
356	*
357	*
358	* Actions taken depending on the guest CR0 flags:
359	*
360	* 3 2 1
361	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
362	* ------------------------------------------------------------------------
363	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
364	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
365	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
366	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
367	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
368	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
369	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
370	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
371	*/
372
373	switch (pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
374	{
375	case X86_CR0_MP \| X86_CR0_TS:
376	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
377	return VINF_EM_RAW_GUEST_TRAP;
378	default:
379	break;
380	}
381
382	return CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
383	}
384
385
386	/**
387	* Saves the host-FPU/XMM state and loads the guest-FPU state into the CPU.
388	*
389	* @returns VBox status code.
390	*
391	* @param pVM Pointer to the VM.
392	* @param pVCpu Pointer to the VMCPU.
393	* @param pCtx Pointer to the guest-CPU context.
394	*/
395	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
396	{
397	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
398	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
399	if (CPUMIsGuestInLongModeEx(pCtx))
400	{
401	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
402
403	/* Save the host state and record the fact (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM). */
404	cpumR0SaveHostFPUState(&pVCpu->cpum.s);
405
406	/* Restore the state on entry as we need to be in 64-bit mode to access the full state. */
407	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
408	}
409	else
410	#endif
411	{
412	NOREF(pCtx);
413	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
414	/** @todo Move the FFXR handling down into
415	* cpumR0SaveHostRestoreGuestFPUState to optimize the
416	* VBOX_WITH_KERNEL_USING_XMM handling. */
417	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
418	uint64_t uHostEfer = 0;
419	bool fRestoreEfer = false;
420	if (pVM->cpum.s.HostFeatures.fLeakyFxSR)
421	{
422	/** @todo r=ramshankar: Can't we used a cached value here
423	* instead of reading the MSR? host EFER doesn't usually
424	* change. */
425	uHostEfer = ASMRdMsr(MSR_K6_EFER);
426	if (uHostEfer & MSR_K6_EFER_FFXSR)
427	{
428	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
429	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
430	fRestoreEfer = true;
431	}
432	}
433
434	/* Do the job and record that we've switched FPU state. */
435	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
436
437	/* Restore EFER. */
438	if (fRestoreEfer)
439	ASMWrMsr(MSR_K6_EFER, uHostEfer);
440	}
441
442	Assert((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM)) == (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM));
443	return VINF_SUCCESS;
444	}
445
446
447	/**
448	* Save guest FPU/XMM state
449	*
450	* @returns VBox status code.
451	* @param pVM Pointer to the VM.
452	* @param pVCpu Pointer to the VMCPU.
453	* @param pCtx Pointer to the guest CPU context.
454	*/
455	VMMR0_INT_DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
456	{
457	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
458	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
459	AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
460	NOREF(pVM); NOREF(pCtx);
461
462	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
463	if (CPUMIsGuestInLongModeEx(pCtx))
464	{
465	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
466	{
467	HMR0SaveFPUState(pVM, pVCpu, pCtx);
468	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
469	}
470	/* else nothing to do; we didn't perform a world switch */
471	}
472	else
473	#endif
474	{
475	#ifdef VBOX_WITH_KERNEL_USING_XMM
476	/*
477	* We've already saved the XMM registers in the assembly wrapper, so
478	* we have to save them before saving the entire FPU state and put them
479	* back afterwards.
480	*/
481	/** @todo This could be skipped if MSR_K6_EFER_FFXSR is set, but
482	* I'm not able to test such an optimization tonight.
483	* We could just all this in assembly. */
484	uint128_t aGuestXmmRegs[16];
485	memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.CTX_SUFF(pXState)->x87.aXMM[0], sizeof(aGuestXmmRegs));
486	#endif
487
488	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
489	uint64_t uHostEfer = 0;
490	bool fRestoreEfer = false;
491	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE)
492	{
493	uHostEfer = ASMRdMsr(MSR_K6_EFER);
494	if (uHostEfer & MSR_K6_EFER_FFXSR)
495	{
496	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
497	fRestoreEfer = true;
498	}
499	}
500
501	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
502
503	/* Restore EFER MSR */
504	if (fRestoreEfer)
505	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
506
507	#ifdef VBOX_WITH_KERNEL_USING_XMM
508	memcpy(&pVCpu->cpum.s.Guest.CTX_SUFF(pXState)->x87.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
509	#endif
510	}
511
512	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU \| CPUM_SYNC_FPU_STATE \| CPUM_USED_MANUAL_XMM_RESTORE);
513	return VINF_SUCCESS;
514	}
515
516
517	/**
518	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
519	* DR7 with safe values.
520	*
521	* @returns VBox status code.
522	* @param pVCpu Pointer to the VMCPU.
523	*/
524	static int cpumR0SaveHostDebugState(PVMCPU pVCpu)
525	{
526	/*
527	* Save the host state.
528	*/
529	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
530	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
531	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
532	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
533	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
534	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
535	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
536
537	/* Preemption paranoia. */
538	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
539
540	/*
541	* Make sure DR7 is harmless or else we could trigger breakpoints when
542	* load guest or hypervisor DRx values later.
543	*/
544	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
545	ASMSetDR7(X86_DR7_INIT_VAL);
546
547	return VINF_SUCCESS;
548	}
549
550
551	/**
552	* Saves the guest DRx state residing in host registers and restore the host
553	* register values.
554	*
555	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
556	* since it's assumed that we're shadowing the guest DRx register values
557	* accurately when using the combined hypervisor debug register values
558	* (CPUMR0LoadHyperDebugState).
559	*
560	* @returns true if either guest or hypervisor debug registers were loaded.
561	* @param pVCpu The cross context CPU structure for the calling EMT.
562	* @param fDr6 Whether to include DR6 or not.
563	* @thread EMT(pVCpu)
564	*/
565	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6)
566	{
567	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
568	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
569
570	/*
571	* Do we need to save the guest DRx registered loaded into host registers?
572	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
573	*/
574	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
575	{
576	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
577	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
578	{
579	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
580	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
581	if (!fDr6)
582	pVCpu->cpum.s.Guest.dr[6] = uDr6;
583	}
584	else
585	#endif
586	{
587	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
588	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
589	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
590	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
591	if (fDr6)
592	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
593	}
594	}
595	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~( CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER
596	\| CPUM_SYNC_DEBUG_REGS_GUEST \| CPUM_SYNC_DEBUG_REGS_HYPER));
597
598	/*
599	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
600	*/
601	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
602	{
603	/* A bit of paranoia first... */
604	uint64_t uCurDR7 = ASMGetDR7();
605	if (uCurDR7 != X86_DR7_INIT_VAL)
606	ASMSetDR7(X86_DR7_INIT_VAL);
607
608	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
609	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
610	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
611	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
612	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
613	* expensive DRx reads are over DRx writes. */
614	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
615	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
616
617	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
618	}
619
620	return fDrXLoaded;
621	}
622
623
624	/**
625	* Saves the guest DRx state if it resides host registers.
626	*
627	* This does NOT clear any use flags, so the host registers remains loaded with
628	* the guest DRx state upon return. The purpose is only to make sure the values
629	* in the CPU context structure is up to date.
630	*
631	* @returns true if the host registers contains guest values, false if not.
632	* @param pVCpu The cross context CPU structure for the calling EMT.
633	* @param fDr6 Whether to include DR6 or not.
634	* @thread EMT(pVCpu)
635	*/
636	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6)
637	{
638	/*
639	* Do we need to save the guest DRx registered loaded into host registers?
640	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
641	*/
642	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
643	{
644	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
645	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
646	{
647	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
648	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
649	if (!fDr6)
650	pVCpu->cpum.s.Guest.dr[6] = uDr6;
651	}
652	else
653	#endif
654	{
655	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
656	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
657	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
658	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
659	if (fDr6)
660	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
661	}
662	return true;
663	}
664	return false;
665	}
666
667
668	/**
669	* Lazily sync in the debug state.
670	*
671	* @param pVCpu The cross context CPU structure for the calling EMT.
672	* @param fDr6 Whether to include DR6 or not.
673	* @thread EMT(pVCpu)
674	*/
675	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6)
676	{
677	/*
678	* Save the host state and disarm all host BPs.
679	*/
680	cpumR0SaveHostDebugState(pVCpu);
681	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
682
683	/*
684	* Activate the guest state DR0-3.
685	* DR7 and DR6 (if fDr6 is true) are left to the caller.
686	*/
687	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
688	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
689	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_GUEST); /* Postpone it to the world switch. */
690	else
691	#endif
692	{
693	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
694	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
695	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
696	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
697	if (fDr6)
698	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
699
700	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
701	}
702	}
703
704
705	/**
706	* Lazily sync in the hypervisor debug state
707	*
708	* @returns VBox status code.
709	* @param pVCpu The cross context CPU structure for the calling EMT.
710	* @param fDr6 Whether to include DR6 or not.
711	* @thread EMT(pVCpu)
712	*/
713	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6)
714	{
715	/*
716	* Save the host state and disarm all host BPs.
717	*/
718	cpumR0SaveHostDebugState(pVCpu);
719	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
720
721	/*
722	* Make sure the hypervisor values are up to date.
723	*/
724	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */, true);
725
726	/*
727	* Activate the guest state DR0-3.
728	* DR7 and DR6 (if fDr6 is true) are left to the caller.
729	*/
730	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
731	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
732	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_HYPER); /* Postpone it. */
733	else
734	#endif
735	{
736	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
737	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
738	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
739	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
740	if (fDr6)
741	ASMSetDR6(X86_DR6_INIT_VAL);
742
743	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
744	}
745	}
746
747	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
748
749	/**
750	* Per-CPU callback that probes the CPU for APIC support.
751	*
752	* @param idCpu The identifier for the CPU the function is called on.
753	* @param pvUser1 Ignored.
754	* @param pvUser2 Ignored.
755	*/
756	static DECLCALLBACK(void) cpumR0MapLocalApicCpuProber(RTCPUID idCpu, void pvUser1, void pvUser2)
757	{
758	NOREF(pvUser1); NOREF(pvUser2);
759	int iCpu = RTMpCpuIdToSetIndex(idCpu);
760	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
761
762	/*
763	* Check for APIC support.
764	*/
765	uint32_t uMaxLeaf, u32EBX, u32ECX, u32EDX;
766	ASMCpuId(0, &uMaxLeaf, &u32EBX, &u32ECX, &u32EDX);
767	if ( ( ASMIsIntelCpuEx(u32EBX, u32ECX, u32EDX)
768	\|\| ASMIsAmdCpuEx(u32EBX, u32ECX, u32EDX)
769	\|\| ASMIsViaCentaurCpuEx(u32EBX, u32ECX, u32EDX))
770	&& ASMIsValidStdRange(uMaxLeaf))
771	{
772	uint32_t uDummy;
773	ASMCpuId(1, &uDummy, &u32EBX, &u32ECX, &u32EDX);
774	if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
775	&& (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
776	{
777	/*
778	* Safe to access the MSR. Read it and calc the BASE (a little complicated).
779	*/
780	uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
781	uint64_t u64Mask = MSR_IA32_APICBASE_BASE_MIN;
782
783	/* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
784	uint32_t uMaxExtLeaf;
785	ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX);
786	if ( uMaxExtLeaf >= UINT32_C(0x80000008)
787	&& ASMIsValidExtRange(uMaxExtLeaf))
788	{
789	uint32_t u32PhysBits;
790	ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
791	u32PhysBits &= 0xff;
792	u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
793	}
794
795	AssertCompile(sizeof(g_aLApics[iCpu].PhysBase) == sizeof(u64ApicBase));
796	g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
797	g_aLApics[iCpu].fEnabled = RT_BOOL(u64ApicBase & MSR_IA32_APICBASE_EN);
798	g_aLApics[iCpu].fX2Apic = (u64ApicBase & (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN))
799	== (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN);
800	}
801	}
802	}
803
804
805
806	/**
807	* Per-CPU callback that verifies our APIC expectations.
808	*
809	* @param idCpu The identifier for the CPU the function is called on.
810	* @param pvUser1 Ignored.
811	* @param pvUser2 Ignored.
812	*/
813	static DECLCALLBACK(void) cpumR0MapLocalApicCpuChecker(RTCPUID idCpu, void pvUser1, void pvUser2)
814	{
815	NOREF(pvUser1); NOREF(pvUser2);
816
817	int iCpu = RTMpCpuIdToSetIndex(idCpu);
818	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
819	if (!g_aLApics[iCpu].fEnabled)
820	return;
821
822	/*
823	* 0x0X 82489 external APIC
824	* 0x1X Local APIC
825	* 0x2X..0xFF reserved
826	*/
827	uint32_t uApicVersion;
828	if (g_aLApics[iCpu].fX2Apic)
829	uApicVersion = ApicX2RegRead32(APIC_REG_VERSION);
830	else
831	uApicVersion = ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_VERSION);
832	if ((APIC_REG_VERSION_GET_VER(uApicVersion) & 0xF0) == 0x10)
833	{
834	g_aLApics[iCpu].uVersion = uApicVersion;
835
836	#if 0 /* enable if you need it. */
837	if (g_aLApics[iCpu].fX2Apic)
838	SUPR0Printf("CPUM: X2APIC %02u - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
839	iCpu, uApicVersion,
840	ApicX2RegRead32(APIC_REG_LVT_LINT0), ApicX2RegRead32(APIC_REG_LVT_LINT1),
841	ApicX2RegRead32(APIC_REG_LVT_PC), ApicX2RegRead32(APIC_REG_LVT_THMR),
842	ApicX2RegRead32(APIC_REG_LVT_CMCI));
843	else
844	{
845	SUPR0Printf("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
846	iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, uApicVersion,
847	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT0), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT1),
848	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_PC), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_THMR),
849	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_CMCI));
850	if (uApicVersion & 0x80000000)
851	{
852	uint32_t uExtFeatures = ApicRegRead(g_aLApics[iCpu].pv, 0x400);
853	uint32_t cEiLvt = (uExtFeatures >> 16) & 0xff;
854	SUPR0Printf("CPUM: APIC %02u: ExtSpace available. extfeat=%08x eilvt[0..3]=%08x %08x %08x %08x\n",
855	iCpu,
856	ApicRegRead(g_aLApics[iCpu].pv, 0x400),
857	cEiLvt >= 1 ? ApicRegRead(g_aLApics[iCpu].pv, 0x500) : 0,
858	cEiLvt >= 2 ? ApicRegRead(g_aLApics[iCpu].pv, 0x510) : 0,
859	cEiLvt >= 3 ? ApicRegRead(g_aLApics[iCpu].pv, 0x520) : 0,
860	cEiLvt >= 4 ? ApicRegRead(g_aLApics[iCpu].pv, 0x530) : 0);
861	}
862	}
863	#endif
864	}
865	else
866	{
867	g_aLApics[iCpu].fEnabled = false;
868	g_aLApics[iCpu].fX2Apic = false;
869	SUPR0Printf("VBox/CPUM: Unsupported APIC version %#x (iCpu=%d)\n", uApicVersion, iCpu);
870	}
871	}
872
873
874	/**
875	* Map the MMIO page of each local APIC in the system.
876	*/
877	static int cpumR0MapLocalApics(void)
878	{
879	/*
880	* Check that we'll always stay within the array bounds.
881	*/
882	if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
883	{
884	LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
885	return VERR_TOO_MANY_CPUS;
886	}
887
888	/*
889	* Create mappings for all online CPUs we think have legacy APICs.
890	*/
891	int rc = RTMpOnAll(cpumR0MapLocalApicCpuProber, NULL, NULL);
892
893	for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
894	{
895	if (g_aLApics[iCpu].fEnabled && !g_aLApics[iCpu].fX2Apic)
896	{
897	rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
898	PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
899	if (RT_SUCCESS(rc))
900	{
901	rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
902	PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
903	if (RT_SUCCESS(rc))
904	{
905	g_aLApics[iCpu].pv = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
906	continue;
907	}
908	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
909	}
910	g_aLApics[iCpu].fEnabled = false;
911	}
912	g_aLApics[iCpu].pv = NULL;
913	}
914
915	/*
916	* Check the APICs.
917	*/
918	if (RT_SUCCESS(rc))
919	rc = RTMpOnAll(cpumR0MapLocalApicCpuChecker, NULL, NULL);
920
921	if (RT_FAILURE(rc))
922	{
923	cpumR0UnmapLocalApics();
924	return rc;
925	}
926
927	#ifdef LOG_ENABLED
928	/*
929	* Log the result (pretty useless, requires enabling CPUM in VBoxDrv
930	* and !VBOX_WITH_R0_LOGGING).
931	*/
932	if (LogIsEnabled())
933	{
934	uint32_t cEnabled = 0;
935	uint32_t cX2Apics = 0;
936	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
937	if (g_aLApics[iCpu].fEnabled)
938	{
939	cEnabled++;
940	cX2Apics += g_aLApics[iCpu].fX2Apic;
941	}
942	Log(("CPUM: %u APICs, %u X2APICs\n", cEnabled, cX2Apics));
943	}
944	#endif
945
946	return VINF_SUCCESS;
947	}
948
949
950	/**
951	* Unmap the Local APIC of all host CPUs.
952	*/
953	static void cpumR0UnmapLocalApics(void)
954	{
955	for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
956	{
957	if (g_aLApics[iCpu].pv)
958	{
959	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
960	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
961	g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
962	g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
963	g_aLApics[iCpu].fEnabled = false;
964	g_aLApics[iCpu].fX2Apic = false;
965	g_aLApics[iCpu].pv = NULL;
966	}
967	}
968	}
969
970
971	/**
972	* Updates CPUMCPU::pvApicBase and CPUMCPU::fX2Apic prior to world switch.
973	*
974	* Writes the Local APIC mapping address of the current host CPU to CPUMCPU so
975	* the world switchers can access the APIC registers for the purpose of
976	* disabling and re-enabling the NMIs. Must be called with disabled preemption
977	* or disabled interrupts!
978	*
979	* @param pVCpu Pointer to the cross context CPU structure of the
980	* calling EMT.
981	* @param iHostCpuSet The CPU set index of the current host CPU.
982	*/
983	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet)
984	{
985	Assert(iHostCpuSet <= RT_ELEMENTS(g_aLApics));
986	pVCpu->cpum.s.pvApicBase = g_aLApics[iHostCpuSet].pv;
987	pVCpu->cpum.s.fX2Apic = g_aLApics[iHostCpuSet].fX2Apic;
988	// Log6(("CPUMR0SetLApic: pvApicBase=%p fX2Apic=%d\n", g_aLApics[idxCpu].pv, g_aLApics[idxCpu].fX2Apic));
989	}
990
991	#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */
992

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 57493

Download in other formats: