CPUMR0.cpp@ 69713

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1	/* $Id: CPUMR0.cpp 69111 2017-10-17 14:26:02Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/err.h>
27	#include <VBox/log.h>
28	#include <VBox/vmm/hm.h>
29	#include <iprt/assert.h>
30	#include <iprt/asm-amd64-x86.h>
31	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
32	# include <iprt/mem.h>
33	# include <iprt/memobj.h>
34	# include <VBox/apic.h>
35	#endif
36	#include <iprt/x86.h>
37
38
39	/*********************************************************************************************************************************
40	* Structures and Typedefs *
41	*********************************************************************************************************************************/
42	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
43	/**
44	* Local APIC mappings.
45	*/
46	typedef struct CPUMHOSTLAPIC
47	{
48	/** Indicates that the entry is in use and have valid data. */
49	bool fEnabled;
50	/** Whether it's operating in X2APIC mode (EXTD). */
51	bool fX2Apic;
52	/** The APIC version number. */
53	uint32_t uVersion;
54	/** The physical address of the APIC registers. */
55	RTHCPHYS PhysBase;
56	/** The memory object entering the physical address. */
57	RTR0MEMOBJ hMemObj;
58	/** The mapping object for hMemObj. */
59	RTR0MEMOBJ hMapObj;
60	/** The mapping address APIC registers.
61	* @remarks Different CPUs may use the same physical address to map their
62	* APICs, so this pointer is only valid when on the CPU owning the
63	* APIC. */
64	void *pv;
65	} CPUMHOSTLAPIC;
66	#endif
67
68
69	/*********************************************************************************************************************************
70	* Global Variables *
71	*********************************************************************************************************************************/
72	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
73	static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
74	#endif
75
76	/**
77	* CPUID bits to unify among all cores.
78	*/
79	static struct
80	{
81	uint32_t uLeaf; /*< Leaf to check. /
82	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
83	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
84	}
85	const g_aCpuidUnifyBits[] =
86	{
87	{
88	0x00000001,
89	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
90	X86_CPUID_FEATURE_EDX_CX8
91	}
92	};
93
94
95
96	/*********************************************************************************************************************************
97	* Internal Functions *
98	*********************************************************************************************************************************/
99	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
100	static int cpumR0MapLocalApics(void);
101	static void cpumR0UnmapLocalApics(void);
102	#endif
103	static int cpumR0SaveHostDebugState(PVMCPU pVCpu);
104
105
106	/**
107	* Does the Ring-0 CPU initialization once during module load.
108	* XXX Host-CPU hot-plugging?
109	*/
110	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
111	{
112	int rc = VINF_SUCCESS;
113	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
114	rc = cpumR0MapLocalApics();
115	#endif
116	return rc;
117	}
118
119
120	/**
121	* Terminate the module.
122	*/
123	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
124	{
125	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
126	cpumR0UnmapLocalApics();
127	#endif
128	return VINF_SUCCESS;
129	}
130
131
132	/**
133	*
134	*
135	* Check the CPUID features of this particular CPU and disable relevant features
136	* for the guest which do not exist on this CPU. We have seen systems where the
137	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
138	* @bugref{5436}.
139	*
140	* @note This function might be called simultaneously on more than one CPU!
141	*
142	* @param idCpu The identifier for the CPU the function is called on.
143	* @param pvUser1 Pointer to the VM structure.
144	* @param pvUser2 Ignored.
145	*/
146	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
147	{
148	PVM pVM = (PVM)pvUser1;
149
150	NOREF(idCpu); NOREF(pvUser2);
151	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
152	{
153	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
154	necessarily in the VM process context. So, we using the
155	legacy arrays as temporary storage. */
156
157	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
158	PCPUMCPUID pLegacyLeaf;
159	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
160	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
161	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
162	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
163	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
164	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
165	else
166	continue;
167
168	uint32_t eax, ebx, ecx, edx;
169	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
170
171	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
172	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
173	}
174	}
175
176
177	/**
178	* Does Ring-0 CPUM initialization.
179	*
180	* This is mainly to check that the Host CPU mode is compatible
181	* with VBox.
182	*
183	* @returns VBox status code.
184	* @param pVM The cross context VM structure.
185	*/
186	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM)
187	{
188	LogFlow(("CPUMR0Init: %p\n", pVM));
189
190	/*
191	* Check CR0 & CR4 flags.
192	*/
193	uint32_t u32CR0 = ASMGetCR0();
194	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
195	{
196	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
197	return VERR_UNSUPPORTED_CPU_MODE;
198	}
199
200	/*
201	* Check for sysenter and syscall usage.
202	*/
203	if (ASMHasCpuId())
204	{
205	/*
206	* SYSENTER/SYSEXIT
207	*
208	* Intel docs claim you should test both the flag and family, model &
209	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
210	* but don't support it. AMD CPUs may support this feature in legacy
211	* mode, they've banned it from long mode. Since we switch to 32-bit
212	* mode when entering raw-mode context the feature would become
213	* accessible again on AMD CPUs, so we have to check regardless of
214	* host bitness.
215	*/
216	uint32_t u32CpuVersion;
217	uint32_t u32Dummy;
218	uint32_t fFeatures;
219	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
220	uint32_t const u32Family = u32CpuVersion >> 8;
221	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
222	uint32_t const u32Stepping = u32CpuVersion & 0xF;
223	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
224	&& ( u32Family != 6 /* (> pentium pro) */
225	\|\| u32Model >= 3
226	\|\| u32Stepping >= 3
227	\|\| !ASMIsIntelCpu())
228	)
229	{
230	/*
231	* Read the MSR and see if it's in use or not.
232	*/
233	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
234	if (u32)
235	{
236	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
237	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
238	}
239	}
240
241	/*
242	* SYSCALL/SYSRET
243	*
244	* This feature is indicated by the SEP bit returned in EDX by CPUID
245	* function 0x80000001. Intel CPUs only supports this feature in
246	* long mode. Since we're not running 64-bit guests in raw-mode there
247	* are no issues with 32-bit intel hosts.
248	*/
249	uint32_t cExt = 0;
250	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
251	if (ASMIsValidExtRange(cExt))
252	{
253	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
254	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
255	{
256	#ifdef RT_ARCH_X86
257	if (!ASMIsIntelCpu())
258	#endif
259	{
260	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
261	if (fEfer & MSR_K6_EFER_SCE)
262	{
263	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
264	Log(("CPUMR0Init: host uses syscall\n"));
265	}
266	}
267	}
268	}
269
270	/*
271	* Unify/cross check some CPUID feature bits on all available CPU cores
272	* and threads. We've seen CPUs where the monitor support differed.
273	*
274	* Because the hyper heap isn't always mapped into ring-0, we cannot
275	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
276	* as temp ring-0 accessible memory instead, ASSUMING that they're all
277	* up to date when we get here.
278	*/
279	RTMpOnAll(cpumR0CheckCpuid, pVM, NULL);
280
281	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
282	{
283	bool fIgnored;
284	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
285	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
286	if (pLeaf)
287	{
288	PCPUMCPUID pLegacyLeaf;
289	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
290	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
291	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
292	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
293	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
294	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
295	else
296	continue;
297
298	pLeaf->uEcx = pLegacyLeaf->uEcx;
299	pLeaf->uEdx = pLegacyLeaf->uEdx;
300	}
301	}
302
303	}
304
305
306	/*
307	* Check if debug registers are armed.
308	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
309	*/
310	uint32_t u32DR7 = ASMGetDR7();
311	if (u32DR7 & X86_DR7_ENABLED_MASK)
312	{
313	for (VMCPUID i = 0; i < pVM->cCpus; i++)
314	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
315	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
316	}
317
318	return VINF_SUCCESS;
319	}
320
321
322	/**
323	* Trap handler for device-not-available fault (\#NM).
324	* Device not available, FP or (F)WAIT instruction.
325	*
326	* @returns VBox status code.
327	* @retval VINF_SUCCESS if the guest FPU state is loaded.
328	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
329	* @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
330	*
331	* @param pVM The cross context VM structure.
332	* @param pVCpu The cross context virtual CPU structure.
333	*/
334	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu)
335	{
336	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
337	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
338
339	/* If the FPU state has already been loaded, then it's a guest trap. */
340	if (CPUMIsGuestFPUStateActive(pVCpu))
341	{
342	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
343	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
344	return VINF_EM_RAW_GUEST_TRAP;
345	}
346
347	/*
348	* There are two basic actions:
349	* 1. Save host fpu and restore guest fpu.
350	* 2. Generate guest trap.
351	*
352	* When entering the hypervisor we'll always enable MP (for proper wait
353	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
354	* is taken from the guest OS in order to get proper SSE handling.
355	*
356	*
357	* Actions taken depending on the guest CR0 flags:
358	*
359	* 3 2 1
360	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
361	* ------------------------------------------------------------------------
362	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
363	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
364	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
365	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
366	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
367	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
368	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
369	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
370	*/
371
372	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
373	{
374	case X86_CR0_MP \| X86_CR0_TS:
375	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
376	return VINF_EM_RAW_GUEST_TRAP;
377	default:
378	break;
379	}
380
381	return CPUMR0LoadGuestFPU(pVM, pVCpu);
382	}
383
384
385	/**
386	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
387	* state into the CPU.
388	*
389	* @returns VINF_SUCCESS on success, host CR0 unmodified.
390	* @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
391	* modified and VT-x needs to update the value in the VMCS.
392	*
393	* @param pVM The cross context VM structure.
394	* @param pVCpu The cross context virtual CPU structure.
395	*/
396	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu)
397	{
398	int rc = VINF_SUCCESS;
399	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
400	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
401	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
402
403	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
404	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
405	{
406	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
407
408	/* Save the host state if necessary. */
409	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST))
410	rc = cpumRZSaveHostFPUState(&pVCpu->cpum.s);
411
412	/* Restore the state on entry as we need to be in 64-bit mode to access the full state. */
413	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
414
415	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
416	== (CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
417	}
418	else
419	#endif
420	{
421	if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
422	{
423	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
424	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
425	}
426	else
427	{
428	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
429	/** @todo r=ramshankar: Can't we used a cached value here
430	* instead of reading the MSR? host EFER doesn't usually
431	* change. */
432	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
433	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
434	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
435	else
436	{
437	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
438	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
439	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
440	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
441	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
442	ASMSetFlags(uSavedFlags);
443	}
444	}
445	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
446	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
447	}
448	return rc;
449	}
450
451
452	/**
453	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
454	* needed.
455	*
456	* @returns true if we saved the guest state.
457	* @param pVCpu The cross context virtual CPU structure.
458	*/
459	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu)
460	{
461	bool fSavedGuest;
462	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
463	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
464	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
465	{
466	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
467	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
468	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
469	{
470	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
471	{
472	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
473	HMR0SaveFPUState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
474	}
475	else
476	pVCpu->cpum.s.fUseFlags &= ~CPUM_SYNC_FPU_STATE;
477	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
478	}
479	else
480	#endif
481	{
482	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
483	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
484	else
485	{
486	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
487	save/restore the XMM state with fxsave/fxrstor. */
488	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
489	if (uHostEfer & MSR_K6_EFER_FFXSR)
490	{
491	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
492	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
493	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
494	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
495	ASMSetFlags(uSavedFlags);
496	}
497	else
498	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
499	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
500	}
501	}
502	}
503	else
504	fSavedGuest = false;
505	Assert(!( pVCpu->cpum.s.fUseFlags
506	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_SYNC_FPU_STATE \| CPUM_USED_MANUAL_XMM_RESTORE)));
507	return fSavedGuest;
508	}
509
510
511	/**
512	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
513	* DR7 with safe values.
514	*
515	* @returns VBox status code.
516	* @param pVCpu The cross context virtual CPU structure.
517	*/
518	static int cpumR0SaveHostDebugState(PVMCPU pVCpu)
519	{
520	/*
521	* Save the host state.
522	*/
523	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
524	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
525	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
526	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
527	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
528	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
529	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
530
531	/* Preemption paranoia. */
532	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
533
534	/*
535	* Make sure DR7 is harmless or else we could trigger breakpoints when
536	* load guest or hypervisor DRx values later.
537	*/
538	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
539	ASMSetDR7(X86_DR7_INIT_VAL);
540
541	return VINF_SUCCESS;
542	}
543
544
545	/**
546	* Saves the guest DRx state residing in host registers and restore the host
547	* register values.
548	*
549	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
550	* since it's assumed that we're shadowing the guest DRx register values
551	* accurately when using the combined hypervisor debug register values
552	* (CPUMR0LoadHyperDebugState).
553	*
554	* @returns true if either guest or hypervisor debug registers were loaded.
555	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
556	* @param fDr6 Whether to include DR6 or not.
557	* @thread EMT(pVCpu)
558	*/
559	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6)
560	{
561	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
562	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
563
564	/*
565	* Do we need to save the guest DRx registered loaded into host registers?
566	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
567	*/
568	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
569	{
570	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
571	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
572	{
573	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
574	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
575	if (!fDr6)
576	pVCpu->cpum.s.Guest.dr[6] = uDr6;
577	}
578	else
579	#endif
580	{
581	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
582	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
583	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
584	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
585	if (fDr6)
586	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
587	}
588	}
589	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~( CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER
590	\| CPUM_SYNC_DEBUG_REGS_GUEST \| CPUM_SYNC_DEBUG_REGS_HYPER));
591
592	/*
593	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
594	*/
595	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
596	{
597	/* A bit of paranoia first... */
598	uint64_t uCurDR7 = ASMGetDR7();
599	if (uCurDR7 != X86_DR7_INIT_VAL)
600	ASMSetDR7(X86_DR7_INIT_VAL);
601
602	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
603	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
604	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
605	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
606	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
607	* expensive DRx reads are over DRx writes. */
608	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
609	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
610
611	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
612	}
613
614	return fDrXLoaded;
615	}
616
617
618	/**
619	* Saves the guest DRx state if it resides host registers.
620	*
621	* This does NOT clear any use flags, so the host registers remains loaded with
622	* the guest DRx state upon return. The purpose is only to make sure the values
623	* in the CPU context structure is up to date.
624	*
625	* @returns true if the host registers contains guest values, false if not.
626	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
627	* @param fDr6 Whether to include DR6 or not.
628	* @thread EMT(pVCpu)
629	*/
630	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6)
631	{
632	/*
633	* Do we need to save the guest DRx registered loaded into host registers?
634	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
635	*/
636	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
637	{
638	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
639	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
640	{
641	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
642	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
643	if (!fDr6)
644	pVCpu->cpum.s.Guest.dr[6] = uDr6;
645	}
646	else
647	#endif
648	{
649	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
650	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
651	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
652	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
653	if (fDr6)
654	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
655	}
656	return true;
657	}
658	return false;
659	}
660
661
662	/**
663	* Lazily sync in the debug state.
664	*
665	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
666	* @param fDr6 Whether to include DR6 or not.
667	* @thread EMT(pVCpu)
668	*/
669	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6)
670	{
671	/*
672	* Save the host state and disarm all host BPs.
673	*/
674	cpumR0SaveHostDebugState(pVCpu);
675	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
676
677	/*
678	* Activate the guest state DR0-3.
679	* DR7 and DR6 (if fDr6 is true) are left to the caller.
680	*/
681	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
682	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
683	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_GUEST); /* Postpone it to the world switch. */
684	else
685	#endif
686	{
687	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
688	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
689	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
690	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
691	if (fDr6)
692	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
693
694	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
695	}
696	}
697
698
699	/**
700	* Lazily sync in the hypervisor debug state
701	*
702	* @returns VBox status code.
703	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
704	* @param fDr6 Whether to include DR6 or not.
705	* @thread EMT(pVCpu)
706	*/
707	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6)
708	{
709	/*
710	* Save the host state and disarm all host BPs.
711	*/
712	cpumR0SaveHostDebugState(pVCpu);
713	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
714
715	/*
716	* Make sure the hypervisor values are up to date.
717	*/
718	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */, true);
719
720	/*
721	* Activate the guest state DR0-3.
722	* DR7 and DR6 (if fDr6 is true) are left to the caller.
723	*/
724	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
725	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
726	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_HYPER); /* Postpone it. */
727	else
728	#endif
729	{
730	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
731	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
732	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
733	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
734	if (fDr6)
735	ASMSetDR6(X86_DR6_INIT_VAL);
736
737	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
738	}
739	}
740
741	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
742
743	/**
744	* Per-CPU callback that probes the CPU for APIC support.
745	*
746	* @param idCpu The identifier for the CPU the function is called on.
747	* @param pvUser1 Ignored.
748	* @param pvUser2 Ignored.
749	*/
750	static DECLCALLBACK(void) cpumR0MapLocalApicCpuProber(RTCPUID idCpu, void pvUser1, void pvUser2)
751	{
752	NOREF(pvUser1); NOREF(pvUser2);
753	int iCpu = RTMpCpuIdToSetIndex(idCpu);
754	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
755
756	/*
757	* Check for APIC support.
758	*/
759	uint32_t uMaxLeaf, u32EBX, u32ECX, u32EDX;
760	ASMCpuId(0, &uMaxLeaf, &u32EBX, &u32ECX, &u32EDX);
761	if ( ( ASMIsIntelCpuEx(u32EBX, u32ECX, u32EDX)
762	\|\| ASMIsAmdCpuEx(u32EBX, u32ECX, u32EDX)
763	\|\| ASMIsViaCentaurCpuEx(u32EBX, u32ECX, u32EDX))
764	&& ASMIsValidStdRange(uMaxLeaf))
765	{
766	uint32_t uDummy;
767	ASMCpuId(1, &uDummy, &u32EBX, &u32ECX, &u32EDX);
768	if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
769	&& (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
770	{
771	/*
772	* Safe to access the MSR. Read it and calc the BASE (a little complicated).
773	*/
774	uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
775	uint64_t u64Mask = MSR_IA32_APICBASE_BASE_MIN;
776
777	/* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
778	uint32_t uMaxExtLeaf;
779	ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX);
780	if ( uMaxExtLeaf >= UINT32_C(0x80000008)
781	&& ASMIsValidExtRange(uMaxExtLeaf))
782	{
783	uint32_t u32PhysBits;
784	ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
785	u32PhysBits &= 0xff;
786	u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
787	}
788
789	AssertCompile(sizeof(g_aLApics[iCpu].PhysBase) == sizeof(u64ApicBase));
790	g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
791	g_aLApics[iCpu].fEnabled = RT_BOOL(u64ApicBase & MSR_IA32_APICBASE_EN);
792	g_aLApics[iCpu].fX2Apic = (u64ApicBase & (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN))
793	== (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN);
794	}
795	}
796	}
797
798
799
800	/**
801	* Per-CPU callback that verifies our APIC expectations.
802	*
803	* @param idCpu The identifier for the CPU the function is called on.
804	* @param pvUser1 Ignored.
805	* @param pvUser2 Ignored.
806	*/
807	static DECLCALLBACK(void) cpumR0MapLocalApicCpuChecker(RTCPUID idCpu, void pvUser1, void pvUser2)
808	{
809	NOREF(pvUser1); NOREF(pvUser2);
810
811	int iCpu = RTMpCpuIdToSetIndex(idCpu);
812	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
813	if (!g_aLApics[iCpu].fEnabled)
814	return;
815
816	/*
817	* 0x0X 82489 external APIC
818	* 0x1X Local APIC
819	* 0x2X..0xFF reserved
820	*/
821	uint32_t uApicVersion;
822	if (g_aLApics[iCpu].fX2Apic)
823	uApicVersion = ApicX2RegRead32(APIC_REG_VERSION);
824	else
825	uApicVersion = ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_VERSION);
826	if ((APIC_REG_VERSION_GET_VER(uApicVersion) & 0xF0) == 0x10)
827	{
828	g_aLApics[iCpu].uVersion = uApicVersion;
829
830	#if 0 /* enable if you need it. */
831	if (g_aLApics[iCpu].fX2Apic)
832	SUPR0Printf("CPUM: X2APIC %02u - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
833	iCpu, uApicVersion,
834	ApicX2RegRead32(APIC_REG_LVT_LINT0), ApicX2RegRead32(APIC_REG_LVT_LINT1),
835	ApicX2RegRead32(APIC_REG_LVT_PC), ApicX2RegRead32(APIC_REG_LVT_THMR),
836	ApicX2RegRead32(APIC_REG_LVT_CMCI));
837	else
838	{
839	SUPR0Printf("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
840	iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, uApicVersion,
841	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT0), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT1),
842	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_PC), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_THMR),
843	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_CMCI));
844	if (uApicVersion & 0x80000000)
845	{
846	uint32_t uExtFeatures = ApicRegRead(g_aLApics[iCpu].pv, 0x400);
847	uint32_t cEiLvt = (uExtFeatures >> 16) & 0xff;
848	SUPR0Printf("CPUM: APIC %02u: ExtSpace available. extfeat=%08x eilvt[0..3]=%08x %08x %08x %08x\n",
849	iCpu,
850	ApicRegRead(g_aLApics[iCpu].pv, 0x400),
851	cEiLvt >= 1 ? ApicRegRead(g_aLApics[iCpu].pv, 0x500) : 0,
852	cEiLvt >= 2 ? ApicRegRead(g_aLApics[iCpu].pv, 0x510) : 0,
853	cEiLvt >= 3 ? ApicRegRead(g_aLApics[iCpu].pv, 0x520) : 0,
854	cEiLvt >= 4 ? ApicRegRead(g_aLApics[iCpu].pv, 0x530) : 0);
855	}
856	}
857	#endif
858	}
859	else
860	{
861	g_aLApics[iCpu].fEnabled = false;
862	g_aLApics[iCpu].fX2Apic = false;
863	SUPR0Printf("VBox/CPUM: Unsupported APIC version %#x (iCpu=%d)\n", uApicVersion, iCpu);
864	}
865	}
866
867
868	/**
869	* Map the MMIO page of each local APIC in the system.
870	*/
871	static int cpumR0MapLocalApics(void)
872	{
873	/*
874	* Check that we'll always stay within the array bounds.
875	*/
876	if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
877	{
878	LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
879	return VERR_TOO_MANY_CPUS;
880	}
881
882	/*
883	* Create mappings for all online CPUs we think have legacy APICs.
884	*/
885	int rc = RTMpOnAll(cpumR0MapLocalApicCpuProber, NULL, NULL);
886
887	for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
888	{
889	if (g_aLApics[iCpu].fEnabled && !g_aLApics[iCpu].fX2Apic)
890	{
891	rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
892	PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
893	if (RT_SUCCESS(rc))
894	{
895	rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
896	PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
897	if (RT_SUCCESS(rc))
898	{
899	g_aLApics[iCpu].pv = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
900	continue;
901	}
902	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
903	}
904	g_aLApics[iCpu].fEnabled = false;
905	}
906	g_aLApics[iCpu].pv = NULL;
907	}
908
909	/*
910	* Check the APICs.
911	*/
912	if (RT_SUCCESS(rc))
913	rc = RTMpOnAll(cpumR0MapLocalApicCpuChecker, NULL, NULL);
914
915	if (RT_FAILURE(rc))
916	{
917	cpumR0UnmapLocalApics();
918	return rc;
919	}
920
921	#ifdef LOG_ENABLED
922	/*
923	* Log the result (pretty useless, requires enabling CPUM in VBoxDrv
924	* and !VBOX_WITH_R0_LOGGING).
925	*/
926	if (LogIsEnabled())
927	{
928	uint32_t cEnabled = 0;
929	uint32_t cX2Apics = 0;
930	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
931	if (g_aLApics[iCpu].fEnabled)
932	{
933	cEnabled++;
934	cX2Apics += g_aLApics[iCpu].fX2Apic;
935	}
936	Log(("CPUM: %u APICs, %u X2APICs\n", cEnabled, cX2Apics));
937	}
938	#endif
939
940	return VINF_SUCCESS;
941	}
942
943
944	/**
945	* Unmap the Local APIC of all host CPUs.
946	*/
947	static void cpumR0UnmapLocalApics(void)
948	{
949	for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
950	{
951	if (g_aLApics[iCpu].pv)
952	{
953	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
954	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
955	g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
956	g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
957	g_aLApics[iCpu].fEnabled = false;
958	g_aLApics[iCpu].fX2Apic = false;
959	g_aLApics[iCpu].pv = NULL;
960	}
961	}
962	}
963
964
965	/**
966	* Updates CPUMCPU::pvApicBase and CPUMCPU::fX2Apic prior to world switch.
967	*
968	* Writes the Local APIC mapping address of the current host CPU to CPUMCPU so
969	* the world switchers can access the APIC registers for the purpose of
970	* disabling and re-enabling the NMIs. Must be called with disabled preemption
971	* or disabled interrupts!
972	*
973	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
974	* @param iHostCpuSet The CPU set index of the current host CPU.
975	*/
976	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet)
977	{
978	Assert(iHostCpuSet <= RT_ELEMENTS(g_aLApics));
979	pVCpu->cpum.s.pvApicBase = g_aLApics[iHostCpuSet].pv;
980	pVCpu->cpum.s.fX2Apic = g_aLApics[iHostCpuSet].fX2Apic;
981	// Log6(("CPUMR0SetLApic: pvApicBase=%p fX2Apic=%d\n", g_aLApics[idxCpu].pv, g_aLApics[idxCpu].fX2Apic));
982	}
983
984	#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */
985

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 69713

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