CPUMR0.cpp@ 78402

Last change on this file since 78402 was 76886, checked in by vboxsync, 6 years ago
VMM (and related changes): Add support for Shanghai/Zhaoxin CPUs. Modified and improved contribution by Journey Ren submitted under MIT license. Thank you!
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1	/* $Id: CPUMR0.cpp 76886 2019-01-18 10:57:02Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/err.h>
27	#include <VBox/log.h>
28	#include <VBox/vmm/hm.h>
29	#include <iprt/assert.h>
30	#include <iprt/asm-amd64-x86.h>
31	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
32	# include <iprt/mem.h>
33	# include <iprt/memobj.h>
34	# include <VBox/apic.h>
35	#endif
36	#include <iprt/x86.h>
37
38
39	/*********************************************************************************************************************************
40	* Structures and Typedefs *
41	*********************************************************************************************************************************/
42	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
43	/**
44	* Local APIC mappings.
45	*/
46	typedef struct CPUMHOSTLAPIC
47	{
48	/** Indicates that the entry is in use and have valid data. */
49	bool fEnabled;
50	/** Whether it's operating in X2APIC mode (EXTD). */
51	bool fX2Apic;
52	/** The APIC version number. */
53	uint32_t uVersion;
54	/** The physical address of the APIC registers. */
55	RTHCPHYS PhysBase;
56	/** The memory object entering the physical address. */
57	RTR0MEMOBJ hMemObj;
58	/** The mapping object for hMemObj. */
59	RTR0MEMOBJ hMapObj;
60	/** The mapping address APIC registers.
61	* @remarks Different CPUs may use the same physical address to map their
62	* APICs, so this pointer is only valid when on the CPU owning the
63	* APIC. */
64	void *pv;
65	} CPUMHOSTLAPIC;
66	#endif
67
68
69	/*********************************************************************************************************************************
70	* Global Variables *
71	*********************************************************************************************************************************/
72	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
73	static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
74	#endif
75
76	/**
77	* CPUID bits to unify among all cores.
78	*/
79	static struct
80	{
81	uint32_t uLeaf; /*< Leaf to check. /
82	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
83	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
84	}
85	const g_aCpuidUnifyBits[] =
86	{
87	{
88	0x00000001,
89	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
90	X86_CPUID_FEATURE_EDX_CX8
91	}
92	};
93
94
95
96	/*********************************************************************************************************************************
97	* Internal Functions *
98	*********************************************************************************************************************************/
99	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
100	static int cpumR0MapLocalApics(void);
101	static void cpumR0UnmapLocalApics(void);
102	#endif
103	static int cpumR0SaveHostDebugState(PVMCPU pVCpu);
104
105
106	/**
107	* Does the Ring-0 CPU initialization once during module load.
108	* XXX Host-CPU hot-plugging?
109	*/
110	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
111	{
112	int rc = VINF_SUCCESS;
113	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
114	rc = cpumR0MapLocalApics();
115	#endif
116	return rc;
117	}
118
119
120	/**
121	* Terminate the module.
122	*/
123	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
124	{
125	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
126	cpumR0UnmapLocalApics();
127	#endif
128	return VINF_SUCCESS;
129	}
130
131
132	/**
133	* Check the CPUID features of this particular CPU and disable relevant features
134	* for the guest which do not exist on this CPU. We have seen systems where the
135	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
136	* @bugref{5436}.
137	*
138	* @note This function might be called simultaneously on more than one CPU!
139	*
140	* @param idCpu The identifier for the CPU the function is called on.
141	* @param pvUser1 Pointer to the VM structure.
142	* @param pvUser2 Ignored.
143	*/
144	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
145	{
146	PVM pVM = (PVM)pvUser1;
147
148	NOREF(idCpu); NOREF(pvUser2);
149	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
150	{
151	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
152	necessarily in the VM process context. So, we using the
153	legacy arrays as temporary storage. */
154
155	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
156	PCPUMCPUID pLegacyLeaf;
157	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
158	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
159	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
160	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
161	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
162	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
163	else
164	continue;
165
166	uint32_t eax, ebx, ecx, edx;
167	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
168
169	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
170	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
171	}
172	}
173
174
175	/**
176	* Does Ring-0 CPUM initialization.
177	*
178	* This is mainly to check that the Host CPU mode is compatible
179	* with VBox.
180	*
181	* @returns VBox status code.
182	* @param pVM The cross context VM structure.
183	*/
184	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM)
185	{
186	LogFlow(("CPUMR0Init: %p\n", pVM));
187
188	/*
189	* Check CR0 & CR4 flags.
190	*/
191	uint32_t u32CR0 = ASMGetCR0();
192	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
193	{
194	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
195	return VERR_UNSUPPORTED_CPU_MODE;
196	}
197
198	/*
199	* Check for sysenter and syscall usage.
200	*/
201	if (ASMHasCpuId())
202	{
203	/*
204	* SYSENTER/SYSEXIT
205	*
206	* Intel docs claim you should test both the flag and family, model &
207	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
208	* but don't support it. AMD CPUs may support this feature in legacy
209	* mode, they've banned it from long mode. Since we switch to 32-bit
210	* mode when entering raw-mode context the feature would become
211	* accessible again on AMD CPUs, so we have to check regardless of
212	* host bitness.
213	*/
214	uint32_t u32CpuVersion;
215	uint32_t u32Dummy;
216	uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
217	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
218	uint32_t const u32Family = u32CpuVersion >> 8;
219	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
220	uint32_t const u32Stepping = u32CpuVersion & 0xF;
221	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
222	&& ( u32Family != 6 /* (> pentium pro) */
223	\|\| u32Model >= 3
224	\|\| u32Stepping >= 3
225	\|\| !ASMIsIntelCpu())
226	)
227	{
228	/*
229	* Read the MSR and see if it's in use or not.
230	*/
231	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
232	if (u32)
233	{
234	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
235	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
236	}
237	}
238
239	/*
240	* SYSCALL/SYSRET
241	*
242	* This feature is indicated by the SEP bit returned in EDX by CPUID
243	* function 0x80000001. Intel CPUs only supports this feature in
244	* long mode. Since we're not running 64-bit guests in raw-mode there
245	* are no issues with 32-bit intel hosts.
246	*/
247	uint32_t cExt = 0;
248	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
249	if (ASMIsValidExtRange(cExt))
250	{
251	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
252	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
253	{
254	#ifdef RT_ARCH_X86
255	if (!ASMIsIntelCpu())
256	#endif
257	{
258	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
259	if (fEfer & MSR_K6_EFER_SCE)
260	{
261	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
262	Log(("CPUMR0Init: host uses syscall\n"));
263	}
264	}
265	}
266	}
267
268	/*
269	* Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host feature structure.
270	*/
271	pVM->cpum.s.HostFeatures.fArchRdclNo = 0;
272	pVM->cpum.s.HostFeatures.fArchIbrsAll = 0;
273	pVM->cpum.s.HostFeatures.fArchRsbOverride = 0;
274	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
275	uint32_t const cStdRange = ASMCpuId_EAX(0);
276	if ( ASMIsValidStdRange(cStdRange)
277	&& cStdRange >= 7)
278	{
279	uint32_t fEdxFeatures = ASMCpuId_EDX(7);
280	if ( (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
281	&& (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
282	{
283	uint64_t const fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
284	pVM->cpum.s.HostFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
285	pVM->cpum.s.HostFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
286	pVM->cpum.s.HostFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
287	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
288	}
289	else
290	pVM->cpum.s.HostFeatures.fArchCap = 0;
291	}
292
293	/*
294	* Unify/cross check some CPUID feature bits on all available CPU cores
295	* and threads. We've seen CPUs where the monitor support differed.
296	*
297	* Because the hyper heap isn't always mapped into ring-0, we cannot
298	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
299	* as temp ring-0 accessible memory instead, ASSUMING that they're all
300	* up to date when we get here.
301	*/
302	RTMpOnAll(cpumR0CheckCpuid, pVM, NULL);
303
304	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
305	{
306	bool fIgnored;
307	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
308	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
309	if (pLeaf)
310	{
311	PCPUMCPUID pLegacyLeaf;
312	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
313	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
314	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
315	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
316	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
317	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
318	else
319	continue;
320
321	pLeaf->uEcx = pLegacyLeaf->uEcx;
322	pLeaf->uEdx = pLegacyLeaf->uEdx;
323	}
324	}
325
326	}
327
328
329	/*
330	* Check if debug registers are armed.
331	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
332	*/
333	uint32_t u32DR7 = ASMGetDR7();
334	if (u32DR7 & X86_DR7_ENABLED_MASK)
335	{
336	for (VMCPUID i = 0; i < pVM->cCpus; i++)
337	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
338	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
339	}
340
341	return VINF_SUCCESS;
342	}
343
344
345	/**
346	* Trap handler for device-not-available fault (\#NM).
347	* Device not available, FP or (F)WAIT instruction.
348	*
349	* @returns VBox status code.
350	* @retval VINF_SUCCESS if the guest FPU state is loaded.
351	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
352	* @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
353	*
354	* @param pVM The cross context VM structure.
355	* @param pVCpu The cross context virtual CPU structure.
356	*/
357	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu)
358	{
359	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
360	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
361
362	/* If the FPU state has already been loaded, then it's a guest trap. */
363	if (CPUMIsGuestFPUStateActive(pVCpu))
364	{
365	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
366	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
367	return VINF_EM_RAW_GUEST_TRAP;
368	}
369
370	/*
371	* There are two basic actions:
372	* 1. Save host fpu and restore guest fpu.
373	* 2. Generate guest trap.
374	*
375	* When entering the hypervisor we'll always enable MP (for proper wait
376	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
377	* is taken from the guest OS in order to get proper SSE handling.
378	*
379	*
380	* Actions taken depending on the guest CR0 flags:
381	*
382	* 3 2 1
383	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
384	* ------------------------------------------------------------------------
385	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
386	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
387	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
388	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
389	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
390	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
391	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
392	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
393	*/
394
395	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
396	{
397	case X86_CR0_MP \| X86_CR0_TS:
398	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
399	return VINF_EM_RAW_GUEST_TRAP;
400	default:
401	break;
402	}
403
404	return CPUMR0LoadGuestFPU(pVM, pVCpu);
405	}
406
407
408	/**
409	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
410	* state into the CPU.
411	*
412	* @returns VINF_SUCCESS on success, host CR0 unmodified.
413	* @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
414	* modified and VT-x needs to update the value in the VMCS.
415	*
416	* @param pVM The cross context VM structure.
417	* @param pVCpu The cross context virtual CPU structure.
418	*/
419	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu)
420	{
421	int rc = VINF_SUCCESS;
422	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
423	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
424	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
425
426	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
427	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
428	{
429	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
430
431	/* Save the host state if necessary. */
432	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST))
433	rc = cpumRZSaveHostFPUState(&pVCpu->cpum.s);
434
435	/* Restore the state on entry as we need to be in 64-bit mode to access the full state. */
436	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
437
438	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
439	== (CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
440	}
441	else
442	#endif
443	{
444	if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
445	{
446	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
447	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
448	}
449	else
450	{
451	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
452	/** @todo r=ramshankar: Can't we used a cached value here
453	* instead of reading the MSR? host EFER doesn't usually
454	* change. */
455	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
456	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
457	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
458	else
459	{
460	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
461	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
462	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
463	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
464	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
465	ASMSetFlags(uSavedFlags);
466	}
467	}
468	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
469	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
470	}
471	return rc;
472	}
473
474
475	/**
476	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
477	* needed.
478	*
479	* @returns true if we saved the guest state.
480	* @param pVCpu The cross context virtual CPU structure.
481	*/
482	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu)
483	{
484	bool fSavedGuest;
485	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
486	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
487	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
488	{
489	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
490	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
491	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
492	{
493	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
494	{
495	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
496	HMR0SaveFPUState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
497	}
498	else
499	pVCpu->cpum.s.fUseFlags &= ~CPUM_SYNC_FPU_STATE;
500	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
501	}
502	else
503	#endif
504	{
505	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
506	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
507	else
508	{
509	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
510	save/restore the XMM state with fxsave/fxrstor. */
511	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
512	if (uHostEfer & MSR_K6_EFER_FFXSR)
513	{
514	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
515	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
516	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
517	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
518	ASMSetFlags(uSavedFlags);
519	}
520	else
521	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
522	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
523	}
524	}
525	}
526	else
527	fSavedGuest = false;
528	Assert(!( pVCpu->cpum.s.fUseFlags
529	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_SYNC_FPU_STATE \| CPUM_USED_MANUAL_XMM_RESTORE)));
530	return fSavedGuest;
531	}
532
533
534	/**
535	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
536	* DR7 with safe values.
537	*
538	* @returns VBox status code.
539	* @param pVCpu The cross context virtual CPU structure.
540	*/
541	static int cpumR0SaveHostDebugState(PVMCPU pVCpu)
542	{
543	/*
544	* Save the host state.
545	*/
546	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
547	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
548	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
549	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
550	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
551	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
552	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
553
554	/* Preemption paranoia. */
555	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
556
557	/*
558	* Make sure DR7 is harmless or else we could trigger breakpoints when
559	* load guest or hypervisor DRx values later.
560	*/
561	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
562	ASMSetDR7(X86_DR7_INIT_VAL);
563
564	return VINF_SUCCESS;
565	}
566
567
568	/**
569	* Saves the guest DRx state residing in host registers and restore the host
570	* register values.
571	*
572	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
573	* since it's assumed that we're shadowing the guest DRx register values
574	* accurately when using the combined hypervisor debug register values
575	* (CPUMR0LoadHyperDebugState).
576	*
577	* @returns true if either guest or hypervisor debug registers were loaded.
578	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
579	* @param fDr6 Whether to include DR6 or not.
580	* @thread EMT(pVCpu)
581	*/
582	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6)
583	{
584	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
585	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
586
587	/*
588	* Do we need to save the guest DRx registered loaded into host registers?
589	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
590	*/
591	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
592	{
593	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
594	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
595	{
596	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
597	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
598	if (!fDr6)
599	pVCpu->cpum.s.Guest.dr[6] = uDr6;
600	}
601	else
602	#endif
603	{
604	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
605	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
606	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
607	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
608	if (fDr6)
609	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
610	}
611	}
612	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~( CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER
613	\| CPUM_SYNC_DEBUG_REGS_GUEST \| CPUM_SYNC_DEBUG_REGS_HYPER));
614
615	/*
616	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
617	*/
618	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
619	{
620	/* A bit of paranoia first... */
621	uint64_t uCurDR7 = ASMGetDR7();
622	if (uCurDR7 != X86_DR7_INIT_VAL)
623	ASMSetDR7(X86_DR7_INIT_VAL);
624
625	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
626	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
627	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
628	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
629	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
630	* expensive DRx reads are over DRx writes. */
631	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
632	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
633
634	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
635	}
636
637	return fDrXLoaded;
638	}
639
640
641	/**
642	* Saves the guest DRx state if it resides host registers.
643	*
644	* This does NOT clear any use flags, so the host registers remains loaded with
645	* the guest DRx state upon return. The purpose is only to make sure the values
646	* in the CPU context structure is up to date.
647	*
648	* @returns true if the host registers contains guest values, false if not.
649	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
650	* @param fDr6 Whether to include DR6 or not.
651	* @thread EMT(pVCpu)
652	*/
653	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6)
654	{
655	/*
656	* Do we need to save the guest DRx registered loaded into host registers?
657	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
658	*/
659	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
660	{
661	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
662	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
663	{
664	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
665	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
666	if (!fDr6)
667	pVCpu->cpum.s.Guest.dr[6] = uDr6;
668	}
669	else
670	#endif
671	{
672	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
673	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
674	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
675	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
676	if (fDr6)
677	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
678	}
679	return true;
680	}
681	return false;
682	}
683
684
685	/**
686	* Lazily sync in the debug state.
687	*
688	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
689	* @param fDr6 Whether to include DR6 or not.
690	* @thread EMT(pVCpu)
691	*/
692	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6)
693	{
694	/*
695	* Save the host state and disarm all host BPs.
696	*/
697	cpumR0SaveHostDebugState(pVCpu);
698	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
699
700	/*
701	* Activate the guest state DR0-3.
702	* DR7 and DR6 (if fDr6 is true) are left to the caller.
703	*/
704	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
705	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
706	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_GUEST); /* Postpone it to the world switch. */
707	else
708	#endif
709	{
710	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
711	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
712	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
713	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
714	if (fDr6)
715	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
716
717	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
718	}
719	}
720
721
722	/**
723	* Lazily sync in the hypervisor debug state
724	*
725	* @returns VBox status code.
726	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
727	* @param fDr6 Whether to include DR6 or not.
728	* @thread EMT(pVCpu)
729	*/
730	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6)
731	{
732	/*
733	* Save the host state and disarm all host BPs.
734	*/
735	cpumR0SaveHostDebugState(pVCpu);
736	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
737
738	/*
739	* Make sure the hypervisor values are up to date.
740	*/
741	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */, true);
742
743	/*
744	* Activate the guest state DR0-3.
745	* DR7 and DR6 (if fDr6 is true) are left to the caller.
746	*/
747	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
748	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
749	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_HYPER); /* Postpone it. */
750	else
751	#endif
752	{
753	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
754	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
755	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
756	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
757	if (fDr6)
758	ASMSetDR6(X86_DR6_INIT_VAL);
759
760	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
761	}
762	}
763
764	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
765
766	/**
767	* Per-CPU callback that probes the CPU for APIC support.
768	*
769	* @param idCpu The identifier for the CPU the function is called on.
770	* @param pvUser1 Ignored.
771	* @param pvUser2 Ignored.
772	*/
773	static DECLCALLBACK(void) cpumR0MapLocalApicCpuProber(RTCPUID idCpu, void pvUser1, void pvUser2)
774	{
775	NOREF(pvUser1); NOREF(pvUser2);
776	int iCpu = RTMpCpuIdToSetIndex(idCpu);
777	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
778
779	/*
780	* Check for APIC support.
781	*/
782	uint32_t uMaxLeaf, u32EBX, u32ECX, u32EDX;
783	ASMCpuId(0, &uMaxLeaf, &u32EBX, &u32ECX, &u32EDX);
784	if ( ( ASMIsIntelCpuEx(u32EBX, u32ECX, u32EDX)
785	\|\| ASMIsAmdCpuEx(u32EBX, u32ECX, u32EDX)
786	\|\| ASMIsViaCentaurCpuEx(u32EBX, u32ECX, u32EDX)
787	\|\| ASMIsShanghaiCpuEx(u32EBX, u32ECX, u32EDX))
788	&& ASMIsValidStdRange(uMaxLeaf))
789	{
790	uint32_t uDummy;
791	ASMCpuId(1, &uDummy, &u32EBX, &u32ECX, &u32EDX);
792	if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
793	&& (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
794	{
795	/*
796	* Safe to access the MSR. Read it and calc the BASE (a little complicated).
797	*/
798	uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
799	uint64_t u64Mask = MSR_IA32_APICBASE_BASE_MIN;
800
801	/* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
802	uint32_t uMaxExtLeaf;
803	ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX);
804	if ( uMaxExtLeaf >= UINT32_C(0x80000008)
805	&& ASMIsValidExtRange(uMaxExtLeaf))
806	{
807	uint32_t u32PhysBits;
808	ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
809	u32PhysBits &= 0xff;
810	u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
811	}
812
813	AssertCompile(sizeof(g_aLApics[iCpu].PhysBase) == sizeof(u64ApicBase));
814	g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
815	g_aLApics[iCpu].fEnabled = RT_BOOL(u64ApicBase & MSR_IA32_APICBASE_EN);
816	g_aLApics[iCpu].fX2Apic = (u64ApicBase & (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN))
817	== (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN);
818	}
819	}
820	}
821
822
823
824	/**
825	* Per-CPU callback that verifies our APIC expectations.
826	*
827	* @param idCpu The identifier for the CPU the function is called on.
828	* @param pvUser1 Ignored.
829	* @param pvUser2 Ignored.
830	*/
831	static DECLCALLBACK(void) cpumR0MapLocalApicCpuChecker(RTCPUID idCpu, void pvUser1, void pvUser2)
832	{
833	NOREF(pvUser1); NOREF(pvUser2);
834
835	int iCpu = RTMpCpuIdToSetIndex(idCpu);
836	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
837	if (!g_aLApics[iCpu].fEnabled)
838	return;
839
840	/*
841	* 0x0X 82489 external APIC
842	* 0x1X Local APIC
843	* 0x2X..0xFF reserved
844	*/
845	uint32_t uApicVersion;
846	if (g_aLApics[iCpu].fX2Apic)
847	uApicVersion = ApicX2RegRead32(APIC_REG_VERSION);
848	else
849	uApicVersion = ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_VERSION);
850	if ((APIC_REG_VERSION_GET_VER(uApicVersion) & 0xF0) == 0x10)
851	{
852	g_aLApics[iCpu].uVersion = uApicVersion;
853
854	#if 0 /* enable if you need it. */
855	if (g_aLApics[iCpu].fX2Apic)
856	SUPR0Printf("CPUM: X2APIC %02u - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
857	iCpu, uApicVersion,
858	ApicX2RegRead32(APIC_REG_LVT_LINT0), ApicX2RegRead32(APIC_REG_LVT_LINT1),
859	ApicX2RegRead32(APIC_REG_LVT_PC), ApicX2RegRead32(APIC_REG_LVT_THMR),
860	ApicX2RegRead32(APIC_REG_LVT_CMCI));
861	else
862	{
863	SUPR0Printf("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
864	iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, uApicVersion,
865	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT0), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT1),
866	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_PC), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_THMR),
867	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_CMCI));
868	if (uApicVersion & 0x80000000)
869	{
870	uint32_t uExtFeatures = ApicRegRead(g_aLApics[iCpu].pv, 0x400);
871	uint32_t cEiLvt = (uExtFeatures >> 16) & 0xff;
872	SUPR0Printf("CPUM: APIC %02u: ExtSpace available. extfeat=%08x eilvt[0..3]=%08x %08x %08x %08x\n",
873	iCpu,
874	ApicRegRead(g_aLApics[iCpu].pv, 0x400),
875	cEiLvt >= 1 ? ApicRegRead(g_aLApics[iCpu].pv, 0x500) : 0,
876	cEiLvt >= 2 ? ApicRegRead(g_aLApics[iCpu].pv, 0x510) : 0,
877	cEiLvt >= 3 ? ApicRegRead(g_aLApics[iCpu].pv, 0x520) : 0,
878	cEiLvt >= 4 ? ApicRegRead(g_aLApics[iCpu].pv, 0x530) : 0);
879	}
880	}
881	#endif
882	}
883	else
884	{
885	g_aLApics[iCpu].fEnabled = false;
886	g_aLApics[iCpu].fX2Apic = false;
887	SUPR0Printf("VBox/CPUM: Unsupported APIC version %#x (iCpu=%d)\n", uApicVersion, iCpu);
888	}
889	}
890
891
892	/**
893	* Map the MMIO page of each local APIC in the system.
894	*/
895	static int cpumR0MapLocalApics(void)
896	{
897	/*
898	* Check that we'll always stay within the array bounds.
899	*/
900	if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
901	{
902	LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
903	return VERR_TOO_MANY_CPUS;
904	}
905
906	/*
907	* Create mappings for all online CPUs we think have legacy APICs.
908	*/
909	int rc = RTMpOnAll(cpumR0MapLocalApicCpuProber, NULL, NULL);
910
911	for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
912	{
913	if (g_aLApics[iCpu].fEnabled && !g_aLApics[iCpu].fX2Apic)
914	{
915	rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
916	PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
917	if (RT_SUCCESS(rc))
918	{
919	rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
920	PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
921	if (RT_SUCCESS(rc))
922	{
923	g_aLApics[iCpu].pv = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
924	continue;
925	}
926	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
927	}
928	g_aLApics[iCpu].fEnabled = false;
929	}
930	g_aLApics[iCpu].pv = NULL;
931	}
932
933	/*
934	* Check the APICs.
935	*/
936	if (RT_SUCCESS(rc))
937	rc = RTMpOnAll(cpumR0MapLocalApicCpuChecker, NULL, NULL);
938
939	if (RT_FAILURE(rc))
940	{
941	cpumR0UnmapLocalApics();
942	return rc;
943	}
944
945	#ifdef LOG_ENABLED
946	/*
947	* Log the result (pretty useless, requires enabling CPUM in VBoxDrv
948	* and !VBOX_WITH_R0_LOGGING).
949	*/
950	if (LogIsEnabled())
951	{
952	uint32_t cEnabled = 0;
953	uint32_t cX2Apics = 0;
954	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
955	if (g_aLApics[iCpu].fEnabled)
956	{
957	cEnabled++;
958	cX2Apics += g_aLApics[iCpu].fX2Apic;
959	}
960	Log(("CPUM: %u APICs, %u X2APICs\n", cEnabled, cX2Apics));
961	}
962	#endif
963
964	return VINF_SUCCESS;
965	}
966
967
968	/**
969	* Unmap the Local APIC of all host CPUs.
970	*/
971	static void cpumR0UnmapLocalApics(void)
972	{
973	for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
974	{
975	if (g_aLApics[iCpu].pv)
976	{
977	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
978	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
979	g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
980	g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
981	g_aLApics[iCpu].fEnabled = false;
982	g_aLApics[iCpu].fX2Apic = false;
983	g_aLApics[iCpu].pv = NULL;
984	}
985	}
986	}
987
988
989	/**
990	* Updates CPUMCPU::pvApicBase and CPUMCPU::fX2Apic prior to world switch.
991	*
992	* Writes the Local APIC mapping address of the current host CPU to CPUMCPU so
993	* the world switchers can access the APIC registers for the purpose of
994	* disabling and re-enabling the NMIs. Must be called with disabled preemption
995	* or disabled interrupts!
996	*
997	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
998	* @param iHostCpuSet The CPU set index of the current host CPU.
999	*/
1000	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet)
1001	{
1002	Assert(iHostCpuSet <= RT_ELEMENTS(g_aLApics));
1003	pVCpu->cpum.s.pvApicBase = g_aLApics[iHostCpuSet].pv;
1004	pVCpu->cpum.s.fX2Apic = g_aLApics[iHostCpuSet].fX2Apic;
1005	// Log6(("CPUMR0SetLApic: pvApicBase=%p fX2Apic=%d\n", g_aLApics[idxCpu].pv, g_aLApics[idxCpu].fX2Apic));
1006	}
1007
1008	#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */
1009

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 78402

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