CPUMR0.cpp@ 78613

Last change on this file since 78613 was 78431, checked in by vboxsync, 6 years ago
VMM: Started refactoring GVM & VM structures for bugref:9217
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1	/* $Id: CPUMR0.cpp 78431 2019-05-07 14:01:45Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/gvm.h>
27	#include <VBox/err.h>
28	#include <VBox/log.h>
29	#include <VBox/vmm/hm.h>
30	#include <iprt/assert.h>
31	#include <iprt/asm-amd64-x86.h>
32	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
33	# include <iprt/mem.h>
34	# include <iprt/memobj.h>
35	# include <VBox/apic.h>
36	#endif
37	#include <iprt/x86.h>
38
39
40	/*********************************************************************************************************************************
41	* Structures and Typedefs *
42	*********************************************************************************************************************************/
43	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
44	/**
45	* Local APIC mappings.
46	*/
47	typedef struct CPUMHOSTLAPIC
48	{
49	/** Indicates that the entry is in use and have valid data. */
50	bool fEnabled;
51	/** Whether it's operating in X2APIC mode (EXTD). */
52	bool fX2Apic;
53	/** The APIC version number. */
54	uint32_t uVersion;
55	/** The physical address of the APIC registers. */
56	RTHCPHYS PhysBase;
57	/** The memory object entering the physical address. */
58	RTR0MEMOBJ hMemObj;
59	/** The mapping object for hMemObj. */
60	RTR0MEMOBJ hMapObj;
61	/** The mapping address APIC registers.
62	* @remarks Different CPUs may use the same physical address to map their
63	* APICs, so this pointer is only valid when on the CPU owning the
64	* APIC. */
65	void *pv;
66	} CPUMHOSTLAPIC;
67	#endif
68
69
70	/*********************************************************************************************************************************
71	* Global Variables *
72	*********************************************************************************************************************************/
73	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
74	static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
75	#endif
76
77	/**
78	* CPUID bits to unify among all cores.
79	*/
80	static struct
81	{
82	uint32_t uLeaf; /*< Leaf to check. /
83	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
84	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
85	}
86	const g_aCpuidUnifyBits[] =
87	{
88	{
89	0x00000001,
90	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
91	X86_CPUID_FEATURE_EDX_CX8
92	}
93	};
94
95
96
97	/*********************************************************************************************************************************
98	* Internal Functions *
99	*********************************************************************************************************************************/
100	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
101	static int cpumR0MapLocalApics(void);
102	static void cpumR0UnmapLocalApics(void);
103	#endif
104	static int cpumR0SaveHostDebugState(PVMCPU pVCpu);
105
106
107	/**
108	* Does the Ring-0 CPU initialization once during module load.
109	* XXX Host-CPU hot-plugging?
110	*/
111	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
112	{
113	int rc = VINF_SUCCESS;
114	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
115	rc = cpumR0MapLocalApics();
116	#endif
117	return rc;
118	}
119
120
121	/**
122	* Terminate the module.
123	*/
124	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
125	{
126	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
127	cpumR0UnmapLocalApics();
128	#endif
129	return VINF_SUCCESS;
130	}
131
132
133	/**
134	* Check the CPUID features of this particular CPU and disable relevant features
135	* for the guest which do not exist on this CPU. We have seen systems where the
136	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
137	* @bugref{5436}.
138	*
139	* @note This function might be called simultaneously on more than one CPU!
140	*
141	* @param idCpu The identifier for the CPU the function is called on.
142	* @param pvUser1 Pointer to the VM structure.
143	* @param pvUser2 Ignored.
144	*/
145	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
146	{
147	PVM pVM = (PVM)pvUser1;
148
149	NOREF(idCpu); NOREF(pvUser2);
150	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
151	{
152	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
153	necessarily in the VM process context. So, we using the
154	legacy arrays as temporary storage. */
155
156	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
157	PCPUMCPUID pLegacyLeaf;
158	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
159	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
160	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
161	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
162	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
163	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
164	else
165	continue;
166
167	uint32_t eax, ebx, ecx, edx;
168	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
169
170	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
171	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
172	}
173	}
174
175
176	/**
177	* Does Ring-0 CPUM initialization.
178	*
179	* This is mainly to check that the Host CPU mode is compatible
180	* with VBox.
181	*
182	* @returns VBox status code.
183	* @param pVM The cross context VM structure.
184	*/
185	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM)
186	{
187	LogFlow(("CPUMR0Init: %p\n", pVM));
188
189	/*
190	* Check CR0 & CR4 flags.
191	*/
192	uint32_t u32CR0 = ASMGetCR0();
193	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
194	{
195	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
196	return VERR_UNSUPPORTED_CPU_MODE;
197	}
198
199	/*
200	* Check for sysenter and syscall usage.
201	*/
202	if (ASMHasCpuId())
203	{
204	/*
205	* SYSENTER/SYSEXIT
206	*
207	* Intel docs claim you should test both the flag and family, model &
208	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
209	* but don't support it. AMD CPUs may support this feature in legacy
210	* mode, they've banned it from long mode. Since we switch to 32-bit
211	* mode when entering raw-mode context the feature would become
212	* accessible again on AMD CPUs, so we have to check regardless of
213	* host bitness.
214	*/
215	uint32_t u32CpuVersion;
216	uint32_t u32Dummy;
217	uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
218	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
219	uint32_t const u32Family = u32CpuVersion >> 8;
220	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
221	uint32_t const u32Stepping = u32CpuVersion & 0xF;
222	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
223	&& ( u32Family != 6 /* (> pentium pro) */
224	\|\| u32Model >= 3
225	\|\| u32Stepping >= 3
226	\|\| !ASMIsIntelCpu())
227	)
228	{
229	/*
230	* Read the MSR and see if it's in use or not.
231	*/
232	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
233	if (u32)
234	{
235	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
236	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
237	}
238	}
239
240	/*
241	* SYSCALL/SYSRET
242	*
243	* This feature is indicated by the SEP bit returned in EDX by CPUID
244	* function 0x80000001. Intel CPUs only supports this feature in
245	* long mode. Since we're not running 64-bit guests in raw-mode there
246	* are no issues with 32-bit intel hosts.
247	*/
248	uint32_t cExt = 0;
249	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
250	if (ASMIsValidExtRange(cExt))
251	{
252	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
253	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
254	{
255	#ifdef RT_ARCH_X86
256	if (!ASMIsIntelCpu())
257	#endif
258	{
259	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
260	if (fEfer & MSR_K6_EFER_SCE)
261	{
262	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
263	Log(("CPUMR0Init: host uses syscall\n"));
264	}
265	}
266	}
267	}
268
269	/*
270	* Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host feature structure.
271	*/
272	pVM->cpum.s.HostFeatures.fArchRdclNo = 0;
273	pVM->cpum.s.HostFeatures.fArchIbrsAll = 0;
274	pVM->cpum.s.HostFeatures.fArchRsbOverride = 0;
275	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
276	uint32_t const cStdRange = ASMCpuId_EAX(0);
277	if ( ASMIsValidStdRange(cStdRange)
278	&& cStdRange >= 7)
279	{
280	uint32_t fEdxFeatures = ASMCpuId_EDX(7);
281	if ( (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
282	&& (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
283	{
284	uint64_t const fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
285	pVM->cpum.s.HostFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
286	pVM->cpum.s.HostFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
287	pVM->cpum.s.HostFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
288	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
289	}
290	else
291	pVM->cpum.s.HostFeatures.fArchCap = 0;
292	}
293
294	/*
295	* Unify/cross check some CPUID feature bits on all available CPU cores
296	* and threads. We've seen CPUs where the monitor support differed.
297	*
298	* Because the hyper heap isn't always mapped into ring-0, we cannot
299	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
300	* as temp ring-0 accessible memory instead, ASSUMING that they're all
301	* up to date when we get here.
302	*/
303	RTMpOnAll(cpumR0CheckCpuid, pVM, NULL);
304
305	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
306	{
307	bool fIgnored;
308	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
309	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
310	if (pLeaf)
311	{
312	PCPUMCPUID pLegacyLeaf;
313	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
314	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
315	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
316	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
317	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
318	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
319	else
320	continue;
321
322	pLeaf->uEcx = pLegacyLeaf->uEcx;
323	pLeaf->uEdx = pLegacyLeaf->uEdx;
324	}
325	}
326
327	}
328
329
330	/*
331	* Check if debug registers are armed.
332	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
333	*/
334	uint32_t u32DR7 = ASMGetDR7();
335	if (u32DR7 & X86_DR7_ENABLED_MASK)
336	{
337	#ifdef VBOX_BUGREF_9217
338	PGVM pGVM = (PGVM)pVM;
339	for (VMCPUID i = 0; i < pGVM->cCpusSafe; i++)
340	pGVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
341	#else
342	for (VMCPUID i = 0; i < pVM->cCpus; i++)
343	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
344	#endif
345	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
346	}
347
348	return VINF_SUCCESS;
349	}
350
351
352	/**
353	* Trap handler for device-not-available fault (\#NM).
354	* Device not available, FP or (F)WAIT instruction.
355	*
356	* @returns VBox status code.
357	* @retval VINF_SUCCESS if the guest FPU state is loaded.
358	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
359	* @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
360	*
361	* @param pVM The cross context VM structure.
362	* @param pVCpu The cross context virtual CPU structure.
363	*/
364	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu)
365	{
366	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
367	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
368
369	/* If the FPU state has already been loaded, then it's a guest trap. */
370	if (CPUMIsGuestFPUStateActive(pVCpu))
371	{
372	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
373	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
374	return VINF_EM_RAW_GUEST_TRAP;
375	}
376
377	/*
378	* There are two basic actions:
379	* 1. Save host fpu and restore guest fpu.
380	* 2. Generate guest trap.
381	*
382	* When entering the hypervisor we'll always enable MP (for proper wait
383	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
384	* is taken from the guest OS in order to get proper SSE handling.
385	*
386	*
387	* Actions taken depending on the guest CR0 flags:
388	*
389	* 3 2 1
390	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
391	* ------------------------------------------------------------------------
392	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
393	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
394	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
395	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
396	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
397	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
398	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
399	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
400	*/
401
402	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
403	{
404	case X86_CR0_MP \| X86_CR0_TS:
405	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
406	return VINF_EM_RAW_GUEST_TRAP;
407	default:
408	break;
409	}
410
411	return CPUMR0LoadGuestFPU(pVM, pVCpu);
412	}
413
414
415	/**
416	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
417	* state into the CPU.
418	*
419	* @returns VINF_SUCCESS on success, host CR0 unmodified.
420	* @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
421	* modified and VT-x needs to update the value in the VMCS.
422	*
423	* @param pVM The cross context VM structure.
424	* @param pVCpu The cross context virtual CPU structure.
425	*/
426	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu)
427	{
428	int rc = VINF_SUCCESS;
429	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
430	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
431	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
432
433	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
434	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
435	{
436	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
437
438	/* Save the host state if necessary. */
439	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST))
440	rc = cpumRZSaveHostFPUState(&pVCpu->cpum.s);
441
442	/* Restore the state on entry as we need to be in 64-bit mode to access the full state. */
443	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
444
445	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
446	== (CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
447	}
448	else
449	#endif
450	{
451	if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
452	{
453	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
454	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
455	}
456	else
457	{
458	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
459	/** @todo r=ramshankar: Can't we used a cached value here
460	* instead of reading the MSR? host EFER doesn't usually
461	* change. */
462	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
463	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
464	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
465	else
466	{
467	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
468	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
469	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
470	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
471	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
472	ASMSetFlags(uSavedFlags);
473	}
474	}
475	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
476	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
477	}
478	return rc;
479	}
480
481
482	/**
483	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
484	* needed.
485	*
486	* @returns true if we saved the guest state.
487	* @param pVCpu The cross context virtual CPU structure.
488	*/
489	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu)
490	{
491	bool fSavedGuest;
492	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
493	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
494	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
495	{
496	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
497	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
498	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
499	{
500	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
501	{
502	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
503	HMR0SaveFPUState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
504	}
505	else
506	pVCpu->cpum.s.fUseFlags &= ~CPUM_SYNC_FPU_STATE;
507	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
508	}
509	else
510	#endif
511	{
512	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
513	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
514	else
515	{
516	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
517	save/restore the XMM state with fxsave/fxrstor. */
518	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
519	if (uHostEfer & MSR_K6_EFER_FFXSR)
520	{
521	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
522	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
523	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
524	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
525	ASMSetFlags(uSavedFlags);
526	}
527	else
528	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
529	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
530	}
531	}
532	}
533	else
534	fSavedGuest = false;
535	Assert(!( pVCpu->cpum.s.fUseFlags
536	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_SYNC_FPU_STATE \| CPUM_USED_MANUAL_XMM_RESTORE)));
537	return fSavedGuest;
538	}
539
540
541	/**
542	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
543	* DR7 with safe values.
544	*
545	* @returns VBox status code.
546	* @param pVCpu The cross context virtual CPU structure.
547	*/
548	static int cpumR0SaveHostDebugState(PVMCPU pVCpu)
549	{
550	/*
551	* Save the host state.
552	*/
553	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
554	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
555	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
556	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
557	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
558	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
559	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
560
561	/* Preemption paranoia. */
562	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
563
564	/*
565	* Make sure DR7 is harmless or else we could trigger breakpoints when
566	* load guest or hypervisor DRx values later.
567	*/
568	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
569	ASMSetDR7(X86_DR7_INIT_VAL);
570
571	return VINF_SUCCESS;
572	}
573
574
575	/**
576	* Saves the guest DRx state residing in host registers and restore the host
577	* register values.
578	*
579	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
580	* since it's assumed that we're shadowing the guest DRx register values
581	* accurately when using the combined hypervisor debug register values
582	* (CPUMR0LoadHyperDebugState).
583	*
584	* @returns true if either guest or hypervisor debug registers were loaded.
585	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
586	* @param fDr6 Whether to include DR6 or not.
587	* @thread EMT(pVCpu)
588	*/
589	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6)
590	{
591	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
592	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
593
594	/*
595	* Do we need to save the guest DRx registered loaded into host registers?
596	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
597	*/
598	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
599	{
600	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
601	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
602	{
603	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
604	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
605	if (!fDr6)
606	pVCpu->cpum.s.Guest.dr[6] = uDr6;
607	}
608	else
609	#endif
610	{
611	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
612	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
613	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
614	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
615	if (fDr6)
616	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
617	}
618	}
619	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~( CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER
620	\| CPUM_SYNC_DEBUG_REGS_GUEST \| CPUM_SYNC_DEBUG_REGS_HYPER));
621
622	/*
623	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
624	*/
625	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
626	{
627	/* A bit of paranoia first... */
628	uint64_t uCurDR7 = ASMGetDR7();
629	if (uCurDR7 != X86_DR7_INIT_VAL)
630	ASMSetDR7(X86_DR7_INIT_VAL);
631
632	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
633	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
634	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
635	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
636	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
637	* expensive DRx reads are over DRx writes. */
638	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
639	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
640
641	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
642	}
643
644	return fDrXLoaded;
645	}
646
647
648	/**
649	* Saves the guest DRx state if it resides host registers.
650	*
651	* This does NOT clear any use flags, so the host registers remains loaded with
652	* the guest DRx state upon return. The purpose is only to make sure the values
653	* in the CPU context structure is up to date.
654	*
655	* @returns true if the host registers contains guest values, false if not.
656	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
657	* @param fDr6 Whether to include DR6 or not.
658	* @thread EMT(pVCpu)
659	*/
660	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6)
661	{
662	/*
663	* Do we need to save the guest DRx registered loaded into host registers?
664	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
665	*/
666	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
667	{
668	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
669	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
670	{
671	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
672	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
673	if (!fDr6)
674	pVCpu->cpum.s.Guest.dr[6] = uDr6;
675	}
676	else
677	#endif
678	{
679	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
680	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
681	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
682	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
683	if (fDr6)
684	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
685	}
686	return true;
687	}
688	return false;
689	}
690
691
692	/**
693	* Lazily sync in the debug state.
694	*
695	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
696	* @param fDr6 Whether to include DR6 or not.
697	* @thread EMT(pVCpu)
698	*/
699	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6)
700	{
701	/*
702	* Save the host state and disarm all host BPs.
703	*/
704	cpumR0SaveHostDebugState(pVCpu);
705	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
706
707	/*
708	* Activate the guest state DR0-3.
709	* DR7 and DR6 (if fDr6 is true) are left to the caller.
710	*/
711	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
712	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
713	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_GUEST); /* Postpone it to the world switch. */
714	else
715	#endif
716	{
717	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
718	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
719	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
720	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
721	if (fDr6)
722	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
723
724	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
725	}
726	}
727
728
729	/**
730	* Lazily sync in the hypervisor debug state
731	*
732	* @returns VBox status code.
733	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
734	* @param fDr6 Whether to include DR6 or not.
735	* @thread EMT(pVCpu)
736	*/
737	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6)
738	{
739	/*
740	* Save the host state and disarm all host BPs.
741	*/
742	cpumR0SaveHostDebugState(pVCpu);
743	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
744
745	/*
746	* Make sure the hypervisor values are up to date.
747	*/
748	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */, true);
749
750	/*
751	* Activate the guest state DR0-3.
752	* DR7 and DR6 (if fDr6 is true) are left to the caller.
753	*/
754	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
755	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
756	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_HYPER); /* Postpone it. */
757	else
758	#endif
759	{
760	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
761	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
762	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
763	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
764	if (fDr6)
765	ASMSetDR6(X86_DR6_INIT_VAL);
766
767	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
768	}
769	}
770
771	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
772
773	/**
774	* Per-CPU callback that probes the CPU for APIC support.
775	*
776	* @param idCpu The identifier for the CPU the function is called on.
777	* @param pvUser1 Ignored.
778	* @param pvUser2 Ignored.
779	*/
780	static DECLCALLBACK(void) cpumR0MapLocalApicCpuProber(RTCPUID idCpu, void pvUser1, void pvUser2)
781	{
782	NOREF(pvUser1); NOREF(pvUser2);
783	int iCpu = RTMpCpuIdToSetIndex(idCpu);
784	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
785
786	/*
787	* Check for APIC support.
788	*/
789	uint32_t uMaxLeaf, u32EBX, u32ECX, u32EDX;
790	ASMCpuId(0, &uMaxLeaf, &u32EBX, &u32ECX, &u32EDX);
791	if ( ( ASMIsIntelCpuEx(u32EBX, u32ECX, u32EDX)
792	\|\| ASMIsAmdCpuEx(u32EBX, u32ECX, u32EDX)
793	\|\| ASMIsViaCentaurCpuEx(u32EBX, u32ECX, u32EDX)
794	\|\| ASMIsShanghaiCpuEx(u32EBX, u32ECX, u32EDX))
795	&& ASMIsValidStdRange(uMaxLeaf))
796	{
797	uint32_t uDummy;
798	ASMCpuId(1, &uDummy, &u32EBX, &u32ECX, &u32EDX);
799	if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
800	&& (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
801	{
802	/*
803	* Safe to access the MSR. Read it and calc the BASE (a little complicated).
804	*/
805	uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
806	uint64_t u64Mask = MSR_IA32_APICBASE_BASE_MIN;
807
808	/* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
809	uint32_t uMaxExtLeaf;
810	ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX);
811	if ( uMaxExtLeaf >= UINT32_C(0x80000008)
812	&& ASMIsValidExtRange(uMaxExtLeaf))
813	{
814	uint32_t u32PhysBits;
815	ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
816	u32PhysBits &= 0xff;
817	u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
818	}
819
820	AssertCompile(sizeof(g_aLApics[iCpu].PhysBase) == sizeof(u64ApicBase));
821	g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
822	g_aLApics[iCpu].fEnabled = RT_BOOL(u64ApicBase & MSR_IA32_APICBASE_EN);
823	g_aLApics[iCpu].fX2Apic = (u64ApicBase & (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN))
824	== (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN);
825	}
826	}
827	}
828
829
830
831	/**
832	* Per-CPU callback that verifies our APIC expectations.
833	*
834	* @param idCpu The identifier for the CPU the function is called on.
835	* @param pvUser1 Ignored.
836	* @param pvUser2 Ignored.
837	*/
838	static DECLCALLBACK(void) cpumR0MapLocalApicCpuChecker(RTCPUID idCpu, void pvUser1, void pvUser2)
839	{
840	NOREF(pvUser1); NOREF(pvUser2);
841
842	int iCpu = RTMpCpuIdToSetIndex(idCpu);
843	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
844	if (!g_aLApics[iCpu].fEnabled)
845	return;
846
847	/*
848	* 0x0X 82489 external APIC
849	* 0x1X Local APIC
850	* 0x2X..0xFF reserved
851	*/
852	uint32_t uApicVersion;
853	if (g_aLApics[iCpu].fX2Apic)
854	uApicVersion = ApicX2RegRead32(APIC_REG_VERSION);
855	else
856	uApicVersion = ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_VERSION);
857	if ((APIC_REG_VERSION_GET_VER(uApicVersion) & 0xF0) == 0x10)
858	{
859	g_aLApics[iCpu].uVersion = uApicVersion;
860
861	#if 0 /* enable if you need it. */
862	if (g_aLApics[iCpu].fX2Apic)
863	SUPR0Printf("CPUM: X2APIC %02u - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
864	iCpu, uApicVersion,
865	ApicX2RegRead32(APIC_REG_LVT_LINT0), ApicX2RegRead32(APIC_REG_LVT_LINT1),
866	ApicX2RegRead32(APIC_REG_LVT_PC), ApicX2RegRead32(APIC_REG_LVT_THMR),
867	ApicX2RegRead32(APIC_REG_LVT_CMCI));
868	else
869	{
870	SUPR0Printf("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
871	iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, uApicVersion,
872	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT0), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT1),
873	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_PC), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_THMR),
874	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_CMCI));
875	if (uApicVersion & 0x80000000)
876	{
877	uint32_t uExtFeatures = ApicRegRead(g_aLApics[iCpu].pv, 0x400);
878	uint32_t cEiLvt = (uExtFeatures >> 16) & 0xff;
879	SUPR0Printf("CPUM: APIC %02u: ExtSpace available. extfeat=%08x eilvt[0..3]=%08x %08x %08x %08x\n",
880	iCpu,
881	ApicRegRead(g_aLApics[iCpu].pv, 0x400),
882	cEiLvt >= 1 ? ApicRegRead(g_aLApics[iCpu].pv, 0x500) : 0,
883	cEiLvt >= 2 ? ApicRegRead(g_aLApics[iCpu].pv, 0x510) : 0,
884	cEiLvt >= 3 ? ApicRegRead(g_aLApics[iCpu].pv, 0x520) : 0,
885	cEiLvt >= 4 ? ApicRegRead(g_aLApics[iCpu].pv, 0x530) : 0);
886	}
887	}
888	#endif
889	}
890	else
891	{
892	g_aLApics[iCpu].fEnabled = false;
893	g_aLApics[iCpu].fX2Apic = false;
894	SUPR0Printf("VBox/CPUM: Unsupported APIC version %#x (iCpu=%d)\n", uApicVersion, iCpu);
895	}
896	}
897
898
899	/**
900	* Map the MMIO page of each local APIC in the system.
901	*/
902	static int cpumR0MapLocalApics(void)
903	{
904	/*
905	* Check that we'll always stay within the array bounds.
906	*/
907	if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
908	{
909	LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
910	return VERR_TOO_MANY_CPUS;
911	}
912
913	/*
914	* Create mappings for all online CPUs we think have legacy APICs.
915	*/
916	int rc = RTMpOnAll(cpumR0MapLocalApicCpuProber, NULL, NULL);
917
918	for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
919	{
920	if (g_aLApics[iCpu].fEnabled && !g_aLApics[iCpu].fX2Apic)
921	{
922	rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
923	PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
924	if (RT_SUCCESS(rc))
925	{
926	rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
927	PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
928	if (RT_SUCCESS(rc))
929	{
930	g_aLApics[iCpu].pv = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
931	continue;
932	}
933	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
934	}
935	g_aLApics[iCpu].fEnabled = false;
936	}
937	g_aLApics[iCpu].pv = NULL;
938	}
939
940	/*
941	* Check the APICs.
942	*/
943	if (RT_SUCCESS(rc))
944	rc = RTMpOnAll(cpumR0MapLocalApicCpuChecker, NULL, NULL);
945
946	if (RT_FAILURE(rc))
947	{
948	cpumR0UnmapLocalApics();
949	return rc;
950	}
951
952	#ifdef LOG_ENABLED
953	/*
954	* Log the result (pretty useless, requires enabling CPUM in VBoxDrv
955	* and !VBOX_WITH_R0_LOGGING).
956	*/
957	if (LogIsEnabled())
958	{
959	uint32_t cEnabled = 0;
960	uint32_t cX2Apics = 0;
961	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
962	if (g_aLApics[iCpu].fEnabled)
963	{
964	cEnabled++;
965	cX2Apics += g_aLApics[iCpu].fX2Apic;
966	}
967	Log(("CPUM: %u APICs, %u X2APICs\n", cEnabled, cX2Apics));
968	}
969	#endif
970
971	return VINF_SUCCESS;
972	}
973
974
975	/**
976	* Unmap the Local APIC of all host CPUs.
977	*/
978	static void cpumR0UnmapLocalApics(void)
979	{
980	for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
981	{
982	if (g_aLApics[iCpu].pv)
983	{
984	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
985	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
986	g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
987	g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
988	g_aLApics[iCpu].fEnabled = false;
989	g_aLApics[iCpu].fX2Apic = false;
990	g_aLApics[iCpu].pv = NULL;
991	}
992	}
993	}
994
995
996	/**
997	* Updates CPUMCPU::pvApicBase and CPUMCPU::fX2Apic prior to world switch.
998	*
999	* Writes the Local APIC mapping address of the current host CPU to CPUMCPU so
1000	* the world switchers can access the APIC registers for the purpose of
1001	* disabling and re-enabling the NMIs. Must be called with disabled preemption
1002	* or disabled interrupts!
1003	*
1004	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1005	* @param iHostCpuSet The CPU set index of the current host CPU.
1006	*/
1007	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet)
1008	{
1009	Assert(iHostCpuSet <= RT_ELEMENTS(g_aLApics));
1010	pVCpu->cpum.s.pvApicBase = g_aLApics[iHostCpuSet].pv;
1011	pVCpu->cpum.s.fX2Apic = g_aLApics[iHostCpuSet].fX2Apic;
1012	// Log6(("CPUMR0SetLApic: pvApicBase=%p fX2Apic=%d\n", g_aLApics[idxCpu].pv, g_aLApics[idxCpu].fX2Apic));
1013	}
1014
1015	#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */
1016

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 78613

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