CPUMR0.cpp@ 79812

Last change on this file since 79812 was 78632, checked in by vboxsync, 6 years ago
Forward ported 130474,130475,130477,130479. bugref:9453
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1	/* $Id: CPUMR0.cpp 78632 2019-05-21 13:56:11Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/gvm.h>
27	#include <VBox/err.h>
28	#include <VBox/log.h>
29	#include <VBox/vmm/hm.h>
30	#include <iprt/assert.h>
31	#include <iprt/asm-amd64-x86.h>
32	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
33	# include <iprt/mem.h>
34	# include <iprt/memobj.h>
35	# include <VBox/apic.h>
36	#endif
37	#include <iprt/x86.h>
38
39
40	/*********************************************************************************************************************************
41	* Structures and Typedefs *
42	*********************************************************************************************************************************/
43	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
44	/**
45	* Local APIC mappings.
46	*/
47	typedef struct CPUMHOSTLAPIC
48	{
49	/** Indicates that the entry is in use and have valid data. */
50	bool fEnabled;
51	/** Whether it's operating in X2APIC mode (EXTD). */
52	bool fX2Apic;
53	/** The APIC version number. */
54	uint32_t uVersion;
55	/** The physical address of the APIC registers. */
56	RTHCPHYS PhysBase;
57	/** The memory object entering the physical address. */
58	RTR0MEMOBJ hMemObj;
59	/** The mapping object for hMemObj. */
60	RTR0MEMOBJ hMapObj;
61	/** The mapping address APIC registers.
62	* @remarks Different CPUs may use the same physical address to map their
63	* APICs, so this pointer is only valid when on the CPU owning the
64	* APIC. */
65	void *pv;
66	} CPUMHOSTLAPIC;
67	#endif
68
69
70	/*********************************************************************************************************************************
71	* Global Variables *
72	*********************************************************************************************************************************/
73	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
74	static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
75	#endif
76
77	/**
78	* CPUID bits to unify among all cores.
79	*/
80	static struct
81	{
82	uint32_t uLeaf; /*< Leaf to check. /
83	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
84	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
85	}
86	const g_aCpuidUnifyBits[] =
87	{
88	{
89	0x00000001,
90	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
91	X86_CPUID_FEATURE_EDX_CX8
92	}
93	};
94
95
96
97	/*********************************************************************************************************************************
98	* Internal Functions *
99	*********************************************************************************************************************************/
100	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
101	static int cpumR0MapLocalApics(void);
102	static void cpumR0UnmapLocalApics(void);
103	#endif
104	static int cpumR0SaveHostDebugState(PVMCPU pVCpu);
105
106
107	/**
108	* Does the Ring-0 CPU initialization once during module load.
109	* XXX Host-CPU hot-plugging?
110	*/
111	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
112	{
113	int rc = VINF_SUCCESS;
114	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
115	rc = cpumR0MapLocalApics();
116	#endif
117	return rc;
118	}
119
120
121	/**
122	* Terminate the module.
123	*/
124	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
125	{
126	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
127	cpumR0UnmapLocalApics();
128	#endif
129	return VINF_SUCCESS;
130	}
131
132
133	/**
134	* Check the CPUID features of this particular CPU and disable relevant features
135	* for the guest which do not exist on this CPU. We have seen systems where the
136	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
137	* @bugref{5436}.
138	*
139	* @note This function might be called simultaneously on more than one CPU!
140	*
141	* @param idCpu The identifier for the CPU the function is called on.
142	* @param pvUser1 Pointer to the VM structure.
143	* @param pvUser2 Ignored.
144	*/
145	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
146	{
147	PVM pVM = (PVM)pvUser1;
148
149	NOREF(idCpu); NOREF(pvUser2);
150	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
151	{
152	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
153	necessarily in the VM process context. So, we using the
154	legacy arrays as temporary storage. */
155
156	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
157	PCPUMCPUID pLegacyLeaf;
158	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
159	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
160	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
161	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
162	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
163	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
164	else
165	continue;
166
167	uint32_t eax, ebx, ecx, edx;
168	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
169
170	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
171	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
172	}
173	}
174
175
176	/**
177	* Does Ring-0 CPUM initialization.
178	*
179	* This is mainly to check that the Host CPU mode is compatible
180	* with VBox.
181	*
182	* @returns VBox status code.
183	* @param pVM The cross context VM structure.
184	*/
185	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM)
186	{
187	LogFlow(("CPUMR0Init: %p\n", pVM));
188
189	/*
190	* Check CR0 & CR4 flags.
191	*/
192	uint32_t u32CR0 = ASMGetCR0();
193	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
194	{
195	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
196	return VERR_UNSUPPORTED_CPU_MODE;
197	}
198
199	/*
200	* Check for sysenter and syscall usage.
201	*/
202	if (ASMHasCpuId())
203	{
204	/*
205	* SYSENTER/SYSEXIT
206	*
207	* Intel docs claim you should test both the flag and family, model &
208	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
209	* but don't support it. AMD CPUs may support this feature in legacy
210	* mode, they've banned it from long mode. Since we switch to 32-bit
211	* mode when entering raw-mode context the feature would become
212	* accessible again on AMD CPUs, so we have to check regardless of
213	* host bitness.
214	*/
215	uint32_t u32CpuVersion;
216	uint32_t u32Dummy;
217	uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
218	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
219	uint32_t const u32Family = u32CpuVersion >> 8;
220	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
221	uint32_t const u32Stepping = u32CpuVersion & 0xF;
222	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
223	&& ( u32Family != 6 /* (> pentium pro) */
224	\|\| u32Model >= 3
225	\|\| u32Stepping >= 3
226	\|\| !ASMIsIntelCpu())
227	)
228	{
229	/*
230	* Read the MSR and see if it's in use or not.
231	*/
232	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
233	if (u32)
234	{
235	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
236	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
237	}
238	}
239
240	/*
241	* SYSCALL/SYSRET
242	*
243	* This feature is indicated by the SEP bit returned in EDX by CPUID
244	* function 0x80000001. Intel CPUs only supports this feature in
245	* long mode. Since we're not running 64-bit guests in raw-mode there
246	* are no issues with 32-bit intel hosts.
247	*/
248	uint32_t cExt = 0;
249	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
250	if (ASMIsValidExtRange(cExt))
251	{
252	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
253	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
254	{
255	#ifdef RT_ARCH_X86
256	if (!ASMIsIntelCpu())
257	#endif
258	{
259	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
260	if (fEfer & MSR_K6_EFER_SCE)
261	{
262	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
263	Log(("CPUMR0Init: host uses syscall\n"));
264	}
265	}
266	}
267	}
268
269	/*
270	* Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host and guest feature
271	* structure and as well as the guest MSR.
272	*/
273	pVM->cpum.s.HostFeatures.fArchRdclNo = 0;
274	pVM->cpum.s.HostFeatures.fArchIbrsAll = 0;
275	pVM->cpum.s.HostFeatures.fArchRsbOverride = 0;
276	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
277	pVM->cpum.s.HostFeatures.fArchMdsNo = 0;
278	uint32_t const cStdRange = ASMCpuId_EAX(0);
279	if ( ASMIsValidStdRange(cStdRange)
280	&& cStdRange >= 7)
281	{
282	uint32_t fEdxFeatures = ASMCpuId_EDX(7);
283	if ( (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
284	&& (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
285	{
286	uint64_t const fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
287	pVM->cpum.s.GuestFeatures.fArchRdclNo
288	= pVM->cpum.s.HostFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
289	pVM->cpum.s.GuestFeatures.fArchIbrsAll
290	= pVM->cpum.s.HostFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
291	pVM->cpum.s.GuestFeatures.fArchRsbOverride
292	= pVM->cpum.s.HostFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
293	pVM->cpum.s.GuestFeatures.fArchVmmNeedNotFlushL1d
294	= pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
295	pVM->cpum.s.GuestFeatures.fArchMdsNo
296	= pVM->cpum.s.HostFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
297
298	if (pVM->cpum.s.GuestFeatures.fArchCap)
299	for (VMCPUID i = 0; i < pVM->cCpus; i++)
300	pVM->aCpus[i].cpum.s.GuestMsrs.msr.ArchCaps = fArchVal;
301	}
302	else
303	pVM->cpum.s.HostFeatures.fArchCap = 0;
304	}
305
306	/*
307	* Unify/cross check some CPUID feature bits on all available CPU cores
308	* and threads. We've seen CPUs where the monitor support differed.
309	*
310	* Because the hyper heap isn't always mapped into ring-0, we cannot
311	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
312	* as temp ring-0 accessible memory instead, ASSUMING that they're all
313	* up to date when we get here.
314	*/
315	RTMpOnAll(cpumR0CheckCpuid, pVM, NULL);
316
317	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
318	{
319	bool fIgnored;
320	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
321	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
322	if (pLeaf)
323	{
324	PCPUMCPUID pLegacyLeaf;
325	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
326	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
327	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
328	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
329	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
330	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
331	else
332	continue;
333
334	pLeaf->uEcx = pLegacyLeaf->uEcx;
335	pLeaf->uEdx = pLegacyLeaf->uEdx;
336	}
337	}
338
339	}
340
341
342	/*
343	* Check if debug registers are armed.
344	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
345	*/
346	uint32_t u32DR7 = ASMGetDR7();
347	if (u32DR7 & X86_DR7_ENABLED_MASK)
348	{
349	#ifdef VBOX_BUGREF_9217
350	PGVM pGVM = (PGVM)pVM;
351	for (VMCPUID i = 0; i < pGVM->cCpusSafe; i++)
352	pGVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
353	#else
354	for (VMCPUID i = 0; i < pVM->cCpus; i++)
355	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
356	#endif
357	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
358	}
359
360	return VINF_SUCCESS;
361	}
362
363
364	/**
365	* Trap handler for device-not-available fault (\#NM).
366	* Device not available, FP or (F)WAIT instruction.
367	*
368	* @returns VBox status code.
369	* @retval VINF_SUCCESS if the guest FPU state is loaded.
370	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
371	* @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
372	*
373	* @param pVM The cross context VM structure.
374	* @param pVCpu The cross context virtual CPU structure.
375	*/
376	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu)
377	{
378	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
379	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
380
381	/* If the FPU state has already been loaded, then it's a guest trap. */
382	if (CPUMIsGuestFPUStateActive(pVCpu))
383	{
384	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
385	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
386	return VINF_EM_RAW_GUEST_TRAP;
387	}
388
389	/*
390	* There are two basic actions:
391	* 1. Save host fpu and restore guest fpu.
392	* 2. Generate guest trap.
393	*
394	* When entering the hypervisor we'll always enable MP (for proper wait
395	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
396	* is taken from the guest OS in order to get proper SSE handling.
397	*
398	*
399	* Actions taken depending on the guest CR0 flags:
400	*
401	* 3 2 1
402	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
403	* ------------------------------------------------------------------------
404	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
405	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
406	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
407	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
408	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
409	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
410	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
411	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
412	*/
413
414	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
415	{
416	case X86_CR0_MP \| X86_CR0_TS:
417	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
418	return VINF_EM_RAW_GUEST_TRAP;
419	default:
420	break;
421	}
422
423	return CPUMR0LoadGuestFPU(pVM, pVCpu);
424	}
425
426
427	/**
428	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
429	* state into the CPU.
430	*
431	* @returns VINF_SUCCESS on success, host CR0 unmodified.
432	* @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
433	* modified and VT-x needs to update the value in the VMCS.
434	*
435	* @param pVM The cross context VM structure.
436	* @param pVCpu The cross context virtual CPU structure.
437	*/
438	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu)
439	{
440	int rc = VINF_SUCCESS;
441	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
442	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
443	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
444
445	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
446	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
447	{
448	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
449
450	/* Save the host state if necessary. */
451	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST))
452	rc = cpumRZSaveHostFPUState(&pVCpu->cpum.s);
453
454	/* Restore the state on entry as we need to be in 64-bit mode to access the full state. */
455	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
456
457	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
458	== (CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
459	}
460	else
461	#endif
462	{
463	if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
464	{
465	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
466	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
467	}
468	else
469	{
470	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
471	/** @todo r=ramshankar: Can't we used a cached value here
472	* instead of reading the MSR? host EFER doesn't usually
473	* change. */
474	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
475	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
476	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
477	else
478	{
479	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
480	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
481	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
482	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
483	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
484	ASMSetFlags(uSavedFlags);
485	}
486	}
487	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
488	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
489	}
490	return rc;
491	}
492
493
494	/**
495	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
496	* needed.
497	*
498	* @returns true if we saved the guest state.
499	* @param pVCpu The cross context virtual CPU structure.
500	*/
501	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu)
502	{
503	bool fSavedGuest;
504	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
505	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
506	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
507	{
508	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
509	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
510	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
511	{
512	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
513	{
514	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
515	HMR0SaveFPUState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
516	}
517	else
518	pVCpu->cpum.s.fUseFlags &= ~CPUM_SYNC_FPU_STATE;
519	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
520	}
521	else
522	#endif
523	{
524	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
525	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
526	else
527	{
528	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
529	save/restore the XMM state with fxsave/fxrstor. */
530	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
531	if (uHostEfer & MSR_K6_EFER_FFXSR)
532	{
533	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
534	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
535	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
536	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
537	ASMSetFlags(uSavedFlags);
538	}
539	else
540	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
541	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
542	}
543	}
544	}
545	else
546	fSavedGuest = false;
547	Assert(!( pVCpu->cpum.s.fUseFlags
548	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_SYNC_FPU_STATE \| CPUM_USED_MANUAL_XMM_RESTORE)));
549	return fSavedGuest;
550	}
551
552
553	/**
554	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
555	* DR7 with safe values.
556	*
557	* @returns VBox status code.
558	* @param pVCpu The cross context virtual CPU structure.
559	*/
560	static int cpumR0SaveHostDebugState(PVMCPU pVCpu)
561	{
562	/*
563	* Save the host state.
564	*/
565	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
566	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
567	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
568	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
569	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
570	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
571	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
572
573	/* Preemption paranoia. */
574	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
575
576	/*
577	* Make sure DR7 is harmless or else we could trigger breakpoints when
578	* load guest or hypervisor DRx values later.
579	*/
580	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
581	ASMSetDR7(X86_DR7_INIT_VAL);
582
583	return VINF_SUCCESS;
584	}
585
586
587	/**
588	* Saves the guest DRx state residing in host registers and restore the host
589	* register values.
590	*
591	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
592	* since it's assumed that we're shadowing the guest DRx register values
593	* accurately when using the combined hypervisor debug register values
594	* (CPUMR0LoadHyperDebugState).
595	*
596	* @returns true if either guest or hypervisor debug registers were loaded.
597	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
598	* @param fDr6 Whether to include DR6 or not.
599	* @thread EMT(pVCpu)
600	*/
601	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6)
602	{
603	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
604	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
605
606	/*
607	* Do we need to save the guest DRx registered loaded into host registers?
608	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
609	*/
610	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
611	{
612	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
613	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
614	{
615	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
616	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
617	if (!fDr6)
618	pVCpu->cpum.s.Guest.dr[6] = uDr6;
619	}
620	else
621	#endif
622	{
623	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
624	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
625	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
626	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
627	if (fDr6)
628	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
629	}
630	}
631	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~( CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER
632	\| CPUM_SYNC_DEBUG_REGS_GUEST \| CPUM_SYNC_DEBUG_REGS_HYPER));
633
634	/*
635	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
636	*/
637	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
638	{
639	/* A bit of paranoia first... */
640	uint64_t uCurDR7 = ASMGetDR7();
641	if (uCurDR7 != X86_DR7_INIT_VAL)
642	ASMSetDR7(X86_DR7_INIT_VAL);
643
644	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
645	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
646	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
647	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
648	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
649	* expensive DRx reads are over DRx writes. */
650	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
651	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
652
653	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
654	}
655
656	return fDrXLoaded;
657	}
658
659
660	/**
661	* Saves the guest DRx state if it resides host registers.
662	*
663	* This does NOT clear any use flags, so the host registers remains loaded with
664	* the guest DRx state upon return. The purpose is only to make sure the values
665	* in the CPU context structure is up to date.
666	*
667	* @returns true if the host registers contains guest values, false if not.
668	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
669	* @param fDr6 Whether to include DR6 or not.
670	* @thread EMT(pVCpu)
671	*/
672	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6)
673	{
674	/*
675	* Do we need to save the guest DRx registered loaded into host registers?
676	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
677	*/
678	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
679	{
680	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
681	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
682	{
683	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
684	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
685	if (!fDr6)
686	pVCpu->cpum.s.Guest.dr[6] = uDr6;
687	}
688	else
689	#endif
690	{
691	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
692	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
693	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
694	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
695	if (fDr6)
696	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
697	}
698	return true;
699	}
700	return false;
701	}
702
703
704	/**
705	* Lazily sync in the debug state.
706	*
707	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
708	* @param fDr6 Whether to include DR6 or not.
709	* @thread EMT(pVCpu)
710	*/
711	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6)
712	{
713	/*
714	* Save the host state and disarm all host BPs.
715	*/
716	cpumR0SaveHostDebugState(pVCpu);
717	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
718
719	/*
720	* Activate the guest state DR0-3.
721	* DR7 and DR6 (if fDr6 is true) are left to the caller.
722	*/
723	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
724	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
725	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_GUEST); /* Postpone it to the world switch. */
726	else
727	#endif
728	{
729	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
730	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
731	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
732	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
733	if (fDr6)
734	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
735
736	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
737	}
738	}
739
740
741	/**
742	* Lazily sync in the hypervisor debug state
743	*
744	* @returns VBox status code.
745	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
746	* @param fDr6 Whether to include DR6 or not.
747	* @thread EMT(pVCpu)
748	*/
749	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6)
750	{
751	/*
752	* Save the host state and disarm all host BPs.
753	*/
754	cpumR0SaveHostDebugState(pVCpu);
755	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
756
757	/*
758	* Make sure the hypervisor values are up to date.
759	*/
760	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */, true);
761
762	/*
763	* Activate the guest state DR0-3.
764	* DR7 and DR6 (if fDr6 is true) are left to the caller.
765	*/
766	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
767	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
768	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_HYPER); /* Postpone it. */
769	else
770	#endif
771	{
772	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
773	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
774	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
775	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
776	if (fDr6)
777	ASMSetDR6(X86_DR6_INIT_VAL);
778
779	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
780	}
781	}
782
783	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
784
785	/**
786	* Per-CPU callback that probes the CPU for APIC support.
787	*
788	* @param idCpu The identifier for the CPU the function is called on.
789	* @param pvUser1 Ignored.
790	* @param pvUser2 Ignored.
791	*/
792	static DECLCALLBACK(void) cpumR0MapLocalApicCpuProber(RTCPUID idCpu, void pvUser1, void pvUser2)
793	{
794	NOREF(pvUser1); NOREF(pvUser2);
795	int iCpu = RTMpCpuIdToSetIndex(idCpu);
796	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
797
798	/*
799	* Check for APIC support.
800	*/
801	uint32_t uMaxLeaf, u32EBX, u32ECX, u32EDX;
802	ASMCpuId(0, &uMaxLeaf, &u32EBX, &u32ECX, &u32EDX);
803	if ( ( ASMIsIntelCpuEx(u32EBX, u32ECX, u32EDX)
804	\|\| ASMIsAmdCpuEx(u32EBX, u32ECX, u32EDX)
805	\|\| ASMIsViaCentaurCpuEx(u32EBX, u32ECX, u32EDX)
806	\|\| ASMIsShanghaiCpuEx(u32EBX, u32ECX, u32EDX))
807	&& ASMIsValidStdRange(uMaxLeaf))
808	{
809	uint32_t uDummy;
810	ASMCpuId(1, &uDummy, &u32EBX, &u32ECX, &u32EDX);
811	if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
812	&& (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
813	{
814	/*
815	* Safe to access the MSR. Read it and calc the BASE (a little complicated).
816	*/
817	uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
818	uint64_t u64Mask = MSR_IA32_APICBASE_BASE_MIN;
819
820	/* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
821	uint32_t uMaxExtLeaf;
822	ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX);
823	if ( uMaxExtLeaf >= UINT32_C(0x80000008)
824	&& ASMIsValidExtRange(uMaxExtLeaf))
825	{
826	uint32_t u32PhysBits;
827	ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
828	u32PhysBits &= 0xff;
829	u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
830	}
831
832	AssertCompile(sizeof(g_aLApics[iCpu].PhysBase) == sizeof(u64ApicBase));
833	g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
834	g_aLApics[iCpu].fEnabled = RT_BOOL(u64ApicBase & MSR_IA32_APICBASE_EN);
835	g_aLApics[iCpu].fX2Apic = (u64ApicBase & (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN))
836	== (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN);
837	}
838	}
839	}
840
841
842
843	/**
844	* Per-CPU callback that verifies our APIC expectations.
845	*
846	* @param idCpu The identifier for the CPU the function is called on.
847	* @param pvUser1 Ignored.
848	* @param pvUser2 Ignored.
849	*/
850	static DECLCALLBACK(void) cpumR0MapLocalApicCpuChecker(RTCPUID idCpu, void pvUser1, void pvUser2)
851	{
852	NOREF(pvUser1); NOREF(pvUser2);
853
854	int iCpu = RTMpCpuIdToSetIndex(idCpu);
855	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
856	if (!g_aLApics[iCpu].fEnabled)
857	return;
858
859	/*
860	* 0x0X 82489 external APIC
861	* 0x1X Local APIC
862	* 0x2X..0xFF reserved
863	*/
864	uint32_t uApicVersion;
865	if (g_aLApics[iCpu].fX2Apic)
866	uApicVersion = ApicX2RegRead32(APIC_REG_VERSION);
867	else
868	uApicVersion = ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_VERSION);
869	if ((APIC_REG_VERSION_GET_VER(uApicVersion) & 0xF0) == 0x10)
870	{
871	g_aLApics[iCpu].uVersion = uApicVersion;
872
873	#if 0 /* enable if you need it. */
874	if (g_aLApics[iCpu].fX2Apic)
875	SUPR0Printf("CPUM: X2APIC %02u - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
876	iCpu, uApicVersion,
877	ApicX2RegRead32(APIC_REG_LVT_LINT0), ApicX2RegRead32(APIC_REG_LVT_LINT1),
878	ApicX2RegRead32(APIC_REG_LVT_PC), ApicX2RegRead32(APIC_REG_LVT_THMR),
879	ApicX2RegRead32(APIC_REG_LVT_CMCI));
880	else
881	{
882	SUPR0Printf("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
883	iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, uApicVersion,
884	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT0), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT1),
885	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_PC), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_THMR),
886	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_CMCI));
887	if (uApicVersion & 0x80000000)
888	{
889	uint32_t uExtFeatures = ApicRegRead(g_aLApics[iCpu].pv, 0x400);
890	uint32_t cEiLvt = (uExtFeatures >> 16) & 0xff;
891	SUPR0Printf("CPUM: APIC %02u: ExtSpace available. extfeat=%08x eilvt[0..3]=%08x %08x %08x %08x\n",
892	iCpu,
893	ApicRegRead(g_aLApics[iCpu].pv, 0x400),
894	cEiLvt >= 1 ? ApicRegRead(g_aLApics[iCpu].pv, 0x500) : 0,
895	cEiLvt >= 2 ? ApicRegRead(g_aLApics[iCpu].pv, 0x510) : 0,
896	cEiLvt >= 3 ? ApicRegRead(g_aLApics[iCpu].pv, 0x520) : 0,
897	cEiLvt >= 4 ? ApicRegRead(g_aLApics[iCpu].pv, 0x530) : 0);
898	}
899	}
900	#endif
901	}
902	else
903	{
904	g_aLApics[iCpu].fEnabled = false;
905	g_aLApics[iCpu].fX2Apic = false;
906	SUPR0Printf("VBox/CPUM: Unsupported APIC version %#x (iCpu=%d)\n", uApicVersion, iCpu);
907	}
908	}
909
910
911	/**
912	* Map the MMIO page of each local APIC in the system.
913	*/
914	static int cpumR0MapLocalApics(void)
915	{
916	/*
917	* Check that we'll always stay within the array bounds.
918	*/
919	if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
920	{
921	LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
922	return VERR_TOO_MANY_CPUS;
923	}
924
925	/*
926	* Create mappings for all online CPUs we think have legacy APICs.
927	*/
928	int rc = RTMpOnAll(cpumR0MapLocalApicCpuProber, NULL, NULL);
929
930	for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
931	{
932	if (g_aLApics[iCpu].fEnabled && !g_aLApics[iCpu].fX2Apic)
933	{
934	rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
935	PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
936	if (RT_SUCCESS(rc))
937	{
938	rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
939	PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
940	if (RT_SUCCESS(rc))
941	{
942	g_aLApics[iCpu].pv = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
943	continue;
944	}
945	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
946	}
947	g_aLApics[iCpu].fEnabled = false;
948	}
949	g_aLApics[iCpu].pv = NULL;
950	}
951
952	/*
953	* Check the APICs.
954	*/
955	if (RT_SUCCESS(rc))
956	rc = RTMpOnAll(cpumR0MapLocalApicCpuChecker, NULL, NULL);
957
958	if (RT_FAILURE(rc))
959	{
960	cpumR0UnmapLocalApics();
961	return rc;
962	}
963
964	#ifdef LOG_ENABLED
965	/*
966	* Log the result (pretty useless, requires enabling CPUM in VBoxDrv
967	* and !VBOX_WITH_R0_LOGGING).
968	*/
969	if (LogIsEnabled())
970	{
971	uint32_t cEnabled = 0;
972	uint32_t cX2Apics = 0;
973	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
974	if (g_aLApics[iCpu].fEnabled)
975	{
976	cEnabled++;
977	cX2Apics += g_aLApics[iCpu].fX2Apic;
978	}
979	Log(("CPUM: %u APICs, %u X2APICs\n", cEnabled, cX2Apics));
980	}
981	#endif
982
983	return VINF_SUCCESS;
984	}
985
986
987	/**
988	* Unmap the Local APIC of all host CPUs.
989	*/
990	static void cpumR0UnmapLocalApics(void)
991	{
992	for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
993	{
994	if (g_aLApics[iCpu].pv)
995	{
996	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
997	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
998	g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
999	g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
1000	g_aLApics[iCpu].fEnabled = false;
1001	g_aLApics[iCpu].fX2Apic = false;
1002	g_aLApics[iCpu].pv = NULL;
1003	}
1004	}
1005	}
1006
1007
1008	/**
1009	* Updates CPUMCPU::pvApicBase and CPUMCPU::fX2Apic prior to world switch.
1010	*
1011	* Writes the Local APIC mapping address of the current host CPU to CPUMCPU so
1012	* the world switchers can access the APIC registers for the purpose of
1013	* disabling and re-enabling the NMIs. Must be called with disabled preemption
1014	* or disabled interrupts!
1015	*
1016	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1017	* @param iHostCpuSet The CPU set index of the current host CPU.
1018	*/
1019	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet)
1020	{
1021	Assert(iHostCpuSet <= RT_ELEMENTS(g_aLApics));
1022	pVCpu->cpum.s.pvApicBase = g_aLApics[iHostCpuSet].pv;
1023	pVCpu->cpum.s.fX2Apic = g_aLApics[iHostCpuSet].fX2Apic;
1024	// Log6(("CPUMR0SetLApic: pvApicBase=%p fX2Apic=%d\n", g_aLApics[idxCpu].pv, g_aLApics[idxCpu].fX2Apic));
1025	}
1026
1027	#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */
1028

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 79812

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