CPUMR0.cpp@ 94940

Last change on this file since 94940 was 94940, checked in by vboxsync, 3 years ago
VMM/CPUM: Apply cpumR0CheckCpuid to the ring-0 g_CpumHostFeatures and add MSR_IA32_ARCH_CAPABILITIES bits (also ring-0 only). bugref:10093
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1	/* $Id: CPUMR0.cpp 94940 2022-05-09 09:16:15Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#define CPUM_WITH_NONCONST_HOST_FEATURES
24	#include <VBox/vmm/cpum.h>
25	#include <VBox/vmm/hm.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vmcc.h>
28	#include <VBox/vmm/gvm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <VBox/vmm/hm.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/mem.h>
35	#include <iprt/x86.h>
36
37
38	/*********************************************************************************************************************************
39	* Global Variables *
40	*********************************************************************************************************************************/
41	/** Host CPU features. */
42	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
43	/** Static storage for host MSRs. */
44	static CPUMMSRS g_CpumHostMsrs;
45
46	/**
47	* CPUID bits to unify among all cores.
48	*/
49	static struct
50	{
51	uint32_t uLeaf; /*< Leaf to check. /
52	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
53	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
54	}
55	const g_aCpuidUnifyBits[] =
56	{
57	{
58	0x00000001,
59	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
60	X86_CPUID_FEATURE_EDX_CX8
61	}
62	};
63
64
65
66	/*********************************************************************************************************************************
67	* Internal Functions *
68	*********************************************************************************************************************************/
69	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu);
70
71
72	/**
73	* Check the CPUID features of this particular CPU and disable relevant features
74	* for the guest which do not exist on this CPU.
75	*
76	* We have seen systems where the X86_CPUID_FEATURE_ECX_MONITOR feature flag is
77	* only set on some host CPUs, see @bugref{5436}.
78	*
79	* @note This function might be called simultaneously on more than one CPU!
80	*
81	* @param idCpu The identifier for the CPU the function is called on.
82	* @param pvUser1 Leaf array.
83	* @param pvUser2 Number of leaves.
84	*/
85	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
86	{
87	PCPUMCPUIDLEAF const paLeaves = (PCPUMCPUIDLEAF)pvUser1;
88	uint32_t const cLeaves = (uint32_t)(uintptr_t)pvUser2;
89	RT_NOREF(idCpu);
90
91	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
92	{
93	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, g_aCpuidUnifyBits[i].uLeaf, 0);
94	if (pLeaf)
95	{
96	uint32_t uEax, uEbx, uEcx, uEdx;
97	ASMCpuIdExSlow(g_aCpuidUnifyBits[i].uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
98
99	ASMAtomicAndU32(&pLeaf->uEcx, uEcx \| ~g_aCpuidUnifyBits[i].uEcx);
100	ASMAtomicAndU32(&pLeaf->uEdx, uEdx \| ~g_aCpuidUnifyBits[i].uEdx);
101	}
102	}
103	}
104
105
106	/**
107	* Does the Ring-0 CPU initialization once during module load.
108	* XXX Host-CPU hot-plugging?
109	*/
110	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
111	{
112	/*
113	* Query the hardware virtualization capabilities of the host CPU first.
114	*/
115	uint32_t fHwCaps = 0;
116	int rc = SUPR0GetVTSupport(&fHwCaps);
117	AssertLogRelMsg(RT_SUCCESS(rc) \|\| rc == VERR_UNSUPPORTED_CPU \|\| rc == VERR_SVM_NO_SVM \|\| rc == VERR_VMX_NO_VMX,
118	("SUPR0GetHwvirtMsrs -> %Rrc\n", rc));
119	if (RT_SUCCESS(rc))
120	{
121	SUPHWVIRTMSRS HwvirtMsrs;
122	rc = SUPR0GetHwvirtMsrs(&HwvirtMsrs, fHwCaps, false /fIgnored/);
123	AssertLogRelRC(rc);
124	if (RT_SUCCESS(rc))
125	{
126	if (fHwCaps & SUPVTCAPS_VT_X)
127	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.vmx);
128	else
129	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.svm);
130	}
131	}
132
133	/*
134	* Collect CPUID leaves.
135	*/
136	PCPUMCPUIDLEAF paLeaves;
137	uint32_t cLeaves;
138	rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
139	AssertLogRelRCReturn(rc, rc);
140
141	/*
142	* Unify/cross check some CPUID feature bits on all available CPU cores
143	* and threads. We've seen CPUs where the monitor support differed.
144	*/
145	RTMpOnAll(cpumR0CheckCpuid, paLeaves, (void *)(uintptr_t)cLeaves);
146
147	/*
148	* Populate the host CPU feature global variable.
149	*/
150	rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &g_CpumHostMsrs, &g_CpumHostFeatures.s);
151	RTMemFree(paLeaves);
152	AssertLogRelRCReturn(rc, rc);
153
154	/*
155	* Get MSR_IA32_ARCH_CAPABILITIES and expand it into the host feature structure.
156	*/
157	if (ASMHasCpuId())
158	{
159	/** @todo Should add this MSR to CPUMMSRS and expose it via SUPDrv... */
160	g_CpumHostFeatures.s.fArchRdclNo = 0;
161	g_CpumHostFeatures.s.fArchIbrsAll = 0;
162	g_CpumHostFeatures.s.fArchRsbOverride = 0;
163	g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = 0;
164	g_CpumHostFeatures.s.fArchMdsNo = 0;
165	uint32_t const cStdRange = ASMCpuId_EAX(0);
166	if ( RTX86IsValidStdRange(cStdRange)
167	&& cStdRange >= 7)
168	{
169	uint32_t const fStdFeaturesEdx = ASMCpuId_EDX(1);
170	uint32_t fStdExtFeaturesEdx;
171	ASMCpuIdExSlow(7, 0, 0, 0, NULL, NULL, NULL, &fStdExtFeaturesEdx);
172	if ( (fStdExtFeaturesEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
173	&& (fStdFeaturesEdx & X86_CPUID_FEATURE_EDX_MSR))
174	{
175	uint64_t fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
176	g_CpumHostFeatures.s.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
177	g_CpumHostFeatures.s.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
178	g_CpumHostFeatures.s.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
179	g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
180	g_CpumHostFeatures.s.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
181	}
182	else
183	g_CpumHostFeatures.s.fArchCap = 0;
184	}
185	}
186
187	return VINF_SUCCESS;
188	}
189
190
191	/**
192	* Terminate the module.
193	*/
194	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
195	{
196	return VINF_SUCCESS;
197	}
198
199
200	/**
201	* Check the CPUID features of this particular CPU and disable relevant features
202	* for the guest which do not exist on this CPU. We have seen systems where the
203	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
204	* @bugref{5436}.
205	*
206	* @note This function might be called simultaneously on more than one CPU!
207	*
208	* @param idCpu The identifier for the CPU the function is called on.
209	* @param pvUser1 Pointer to the VM structure.
210	* @param pvUser2 Ignored.
211	*/
212	static DECLCALLBACK(void) cpumR0CheckCpuidLegacy(RTCPUID idCpu, void pvUser1, void pvUser2)
213	{
214	PVMCC pVM = (PVMCC)pvUser1;
215
216	NOREF(idCpu); NOREF(pvUser2);
217	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
218	{
219	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
220	necessarily in the VM process context. So, we using the
221	legacy arrays as temporary storage. */
222
223	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
224	PCPUMCPUID pLegacyLeaf;
225	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
226	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
227	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
228	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
229	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
230	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
231	else
232	continue;
233
234	uint32_t eax, ebx, ecx, edx;
235	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
236
237	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
238	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
239	}
240	}
241
242
243	/**
244	* Does Ring-0 CPUM initialization.
245	*
246	* This is mainly to check that the Host CPU mode is compatible
247	* with VBox.
248	*
249	* @returns VBox status code.
250	* @param pVM The cross context VM structure.
251	*/
252	VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM)
253	{
254	LogFlow(("CPUMR0Init: %p\n", pVM));
255	AssertCompile(sizeof(pVM->aCpus[0].cpum.s.Host.abXState) >= sizeof(pVM->aCpus[0].cpum.s.Guest.abXState));
256
257	/*
258	* Check CR0 & CR4 flags.
259	*/
260	uint32_t u32CR0 = ASMGetCR0();
261	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
262	{
263	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
264	return VERR_UNSUPPORTED_CPU_MODE;
265	}
266
267	/*
268	* Check for sysenter and syscall usage.
269	*/
270	if (ASMHasCpuId())
271	{
272	/*
273	* SYSENTER/SYSEXIT
274	*
275	* Intel docs claim you should test both the flag and family, model &
276	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
277	* but don't support it. AMD CPUs may support this feature in legacy
278	* mode, they've banned it from long mode. Since we switch to 32-bit
279	* mode when entering raw-mode context the feature would become
280	* accessible again on AMD CPUs, so we have to check regardless of
281	* host bitness.
282	*/
283	uint32_t u32CpuVersion;
284	uint32_t u32Dummy;
285	uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
286	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
287	uint32_t const u32Family = u32CpuVersion >> 8;
288	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
289	uint32_t const u32Stepping = u32CpuVersion & 0xF;
290	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
291	&& ( u32Family != 6 /* (> pentium pro) */
292	\|\| u32Model >= 3
293	\|\| u32Stepping >= 3
294	\|\| !ASMIsIntelCpu())
295	)
296	{
297	/*
298	* Read the MSR and see if it's in use or not.
299	*/
300	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
301	if (u32)
302	{
303	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
304	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
305	}
306	}
307
308	/*
309	* SYSCALL/SYSRET
310	*
311	* This feature is indicated by the SEP bit returned in EDX by CPUID
312	* function 0x80000001. Intel CPUs only supports this feature in
313	* long mode. Since we're not running 64-bit guests in raw-mode there
314	* are no issues with 32-bit intel hosts.
315	*/
316	uint32_t cExt = 0;
317	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
318	if (RTX86IsValidExtRange(cExt))
319	{
320	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
321	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
322	{
323	#ifdef RT_ARCH_X86
324	if (!ASMIsIntelCpu())
325	#endif
326	{
327	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
328	if (fEfer & MSR_K6_EFER_SCE)
329	{
330	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
331	Log(("CPUMR0Init: host uses syscall\n"));
332	}
333	}
334	}
335	}
336
337	/*
338	* Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host and guest feature
339	* structure and as well as the guest MSR.
340	* Note! we assume this happens after the CPUMR3Init is done, so CPUID bits are settled.
341	*/
342	pVM->cpum.s.HostFeatures.fArchRdclNo = 0;
343	pVM->cpum.s.HostFeatures.fArchIbrsAll = 0;
344	pVM->cpum.s.HostFeatures.fArchRsbOverride = 0;
345	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
346	pVM->cpum.s.HostFeatures.fArchMdsNo = 0;
347	uint32_t const cStdRange = ASMCpuId_EAX(0);
348	if ( RTX86IsValidStdRange(cStdRange)
349	&& cStdRange >= 7)
350	{
351	uint32_t fEdxFeatures = ASMCpuId_EDX(7);
352	if ( (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
353	&& (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
354	{
355	/* Host: */
356	uint64_t fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
357	pVM->cpum.s.HostFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
358	pVM->cpum.s.HostFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
359	pVM->cpum.s.HostFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
360	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
361	pVM->cpum.s.HostFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
362
363	/* guest: */
364	if (!pVM->cpum.s.GuestFeatures.fArchCap)
365	fArchVal = 0;
366	else if (!pVM->cpum.s.GuestFeatures.fIbrs)
367	fArchVal &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL;
368	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps = fArchVal);
369	pVM->cpum.s.GuestFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
370	pVM->cpum.s.GuestFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
371	pVM->cpum.s.GuestFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
372	pVM->cpum.s.GuestFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
373	pVM->cpum.s.GuestFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
374	}
375	else
376	pVM->cpum.s.HostFeatures.fArchCap = 0;
377	}
378
379	/*
380	* Unify/cross check some CPUID feature bits on all available CPU cores
381	* and threads. We've seen CPUs where the monitor support differed.
382	*
383	* Because the hyper heap isn't always mapped into ring-0, we cannot
384	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
385	* as temp ring-0 accessible memory instead, ASSUMING that they're all
386	* up to date when we get here.
387	*/
388	RTMpOnAll(cpumR0CheckCpuidLegacy, pVM, NULL);
389
390	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
391	{
392	bool fIgnored;
393	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
394	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
395	if (pLeaf)
396	{
397	PCPUMCPUID pLegacyLeaf;
398	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
399	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
400	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
401	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
402	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
403	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
404	else
405	continue;
406
407	pLeaf->uEcx = pLegacyLeaf->uEcx;
408	pLeaf->uEdx = pLegacyLeaf->uEdx;
409	}
410	}
411
412	}
413
414
415	/*
416	* Check if debug registers are armed.
417	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
418	*/
419	uint32_t u32DR7 = ASMGetDR7();
420	if (u32DR7 & X86_DR7_ENABLED_MASK)
421	{
422	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST);
423	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
424	}
425
426	return VINF_SUCCESS;
427	}
428
429
430	/**
431	* Trap handler for device-not-available fault (\#NM).
432	* Device not available, FP or (F)WAIT instruction.
433	*
434	* @returns VBox status code.
435	* @retval VINF_SUCCESS if the guest FPU state is loaded.
436	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
437	* @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
438	*
439	* @param pVM The cross context VM structure.
440	* @param pVCpu The cross context virtual CPU structure.
441	*/
442	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu)
443	{
444	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
445	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
446
447	/* If the FPU state has already been loaded, then it's a guest trap. */
448	if (CPUMIsGuestFPUStateActive(pVCpu))
449	{
450	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
451	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
452	return VINF_EM_RAW_GUEST_TRAP;
453	}
454
455	/*
456	* There are two basic actions:
457	* 1. Save host fpu and restore guest fpu.
458	* 2. Generate guest trap.
459	*
460	* When entering the hypervisor we'll always enable MP (for proper wait
461	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
462	* is taken from the guest OS in order to get proper SSE handling.
463	*
464	*
465	* Actions taken depending on the guest CR0 flags:
466	*
467	* 3 2 1
468	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
469	* ------------------------------------------------------------------------
470	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
471	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
472	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
473	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
474	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
475	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
476	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
477	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
478	*/
479
480	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
481	{
482	case X86_CR0_MP \| X86_CR0_TS:
483	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
484	return VINF_EM_RAW_GUEST_TRAP;
485	default:
486	break;
487	}
488
489	return CPUMR0LoadGuestFPU(pVM, pVCpu);
490	}
491
492
493	/**
494	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
495	* state into the CPU.
496	*
497	* @returns VINF_SUCCESS on success, host CR0 unmodified.
498	* @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
499	* modified and VT-x needs to update the value in the VMCS.
500	*
501	* @param pVM The cross context VM structure.
502	* @param pVCpu The cross context virtual CPU structure.
503	*/
504	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu)
505	{
506	int rc;
507	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
508	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
509
510	if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
511	{
512	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
513	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
514	}
515	else
516	{
517	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
518	/** @todo r=ramshankar: Can't we used a cached value here
519	* instead of reading the MSR? host EFER doesn't usually
520	* change. */
521	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
522	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
523	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
524	else
525	{
526	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
527	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
528	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
529	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
530	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
531	ASMSetFlags(uSavedFlags);
532	}
533	}
534	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
535	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
536	Assert(pVCpu->cpum.s.Guest.fUsedFpuGuest);
537	return rc;
538	}
539
540
541	/**
542	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
543	* needed.
544	*
545	* @returns true if we saved the guest state.
546	* @param pVCpu The cross context virtual CPU structure.
547	*/
548	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu)
549	{
550	bool fSavedGuest;
551	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
552	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
553	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
554	{
555	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
556	Assert(fSavedGuest == pVCpu->cpum.s.Guest.fUsedFpuGuest);
557	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
558	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
559	else
560	{
561	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
562	save/restore the XMM state with fxsave/fxrstor. */
563	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
564	if (uHostEfer & MSR_K6_EFER_FFXSR)
565	{
566	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
567	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
568	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
569	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
570	ASMSetFlags(uSavedFlags);
571	}
572	else
573	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
574	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
575	}
576	}
577	else
578	fSavedGuest = false;
579	Assert(!( pVCpu->cpum.s.fUseFlags
580	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_MANUAL_XMM_RESTORE)));
581	Assert(!pVCpu->cpum.s.Guest.fUsedFpuGuest);
582	return fSavedGuest;
583	}
584
585
586	/**
587	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
588	* DR7 with safe values.
589	*
590	* @returns VBox status code.
591	* @param pVCpu The cross context virtual CPU structure.
592	*/
593	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu)
594	{
595	/*
596	* Save the host state.
597	*/
598	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
599	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
600	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
601	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
602	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
603	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
604	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
605
606	/* Preemption paranoia. */
607	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
608
609	/*
610	* Make sure DR7 is harmless or else we could trigger breakpoints when
611	* load guest or hypervisor DRx values later.
612	*/
613	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
614	ASMSetDR7(X86_DR7_INIT_VAL);
615
616	return VINF_SUCCESS;
617	}
618
619
620	/**
621	* Saves the guest DRx state residing in host registers and restore the host
622	* register values.
623	*
624	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
625	* since it's assumed that we're shadowing the guest DRx register values
626	* accurately when using the combined hypervisor debug register values
627	* (CPUMR0LoadHyperDebugState).
628	*
629	* @returns true if either guest or hypervisor debug registers were loaded.
630	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
631	* @param fDr6 Whether to include DR6 or not.
632	* @thread EMT(pVCpu)
633	*/
634	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6)
635	{
636	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
637	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
638
639	/*
640	* Do we need to save the guest DRx registered loaded into host registers?
641	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
642	*/
643	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
644	{
645	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
646	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
647	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
648	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
649	if (fDr6)
650	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
651	}
652	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~(CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
653
654	/*
655	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
656	*/
657	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
658	{
659	/* A bit of paranoia first... */
660	uint64_t uCurDR7 = ASMGetDR7();
661	if (uCurDR7 != X86_DR7_INIT_VAL)
662	ASMSetDR7(X86_DR7_INIT_VAL);
663
664	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
665	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
666	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
667	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
668	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
669	* expensive DRx reads are over DRx writes. */
670	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
671	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
672
673	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
674	}
675
676	return fDrXLoaded;
677	}
678
679
680	/**
681	* Saves the guest DRx state if it resides host registers.
682	*
683	* This does NOT clear any use flags, so the host registers remains loaded with
684	* the guest DRx state upon return. The purpose is only to make sure the values
685	* in the CPU context structure is up to date.
686	*
687	* @returns true if the host registers contains guest values, false if not.
688	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
689	* @param fDr6 Whether to include DR6 or not.
690	* @thread EMT(pVCpu)
691	*/
692	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6)
693	{
694	/*
695	* Do we need to save the guest DRx registered loaded into host registers?
696	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
697	*/
698	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
699	{
700	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
701	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
702	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
703	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
704	if (fDr6)
705	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
706	return true;
707	}
708	return false;
709	}
710
711
712	/**
713	* Lazily sync in the debug state.
714	*
715	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
716	* @param fDr6 Whether to include DR6 or not.
717	* @thread EMT(pVCpu)
718	*/
719	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6)
720	{
721	/*
722	* Save the host state and disarm all host BPs.
723	*/
724	cpumR0SaveHostDebugState(pVCpu);
725	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
726
727	/*
728	* Activate the guest state DR0-3.
729	* DR7 and DR6 (if fDr6 is true) are left to the caller.
730	*/
731	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
732	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
733	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
734	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
735	if (fDr6)
736	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
737
738	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
739	}
740
741
742	/**
743	* Lazily sync in the hypervisor debug state
744	*
745	* @returns VBox status code.
746	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
747	* @param fDr6 Whether to include DR6 or not.
748	* @thread EMT(pVCpu)
749	*/
750	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6)
751	{
752	/*
753	* Save the host state and disarm all host BPs.
754	*/
755	cpumR0SaveHostDebugState(pVCpu);
756	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
757
758	/*
759	* Make sure the hypervisor values are up to date.
760	*/
761	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
762
763	/*
764	* Activate the guest state DR0-3.
765	* DR7 and DR6 (if fDr6 is true) are left to the caller.
766	*/
767	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
768	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
769	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
770	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
771	if (fDr6)
772	ASMSetDR6(X86_DR6_INIT_VAL);
773
774	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
775	}
776

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 94940

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