HMR0.cpp@ 43834

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1	/* $Id: HMR0.cpp 43803 2012-11-05 13:50:57Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HWVMXR0.h"
44	#include "HWSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBLCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94	bool fEnabledByHost));
95	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
96	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
99	/** @} */
100
101	/** Maximum ASID allowed. */
102	uint32_t uMaxAsid;
103
104	/** VT-x data. */
105	struct
106	{
107	/** Set to by us to indicate VMX is supported by the CPU. */
108	bool fSupported;
109	/** Whether we're using SUPR0EnableVTx or not. */
110	bool fUsingSUPR0EnableVTx;
111	/** Whether we're using the preemption timer or not. */
112	bool fUsePreemptTimer;
113	/** The shift mask employed by the VMX-Preemption timer. */
114	uint8_t cPreemptTimerShift;
115
116	/** Host CR4 value (set by ring-0 VMX init) */
117	uint64_t hostCR4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t hostEFER;
121
122	/** VMX MSR values */
123	struct
124	{
125	uint64_t feature_ctrl;
126	uint64_t vmx_basic_info;
127	VMX_CAPABILITY vmx_pin_ctls;
128	VMX_CAPABILITY vmx_proc_ctls;
129	VMX_CAPABILITY vmx_proc_ctls2;
130	VMX_CAPABILITY vmx_exit;
131	VMX_CAPABILITY vmx_entry;
132	uint64_t vmx_misc;
133	uint64_t vmx_cr0_fixed0;
134	uint64_t vmx_cr0_fixed1;
135	uint64_t vmx_cr4_fixed0;
136	uint64_t vmx_cr4_fixed1;
137	uint64_t vmx_vmcs_enum;
138	uint64_t vmx_ept_vpid_caps;
139	} msr;
140	/* Last instruction error */
141	uint32_t ulLastInstrError;
142	} vmx;
143
144	/** AMD-V information. */
145	struct
146	{
147	/* HWCR MSR (for diagnostics) */
148	uint64_t msrHwcr;
149
150	/** SVM revision. */
151	uint32_t u32Rev;
152
153	/** SVM feature bits from cpuid 0x8000000a */
154	uint32_t u32Features;
155
156	/** Set by us to indicate SVM is supported by the CPU. */
157	bool fSupported;
158	} svm;
159	/** Saved error from detection */
160	int32_t lLastError;
161
162	struct
163	{
164	uint32_t u32AMDFeatureECX;
165	uint32_t u32AMDFeatureEDX;
166	} cpuid;
167
168	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
169	* enabled and disabled each time it's used to execute guest code. */
170	bool fGlobalInit;
171	/** Indicates whether the host is suspending or not. We'll refuse a few
172	* actions when the host is being suspended to speed up the suspending and
173	* avoid trouble. */
174	volatile bool fSuspended;
175
176	/** Whether we've already initialized all CPUs.
177	* @remarks We could check the EnableAllCpusOnce state, but this is
178	* simpler and hopefully easier to understand. */
179	bool fEnabled;
180	/** Serialize initialization in HMR0EnableAllCpus. */
181	RTONCE EnableAllCpusOnce;
182	} g_HvmR0;
183
184
185
186	/**
187	* Initializes a first return code structure.
188	*
189	* @param pFirstRc The structure to init.
190	*/
191	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
192	{
193	pFirstRc->rc = VINF_SUCCESS;
194	pFirstRc->idCpu = NIL_RTCPUID;
195	}
196
197
198	/**
199	* Try set the status code (success ignored).
200	*
201	* @param pFirstRc The first return code structure.
202	* @param rc The status code.
203	*/
204	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
205	{
206	if ( RT_FAILURE(rc)
207	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
208	pFirstRc->idCpu = RTMpCpuId();
209	}
210
211
212	/**
213	* Get the status code of a first return code structure.
214	*
215	* @returns The status code; VINF_SUCCESS or error status, no informational or
216	* warning errors.
217	* @param pFirstRc The first return code structure.
218	*/
219	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
220	{
221	return pFirstRc->rc;
222	}
223
224
225	#ifdef VBOX_STRICT
226	/**
227	* Get the CPU ID on which the failure status code was reported.
228	*
229	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
230	* @param pFirstRc The first return code structure.
231	*/
232	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
233	{
234	return pFirstRc->idCpu;
235	}
236	#endif /* VBOX_STRICT */
237
238
239	/** @name Dummy callback handlers.
240	* @{ */
241
242	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
243	{
244	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
245	return VINF_SUCCESS;
246	}
247
248	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
249	{
250	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
251	return VINF_SUCCESS;
252	}
253
254	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
255	bool fEnabledBySystem)
256	{
257	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem);
258	return VINF_SUCCESS;
259	}
260
261	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
262	{
263	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
264	return VINF_SUCCESS;
265	}
266
267	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
268	{
269	NOREF(pVM);
270	return VINF_SUCCESS;
271	}
272
273	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
274	{
275	NOREF(pVM);
276	return VINF_SUCCESS;
277	}
278
279	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
280	{
281	NOREF(pVM);
282	return VINF_SUCCESS;
283	}
284
285	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
286	{
287	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
288	return VINF_SUCCESS;
289	}
290
291	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
292	{
293	NOREF(pVM); NOREF(pVCpu);
294	return VINF_SUCCESS;
295	}
296
297	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
298	{
299	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
300	return VINF_SUCCESS;
301	}
302
303	/** @} */
304
305
306	/**
307	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
308	* Down at the Rate Specified" erratum.
309	*
310	* Errata names and related steppings:
311	* - BA86 - D0.
312	* - AAX65 - C2.
313	* - AAU65 - C2, K0.
314	* - AAO95 - B1.
315	* - AAT59 - C2.
316	* - AAK139 - D0.
317	* - AAM126 - C0, C1, D0.
318	* - AAN92 - B1.
319	* - AAJ124 - C0, D0.
320	*
321	* - AAP86 - B1.
322	*
323	* Steppings: B1, C0, C1, C2, D0, K0.
324	*
325	* @returns true if subject to it, false if not.
326	*/
327	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
328	{
329	uint32_t u = ASMCpuId_EAX(1);
330	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
331	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
332	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
333	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
334	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
335	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
336	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
337	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
338	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
339	\|\| u == UINT32_C(0x000106A0) /?321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification /
340	\|\| u == UINT32_C(0x000106A1) /?321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification /
341	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
342	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
343	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
344	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
345	)
346	return true;
347	return false;
348	}
349
350
351	/**
352	* Intel specific initialization code.
353	*
354	* @returns VBox status code (will only fail if out of memory).
355	*/
356	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
357	{
358	/*
359	* Check that all the required VT-x features are present.
360	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
361	*/
362	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
363	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
364	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
365	)
366	{
367	/** @todo move this into a separate function. */
368	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
369
370	/*
371	* First try use native kernel API for controlling VT-x.
372	* (This is only supported by some Mac OS X kernels atm.)
373	*/
374	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
375	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
376	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
377	{
378	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
379	if (RT_SUCCESS(rc))
380	{
381	g_HvmR0.vmx.fSupported = true;
382	rc = SUPR0EnableVTx(false /* fEnable */);
383	AssertLogRelRC(rc);
384	}
385	}
386	else
387	{
388	/* We need to check if VT-x has been properly initialized on all
389	CPUs. Some BIOSes do a lousy job. */
390	HMR0FIRSTRC FirstRc;
391	hmR0FirstRcInit(&FirstRc);
392	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
393	if (RT_SUCCESS(g_HvmR0.lLastError))
394	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
395	}
396	if (RT_SUCCESS(g_HvmR0.lLastError))
397	{
398	/* Reread in case we've changed it. */
399	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
400
401	if ( (g_HvmR0.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
402	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
403	{
404	/*
405	* Read all relevant MSR.
406	*/
407	g_HvmR0.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
408	g_HvmR0.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
409	g_HvmR0.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
410	g_HvmR0.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
411	g_HvmR0.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
412	g_HvmR0.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
413	g_HvmR0.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
414	g_HvmR0.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
415	g_HvmR0.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
416	g_HvmR0.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
417	g_HvmR0.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
418	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
419	g_HvmR0.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
420	/* VPID 16 bits ASID. */
421	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
422
423	if (g_HvmR0.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
424	{
425	g_HvmR0.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
426	if ( g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1
427	& (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
428	{
429	g_HvmR0.vmx.msr.vmx_ept_vpid_caps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
430	}
431	}
432
433	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
434	{
435	/*
436	* Enter root mode
437	*/
438	RTR0MEMOBJ hScatchMemObj;
439	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
440	if (RT_FAILURE(rc))
441	{
442	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
443	return rc;
444	}
445
446	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
447	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
448	ASMMemZeroPage(pvScatchPage);
449
450	/* Set revision dword at the beginning of the structure. */
451	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.vmx_basic_info);
452
453	/* Make sure we don't get rescheduled to another cpu during this probe. */
454	RTCCUINTREG fFlags = ASMIntDisableFlags();
455
456	/*
457	* Check CR4.VMXE
458	*/
459	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
460	if (!(g_HvmR0.vmx.hostCR4 & X86_CR4_VMXE))
461	{
462	/* In theory this bit could be cleared behind our back. Which would cause
463	#UD faults when we try to execute the VMX instructions... */
464	ASMSetCR4(g_HvmR0.vmx.hostCR4 \| X86_CR4_VMXE);
465	}
466
467	/* Enter VMX Root Mode */
468	rc = VMXEnable(HCPhysScratchPage);
469	if (RT_SUCCESS(rc))
470	{
471	g_HvmR0.vmx.fSupported = true;
472	VMXDisable();
473	}
474	else
475	{
476	/*
477	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
478	* it will crash the host when we enter raw mode, because:
479	*
480	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
481	* this bit), and
482	* (b) turning off paging causes a #GP (unavoidable when switching
483	* from long to 32 bits mode or 32 bits to PAE).
484	*
485	* They should fix their code, but until they do we simply refuse to run.
486	*/
487	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
488	}
489
490	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
491	if it wasn't so before (some software could incorrectly
492	think it's in VMX mode). */
493	ASMSetCR4(g_HvmR0.vmx.hostCR4);
494	ASMSetFlags(fFlags);
495
496	RTR0MemObjFree(hScatchMemObj, false);
497	}
498	}
499	else
500	{
501	AssertFailed(); /* can't hit this case anymore */
502	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
503	}
504
505	if (g_HvmR0.vmx.fSupported)
506	{
507	/*
508	* Install the VT-x methods.
509	*/
510	g_HvmR0.pfnEnterSession = VMXR0Enter;
511	g_HvmR0.pfnLeaveSession = VMXR0Leave;
512	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
513	g_HvmR0.pfnLoadGuestState = VMXR0LoadGuestState;
514	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
515	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
516	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
517	g_HvmR0.pfnInitVM = VMXR0InitVM;
518	g_HvmR0.pfnTermVM = VMXR0TermVM;
519	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
520
521	/*
522	* Check for the VMX-Preemption Timer and adjust for the * "VMX-Preemption
523	* Timer Does Not Count Down at the Rate Specified" erratum.
524	*/
525	if ( g_HvmR0.vmx.msr.vmx_pin_ctls.n.allowed1
526	& VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
527	{
528	g_HvmR0.vmx.fUsePreemptTimer = true;
529	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.vmx_misc);
530	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
531	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
532	}
533	}
534	}
535	#ifdef LOG_ENABLED
536	else
537	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
538	#endif
539	}
540	else
541	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
542	return VINF_SUCCESS;
543	}
544
545
546	/**
547	* AMD-specific initialization code.
548	*/
549	static void hmR0InitAmd(uint32_t u32FeaturesEDX)
550	{
551	/*
552	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
553	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
554	*/
555	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
556	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
557	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
558	)
559	{
560	g_HvmR0.pfnEnterSession = SVMR0Enter;
561	g_HvmR0.pfnLeaveSession = SVMR0Leave;
562	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
563	g_HvmR0.pfnLoadGuestState = SVMR0LoadGuestState;
564	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
565	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
566	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
567	g_HvmR0.pfnInitVM = SVMR0InitVM;
568	g_HvmR0.pfnTermVM = SVMR0TermVM;
569	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
570
571	/* Query AMD features. */
572	uint32_t u32Dummy;
573	ASMCpuId(0x8000000A, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
574
575	/*
576	* We need to check if AMD-V has been properly initialized on all CPUs.
577	* Some BIOSes might do a poor job.
578	*/
579	HMR0FIRSTRC FirstRc;
580	hmR0FirstRcInit(&FirstRc);
581	int rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
582	AssertRC(rc);
583	if (RT_SUCCESS(rc))
584	rc = hmR0FirstRcGetStatus(&FirstRc);
585	#ifndef DEBUG_bird
586	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
587	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
588	#endif
589	if (RT_SUCCESS(rc))
590	{
591	/* Read the HWCR MSR for diagnostics. */
592	g_HvmR0.svm.msrHwcr = ASMRdMsr(MSR_K8_HWCR);
593	g_HvmR0.svm.fSupported = true;
594	}
595	else
596	g_HvmR0.lLastError = rc;
597	}
598	else
599	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
600	}
601
602
603	/**
604	* Does global Ring-0 HM initialization (at module init).
605	*
606	* @returns VBox status code.
607	*/
608	VMMR0DECL(int) HMR0Init(void)
609	{
610	/*
611	* Initialize the globals.
612	*/
613	g_HvmR0.fEnabled = false;
614	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
615	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
616	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
617	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
618
619	/* Fill in all callbacks with placeholders. */
620	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
621	g_HvmR0.pfnLeaveSession = hmR0DummyLeave;
622	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
623	g_HvmR0.pfnLoadGuestState = hmR0DummyLoadGuestState;
624	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
625	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
626	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
627	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
628	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
629	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
630
631	/* Default is global VT-x/AMD-V init. */
632	g_HvmR0.fGlobalInit = true;
633
634	/*
635	* Make sure aCpuInfo is big enough for all the CPUs on this system.
636	*/
637	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
638	{
639	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
640	return VERR_TOO_MANY_CPUS;
641	}
642
643	/*
644	* Check for VT-x and AMD-V capabilities.
645	*/
646	int rc;
647	if (ASMHasCpuId())
648	{
649	uint32_t u32FeaturesECX, u32FeaturesEDX;
650	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
651	uint32_t u32Dummy;
652
653	/* Standard features. */
654	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
655	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
656
657	/* Query AMD features. */
658	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
659	&g_HvmR0.cpuid.u32AMDFeatureECX,
660	&g_HvmR0.cpuid.u32AMDFeatureEDX);
661
662	/* Go to CPU specific initialization code. */
663	if ( ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
664	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
665	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX)
666	\|\| ( u32VendorEBX == X86_CPUID_VENDOR_VIA_EBX
667	&& u32VendorECX == X86_CPUID_VENDOR_VIA_ECX
668	&& u32VendorEDX == X86_CPUID_VENDOR_VIA_EDX))
669	{
670	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
671	if (RT_FAILURE(rc))
672	return rc;
673	}
674	else if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
675	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
676	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX)
677	hmR0InitAmd(u32FeaturesEDX);
678	else
679	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
680	}
681	else
682	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
683
684	/*
685	* Register notification callbacks that we can use to disable/enable CPUs
686	* when brought offline/online or suspending/resuming.
687	*/
688	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
689	{
690	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
691	AssertRC(rc);
692
693	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
694	AssertRC(rc);
695	}
696
697	/* We return success here because module init shall not fail if HM
698	fails to initialize. */
699	return VINF_SUCCESS;
700	}
701
702
703	/**
704	* Does global Ring-0 HM termination (at module termination).
705	*
706	* @returns VBox status code.
707	*/
708	VMMR0DECL(int) HMR0Term(void)
709	{
710	int rc;
711	if ( g_HvmR0.vmx.fSupported
712	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
713	{
714	/*
715	* Simple if the host OS manages VT-x.
716	*/
717	Assert(g_HvmR0.fGlobalInit);
718	rc = SUPR0EnableVTx(false /* fEnable */);
719
720	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
721	{
722	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
723	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
724	}
725	}
726	else
727	{
728	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
729	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
730	{
731	/* Doesn't really matter if this fails. */
732	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
733	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
734	}
735	else
736	rc = VINF_SUCCESS;
737
738	/*
739	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
740	*/
741	if (g_HvmR0.fGlobalInit)
742	{
743	HMR0FIRSTRC FirstRc;
744	hmR0FirstRcInit(&FirstRc);
745	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
746	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
747	if (RT_SUCCESS(rc))
748	{
749	rc = hmR0FirstRcGetStatus(&FirstRc);
750	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
751	}
752	}
753
754	/*
755	* Free the per-cpu pages used for VT-x and AMD-V.
756	*/
757	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
758	{
759	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
760	{
761	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
762	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
763	}
764	}
765	}
766	return rc;
767	}
768
769
770	/**
771	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
772	* VT-x on a CPU.
773	*
774	* @param idCpu The identifier for the CPU the function is called on.
775	* @param pvUser1 Pointer to the first RC structure.
776	* @param pvUser2 Ignored.
777	*/
778	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
779	{
780	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
781	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
782	NOREF(pvUser2);
783
784	/*
785	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
786	* Once the lock bit is set, this MSR can no longer be modified.
787	*/
788	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
789	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
790	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
791	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
792	)
793	{
794	/* MSR is not yet locked; we can change it ourselves here. */
795	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
796	g_HvmR0.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
797	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
798	}
799
800	int rc;
801	if ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
802	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
803	rc = VINF_SUCCESS;
804	else
805	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
806
807	hmR0FirstRcSetStatus(pFirstRc, rc);
808	}
809
810
811	/**
812	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
813	* VT-x / AMD-V on a CPU.
814	*
815	* @param idCpu The identifier for the CPU the function is called on.
816	* @param pvUser1 Pointer to the first RC structure.
817	* @param pvUser2 Ignored.
818	*/
819	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
820	{
821	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
822	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
823	NOREF(pvUser2);
824
825	/* Check if SVM is disabled. */
826	int rc;
827	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
828	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
829	{
830	/* Turn on SVM in the EFER MSR. */
831	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
832	if (fEfer & MSR_K6_EFER_SVME)
833	rc = VERR_SVM_IN_USE;
834	else
835	{
836	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
837
838	/* Paranoia. */
839	fEfer = ASMRdMsr(MSR_K6_EFER);
840	if (fEfer & MSR_K6_EFER_SVME)
841	{
842	/* Restore previous value. */
843	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
844	rc = VINF_SUCCESS;
845	}
846	else
847	rc = VERR_SVM_ILLEGAL_EFER_MSR;
848	}
849	}
850	else
851	rc = VERR_SVM_DISABLED;
852
853	hmR0FirstRcSetStatus(pFirstRc, rc);
854	}
855
856
857	/**
858	* Disable VT-x or AMD-V on the current CPU
859	*
860	* @returns VBox status code.
861	* @param pVM Pointer to the VM (can be 0).
862	* @param idCpu The identifier for the CPU the function is called on.
863	*/
864	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
865	{
866	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
867
868	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
869	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
870	Assert(!pCpu->fConfigured);
871	Assert(!g_HvmR0.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
872
873	pCpu->idCpu = idCpu;
874	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
875	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
876
877	int rc;
878	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
879	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL, NIL_RTHCPHYS, true);
880	else
881	{
882	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
883	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
884	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
885	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
886	}
887	AssertRC(rc);
888	if (RT_SUCCESS(rc))
889	pCpu->fConfigured = true;
890
891	return rc;
892	}
893
894
895	/**
896	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
897	* is to be called on the target cpus.
898	*
899	* @param idCpu The identifier for the CPU the function is called on.
900	* @param pvUser1 The 1st user argument.
901	* @param pvUser2 The 2nd user argument.
902	*/
903	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
904	{
905	PVM pVM = (PVM)pvUser1; /* can be NULL! */
906	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
907	AssertReturnVoid(g_HvmR0.fGlobalInit);
908	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
909	}
910
911
912	/**
913	* RTOnce callback employed by HMR0EnableAllCpus.
914	*
915	* @returns VBox status code.
916	* @param pvUser Pointer to the VM.
917	* @param pvUserIgnore NULL, ignored.
918	*/
919	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void pvUser, void pvUserIgnore)
920	{
921	PVM pVM = (PVM)pvUser;
922	NOREF(pvUserIgnore);
923
924	/*
925	* Indicate that we've initialized.
926	*
927	* Note! There is a potential race between this function and the suspend
928	* notification. Kind of unlikely though, so ignored for now.
929	*/
930	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
931	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
932
933	/*
934	* The global init variable is set by the first VM.
935	*/
936	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
937
938	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
939	{
940	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
941	g_HvmR0.aCpuInfo[i].fConfigured = false;
942	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
943	}
944
945	int rc;
946	if ( g_HvmR0.vmx.fSupported
947	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
948	{
949	/*
950	* Global VT-x initialization API (only darwin for now).
951	*/
952	rc = SUPR0EnableVTx(true /* fEnable */);
953	if (RT_SUCCESS(rc))
954	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
955	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
956	else
957	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
958	}
959	else
960	{
961	/*
962	* We're doing the job ourselves.
963	*/
964	/* Allocate one page per cpu for the global vt-x and amd-v pages */
965	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
966	{
967	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
968
969	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
970	{
971	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
972	AssertLogRelRCReturn(rc, rc);
973
974	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
975	ASMMemZeroPage(pvR0);
976	}
977	}
978
979	rc = VINF_SUCCESS;
980	}
981
982	if (RT_SUCCESS(rc) && g_HvmR0.fGlobalInit)
983	{
984	/* First time, so initialize each cpu/core. */
985	HMR0FIRSTRC FirstRc;
986	hmR0FirstRcInit(&FirstRc);
987	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
988	if (RT_SUCCESS(rc))
989	rc = hmR0FirstRcGetStatus(&FirstRc);
990	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
991	}
992
993	return rc;
994	}
995
996
997	/**
998	* Sets up HM on all cpus.
999	*
1000	* @returns VBox status code.
1001	* @param pVM Pointer to the VM.
1002	*/
1003	VMMR0DECL(int) HMR0EnableAllCpus(PVM pVM)
1004	{
1005	/* Make sure we don't touch hm after we've disabled hm in
1006	preparation of a suspend. */
1007	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1008	return VERR_HM_SUSPEND_PENDING;
1009
1010	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM, NULL);
1011	}
1012
1013
1014	/**
1015	* Disable VT-x or AMD-V on the current CPU.
1016	*
1017	* @returns VBox status code.
1018	* @param idCpu The identifier for the CPU the function is called on.
1019	*/
1020	static int hmR0DisableCpu(RTCPUID idCpu)
1021	{
1022	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1023
1024	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1025	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1026	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1027	Assert(!g_HvmR0.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
1028	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1029
1030	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1031	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1032
1033	int rc;
1034	if (pCpu->fConfigured)
1035	{
1036	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1037	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1038	if (idCpu == RTMpCpuId())
1039	{
1040	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1041	AssertRC(rc);
1042	}
1043	else
1044	{
1045	pCpu->fIgnoreAMDVInUseError = true;
1046	rc = VINF_SUCCESS;
1047	}
1048
1049	pCpu->fConfigured = false;
1050	}
1051	else
1052	rc = VINF_SUCCESS; /* nothing to do */
1053
1054	pCpu->uCurrentAsid = 0;
1055	return rc;
1056	}
1057
1058
1059	/**
1060	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1061	* is to be called on the target cpus.
1062	*
1063	* @param idCpu The identifier for the CPU the function is called on.
1064	* @param pvUser1 The 1st user argument.
1065	* @param pvUser2 The 2nd user argument.
1066	*/
1067	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1068	{
1069	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1070	AssertReturnVoid(g_HvmR0.fGlobalInit);
1071	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1072	}
1073
1074
1075	/**
1076	* Callback function invoked when a cpu goes online or offline.
1077	*
1078	* @param enmEvent The Mp event.
1079	* @param idCpu The identifier for the CPU the function is called on.
1080	* @param pvData Opaque data (PVM pointer).
1081	*/
1082	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1083	{
1084	NOREF(pvData);
1085
1086	/*
1087	* We only care about uninitializing a CPU that is going offline. When a
1088	* CPU comes online, the initialization is done lazily in HMR0Enter().
1089	*/
1090	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1091	switch (enmEvent)
1092	{
1093	case RTMPEVENT_OFFLINE:
1094	{
1095	int rc = hmR0DisableCpu(idCpu);
1096	AssertRC(rc);
1097	break;
1098	}
1099
1100	default:
1101	break;
1102	}
1103	}
1104
1105
1106	/**
1107	* Called whenever a system power state change occurs.
1108	*
1109	* @param enmEvent The Power event.
1110	* @param pvUser User argument.
1111	*/
1112	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1113	{
1114	NOREF(pvUser);
1115	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1116
1117	#ifdef LOG_ENABLED
1118	if (enmEvent == RTPOWEREVENT_SUSPEND)
1119	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1120	else
1121	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1122	#endif
1123
1124	if (enmEvent == RTPOWEREVENT_SUSPEND)
1125	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1126
1127	if (g_HvmR0.fEnabled)
1128	{
1129	int rc;
1130	HMR0FIRSTRC FirstRc;
1131	hmR0FirstRcInit(&FirstRc);
1132
1133	if (enmEvent == RTPOWEREVENT_SUSPEND)
1134	{
1135	if (g_HvmR0.fGlobalInit)
1136	{
1137	/* Turn off VT-x or AMD-V on all CPUs. */
1138	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
1139	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1140	}
1141	/* else nothing to do here for the local init case */
1142	}
1143	else
1144	{
1145	/* Reinit the CPUs from scratch as the suspend state might have
1146	messed with the MSRs. (lousy BIOSes as usual) */
1147	if (g_HvmR0.vmx.fSupported)
1148	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1149	else
1150	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1151	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1152	if (RT_SUCCESS(rc))
1153	rc = hmR0FirstRcGetStatus(&FirstRc);
1154	#ifdef LOG_ENABLED
1155	if (RT_FAILURE(rc))
1156	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1157	#endif
1158	if (g_HvmR0.fGlobalInit)
1159	{
1160	/* Turn VT-x or AMD-V back on on all CPUs. */
1161	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
1162	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1163	}
1164	/* else nothing to do here for the local init case */
1165	}
1166	}
1167
1168	if (enmEvent == RTPOWEREVENT_RESUME)
1169	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1170	}
1171
1172
1173	/**
1174	* Does Ring-0 per VM HM initialization.
1175	*
1176	* This will copy HM global into the VM structure and call the CPU specific
1177	* init routine which will allocate resources for each virtual CPU and such.
1178	*
1179	* @returns VBox status code.
1180	* @param pVM Pointer to the VM.
1181	*/
1182	VMMR0DECL(int) HMR0InitVM(PVM pVM)
1183	{
1184	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1185
1186	#ifdef LOG_ENABLED
1187	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1188	#endif
1189
1190	/* Make sure we don't touch hm after we've disabled hm in preparation of a suspend. */
1191	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1192	return VERR_HM_SUSPEND_PENDING;
1193
1194	/*
1195	* Copy globals to the VM structure.
1196	*/
1197	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1198	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1199
1200	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1201	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1202	pVM->hm.s.vmx.msr.feature_ctrl = g_HvmR0.vmx.msr.feature_ctrl;
1203	pVM->hm.s.vmx.hostCR4 = g_HvmR0.vmx.hostCR4;
1204	pVM->hm.s.vmx.hostEFER = g_HvmR0.vmx.hostEFER;
1205	pVM->hm.s.vmx.msr.vmx_basic_info = g_HvmR0.vmx.msr.vmx_basic_info;
1206	pVM->hm.s.vmx.msr.vmx_pin_ctls = g_HvmR0.vmx.msr.vmx_pin_ctls;
1207	pVM->hm.s.vmx.msr.vmx_proc_ctls = g_HvmR0.vmx.msr.vmx_proc_ctls;
1208	pVM->hm.s.vmx.msr.vmx_proc_ctls2 = g_HvmR0.vmx.msr.vmx_proc_ctls2;
1209	pVM->hm.s.vmx.msr.vmx_exit = g_HvmR0.vmx.msr.vmx_exit;
1210	pVM->hm.s.vmx.msr.vmx_entry = g_HvmR0.vmx.msr.vmx_entry;
1211	pVM->hm.s.vmx.msr.vmx_misc = g_HvmR0.vmx.msr.vmx_misc;
1212	pVM->hm.s.vmx.msr.vmx_cr0_fixed0 = g_HvmR0.vmx.msr.vmx_cr0_fixed0;
1213	pVM->hm.s.vmx.msr.vmx_cr0_fixed1 = g_HvmR0.vmx.msr.vmx_cr0_fixed1;
1214	pVM->hm.s.vmx.msr.vmx_cr4_fixed0 = g_HvmR0.vmx.msr.vmx_cr4_fixed0;
1215	pVM->hm.s.vmx.msr.vmx_cr4_fixed1 = g_HvmR0.vmx.msr.vmx_cr4_fixed1;
1216	pVM->hm.s.vmx.msr.vmx_vmcs_enum = g_HvmR0.vmx.msr.vmx_vmcs_enum;
1217	pVM->hm.s.vmx.msr.vmx_ept_vpid_caps = g_HvmR0.vmx.msr.vmx_ept_vpid_caps;
1218	pVM->hm.s.svm.msrHwcr = g_HvmR0.svm.msrHwcr;
1219	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1220	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1221	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1222	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1223	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1224
1225	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1226
1227
1228	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1229	{
1230	pVM->hm.s.cMaxResumeLoops = 1024;
1231	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1232	if (RTThreadPreemptIsPendingTrusty())
1233	pVM->hm.s.cMaxResumeLoops = 8192;
1234	#endif
1235	}
1236
1237	/*
1238	* Initialize some per CPU fields.
1239	*/
1240	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1241	{
1242	PVMCPU pVCpu = &pVM->aCpus[i];
1243
1244	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1245
1246	/* Invalidate the last cpu we were running on. */
1247	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1248
1249	/* We'll aways increment this the first time (host uses ASID 0) */
1250	pVCpu->hm.s.uCurrentAsid = 0;
1251	}
1252
1253	/*
1254	* Call the hardware specific initialization method.
1255	*
1256	* Note! The fInUse handling here isn't correct as we can we can be
1257	* rescheduled to a different cpu, but the fInUse case is mostly for
1258	* debugging... Disabling preemption isn't an option when allocating
1259	* memory, so we'll let it slip for now.
1260	*/
1261	RTCCUINTREG fFlags = ASMIntDisableFlags();
1262	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
1263	ASMAtomicWriteBool(&pCpu->fInUse, true);
1264	ASMSetFlags(fFlags);
1265
1266	int rc = g_HvmR0.pfnInitVM(pVM);
1267
1268	ASMAtomicWriteBool(&pCpu->fInUse, false);
1269	return rc;
1270	}
1271
1272
1273	/**
1274	* Does Ring-0 per VM HM termination.
1275	*
1276	* @returns VBox status code.
1277	* @param pVM Pointer to the VM.
1278	*/
1279	VMMR0DECL(int) HMR0TermVM(PVM pVM)
1280	{
1281	Log(("HMR0TermVM: %p\n", pVM));
1282	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1283
1284	/* Make sure we don't touch hm after we've disabled hm in preparation
1285	of a suspend. */
1286	/** @todo r=bird: This cannot be right, the termination functions are
1287	* just freeing memory and resetting pVM/pVCpu members...
1288	* ==> memory leak. */
1289	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1290
1291	/*
1292	* Call the hardware specific method.
1293	*
1294	* Note! Not correct as we can be rescheduled to a different cpu, but the
1295	* fInUse case is mostly for debugging.
1296	*/
1297	RTCCUINTREG fFlags = ASMIntDisableFlags();
1298	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
1299	ASMAtomicWriteBool(&pCpu->fInUse, true);
1300	ASMSetFlags(fFlags);
1301
1302	int rc = g_HvmR0.pfnTermVM(pVM);
1303
1304	ASMAtomicWriteBool(&pCpu->fInUse, false);
1305	return rc;
1306	}
1307
1308
1309	/**
1310	* Sets up a VT-x or AMD-V session.
1311	*
1312	* This is mostly about setting up the hardware VM state.
1313	*
1314	* @returns VBox status code.
1315	* @param pVM Pointer to the VM.
1316	*/
1317	VMMR0DECL(int) HMR0SetupVM(PVM pVM)
1318	{
1319	Log(("HMR0SetupVM: %p\n", pVM));
1320	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1321
1322	/* Make sure we don't touch hm after we've disabled hm in
1323	preparation of a suspend. */
1324	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1325
1326
1327	/*
1328	* Call the hardware specific setup VM method. This requires the CPU to be
1329	* enabled for AMD-V/VT-x and preemption to be prevented.
1330	*/
1331	RTCCUINTREG fFlags = ASMIntDisableFlags();
1332	RTCPUID idCpu = RTMpCpuId();
1333	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1334	ASMAtomicWriteBool(&pCpu->fInUse, true);
1335
1336	/* On first entry we'll sync everything. */
1337	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1338	pVM->aCpus[i].hm.s.fContextUseFlags = HM_CHANGED_ALL;
1339
1340	/* Enable VT-x or AMD-V if local init is required. */
1341	int rc;
1342	if (!g_HvmR0.fGlobalInit)
1343	{
1344	rc = hmR0EnableCpu(pVM, idCpu);
1345	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1346	}
1347
1348	/* Setup VT-x or AMD-V. */
1349	rc = g_HvmR0.pfnSetupVM(pVM);
1350
1351	/* Disable VT-x or AMD-V if local init was done before. */
1352	if (!g_HvmR0.fGlobalInit)
1353	{
1354	int rc2 = hmR0DisableCpu(idCpu);
1355	AssertRC(rc2);
1356	}
1357
1358	ASMAtomicWriteBool(&pCpu->fInUse, false);
1359	ASMSetFlags(fFlags);
1360
1361	return rc;
1362	}
1363
1364
1365	/**
1366	* Enters the VT-x or AMD-V session.
1367	*
1368	* @returns VBox status code.
1369	* @param pVM Pointer to the VM.
1370	* @param pVCpu Pointer to the VMCPU.
1371	*
1372	* @remarks This is called with preemption disabled.
1373	*/
1374	VMMR0DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1375	{
1376	RTCPUID idCpu = RTMpCpuId();
1377	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1378
1379	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1380	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1381	ASMAtomicWriteBool(&pCpu->fInUse, true);
1382
1383	AssertMsg(pVCpu->hm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hm.s.idEnteredCpu));
1384	pVCpu->hm.s.idEnteredCpu = idCpu;
1385
1386	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1387
1388	/* Always load the guest's FPU/XMM state on-demand. */
1389	CPUMDeactivateGuestFPUState(pVCpu);
1390
1391	/* Always load the guest's debug state on-demand. */
1392	CPUMDeactivateGuestDebugState(pVCpu);
1393
1394	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1395	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0 \| HM_CHANGED_HOST_CONTEXT;
1396
1397	/* Setup the register and mask according to the current execution mode. */
1398	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1399	pVM->hm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1400	else
1401	pVM->hm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1402
1403	/* Enable VT-x or AMD-V if local init is required, or enable if it's a
1404	freshly onlined CPU. */
1405	int rc;
1406	if ( !pCpu->fConfigured
1407	\|\| !g_HvmR0.fGlobalInit)
1408	{
1409	rc = hmR0EnableCpu(pVM, idCpu);
1410	AssertRCReturn(rc, rc);
1411	}
1412
1413	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1414	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1415	#endif
1416
1417	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1418	AssertRC(rc);
1419	/* We must save the host context here (VT-x) as we might be rescheduled on
1420	a different cpu after a long jump back to ring 3. */
1421	rc \|= g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1422	AssertRC(rc);
1423	rc \|= g_HvmR0.pfnLoadGuestState(pVM, pVCpu, pCtx);
1424	AssertRC(rc);
1425
1426	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1427	if (fStartedSet)
1428	PGMRZDynMapReleaseAutoSet(pVCpu);
1429	#endif
1430
1431	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1432	and ring-3 calls. */
1433	if (RT_FAILURE(rc))
1434	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1435	return rc;
1436	}
1437
1438
1439	/**
1440	* Leaves the VT-x or AMD-V session.
1441	*
1442	* @returns VBox status code.
1443	* @param pVM Pointer to the VM.
1444	* @param pVCpu Pointer to the VMCPU.
1445	*
1446	* @remarks Called with preemption disabled just like HMR0Enter, our
1447	* counterpart.
1448	*/
1449	VMMR0DECL(int) HMR0Leave(PVM pVM, PVMCPU pVCpu)
1450	{
1451	int rc;
1452	RTCPUID idCpu = RTMpCpuId();
1453	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1454	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1455
1456	/** @todo r=bird: This can't be entirely right? */
1457	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1458
1459	/*
1460	* Save the guest FPU and XMM state if necessary.
1461	*
1462	* Note! It's rather tricky with longjmps done by e.g. Log statements or
1463	* the page fault handler. We must restore the host FPU here to make
1464	* absolutely sure we don't leave the guest FPU state active or trash
1465	* somebody else's FPU state.
1466	*/
1467	if (CPUMIsGuestFPUStateActive(pVCpu))
1468	{
1469	Log2(("CPUMR0SaveGuestFPU\n"));
1470	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1471
1472	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
1473	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1474	}
1475
1476	rc = g_HvmR0.pfnLeaveSession(pVM, pVCpu, pCtx);
1477
1478	/* We don't pass on invlpg information to the recompiler for nested paging
1479	guests, so we must make sure the recompiler flushes its TLB the next
1480	time it executes code. */
1481	if ( pVM->hm.s.fNestedPaging
1482	&& CPUMIsGuestInPagedProtectedModeEx(pCtx))
1483	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1484
1485	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1486	and ring-3 calls. */
1487	AssertMsgStmt( pVCpu->hm.s.idEnteredCpu == idCpu
1488	\|\| RT_FAILURE_NP(rc),
1489	("Owner is %u, I'm %u", pVCpu->hm.s.idEnteredCpu, idCpu),
1490	rc = VERR_HM_WRONG_CPU_1);
1491	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1492
1493	/*
1494	* Disable VT-x or AMD-V if local init was done before.
1495	*/
1496	if (!g_HvmR0.fGlobalInit)
1497	{
1498	rc = hmR0DisableCpu(idCpu);
1499	AssertRC(rc);
1500
1501	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1502	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1503	pVCpu->hm.s.uCurrentAsid = 0;
1504	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1505	}
1506
1507	ASMAtomicWriteBool(&pCpu->fInUse, false);
1508	return rc;
1509	}
1510
1511
1512	/**
1513	* Runs guest code in a hardware accelerated VM.
1514	*
1515	* @returns VBox status code.
1516	* @param pVM Pointer to the VM.
1517	* @param pVCpu Pointer to the VMCPU.
1518	*
1519	* @remarks Called with preemption disabled and after first having called
1520	* HMR0Enter.
1521	*/
1522	VMMR0DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1523	{
1524	#ifdef VBOX_STRICT
1525	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1526	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1527	Assert(pCpu->fConfigured);
1528	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1529	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1530	#endif
1531
1532	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1533	PGMRZDynMapStartAutoSet(pVCpu);
1534	#endif
1535
1536	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1537
1538	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1539	PGMRZDynMapReleaseAutoSet(pVCpu);
1540	#endif
1541	return rc;
1542	}
1543
1544	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1545
1546	/**
1547	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1548	*
1549	* @returns VBox status code.
1550	* @param pVM Pointer to the VM.
1551	* @param pVCpu Pointer to the VMCPU.
1552	* @param pCtx Pointer to the guest CPU context.
1553	*/
1554	VMMR0DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1555	{
1556	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1557	if (pVM->hm.s.vmx.fSupported)
1558	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnSaveGuestFPU64, 0, NULL);
1559	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnSaveGuestFPU64, 0, NULL);
1560	}
1561
1562
1563	/**
1564	* Save guest debug state (64 bits guest mode & 32 bits host only)
1565	*
1566	* @returns VBox status code.
1567	* @param pVM Pointer to the VM.
1568	* @param pVCpu Pointer to the VMCPU.
1569	* @param pCtx Pointer to the guest CPU context.
1570	*/
1571	VMMR0DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1572	{
1573	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1574	if (pVM->hm.s.vmx.fSupported)
1575	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnSaveGuestDebug64, 0, NULL);
1576	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnSaveGuestDebug64, 0, NULL);
1577	}
1578
1579
1580	/**
1581	* Test the 32->64 bits switcher.
1582	*
1583	* @returns VBox status code.
1584	* @param pVM Pointer to the VM.
1585	*/
1586	VMMR0DECL(int) HMR0TestSwitcher3264(PVM pVM)
1587	{
1588	PVMCPU pVCpu = &pVM->aCpus[0];
1589	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1590	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1591	int rc;
1592
1593	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1594	if (pVM->hm.s.vmx.fSupported)
1595	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnTest64, 5, &aParam[0]);
1596	else
1597	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnTest64, 5, &aParam[0]);
1598	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1599
1600	return rc;
1601	}
1602
1603	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1604
1605	/**
1606	* Returns suspend status of the host.
1607	*
1608	* @returns Suspend pending or not.
1609	*/
1610	VMMR0DECL(bool) HMR0SuspendPending(void)
1611	{
1612	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1613	}
1614
1615
1616	/**
1617	* Returns the cpu structure for the current cpu.
1618	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1619	*
1620	* @returns The cpu structure pointer.
1621	*/
1622	VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpu(void)
1623	{
1624	RTCPUID idCpu = RTMpCpuId();
1625	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1626	return &g_HvmR0.aCpuInfo[idCpu];
1627	}
1628
1629
1630	/**
1631	* Returns the cpu structure for the current cpu.
1632	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1633	*
1634	* @returns The cpu structure pointer.
1635	* @param idCpu id of the VCPU.
1636	*/
1637	VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1638	{
1639	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1640	return &g_HvmR0.aCpuInfo[idCpu];
1641	}
1642
1643
1644	/**
1645	* Save a pending IO read.
1646	*
1647	* @param pVCpu Pointer to the VMCPU.
1648	* @param GCPtrRip Address of IO instruction.
1649	* @param GCPtrRipNext Address of the next instruction.
1650	* @param uPort Port address.
1651	* @param uAndVal AND mask for saving the result in eax.
1652	* @param cbSize Read size.
1653	*/
1654	VMMR0DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1655	{
1656	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1657	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1658	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1659	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1660	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1661	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1662	return;
1663	}
1664
1665
1666	/**
1667	* Save a pending IO write.
1668	*
1669	* @param pVCpu Pointer to the VMCPU.
1670	* @param GCPtrRIP Address of IO instruction.
1671	* @param uPort Port address.
1672	* @param uAndVal AND mask for fetching the result from eax.
1673	* @param cbSize Read size.
1674	*/
1675	VMMR0DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1676	{
1677	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1678	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1679	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1680	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1681	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1682	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1683	return;
1684	}
1685
1686
1687	/**
1688	* Raw-mode switcher hook - disable VT-x if it's active and the current
1689	* switcher turns off paging.
1690	*
1691	* @returns VBox status code.
1692	* @param pVM Pointer to the VM.
1693	* @param enmSwitcher The switcher we're about to use.
1694	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1695	*/
1696	VMMR0DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1697	{
1698	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1699
1700	*pfVTxDisabled = false;
1701
1702	/* No such issues with AMD-V */
1703	if (!g_HvmR0.vmx.fSupported)
1704	return VINF_SUCCESS;
1705
1706	/* Check if the swithcing we're up to is safe. */
1707	switch (enmSwitcher)
1708	{
1709	case VMMSWITCHER_32_TO_32:
1710	case VMMSWITCHER_PAE_TO_PAE:
1711	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1712
1713	case VMMSWITCHER_32_TO_PAE:
1714	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1715	case VMMSWITCHER_AMD64_TO_32:
1716	case VMMSWITCHER_AMD64_TO_PAE:
1717	break; /* unsafe switchers */
1718
1719	default:
1720	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1721	}
1722
1723	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1724	regardless of whether we're currently using VT-x or not. */
1725	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1726	{
1727	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1728	return VINF_SUCCESS;
1729	}
1730
1731	/** @todo Check if this code is presumtive wrt other VT-x users on the
1732	* system... */
1733
1734	/* Nothing to do if we haven't enabled VT-x. */
1735	if (!g_HvmR0.fEnabled)
1736	return VINF_SUCCESS;
1737
1738	/* Local init implies the CPU is currently not in VMX root mode. */
1739	if (!g_HvmR0.fGlobalInit)
1740	return VINF_SUCCESS;
1741
1742	/* Ok, disable VT-x. */
1743	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
1744	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1745
1746	*pfVTxDisabled = true;
1747	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1748	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1749	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1750	}
1751
1752
1753	/**
1754	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1755	* switcher turned off paging.
1756	*
1757	* @param pVM Pointer to the VM.
1758	* @param fVTxDisabled Whether VT-x was disabled or not.
1759	*/
1760	VMMR0DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1761	{
1762	Assert(!(ASMGetFlags() & X86_EFL_IF));
1763
1764	if (!fVTxDisabled)
1765	return; /* nothing to do */
1766
1767	Assert(g_HvmR0.vmx.fSupported);
1768	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1769	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1770	else
1771	{
1772	Assert(g_HvmR0.fEnabled);
1773	Assert(g_HvmR0.fGlobalInit);
1774
1775	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
1776	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1777
1778	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1779	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1780	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
1781	}
1782	}
1783
1784	#ifdef VBOX_STRICT
1785
1786	/**
1787	* Dumps a descriptor.
1788	*
1789	* @param pDesc Descriptor to dump.
1790	* @param Sel Selector number.
1791	* @param pszMsg Message to prepend the log entry with.
1792	*/
1793	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1794	{
1795	/*
1796	* Make variable description string.
1797	*/
1798	static struct
1799	{
1800	unsigned cch;
1801	const char *psz;
1802	} const s_aTypes[32] =
1803	{
1804	# define STRENTRY(str) { sizeof(str) - 1, str }
1805
1806	/* system */
1807	# if HC_ARCH_BITS == 64
1808	STRENTRY("Reserved0 "), /* 0x00 */
1809	STRENTRY("Reserved1 "), /* 0x01 */
1810	STRENTRY("LDT "), /* 0x02 */
1811	STRENTRY("Reserved3 "), /* 0x03 */
1812	STRENTRY("Reserved4 "), /* 0x04 */
1813	STRENTRY("Reserved5 "), /* 0x05 */
1814	STRENTRY("Reserved6 "), /* 0x06 */
1815	STRENTRY("Reserved7 "), /* 0x07 */
1816	STRENTRY("Reserved8 "), /* 0x08 */
1817	STRENTRY("TSS64Avail "), /* 0x09 */
1818	STRENTRY("ReservedA "), /* 0x0a */
1819	STRENTRY("TSS64Busy "), /* 0x0b */
1820	STRENTRY("Call64 "), /* 0x0c */
1821	STRENTRY("ReservedD "), /* 0x0d */
1822	STRENTRY("Int64 "), /* 0x0e */
1823	STRENTRY("Trap64 "), /* 0x0f */
1824	# else
1825	STRENTRY("Reserved0 "), /* 0x00 */
1826	STRENTRY("TSS16Avail "), /* 0x01 */
1827	STRENTRY("LDT "), /* 0x02 */
1828	STRENTRY("TSS16Busy "), /* 0x03 */
1829	STRENTRY("Call16 "), /* 0x04 */
1830	STRENTRY("Task "), /* 0x05 */
1831	STRENTRY("Int16 "), /* 0x06 */
1832	STRENTRY("Trap16 "), /* 0x07 */
1833	STRENTRY("Reserved8 "), /* 0x08 */
1834	STRENTRY("TSS32Avail "), /* 0x09 */
1835	STRENTRY("ReservedA "), /* 0x0a */
1836	STRENTRY("TSS32Busy "), /* 0x0b */
1837	STRENTRY("Call32 "), /* 0x0c */
1838	STRENTRY("ReservedD "), /* 0x0d */
1839	STRENTRY("Int32 "), /* 0x0e */
1840	STRENTRY("Trap32 "), /* 0x0f */
1841	# endif
1842	/* non system */
1843	STRENTRY("DataRO "), /* 0x10 */
1844	STRENTRY("DataRO Accessed "), /* 0x11 */
1845	STRENTRY("DataRW "), /* 0x12 */
1846	STRENTRY("DataRW Accessed "), /* 0x13 */
1847	STRENTRY("DataDownRO "), /* 0x14 */
1848	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1849	STRENTRY("DataDownRW "), /* 0x16 */
1850	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1851	STRENTRY("CodeEO "), /* 0x18 */
1852	STRENTRY("CodeEO Accessed "), /* 0x19 */
1853	STRENTRY("CodeER "), /* 0x1a */
1854	STRENTRY("CodeER Accessed "), /* 0x1b */
1855	STRENTRY("CodeConfEO "), /* 0x1c */
1856	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1857	STRENTRY("CodeConfER "), /* 0x1e */
1858	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1859	# undef SYSENTRY
1860	};
1861	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1862	char szMsg[128];
1863	char *psz = &szMsg[0];
1864	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1865	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1866	psz += s_aTypes[i].cch;
1867
1868	if (pDesc->Gen.u1Present)
1869	ADD_STR(psz, "Present ");
1870	else
1871	ADD_STR(psz, "Not-Present ");
1872	# if HC_ARCH_BITS == 64
1873	if (pDesc->Gen.u1Long)
1874	ADD_STR(psz, "64-bit ");
1875	else
1876	ADD_STR(psz, "Comp ");
1877	# else
1878	if (pDesc->Gen.u1Granularity)
1879	ADD_STR(psz, "Page ");
1880	if (pDesc->Gen.u1DefBig)
1881	ADD_STR(psz, "32-bit ");
1882	else
1883	ADD_STR(psz, "16-bit ");
1884	# endif
1885	# undef ADD_STR
1886	*psz = '\0';
1887
1888	/*
1889	* Limit and Base and format the output.
1890	*/
1891	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1892
1893	# if HC_ARCH_BITS == 64
1894	uint64_t u32Base = X86DESC64_BASE(pDesc);
1895
1896	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1897	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1898	# else
1899	uint32_t u32Base = X86DESC_BASE(pDesc);
1900
1901	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1902	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1903	# endif
1904	}
1905
1906
1907	/**
1908	* Formats a full register dump.
1909	*
1910	* @param pVM Pointer to the VM.
1911	* @param pVCpu Pointer to the VMCPU.
1912	* @param pCtx Pointer to the CPU context.
1913	*/
1914	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1915	{
1916	NOREF(pVM);
1917
1918	/*
1919	* Format the flags.
1920	*/
1921	static struct
1922	{
1923	const char pszSet; const char pszClear; uint32_t fFlag;
1924	} const s_aFlags[] =
1925	{
1926	{ "vip",NULL, X86_EFL_VIP },
1927	{ "vif",NULL, X86_EFL_VIF },
1928	{ "ac", NULL, X86_EFL_AC },
1929	{ "vm", NULL, X86_EFL_VM },
1930	{ "rf", NULL, X86_EFL_RF },
1931	{ "nt", NULL, X86_EFL_NT },
1932	{ "ov", "nv", X86_EFL_OF },
1933	{ "dn", "up", X86_EFL_DF },
1934	{ "ei", "di", X86_EFL_IF },
1935	{ "tf", NULL, X86_EFL_TF },
1936	{ "nt", "pl", X86_EFL_SF },
1937	{ "nz", "zr", X86_EFL_ZF },
1938	{ "ac", "na", X86_EFL_AF },
1939	{ "po", "pe", X86_EFL_PF },
1940	{ "cy", "nc", X86_EFL_CF },
1941	};
1942	char szEFlags[80];
1943	char *psz = szEFlags;
1944	uint32_t efl = pCtx->eflags.u32;
1945	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1946	{
1947	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1948	if (pszAdd)
1949	{
1950	strcpy(psz, pszAdd);
1951	psz += strlen(pszAdd);
1952	*psz++ = ' ';
1953	}
1954	}
1955	psz[-1] = '\0';
1956
1957
1958	/*
1959	* Format the registers.
1960	*/
1961	if (CPUMIsGuestIn64BitCode(pVCpu))
1962	{
1963	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1964	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1965	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1966	"r14=%016RX64 r15=%016RX64\n"
1967	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1968	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1969	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1970	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1971	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1972	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1973	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1974	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1975	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1976	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1977	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1978	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1979	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1980	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1981	,
1982	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1983	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1984	pCtx->r14, pCtx->r15,
1985	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1986	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1987	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1988	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1989	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1990	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1991	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1992	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1993	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1994	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1995	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1996	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1997	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1998	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1999	}
2000	else
2001	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2002	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2003	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2004	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2005	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2006	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2007	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2008	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2009	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2010	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2011	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2012	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2013	,
2014	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2015	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2016	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2017	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2018	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2019	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2020	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2021	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2022	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2023	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2024	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2025	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2026
2027	Log(("FPU:\n"
2028	"FCW=%04x FSW=%04x FTW=%02x\n"
2029	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2030	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2031	,
2032	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2033	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2034	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2035	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2036
2037
2038	Log(("MSR:\n"
2039	"EFER =%016RX64\n"
2040	"PAT =%016RX64\n"
2041	"STAR =%016RX64\n"
2042	"CSTAR =%016RX64\n"
2043	"LSTAR =%016RX64\n"
2044	"SFMASK =%016RX64\n"
2045	"KERNELGSBASE =%016RX64\n",
2046	pCtx->msrEFER,
2047	pCtx->msrPAT,
2048	pCtx->msrSTAR,
2049	pCtx->msrCSTAR,
2050	pCtx->msrLSTAR,
2051	pCtx->msrSFMASK,
2052	pCtx->msrKERNELGSBASE));
2053
2054	}
2055
2056	#endif /* VBOX_STRICT */
2057

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 43834

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