HMR0.cpp@ 56690

Last change on this file since 56690 was 56620, checked in by vboxsync, 9 years ago
VMM/HMR0: comments.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 70.4 KB

Line
1	/* $Id: HMR0.cpp 56620 2015-06-24 12:24:28Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <VBox/vmm/hm.h>
23	#include <VBox/vmm/pgm.h>
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/hm_vmx.h>
27	#include <VBox/vmm/hm_svm.h>
28	#include <VBox/vmm/gim.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState, (PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost, void *pvArg));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM ,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	uint64_t u64HostCr4;
117
118	/** Host EFER value (set by ring-0 VMX init) */
119	uint64_t u64HostEfer;
120
121	/** VMX MSR values */
122	VMXMSRS Msrs;
123
124	/* Last instruction error */
125	uint32_t ulLastInstrError;
126	} vmx;
127
128	/** AMD-V information. */
129	struct
130	{
131	/* HWCR MSR (for diagnostics) */
132	uint64_t u64MsrHwcr;
133
134	/** SVM revision. */
135	uint32_t u32Rev;
136
137	/** SVM feature bits from cpuid 0x8000000a */
138	uint32_t u32Features;
139
140	/** Set by us to indicate SVM is supported by the CPU. */
141	bool fSupported;
142	} svm;
143	/** Saved error from detection */
144	int32_t lLastError;
145
146	/** CPUID 0x80000001 ecx:edx features */
147	struct
148	{
149	uint32_t u32AMDFeatureECX;
150	uint32_t u32AMDFeatureEDX;
151	} cpuid;
152
153	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
154	* enabled and disabled each time it's used to execute guest code. */
155	bool fGlobalInit;
156	/** Indicates whether the host is suspending or not. We'll refuse a few
157	* actions when the host is being suspended to speed up the suspending and
158	* avoid trouble. */
159	volatile bool fSuspended;
160
161	/** Whether we've already initialized all CPUs.
162	* @remarks We could check the EnableAllCpusOnce state, but this is
163	* simpler and hopefully easier to understand. */
164	bool fEnabled;
165	/** Serialize initialization in HMR0EnableAllCpus. */
166	RTONCE EnableAllCpusOnce;
167	} g_HmR0;
168
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	/**
212	* Get the CPU ID on which the failure status code was reported.
213	*
214	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
215	* @param pFirstRc The first return code structure.
216	*/
217	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
218	{
219	return pFirstRc->idCpu;
220	}
221	#endif /* VBOX_STRICT */
222
223
224	/** @name Dummy callback handlers.
225	* @{ */
226
227	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
228	{
229	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
234	{
235	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
236	}
237
238	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
239	bool fEnabledBySystem, void *pvArg)
240	{
241	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
242	return VINF_SUCCESS;
243	}
244
245	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
246	{
247	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
252	{
253	NOREF(pVM);
254	return VINF_SUCCESS;
255	}
256
257	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
258	{
259	NOREF(pVM);
260	return VINF_SUCCESS;
261	}
262
263	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
264	{
265	NOREF(pVM);
266	return VINF_SUCCESS;
267	}
268
269	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
270	{
271	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
272	return VINF_SUCCESS;
273	}
274
275	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
276	{
277	NOREF(pVM); NOREF(pVCpu);
278	return VINF_SUCCESS;
279	}
280
281	/** @} */
282
283
284	/**
285	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
286	* Down at the Rate Specified" erratum.
287	*
288	* Errata names and related steppings:
289	* - BA86 - D0.
290	* - AAX65 - C2.
291	* - AAU65 - C2, K0.
292	* - AAO95 - B1.
293	* - AAT59 - C2.
294	* - AAK139 - D0.
295	* - AAM126 - C0, C1, D0.
296	* - AAN92 - B1.
297	* - AAJ124 - C0, D0.
298	*
299	* - AAP86 - B1.
300	*
301	* Steppings: B1, C0, C1, C2, D0, K0.
302	*
303	* @returns true if subject to it, false if not.
304	*/
305	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
306	{
307	uint32_t u = ASMCpuId_EAX(1);
308	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
309	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
310	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
311	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
312	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
313	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
314	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
315	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
316	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
317	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
318	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
319	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
320	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
321	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
322	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
323	)
324	return true;
325	return false;
326	}
327
328
329	/**
330	* Intel specific initialization code.
331	*
332	* @returns VBox status code (will only fail if out of memory).
333	*/
334	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
335	{
336	/*
337	* Check that all the required VT-x features are present.
338	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
339	*/
340	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
341	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
342	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
343	)
344	{
345	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
346	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
347
348	/*
349	* First try use native kernel API for controlling VT-x.
350	* (This is only supported by some Mac OS X kernels atm.)
351	*/
352	int rc = g_HmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
353	g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
354	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
355	{
356	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
357	if (RT_SUCCESS(rc))
358	{
359	g_HmR0.vmx.fSupported = true;
360	rc = SUPR0EnableVTx(false /* fEnable */);
361	AssertLogRelRC(rc);
362	}
363	}
364	else
365	{
366	HMR0FIRSTRC FirstRc;
367	hmR0FirstRcInit(&FirstRc);
368	g_HmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
369	if (RT_SUCCESS(g_HmR0.lLastError))
370	g_HmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
371	}
372	if (RT_SUCCESS(g_HmR0.lLastError))
373	{
374	/* Reread in case it was changed by SUPR0GetVmxUsability(). */
375	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
376
377	/*
378	* Read all relevant registers and MSRs.
379	*/
380	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
381	g_HmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
382	g_HmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
383	g_HmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
384	g_HmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
385	g_HmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
386	g_HmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
387	g_HmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
388	g_HmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
389	g_HmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
390	g_HmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
391	g_HmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
392	g_HmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
393	/* VPID 16 bits ASID. */
394	g_HmR0.uMaxAsid = 0x10000; /* exclusive */
395
396	if (g_HmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
397	{
398	g_HmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
399	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
400	g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
401
402	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
403	g_HmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
404	}
405
406	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
407	{
408	/*
409	* Enter root mode
410	*/
411	RTR0MEMOBJ hScatchMemObj;
412	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
413	if (RT_FAILURE(rc))
414	{
415	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
416	return rc;
417	}
418
419	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
420	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
421	ASMMemZeroPage(pvScatchPage);
422
423	/* Set revision dword at the beginning of the structure. */
424	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HmR0.vmx.Msrs.u64BasicInfo);
425
426	/* Make sure we don't get rescheduled to another cpu during this probe. */
427	RTCCUINTREG fFlags = ASMIntDisableFlags();
428
429	/*
430	* Check CR4.VMXE
431	*/
432	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
433	if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
434	{
435	/* In theory this bit could be cleared behind our back. Which would cause
436	#UD faults when we try to execute the VMX instructions... */
437	ASMSetCR4(g_HmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
438	}
439
440	/*
441	* The only way of checking if we're in VMX root mode or not is to try and enter it.
442	* There is no instruction or control bit that tells us if we're in VMX root mode.
443	* Therefore, try and enter VMX root mode here.
444	*/
445	rc = VMXEnable(HCPhysScratchPage);
446	if (RT_SUCCESS(rc))
447	{
448	g_HmR0.vmx.fSupported = true;
449	VMXDisable();
450	}
451	else
452	{
453	/*
454	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
455	* it will crash the host when we enter raw mode, because:
456	*
457	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
458	* this bit), and
459	* (b) turning off paging causes a #GP (unavoidable when switching
460	* from long to 32 bits mode or 32 bits to PAE).
461	*
462	* They should fix their code, but until they do we simply refuse to run.
463	*/
464	g_HmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
465	Assert(g_HmR0.vmx.fSupported == false);
466	}
467
468	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
469	if it wasn't so before (some software could incorrectly
470	think it's in VMX mode). */
471	ASMSetCR4(g_HmR0.vmx.u64HostCr4);
472	ASMSetFlags(fFlags);
473
474	RTR0MemObjFree(hScatchMemObj, false);
475	}
476
477	if (g_HmR0.vmx.fSupported)
478	{
479	rc = VMXR0GlobalInit();
480	if (RT_FAILURE(rc))
481	g_HmR0.lLastError = rc;
482
483	/*
484	* Install the VT-x methods.
485	*/
486	g_HmR0.pfnEnterSession = VMXR0Enter;
487	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
488	g_HmR0.pfnSaveHostState = VMXR0SaveHostState;
489	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
490	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
491	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
492	g_HmR0.pfnInitVM = VMXR0InitVM;
493	g_HmR0.pfnTermVM = VMXR0TermVM;
494	g_HmR0.pfnSetupVM = VMXR0SetupVM;
495
496	/*
497	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
498	* Timer Does Not Count Down at the Rate Specified" erratum.
499	*/
500	if (g_HmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
501	{
502	g_HmR0.vmx.fUsePreemptTimer = true;
503	g_HmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HmR0.vmx.Msrs.u64Misc);
504	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
505	g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
506	}
507	}
508	}
509	#ifdef LOG_ENABLED
510	else
511	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HmR0.lLastError);
512	#endif
513	}
514	else
515	g_HmR0.lLastError = VERR_VMX_NO_VMX;
516	return VINF_SUCCESS;
517	}
518
519
520	/**
521	* AMD-specific initialization code.
522	*
523	* @returns VBox status code.
524	*/
525	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
526	{
527	/*
528	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
529	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
530	*/
531	int rc;
532	if ( (g_HmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
533	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
534	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
535	&& ASMIsValidExtRange(uMaxExtLeaf)
536	&& uMaxExtLeaf >= 0x8000000a
537	)
538	{
539	/* Call the global AMD-V initialization routine. */
540	rc = SVMR0GlobalInit();
541	if (RT_FAILURE(rc))
542	{
543	g_HmR0.lLastError = rc;
544	return rc;
545	}
546
547	/*
548	* Install the AMD-V methods.
549	*/
550	g_HmR0.pfnEnterSession = SVMR0Enter;
551	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
552	g_HmR0.pfnSaveHostState = SVMR0SaveHostState;
553	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
554	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
555	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
556	g_HmR0.pfnInitVM = SVMR0InitVM;
557	g_HmR0.pfnTermVM = SVMR0TermVM;
558	g_HmR0.pfnSetupVM = SVMR0SetupVM;
559
560	/* Query AMD features. */
561	uint32_t u32Dummy;
562	ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
563
564	/*
565	* We need to check if AMD-V has been properly initialized on all CPUs.
566	* Some BIOSes might do a poor job.
567	*/
568	HMR0FIRSTRC FirstRc;
569	hmR0FirstRcInit(&FirstRc);
570	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
571	AssertRC(rc);
572	if (RT_SUCCESS(rc))
573	rc = hmR0FirstRcGetStatus(&FirstRc);
574	#ifndef DEBUG_bird
575	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
576	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
577	#endif
578	if (RT_SUCCESS(rc))
579	{
580	/* Read the HWCR MSR for diagnostics. */
581	g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
582	g_HmR0.svm.fSupported = true;
583	}
584	else
585	{
586	g_HmR0.lLastError = rc;
587	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
588	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
589	}
590	}
591	else
592	{
593	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
594	g_HmR0.lLastError = VERR_SVM_NO_SVM;
595	}
596	return rc;
597	}
598
599
600	/**
601	* Does global Ring-0 HM initialization (at module init).
602	*
603	* @returns VBox status code.
604	*/
605	VMMR0_INT_DECL(int) HMR0Init(void)
606	{
607	/*
608	* Initialize the globals.
609	*/
610	g_HmR0.fEnabled = false;
611	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
612	g_HmR0.EnableAllCpusOnce = s_OnceInit;
613	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
614	{
615	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
616	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
617	}
618
619	/* Fill in all callbacks with placeholders. */
620	g_HmR0.pfnEnterSession = hmR0DummyEnter;
621	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
622	g_HmR0.pfnSaveHostState = hmR0DummySaveHostState;
623	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
624	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
625	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
626	g_HmR0.pfnInitVM = hmR0DummyInitVM;
627	g_HmR0.pfnTermVM = hmR0DummyTermVM;
628	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
629
630	/* Default is global VT-x/AMD-V init. */
631	g_HmR0.fGlobalInit = true;
632
633	/*
634	* Make sure aCpuInfo is big enough for all the CPUs on this system.
635	*/
636	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
637	{
638	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
639	return VERR_TOO_MANY_CPUS;
640	}
641
642	/*
643	* Check for VT-x and AMD-V capabilities.
644	*/
645	int rc;
646	if (ASMHasCpuId())
647	{
648	/* Standard features. */
649	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
650	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
651	if (ASMIsValidStdRange(uMaxLeaf))
652	{
653	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
654	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
655
656	/* Query AMD features. */
657	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
658	if (ASMIsValidExtRange(uMaxExtLeaf))
659	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
660	&g_HmR0.cpuid.u32AMDFeatureECX,
661	&g_HmR0.cpuid.u32AMDFeatureEDX);
662	else
663	g_HmR0.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureEDX = 0;
664
665	/* Go to CPU specific initialization code. */
666	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
667	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
668	{
669	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
670	if (RT_FAILURE(rc))
671	return rc;
672	}
673	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
674	{
675	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
676	if (RT_FAILURE(rc))
677	return rc;
678	}
679	else
680	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
681	}
682	else
683	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
684	}
685	else
686	g_HmR0.lLastError = VERR_HM_NO_CPUID;
687
688	/*
689	* Register notification callbacks that we can use to disable/enable CPUs
690	* when brought offline/online or suspending/resuming.
691	*/
692	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
693	{
694	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
695	AssertRC(rc);
696
697	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
698	AssertRC(rc);
699	}
700
701	/* We return success here because module init shall not fail if HM
702	fails to initialize. */
703	return VINF_SUCCESS;
704	}
705
706
707	/**
708	* Does global Ring-0 HM termination (at module termination).
709	*
710	* @returns VBox status code.
711	*/
712	VMMR0_INT_DECL(int) HMR0Term(void)
713	{
714	int rc;
715	if ( g_HmR0.vmx.fSupported
716	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
717	{
718	/*
719	* Simple if the host OS manages VT-x.
720	*/
721	Assert(g_HmR0.fGlobalInit);
722	rc = SUPR0EnableVTx(false /* fEnable */);
723
724	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
725	{
726	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
727	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
728	}
729	}
730	else
731	{
732	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
733
734	/* Doesn't really matter if this fails. */
735	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
736	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
737
738	/*
739	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
740	*/
741	if (g_HmR0.fGlobalInit)
742	{
743	HMR0FIRSTRC FirstRc;
744	hmR0FirstRcInit(&FirstRc);
745	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
746	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
747	if (RT_SUCCESS(rc))
748	rc = hmR0FirstRcGetStatus(&FirstRc);
749	}
750
751	/*
752	* Free the per-cpu pages used for VT-x and AMD-V.
753	*/
754	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
755	{
756	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
757	{
758	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
759	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
760	}
761	}
762	}
763
764	/** @todo This needs cleaning up. There's no matching
765	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
766	* should move into their respective modules. */
767	/* Finally, call global VT-x/AMD-V termination. */
768	if (g_HmR0.vmx.fSupported)
769	VMXR0GlobalTerm();
770	else if (g_HmR0.svm.fSupported)
771	SVMR0GlobalTerm();
772
773	return rc;
774	}
775
776
777	/**
778	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
779	* on a CPU.
780	*
781	* @param idCpu The identifier for the CPU the function is called on.
782	* @param pvUser1 Pointer to the first RC structure.
783	* @param pvUser2 Ignored.
784	*/
785	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
786	{
787	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
788	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
789	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
790	NOREF(idCpu); NOREF(pvUser2);
791
792	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
793	hmR0FirstRcSetStatus(pFirstRc, rc);
794	}
795
796
797	/**
798	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
799	* on a CPU.
800	*
801	* @param idCpu The identifier for the CPU the function is called on.
802	* @param pvUser1 Pointer to the first RC structure.
803	* @param pvUser2 Ignored.
804	*/
805	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
806	{
807	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
808	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
809	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
810	NOREF(idCpu); NOREF(pvUser2);
811
812	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
813	hmR0FirstRcSetStatus(pFirstRc, rc);
814	}
815
816
817	/**
818	* Enable VT-x or AMD-V on the current CPU
819	*
820	* @returns VBox status code.
821	* @param pVM Pointer to the VM (can be NULL).
822	* @param idCpu The identifier for the CPU the function is called on.
823	*
824	* @remarks Maybe called with interrupts disabled!
825	*/
826	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
827	{
828	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
829
830	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
831	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
832	Assert(!pCpu->fConfigured);
833	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
834
835	pCpu->idCpu = idCpu;
836	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
837
838	int rc;
839	if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
840	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
841	else
842	{
843	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
844	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
845	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0 /* iPage */);
846
847	if (g_HmR0.vmx.fSupported)
848	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HmR0.vmx.Msrs);
849	else
850	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
851	}
852	if (RT_SUCCESS(rc))
853	pCpu->fConfigured = true;
854
855	return rc;
856	}
857
858
859	/**
860	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
861	*
862	* @param idCpu The identifier for the CPU the function is called on.
863	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
864	* @param pvUser2 The 2nd user argument.
865	*/
866	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
867	{
868	PVM pVM = (PVM)pvUser1; /* can be NULL! */
869	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
870	AssertReturnVoid(g_HmR0.fGlobalInit);
871	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
872	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
873	}
874
875
876	/**
877	* RTOnce callback employed by HMR0EnableAllCpus.
878	*
879	* @returns VBox status code.
880	* @param pvUser Pointer to the VM.
881	* @param pvUserIgnore NULL, ignored.
882	*/
883	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
884	{
885	PVM pVM = (PVM)pvUser;
886
887	/*
888	* Indicate that we've initialized.
889	*
890	* Note! There is a potential race between this function and the suspend
891	* notification. Kind of unlikely though, so ignored for now.
892	*/
893	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
894	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
895
896	/*
897	* The global init variable is set by the first VM.
898	*/
899	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
900
901	#ifdef VBOX_STRICT
902	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
903	{
904	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
905	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
906	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
907	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
908	}
909	#endif
910
911	int rc;
912	if ( g_HmR0.vmx.fSupported
913	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
914	{
915	/*
916	* Global VT-x initialization API (only darwin for now).
917	*/
918	rc = SUPR0EnableVTx(true /* fEnable */);
919	if (RT_SUCCESS(rc))
920	{
921	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
922	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
923	}
924	else
925	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
926	}
927	else
928	{
929	/*
930	* We're doing the job ourselves.
931	*/
932	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
933	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
934	{
935	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
936
937	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
938	{
939	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
940	AssertLogRelRCReturn(rc, rc);
941
942	void *pvR0 = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
943	ASMMemZeroPage(pvR0);
944	}
945	}
946
947	rc = VINF_SUCCESS;
948	}
949
950	if ( RT_SUCCESS(rc)
951	&& g_HmR0.fGlobalInit)
952	{
953	/* First time, so initialize each cpu/core. */
954	HMR0FIRSTRC FirstRc;
955	hmR0FirstRcInit(&FirstRc);
956	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
957	if (RT_SUCCESS(rc))
958	rc = hmR0FirstRcGetStatus(&FirstRc);
959	}
960
961	return rc;
962	}
963
964
965	/**
966	* Sets up HM on all cpus.
967	*
968	* @returns VBox status code.
969	* @param pVM Pointer to the VM.
970	*/
971	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
972	{
973	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
974	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
975	return VERR_HM_SUSPEND_PENDING;
976
977	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
978	}
979
980
981	/**
982	* Disable VT-x or AMD-V on the current CPU.
983	*
984	* @returns VBox status code.
985	* @param idCpu The identifier for the CPU this function is called on.
986	*
987	* @remarks Must be called with preemption disabled.
988	*/
989	static int hmR0DisableCpu(RTCPUID idCpu)
990	{
991	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
992
993	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
994	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
995	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
996	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
997	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
998	AssertRelease(idCpu == RTMpCpuId());
999
1000	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1001	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1002
1003	int rc;
1004	if (pCpu->fConfigured)
1005	{
1006	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1007	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1008
1009	rc = g_HmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1010	AssertRCReturn(rc, rc);
1011
1012	pCpu->fConfigured = false;
1013	pCpu->idCpu = NIL_RTCPUID;
1014	}
1015	else
1016	rc = VINF_SUCCESS; /* nothing to do */
1017	return rc;
1018	}
1019
1020
1021	/**
1022	* Worker function passed to RTMpOnAll() that is to be called on the target
1023	* CPUs.
1024	*
1025	* @param idCpu The identifier for the CPU the function is called on.
1026	* @param pvUser1 The 1st user argument.
1027	* @param pvUser2 Opaque pointer to the FirstRc.
1028	*/
1029	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1030	{
1031	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1032	AssertReturnVoid(g_HmR0.fGlobalInit);
1033	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1034	}
1035
1036
1037	/**
1038	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1039	* CPU.
1040	*
1041	* @param idCpu The identifier for the CPU the function is called on.
1042	* @param pvUser1 Null, not used.
1043	* @param pvUser2 Null, not used.
1044	*/
1045	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1046	{
1047	NOREF(pvUser1);
1048	NOREF(pvUser2);
1049	hmR0DisableCpu(idCpu);
1050	}
1051
1052
1053	/**
1054	* Callback function invoked when a cpu goes online or offline.
1055	*
1056	* @param enmEvent The Mp event.
1057	* @param idCpu The identifier for the CPU the function is called on.
1058	* @param pvData Opaque data (PVM pointer).
1059	*/
1060	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1061	{
1062	NOREF(pvData);
1063	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1064
1065	/*
1066	* We only care about uninitializing a CPU that is going offline. When a
1067	* CPU comes online, the initialization is done lazily in HMR0Enter().
1068	*/
1069	switch (enmEvent)
1070	{
1071	case RTMPEVENT_OFFLINE:
1072	{
1073	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1074	RTThreadPreemptDisable(&PreemptState);
1075	if (idCpu == RTMpCpuId())
1076	{
1077	int rc = hmR0DisableCpu(idCpu);
1078	AssertRC(rc);
1079	RTThreadPreemptRestore(&PreemptState);
1080	}
1081	else
1082	{
1083	RTThreadPreemptRestore(&PreemptState);
1084	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1085	}
1086	break;
1087	}
1088
1089	default:
1090	break;
1091	}
1092	}
1093
1094
1095	/**
1096	* Called whenever a system power state change occurs.
1097	*
1098	* @param enmEvent The Power event.
1099	* @param pvUser User argument.
1100	*/
1101	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1102	{
1103	NOREF(pvUser);
1104	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1105
1106	#ifdef LOG_ENABLED
1107	if (enmEvent == RTPOWEREVENT_SUSPEND)
1108	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1109	else
1110	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1111	#endif
1112
1113	if (enmEvent == RTPOWEREVENT_SUSPEND)
1114	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1115
1116	if (g_HmR0.fEnabled)
1117	{
1118	int rc;
1119	HMR0FIRSTRC FirstRc;
1120	hmR0FirstRcInit(&FirstRc);
1121
1122	if (enmEvent == RTPOWEREVENT_SUSPEND)
1123	{
1124	if (g_HmR0.fGlobalInit)
1125	{
1126	/* Turn off VT-x or AMD-V on all CPUs. */
1127	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1128	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1129	}
1130	/* else nothing to do here for the local init case */
1131	}
1132	else
1133	{
1134	/* Reinit the CPUs from scratch as the suspend state might have
1135	messed with the MSRs. (lousy BIOSes as usual) */
1136	if (g_HmR0.vmx.fSupported)
1137	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1138	else
1139	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1140	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1141	if (RT_SUCCESS(rc))
1142	rc = hmR0FirstRcGetStatus(&FirstRc);
1143	#ifdef LOG_ENABLED
1144	if (RT_FAILURE(rc))
1145	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1146	#endif
1147	if (g_HmR0.fGlobalInit)
1148	{
1149	/* Turn VT-x or AMD-V back on on all CPUs. */
1150	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1151	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1152	}
1153	/* else nothing to do here for the local init case */
1154	}
1155	}
1156
1157	if (enmEvent == RTPOWEREVENT_RESUME)
1158	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1159	}
1160
1161
1162	/**
1163	* Does ring-0 per-VM HM initialization.
1164	*
1165	* This will copy HM global into the VM structure and call the CPU specific
1166	* init routine which will allocate resources for each virtual CPU and such.
1167	*
1168	* @returns VBox status code.
1169	* @param pVM Pointer to the VM.
1170	*
1171	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1172	* vmR3InitRing3().
1173	*/
1174	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1175	{
1176	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1177
1178	#ifdef LOG_ENABLED
1179	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1180	#endif
1181
1182	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1183	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1184	return VERR_HM_SUSPEND_PENDING;
1185
1186	/*
1187	* Copy globals to the VM structure.
1188	*/
1189	pVM->hm.s.vmx.fSupported = g_HmR0.vmx.fSupported;
1190	pVM->hm.s.svm.fSupported = g_HmR0.svm.fSupported;
1191
1192	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1193	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.vmx.cPreemptTimerShift;
1194	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.vmx.u64HostCr4;
1195	pVM->hm.s.vmx.u64HostEfer = g_HmR0.vmx.u64HostEfer;
1196	pVM->hm.s.vmx.Msrs = g_HmR0.vmx.Msrs;
1197	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.svm.u64MsrHwcr;
1198	pVM->hm.s.svm.u32Rev = g_HmR0.svm.u32Rev;
1199	pVM->hm.s.svm.u32Features = g_HmR0.svm.u32Features;
1200	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureECX;
1201	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HmR0.cpuid.u32AMDFeatureEDX;
1202	pVM->hm.s.lLastError = g_HmR0.lLastError;
1203	pVM->hm.s.uMaxAsid = g_HmR0.uMaxAsid;
1204
1205	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1206	{
1207	pVM->hm.s.cMaxResumeLoops = 1024;
1208	if (RTThreadPreemptIsPendingTrusty())
1209	pVM->hm.s.cMaxResumeLoops = 8192;
1210	}
1211
1212	/*
1213	* Initialize some per-VCPU fields.
1214	*/
1215	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1216	{
1217	PVMCPU pVCpu = &pVM->aCpus[i];
1218	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1219	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1220	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1221
1222	/* We'll aways increment this the first time (host uses ASID 0). */
1223	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1224	}
1225
1226	pVM->hm.s.uHostKernelFeatures = SUPR0GetKernelFeatures();
1227
1228	/*
1229	* Call the hardware specific initialization method.
1230	*/
1231	return g_HmR0.pfnInitVM(pVM);
1232	}
1233
1234
1235	/**
1236	* Does ring-0 per VM HM termination.
1237	*
1238	* @returns VBox status code.
1239	* @param pVM Pointer to the VM.
1240	*/
1241	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1242	{
1243	Log(("HMR0TermVM: %p\n", pVM));
1244	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1245
1246	/*
1247	* Call the hardware specific method.
1248	*
1249	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1250	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1251	*/
1252	return g_HmR0.pfnTermVM(pVM);
1253	}
1254
1255
1256	/**
1257	* Sets up a VT-x or AMD-V session.
1258	*
1259	* This is mostly about setting up the hardware VM state.
1260	*
1261	* @returns VBox status code.
1262	* @param pVM Pointer to the VM.
1263	*/
1264	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1265	{
1266	Log(("HMR0SetupVM: %p\n", pVM));
1267	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1268
1269	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1270	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1271
1272	/* On first entry we'll sync everything. */
1273	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1274	HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1275
1276	/*
1277	* Call the hardware specific setup VM method. This requires the CPU to be
1278	* enabled for AMD-V/VT-x and preemption to be prevented.
1279	*/
1280	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1281	RTThreadPreemptDisable(&PreemptState);
1282	RTCPUID idCpu = RTMpCpuId();
1283
1284	/* Enable VT-x or AMD-V if local init is required. */
1285	int rc;
1286	if (!g_HmR0.fGlobalInit)
1287	{
1288	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1289	rc = hmR0EnableCpu(pVM, idCpu);
1290	if (RT_FAILURE(rc))
1291	{
1292	RTThreadPreemptRestore(&PreemptState);
1293	return rc;
1294	}
1295	}
1296
1297	/* Setup VT-x or AMD-V. */
1298	rc = g_HmR0.pfnSetupVM(pVM);
1299
1300	/* Disable VT-x or AMD-V if local init was done before. */
1301	if (!g_HmR0.fGlobalInit)
1302	{
1303	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1304	int rc2 = hmR0DisableCpu(idCpu);
1305	AssertRC(rc2);
1306	}
1307
1308	RTThreadPreemptRestore(&PreemptState);
1309	return rc;
1310	}
1311
1312
1313	/**
1314	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1315	* required for entering HM context.
1316	*
1317	* @returns VBox status code.
1318	* @param pvCpu Pointer to the VMCPU.
1319	*
1320	* @remarks No-long-jump zone!!!
1321	*/
1322	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1323	{
1324	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1325
1326	int rc = VINF_SUCCESS;
1327	RTCPUID idCpu = RTMpCpuId();
1328	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1329	AssertPtr(pCpu);
1330
1331	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1332	if (!pCpu->fConfigured)
1333	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1334
1335	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1336	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1337
1338	Assert(pCpu->idCpu == idCpu && pCpu->idCpu != NIL_RTCPUID);
1339	pVCpu->hm.s.idEnteredCpu = idCpu;
1340	return rc;
1341	}
1342
1343
1344	/**
1345	* Enters the VT-x or AMD-V session.
1346	*
1347	* @returns VBox status code.
1348	* @param pVM Pointer to the VM.
1349	* @param pVCpu Pointer to the VMCPU.
1350	*
1351	* @remarks This is called with preemption disabled.
1352	*/
1353	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1354	{
1355	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1356	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1357	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1358
1359	/* Load the bare minimum state required for entering HM. */
1360	int rc = HMR0EnterCpu(pVCpu);
1361	AssertRCReturn(rc, rc);
1362
1363	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1364	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1365	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1366	#endif
1367
1368	RTCPUID idCpu = RTMpCpuId();
1369	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1370	Assert(pCpu);
1371	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1372
1373	rc = g_HmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1374	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1375
1376	/* Load the host-state as we may be resuming code after a longjmp and quite
1377	possibly now be scheduled on a different CPU. */
1378	rc = g_HmR0.pfnSaveHostState(pVM, pVCpu);
1379	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1380
1381	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1382	if (fStartedSet)
1383	PGMRZDynMapReleaseAutoSet(pVCpu);
1384	#endif
1385
1386	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1387	if (RT_FAILURE(rc))
1388	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1389	return rc;
1390	}
1391
1392
1393	/**
1394	* Deinitializes the bare minimum state used for HM context and if necessary
1395	* disable HM on the CPU.
1396	*
1397	* @returns VBox status code.
1398	* @param pVCpu Pointer to the VMCPU.
1399	*
1400	* @remarks No-long-jump zone!!!
1401	*/
1402	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1403	{
1404	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1405	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1406
1407	RTCPUID idCpu = RTMpCpuId();
1408	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1409
1410	if ( !g_HmR0.fGlobalInit
1411	&& pCpu->fConfigured)
1412	{
1413	int rc = hmR0DisableCpu(idCpu);
1414	AssertRCReturn(rc, rc);
1415	Assert(!pCpu->fConfigured);
1416	Assert(pCpu->idCpu == NIL_RTCPUID);
1417
1418	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1419	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1420	}
1421
1422	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1423	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1424
1425	return VINF_SUCCESS;
1426	}
1427
1428
1429	/**
1430	* Thread-context hook for HM.
1431	*
1432	* @param enmEvent The thread-context event.
1433	* @param pvUser Opaque pointer to the VMCPU.
1434	*/
1435	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1436	{
1437	PVMCPU pVCpu = (PVMCPU)pvUser;
1438	Assert(pVCpu);
1439	Assert(g_HmR0.pfnThreadCtxCallback);
1440
1441	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1442	}
1443
1444
1445	/**
1446	* Runs guest code in a hardware accelerated VM.
1447	*
1448	* @returns VBox status code.
1449	* @param pVM Pointer to the VM.
1450	* @param pVCpu Pointer to the VMCPU.
1451	*
1452	* @remarks Can be called with preemption enabled if thread-context hooks are
1453	* used!!!
1454	*/
1455	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1456	{
1457	#ifdef VBOX_STRICT
1458	/* With thread-context hooks we would be running this code with preemption enabled. */
1459	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1460	{
1461	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1462	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1463	Assert(pCpu->fConfigured);
1464	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1465	}
1466	#endif
1467
1468	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1469	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1470	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1471	PGMRZDynMapStartAutoSet(pVCpu);
1472	#endif
1473
1474	int rc = g_HmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1475
1476	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1477	PGMRZDynMapReleaseAutoSet(pVCpu);
1478	#endif
1479	return rc;
1480	}
1481
1482	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1483
1484	/**
1485	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1486	*
1487	* @returns VBox status code.
1488	* @param pVM Pointer to the VM.
1489	* @param pVCpu Pointer to the VMCPU.
1490	* @param pCtx Pointer to the guest CPU context.
1491	*/
1492	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1493	{
1494	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1495	if (pVM->hm.s.vmx.fSupported)
1496	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1497	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1498	}
1499
1500
1501	/**
1502	* Save guest debug state (64 bits guest mode & 32 bits host only)
1503	*
1504	* @returns VBox status code.
1505	* @param pVM Pointer to the VM.
1506	* @param pVCpu Pointer to the VMCPU.
1507	* @param pCtx Pointer to the guest CPU context.
1508	*/
1509	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1510	{
1511	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1512	if (pVM->hm.s.vmx.fSupported)
1513	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1514	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1515	}
1516
1517
1518	/**
1519	* Test the 32->64 bits switcher.
1520	*
1521	* @returns VBox status code.
1522	* @param pVM Pointer to the VM.
1523	*/
1524	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1525	{
1526	PVMCPU pVCpu = &pVM->aCpus[0];
1527	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1528	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1529	int rc;
1530
1531	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1532	if (pVM->hm.s.vmx.fSupported)
1533	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1534	else
1535	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1536	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1537
1538	return rc;
1539	}
1540
1541	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1542
1543	/**
1544	* Returns suspend status of the host.
1545	*
1546	* @returns Suspend pending or not.
1547	*/
1548	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1549	{
1550	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1551	}
1552
1553
1554	/**
1555	* Returns the cpu structure for the current cpu.
1556	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1557	*
1558	* @returns The cpu structure pointer.
1559	*/
1560	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1561	{
1562	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1563	RTCPUID idCpu = RTMpCpuId();
1564	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1565	return &g_HmR0.aCpuInfo[idCpu];
1566	}
1567
1568
1569	/**
1570	* Returns the cpu structure for the current cpu.
1571	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1572	*
1573	* @returns The cpu structure pointer.
1574	* @param idCpu id of the VCPU.
1575	*/
1576	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1577	{
1578	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1579	return &g_HmR0.aCpuInfo[idCpu];
1580	}
1581
1582
1583	/**
1584	* Save a pending IO read.
1585	*
1586	* @param pVCpu Pointer to the VMCPU.
1587	* @param GCPtrRip Address of IO instruction.
1588	* @param GCPtrRipNext Address of the next instruction.
1589	* @param uPort Port address.
1590	* @param uAndVal AND mask for saving the result in eax.
1591	* @param cbSize Read size.
1592	*/
1593	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1594	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1595	{
1596	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1597	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1598	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1599	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1600	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1601	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1602	return;
1603	}
1604
1605
1606	/**
1607	* Save a pending IO write.
1608	*
1609	* @param pVCpu Pointer to the VMCPU.
1610	* @param GCPtrRIP Address of IO instruction.
1611	* @param uPort Port address.
1612	* @param uAndVal AND mask for fetching the result from eax.
1613	* @param cbSize Read size.
1614	*/
1615	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1616	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1617	{
1618	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1619	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1620	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1621	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1622	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1623	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1624	return;
1625	}
1626
1627	#ifdef VBOX_WITH_RAW_MODE
1628
1629	/**
1630	* Raw-mode switcher hook - disable VT-x if it's active and the current
1631	* switcher turns off paging.
1632	*
1633	* @returns VBox status code.
1634	* @param pVM Pointer to the VM.
1635	* @param enmSwitcher The switcher we're about to use.
1636	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1637	*/
1638	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1639	{
1640	NOREF(pVM);
1641
1642	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1643
1644	*pfVTxDisabled = false;
1645
1646	/* No such issues with AMD-V */
1647	if (!g_HmR0.vmx.fSupported)
1648	return VINF_SUCCESS;
1649
1650	/* Check if the switching we're up to is safe. */
1651	switch (enmSwitcher)
1652	{
1653	case VMMSWITCHER_32_TO_32:
1654	case VMMSWITCHER_PAE_TO_PAE:
1655	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1656
1657	case VMMSWITCHER_32_TO_PAE:
1658	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1659	case VMMSWITCHER_AMD64_TO_32:
1660	case VMMSWITCHER_AMD64_TO_PAE:
1661	break; /* unsafe switchers */
1662
1663	default:
1664	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1665	}
1666
1667	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1668	regardless of whether we're currently using VT-x or not. */
1669	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1670	{
1671	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1672	return VINF_SUCCESS;
1673	}
1674
1675	/** @todo Check if this code is presumptive wrt other VT-x users on the
1676	* system... */
1677
1678	/* Nothing to do if we haven't enabled VT-x. */
1679	if (!g_HmR0.fEnabled)
1680	return VINF_SUCCESS;
1681
1682	/* Local init implies the CPU is currently not in VMX root mode. */
1683	if (!g_HmR0.fGlobalInit)
1684	return VINF_SUCCESS;
1685
1686	/* Ok, disable VT-x. */
1687	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1688	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1689
1690	*pfVTxDisabled = true;
1691	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1692	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1693	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1694	}
1695
1696
1697	/**
1698	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1699	* switcher turned off paging.
1700	*
1701	* @param pVM Pointer to the VM.
1702	* @param fVTxDisabled Whether VT-x was disabled or not.
1703	*/
1704	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1705	{
1706	Assert(!ASMIntAreEnabled());
1707
1708	if (!fVTxDisabled)
1709	return; /* nothing to do */
1710
1711	Assert(g_HmR0.vmx.fSupported);
1712	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1713	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1714	else
1715	{
1716	Assert(g_HmR0.fEnabled);
1717	Assert(g_HmR0.fGlobalInit);
1718
1719	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1720	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1721
1722	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1723	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1724	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HmR0.vmx.Msrs);
1725	}
1726	}
1727
1728	#endif /* VBOX_WITH_RAW_MODE */
1729	#ifdef VBOX_STRICT
1730
1731	/**
1732	* Dumps a descriptor.
1733	*
1734	* @param pDesc Descriptor to dump.
1735	* @param Sel Selector number.
1736	* @param pszMsg Message to prepend the log entry with.
1737	*/
1738	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1739	{
1740	/*
1741	* Make variable description string.
1742	*/
1743	static struct
1744	{
1745	unsigned cch;
1746	const char *psz;
1747	} const s_aTypes[32] =
1748	{
1749	# define STRENTRY(str) { sizeof(str) - 1, str }
1750
1751	/* system */
1752	# if HC_ARCH_BITS == 64
1753	STRENTRY("Reserved0 "), /* 0x00 */
1754	STRENTRY("Reserved1 "), /* 0x01 */
1755	STRENTRY("LDT "), /* 0x02 */
1756	STRENTRY("Reserved3 "), /* 0x03 */
1757	STRENTRY("Reserved4 "), /* 0x04 */
1758	STRENTRY("Reserved5 "), /* 0x05 */
1759	STRENTRY("Reserved6 "), /* 0x06 */
1760	STRENTRY("Reserved7 "), /* 0x07 */
1761	STRENTRY("Reserved8 "), /* 0x08 */
1762	STRENTRY("TSS64Avail "), /* 0x09 */
1763	STRENTRY("ReservedA "), /* 0x0a */
1764	STRENTRY("TSS64Busy "), /* 0x0b */
1765	STRENTRY("Call64 "), /* 0x0c */
1766	STRENTRY("ReservedD "), /* 0x0d */
1767	STRENTRY("Int64 "), /* 0x0e */
1768	STRENTRY("Trap64 "), /* 0x0f */
1769	# else
1770	STRENTRY("Reserved0 "), /* 0x00 */
1771	STRENTRY("TSS16Avail "), /* 0x01 */
1772	STRENTRY("LDT "), /* 0x02 */
1773	STRENTRY("TSS16Busy "), /* 0x03 */
1774	STRENTRY("Call16 "), /* 0x04 */
1775	STRENTRY("Task "), /* 0x05 */
1776	STRENTRY("Int16 "), /* 0x06 */
1777	STRENTRY("Trap16 "), /* 0x07 */
1778	STRENTRY("Reserved8 "), /* 0x08 */
1779	STRENTRY("TSS32Avail "), /* 0x09 */
1780	STRENTRY("ReservedA "), /* 0x0a */
1781	STRENTRY("TSS32Busy "), /* 0x0b */
1782	STRENTRY("Call32 "), /* 0x0c */
1783	STRENTRY("ReservedD "), /* 0x0d */
1784	STRENTRY("Int32 "), /* 0x0e */
1785	STRENTRY("Trap32 "), /* 0x0f */
1786	# endif
1787	/* non system */
1788	STRENTRY("DataRO "), /* 0x10 */
1789	STRENTRY("DataRO Accessed "), /* 0x11 */
1790	STRENTRY("DataRW "), /* 0x12 */
1791	STRENTRY("DataRW Accessed "), /* 0x13 */
1792	STRENTRY("DataDownRO "), /* 0x14 */
1793	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1794	STRENTRY("DataDownRW "), /* 0x16 */
1795	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1796	STRENTRY("CodeEO "), /* 0x18 */
1797	STRENTRY("CodeEO Accessed "), /* 0x19 */
1798	STRENTRY("CodeER "), /* 0x1a */
1799	STRENTRY("CodeER Accessed "), /* 0x1b */
1800	STRENTRY("CodeConfEO "), /* 0x1c */
1801	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1802	STRENTRY("CodeConfER "), /* 0x1e */
1803	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1804	# undef SYSENTRY
1805	};
1806	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1807	char szMsg[128];
1808	char *psz = &szMsg[0];
1809	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1810	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1811	psz += s_aTypes[i].cch;
1812
1813	if (pDesc->Gen.u1Present)
1814	ADD_STR(psz, "Present ");
1815	else
1816	ADD_STR(psz, "Not-Present ");
1817	# if HC_ARCH_BITS == 64
1818	if (pDesc->Gen.u1Long)
1819	ADD_STR(psz, "64-bit ");
1820	else
1821	ADD_STR(psz, "Comp ");
1822	# else
1823	if (pDesc->Gen.u1Granularity)
1824	ADD_STR(psz, "Page ");
1825	if (pDesc->Gen.u1DefBig)
1826	ADD_STR(psz, "32-bit ");
1827	else
1828	ADD_STR(psz, "16-bit ");
1829	# endif
1830	# undef ADD_STR
1831	*psz = '\0';
1832
1833	/*
1834	* Limit and Base and format the output.
1835	*/
1836	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1837
1838	# if HC_ARCH_BITS == 64
1839	uint64_t u32Base = X86DESC64_BASE(pDesc);
1840	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1841	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1842	# else
1843	uint32_t u32Base = X86DESC_BASE(pDesc);
1844	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1845	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1846	# endif
1847	}
1848
1849
1850	/**
1851	* Formats a full register dump.
1852	*
1853	* @param pVM Pointer to the VM.
1854	* @param pVCpu Pointer to the VMCPU.
1855	* @param pCtx Pointer to the CPU context.
1856	*/
1857	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1858	{
1859	NOREF(pVM);
1860
1861	/*
1862	* Format the flags.
1863	*/
1864	static struct
1865	{
1866	const char pszSet; const char pszClear; uint32_t fFlag;
1867	} const s_aFlags[] =
1868	{
1869	{ "vip", NULL, X86_EFL_VIP },
1870	{ "vif", NULL, X86_EFL_VIF },
1871	{ "ac", NULL, X86_EFL_AC },
1872	{ "vm", NULL, X86_EFL_VM },
1873	{ "rf", NULL, X86_EFL_RF },
1874	{ "nt", NULL, X86_EFL_NT },
1875	{ "ov", "nv", X86_EFL_OF },
1876	{ "dn", "up", X86_EFL_DF },
1877	{ "ei", "di", X86_EFL_IF },
1878	{ "tf", NULL, X86_EFL_TF },
1879	{ "nt", "pl", X86_EFL_SF },
1880	{ "nz", "zr", X86_EFL_ZF },
1881	{ "ac", "na", X86_EFL_AF },
1882	{ "po", "pe", X86_EFL_PF },
1883	{ "cy", "nc", X86_EFL_CF },
1884	};
1885	char szEFlags[80];
1886	char *psz = szEFlags;
1887	uint32_t uEFlags = pCtx->eflags.u32;
1888	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1889	{
1890	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1891	if (pszAdd)
1892	{
1893	strcpy(psz, pszAdd);
1894	psz += strlen(pszAdd);
1895	*psz++ = ' ';
1896	}
1897	}
1898	psz[-1] = '\0';
1899
1900
1901	/*
1902	* Format the registers.
1903	*/
1904	if (CPUMIsGuestIn64BitCode(pVCpu))
1905	{
1906	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1907	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1908	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1909	"r14=%016RX64 r15=%016RX64\n"
1910	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1911	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1912	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1913	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1914	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1915	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1916	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1917	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1918	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1919	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1920	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1921	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1922	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1923	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1924	,
1925	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1926	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1927	pCtx->r14, pCtx->r15,
1928	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1929	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1930	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1931	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1932	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1933	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1934	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1935	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1936	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1937	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1938	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1939	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1940	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1941	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1942	}
1943	else
1944	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1945	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1946	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1947	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1948	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1949	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1950	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1951	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1952	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1953	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1954	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1955	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1956	,
1957	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1958	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1959	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1960	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1961	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1962	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1963	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1964	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1965	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1966	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1967	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1968	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1969
1970	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1971	Log(("FPU:\n"
1972	"FCW=%04x FSW=%04x FTW=%02x\n"
1973	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1974	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1975	,
1976	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1977	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1978	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1979	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1980
1981	Log(("MSR:\n"
1982	"EFER =%016RX64\n"
1983	"PAT =%016RX64\n"
1984	"STAR =%016RX64\n"
1985	"CSTAR =%016RX64\n"
1986	"LSTAR =%016RX64\n"
1987	"SFMASK =%016RX64\n"
1988	"KERNELGSBASE =%016RX64\n",
1989	pCtx->msrEFER,
1990	pCtx->msrPAT,
1991	pCtx->msrSTAR,
1992	pCtx->msrCSTAR,
1993	pCtx->msrLSTAR,
1994	pCtx->msrSFMASK,
1995	pCtx->msrKERNELGSBASE));
1996	}
1997
1998	#endif /* VBOX_STRICT */
1999

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 56690

Download in other formats: