HMR0.cpp@ 101388

Last change on this file since 101388 was 101388, checked in by vboxsync, 14 months ago
VMM/HMR0: bugref:9918 Comment typo.
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1	/* $Id: HMR0.cpp 101388 2023-10-09 06:34:15Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_HM
33	#define VMCPU_INCL_CPUM_GST_CTX
34	#include <VBox/vmm/hm.h>
35	#include <VBox/vmm/pgm.h>
36	#include "HMInternal.h"
37	#include <VBox/vmm/vmcc.h>
38	#include <VBox/vmm/hm_svm.h>
39	#include <VBox/vmm/hmvmxinline.h>
40	#include <VBox/err.h>
41	#include <VBox/log.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/asm-amd64-x86.h>
45	#include <iprt/cpuset.h>
46	#include <iprt/mem.h>
47	#include <iprt/memobj.h>
48	#include <iprt/once.h>
49	#include <iprt/param.h>
50	#include <iprt/power.h>
51	#include <iprt/string.h>
52	#include <iprt/thread.h>
53	#include <iprt/x86.h>
54	#include "HMVMXR0.h"
55	#include "HMSVMR0.h"
56
57
58	/*********************************************************************************************************************************
59	* Internal Functions *
60	*********************************************************************************************************************************/
61	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
62	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
63	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
64	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
65
66
67	/*********************************************************************************************************************************
68	* Structures and Typedefs *
69	*********************************************************************************************************************************/
70	/**
71	* This is used to manage the status code of a RTMpOnAll in HM.
72	*/
73	typedef struct HMR0FIRSTRC
74	{
75	/** The status code. */
76	int32_t volatile rc;
77	/** The ID of the CPU reporting the first failure. */
78	RTCPUID volatile idCpu;
79	} HMR0FIRSTRC;
80	/** Pointer to a first return code structure. */
81	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
82
83	/**
84	* Ring-0 method table for AMD-V and VT-x specific operations.
85	*/
86	typedef struct HMR0VTABLE
87	{
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPUCC pVCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnAssertionCallback, (PVMCPUCC pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPUCC pVCpu));
92	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPUCC pVCpu));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94	bool fEnabledByHost, PCSUPHWVIRTMSRS pHwvirtMsrs));
95	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
96	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVMCC pVM));
97	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVMCC pVM));
98	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVMCC pVM));
99	} HMR0VTABLE;
100
101
102	/*********************************************************************************************************************************
103	* Global Variables *
104	*********************************************************************************************************************************/
105	/** The active ring-0 HM operations (copied from one of the table at init). */
106	static HMR0VTABLE g_HmR0Ops;
107	/** Indicates whether the host is suspending or not. We'll refuse a few
108	* actions when the host is being suspended to speed up the suspending and
109	* avoid trouble. */
110	static bool volatile g_fHmSuspended;
111	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
112	* enabled and disabled each time it's used to execute guest code. */
113	static bool g_fHmGlobalInit;
114	/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
115	uint32_t g_fHmHostKernelFeatures;
116	/** Maximum allowed ASID/VPID (inclusive).
117	* @todo r=bird: This is exclusive for VT-x according to source code comment.
118	* Couldn't immediately find any docs on AMD-V, but suspect it is
119	* exclusive there as well given how hmR0SvmFlushTaggedTlb() use it. */
120	uint32_t g_uHmMaxAsid;
121
122
123	/** Set if VT-x (VMX) is supported by the CPU. */
124	bool g_fHmVmxSupported = false;
125	/** VMX: Whether we're using the preemption timer or not. */
126	bool g_fHmVmxUsePreemptTimer;
127	/** VMX: The shift mask employed by the VMX-Preemption timer. */
128	uint8_t g_cHmVmxPreemptTimerShift;
129	/** VMX: Set if swapping EFER is supported. */
130	bool g_fHmVmxSupportsVmcsEfer = false;
131	/** VMX: Whether we're using SUPR0EnableVTx or not. */
132	static bool g_fHmVmxUsingSUPR0EnableVTx = false;
133	/** VMX: Set if we've called SUPR0EnableVTx(true) and should disable it during
134	* module termination. */
135	static bool g_fHmVmxCalledSUPR0EnableVTx = false;
136	/** VMX: Host CR4 value (set by ring-0 VMX init) */
137	uint64_t g_uHmVmxHostCr4;
138	/** VMX: Host EFER value (set by ring-0 VMX init) */
139	uint64_t g_uHmVmxHostMsrEfer;
140	/** VMX: Host SMM monitor control (used for logging/diagnostics) */
141	uint64_t g_uHmVmxHostSmmMonitorCtl;
142
143
144	/** Set if AMD-V is supported by the CPU. */
145	bool g_fHmSvmSupported = false;
146	/** SVM revision. */
147	uint32_t g_uHmSvmRev;
148	/** SVM feature bits from cpuid 0x8000000a */
149	uint32_t g_fHmSvmFeatures;
150
151
152	/** MSRs. */
153	SUPHWVIRTMSRS g_HmMsrs;
154
155	/** Last recorded error code during HM ring-0 init. */
156	static int32_t g_rcHmInit = VINF_SUCCESS;
157
158	/** Per CPU globals. */
159	static HMPHYSCPU g_aHmCpuInfo[RTCPUSET_MAX_CPUS];
160
161	/** Whether we've already initialized all CPUs.
162	* @remarks We could check the EnableAllCpusOnce state, but this is
163	* simpler and hopefully easier to understand. */
164	static bool g_fHmEnabled = false;
165	/** Serialize initialization in HMR0EnableAllCpus. */
166	static RTONCE g_HmEnableAllCpusOnce = RTONCE_INITIALIZER;
167
168
169	/** HM ring-0 operations for VT-x. */
170	static HMR0VTABLE const g_HmR0OpsVmx =
171	{
172	/* .pfnEnterSession = */ VMXR0Enter,
173	/* .pfnThreadCtxCallback = */ VMXR0ThreadCtxCallback,
174	/* .pfnAssertionCallback = */ VMXR0AssertionCallback,
175	/* .pfnExportHostState = */ VMXR0ExportHostState,
176	/* .pfnRunGuestCode = */ VMXR0RunGuestCode,
177	/* .pfnEnableCpu = */ VMXR0EnableCpu,
178	/* .pfnDisableCpu = */ VMXR0DisableCpu,
179	/* .pfnInitVM = */ VMXR0InitVM,
180	/* .pfnTermVM = */ VMXR0TermVM,
181	/* .pfnSetupVM = */ VMXR0SetupVM,
182	};
183
184	/** HM ring-0 operations for AMD-V. */
185	static HMR0VTABLE const g_HmR0OpsSvm =
186	{
187	/* .pfnEnterSession = */ SVMR0Enter,
188	/* .pfnThreadCtxCallback = */ SVMR0ThreadCtxCallback,
189	/* .pfnAssertionCallback = */ SVMR0AssertionCallback,
190	/* .pfnExportHostState = */ SVMR0ExportHostState,
191	/* .pfnRunGuestCode = */ SVMR0RunGuestCode,
192	/* .pfnEnableCpu = */ SVMR0EnableCpu,
193	/* .pfnDisableCpu = */ SVMR0DisableCpu,
194	/* .pfnInitVM = */ SVMR0InitVM,
195	/* .pfnTermVM = */ SVMR0TermVM,
196	/* .pfnSetupVM = */ SVMR0SetupVM,
197	};
198
199
200	/** @name Dummy callback handlers for when neither VT-x nor AMD-V is supported.
201	* @{ */
202
203	static DECLCALLBACK(int) hmR0DummyEnter(PVMCPUCC pVCpu)
204	{
205	RT_NOREF(pVCpu);
206	return VINF_SUCCESS;
207	}
208
209	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
210	{
211	RT_NOREF(enmEvent, pVCpu, fGlobalInit);
212	}
213
214	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
215	bool fEnabledBySystem, PCSUPHWVIRTMSRS pHwvirtMsrs)
216	{
217	RT_NOREF(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pHwvirtMsrs);
218	return VINF_SUCCESS;
219	}
220
221	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
222	{
223	RT_NOREF(pHostCpu, pvCpuPage, HCPhysCpuPage);
224	return VINF_SUCCESS;
225	}
226
227	static DECLCALLBACK(int) hmR0DummyInitVM(PVMCC pVM)
228	{
229	RT_NOREF(pVM);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(int) hmR0DummyTermVM(PVMCC pVM)
234	{
235	RT_NOREF(pVM);
236	return VINF_SUCCESS;
237	}
238
239	static DECLCALLBACK(int) hmR0DummySetupVM(PVMCC pVM)
240	{
241	RT_NOREF(pVM);
242	return VINF_SUCCESS;
243	}
244
245	static DECLCALLBACK(int) hmR0DummyAssertionCallback(PVMCPUCC pVCpu)
246	{
247	RT_NOREF(pVCpu);
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPUCC pVCpu)
252	{
253	RT_NOREF(pVCpu);
254	return VERR_NOT_SUPPORTED;
255	}
256
257	static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPUCC pVCpu)
258	{
259	RT_NOREF(pVCpu);
260	return VINF_SUCCESS;
261	}
262
263	/** Dummy ops. */
264	static HMR0VTABLE const g_HmR0OpsDummy =
265	{
266	/* .pfnEnterSession = */ hmR0DummyEnter,
267	/* .pfnThreadCtxCallback = */ hmR0DummyThreadCtxCallback,
268	/* .pfnAssertionCallback = */ hmR0DummyAssertionCallback,
269	/* .pfnExportHostState = */ hmR0DummyExportHostState,
270	/* .pfnRunGuestCode = */ hmR0DummyRunGuestCode,
271	/* .pfnEnableCpu = */ hmR0DummyEnableCpu,
272	/* .pfnDisableCpu = */ hmR0DummyDisableCpu,
273	/* .pfnInitVM = */ hmR0DummyInitVM,
274	/* .pfnTermVM = */ hmR0DummyTermVM,
275	/* .pfnSetupVM = */ hmR0DummySetupVM,
276	};
277
278	/** @} */
279
280
281	/**
282	* Initializes a first return code structure.
283	*
284	* @param pFirstRc The structure to init.
285	*/
286	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
287	{
288	pFirstRc->rc = VINF_SUCCESS;
289	pFirstRc->idCpu = NIL_RTCPUID;
290	}
291
292
293	/**
294	* Try set the status code (success ignored).
295	*
296	* @param pFirstRc The first return code structure.
297	* @param rc The status code.
298	*/
299	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
300	{
301	if ( RT_FAILURE(rc)
302	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
303	pFirstRc->idCpu = RTMpCpuId();
304	}
305
306
307	/**
308	* Get the status code of a first return code structure.
309	*
310	* @returns The status code; VINF_SUCCESS or error status, no informational or
311	* warning errors.
312	* @param pFirstRc The first return code structure.
313	*/
314	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
315	{
316	return pFirstRc->rc;
317	}
318
319
320	#ifdef VBOX_STRICT
321	# ifndef DEBUG_bird
322	/**
323	* Get the CPU ID on which the failure status code was reported.
324	*
325	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
326	* @param pFirstRc The first return code structure.
327	*/
328	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
329	{
330	return pFirstRc->idCpu;
331	}
332	# endif
333	#endif /* VBOX_STRICT */
334
335
336	/**
337	* Verify if VMX is really usable by entering and exiting VMX root mode.
338	*
339	* @returns VBox status code.
340	* @param uVmxBasicMsr The host's IA32_VMX_BASIC_MSR value.
341	*/
342	static int hmR0InitIntelVerifyVmxUsability(uint64_t uVmxBasicMsr)
343	{
344	/* Allocate a temporary VMXON region. */
345	RTR0MEMOBJ hScatchMemObj;
346	int rc = RTR0MemObjAllocCont(&hScatchMemObj, HOST_PAGE_SIZE, NIL_RTHCPHYS /* PhysHighest /, false / fExecutable */);
347	if (RT_FAILURE(rc))
348	{
349	LogRelFunc(("RTR0MemObjAllocCont(,HOST_PAGE_SIZE,false) -> %Rrc\n", rc));
350	return rc;
351	}
352	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
353	RTHCPHYS const HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
354	RT_BZERO(pvScatchPage, HOST_PAGE_SIZE);
355
356	/* Set revision dword at the beginning of the VMXON structure. */
357	(uint32_t )pvScatchPage = RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_VMCS_ID);
358
359	/* Make sure we don't get rescheduled to another CPU during this probe. */
360	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
361
362	/* Enable CR4.VMXE if it isn't already set. */
363	RTCCUINTREG const uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
364
365	/*
366	* The only way of checking if we're in VMX root mode is to try and enter it.
367	* There is no instruction or control bit that tells us if we're in VMX root mode.
368	* Therefore, try and enter and exit VMX root mode.
369	*/
370	rc = VMXEnable(HCPhysScratchPage);
371	if (RT_SUCCESS(rc))
372	VMXDisable();
373	else
374	{
375	/*
376	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
377	* it will crash the host when we enter raw mode, because:
378	*
379	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
380	* this bit), and
381	* (b) turning off paging causes a #GP (unavoidable when switching
382	* from long to 32 bits mode or 32 bits to PAE).
383	*
384	* They should fix their code, but until they do we simply refuse to run.
385	*/
386	rc = VERR_VMX_IN_VMX_ROOT_MODE;
387	}
388
389	/* Restore CR4.VMXE if it wasn't set prior to us setting it above. */
390	if (!(uOldCr4 & X86_CR4_VMXE))
391	SUPR0ChangeCR4(0 /* fOrMask */, ~(uint64_t)X86_CR4_VMXE);
392
393	/* Restore interrupts. */
394	ASMSetFlags(fEFlags);
395
396	RTR0MemObjFree(hScatchMemObj, false);
397
398	return rc;
399	}
400
401
402	/**
403	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
404	* on a CPU.
405	*
406	* @param idCpu The identifier for the CPU the function is called on.
407	* @param pvUser1 Pointer to the first RC structure.
408	* @param pvUser2 Ignored.
409	*/
410	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
411	{
412	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
413	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
414	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
415	NOREF(idCpu); NOREF(pvUser2);
416
417	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
418	hmR0FirstRcSetStatus(pFirstRc, rc);
419	}
420
421
422	/**
423	* Intel specific initialization code.
424	*
425	* @returns VBox status code (will only fail if out of memory).
426	*/
427	static int hmR0InitIntel(void)
428	{
429	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
430	g_HmMsrs.u.vmx.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
431
432	/*
433	* First try use native kernel API for controlling VT-x.
434	* (This is only supported by some Mac OS X kernels atm.)
435	*/
436	int rc;
437	g_rcHmInit = rc = SUPR0EnableVTx(true /* fEnable */);
438	g_fHmVmxUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
439	if (g_fHmVmxUsingSUPR0EnableVTx)
440	{
441	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
442	if (RT_SUCCESS(rc))
443	{
444	g_fHmVmxSupported = true;
445	rc = SUPR0EnableVTx(false /* fEnable */);
446	AssertLogRelRC(rc);
447	rc = VINF_SUCCESS;
448	}
449	}
450	else
451	{
452	HMR0FIRSTRC FirstRc;
453	hmR0FirstRcInit(&FirstRc);
454	g_rcHmInit = rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
455	if (RT_SUCCESS(rc))
456	g_rcHmInit = rc = hmR0FirstRcGetStatus(&FirstRc);
457	}
458
459	if (RT_SUCCESS(rc))
460	{
461	/* Read CR4 and EFER for logging/diagnostic purposes. */
462	g_uHmVmxHostCr4 = ASMGetCR4();
463	g_uHmVmxHostMsrEfer = ASMRdMsr(MSR_K6_EFER);
464
465	/* Get VMX MSRs (and feature control MSR) for determining VMX features we can ultimately use. */
466	SUPR0GetHwvirtMsrs(&g_HmMsrs, SUPVTCAPS_VT_X, false /* fForce */);
467
468	/*
469	* Nested KVM workaround: Intel SDM section 34.15.5 describes that
470	* MSR_IA32_SMM_MONITOR_CTL depends on bit 49 of MSR_IA32_VMX_BASIC while
471	* table 35-2 says that this MSR is available if either VMX or SMX is supported.
472	*/
473	uint64_t const uVmxBasicMsr = g_HmMsrs.u.vmx.u64Basic;
474	if (RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_DUAL_MON))
475	g_uHmVmxHostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
476
477	/* Initialize VPID - 16 bits ASID. */
478	g_uHmMaxAsid = 0x10000; /* exclusive */
479
480	/*
481	* If the host OS has not enabled VT-x for us, try enter VMX root mode
482	* to really verify if VT-x is usable.
483	*/
484	if (!g_fHmVmxUsingSUPR0EnableVTx)
485	{
486	rc = hmR0InitIntelVerifyVmxUsability(uVmxBasicMsr);
487	if (RT_SUCCESS(rc))
488	g_fHmVmxSupported = true;
489	else
490	{
491	g_rcHmInit = rc;
492	Assert(g_fHmVmxSupported == false);
493	}
494	}
495
496	if (g_fHmVmxSupported)
497	{
498	rc = VMXR0GlobalInit();
499	if (RT_SUCCESS(rc))
500	{
501	/*
502	* Install the VT-x methods.
503	*/
504	g_HmR0Ops = g_HmR0OpsVmx;
505
506	/*
507	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
508	* Timer Does Not Count Down at the Rate Specified" CPU erratum.
509	*/
510	if (g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER)
511	{
512	g_fHmVmxUsePreemptTimer = true;
513	g_cHmVmxPreemptTimerShift = RT_BF_GET(g_HmMsrs.u.vmx.u64Misc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
514	if (HMIsSubjectToVmxPreemptTimerErratum())
515	g_cHmVmxPreemptTimerShift = 0; /* This is about right most of the time here. */
516	}
517	else
518	g_fHmVmxUsePreemptTimer = false;
519
520	/*
521	* Check for EFER swapping support.
522	*/
523	g_fHmVmxSupportsVmcsEfer = (g_HmMsrs.u.vmx.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
524	&& (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
525	&& (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR);
526	}
527	else
528	{
529	g_rcHmInit = rc;
530	g_fHmVmxSupported = false;
531	}
532	}
533	}
534	#ifdef LOG_ENABLED
535	else
536	SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_rcHmInit);
537	#endif
538	return VINF_SUCCESS;
539	}
540
541
542	/**
543	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
544	* on a CPU.
545	*
546	* @param idCpu The identifier for the CPU the function is called on.
547	* @param pvUser1 Pointer to the first RC structure.
548	* @param pvUser2 Ignored.
549	*/
550	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
551	{
552	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
553	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
554	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
555	NOREF(idCpu); NOREF(pvUser2);
556
557	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
558	hmR0FirstRcSetStatus(pFirstRc, rc);
559	}
560
561
562	/**
563	* AMD-specific initialization code.
564	*
565	* @returns VBox status code (will only fail if out of memory).
566	*/
567	static int hmR0InitAmd(void)
568	{
569	/* Call the global AMD-V initialization routine (should only fail in out-of-memory situations). */
570	int rc = SVMR0GlobalInit();
571	if (RT_SUCCESS(rc))
572	{
573	/*
574	* Install the AMD-V methods.
575	*/
576	g_HmR0Ops = g_HmR0OpsSvm;
577
578	/* Query AMD features. */
579	uint32_t u32Dummy;
580	ASMCpuId(0x8000000a, &g_uHmSvmRev, &g_uHmMaxAsid, &u32Dummy, &g_fHmSvmFeatures);
581
582	/*
583	* We need to check if AMD-V has been properly initialized on all CPUs.
584	* Some BIOSes might do a poor job.
585	*/
586	HMR0FIRSTRC FirstRc;
587	hmR0FirstRcInit(&FirstRc);
588	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
589	AssertRC(rc);
590	if (RT_SUCCESS(rc))
591	rc = hmR0FirstRcGetStatus(&FirstRc);
592	#ifndef DEBUG_bird
593	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
594	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
595	#endif
596	if (RT_SUCCESS(rc))
597	{
598	SUPR0GetHwvirtMsrs(&g_HmMsrs, SUPVTCAPS_AMD_V, false /* fForce */);
599	g_fHmSvmSupported = true;
600	}
601	else
602	{
603	g_rcHmInit = rc;
604	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
605	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
606	}
607	}
608	else
609	g_rcHmInit = rc;
610	return rc;
611	}
612
613
614	/**
615	* Does global Ring-0 HM initialization (at module init).
616	*
617	* @returns VBox status code.
618	*/
619	VMMR0_INT_DECL(int) HMR0Init(void)
620	{
621	/*
622	* Initialize the globals.
623	*/
624	g_fHmEnabled = false;
625	for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
626	{
627	g_aHmCpuInfo[i].idCpu = NIL_RTCPUID;
628	g_aHmCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
629	g_aHmCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
630	g_aHmCpuInfo[i].pvMemObj = NULL;
631	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
632	g_aHmCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
633	g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
634	g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
635	#endif
636	}
637
638	/* Fill in all callbacks with placeholders. */
639	g_HmR0Ops = g_HmR0OpsDummy;
640
641	/* Default is global VT-x/AMD-V init. */
642	g_fHmGlobalInit = true;
643
644	g_fHmVmxSupported = false;
645	g_fHmSvmSupported = false;
646	g_uHmMaxAsid = 0;
647
648	/*
649	* Get host kernel features that HM might need to know in order
650	* to co-operate and function properly with the host OS (e.g. SMAP).
651	*/
652	g_fHmHostKernelFeatures = SUPR0GetKernelFeatures();
653
654	/*
655	* Make sure aCpuInfo is big enough for all the CPUs on this system.
656	*/
657	if (RTMpGetArraySize() > RT_ELEMENTS(g_aHmCpuInfo))
658	{
659	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aHmCpuInfo)));
660	return VERR_TOO_MANY_CPUS;
661	}
662
663	/*
664	* Check for VT-x or AMD-V support.
665	* Return failure only in out-of-memory situations.
666	*/
667	uint32_t fCaps = 0;
668	int rc = SUPR0GetVTSupport(&fCaps);
669	if (RT_SUCCESS(rc))
670	{
671	if (fCaps & SUPVTCAPS_VT_X)
672	rc = hmR0InitIntel();
673	else
674	{
675	Assert(fCaps & SUPVTCAPS_AMD_V);
676	rc = hmR0InitAmd();
677	}
678	if (RT_SUCCESS(rc))
679	{
680	/*
681	* Register notification callbacks that we can use to disable/enable CPUs
682	* when brought offline/online or suspending/resuming.
683	*/
684	if (!g_fHmVmxUsingSUPR0EnableVTx)
685	{
686	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
687	if (RT_SUCCESS(rc))
688	{
689	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
690	if (RT_FAILURE(rc))
691	RTMpNotificationDeregister(hmR0MpEventCallback, NULL);
692	}
693	if (RT_FAILURE(rc))
694	{
695	/* There shouldn't be any per-cpu allocations at this point,
696	so just have to call SVMR0GlobalTerm and VMXR0GlobalTerm. */
697	if (fCaps & SUPVTCAPS_VT_X)
698	VMXR0GlobalTerm();
699	else
700	SVMR0GlobalTerm();
701	g_HmR0Ops = g_HmR0OpsDummy;
702	g_rcHmInit = rc;
703	g_fHmSvmSupported = false;
704	g_fHmVmxSupported = false;
705	}
706	}
707	}
708	}
709	else
710	{
711	g_rcHmInit = rc;
712	rc = VINF_SUCCESS; /* We return success here because module init shall not fail if HM fails to initialize. */
713	}
714	return rc;
715	}
716
717
718	/**
719	* Does global Ring-0 HM termination (at module termination).
720	*
721	* @returns VBox status code (ignored).
722	*/
723	VMMR0_INT_DECL(int) HMR0Term(void)
724	{
725	int rc;
726	if ( g_fHmVmxSupported
727	&& g_fHmVmxUsingSUPR0EnableVTx)
728	{
729	/*
730	* Simple if the host OS manages VT-x.
731	*/
732	Assert(g_fHmGlobalInit);
733
734	if (g_fHmVmxCalledSUPR0EnableVTx)
735	{
736	rc = SUPR0EnableVTx(false /* fEnable */);
737	g_fHmVmxCalledSUPR0EnableVTx = false;
738	}
739	else
740	rc = VINF_SUCCESS;
741
742	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aHmCpuInfo); iCpu++)
743	{
744	g_aHmCpuInfo[iCpu].fConfigured = false;
745	Assert(g_aHmCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
746	}
747	}
748	else
749	{
750	Assert(!g_fHmVmxSupported \|\| !g_fHmVmxUsingSUPR0EnableVTx);
751
752	/* Doesn't really matter if this fails. */
753	RTMpNotificationDeregister(hmR0MpEventCallback, NULL);
754	RTPowerNotificationDeregister(hmR0PowerCallback, NULL);
755	rc = VINF_SUCCESS;
756
757	/*
758	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
759	*/
760	if (g_fHmGlobalInit)
761	{
762	HMR0FIRSTRC FirstRc;
763	hmR0FirstRcInit(&FirstRc);
764	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
765	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
766	if (RT_SUCCESS(rc))
767	rc = hmR0FirstRcGetStatus(&FirstRc);
768	}
769
770	/*
771	* Free the per-cpu pages used for VT-x and AMD-V.
772	*/
773	for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
774	{
775	if (g_aHmCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
776	{
777	RTR0MemObjFree(g_aHmCpuInfo[i].hMemObj, false);
778	g_aHmCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
779	g_aHmCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
780	g_aHmCpuInfo[i].pvMemObj = NULL;
781	}
782	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
783	if (g_aHmCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
784	{
785	RTR0MemObjFree(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, false);
786	g_aHmCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
787	g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
788	g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
789	}
790	#endif
791	}
792	}
793
794	/** @todo This needs cleaning up. There's no matching
795	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
796	* should move into their respective modules. */
797	/* Finally, call global VT-x/AMD-V termination. */
798	if (g_fHmVmxSupported)
799	VMXR0GlobalTerm();
800	else if (g_fHmSvmSupported)
801	SVMR0GlobalTerm();
802
803	return rc;
804	}
805
806
807	/**
808	* Enable VT-x or AMD-V on the current CPU
809	*
810	* @returns VBox status code.
811	* @param pVM The cross context VM structure. Can be NULL.
812	* @param idCpu The identifier for the CPU the function is called on.
813	*
814	* @remarks Maybe called with interrupts disabled!
815	*/
816	static int hmR0EnableCpu(PVMCC pVM, RTCPUID idCpu)
817	{
818	PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
819
820	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
821	Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
822	Assert(!pHostCpu->fConfigured);
823	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
824
825	pHostCpu->idCpu = idCpu;
826	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
827
828	int rc;
829	if ( g_fHmVmxSupported
830	&& g_fHmVmxUsingSUPR0EnableVTx)
831	rc = g_HmR0Ops.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmMsrs);
832	else
833	{
834	AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
835	rc = g_HmR0Ops.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmMsrs);
836	}
837	if (RT_SUCCESS(rc))
838	pHostCpu->fConfigured = true;
839	return rc;
840	}
841
842
843	/**
844	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
845	*
846	* @param idCpu The identifier for the CPU the function is called on.
847	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
848	* @param pvUser2 The 2nd user argument.
849	*/
850	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
851	{
852	PVMCC pVM = (PVMCC)pvUser1; /* can be NULL! */
853	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
854	AssertReturnVoid(g_fHmGlobalInit);
855	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
856	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
857	}
858
859
860	/**
861	* RTOnce callback employed by HMR0EnableAllCpus.
862	*
863	* @returns VBox status code.
864	* @param pvUser Pointer to the VM.
865	*/
866	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
867	{
868	PVMCC pVM = (PVMCC)pvUser;
869
870	/*
871	* Indicate that we've initialized.
872	*
873	* Note! There is a potential race between this function and the suspend
874	* notification. Kind of unlikely though, so ignored for now.
875	*/
876	AssertReturn(!g_fHmEnabled, VERR_HM_ALREADY_ENABLED_IPE);
877	ASMAtomicWriteBool(&g_fHmEnabled, true);
878
879	/*
880	* The global init variable is set by the first VM.
881	*/
882	g_fHmGlobalInit = pVM->hm.s.fGlobalInit;
883
884	#ifdef VBOX_STRICT
885	for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
886	{
887	Assert(g_aHmCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
888	Assert(g_aHmCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
889	Assert(g_aHmCpuInfo[i].pvMemObj == NULL);
890	Assert(!g_aHmCpuInfo[i].fConfigured);
891	Assert(!g_aHmCpuInfo[i].cTlbFlushes);
892	Assert(!g_aHmCpuInfo[i].uCurrentAsid);
893	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
894	Assert(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
895	Assert(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
896	Assert(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
897	# endif
898	}
899	#endif
900
901	int rc;
902	if ( g_fHmVmxSupported
903	&& g_fHmVmxUsingSUPR0EnableVTx)
904	{
905	/*
906	* Global VT-x initialization API (only darwin for now).
907	*/
908	rc = SUPR0EnableVTx(true /* fEnable */);
909	if (RT_SUCCESS(rc))
910	{
911	g_fHmVmxCalledSUPR0EnableVTx = true;
912	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
913	g_fHmGlobalInit = pVM->hm.s.fGlobalInit = true;
914	}
915	else
916	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
917	}
918	else
919	{
920	/*
921	* We're doing the job ourselves.
922	*/
923	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
924	for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
925	{
926	Assert(g_aHmCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
927	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
928	Assert(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
929	#endif
930	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
931	{
932	/** @todo NUMA */
933	rc = RTR0MemObjAllocCont(&g_aHmCpuInfo[i].hMemObj, HOST_PAGE_SIZE, NIL_RTHCPHYS /PhysHighest/, false /* executable R0 mapping */);
934	AssertLogRelRCReturn(rc, rc);
935
936	g_aHmCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_aHmCpuInfo[i].hMemObj, 0);
937	Assert(g_aHmCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
938	Assert(!(g_aHmCpuInfo[i].HCPhysMemObj & HOST_PAGE_OFFSET_MASK));
939
940	g_aHmCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_aHmCpuInfo[i].hMemObj);
941	AssertPtr(g_aHmCpuInfo[i].pvMemObj);
942	RT_BZERO(g_aHmCpuInfo[i].pvMemObj, HOST_PAGE_SIZE);
943
944	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
945	rc = RTR0MemObjAllocCont(&g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
946	NIL_RTHCPHYS /PhysHighest/, false /* executable R0 mapping */);
947	AssertLogRelRCReturn(rc, rc);
948
949	g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, 0);
950	Assert(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
951	Assert(!(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm & HOST_PAGE_OFFSET_MASK));
952
953	g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm);
954	AssertPtr(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm);
955	ASMMemFill32(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
956	#endif
957	}
958	}
959
960	rc = VINF_SUCCESS;
961	}
962
963	if ( RT_SUCCESS(rc)
964	&& g_fHmGlobalInit)
965	{
966	/*
967	* It's possible we end up here with VMX (and perhaps SVM) not supported, see @bugref{9918}.
968	* In that case, our HMR0 function table contains the dummy placeholder functions which pretend
969	* success. However, we must not pretend success any longer (like we did during HMR0Init called
970	* during VMMR0 module init) as the HM init error code (g_rcHmInit) should be propagated to
971	* ring-3 especially since we now have a VM instance.
972	*/
973	if ( !g_fHmVmxSupported
974	&& !g_fHmSvmSupported)
975	{
976	Assert(g_HmR0Ops.pfnEnableCpu == hmR0DummyEnableCpu);
977	Assert(RT_FAILURE(g_rcHmInit));
978	rc = g_rcHmInit;
979	}
980	else
981	{
982	/* First time, so initialize each cpu/core. */
983	HMR0FIRSTRC FirstRc;
984	hmR0FirstRcInit(&FirstRc);
985	Assert(g_HmR0Ops.pfnEnableCpu != hmR0DummyEnableCpu);
986	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
987	if (RT_SUCCESS(rc))
988	rc = hmR0FirstRcGetStatus(&FirstRc);
989	}
990	}
991
992	return rc;
993	}
994
995
996	/**
997	* Sets up HM on all cpus.
998	*
999	* @returns VBox status code.
1000	* @param pVM The cross context VM structure.
1001	*/
1002	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVMCC pVM)
1003	{
1004	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1005	if (ASMAtomicReadBool(&g_fHmSuspended))
1006	return VERR_HM_SUSPEND_PENDING;
1007
1008	return RTOnce(&g_HmEnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1009	}
1010
1011
1012	/**
1013	* Disable VT-x or AMD-V on the current CPU.
1014	*
1015	* @returns VBox status code.
1016	* @param idCpu The identifier for the CPU this function is called on.
1017	*
1018	* @remarks Must be called with preemption disabled.
1019	*/
1020	static int hmR0DisableCpu(RTCPUID idCpu)
1021	{
1022	PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
1023
1024	Assert(!g_fHmVmxSupported \|\| !g_fHmVmxUsingSUPR0EnableVTx);
1025	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1026	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1027	Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
1028	Assert(!pHostCpu->fConfigured \|\| pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
1029	AssertRelease(idCpu == RTMpCpuId());
1030
1031	if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
1032	return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1033	AssertPtr(pHostCpu->pvMemObj);
1034	Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
1035
1036	int rc;
1037	if (pHostCpu->fConfigured)
1038	{
1039	rc = g_HmR0Ops.pfnDisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
1040	AssertRCReturn(rc, rc);
1041
1042	pHostCpu->fConfigured = false;
1043	pHostCpu->idCpu = NIL_RTCPUID;
1044	}
1045	else
1046	rc = VINF_SUCCESS; /* nothing to do */
1047	return rc;
1048	}
1049
1050
1051	/**
1052	* Worker function passed to RTMpOnAll() that is to be called on the target
1053	* CPUs.
1054	*
1055	* @param idCpu The identifier for the CPU the function is called on.
1056	* @param pvUser1 The 1st user argument.
1057	* @param pvUser2 Opaque pointer to the FirstRc.
1058	*/
1059	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1060	{
1061	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1062	AssertReturnVoid(g_fHmGlobalInit);
1063	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1064	}
1065
1066
1067	/**
1068	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1069	* CPU.
1070	*
1071	* @param idCpu The identifier for the CPU the function is called on.
1072	* @param pvUser1 Null, not used.
1073	* @param pvUser2 Null, not used.
1074	*/
1075	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1076	{
1077	NOREF(pvUser1);
1078	NOREF(pvUser2);
1079	hmR0DisableCpu(idCpu);
1080	}
1081
1082
1083	/**
1084	* Callback function invoked when a cpu goes online or offline.
1085	*
1086	* @param enmEvent The Mp event.
1087	* @param idCpu The identifier for the CPU the function is called on.
1088	* @param pvData Opaque data (PVMCC pointer).
1089	*/
1090	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1091	{
1092	NOREF(pvData);
1093	Assert(!g_fHmVmxSupported \|\| !g_fHmVmxUsingSUPR0EnableVTx);
1094
1095	/*
1096	* We only care about uninitializing a CPU that is going offline. When a
1097	* CPU comes online, the initialization is done lazily in HMR0Enter().
1098	*/
1099	switch (enmEvent)
1100	{
1101	case RTMPEVENT_OFFLINE:
1102	{
1103	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1104	RTThreadPreemptDisable(&PreemptState);
1105	if (idCpu == RTMpCpuId())
1106	{
1107	int rc = hmR0DisableCpu(idCpu);
1108	AssertRC(rc);
1109	RTThreadPreemptRestore(&PreemptState);
1110	}
1111	else
1112	{
1113	RTThreadPreemptRestore(&PreemptState);
1114	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1115	}
1116	break;
1117	}
1118
1119	default:
1120	break;
1121	}
1122	}
1123
1124
1125	/**
1126	* Called whenever a system power state change occurs.
1127	*
1128	* @param enmEvent The Power event.
1129	* @param pvUser User argument.
1130	*/
1131	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1132	{
1133	NOREF(pvUser);
1134	Assert(!g_fHmVmxSupported \|\| !g_fHmVmxUsingSUPR0EnableVTx);
1135
1136	#ifdef LOG_ENABLED
1137	if (enmEvent == RTPOWEREVENT_SUSPEND)
1138	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1139	else
1140	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1141	#endif
1142
1143	if (enmEvent == RTPOWEREVENT_SUSPEND)
1144	ASMAtomicWriteBool(&g_fHmSuspended, true);
1145
1146	if (g_fHmEnabled)
1147	{
1148	int rc;
1149	HMR0FIRSTRC FirstRc;
1150	hmR0FirstRcInit(&FirstRc);
1151
1152	if (enmEvent == RTPOWEREVENT_SUSPEND)
1153	{
1154	if (g_fHmGlobalInit)
1155	{
1156	/* Turn off VT-x or AMD-V on all CPUs. */
1157	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1158	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1159	}
1160	/* else nothing to do here for the local init case */
1161	}
1162	else
1163	{
1164	/* Reinit the CPUs from scratch as the suspend state might have
1165	messed with the MSRs. (lousy BIOSes as usual) */
1166	if (g_fHmVmxSupported)
1167	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1168	else
1169	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1170	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1171	if (RT_SUCCESS(rc))
1172	rc = hmR0FirstRcGetStatus(&FirstRc);
1173	#ifdef LOG_ENABLED
1174	if (RT_FAILURE(rc))
1175	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1176	#endif
1177	if (g_fHmGlobalInit)
1178	{
1179	/* Turn VT-x or AMD-V back on on all CPUs. */
1180	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1181	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1182	}
1183	/* else nothing to do here for the local init case */
1184	}
1185	}
1186
1187	if (enmEvent == RTPOWEREVENT_RESUME)
1188	ASMAtomicWriteBool(&g_fHmSuspended, false);
1189	}
1190
1191
1192	/**
1193	* Does ring-0 per-VM HM initialization.
1194	*
1195	* This will call the CPU specific init. routine which may initialize and allocate
1196	* resources for virtual CPUs.
1197	*
1198	* @returns VBox status code.
1199	* @param pVM The cross context VM structure.
1200	*
1201	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1202	* vmR3InitRing3().
1203	*/
1204	VMMR0_INT_DECL(int) HMR0InitVM(PVMCC pVM)
1205	{
1206	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
1207	AssertCompile(sizeof(pVM->hmr0.s) <= sizeof(pVM->hmr0.padding));
1208	AssertCompile(sizeof(pVM->aCpus[0].hm.s) <= sizeof(pVM->aCpus[0].hm.padding));
1209	AssertCompile(sizeof(pVM->aCpus[0].hmr0.s) <= sizeof(pVM->aCpus[0].hmr0.padding));
1210	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1211
1212	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1213	if (ASMAtomicReadBool(&g_fHmSuspended))
1214	return VERR_HM_SUSPEND_PENDING;
1215
1216	/*
1217	* Copy globals to the VM structure.
1218	*/
1219	Assert(!(pVM->hm.s.vmx.fSupported && pVM->hm.s.svm.fSupported));
1220	if (pVM->hm.s.vmx.fSupported)
1221	{
1222	pVM->hmr0.s.vmx.fUsePreemptTimer = pVM->hm.s.vmx.fUsePreemptTimerCfg && g_fHmVmxUsePreemptTimer;
1223	pVM->hm.s.vmx.fUsePreemptTimerCfg = pVM->hmr0.s.vmx.fUsePreemptTimer;
1224	pVM->hm.s.vmx.cPreemptTimerShift = g_cHmVmxPreemptTimerShift;
1225	pVM->hm.s.ForR3.vmx.u64HostCr4 = g_uHmVmxHostCr4;
1226	pVM->hm.s.ForR3.vmx.u64HostMsrEfer = g_uHmVmxHostMsrEfer;
1227	pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl = g_uHmVmxHostSmmMonitorCtl;
1228	pVM->hm.s.ForR3.vmx.u64HostFeatCtrl = g_HmMsrs.u.vmx.u64FeatCtrl;
1229	HMGetVmxMsrsFromHwvirtMsrs(&g_HmMsrs, &pVM->hm.s.ForR3.vmx.Msrs);
1230	/* If you need to tweak host MSRs for testing VMX R0 code, do it here. */
1231
1232	/* Enable VPID if supported and configured. */
1233	if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
1234	pVM->hm.s.ForR3.vmx.fVpid = pVM->hmr0.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid; /* Can be overridden by CFGM in HMR3Init(). */
1235
1236	/* Use VMCS shadowing if supported. */
1237	pVM->hmr0.s.vmx.fUseVmcsShadowing = pVM->cpum.ro.GuestFeatures.fVmx
1238	&& (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1239	pVM->hm.s.ForR3.vmx.fUseVmcsShadowing = pVM->hmr0.s.vmx.fUseVmcsShadowing;
1240
1241	/* Use the VMCS controls for swapping the EFER MSR if supported. */
1242	pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer = g_fHmVmxSupportsVmcsEfer;
1243
1244	#if 0
1245	/* Enable APIC register virtualization and virtual-interrupt delivery if supported. */
1246	if ( (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
1247	&& (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
1248	pVM->hm.s.fVirtApicRegs = true;
1249
1250	/* Enable posted-interrupt processing if supported. */
1251	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1252	* here. */
1253	if ( (g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT)
1254	&& (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
1255	pVM->hm.s.fPostedIntrs = true;
1256	#endif
1257	}
1258	else if (pVM->hm.s.svm.fSupported)
1259	{
1260	pVM->hm.s.ForR3.svm.u32Rev = g_uHmSvmRev;
1261	pVM->hm.s.ForR3.svm.fFeatures = g_fHmSvmFeatures;
1262	pVM->hm.s.ForR3.svm.u64MsrHwcr = g_HmMsrs.u.svm.u64MsrHwcr;
1263	/* If you need to tweak host MSRs for testing SVM R0 code, do it here. */
1264	}
1265	pVM->hm.s.ForR3.rcInit = g_rcHmInit;
1266	pVM->hm.s.ForR3.uMaxAsid = g_uHmMaxAsid;
1267
1268	/*
1269	* Set default maximum inner loops in ring-0 before returning to ring-3.
1270	* Can be overriden using CFGM.
1271	*/
1272	uint32_t cMaxResumeLoops = pVM->hm.s.cMaxResumeLoopsCfg;
1273	if (!cMaxResumeLoops)
1274	{
1275	cMaxResumeLoops = 1024;
1276	if (RTThreadPreemptIsPendingTrusty())
1277	cMaxResumeLoops = 8192;
1278	}
1279	else if (cMaxResumeLoops > 16384)
1280	cMaxResumeLoops = 16384;
1281	else if (cMaxResumeLoops < 32)
1282	cMaxResumeLoops = 32;
1283	pVM->hm.s.cMaxResumeLoopsCfg = pVM->hmr0.s.cMaxResumeLoops = cMaxResumeLoops;
1284
1285	/*
1286	* Initialize some per-VCPU fields.
1287	*/
1288	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1289	{
1290	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
1291	pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID;
1292	pVCpu->hmr0.s.idLastCpu = NIL_RTCPUID;
1293
1294	/* We'll aways increment this the first time (host uses ASID 0). */
1295	AssertReturn(!pVCpu->hmr0.s.uCurrentAsid, VERR_HM_IPE_3);
1296	}
1297
1298	/*
1299	* Configure defences against spectre and other CPU bugs.
1300	*/
1301	uint32_t fWorldSwitcher = 0;
1302	uint32_t cLastStdLeaf = ASMCpuId_EAX(0);
1303	if (cLastStdLeaf >= 0x00000007 && RTX86IsValidStdRange(cLastStdLeaf))
1304	{
1305	uint32_t uEdx = 0;
1306	ASMCpuIdExSlow(0x00000007, 0, 0, 0, NULL, NULL, NULL, &uEdx);
1307
1308	if (uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB)
1309	{
1310	if (pVM->hm.s.fIbpbOnVmExit)
1311	fWorldSwitcher \|= HM_WSF_IBPB_EXIT;
1312	if (pVM->hm.s.fIbpbOnVmEntry)
1313	fWorldSwitcher \|= HM_WSF_IBPB_ENTRY;
1314	}
1315	if (uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
1316	{
1317	if (pVM->hm.s.fL1dFlushOnVmEntry)
1318	fWorldSwitcher \|= HM_WSF_L1D_ENTRY;
1319	else if (pVM->hm.s.fL1dFlushOnSched)
1320	fWorldSwitcher \|= HM_WSF_L1D_SCHED;
1321	}
1322	if (uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
1323	{
1324	if (pVM->hm.s.fMdsClearOnVmEntry)
1325	fWorldSwitcher \|= HM_WSF_MDS_ENTRY;
1326	else if (pVM->hm.s.fMdsClearOnSched)
1327	fWorldSwitcher \|= HM_WSF_MDS_SCHED;
1328	}
1329	}
1330	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1331	{
1332	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
1333	pVCpu->hmr0.s.fWorldSwitcher = fWorldSwitcher;
1334	}
1335	pVM->hm.s.ForR3.fWorldSwitcher = fWorldSwitcher;
1336
1337
1338	/*
1339	* Call the hardware specific initialization method.
1340	*/
1341	return g_HmR0Ops.pfnInitVM(pVM);
1342	}
1343
1344
1345	/**
1346	* Does ring-0 per VM HM termination.
1347	*
1348	* @returns VBox status code.
1349	* @param pVM The cross context VM structure.
1350	*/
1351	VMMR0_INT_DECL(int) HMR0TermVM(PVMCC pVM)
1352	{
1353	Log(("HMR0TermVM: %p\n", pVM));
1354	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1355
1356	/*
1357	* Call the hardware specific method.
1358	*
1359	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1360	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1361	*/
1362	return g_HmR0Ops.pfnTermVM(pVM);
1363	}
1364
1365
1366	/**
1367	* Sets up a VT-x or AMD-V session.
1368	*
1369	* This is mostly about setting up the hardware VM state.
1370	*
1371	* @returns VBox status code.
1372	* @param pVM The cross context VM structure.
1373	*/
1374	VMMR0_INT_DECL(int) HMR0SetupVM(PVMCC pVM)
1375	{
1376	Log(("HMR0SetupVM: %p\n", pVM));
1377	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1378
1379	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1380	AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
1381
1382	/* On first entry we'll sync everything. */
1383	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1384
1385	/*
1386	* Call the hardware specific setup VM method. This requires the CPU to be
1387	* enabled for AMD-V/VT-x and preemption to be prevented.
1388	*/
1389	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1390	RTThreadPreemptDisable(&PreemptState);
1391	RTCPUID const idCpu = RTMpCpuId();
1392
1393	/* Enable VT-x or AMD-V if local init is required. */
1394	int rc;
1395	if (!g_fHmGlobalInit)
1396	{
1397	Assert(!g_fHmVmxSupported \|\| !g_fHmVmxUsingSUPR0EnableVTx);
1398	rc = hmR0EnableCpu(pVM, idCpu);
1399	if (RT_FAILURE(rc))
1400	{
1401	RTThreadPreemptRestore(&PreemptState);
1402	return rc;
1403	}
1404	}
1405
1406	/* Setup VT-x or AMD-V. */
1407	rc = g_HmR0Ops.pfnSetupVM(pVM);
1408
1409	/* Disable VT-x or AMD-V if local init was done before. */
1410	if (!g_fHmGlobalInit)
1411	{
1412	Assert(!g_fHmVmxSupported \|\| !g_fHmVmxUsingSUPR0EnableVTx);
1413	int rc2 = hmR0DisableCpu(idCpu);
1414	AssertRC(rc2);
1415	}
1416
1417	RTThreadPreemptRestore(&PreemptState);
1418	return rc;
1419	}
1420
1421
1422	/**
1423	* Notification callback before an assertion longjump and guru mediation.
1424	*
1425	* @returns VBox status code.
1426	* @param pVCpu The cross context virtual CPU structure.
1427	* @param pvUser User argument, currently unused, NULL.
1428	*/
1429	static DECLCALLBACK(int) hmR0AssertionCallback(PVMCPUCC pVCpu, void *pvUser)
1430	{
1431	RT_NOREF(pvUser);
1432	Assert(pVCpu);
1433	Assert(g_HmR0Ops.pfnAssertionCallback);
1434	return g_HmR0Ops.pfnAssertionCallback(pVCpu);
1435	}
1436
1437
1438	/**
1439	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1440	* required for entering HM context.
1441	*
1442	* @returns VBox status code.
1443	* @param pVCpu The cross context virtual CPU structure.
1444	*
1445	* @remarks No-long-jump zone!!!
1446	*/
1447	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu)
1448	{
1449	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1450
1451	int rc = VINF_SUCCESS;
1452	RTCPUID const idCpu = RTMpCpuId();
1453	PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
1454	AssertPtr(pHostCpu);
1455
1456	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1457	if (!pHostCpu->fConfigured)
1458	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1459
1460	/* Register a callback to fire prior to performing a longjmp to ring-3 so HM can disable VT-x/AMD-V if needed. */
1461	VMMR0AssertionSetNotification(pVCpu, hmR0AssertionCallback, NULL /pvUser/);
1462
1463	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1464	if (g_fHmVmxSupported)
1465	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1466	else
1467	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1468
1469	Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
1470	pVCpu->hmr0.s.idEnteredCpu = idCpu;
1471	return rc;
1472	}
1473
1474
1475	/**
1476	* Enters the VT-x or AMD-V session.
1477	*
1478	* @returns VBox status code.
1479	* @param pVCpu The cross context virtual CPU structure.
1480	*
1481	* @remarks This is called with preemption disabled.
1482	*/
1483	VMMR0_INT_DECL(int) HMR0Enter(PVMCPUCC pVCpu)
1484	{
1485	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1486	AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
1487	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1488
1489	/* Load the bare minimum state required for entering HM. */
1490	int rc = hmR0EnterCpu(pVCpu);
1491	if (RT_SUCCESS(rc))
1492	{
1493	if (g_fHmVmxSupported)
1494	Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1495	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1496	else
1497	Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1498	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1499
1500	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1501	rc = g_HmR0Ops.pfnEnterSession(pVCpu);
1502	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID, rc);
1503
1504	/* Exports the host-state as we may be resuming code after a longjmp and quite
1505	possibly now be scheduled on a different CPU. */
1506	rc = g_HmR0Ops.pfnExportHostState(pVCpu);
1507	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID, rc);
1508	}
1509	return rc;
1510	}
1511
1512
1513	/**
1514	* Deinitializes the bare minimum state used for HM context and if necessary
1515	* disable HM on the CPU.
1516	*
1517	* @returns VBox status code.
1518	* @param pVCpu The cross context virtual CPU structure.
1519	*
1520	* @remarks No-long-jump zone!!!
1521	*/
1522	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPUCC pVCpu)
1523	{
1524	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1525	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1526
1527	RTCPUID const idCpu = RTMpCpuId();
1528	PCHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
1529
1530	if ( !g_fHmGlobalInit
1531	&& pHostCpu->fConfigured)
1532	{
1533	int rc = hmR0DisableCpu(idCpu);
1534	AssertRCReturn(rc, rc);
1535	Assert(!pHostCpu->fConfigured);
1536	Assert(pHostCpu->idCpu == NIL_RTCPUID);
1537
1538	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1539	pVCpu->hmr0.s.idLastCpu = NIL_RTCPUID;
1540	}
1541
1542	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1543	pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID;
1544
1545	/* De-register the longjmp-to-ring 3 callback now that we have reliquished hardware resources. */
1546	VMMR0AssertionRemoveNotification(pVCpu);
1547	return VINF_SUCCESS;
1548	}
1549
1550
1551	/**
1552	* Thread-context hook for HM.
1553	*
1554	* This is used together with RTThreadCtxHookCreate() on platforms which
1555	* supports it, and directly from VMMR0EmtPrepareForBlocking() and
1556	* VMMR0EmtResumeAfterBlocking() on platforms which don't.
1557	*
1558	* @param enmEvent The thread-context event.
1559	* @param pvUser Opaque pointer to the VMCPU.
1560	*/
1561	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1562	{
1563	PVMCPUCC pVCpu = (PVMCPUCC)pvUser;
1564	Assert(pVCpu);
1565	Assert(g_HmR0Ops.pfnThreadCtxCallback);
1566
1567	g_HmR0Ops.pfnThreadCtxCallback(enmEvent, pVCpu, g_fHmGlobalInit);
1568	}
1569
1570
1571	/**
1572	* Runs guest code in a hardware accelerated VM.
1573	*
1574	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1575	* called from setjmp assembly.)
1576	* @param pVM The cross context VM structure.
1577	* @param pVCpu The cross context virtual CPU structure.
1578	*
1579	* @remarks Can be called with preemption enabled if thread-context hooks are
1580	* used!!!
1581	*/
1582	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVMCC pVM, PVMCPUCC pVCpu)
1583	{
1584	RT_NOREF(pVM);
1585
1586	#ifdef VBOX_STRICT
1587	/* With thread-context hooks we would be running this code with preemption enabled. */
1588	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1589	{
1590	PCHMPHYSCPU pHostCpu = &g_aHmCpuInfo[RTMpCpuId()];
1591	Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1592	Assert(pHostCpu->fConfigured);
1593	AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
1594	}
1595	#endif
1596
1597	VBOXSTRICTRC rcStrict = g_HmR0Ops.pfnRunGuestCode(pVCpu);
1598	return VBOXSTRICTRC_VAL(rcStrict);
1599	}
1600
1601
1602	/**
1603	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1604	* the host CPU and that guest access to it must be intercepted.
1605	*
1606	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1607	*/
1608	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPUCC pVCpu)
1609	{
1610	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1611	}
1612
1613
1614	/**
1615	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1616	*
1617	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1618	*/
1619	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPUCC pVCpu)
1620	{
1621	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1622	}
1623
1624
1625	/**
1626	* Returns suspend status of the host.
1627	*
1628	* @returns Suspend pending or not.
1629	*/
1630	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1631	{
1632	return ASMAtomicReadBool(&g_fHmSuspended);
1633	}
1634
1635
1636	/**
1637	* Invalidates a guest page from the host TLB.
1638	*
1639	* @param pVCpu The cross context virtual CPU structure.
1640	* @param GCVirt Page to invalidate.
1641	*/
1642	VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1643	{
1644	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1645	if (pVM->hm.s.vmx.fSupported)
1646	return VMXR0InvalidatePage(pVCpu, GCVirt);
1647	return SVMR0InvalidatePage(pVCpu, GCVirt);
1648	}
1649
1650
1651	/**
1652	* Returns the cpu structure for the current cpu.
1653	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1654	*
1655	* @returns The cpu structure pointer.
1656	*/
1657	VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void)
1658	{
1659	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1660	RTCPUID const idCpu = RTMpCpuId();
1661	Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
1662	return &g_aHmCpuInfo[idCpu];
1663	}
1664
1665
1666	/**
1667	* Interface for importing state on demand (used by IEM).
1668	*
1669	* @returns VBox status code.
1670	* @param pVCpu The cross context CPU structure.
1671	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1672	*/
1673	VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1674	{
1675	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1676	return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1677	return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1678	}
1679
1680
1681	/**
1682	* Gets HM VM-exit auxiliary information.
1683	*
1684	* @returns VBox status code.
1685	* @param pVCpu The cross context CPU structure.
1686	* @param pHmExitAux Where to store the auxiliary info.
1687	* @param fWhat What to get, see HMVMX_READ_XXX. This is ignored/unused
1688	* on AMD-V.
1689	*
1690	* @remarks Currently this works only when executing a nested-guest using
1691	* hardware-assisted execution as it's where the auxiliary information is
1692	* required outside of HM. In the future we can make this available while
1693	* executing a regular (non-nested) guest if necessary.
1694	*/
1695	VMMR0_INT_DECL(int) HMR0GetExitAuxInfo(PVMCPUCC pVCpu, PHMEXITAUX pHmExitAux, uint32_t fWhat)
1696	{
1697	Assert(pHmExitAux);
1698	Assert(!(fWhat & ~HMVMX_READ_VALID_MASK));
1699	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1700	return VMXR0GetExitAuxInfo(pVCpu, &pHmExitAux->Vmx, fWhat);
1701	return SVMR0GetExitAuxInfo(pVCpu, &pHmExitAux->Svm);
1702	}
1703
1704
1705	#ifdef VBOX_STRICT
1706
1707	/**
1708	* Dumps a descriptor.
1709	*
1710	* @param pDesc Descriptor to dump.
1711	* @param Sel The selector.
1712	* @param pszSel The name of the selector.
1713	*/
1714	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszSel)
1715	{
1716	/*
1717	* Make variable description string.
1718	*/
1719	static struct
1720	{
1721	unsigned cch;
1722	const char *psz;
1723	} const s_aTypes[32] =
1724	{
1725	# define STRENTRY(str) { sizeof(str) - 1, str }
1726
1727	/* system */
1728	# if HC_ARCH_BITS == 64
1729	STRENTRY("Reserved0 "), /* 0x00 */
1730	STRENTRY("Reserved1 "), /* 0x01 */
1731	STRENTRY("LDT "), /* 0x02 */
1732	STRENTRY("Reserved3 "), /* 0x03 */
1733	STRENTRY("Reserved4 "), /* 0x04 */
1734	STRENTRY("Reserved5 "), /* 0x05 */
1735	STRENTRY("Reserved6 "), /* 0x06 */
1736	STRENTRY("Reserved7 "), /* 0x07 */
1737	STRENTRY("Reserved8 "), /* 0x08 */
1738	STRENTRY("TSS64Avail "), /* 0x09 */
1739	STRENTRY("ReservedA "), /* 0x0a */
1740	STRENTRY("TSS64Busy "), /* 0x0b */
1741	STRENTRY("Call64 "), /* 0x0c */
1742	STRENTRY("ReservedD "), /* 0x0d */
1743	STRENTRY("Int64 "), /* 0x0e */
1744	STRENTRY("Trap64 "), /* 0x0f */
1745	# else
1746	STRENTRY("Reserved0 "), /* 0x00 */
1747	STRENTRY("TSS16Avail "), /* 0x01 */
1748	STRENTRY("LDT "), /* 0x02 */
1749	STRENTRY("TSS16Busy "), /* 0x03 */
1750	STRENTRY("Call16 "), /* 0x04 */
1751	STRENTRY("Task "), /* 0x05 */
1752	STRENTRY("Int16 "), /* 0x06 */
1753	STRENTRY("Trap16 "), /* 0x07 */
1754	STRENTRY("Reserved8 "), /* 0x08 */
1755	STRENTRY("TSS32Avail "), /* 0x09 */
1756	STRENTRY("ReservedA "), /* 0x0a */
1757	STRENTRY("TSS32Busy "), /* 0x0b */
1758	STRENTRY("Call32 "), /* 0x0c */
1759	STRENTRY("ReservedD "), /* 0x0d */
1760	STRENTRY("Int32 "), /* 0x0e */
1761	STRENTRY("Trap32 "), /* 0x0f */
1762	# endif
1763	/* non system */
1764	STRENTRY("DataRO "), /* 0x10 */
1765	STRENTRY("DataRO Accessed "), /* 0x11 */
1766	STRENTRY("DataRW "), /* 0x12 */
1767	STRENTRY("DataRW Accessed "), /* 0x13 */
1768	STRENTRY("DataDownRO "), /* 0x14 */
1769	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1770	STRENTRY("DataDownRW "), /* 0x16 */
1771	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1772	STRENTRY("CodeEO "), /* 0x18 */
1773	STRENTRY("CodeEO Accessed "), /* 0x19 */
1774	STRENTRY("CodeER "), /* 0x1a */
1775	STRENTRY("CodeER Accessed "), /* 0x1b */
1776	STRENTRY("CodeConfEO "), /* 0x1c */
1777	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1778	STRENTRY("CodeConfER "), /* 0x1e */
1779	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1780	# undef SYSENTRY
1781	};
1782	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1783	char szMsg[128];
1784	char *psz = &szMsg[0];
1785	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1786	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1787	psz += s_aTypes[i].cch;
1788
1789	if (pDesc->Gen.u1Present)
1790	ADD_STR(psz, "Present ");
1791	else
1792	ADD_STR(psz, "Not-Present ");
1793	# if HC_ARCH_BITS == 64
1794	if (pDesc->Gen.u1Long)
1795	ADD_STR(psz, "64-bit ");
1796	else
1797	ADD_STR(psz, "Comp ");
1798	# else
1799	if (pDesc->Gen.u1Granularity)
1800	ADD_STR(psz, "Page ");
1801	if (pDesc->Gen.u1DefBig)
1802	ADD_STR(psz, "32-bit ");
1803	else
1804	ADD_STR(psz, "16-bit ");
1805	# endif
1806	# undef ADD_STR
1807	*psz = '\0';
1808
1809	/*
1810	* Limit and Base and format the output.
1811	*/
1812	#ifdef LOG_ENABLED
1813	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1814
1815	# if HC_ARCH_BITS == 64
1816	uint64_t const u64Base = X86DESC64_BASE(pDesc);
1817	Log((" %s { %#04x - %#RX64 %#RX64 - base=%#RX64 limit=%#08x dpl=%d } %s\n", pszSel,
1818	Sel, pDesc->au64[0], pDesc->au64[1], u64Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1819	# else
1820	uint32_t const u32Base = X86DESC_BASE(pDesc);
1821	Log((" %s { %#04x - %#08x %#08x - base=%#08x limit=%#08x dpl=%d } %s\n", pszSel,
1822	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1823	# endif
1824	#else
1825	NOREF(Sel); NOREF(pszSel);
1826	#endif
1827	}
1828
1829
1830	/**
1831	* Formats a full register dump.
1832	*
1833	* @param pVCpu The cross context virtual CPU structure.
1834	* @param fFlags The dumping flags (HM_DUMP_REG_FLAGS_XXX).
1835	*/
1836	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags)
1837	{
1838	/*
1839	* Format the flags.
1840	*/
1841	static struct
1842	{
1843	const char *pszSet;
1844	const char *pszClear;
1845	uint32_t fFlag;
1846	} const s_aFlags[] =
1847	{
1848	{ "vip", NULL, X86_EFL_VIP },
1849	{ "vif", NULL, X86_EFL_VIF },
1850	{ "ac", NULL, X86_EFL_AC },
1851	{ "vm", NULL, X86_EFL_VM },
1852	{ "rf", NULL, X86_EFL_RF },
1853	{ "nt", NULL, X86_EFL_NT },
1854	{ "ov", "nv", X86_EFL_OF },
1855	{ "dn", "up", X86_EFL_DF },
1856	{ "ei", "di", X86_EFL_IF },
1857	{ "tf", NULL, X86_EFL_TF },
1858	{ "nt", "pl", X86_EFL_SF },
1859	{ "nz", "zr", X86_EFL_ZF },
1860	{ "ac", "na", X86_EFL_AF },
1861	{ "po", "pe", X86_EFL_PF },
1862	{ "cy", "nc", X86_EFL_CF },
1863	};
1864	char szEFlags[80];
1865	char *psz = szEFlags;
1866	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1867	uint32_t fEFlags = pCtx->eflags.u;
1868	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1869	{
1870	const char *pszAdd = s_aFlags[i].fFlag & fEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1871	if (pszAdd)
1872	{
1873	strcpy(psz, pszAdd);
1874	psz += strlen(pszAdd);
1875	*psz++ = ' ';
1876	}
1877	}
1878	psz[-1] = '\0';
1879
1880	if (fFlags & HM_DUMP_REG_FLAGS_GPRS)
1881	{
1882	/*
1883	* Format the registers.
1884	*/
1885	if (CPUMIsGuestIn64BitCode(pVCpu))
1886	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1887	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1888	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1889	"r14=%016RX64 r15=%016RX64\n"
1890	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1891	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1892	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1893	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1894	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1895	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1896	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1897	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1898	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1899	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1900	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1901	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1902	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1903	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1904	,
1905	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1906	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1907	pCtx->r14, pCtx->r15,
1908	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(fEFlags), 31, szEFlags,
1909	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1910	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1911	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1912	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1913	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1914	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1915	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1916	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1917	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1918	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, fEFlags,
1919	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1920	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1921	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1922	else
1923	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1924	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1925	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1926	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1927	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1928	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1929	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1930	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1931	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1932	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1933	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1934	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1935	,
1936	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1937	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(fEFlags), 31, szEFlags,
1938	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1939	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1940	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1941	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1942	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1943	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1944	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, fEFlags,
1945	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1946	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1947	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1948	}
1949
1950	if (fFlags & HM_DUMP_REG_FLAGS_FPU)
1951	{
1952	PCX86FXSTATE pFpuCtx = &pCtx->XState.x87;
1953	Log(("FPU:\n"
1954	"FCW=%04x FSW=%04x FTW=%02x\n"
1955	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1956	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1957	,
1958	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1959	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1960	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1961	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1962	NOREF(pFpuCtx);
1963	}
1964
1965	if (fFlags & HM_DUMP_REG_FLAGS_MSRS)
1966	Log(("MSR:\n"
1967	"EFER =%016RX64\n"
1968	"PAT =%016RX64\n"
1969	"STAR =%016RX64\n"
1970	"CSTAR =%016RX64\n"
1971	"LSTAR =%016RX64\n"
1972	"SFMASK =%016RX64\n"
1973	"KERNELGSBASE =%016RX64\n",
1974	pCtx->msrEFER,
1975	pCtx->msrPAT,
1976	pCtx->msrSTAR,
1977	pCtx->msrCSTAR,
1978	pCtx->msrLSTAR,
1979	pCtx->msrSFMASK,
1980	pCtx->msrKERNELGSBASE));
1981	}
1982
1983	#endif /* VBOX_STRICT */
1984

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 101388

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