HMR0.cpp@ 43466

Last change on this file since 43466 was 43430, checked in by vboxsync, 12 years ago
VMM/VMMR0/HMR0: The VMXON region is not to be executed.
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1	/* $Id: HMR0.cpp 43430 2012-09-25 15:25:49Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HWVMXR0.h"
44	#include "HWSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBLCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94	bool fEnabledByHost));
95	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
96	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
99	/** @} */
100
101	/** Maximum ASID allowed. */
102	uint32_t uMaxASID;
103
104	/** VT-x data. */
105	struct
106	{
107	/** Set to by us to indicate VMX is supported by the CPU. */
108	bool fSupported;
109	/** Whether we're using SUPR0EnableVTx or not. */
110	bool fUsingSUPR0EnableVTx;
111	/** Whether we're using the preemption timer or not. */
112	bool fUsePreemptTimer;
113	/** The shift mask employed by the VMX-Preemption timer. */
114	uint8_t cPreemptTimerShift;
115
116	/** Host CR4 value (set by ring-0 VMX init) */
117	uint64_t hostCR4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t hostEFER;
121
122	/** VMX MSR values */
123	struct
124	{
125	uint64_t feature_ctrl;
126	uint64_t vmx_basic_info;
127	VMX_CAPABILITY vmx_pin_ctls;
128	VMX_CAPABILITY vmx_proc_ctls;
129	VMX_CAPABILITY vmx_proc_ctls2;
130	VMX_CAPABILITY vmx_exit;
131	VMX_CAPABILITY vmx_entry;
132	uint64_t vmx_misc;
133	uint64_t vmx_cr0_fixed0;
134	uint64_t vmx_cr0_fixed1;
135	uint64_t vmx_cr4_fixed0;
136	uint64_t vmx_cr4_fixed1;
137	uint64_t vmx_vmcs_enum;
138	uint64_t vmx_eptcaps;
139	} msr;
140	/* Last instruction error */
141	uint32_t ulLastInstrError;
142	} vmx;
143
144	/** AMD-V information. */
145	struct
146	{
147	/* HWCR msr (for diagnostics) */
148	uint64_t msrHWCR;
149
150	/** SVM revision. */
151	uint32_t u32Rev;
152
153	/** SVM feature bits from cpuid 0x8000000a */
154	uint32_t u32Features;
155
156	/** Set by us to indicate SVM is supported by the CPU. */
157	bool fSupported;
158	} svm;
159	/** Saved error from detection */
160	int32_t lLastError;
161
162	struct
163	{
164	uint32_t u32AMDFeatureECX;
165	uint32_t u32AMDFeatureEDX;
166	} cpuid;
167
168	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
169	* enabled and disabled each time it's used to execute guest code. */
170	bool fGlobalInit;
171	/** Indicates whether the host is suspending or not. We'll refuse a few
172	* actions when the host is being suspended to speed up the suspending and
173	* avoid trouble. */
174	volatile bool fSuspended;
175
176	/** Whether we've already initialized all CPUs.
177	* @remarks We could check the EnableAllCpusOnce state, but this is
178	* simpler and hopefully easier to understand. */
179	bool fEnabled;
180	/** Serialize initialization in HMR0EnableAllCpus. */
181	RTONCE EnableAllCpusOnce;
182	} g_HvmR0;
183
184
185
186	/**
187	* Initializes a first return code structure.
188	*
189	* @param pFirstRc The structure to init.
190	*/
191	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
192	{
193	pFirstRc->rc = VINF_SUCCESS;
194	pFirstRc->idCpu = NIL_RTCPUID;
195	}
196
197
198	/**
199	* Try set the status code (success ignored).
200	*
201	* @param pFirstRc The first return code structure.
202	* @param rc The status code.
203	*/
204	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
205	{
206	if ( RT_FAILURE(rc)
207	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
208	pFirstRc->idCpu = RTMpCpuId();
209	}
210
211
212	/**
213	* Get the status code of a first return code structure.
214	*
215	* @returns The status code; VINF_SUCCESS or error status, no informational or
216	* warning errors.
217	* @param pFirstRc The first return code structure.
218	*/
219	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
220	{
221	return pFirstRc->rc;
222	}
223
224
225	#ifdef VBOX_STRICT
226	/**
227	* Get the CPU ID on which the failure status code was reported.
228	*
229	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
230	* @param pFirstRc The first return code structure.
231	*/
232	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
233	{
234	return pFirstRc->idCpu;
235	}
236	#endif /* VBOX_STRICT */
237
238
239	/** @name Dummy callback handlers.
240	* @{ */
241
242	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
243	{
244	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
245	return VINF_SUCCESS;
246	}
247
248	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
249	{
250	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
251	return VINF_SUCCESS;
252	}
253
254	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
255	bool fEnabledBySystem)
256	{
257	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem);
258	return VINF_SUCCESS;
259	}
260
261	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
262	{
263	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
264	return VINF_SUCCESS;
265	}
266
267	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
268	{
269	NOREF(pVM);
270	return VINF_SUCCESS;
271	}
272
273	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
274	{
275	NOREF(pVM);
276	return VINF_SUCCESS;
277	}
278
279	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
280	{
281	NOREF(pVM);
282	return VINF_SUCCESS;
283	}
284
285	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
286	{
287	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
288	return VINF_SUCCESS;
289	}
290
291	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
292	{
293	NOREF(pVM); NOREF(pVCpu);
294	return VINF_SUCCESS;
295	}
296
297	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
298	{
299	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
300	return VINF_SUCCESS;
301	}
302
303	/** @} */
304
305
306	/**
307	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
308	* Down at the Rate Specified" erratum.
309	*
310	* Errata names and related steppings:
311	* - BA86 - D0.
312	* - AAX65 - C2.
313	* - AAU65 - C2, K0.
314	* - AAO95 - B1.
315	* - AAT59 - C2.
316	* - AAK139 - D0.
317	* - AAM126 - C0, C1, D0.
318	* - AAN92 - B1.
319	* - AAJ124 - C0, D0.
320	*
321	* - AAP86 - B1.
322	*
323	* Steppings: B1, C0, C1, C2, D0, K0.
324	*
325	* @returns true if subject to it, false if not.
326	*/
327	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
328	{
329	uint32_t u = ASMCpuId_EAX(1);
330	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
331	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
332	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
333	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
334	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
335	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
336	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
337	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
338	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
339	\|\| u == UINT32_C(0x000106A0) /?321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification /
340	\|\| u == UINT32_C(0x000106A1) /?321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification /
341	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
342	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
343	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
344	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
345	)
346	return true;
347	return false;
348	}
349
350
351	/**
352	* Intel specific initialization code.
353	*
354	* @returns VBox status code (will only fail if out of memory).
355	*/
356	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
357	{
358	/*
359	* Check that all the required VT-x features are present.
360	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
361	*/
362	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
363	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
364	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
365	)
366	{
367	/** @todo move this into a separate function. */
368	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
369
370	/*
371	* First try use native kernel API for controlling VT-x.
372	* (This is only supported by some Mac OS X kernels atm.)
373	*/
374	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
375	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
376	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
377	{
378	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
379	if (RT_SUCCESS(rc))
380	{
381	g_HvmR0.vmx.fSupported = true;
382	rc = SUPR0EnableVTx(false /* fEnable */);
383	AssertLogRelRC(rc);
384	}
385	}
386	else
387	{
388	/* We need to check if VT-x has been properly initialized on all
389	CPUs. Some BIOSes do a lousy job. */
390	HMR0FIRSTRC FirstRc;
391	hmR0FirstRcInit(&FirstRc);
392	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
393	if (RT_SUCCESS(g_HvmR0.lLastError))
394	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
395	}
396	if (RT_SUCCESS(g_HvmR0.lLastError))
397	{
398	/* Reread in case we've changed it. */
399	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
400
401	if ( (g_HvmR0.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
402	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
403	{
404	/*
405	* Read all relevant MSR.
406	*/
407	g_HvmR0.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
408	g_HvmR0.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
409	g_HvmR0.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
410	g_HvmR0.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
411	g_HvmR0.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
412	g_HvmR0.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
413	g_HvmR0.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
414	g_HvmR0.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
415	g_HvmR0.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
416	g_HvmR0.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
417	g_HvmR0.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
418	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
419	g_HvmR0.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
420	/* VPID 16 bits ASID. */
421	g_HvmR0.uMaxASID = 0x10000; /* exclusive */
422
423	if (g_HvmR0.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
424	{
425	g_HvmR0.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
426	if ( g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1
427	& (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
428	g_HvmR0.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
429	}
430
431	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
432	{
433	/*
434	* Enter root mode
435	*/
436	RTR0MEMOBJ hScatchMemObj;
437	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
438	if (RT_FAILURE(rc))
439	{
440	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
441	return rc;
442	}
443
444	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
445	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
446	ASMMemZeroPage(pvScatchPage);
447
448	/* Set revision dword at the beginning of the structure. */
449	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.vmx_basic_info);
450
451	/* Make sure we don't get rescheduled to another cpu during this probe. */
452	RTCCUINTREG fFlags = ASMIntDisableFlags();
453
454	/*
455	* Check CR4.VMXE
456	*/
457	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
458	if (!(g_HvmR0.vmx.hostCR4 & X86_CR4_VMXE))
459	{
460	/* In theory this bit could be cleared behind our back. Which would cause
461	#UD faults when we try to execute the VMX instructions... */
462	ASMSetCR4(g_HvmR0.vmx.hostCR4 \| X86_CR4_VMXE);
463	}
464
465	/* Enter VMX Root Mode */
466	rc = VMXEnable(HCPhysScratchPage);
467	if (RT_SUCCESS(rc))
468	{
469	g_HvmR0.vmx.fSupported = true;
470	VMXDisable();
471	}
472	else
473	{
474	/*
475	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
476	* it will crash the host when we enter raw mode, because:
477	*
478	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
479	* this bit), and
480	* (b) turning off paging causes a #GP (unavoidable when switching
481	* from long to 32 bits mode or 32 bits to PAE).
482	*
483	* They should fix their code, but until they do we simply refuse to run.
484	*/
485	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
486	}
487
488	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
489	if it wasn't so before (some software could incorrectly
490	think it's in VMX mode). */
491	ASMSetCR4(g_HvmR0.vmx.hostCR4);
492	ASMSetFlags(fFlags);
493
494	RTR0MemObjFree(hScatchMemObj, false);
495	}
496	}
497	else
498	{
499	AssertFailed(); /* can't hit this case anymore */
500	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
501	}
502
503	if (g_HvmR0.vmx.fSupported)
504	{
505	/*
506	* Install the VT-x methods.
507	*/
508	g_HvmR0.pfnEnterSession = VMXR0Enter;
509	g_HvmR0.pfnLeaveSession = VMXR0Leave;
510	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
511	g_HvmR0.pfnLoadGuestState = VMXR0LoadGuestState;
512	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
513	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
514	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
515	g_HvmR0.pfnInitVM = VMXR0InitVM;
516	g_HvmR0.pfnTermVM = VMXR0TermVM;
517	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
518
519	/*
520	* Check for the VMX-Preemption Timer and adjust for the * "VMX-Preemption
521	* Timer Does Not Count Down at the Rate Specified" erratum.
522	*/
523	if ( g_HvmR0.vmx.msr.vmx_pin_ctls.n.allowed1
524	& VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
525	{
526	g_HvmR0.vmx.fUsePreemptTimer = true;
527	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.vmx_misc);
528	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
529	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
530	}
531	}
532	}
533	#ifdef LOG_ENABLED
534	else
535	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
536	#endif
537	}
538	else
539	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
540	return VINF_SUCCESS;
541	}
542
543
544	/**
545	* AMD-specific initialization code.
546	*/
547	static void hmR0InitAmd(uint32_t u32FeaturesEDX)
548	{
549	/*
550	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
551	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
552	*/
553	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
554	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
555	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
556	)
557	{
558	g_HvmR0.pfnEnterSession = SVMR0Enter;
559	g_HvmR0.pfnLeaveSession = SVMR0Leave;
560	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
561	g_HvmR0.pfnLoadGuestState = SVMR0LoadGuestState;
562	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
563	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
564	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
565	g_HvmR0.pfnInitVM = SVMR0InitVM;
566	g_HvmR0.pfnTermVM = SVMR0TermVM;
567	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
568
569	/* Query AMD features. */
570	uint32_t u32Dummy;
571	ASMCpuId(0x8000000A, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxASID,
572	&u32Dummy, &g_HvmR0.svm.u32Features);
573
574	/*
575	* We need to check if AMD-V has been properly initialized on all CPUs.
576	* Some BIOSes might do a poor job.
577	*/
578	HMR0FIRSTRC FirstRc;
579	hmR0FirstRcInit(&FirstRc);
580	int rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
581	AssertRC(rc);
582	if (RT_SUCCESS(rc))
583	rc = hmR0FirstRcGetStatus(&FirstRc);
584	#ifndef DEBUG_bird
585	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
586	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
587	#endif
588	if (RT_SUCCESS(rc))
589	{
590	/* Read the HWCR msr for diagnostics. */
591	g_HvmR0.svm.msrHWCR = ASMRdMsr(MSR_K8_HWCR);
592	g_HvmR0.svm.fSupported = true;
593	}
594	else
595	g_HvmR0.lLastError = rc;
596	}
597	else
598	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
599	}
600
601
602	/**
603	* Does global Ring-0 HM initialization (at module init).
604	*
605	* @returns VBox status code.
606	*/
607	VMMR0DECL(int) HMR0Init(void)
608	{
609	/*
610	* Initialize the globals.
611	*/
612	g_HvmR0.fEnabled = false;
613	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
614	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
615	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
616	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
617
618	/* Fill in all callbacks with placeholders. */
619	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
620	g_HvmR0.pfnLeaveSession = hmR0DummyLeave;
621	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
622	g_HvmR0.pfnLoadGuestState = hmR0DummyLoadGuestState;
623	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
624	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
625	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
626	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
627	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
628	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
629
630	/* Default is global VT-x/AMD-V init. */
631	g_HvmR0.fGlobalInit = true;
632
633	/*
634	* Make sure aCpuInfo is big enough for all the CPUs on this system.
635	*/
636	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
637	{
638	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
639	return VERR_TOO_MANY_CPUS;
640	}
641
642	/*
643	* Check for VT-x and AMD-V capabilities.
644	*/
645	int rc;
646	if (ASMHasCpuId())
647	{
648	uint32_t u32FeaturesECX, u32FeaturesEDX;
649	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
650	uint32_t u32Dummy;
651
652	/* Standard features. */
653	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
654	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
655
656	/* Query AMD features. */
657	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
658	&g_HvmR0.cpuid.u32AMDFeatureECX,
659	&g_HvmR0.cpuid.u32AMDFeatureEDX);
660
661	/* Go to CPU specific initialization code. */
662	if ( ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
663	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
664	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX)
665	\|\| ( u32VendorEBX == X86_CPUID_VENDOR_VIA_EBX
666	&& u32VendorECX == X86_CPUID_VENDOR_VIA_ECX
667	&& u32VendorEDX == X86_CPUID_VENDOR_VIA_EDX))
668	{
669	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
670	if (RT_FAILURE(rc))
671	return rc;
672	}
673	else if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
674	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
675	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX)
676	hmR0InitAmd(u32FeaturesEDX);
677	else
678	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
679	}
680	else
681	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
682
683	/*
684	* Register notification callbacks that we can use to disable/enable CPUs
685	* when brought offline/online or suspending/resuming.
686	*/
687	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
688	{
689	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
690	AssertRC(rc);
691
692	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
693	AssertRC(rc);
694	}
695
696	/* We return success here because module init shall not fail if HM
697	fails to initialize. */
698	return VINF_SUCCESS;
699	}
700
701
702	/**
703	* Does global Ring-0 HM termination (at module termination).
704	*
705	* @returns VBox status code.
706	*/
707	VMMR0DECL(int) HMR0Term(void)
708	{
709	int rc;
710	if ( g_HvmR0.vmx.fSupported
711	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
712	{
713	/*
714	* Simple if the host OS manages VT-x.
715	*/
716	Assert(g_HvmR0.fGlobalInit);
717	rc = SUPR0EnableVTx(false /* fEnable */);
718
719	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
720	{
721	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
722	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
723	}
724	}
725	else
726	{
727	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
728	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
729	{
730	/* Doesn't really matter if this fails. */
731	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
732	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
733	}
734	else
735	rc = VINF_SUCCESS;
736
737	/*
738	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
739	*/
740	if (g_HvmR0.fGlobalInit)
741	{
742	HMR0FIRSTRC FirstRc;
743	hmR0FirstRcInit(&FirstRc);
744	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
745	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
746	if (RT_SUCCESS(rc))
747	{
748	rc = hmR0FirstRcGetStatus(&FirstRc);
749	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
750	}
751	}
752
753	/*
754	* Free the per-cpu pages used for VT-x and AMD-V.
755	*/
756	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
757	{
758	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
759	{
760	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
761	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
762	}
763	}
764	}
765	return rc;
766	}
767
768
769	/**
770	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
771	* VT-x on a CPU.
772	*
773	* @param idCpu The identifier for the CPU the function is called on.
774	* @param pvUser1 Pointer to the first RC structure.
775	* @param pvUser2 Ignored.
776	*/
777	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
778	{
779	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
780	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
781	NOREF(pvUser2);
782
783	/*
784	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
785	* Once the lock bit is set, this MSR can no longer be modified.
786	*/
787	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
788	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
789	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
790	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
791	)
792	{
793	/* MSR is not yet locked; we can change it ourselves here. */
794	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
795	g_HvmR0.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
796	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
797	}
798
799	int rc;
800	if ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
801	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
802	rc = VINF_SUCCESS;
803	else
804	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
805
806	hmR0FirstRcSetStatus(pFirstRc, rc);
807	}
808
809
810	/**
811	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
812	* VT-x / AMD-V on a CPU.
813	*
814	* @param idCpu The identifier for the CPU the function is called on.
815	* @param pvUser1 Pointer to the first RC structure.
816	* @param pvUser2 Ignored.
817	*/
818	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
819	{
820	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
821	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
822	NOREF(pvUser2);
823
824	/* Check if SVM is disabled. */
825	int rc;
826	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
827	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
828	{
829	/* Turn on SVM in the EFER MSR. */
830	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
831	if (fEfer & MSR_K6_EFER_SVME)
832	rc = VERR_SVM_IN_USE;
833	else
834	{
835	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
836
837	/* Paranoia. */
838	fEfer = ASMRdMsr(MSR_K6_EFER);
839	if (fEfer & MSR_K6_EFER_SVME)
840	{
841	/* Restore previous value. */
842	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
843	rc = VINF_SUCCESS;
844	}
845	else
846	rc = VERR_SVM_ILLEGAL_EFER_MSR;
847	}
848	}
849	else
850	rc = VERR_SVM_DISABLED;
851
852	hmR0FirstRcSetStatus(pFirstRc, rc);
853	}
854
855
856	/**
857	* Disable VT-x or AMD-V on the current CPU
858	*
859	* @returns VBox status code.
860	* @param pVM Pointer to the VM (can be 0).
861	* @param idCpu The identifier for the CPU the function is called on.
862	*/
863	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
864	{
865	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
866
867	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
868	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
869	Assert(!pCpu->fConfigured);
870	Assert(!g_HvmR0.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
871
872	pCpu->idCpu = idCpu;
873	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
874	/* Do NOT reset cTLBFlushes here, see @bugref{6255}. */
875
876	int rc;
877	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
878	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL, NIL_RTHCPHYS, true);
879	else
880	{
881	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
882	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
883	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
884	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
885	}
886	AssertRC(rc);
887	if (RT_SUCCESS(rc))
888	pCpu->fConfigured = true;
889
890	return rc;
891	}
892
893
894	/**
895	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
896	* is to be called on the target cpus.
897	*
898	* @param idCpu The identifier for the CPU the function is called on.
899	* @param pvUser1 The 1st user argument.
900	* @param pvUser2 The 2nd user argument.
901	*/
902	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
903	{
904	PVM pVM = (PVM)pvUser1; /* can be NULL! */
905	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
906	AssertReturnVoid(g_HvmR0.fGlobalInit);
907	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
908	}
909
910
911	/**
912	* RTOnce callback employed by HMR0EnableAllCpus.
913	*
914	* @returns VBox status code.
915	* @param pvUser Pointer to the VM.
916	* @param pvUserIgnore NULL, ignored.
917	*/
918	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void pvUser, void pvUserIgnore)
919	{
920	PVM pVM = (PVM)pvUser;
921	NOREF(pvUserIgnore);
922
923	/*
924	* Indicate that we've initialized.
925	*
926	* Note! There is a potential race between this function and the suspend
927	* notification. Kind of unlikely though, so ignored for now.
928	*/
929	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
930	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
931
932	/*
933	* The global init variable is set by the first VM.
934	*/
935	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
936
937	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
938	{
939	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
940	g_HvmR0.aCpuInfo[i].fConfigured = false;
941	g_HvmR0.aCpuInfo[i].cTLBFlushes = 0;
942	}
943
944	int rc;
945	if ( g_HvmR0.vmx.fSupported
946	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
947	{
948	/*
949	* Global VT-x initialization API (only darwin for now).
950	*/
951	rc = SUPR0EnableVTx(true /* fEnable */);
952	if (RT_SUCCESS(rc))
953	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
954	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
955	else
956	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
957	}
958	else
959	{
960	/*
961	* We're doing the job ourselves.
962	*/
963	/* Allocate one page per cpu for the global vt-x and amd-v pages */
964	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
965	{
966	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
967
968	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
969	{
970	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
971	AssertLogRelRCReturn(rc, rc);
972
973	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
974	ASMMemZeroPage(pvR0);
975	}
976	}
977
978	rc = VINF_SUCCESS;
979	}
980
981	if (RT_SUCCESS(rc) && g_HvmR0.fGlobalInit)
982	{
983	/* First time, so initialize each cpu/core. */
984	HMR0FIRSTRC FirstRc;
985	hmR0FirstRcInit(&FirstRc);
986	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
987	if (RT_SUCCESS(rc))
988	rc = hmR0FirstRcGetStatus(&FirstRc);
989	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
990	}
991
992	return rc;
993	}
994
995
996	/**
997	* Sets up HM on all cpus.
998	*
999	* @returns VBox status code.
1000	* @param pVM Pointer to the VM.
1001	*/
1002	VMMR0DECL(int) HMR0EnableAllCpus(PVM pVM)
1003	{
1004	/* Make sure we don't touch hm after we've disabled hm in
1005	preparation of a suspend. */
1006	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1007	return VERR_HM_SUSPEND_PENDING;
1008
1009	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM, NULL);
1010	}
1011
1012
1013	/**
1014	* Disable VT-x or AMD-V on the current CPU.
1015	*
1016	* @returns VBox status code.
1017	* @param idCpu The identifier for the CPU the function is called on.
1018	*/
1019	static int hmR0DisableCpu(RTCPUID idCpu)
1020	{
1021	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1022
1023	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1024	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1025	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1026	Assert(!g_HvmR0.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
1027	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1028
1029	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1030	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1031
1032	int rc;
1033	if (pCpu->fConfigured)
1034	{
1035	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1036	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1037	if (idCpu == RTMpCpuId())
1038	{
1039	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1040	AssertRC(rc);
1041	}
1042	else
1043	{
1044	pCpu->fIgnoreAMDVInUseError = true;
1045	rc = VINF_SUCCESS;
1046	}
1047
1048	pCpu->fConfigured = false;
1049	}
1050	else
1051	rc = VINF_SUCCESS; /* nothing to do */
1052
1053	pCpu->uCurrentASID = 0;
1054	return rc;
1055	}
1056
1057
1058	/**
1059	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1060	* is to be called on the target cpus.
1061	*
1062	* @param idCpu The identifier for the CPU the function is called on.
1063	* @param pvUser1 The 1st user argument.
1064	* @param pvUser2 The 2nd user argument.
1065	*/
1066	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1067	{
1068	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1069	AssertReturnVoid(g_HvmR0.fGlobalInit);
1070	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1071	}
1072
1073
1074	/**
1075	* Callback function invoked when a cpu goes online or offline.
1076	*
1077	* @param enmEvent The Mp event.
1078	* @param idCpu The identifier for the CPU the function is called on.
1079	* @param pvData Opaque data (PVM pointer).
1080	*/
1081	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1082	{
1083	NOREF(pvData);
1084
1085	/*
1086	* We only care about uninitializing a CPU that is going offline. When a
1087	* CPU comes online, the initialization is done lazily in HMR0Enter().
1088	*/
1089	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1090	switch (enmEvent)
1091	{
1092	case RTMPEVENT_OFFLINE:
1093	{
1094	int rc = hmR0DisableCpu(idCpu);
1095	AssertRC(rc);
1096	break;
1097	}
1098
1099	default:
1100	break;
1101	}
1102	}
1103
1104
1105	/**
1106	* Called whenever a system power state change occurs.
1107	*
1108	* @param enmEvent The Power event.
1109	* @param pvUser User argument.
1110	*/
1111	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1112	{
1113	NOREF(pvUser);
1114	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1115
1116	#ifdef LOG_ENABLED
1117	if (enmEvent == RTPOWEREVENT_SUSPEND)
1118	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1119	else
1120	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1121	#endif
1122
1123	if (enmEvent == RTPOWEREVENT_SUSPEND)
1124	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1125
1126	if (g_HvmR0.fEnabled)
1127	{
1128	int rc;
1129	HMR0FIRSTRC FirstRc;
1130	hmR0FirstRcInit(&FirstRc);
1131
1132	if (enmEvent == RTPOWEREVENT_SUSPEND)
1133	{
1134	if (g_HvmR0.fGlobalInit)
1135	{
1136	/* Turn off VT-x or AMD-V on all CPUs. */
1137	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
1138	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1139	}
1140	/* else nothing to do here for the local init case */
1141	}
1142	else
1143	{
1144	/* Reinit the CPUs from scratch as the suspend state might have
1145	messed with the MSRs. (lousy BIOSes as usual) */
1146	if (g_HvmR0.vmx.fSupported)
1147	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1148	else
1149	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1150	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1151	if (RT_SUCCESS(rc))
1152	rc = hmR0FirstRcGetStatus(&FirstRc);
1153	#ifdef LOG_ENABLED
1154	if (RT_FAILURE(rc))
1155	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1156	#endif
1157	if (g_HvmR0.fGlobalInit)
1158	{
1159	/* Turn VT-x or AMD-V back on on all CPUs. */
1160	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
1161	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1162	}
1163	/* else nothing to do here for the local init case */
1164	}
1165	}
1166
1167	if (enmEvent == RTPOWEREVENT_RESUME)
1168	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1169	}
1170
1171
1172	/**
1173	* Does Ring-0 per VM HM initialization.
1174	*
1175	* This will copy HM global into the VM structure and call the CPU specific
1176	* init routine which will allocate resources for each virtual CPU and such.
1177	*
1178	* @returns VBox status code.
1179	* @param pVM Pointer to the VM.
1180	*/
1181	VMMR0DECL(int) HMR0InitVM(PVM pVM)
1182	{
1183	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1184
1185	#ifdef LOG_ENABLED
1186	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1187	#endif
1188
1189	/* Make sure we don't touch hm after we've disabled hm in preparation of a suspend. */
1190	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1191	return VERR_HM_SUSPEND_PENDING;
1192
1193	/*
1194	* Copy globals to the VM structure.
1195	*/
1196	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1197	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1198
1199	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1200	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1201	pVM->hm.s.vmx.msr.feature_ctrl = g_HvmR0.vmx.msr.feature_ctrl;
1202	pVM->hm.s.vmx.hostCR4 = g_HvmR0.vmx.hostCR4;
1203	pVM->hm.s.vmx.hostEFER = g_HvmR0.vmx.hostEFER;
1204	pVM->hm.s.vmx.msr.vmx_basic_info = g_HvmR0.vmx.msr.vmx_basic_info;
1205	pVM->hm.s.vmx.msr.vmx_pin_ctls = g_HvmR0.vmx.msr.vmx_pin_ctls;
1206	pVM->hm.s.vmx.msr.vmx_proc_ctls = g_HvmR0.vmx.msr.vmx_proc_ctls;
1207	pVM->hm.s.vmx.msr.vmx_proc_ctls2 = g_HvmR0.vmx.msr.vmx_proc_ctls2;
1208	pVM->hm.s.vmx.msr.vmx_exit = g_HvmR0.vmx.msr.vmx_exit;
1209	pVM->hm.s.vmx.msr.vmx_entry = g_HvmR0.vmx.msr.vmx_entry;
1210	pVM->hm.s.vmx.msr.vmx_misc = g_HvmR0.vmx.msr.vmx_misc;
1211	pVM->hm.s.vmx.msr.vmx_cr0_fixed0 = g_HvmR0.vmx.msr.vmx_cr0_fixed0;
1212	pVM->hm.s.vmx.msr.vmx_cr0_fixed1 = g_HvmR0.vmx.msr.vmx_cr0_fixed1;
1213	pVM->hm.s.vmx.msr.vmx_cr4_fixed0 = g_HvmR0.vmx.msr.vmx_cr4_fixed0;
1214	pVM->hm.s.vmx.msr.vmx_cr4_fixed1 = g_HvmR0.vmx.msr.vmx_cr4_fixed1;
1215	pVM->hm.s.vmx.msr.vmx_vmcs_enum = g_HvmR0.vmx.msr.vmx_vmcs_enum;
1216	pVM->hm.s.vmx.msr.vmx_eptcaps = g_HvmR0.vmx.msr.vmx_eptcaps;
1217	pVM->hm.s.svm.msrHWCR = g_HvmR0.svm.msrHWCR;
1218	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1219	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1220	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1221	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1222	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1223
1224	pVM->hm.s.uMaxASID = g_HvmR0.uMaxASID;
1225
1226
1227	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1228	{
1229	pVM->hm.s.cMaxResumeLoops = 1024;
1230	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1231	if (RTThreadPreemptIsPendingTrusty())
1232	pVM->hm.s.cMaxResumeLoops = 8192;
1233	#endif
1234	}
1235
1236	/*
1237	* Initialize some per CPU fields.
1238	*/
1239	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1240	{
1241	PVMCPU pVCpu = &pVM->aCpus[i];
1242
1243	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1244
1245	/* Invalidate the last cpu we were running on. */
1246	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1247
1248	/* We'll aways increment this the first time (host uses ASID 0) */
1249	pVCpu->hm.s.uCurrentASID = 0;
1250	}
1251
1252	/*
1253	* Call the hardware specific initialization method.
1254	*
1255	* Note! The fInUse handling here isn't correct as we can we can be
1256	* rescheduled to a different cpu, but the fInUse case is mostly for
1257	* debugging... Disabling preemption isn't an option when allocating
1258	* memory, so we'll let it slip for now.
1259	*/
1260	RTCCUINTREG fFlags = ASMIntDisableFlags();
1261	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
1262	ASMAtomicWriteBool(&pCpu->fInUse, true);
1263	ASMSetFlags(fFlags);
1264
1265	int rc = g_HvmR0.pfnInitVM(pVM);
1266
1267	ASMAtomicWriteBool(&pCpu->fInUse, false);
1268	return rc;
1269	}
1270
1271
1272	/**
1273	* Does Ring-0 per VM HM termination.
1274	*
1275	* @returns VBox status code.
1276	* @param pVM Pointer to the VM.
1277	*/
1278	VMMR0DECL(int) HMR0TermVM(PVM pVM)
1279	{
1280	Log(("HMR0TermVM: %p\n", pVM));
1281	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1282
1283	/* Make sure we don't touch hm after we've disabled hm in preparation
1284	of a suspend. */
1285	/** @todo r=bird: This cannot be right, the termination functions are
1286	* just freeing memory and resetting pVM/pVCpu members...
1287	* ==> memory leak. */
1288	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1289
1290	/*
1291	* Call the hardware specific method.
1292	*
1293	* Note! Not correct as we can be rescheduled to a different cpu, but the
1294	* fInUse case is mostly for debugging.
1295	*/
1296	RTCCUINTREG fFlags = ASMIntDisableFlags();
1297	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
1298	ASMAtomicWriteBool(&pCpu->fInUse, true);
1299	ASMSetFlags(fFlags);
1300
1301	int rc = g_HvmR0.pfnTermVM(pVM);
1302
1303	ASMAtomicWriteBool(&pCpu->fInUse, false);
1304	return rc;
1305	}
1306
1307
1308	/**
1309	* Sets up a VT-x or AMD-V session.
1310	*
1311	* This is mostly about setting up the hardware VM state.
1312	*
1313	* @returns VBox status code.
1314	* @param pVM Pointer to the VM.
1315	*/
1316	VMMR0DECL(int) HMR0SetupVM(PVM pVM)
1317	{
1318	Log(("HMR0SetupVM: %p\n", pVM));
1319	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1320
1321	/* Make sure we don't touch hm after we've disabled hm in
1322	preparation of a suspend. */
1323	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1324
1325
1326	/*
1327	* Call the hardware specific setup VM method. This requires the CPU to be
1328	* enabled for AMD-V/VT-x and preemption to be prevented.
1329	*/
1330	RTCCUINTREG fFlags = ASMIntDisableFlags();
1331	RTCPUID idCpu = RTMpCpuId();
1332	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1333	ASMAtomicWriteBool(&pCpu->fInUse, true);
1334
1335	/* On first entry we'll sync everything. */
1336	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1337	pVM->aCpus[i].hm.s.fContextUseFlags = HM_CHANGED_ALL;
1338
1339	/* Enable VT-x or AMD-V if local init is required. */
1340	int rc;
1341	if (!g_HvmR0.fGlobalInit)
1342	{
1343	rc = hmR0EnableCpu(pVM, idCpu);
1344	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1345	}
1346
1347	/* Setup VT-x or AMD-V. */
1348	rc = g_HvmR0.pfnSetupVM(pVM);
1349
1350	/* Disable VT-x or AMD-V if local init was done before. */
1351	if (!g_HvmR0.fGlobalInit)
1352	{
1353	int rc2 = hmR0DisableCpu(idCpu);
1354	AssertRC(rc2);
1355	}
1356
1357	ASMAtomicWriteBool(&pCpu->fInUse, false);
1358	ASMSetFlags(fFlags);
1359
1360	return rc;
1361	}
1362
1363
1364	/**
1365	* Enters the VT-x or AMD-V session.
1366	*
1367	* @returns VBox status code.
1368	* @param pVM Pointer to the VM.
1369	* @param pVCpu Pointer to the VMCPU.
1370	*
1371	* @remarks This is called with preemption disabled.
1372	*/
1373	VMMR0DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1374	{
1375	RTCPUID idCpu = RTMpCpuId();
1376	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1377
1378	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1379	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1380	ASMAtomicWriteBool(&pCpu->fInUse, true);
1381
1382	AssertMsg(pVCpu->hm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hm.s.idEnteredCpu));
1383	pVCpu->hm.s.idEnteredCpu = idCpu;
1384
1385	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1386
1387	/* Always load the guest's FPU/XMM state on-demand. */
1388	CPUMDeactivateGuestFPUState(pVCpu);
1389
1390	/* Always load the guest's debug state on-demand. */
1391	CPUMDeactivateGuestDebugState(pVCpu);
1392
1393	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1394	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0 \| HM_CHANGED_HOST_CONTEXT;
1395
1396	/* Setup the register and mask according to the current execution mode. */
1397	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1398	pVM->hm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1399	else
1400	pVM->hm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1401
1402	/* Enable VT-x or AMD-V if local init is required, or enable if it's a
1403	freshly onlined CPU. */
1404	int rc;
1405	if ( !pCpu->fConfigured
1406	\|\| !g_HvmR0.fGlobalInit)
1407	{
1408	rc = hmR0EnableCpu(pVM, idCpu);
1409	AssertRCReturn(rc, rc);
1410	}
1411
1412	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1413	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1414	#endif
1415
1416	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1417	AssertRC(rc);
1418	/* We must save the host context here (VT-x) as we might be rescheduled on
1419	a different cpu after a long jump back to ring 3. */
1420	rc \|= g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1421	AssertRC(rc);
1422	rc \|= g_HvmR0.pfnLoadGuestState(pVM, pVCpu, pCtx);
1423	AssertRC(rc);
1424
1425	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1426	if (fStartedSet)
1427	PGMRZDynMapReleaseAutoSet(pVCpu);
1428	#endif
1429
1430	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1431	and ring-3 calls. */
1432	if (RT_FAILURE(rc))
1433	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1434	return rc;
1435	}
1436
1437
1438	/**
1439	* Leaves the VT-x or AMD-V session.
1440	*
1441	* @returns VBox status code.
1442	* @param pVM Pointer to the VM.
1443	* @param pVCpu Pointer to the VMCPU.
1444	*
1445	* @remarks Called with preemption disabled just like HMR0Enter, our
1446	* counterpart.
1447	*/
1448	VMMR0DECL(int) HMR0Leave(PVM pVM, PVMCPU pVCpu)
1449	{
1450	int rc;
1451	RTCPUID idCpu = RTMpCpuId();
1452	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1453	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1454
1455	/** @todo r=bird: This can't be entirely right? */
1456	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1457
1458	/*
1459	* Save the guest FPU and XMM state if necessary.
1460	*
1461	* Note! It's rather tricky with longjmps done by e.g. Log statements or
1462	* the page fault handler. We must restore the host FPU here to make
1463	* absolutely sure we don't leave the guest FPU state active or trash
1464	* somebody else's FPU state.
1465	*/
1466	if (CPUMIsGuestFPUStateActive(pVCpu))
1467	{
1468	Log2(("CPUMR0SaveGuestFPU\n"));
1469	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1470
1471	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
1472	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1473	}
1474
1475	rc = g_HvmR0.pfnLeaveSession(pVM, pVCpu, pCtx);
1476
1477	/* We don't pass on invlpg information to the recompiler for nested paging
1478	guests, so we must make sure the recompiler flushes its TLB the next
1479	time it executes code. */
1480	if ( pVM->hm.s.fNestedPaging
1481	&& CPUMIsGuestInPagedProtectedModeEx(pCtx))
1482	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1483
1484	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1485	and ring-3 calls. */
1486	AssertMsgStmt( pVCpu->hm.s.idEnteredCpu == idCpu
1487	\|\| RT_FAILURE_NP(rc),
1488	("Owner is %u, I'm %u", pVCpu->hm.s.idEnteredCpu, idCpu),
1489	rc = VERR_HM_WRONG_CPU_1);
1490	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1491
1492	/*
1493	* Disable VT-x or AMD-V if local init was done before.
1494	*/
1495	if (!g_HvmR0.fGlobalInit)
1496	{
1497	rc = hmR0DisableCpu(idCpu);
1498	AssertRC(rc);
1499
1500	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1501	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1502	pVCpu->hm.s.uCurrentASID = 0;
1503	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1504	}
1505
1506	ASMAtomicWriteBool(&pCpu->fInUse, false);
1507	return rc;
1508	}
1509
1510
1511	/**
1512	* Runs guest code in a hardware accelerated VM.
1513	*
1514	* @returns VBox status code.
1515	* @param pVM Pointer to the VM.
1516	* @param pVCpu Pointer to the VMCPU.
1517	*
1518	* @remarks Called with preemption disabled and after first having called
1519	* HMR0Enter.
1520	*/
1521	VMMR0DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1522	{
1523	#ifdef VBOX_STRICT
1524	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1525	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1526	Assert(pCpu->fConfigured);
1527	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1528	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1529	#endif
1530
1531	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1532	PGMRZDynMapStartAutoSet(pVCpu);
1533	#endif
1534
1535	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1536
1537	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1538	PGMRZDynMapReleaseAutoSet(pVCpu);
1539	#endif
1540	return rc;
1541	}
1542
1543	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1544
1545	/**
1546	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1547	*
1548	* @returns VBox status code.
1549	* @param pVM Pointer to the VM.
1550	* @param pVCpu Pointer to the VMCPU.
1551	* @param pCtx Pointer to the guest CPU context.
1552	*/
1553	VMMR0DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1554	{
1555	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1556	if (pVM->hm.s.vmx.fSupported)
1557	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnSaveGuestFPU64, 0, NULL);
1558	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnSaveGuestFPU64, 0, NULL);
1559	}
1560
1561
1562	/**
1563	* Save guest debug state (64 bits guest mode & 32 bits host only)
1564	*
1565	* @returns VBox status code.
1566	* @param pVM Pointer to the VM.
1567	* @param pVCpu Pointer to the VMCPU.
1568	* @param pCtx Pointer to the guest CPU context.
1569	*/
1570	VMMR0DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1571	{
1572	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1573	if (pVM->hm.s.vmx.fSupported)
1574	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnSaveGuestDebug64, 0, NULL);
1575	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnSaveGuestDebug64, 0, NULL);
1576	}
1577
1578
1579	/**
1580	* Test the 32->64 bits switcher.
1581	*
1582	* @returns VBox status code.
1583	* @param pVM Pointer to the VM.
1584	*/
1585	VMMR0DECL(int) HMR0TestSwitcher3264(PVM pVM)
1586	{
1587	PVMCPU pVCpu = &pVM->aCpus[0];
1588	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1589	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1590	int rc;
1591
1592	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1593	if (pVM->hm.s.vmx.fSupported)
1594	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnTest64, 5, &aParam[0]);
1595	else
1596	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnTest64, 5, &aParam[0]);
1597	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1598
1599	return rc;
1600	}
1601
1602	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1603
1604	/**
1605	* Returns suspend status of the host.
1606	*
1607	* @returns Suspend pending or not.
1608	*/
1609	VMMR0DECL(bool) HMR0SuspendPending(void)
1610	{
1611	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1612	}
1613
1614
1615	/**
1616	* Returns the cpu structure for the current cpu.
1617	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1618	*
1619	* @returns The cpu structure pointer.
1620	*/
1621	VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpu(void)
1622	{
1623	RTCPUID idCpu = RTMpCpuId();
1624	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1625	return &g_HvmR0.aCpuInfo[idCpu];
1626	}
1627
1628
1629	/**
1630	* Returns the cpu structure for the current cpu.
1631	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1632	*
1633	* @returns The cpu structure pointer.
1634	* @param idCpu id of the VCPU.
1635	*/
1636	VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1637	{
1638	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1639	return &g_HvmR0.aCpuInfo[idCpu];
1640	}
1641
1642
1643	/**
1644	* Save a pending IO read.
1645	*
1646	* @param pVCpu Pointer to the VMCPU.
1647	* @param GCPtrRip Address of IO instruction.
1648	* @param GCPtrRipNext Address of the next instruction.
1649	* @param uPort Port address.
1650	* @param uAndVal AND mask for saving the result in eax.
1651	* @param cbSize Read size.
1652	*/
1653	VMMR0DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1654	{
1655	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1656	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1657	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1658	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1659	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1660	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1661	return;
1662	}
1663
1664
1665	/**
1666	* Save a pending IO write.
1667	*
1668	* @param pVCpu Pointer to the VMCPU.
1669	* @param GCPtrRIP Address of IO instruction.
1670	* @param uPort Port address.
1671	* @param uAndVal AND mask for fetching the result from eax.
1672	* @param cbSize Read size.
1673	*/
1674	VMMR0DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1675	{
1676	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1677	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1678	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1679	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1680	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1681	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1682	return;
1683	}
1684
1685
1686	/**
1687	* Raw-mode switcher hook - disable VT-x if it's active and the current
1688	* switcher turns off paging.
1689	*
1690	* @returns VBox status code.
1691	* @param pVM Pointer to the VM.
1692	* @param enmSwitcher The switcher we're about to use.
1693	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1694	*/
1695	VMMR0DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1696	{
1697	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1698
1699	*pfVTxDisabled = false;
1700
1701	/* No such issues with AMD-V */
1702	if (!g_HvmR0.vmx.fSupported)
1703	return VINF_SUCCESS;
1704
1705	/* Check if the swithcing we're up to is safe. */
1706	switch (enmSwitcher)
1707	{
1708	case VMMSWITCHER_32_TO_32:
1709	case VMMSWITCHER_PAE_TO_PAE:
1710	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1711
1712	case VMMSWITCHER_32_TO_PAE:
1713	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1714	case VMMSWITCHER_AMD64_TO_32:
1715	case VMMSWITCHER_AMD64_TO_PAE:
1716	break; /* unsafe switchers */
1717
1718	default:
1719	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1720	}
1721
1722	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1723	regardless of whether we're currently using VT-x or not. */
1724	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1725	{
1726	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1727	return VINF_SUCCESS;
1728	}
1729
1730	/** @todo Check if this code is presumtive wrt other VT-x users on the
1731	* system... */
1732
1733	/* Nothing to do if we haven't enabled VT-x. */
1734	if (!g_HvmR0.fEnabled)
1735	return VINF_SUCCESS;
1736
1737	/* Local init implies the CPU is currently not in VMX root mode. */
1738	if (!g_HvmR0.fGlobalInit)
1739	return VINF_SUCCESS;
1740
1741	/* Ok, disable VT-x. */
1742	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
1743	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1744
1745	*pfVTxDisabled = true;
1746	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1747	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1748	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1749	}
1750
1751
1752	/**
1753	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1754	* switcher turned off paging.
1755	*
1756	* @param pVM Pointer to the VM.
1757	* @param fVTxDisabled Whether VT-x was disabled or not.
1758	*/
1759	VMMR0DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1760	{
1761	Assert(!(ASMGetFlags() & X86_EFL_IF));
1762
1763	if (!fVTxDisabled)
1764	return; /* nothing to do */
1765
1766	Assert(g_HvmR0.vmx.fSupported);
1767	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1768	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1769	else
1770	{
1771	Assert(g_HvmR0.fEnabled);
1772	Assert(g_HvmR0.fGlobalInit);
1773
1774	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
1775	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1776
1777	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1778	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1779	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
1780	}
1781	}
1782
1783	#ifdef VBOX_STRICT
1784
1785	/**
1786	* Dumps a descriptor.
1787	*
1788	* @param pDesc Descriptor to dump.
1789	* @param Sel Selector number.
1790	* @param pszMsg Message to prepend the log entry with.
1791	*/
1792	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1793	{
1794	/*
1795	* Make variable description string.
1796	*/
1797	static struct
1798	{
1799	unsigned cch;
1800	const char *psz;
1801	} const s_aTypes[32] =
1802	{
1803	# define STRENTRY(str) { sizeof(str) - 1, str }
1804
1805	/* system */
1806	# if HC_ARCH_BITS == 64
1807	STRENTRY("Reserved0 "), /* 0x00 */
1808	STRENTRY("Reserved1 "), /* 0x01 */
1809	STRENTRY("LDT "), /* 0x02 */
1810	STRENTRY("Reserved3 "), /* 0x03 */
1811	STRENTRY("Reserved4 "), /* 0x04 */
1812	STRENTRY("Reserved5 "), /* 0x05 */
1813	STRENTRY("Reserved6 "), /* 0x06 */
1814	STRENTRY("Reserved7 "), /* 0x07 */
1815	STRENTRY("Reserved8 "), /* 0x08 */
1816	STRENTRY("TSS64Avail "), /* 0x09 */
1817	STRENTRY("ReservedA "), /* 0x0a */
1818	STRENTRY("TSS64Busy "), /* 0x0b */
1819	STRENTRY("Call64 "), /* 0x0c */
1820	STRENTRY("ReservedD "), /* 0x0d */
1821	STRENTRY("Int64 "), /* 0x0e */
1822	STRENTRY("Trap64 "), /* 0x0f */
1823	# else
1824	STRENTRY("Reserved0 "), /* 0x00 */
1825	STRENTRY("TSS16Avail "), /* 0x01 */
1826	STRENTRY("LDT "), /* 0x02 */
1827	STRENTRY("TSS16Busy "), /* 0x03 */
1828	STRENTRY("Call16 "), /* 0x04 */
1829	STRENTRY("Task "), /* 0x05 */
1830	STRENTRY("Int16 "), /* 0x06 */
1831	STRENTRY("Trap16 "), /* 0x07 */
1832	STRENTRY("Reserved8 "), /* 0x08 */
1833	STRENTRY("TSS32Avail "), /* 0x09 */
1834	STRENTRY("ReservedA "), /* 0x0a */
1835	STRENTRY("TSS32Busy "), /* 0x0b */
1836	STRENTRY("Call32 "), /* 0x0c */
1837	STRENTRY("ReservedD "), /* 0x0d */
1838	STRENTRY("Int32 "), /* 0x0e */
1839	STRENTRY("Trap32 "), /* 0x0f */
1840	# endif
1841	/* non system */
1842	STRENTRY("DataRO "), /* 0x10 */
1843	STRENTRY("DataRO Accessed "), /* 0x11 */
1844	STRENTRY("DataRW "), /* 0x12 */
1845	STRENTRY("DataRW Accessed "), /* 0x13 */
1846	STRENTRY("DataDownRO "), /* 0x14 */
1847	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1848	STRENTRY("DataDownRW "), /* 0x16 */
1849	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1850	STRENTRY("CodeEO "), /* 0x18 */
1851	STRENTRY("CodeEO Accessed "), /* 0x19 */
1852	STRENTRY("CodeER "), /* 0x1a */
1853	STRENTRY("CodeER Accessed "), /* 0x1b */
1854	STRENTRY("CodeConfEO "), /* 0x1c */
1855	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1856	STRENTRY("CodeConfER "), /* 0x1e */
1857	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1858	# undef SYSENTRY
1859	};
1860	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1861	char szMsg[128];
1862	char *psz = &szMsg[0];
1863	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1864	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1865	psz += s_aTypes[i].cch;
1866
1867	if (pDesc->Gen.u1Present)
1868	ADD_STR(psz, "Present ");
1869	else
1870	ADD_STR(psz, "Not-Present ");
1871	# if HC_ARCH_BITS == 64
1872	if (pDesc->Gen.u1Long)
1873	ADD_STR(psz, "64-bit ");
1874	else
1875	ADD_STR(psz, "Comp ");
1876	# else
1877	if (pDesc->Gen.u1Granularity)
1878	ADD_STR(psz, "Page ");
1879	if (pDesc->Gen.u1DefBig)
1880	ADD_STR(psz, "32-bit ");
1881	else
1882	ADD_STR(psz, "16-bit ");
1883	# endif
1884	# undef ADD_STR
1885	*psz = '\0';
1886
1887	/*
1888	* Limit and Base and format the output.
1889	*/
1890	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1891
1892	# if HC_ARCH_BITS == 64
1893	uint64_t u32Base = X86DESC64_BASE(pDesc);
1894
1895	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1896	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1897	# else
1898	uint32_t u32Base = X86DESC_BASE(pDesc);
1899
1900	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1901	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1902	# endif
1903	}
1904
1905
1906	/**
1907	* Formats a full register dump.
1908	*
1909	* @param pVM Pointer to the VM.
1910	* @param pVCpu Pointer to the VMCPU.
1911	* @param pCtx Pointer to the CPU context.
1912	*/
1913	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1914	{
1915	NOREF(pVM);
1916
1917	/*
1918	* Format the flags.
1919	*/
1920	static struct
1921	{
1922	const char pszSet; const char pszClear; uint32_t fFlag;
1923	} const s_aFlags[] =
1924	{
1925	{ "vip",NULL, X86_EFL_VIP },
1926	{ "vif",NULL, X86_EFL_VIF },
1927	{ "ac", NULL, X86_EFL_AC },
1928	{ "vm", NULL, X86_EFL_VM },
1929	{ "rf", NULL, X86_EFL_RF },
1930	{ "nt", NULL, X86_EFL_NT },
1931	{ "ov", "nv", X86_EFL_OF },
1932	{ "dn", "up", X86_EFL_DF },
1933	{ "ei", "di", X86_EFL_IF },
1934	{ "tf", NULL, X86_EFL_TF },
1935	{ "nt", "pl", X86_EFL_SF },
1936	{ "nz", "zr", X86_EFL_ZF },
1937	{ "ac", "na", X86_EFL_AF },
1938	{ "po", "pe", X86_EFL_PF },
1939	{ "cy", "nc", X86_EFL_CF },
1940	};
1941	char szEFlags[80];
1942	char *psz = szEFlags;
1943	uint32_t efl = pCtx->eflags.u32;
1944	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1945	{
1946	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1947	if (pszAdd)
1948	{
1949	strcpy(psz, pszAdd);
1950	psz += strlen(pszAdd);
1951	*psz++ = ' ';
1952	}
1953	}
1954	psz[-1] = '\0';
1955
1956
1957	/*
1958	* Format the registers.
1959	*/
1960	if (CPUMIsGuestIn64BitCode(pVCpu))
1961	{
1962	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1963	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1964	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1965	"r14=%016RX64 r15=%016RX64\n"
1966	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1967	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1968	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1969	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1970	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1971	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1972	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1973	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1974	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1975	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1976	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1977	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1978	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1979	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1980	,
1981	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1982	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1983	pCtx->r14, pCtx->r15,
1984	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1985	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1986	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1987	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1988	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1989	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1990	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1991	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1992	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1993	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1994	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1995	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1996	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1997	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1998	}
1999	else
2000	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2001	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2002	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2003	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2004	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2005	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2006	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2007	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2008	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2009	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2010	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2011	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2012	,
2013	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2014	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2015	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2016	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2017	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2018	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2019	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2020	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2021	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2022	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2023	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2024	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2025
2026	Log(("FPU:\n"
2027	"FCW=%04x FSW=%04x FTW=%02x\n"
2028	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2029	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2030	,
2031	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2032	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2033	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2034	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2035
2036
2037	Log(("MSR:\n"
2038	"EFER =%016RX64\n"
2039	"PAT =%016RX64\n"
2040	"STAR =%016RX64\n"
2041	"CSTAR =%016RX64\n"
2042	"LSTAR =%016RX64\n"
2043	"SFMASK =%016RX64\n"
2044	"KERNELGSBASE =%016RX64\n",
2045	pCtx->msrEFER,
2046	pCtx->msrPAT,
2047	pCtx->msrSTAR,
2048	pCtx->msrCSTAR,
2049	pCtx->msrLSTAR,
2050	pCtx->msrSFMASK,
2051	pCtx->msrKERNELGSBASE));
2052
2053	}
2054
2055	#endif /* VBOX_STRICT */
2056

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 43466

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