HMR0.cpp@ 48130

Last change on this file since 48130 was 48044, checked in by vboxsync, 11 years ago
VMM/HM: Thread-context hooks, disable preemption while touching host state on VM-exits. AMD-V still todo.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 74.8 KB

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1	/* $Id: HMR0.cpp 48044 2013-08-25 19:21:27Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
90	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
91	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
92	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
94	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
95	bool fEnabledByHost));
96	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
97	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
99	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
100	/** @} */
101
102	/** Maximum ASID allowed. */
103	uint32_t uMaxAsid;
104
105	/** VT-x data. */
106	struct
107	{
108	/** Set to by us to indicate VMX is supported by the CPU. */
109	bool fSupported;
110	/** Whether we're using SUPR0EnableVTx or not. */
111	bool fUsingSUPR0EnableVTx;
112	/** Whether we're using the preemption timer or not. */
113	bool fUsePreemptTimer;
114	/** The shift mask employed by the VMX-Preemption timer. */
115	uint8_t cPreemptTimerShift;
116
117	/** Host CR4 value (set by ring-0 VMX init) */
118	uint64_t hostCR4;
119
120	/** Host EFER value (set by ring-0 VMX init) */
121	uint64_t hostEFER;
122
123	/** VMX MSR values */
124	struct
125	{
126	uint64_t feature_ctrl;
127	uint64_t vmx_basic_info;
128	VMX_CAPABILITY vmx_pin_ctls;
129	VMX_CAPABILITY vmx_proc_ctls;
130	VMX_CAPABILITY vmx_proc_ctls2;
131	VMX_CAPABILITY vmx_exit;
132	VMX_CAPABILITY vmx_entry;
133	uint64_t vmx_misc;
134	uint64_t vmx_cr0_fixed0;
135	uint64_t vmx_cr0_fixed1;
136	uint64_t vmx_cr4_fixed0;
137	uint64_t vmx_cr4_fixed1;
138	uint64_t vmx_vmcs_enum;
139	uint64_t vmx_vmfunc;
140	uint64_t vmx_ept_vpid_caps;
141	} msr;
142	/* Last instruction error */
143	uint32_t ulLastInstrError;
144	} vmx;
145
146	/** AMD-V information. */
147	struct
148	{
149	/* HWCR MSR (for diagnostics) */
150	uint64_t msrHwcr;
151
152	/** SVM revision. */
153	uint32_t u32Rev;
154
155	/** SVM feature bits from cpuid 0x8000000a */
156	uint32_t u32Features;
157
158	/** Set by us to indicate SVM is supported by the CPU. */
159	bool fSupported;
160	} svm;
161	/** Saved error from detection */
162	int32_t lLastError;
163
164	struct
165	{
166	uint32_t u32AMDFeatureECX;
167	uint32_t u32AMDFeatureEDX;
168	} cpuid;
169
170	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
171	* enabled and disabled each time it's used to execute guest code. */
172	bool fGlobalInit;
173	/** Indicates whether the host is suspending or not. We'll refuse a few
174	* actions when the host is being suspended to speed up the suspending and
175	* avoid trouble. */
176	volatile bool fSuspended;
177
178	/** Whether we've already initialized all CPUs.
179	* @remarks We could check the EnableAllCpusOnce state, but this is
180	* simpler and hopefully easier to understand. */
181	bool fEnabled;
182	/** Serialize initialization in HMR0EnableAllCpus. */
183	RTONCE EnableAllCpusOnce;
184	} g_HvmR0;
185
186
187
188	/**
189	* Initializes a first return code structure.
190	*
191	* @param pFirstRc The structure to init.
192	*/
193	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
194	{
195	pFirstRc->rc = VINF_SUCCESS;
196	pFirstRc->idCpu = NIL_RTCPUID;
197	}
198
199
200	/**
201	* Try set the status code (success ignored).
202	*
203	* @param pFirstRc The first return code structure.
204	* @param rc The status code.
205	*/
206	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
207	{
208	if ( RT_FAILURE(rc)
209	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
210	pFirstRc->idCpu = RTMpCpuId();
211	}
212
213
214	/**
215	* Get the status code of a first return code structure.
216	*
217	* @returns The status code; VINF_SUCCESS or error status, no informational or
218	* warning errors.
219	* @param pFirstRc The first return code structure.
220	*/
221	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
222	{
223	return pFirstRc->rc;
224	}
225
226
227	#ifdef VBOX_STRICT
228	/**
229	* Get the CPU ID on which the failure status code was reported.
230	*
231	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
232	* @param pFirstRc The first return code structure.
233	*/
234	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
235	{
236	return pFirstRc->idCpu;
237	}
238	#endif /* VBOX_STRICT */
239
240
241	/** @name Dummy callback handlers.
242	* @{ */
243
244	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
245	{
246	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
247	return VINF_SUCCESS;
248	}
249
250	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
251	{
252	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
253	return VINF_SUCCESS;
254	}
255
256	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
257	{
258	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
259	}
260
261	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
262	bool fEnabledBySystem)
263	{
264	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem);
265	return VINF_SUCCESS;
266	}
267
268	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
269	{
270	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
271	return VINF_SUCCESS;
272	}
273
274	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
275	{
276	NOREF(pVM);
277	return VINF_SUCCESS;
278	}
279
280	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
281	{
282	NOREF(pVM);
283	return VINF_SUCCESS;
284	}
285
286	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
287	{
288	NOREF(pVM);
289	return VINF_SUCCESS;
290	}
291
292	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
293	{
294	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
295	return VINF_SUCCESS;
296	}
297
298	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
299	{
300	NOREF(pVM); NOREF(pVCpu);
301	return VINF_SUCCESS;
302	}
303
304	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
305	{
306	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
307	return VINF_SUCCESS;
308	}
309
310	/** @} */
311
312
313	/**
314	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
315	* Down at the Rate Specified" erratum.
316	*
317	* Errata names and related steppings:
318	* - BA86 - D0.
319	* - AAX65 - C2.
320	* - AAU65 - C2, K0.
321	* - AAO95 - B1.
322	* - AAT59 - C2.
323	* - AAK139 - D0.
324	* - AAM126 - C0, C1, D0.
325	* - AAN92 - B1.
326	* - AAJ124 - C0, D0.
327	*
328	* - AAP86 - B1.
329	*
330	* Steppings: B1, C0, C1, C2, D0, K0.
331	*
332	* @returns true if subject to it, false if not.
333	*/
334	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
335	{
336	uint32_t u = ASMCpuId_EAX(1);
337	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
338	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
339	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
340	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
341	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
342	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
343	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
344	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
345	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
346	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
347	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
348	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
349	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
350	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
351	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
352	)
353	return true;
354	return false;
355	}
356
357
358	/**
359	* Intel specific initialization code.
360	*
361	* @returns VBox status code (will only fail if out of memory).
362	*/
363	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
364	{
365	/*
366	* Check that all the required VT-x features are present.
367	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
368	*/
369	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
370	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
371	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
372	)
373	{
374	/** @todo move this into a separate function. */
375	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
376
377	/*
378	* First try use native kernel API for controlling VT-x.
379	* (This is only supported by some Mac OS X kernels atm.)
380	*/
381	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
382	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
383	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
384	{
385	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
386	if (RT_SUCCESS(rc))
387	{
388	g_HvmR0.vmx.fSupported = true;
389	rc = SUPR0EnableVTx(false /* fEnable */);
390	AssertLogRelRC(rc);
391	}
392	}
393	else
394	{
395	/* We need to check if VT-x has been properly initialized on all
396	CPUs. Some BIOSes do a lousy job. */
397	HMR0FIRSTRC FirstRc;
398	hmR0FirstRcInit(&FirstRc);
399	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
400	if (RT_SUCCESS(g_HvmR0.lLastError))
401	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
402	}
403	if (RT_SUCCESS(g_HvmR0.lLastError))
404	{
405	/* Reread in case we've changed it. */
406	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
407
408	if ( (g_HvmR0.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
409	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
410	{
411	/*
412	* Read all relevant MSR.
413	*/
414	g_HvmR0.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
415	g_HvmR0.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
416	g_HvmR0.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
417	g_HvmR0.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
418	g_HvmR0.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
419	g_HvmR0.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
420	g_HvmR0.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
421	g_HvmR0.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
422	g_HvmR0.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
423	g_HvmR0.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
424	g_HvmR0.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
425	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
426	g_HvmR0.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
427	/* VPID 16 bits ASID. */
428	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
429
430	if (g_HvmR0.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
431	{
432	g_HvmR0.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
433	if ( g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1
434	& (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
435	{
436	g_HvmR0.vmx.msr.vmx_ept_vpid_caps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
437	}
438
439	if (g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
440	g_HvmR0.vmx.msr.vmx_vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
441	}
442
443	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
444	{
445	/*
446	* Enter root mode
447	*/
448	RTR0MEMOBJ hScatchMemObj;
449	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
450	if (RT_FAILURE(rc))
451	{
452	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
453	return rc;
454	}
455
456	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
457	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
458	ASMMemZeroPage(pvScatchPage);
459
460	/* Set revision dword at the beginning of the structure. */
461	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.vmx_basic_info);
462
463	/* Make sure we don't get rescheduled to another cpu during this probe. */
464	RTCCUINTREG fFlags = ASMIntDisableFlags();
465
466	/*
467	* Check CR4.VMXE
468	*/
469	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
470	if (!(g_HvmR0.vmx.hostCR4 & X86_CR4_VMXE))
471	{
472	/* In theory this bit could be cleared behind our back. Which would cause
473	#UD faults when we try to execute the VMX instructions... */
474	ASMSetCR4(g_HvmR0.vmx.hostCR4 \| X86_CR4_VMXE);
475	}
476
477	/*
478	* The only way of checking if we're in VMX root mode or not is to try and enter it.
479	* There is no instruction or control bit that tells us if we're in VMX root mode.
480	* Therefore, try and enter VMX root mode here.
481	*/
482	rc = VMXEnable(HCPhysScratchPage);
483	if (RT_SUCCESS(rc))
484	{
485	g_HvmR0.vmx.fSupported = true;
486	VMXDisable();
487	}
488	else
489	{
490	/*
491	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
492	* it will crash the host when we enter raw mode, because:
493	*
494	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
495	* this bit), and
496	* (b) turning off paging causes a #GP (unavoidable when switching
497	* from long to 32 bits mode or 32 bits to PAE).
498	*
499	* They should fix their code, but until they do we simply refuse to run.
500	*/
501	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
502	}
503
504	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
505	if it wasn't so before (some software could incorrectly
506	think it's in VMX mode). */
507	ASMSetCR4(g_HvmR0.vmx.hostCR4);
508	ASMSetFlags(fFlags);
509
510	RTR0MemObjFree(hScatchMemObj, false);
511	}
512	}
513	else
514	{
515	AssertFailed(); /* can't hit this case anymore */
516	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
517	}
518
519	if (g_HvmR0.vmx.fSupported)
520	{
521	/* Call the global VT-x initialization routine. */
522	rc = VMXR0GlobalInit();
523	if (RT_FAILURE(rc))
524	g_HvmR0.lLastError = rc;
525
526	/*
527	* Install the VT-x methods.
528	*/
529	g_HvmR0.pfnEnterSession = VMXR0Enter;
530	g_HvmR0.pfnLeaveSession = VMXR0Leave;
531	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
532	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
533	g_HvmR0.pfnLoadGuestState = VMXR0LoadGuestState;
534	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
535	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
536	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
537	g_HvmR0.pfnInitVM = VMXR0InitVM;
538	g_HvmR0.pfnTermVM = VMXR0TermVM;
539	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
540
541	/*
542	* Check for the VMX-Preemption Timer and adjust for the * "VMX-Preemption
543	* Timer Does Not Count Down at the Rate Specified" erratum.
544	*/
545	if (g_HvmR0.vmx.msr.vmx_pin_ctls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
546	{
547	g_HvmR0.vmx.fUsePreemptTimer = true;
548	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.vmx_misc);
549	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
550	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
551	}
552	}
553	}
554	#ifdef LOG_ENABLED
555	else
556	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
557	#endif
558	}
559	else
560	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
561	return VINF_SUCCESS;
562	}
563
564
565	/**
566	* AMD-specific initialization code.
567	*
568	* @returns VBox status code.
569	*/
570	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
571	{
572	/*
573	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
574	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
575	*/
576	int rc;
577	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
578	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
579	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
580	&& ASMIsValidExtRange(uMaxExtLeaf)
581	&& uMaxExtLeaf >= 0x8000000a
582	)
583	{
584	/* Call the global AMD-V initialization routine. */
585	rc = SVMR0GlobalInit();
586	if (RT_FAILURE(rc))
587	{
588	g_HvmR0.lLastError = rc;
589	return rc;
590	}
591
592	/*
593	* Install the AMD-V methods.
594	*/
595	g_HvmR0.pfnEnterSession = SVMR0Enter;
596	g_HvmR0.pfnLeaveSession = SVMR0Leave;
597	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
598	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
599	g_HvmR0.pfnLoadGuestState = SVMR0LoadGuestState;
600	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
601	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
602	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
603	g_HvmR0.pfnInitVM = SVMR0InitVM;
604	g_HvmR0.pfnTermVM = SVMR0TermVM;
605	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
606
607	/* Query AMD features. */
608	uint32_t u32Dummy;
609	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
610
611	/*
612	* We need to check if AMD-V has been properly initialized on all CPUs.
613	* Some BIOSes might do a poor job.
614	*/
615	HMR0FIRSTRC FirstRc;
616	hmR0FirstRcInit(&FirstRc);
617	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
618	AssertRC(rc);
619	if (RT_SUCCESS(rc))
620	rc = hmR0FirstRcGetStatus(&FirstRc);
621	#ifndef DEBUG_bird
622	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
623	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
624	#endif
625	if (RT_SUCCESS(rc))
626	{
627	/* Read the HWCR MSR for diagnostics. */
628	g_HvmR0.svm.msrHwcr = ASMRdMsr(MSR_K8_HWCR);
629	g_HvmR0.svm.fSupported = true;
630	}
631	else
632	g_HvmR0.lLastError = rc;
633	}
634	else
635	{
636	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
637	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
638	}
639	return rc;
640	}
641
642
643	/**
644	* Does global Ring-0 HM initialization (at module init).
645	*
646	* @returns VBox status code.
647	*/
648	VMMR0_INT_DECL(int) HMR0Init(void)
649	{
650	/*
651	* Initialize the globals.
652	*/
653	g_HvmR0.fEnabled = false;
654	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
655	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
656	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
657	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
658
659	/* Fill in all callbacks with placeholders. */
660	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
661	g_HvmR0.pfnLeaveSession = hmR0DummyLeave;
662	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
663	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
664	g_HvmR0.pfnLoadGuestState = hmR0DummyLoadGuestState;
665	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
666	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
667	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
668	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
669	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
670	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
671
672	/* Default is global VT-x/AMD-V init. */
673	g_HvmR0.fGlobalInit = true;
674
675	/*
676	* Make sure aCpuInfo is big enough for all the CPUs on this system.
677	*/
678	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
679	{
680	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
681	return VERR_TOO_MANY_CPUS;
682	}
683
684	/*
685	* Check for VT-x and AMD-V capabilities.
686	*/
687	int rc;
688	if (ASMHasCpuId())
689	{
690	/* Standard features. */
691	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
692	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
693	if (ASMIsValidStdRange(uMaxLeaf))
694	{
695	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
696	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
697
698	/* Query AMD features. */
699	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
700	if (ASMIsValidExtRange(uMaxExtLeaf))
701	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
702	&g_HvmR0.cpuid.u32AMDFeatureECX,
703	&g_HvmR0.cpuid.u32AMDFeatureEDX);
704	else
705	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
706
707	/* Go to CPU specific initialization code. */
708	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
709	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
710	{
711	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
712	if (RT_FAILURE(rc))
713	return rc;
714	}
715	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
716	{
717	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
718	if (RT_FAILURE(rc))
719	return rc;
720	}
721	else
722	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
723	}
724	else
725	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
726	}
727	else
728	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
729
730	/*
731	* Register notification callbacks that we can use to disable/enable CPUs
732	* when brought offline/online or suspending/resuming.
733	*/
734	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
735	{
736	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
737	AssertRC(rc);
738
739	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
740	AssertRC(rc);
741	}
742
743	/* We return success here because module init shall not fail if HM
744	fails to initialize. */
745	return VINF_SUCCESS;
746	}
747
748
749	/**
750	* Does global Ring-0 HM termination (at module termination).
751	*
752	* @returns VBox status code.
753	*/
754	VMMR0_INT_DECL(int) HMR0Term(void)
755	{
756	int rc;
757	if ( g_HvmR0.vmx.fSupported
758	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
759	{
760	/*
761	* Simple if the host OS manages VT-x.
762	*/
763	Assert(g_HvmR0.fGlobalInit);
764	rc = SUPR0EnableVTx(false /* fEnable */);
765
766	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
767	{
768	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
769	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
770	}
771	}
772	else
773	{
774	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
775	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
776	{
777	/* Doesn't really matter if this fails. */
778	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
779	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
780	}
781	else
782	rc = VINF_SUCCESS;
783
784	/*
785	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
786	*/
787	if (g_HvmR0.fGlobalInit)
788	{
789	HMR0FIRSTRC FirstRc;
790	hmR0FirstRcInit(&FirstRc);
791	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
792	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
793	if (RT_SUCCESS(rc))
794	{
795	rc = hmR0FirstRcGetStatus(&FirstRc);
796	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
797	}
798	}
799
800	/*
801	* Free the per-cpu pages used for VT-x and AMD-V.
802	*/
803	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
804	{
805	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
806	{
807	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
808	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
809	}
810	}
811	}
812
813	/** @todo This needs cleaning up. There's no matching
814	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
815	* should move into their respective modules. */
816	/* Finally, call global VT-x/AMD-V termination. */
817	if (g_HvmR0.vmx.fSupported)
818	VMXR0GlobalTerm();
819	else if (g_HvmR0.svm.fSupported)
820	SVMR0GlobalTerm();
821
822	return rc;
823	}
824
825
826	/**
827	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
828	* VT-x on a CPU.
829	*
830	* @param idCpu The identifier for the CPU the function is called on.
831	* @param pvUser1 Pointer to the first RC structure.
832	* @param pvUser2 Ignored.
833	*/
834	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
835	{
836	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
837	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
838	NOREF(pvUser2);
839
840	/*
841	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
842	* Once the lock bit is set, this MSR can no longer be modified.
843	*/
844	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
845	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
846	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
847	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
848	)
849	{
850	/* MSR is not yet locked; we can change it ourselves here. */
851	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
852	g_HvmR0.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
853	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
854	}
855
856	int rc;
857	if ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
858	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
859	rc = VINF_SUCCESS;
860	else
861	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
862
863	hmR0FirstRcSetStatus(pFirstRc, rc);
864	}
865
866
867	/**
868	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
869	* on a CPU.
870	*
871	* @param idCpu The identifier for the CPU the function is called on.
872	* @param pvUser1 Pointer to the first RC structure.
873	* @param pvUser2 Ignored.
874	*/
875	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
876	{
877	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
878	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
879	NOREF(pvUser2);
880
881	/* Check if SVM is disabled. */
882	int rc;
883	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
884	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
885	{
886	/* Turn on SVM in the EFER MSR. */
887	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
888	if (fEfer & MSR_K6_EFER_SVME)
889	rc = VERR_SVM_IN_USE;
890	else
891	{
892	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
893
894	/* Paranoia. */
895	fEfer = ASMRdMsr(MSR_K6_EFER);
896	if (fEfer & MSR_K6_EFER_SVME)
897	{
898	/* Restore previous value. */
899	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
900	rc = VINF_SUCCESS;
901	}
902	else
903	rc = VERR_SVM_ILLEGAL_EFER_MSR;
904	}
905	}
906	else
907	rc = VERR_SVM_DISABLED;
908
909	hmR0FirstRcSetStatus(pFirstRc, rc);
910	}
911
912
913	/**
914	* Enable VT-x or AMD-V on the current CPU
915	*
916	* @returns VBox status code.
917	* @param pVM Pointer to the VM (can be 0).
918	* @param idCpu The identifier for the CPU the function is called on.
919	*/
920	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
921	{
922	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
923
924	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
925	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
926	Assert(!pCpu->fConfigured);
927
928	pCpu->idCpu = idCpu;
929	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
930	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
931
932	int rc;
933	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
934	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL, NIL_RTHCPHYS, true);
935	else
936	{
937	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
938	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
939	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
940	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
941	}
942	AssertRC(rc);
943	if (RT_SUCCESS(rc))
944	pCpu->fConfigured = true;
945
946	return rc;
947	}
948
949
950	/**
951	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
952	* is to be called on the target cpus.
953	*
954	* @param idCpu The identifier for the CPU the function is called on.
955	* @param pvUser1 The 1st user argument.
956	* @param pvUser2 The 2nd user argument.
957	*/
958	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
959	{
960	PVM pVM = (PVM)pvUser1; /* can be NULL! */
961	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
962	AssertReturnVoid(g_HvmR0.fGlobalInit);
963	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
964	}
965
966
967	/**
968	* RTOnce callback employed by HMR0EnableAllCpus.
969	*
970	* @returns VBox status code.
971	* @param pvUser Pointer to the VM.
972	* @param pvUserIgnore NULL, ignored.
973	*/
974	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
975	{
976	PVM pVM = (PVM)pvUser;
977
978	/*
979	* Indicate that we've initialized.
980	*
981	* Note! There is a potential race between this function and the suspend
982	* notification. Kind of unlikely though, so ignored for now.
983	*/
984	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
985	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
986
987	/*
988	* The global init variable is set by the first VM.
989	*/
990	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
991
992	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
993	{
994	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
995	g_HvmR0.aCpuInfo[i].fConfigured = false;
996	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
997	g_HvmR0.aCpuInfo[i].uCurrentAsid = 0;
998	}
999
1000	int rc;
1001	if ( g_HvmR0.vmx.fSupported
1002	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1003	{
1004	/*
1005	* Global VT-x initialization API (only darwin for now).
1006	*/
1007	rc = SUPR0EnableVTx(true /* fEnable */);
1008	if (RT_SUCCESS(rc))
1009	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
1010	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
1011	else
1012	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
1013	}
1014	else
1015	{
1016	/*
1017	* We're doing the job ourselves.
1018	*/
1019	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
1020	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1021	{
1022	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1023
1024	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1025	{
1026	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1027	AssertLogRelRCReturn(rc, rc);
1028
1029	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1030	ASMMemZeroPage(pvR0);
1031	}
1032	}
1033
1034	rc = VINF_SUCCESS;
1035	}
1036
1037	if ( RT_SUCCESS(rc)
1038	&& g_HvmR0.fGlobalInit)
1039	{
1040	/* First time, so initialize each cpu/core. */
1041	HMR0FIRSTRC FirstRc;
1042	hmR0FirstRcInit(&FirstRc);
1043	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1044	if (RT_SUCCESS(rc))
1045	rc = hmR0FirstRcGetStatus(&FirstRc);
1046	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1047	}
1048
1049	return rc;
1050	}
1051
1052
1053	/**
1054	* Sets up HM on all cpus.
1055	*
1056	* @returns VBox status code.
1057	* @param pVM Pointer to the VM.
1058	*/
1059	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1060	{
1061	/* Make sure we don't touch HM after we've disabled HM in
1062	preparation of a suspend. */
1063	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1064	return VERR_HM_SUSPEND_PENDING;
1065
1066	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1067	}
1068
1069
1070	/**
1071	* Disable VT-x or AMD-V on the current CPU.
1072	*
1073	* @returns VBox status code.
1074	* @param idCpu The identifier for the CPU the function is called on.
1075	*/
1076	static int hmR0DisableCpu(RTCPUID idCpu)
1077	{
1078	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1079
1080	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1081	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1082	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1083	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1084
1085	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1086	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1087
1088	int rc;
1089	if (pCpu->fConfigured)
1090	{
1091	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1092	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1093	if (idCpu == RTMpCpuId())
1094	{
1095	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1096	AssertRC(rc);
1097	}
1098	else
1099	{
1100	pCpu->fIgnoreAMDVInUseError = true;
1101	rc = VINF_SUCCESS;
1102	}
1103
1104	pCpu->fConfigured = false;
1105	}
1106	else
1107	rc = VINF_SUCCESS; /* nothing to do */
1108
1109	pCpu->uCurrentAsid = 0;
1110	return rc;
1111	}
1112
1113
1114	/**
1115	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1116	* is to be called on the target cpus.
1117	*
1118	* @param idCpu The identifier for the CPU the function is called on.
1119	* @param pvUser1 The 1st user argument.
1120	* @param pvUser2 The 2nd user argument.
1121	*/
1122	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1123	{
1124	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1125	AssertReturnVoid(g_HvmR0.fGlobalInit);
1126	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1127	}
1128
1129
1130	/**
1131	* Callback function invoked when a cpu goes online or offline.
1132	*
1133	* @param enmEvent The Mp event.
1134	* @param idCpu The identifier for the CPU the function is called on.
1135	* @param pvData Opaque data (PVM pointer).
1136	*/
1137	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1138	{
1139	NOREF(pvData);
1140
1141	/*
1142	* We only care about uninitializing a CPU that is going offline. When a
1143	* CPU comes online, the initialization is done lazily in HMR0Enter().
1144	*/
1145	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1146	switch (enmEvent)
1147	{
1148	case RTMPEVENT_OFFLINE:
1149	{
1150	int rc = hmR0DisableCpu(idCpu);
1151	AssertRC(rc);
1152	break;
1153	}
1154
1155	default:
1156	break;
1157	}
1158	}
1159
1160
1161	/**
1162	* Called whenever a system power state change occurs.
1163	*
1164	* @param enmEvent The Power event.
1165	* @param pvUser User argument.
1166	*/
1167	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1168	{
1169	NOREF(pvUser);
1170	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1171
1172	#ifdef LOG_ENABLED
1173	if (enmEvent == RTPOWEREVENT_SUSPEND)
1174	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1175	else
1176	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1177	#endif
1178
1179	if (enmEvent == RTPOWEREVENT_SUSPEND)
1180	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1181
1182	if (g_HvmR0.fEnabled)
1183	{
1184	int rc;
1185	HMR0FIRSTRC FirstRc;
1186	hmR0FirstRcInit(&FirstRc);
1187
1188	if (enmEvent == RTPOWEREVENT_SUSPEND)
1189	{
1190	if (g_HvmR0.fGlobalInit)
1191	{
1192	/* Turn off VT-x or AMD-V on all CPUs. */
1193	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
1194	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1195	}
1196	/* else nothing to do here for the local init case */
1197	}
1198	else
1199	{
1200	/* Reinit the CPUs from scratch as the suspend state might have
1201	messed with the MSRs. (lousy BIOSes as usual) */
1202	if (g_HvmR0.vmx.fSupported)
1203	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1204	else
1205	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1206	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1207	if (RT_SUCCESS(rc))
1208	rc = hmR0FirstRcGetStatus(&FirstRc);
1209	#ifdef LOG_ENABLED
1210	if (RT_FAILURE(rc))
1211	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1212	#endif
1213	if (g_HvmR0.fGlobalInit)
1214	{
1215	/* Turn VT-x or AMD-V back on on all CPUs. */
1216	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
1217	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1218	}
1219	/* else nothing to do here for the local init case */
1220	}
1221	}
1222
1223	if (enmEvent == RTPOWEREVENT_RESUME)
1224	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1225	}
1226
1227
1228	/**
1229	* Does Ring-0 per VM HM initialization.
1230	*
1231	* This will copy HM global into the VM structure and call the CPU specific
1232	* init routine which will allocate resources for each virtual CPU and such.
1233	*
1234	* @returns VBox status code.
1235	* @param pVM Pointer to the VM.
1236	*/
1237	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1238	{
1239	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1240
1241	#ifdef LOG_ENABLED
1242	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1243	#endif
1244
1245	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1246	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1247	return VERR_HM_SUSPEND_PENDING;
1248
1249	/*
1250	* Copy globals to the VM structure.
1251	*/
1252	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1253	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1254
1255	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1256	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1257	pVM->hm.s.vmx.msr.feature_ctrl = g_HvmR0.vmx.msr.feature_ctrl;
1258	pVM->hm.s.vmx.hostCR4 = g_HvmR0.vmx.hostCR4;
1259	pVM->hm.s.vmx.hostEFER = g_HvmR0.vmx.hostEFER;
1260	pVM->hm.s.vmx.msr.vmx_basic_info = g_HvmR0.vmx.msr.vmx_basic_info;
1261	pVM->hm.s.vmx.msr.vmx_pin_ctls = g_HvmR0.vmx.msr.vmx_pin_ctls;
1262	pVM->hm.s.vmx.msr.vmx_proc_ctls = g_HvmR0.vmx.msr.vmx_proc_ctls;
1263	pVM->hm.s.vmx.msr.vmx_proc_ctls2 = g_HvmR0.vmx.msr.vmx_proc_ctls2;
1264	pVM->hm.s.vmx.msr.vmx_exit = g_HvmR0.vmx.msr.vmx_exit;
1265	pVM->hm.s.vmx.msr.vmx_entry = g_HvmR0.vmx.msr.vmx_entry;
1266	pVM->hm.s.vmx.msr.vmx_misc = g_HvmR0.vmx.msr.vmx_misc;
1267	pVM->hm.s.vmx.msr.vmx_cr0_fixed0 = g_HvmR0.vmx.msr.vmx_cr0_fixed0;
1268	pVM->hm.s.vmx.msr.vmx_cr0_fixed1 = g_HvmR0.vmx.msr.vmx_cr0_fixed1;
1269	pVM->hm.s.vmx.msr.vmx_cr4_fixed0 = g_HvmR0.vmx.msr.vmx_cr4_fixed0;
1270	pVM->hm.s.vmx.msr.vmx_cr4_fixed1 = g_HvmR0.vmx.msr.vmx_cr4_fixed1;
1271	pVM->hm.s.vmx.msr.vmx_vmcs_enum = g_HvmR0.vmx.msr.vmx_vmcs_enum;
1272	pVM->hm.s.vmx.msr.vmx_vmfunc = g_HvmR0.vmx.msr.vmx_vmfunc;
1273	pVM->hm.s.vmx.msr.vmx_ept_vpid_caps = g_HvmR0.vmx.msr.vmx_ept_vpid_caps;
1274	pVM->hm.s.svm.msrHwcr = g_HvmR0.svm.msrHwcr;
1275	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1276	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1277	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1278	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1279	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1280
1281	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1282
1283
1284	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1285	{
1286	pVM->hm.s.cMaxResumeLoops = 1024;
1287	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1288	if (RTThreadPreemptIsPendingTrusty())
1289	pVM->hm.s.cMaxResumeLoops = 8192;
1290	#endif
1291	}
1292
1293	/*
1294	* Initialize some per CPU fields.
1295	*/
1296	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1297	{
1298	PVMCPU pVCpu = &pVM->aCpus[i];
1299
1300	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1301
1302	/* Invalidate the last cpu we were running on. */
1303	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1304
1305	/* We'll aways increment this the first time (host uses ASID 0) */
1306	pVCpu->hm.s.uCurrentAsid = 0;
1307	}
1308
1309	/*
1310	* Call the hardware specific initialization method.
1311	*/
1312	RTCCUINTREG fFlags = ASMIntDisableFlags();
1313	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1314	ASMSetFlags(fFlags);
1315
1316	int rc = g_HvmR0.pfnInitVM(pVM);
1317	return rc;
1318	}
1319
1320
1321	/**
1322	* Does Ring-0 per VM HM termination.
1323	*
1324	* @returns VBox status code.
1325	* @param pVM Pointer to the VM.
1326	*/
1327	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1328	{
1329	Log(("HMR0TermVM: %p\n", pVM));
1330	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1331
1332	/* Make sure we don't touch HM after we've disabled HM in preparation
1333	of a suspend. */
1334	/** @todo r=bird: This cannot be right, the termination functions are
1335	* just freeing memory and resetting pVM/pVCpu members...
1336	* ==> memory leak. */
1337	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1338
1339	/*
1340	* Call the hardware specific method.
1341	*/
1342	RTCCUINTREG fFlags = ASMIntDisableFlags();
1343	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1344	ASMSetFlags(fFlags);
1345
1346	int rc = g_HvmR0.pfnTermVM(pVM);
1347	return rc;
1348	}
1349
1350
1351	/**
1352	* Sets up a VT-x or AMD-V session.
1353	*
1354	* This is mostly about setting up the hardware VM state.
1355	*
1356	* @returns VBox status code.
1357	* @param pVM Pointer to the VM.
1358	*/
1359	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1360	{
1361	Log(("HMR0SetupVM: %p\n", pVM));
1362	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1363
1364	/* Make sure we don't touch HM after we've disabled HM in
1365	preparation of a suspend. */
1366	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1367
1368	/*
1369	* Call the hardware specific setup VM method. This requires the CPU to be
1370	* enabled for AMD-V/VT-x and preemption to be prevented.
1371	*/
1372	RTCCUINTREG fFlags = ASMIntDisableFlags();
1373	RTCPUID idCpu = RTMpCpuId();
1374	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1375
1376	/* On first entry we'll sync everything. */
1377	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1378	pVM->aCpus[i].hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1379
1380	/* Enable VT-x or AMD-V if local init is required. */
1381	int rc;
1382	if (!g_HvmR0.fGlobalInit)
1383	{
1384	rc = hmR0EnableCpu(pVM, idCpu);
1385	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1386	}
1387
1388	/* Setup VT-x or AMD-V. */
1389	rc = g_HvmR0.pfnSetupVM(pVM);
1390
1391	/* Disable VT-x or AMD-V if local init was done before. */
1392	if (!g_HvmR0.fGlobalInit)
1393	{
1394	int rc2 = hmR0DisableCpu(idCpu);
1395	AssertRC(rc2);
1396	}
1397
1398	ASMSetFlags(fFlags);
1399	return rc;
1400	}
1401
1402
1403	/**
1404	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1405	* required for entering HM context.
1406	*
1407	* @returns VBox status code.
1408	* @param pvCpu Pointer to the VMCPU.
1409	*
1410	* @remarks No-long-jump zone!!!
1411	*/
1412	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1413	{
1414	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1415
1416	int rc = VINF_SUCCESS;
1417	RTCPUID idCpu = RTMpCpuId();
1418	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1419	AssertPtr(pCpu);
1420
1421	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1422	if (!pCpu->fConfigured)
1423	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1424
1425	/* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
1426	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE;
1427	pVCpu->hm.s.idEnteredCpu = idCpu;
1428	return rc;
1429	}
1430
1431
1432	/**
1433	* Enters the VT-x or AMD-V session.
1434	*
1435	* @returns VBox status code.
1436	* @param pVM Pointer to the VM.
1437	* @param pVCpu Pointer to the VMCPU.
1438	*
1439	* @remarks This is called with preemption disabled.
1440	*/
1441	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1442	{
1443	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1444	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1445	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1446
1447	/* Load the bare minimum state required for entering HM. */
1448	int rc = HMR0EnterCpu(pVCpu);
1449	AssertRCReturn(rc, rc);
1450
1451	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1452	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1453	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1454	#endif
1455
1456	RTCPUID idCpu = RTMpCpuId();
1457	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1458	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1459	Assert(pCpu);
1460	Assert(pCtx);
1461	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1462
1463	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1464	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1465
1466	/* Load the host as we may be resuming code after a longjmp and quite
1467	possibly be scheduled on a different CPU. */
1468	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1469	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1470
1471	/** @todo This is not needed to be done here anymore, can fix/optimize later. */
1472	rc = g_HvmR0.pfnLoadGuestState(pVM, pVCpu, pCtx);
1473	AssertMsgRCReturn(rc, ("pfnLoadGuestState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1474
1475	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1476	if (fStartedSet)
1477	PGMRZDynMapReleaseAutoSet(pVCpu);
1478	#endif
1479
1480	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1481	and ring-3 calls. */
1482	if (RT_FAILURE(rc))
1483	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1484	return rc;
1485	}
1486
1487
1488	/**
1489	* Deinitializes the bare minimum state used for HM context and if necessary
1490	* disable HM on the CPU.
1491	*
1492	* @returns VBox status code.
1493	* @param pVCpu Pointer to the VMCPU.
1494	*
1495	* @remarks No-long-jump zone!!!
1496	*/
1497	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1498	{
1499	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1500
1501	RTCPUID idCpu = RTMpCpuId();
1502	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1503
1504	if ( !g_HvmR0.fGlobalInit
1505	&& pCpu->fConfigured)
1506	{
1507	int rc = hmR0DisableCpu(idCpu);
1508	AssertRCReturn(rc, rc);
1509	Assert(!pCpu->fConfigured);
1510	}
1511
1512	/* Reset these to force a TLB flush for the next entry. */
1513	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1514	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1515	pVCpu->hm.s.uCurrentAsid = 0;
1516	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1517
1518	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1519	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1520
1521	return VINF_SUCCESS;
1522	}
1523
1524
1525	/**
1526	* Leaves the VT-x or AMD-V session.
1527	*
1528	* @returns VBox status code.
1529	* @param pVM Pointer to the VM.
1530	* @param pVCpu Pointer to the VMCPU.
1531	*
1532	* @remarks Called with preemption disabled just like HMR0Enter, our
1533	* counterpart.
1534	*/
1535	VMMR0_INT_DECL(int) HMR0Leave(PVM pVM, PVMCPU pVCpu)
1536	{
1537	/* Nothing to do currently. Taken care of HMR0LeaveCpu() and in hmR0VmxLeaveSession() and hmR0SvmLeaveSession(). */
1538	/** @todo refactor later to more common code. */
1539	return VINF_SUCCESS;
1540	}
1541
1542
1543	/**
1544	* Thread-context hook for HM.
1545	*
1546	* @param enmEvent The thread-context event.
1547	* @param pvUser Opaque pointer to the VMCPU.
1548	*/
1549	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1550	{
1551	PVMCPU pVCpu = (PVMCPU)pvUser;
1552	Assert(pVCpu);
1553	Assert(g_HvmR0.pfnThreadCtxCallback);
1554
1555	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1556	}
1557
1558
1559	/**
1560	* Runs guest code in a hardware accelerated VM.
1561	*
1562	* @returns VBox status code.
1563	* @param pVM Pointer to the VM.
1564	* @param pVCpu Pointer to the VMCPU.
1565	*
1566	* @remarks Called with preemption disabled and after first having called
1567	* HMR0Enter.
1568	*/
1569	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1570	{
1571	#ifdef VBOX_STRICT
1572	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1573	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1574	Assert(pCpu->fConfigured);
1575	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1576	#endif
1577
1578	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1579	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1580	PGMRZDynMapStartAutoSet(pVCpu);
1581	#endif
1582
1583	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1584
1585	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1586	PGMRZDynMapReleaseAutoSet(pVCpu);
1587	#endif
1588	return rc;
1589	}
1590
1591	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1592
1593	/**
1594	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1595	*
1596	* @returns VBox status code.
1597	* @param pVM Pointer to the VM.
1598	* @param pVCpu Pointer to the VMCPU.
1599	* @param pCtx Pointer to the guest CPU context.
1600	*/
1601	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1602	{
1603	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1604	if (pVM->hm.s.vmx.fSupported)
1605	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1606	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1607	}
1608
1609
1610	/**
1611	* Save guest debug state (64 bits guest mode & 32 bits host only)
1612	*
1613	* @returns VBox status code.
1614	* @param pVM Pointer to the VM.
1615	* @param pVCpu Pointer to the VMCPU.
1616	* @param pCtx Pointer to the guest CPU context.
1617	*/
1618	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1619	{
1620	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1621	if (pVM->hm.s.vmx.fSupported)
1622	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1623	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1624	}
1625
1626
1627	/**
1628	* Test the 32->64 bits switcher.
1629	*
1630	* @returns VBox status code.
1631	* @param pVM Pointer to the VM.
1632	*/
1633	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1634	{
1635	PVMCPU pVCpu = &pVM->aCpus[0];
1636	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1637	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1638	int rc;
1639
1640	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1641	if (pVM->hm.s.vmx.fSupported)
1642	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1643	else
1644	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1645	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1646
1647	return rc;
1648	}
1649
1650	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1651
1652	/**
1653	* Returns suspend status of the host.
1654	*
1655	* @returns Suspend pending or not.
1656	*/
1657	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1658	{
1659	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1660	}
1661
1662
1663	/**
1664	* Returns the cpu structure for the current cpu.
1665	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1666	*
1667	* @returns The cpu structure pointer.
1668	*/
1669	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1670	{
1671	RTCPUID idCpu = RTMpCpuId();
1672	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1673	return &g_HvmR0.aCpuInfo[idCpu];
1674	}
1675
1676
1677	/**
1678	* Returns the cpu structure for the current cpu.
1679	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1680	*
1681	* @returns The cpu structure pointer.
1682	* @param idCpu id of the VCPU.
1683	*/
1684	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1685	{
1686	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1687	return &g_HvmR0.aCpuInfo[idCpu];
1688	}
1689
1690
1691	/**
1692	* Save a pending IO read.
1693	*
1694	* @param pVCpu Pointer to the VMCPU.
1695	* @param GCPtrRip Address of IO instruction.
1696	* @param GCPtrRipNext Address of the next instruction.
1697	* @param uPort Port address.
1698	* @param uAndVal AND mask for saving the result in eax.
1699	* @param cbSize Read size.
1700	*/
1701	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1702	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1703	{
1704	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1705	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1706	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1707	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1708	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1709	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1710	return;
1711	}
1712
1713
1714	/**
1715	* Save a pending IO write.
1716	*
1717	* @param pVCpu Pointer to the VMCPU.
1718	* @param GCPtrRIP Address of IO instruction.
1719	* @param uPort Port address.
1720	* @param uAndVal AND mask for fetching the result from eax.
1721	* @param cbSize Read size.
1722	*/
1723	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1724	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1725	{
1726	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1727	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1728	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1729	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1730	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1731	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1732	return;
1733	}
1734
1735
1736	/**
1737	* Raw-mode switcher hook - disable VT-x if it's active and the current
1738	* switcher turns off paging.
1739	*
1740	* @returns VBox status code.
1741	* @param pVM Pointer to the VM.
1742	* @param enmSwitcher The switcher we're about to use.
1743	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1744	*/
1745	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1746	{
1747	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1748
1749	*pfVTxDisabled = false;
1750
1751	/* No such issues with AMD-V */
1752	if (!g_HvmR0.vmx.fSupported)
1753	return VINF_SUCCESS;
1754
1755	/* Check if the swithcing we're up to is safe. */
1756	switch (enmSwitcher)
1757	{
1758	case VMMSWITCHER_32_TO_32:
1759	case VMMSWITCHER_PAE_TO_PAE:
1760	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1761
1762	case VMMSWITCHER_32_TO_PAE:
1763	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1764	case VMMSWITCHER_AMD64_TO_32:
1765	case VMMSWITCHER_AMD64_TO_PAE:
1766	break; /* unsafe switchers */
1767
1768	default:
1769	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1770	}
1771
1772	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1773	regardless of whether we're currently using VT-x or not. */
1774	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1775	{
1776	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1777	return VINF_SUCCESS;
1778	}
1779
1780	/** @todo Check if this code is presumtive wrt other VT-x users on the
1781	* system... */
1782
1783	/* Nothing to do if we haven't enabled VT-x. */
1784	if (!g_HvmR0.fEnabled)
1785	return VINF_SUCCESS;
1786
1787	/* Local init implies the CPU is currently not in VMX root mode. */
1788	if (!g_HvmR0.fGlobalInit)
1789	return VINF_SUCCESS;
1790
1791	/* Ok, disable VT-x. */
1792	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1793	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1794
1795	*pfVTxDisabled = true;
1796	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1797	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1798	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1799	}
1800
1801
1802	/**
1803	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1804	* switcher turned off paging.
1805	*
1806	* @param pVM Pointer to the VM.
1807	* @param fVTxDisabled Whether VT-x was disabled or not.
1808	*/
1809	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1810	{
1811	Assert(!(ASMGetFlags() & X86_EFL_IF));
1812
1813	if (!fVTxDisabled)
1814	return; /* nothing to do */
1815
1816	Assert(g_HvmR0.vmx.fSupported);
1817	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1818	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1819	else
1820	{
1821	Assert(g_HvmR0.fEnabled);
1822	Assert(g_HvmR0.fGlobalInit);
1823
1824	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1825	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1826
1827	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1828	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1829	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
1830	}
1831	}
1832
1833	#ifdef VBOX_STRICT
1834
1835	/**
1836	* Dumps a descriptor.
1837	*
1838	* @param pDesc Descriptor to dump.
1839	* @param Sel Selector number.
1840	* @param pszMsg Message to prepend the log entry with.
1841	*/
1842	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1843	{
1844	/*
1845	* Make variable description string.
1846	*/
1847	static struct
1848	{
1849	unsigned cch;
1850	const char *psz;
1851	} const s_aTypes[32] =
1852	{
1853	# define STRENTRY(str) { sizeof(str) - 1, str }
1854
1855	/* system */
1856	# if HC_ARCH_BITS == 64
1857	STRENTRY("Reserved0 "), /* 0x00 */
1858	STRENTRY("Reserved1 "), /* 0x01 */
1859	STRENTRY("LDT "), /* 0x02 */
1860	STRENTRY("Reserved3 "), /* 0x03 */
1861	STRENTRY("Reserved4 "), /* 0x04 */
1862	STRENTRY("Reserved5 "), /* 0x05 */
1863	STRENTRY("Reserved6 "), /* 0x06 */
1864	STRENTRY("Reserved7 "), /* 0x07 */
1865	STRENTRY("Reserved8 "), /* 0x08 */
1866	STRENTRY("TSS64Avail "), /* 0x09 */
1867	STRENTRY("ReservedA "), /* 0x0a */
1868	STRENTRY("TSS64Busy "), /* 0x0b */
1869	STRENTRY("Call64 "), /* 0x0c */
1870	STRENTRY("ReservedD "), /* 0x0d */
1871	STRENTRY("Int64 "), /* 0x0e */
1872	STRENTRY("Trap64 "), /* 0x0f */
1873	# else
1874	STRENTRY("Reserved0 "), /* 0x00 */
1875	STRENTRY("TSS16Avail "), /* 0x01 */
1876	STRENTRY("LDT "), /* 0x02 */
1877	STRENTRY("TSS16Busy "), /* 0x03 */
1878	STRENTRY("Call16 "), /* 0x04 */
1879	STRENTRY("Task "), /* 0x05 */
1880	STRENTRY("Int16 "), /* 0x06 */
1881	STRENTRY("Trap16 "), /* 0x07 */
1882	STRENTRY("Reserved8 "), /* 0x08 */
1883	STRENTRY("TSS32Avail "), /* 0x09 */
1884	STRENTRY("ReservedA "), /* 0x0a */
1885	STRENTRY("TSS32Busy "), /* 0x0b */
1886	STRENTRY("Call32 "), /* 0x0c */
1887	STRENTRY("ReservedD "), /* 0x0d */
1888	STRENTRY("Int32 "), /* 0x0e */
1889	STRENTRY("Trap32 "), /* 0x0f */
1890	# endif
1891	/* non system */
1892	STRENTRY("DataRO "), /* 0x10 */
1893	STRENTRY("DataRO Accessed "), /* 0x11 */
1894	STRENTRY("DataRW "), /* 0x12 */
1895	STRENTRY("DataRW Accessed "), /* 0x13 */
1896	STRENTRY("DataDownRO "), /* 0x14 */
1897	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1898	STRENTRY("DataDownRW "), /* 0x16 */
1899	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1900	STRENTRY("CodeEO "), /* 0x18 */
1901	STRENTRY("CodeEO Accessed "), /* 0x19 */
1902	STRENTRY("CodeER "), /* 0x1a */
1903	STRENTRY("CodeER Accessed "), /* 0x1b */
1904	STRENTRY("CodeConfEO "), /* 0x1c */
1905	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1906	STRENTRY("CodeConfER "), /* 0x1e */
1907	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1908	# undef SYSENTRY
1909	};
1910	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1911	char szMsg[128];
1912	char *psz = &szMsg[0];
1913	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1914	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1915	psz += s_aTypes[i].cch;
1916
1917	if (pDesc->Gen.u1Present)
1918	ADD_STR(psz, "Present ");
1919	else
1920	ADD_STR(psz, "Not-Present ");
1921	# if HC_ARCH_BITS == 64
1922	if (pDesc->Gen.u1Long)
1923	ADD_STR(psz, "64-bit ");
1924	else
1925	ADD_STR(psz, "Comp ");
1926	# else
1927	if (pDesc->Gen.u1Granularity)
1928	ADD_STR(psz, "Page ");
1929	if (pDesc->Gen.u1DefBig)
1930	ADD_STR(psz, "32-bit ");
1931	else
1932	ADD_STR(psz, "16-bit ");
1933	# endif
1934	# undef ADD_STR
1935	*psz = '\0';
1936
1937	/*
1938	* Limit and Base and format the output.
1939	*/
1940	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1941
1942	# if HC_ARCH_BITS == 64
1943	uint64_t u32Base = X86DESC64_BASE(pDesc);
1944
1945	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1946	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1947	# else
1948	uint32_t u32Base = X86DESC_BASE(pDesc);
1949
1950	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1951	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1952	# endif
1953	}
1954
1955
1956	/**
1957	* Formats a full register dump.
1958	*
1959	* @param pVM Pointer to the VM.
1960	* @param pVCpu Pointer to the VMCPU.
1961	* @param pCtx Pointer to the CPU context.
1962	*/
1963	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1964	{
1965	NOREF(pVM);
1966
1967	/*
1968	* Format the flags.
1969	*/
1970	static struct
1971	{
1972	const char pszSet; const char pszClear; uint32_t fFlag;
1973	} const s_aFlags[] =
1974	{
1975	{ "vip",NULL, X86_EFL_VIP },
1976	{ "vif",NULL, X86_EFL_VIF },
1977	{ "ac", NULL, X86_EFL_AC },
1978	{ "vm", NULL, X86_EFL_VM },
1979	{ "rf", NULL, X86_EFL_RF },
1980	{ "nt", NULL, X86_EFL_NT },
1981	{ "ov", "nv", X86_EFL_OF },
1982	{ "dn", "up", X86_EFL_DF },
1983	{ "ei", "di", X86_EFL_IF },
1984	{ "tf", NULL, X86_EFL_TF },
1985	{ "nt", "pl", X86_EFL_SF },
1986	{ "nz", "zr", X86_EFL_ZF },
1987	{ "ac", "na", X86_EFL_AF },
1988	{ "po", "pe", X86_EFL_PF },
1989	{ "cy", "nc", X86_EFL_CF },
1990	};
1991	char szEFlags[80];
1992	char *psz = szEFlags;
1993	uint32_t efl = pCtx->eflags.u32;
1994	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1995	{
1996	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1997	if (pszAdd)
1998	{
1999	strcpy(psz, pszAdd);
2000	psz += strlen(pszAdd);
2001	*psz++ = ' ';
2002	}
2003	}
2004	psz[-1] = '\0';
2005
2006
2007	/*
2008	* Format the registers.
2009	*/
2010	if (CPUMIsGuestIn64BitCode(pVCpu))
2011	{
2012	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
2013	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
2014	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2015	"r14=%016RX64 r15=%016RX64\n"
2016	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
2017	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2018	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2019	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2020	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2021	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2022	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2023	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
2024	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
2025	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
2026	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2027	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2028	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2029	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2030	,
2031	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
2032	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
2033	pCtx->r14, pCtx->r15,
2034	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2035	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2036	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2037	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2038	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2039	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2040	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2041	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
2042	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
2043	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2044	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2045	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2046	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2047	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2048	}
2049	else
2050	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2051	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2052	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2053	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2054	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2055	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2056	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2057	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2058	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2059	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2060	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2061	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2062	,
2063	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2064	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2065	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2066	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2067	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2068	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2069	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2070	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2071	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2072	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2073	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2074	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2075
2076	Log(("FPU:\n"
2077	"FCW=%04x FSW=%04x FTW=%02x\n"
2078	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2079	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2080	,
2081	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2082	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2083	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2084	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2085
2086
2087	Log(("MSR:\n"
2088	"EFER =%016RX64\n"
2089	"PAT =%016RX64\n"
2090	"STAR =%016RX64\n"
2091	"CSTAR =%016RX64\n"
2092	"LSTAR =%016RX64\n"
2093	"SFMASK =%016RX64\n"
2094	"KERNELGSBASE =%016RX64\n",
2095	pCtx->msrEFER,
2096	pCtx->msrPAT,
2097	pCtx->msrSTAR,
2098	pCtx->msrCSTAR,
2099	pCtx->msrLSTAR,
2100	pCtx->msrSFMASK,
2101	pCtx->msrKERNELGSBASE));
2102
2103	}
2104
2105	#endif /* VBOX_STRICT */
2106

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 48130

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