HMR0.cpp@ 48140

Last change on this file since 48140 was 48135, checked in by vboxsync, 12 years ago
VMM/HM: Eliminate dead code paths.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 74.0 KB

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1	/* $Id: HMR0.cpp 48135 2013-08-28 18:04:49Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94	bool fEnabledByHost));
95	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
96	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
99	/** @} */
100
101	/** Maximum ASID allowed. */
102	uint32_t uMaxAsid;
103
104	/** VT-x data. */
105	struct
106	{
107	/** Set to by us to indicate VMX is supported by the CPU. */
108	bool fSupported;
109	/** Whether we're using SUPR0EnableVTx or not. */
110	bool fUsingSUPR0EnableVTx;
111	/** Whether we're using the preemption timer or not. */
112	bool fUsePreemptTimer;
113	/** The shift mask employed by the VMX-Preemption timer. */
114	uint8_t cPreemptTimerShift;
115
116	/** Host CR4 value (set by ring-0 VMX init) */
117	uint64_t hostCR4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t hostEFER;
121
122	/** VMX MSR values */
123	struct
124	{
125	uint64_t feature_ctrl;
126	uint64_t vmx_basic_info;
127	VMX_CAPABILITY vmx_pin_ctls;
128	VMX_CAPABILITY vmx_proc_ctls;
129	VMX_CAPABILITY vmx_proc_ctls2;
130	VMX_CAPABILITY vmx_exit;
131	VMX_CAPABILITY vmx_entry;
132	uint64_t vmx_misc;
133	uint64_t vmx_cr0_fixed0;
134	uint64_t vmx_cr0_fixed1;
135	uint64_t vmx_cr4_fixed0;
136	uint64_t vmx_cr4_fixed1;
137	uint64_t vmx_vmcs_enum;
138	uint64_t vmx_vmfunc;
139	uint64_t vmx_ept_vpid_caps;
140	} msr;
141	/* Last instruction error */
142	uint32_t ulLastInstrError;
143	} vmx;
144
145	/** AMD-V information. */
146	struct
147	{
148	/* HWCR MSR (for diagnostics) */
149	uint64_t msrHwcr;
150
151	/** SVM revision. */
152	uint32_t u32Rev;
153
154	/** SVM feature bits from cpuid 0x8000000a */
155	uint32_t u32Features;
156
157	/** Set by us to indicate SVM is supported by the CPU. */
158	bool fSupported;
159	} svm;
160	/** Saved error from detection */
161	int32_t lLastError;
162
163	struct
164	{
165	uint32_t u32AMDFeatureECX;
166	uint32_t u32AMDFeatureEDX;
167	} cpuid;
168
169	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
170	* enabled and disabled each time it's used to execute guest code. */
171	bool fGlobalInit;
172	/** Indicates whether the host is suspending or not. We'll refuse a few
173	* actions when the host is being suspended to speed up the suspending and
174	* avoid trouble. */
175	volatile bool fSuspended;
176
177	/** Whether we've already initialized all CPUs.
178	* @remarks We could check the EnableAllCpusOnce state, but this is
179	* simpler and hopefully easier to understand. */
180	bool fEnabled;
181	/** Serialize initialization in HMR0EnableAllCpus. */
182	RTONCE EnableAllCpusOnce;
183	} g_HvmR0;
184
185
186
187	/**
188	* Initializes a first return code structure.
189	*
190	* @param pFirstRc The structure to init.
191	*/
192	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
193	{
194	pFirstRc->rc = VINF_SUCCESS;
195	pFirstRc->idCpu = NIL_RTCPUID;
196	}
197
198
199	/**
200	* Try set the status code (success ignored).
201	*
202	* @param pFirstRc The first return code structure.
203	* @param rc The status code.
204	*/
205	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
206	{
207	if ( RT_FAILURE(rc)
208	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
209	pFirstRc->idCpu = RTMpCpuId();
210	}
211
212
213	/**
214	* Get the status code of a first return code structure.
215	*
216	* @returns The status code; VINF_SUCCESS or error status, no informational or
217	* warning errors.
218	* @param pFirstRc The first return code structure.
219	*/
220	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
221	{
222	return pFirstRc->rc;
223	}
224
225
226	#ifdef VBOX_STRICT
227	/**
228	* Get the CPU ID on which the failure status code was reported.
229	*
230	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
231	* @param pFirstRc The first return code structure.
232	*/
233	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
234	{
235	return pFirstRc->idCpu;
236	}
237	#endif /* VBOX_STRICT */
238
239
240	/** @name Dummy callback handlers.
241	* @{ */
242
243	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
244	{
245	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
246	return VINF_SUCCESS;
247	}
248
249	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
250	{
251	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
252	return VINF_SUCCESS;
253	}
254
255	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
256	{
257	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
258	}
259
260	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
261	bool fEnabledBySystem)
262	{
263	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem);
264	return VINF_SUCCESS;
265	}
266
267	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
268	{
269	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
270	return VINF_SUCCESS;
271	}
272
273	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
274	{
275	NOREF(pVM);
276	return VINF_SUCCESS;
277	}
278
279	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
280	{
281	NOREF(pVM);
282	return VINF_SUCCESS;
283	}
284
285	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
286	{
287	NOREF(pVM);
288	return VINF_SUCCESS;
289	}
290
291	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
292	{
293	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
294	return VINF_SUCCESS;
295	}
296
297	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
298	{
299	NOREF(pVM); NOREF(pVCpu);
300	return VINF_SUCCESS;
301	}
302
303	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
304	{
305	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
306	return VINF_SUCCESS;
307	}
308
309	/** @} */
310
311
312	/**
313	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
314	* Down at the Rate Specified" erratum.
315	*
316	* Errata names and related steppings:
317	* - BA86 - D0.
318	* - AAX65 - C2.
319	* - AAU65 - C2, K0.
320	* - AAO95 - B1.
321	* - AAT59 - C2.
322	* - AAK139 - D0.
323	* - AAM126 - C0, C1, D0.
324	* - AAN92 - B1.
325	* - AAJ124 - C0, D0.
326	*
327	* - AAP86 - B1.
328	*
329	* Steppings: B1, C0, C1, C2, D0, K0.
330	*
331	* @returns true if subject to it, false if not.
332	*/
333	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
334	{
335	uint32_t u = ASMCpuId_EAX(1);
336	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
337	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
338	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
339	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
340	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
341	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
342	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
343	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
344	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
345	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
346	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
347	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
348	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
349	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
350	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
351	)
352	return true;
353	return false;
354	}
355
356
357	/**
358	* Intel specific initialization code.
359	*
360	* @returns VBox status code (will only fail if out of memory).
361	*/
362	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
363	{
364	/*
365	* Check that all the required VT-x features are present.
366	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
367	*/
368	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
369	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
370	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
371	)
372	{
373	/** @todo move this into a separate function. */
374	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
375
376	/*
377	* First try use native kernel API for controlling VT-x.
378	* (This is only supported by some Mac OS X kernels atm.)
379	*/
380	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
381	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
382	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
383	{
384	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
385	if (RT_SUCCESS(rc))
386	{
387	g_HvmR0.vmx.fSupported = true;
388	rc = SUPR0EnableVTx(false /* fEnable */);
389	AssertLogRelRC(rc);
390	}
391	}
392	else
393	{
394	/* We need to check if VT-x has been properly initialized on all
395	CPUs. Some BIOSes do a lousy job. */
396	HMR0FIRSTRC FirstRc;
397	hmR0FirstRcInit(&FirstRc);
398	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
399	if (RT_SUCCESS(g_HvmR0.lLastError))
400	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
401	}
402	if (RT_SUCCESS(g_HvmR0.lLastError))
403	{
404	/* Reread in case we've changed it. */
405	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
406
407	if ( (g_HvmR0.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
408	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
409	{
410	/*
411	* Read all relevant MSR.
412	*/
413	g_HvmR0.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
414	g_HvmR0.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
415	g_HvmR0.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
416	g_HvmR0.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
417	g_HvmR0.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
418	g_HvmR0.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
419	g_HvmR0.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
420	g_HvmR0.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
421	g_HvmR0.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
422	g_HvmR0.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
423	g_HvmR0.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
424	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
425	g_HvmR0.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
426	/* VPID 16 bits ASID. */
427	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
428
429	if (g_HvmR0.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
430	{
431	g_HvmR0.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
432	if ( g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1
433	& (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
434	{
435	g_HvmR0.vmx.msr.vmx_ept_vpid_caps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
436	}
437
438	if (g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
439	g_HvmR0.vmx.msr.vmx_vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
440	}
441
442	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
443	{
444	/*
445	* Enter root mode
446	*/
447	RTR0MEMOBJ hScatchMemObj;
448	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
449	if (RT_FAILURE(rc))
450	{
451	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
452	return rc;
453	}
454
455	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
456	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
457	ASMMemZeroPage(pvScatchPage);
458
459	/* Set revision dword at the beginning of the structure. */
460	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.vmx_basic_info);
461
462	/* Make sure we don't get rescheduled to another cpu during this probe. */
463	RTCCUINTREG fFlags = ASMIntDisableFlags();
464
465	/*
466	* Check CR4.VMXE
467	*/
468	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
469	if (!(g_HvmR0.vmx.hostCR4 & X86_CR4_VMXE))
470	{
471	/* In theory this bit could be cleared behind our back. Which would cause
472	#UD faults when we try to execute the VMX instructions... */
473	ASMSetCR4(g_HvmR0.vmx.hostCR4 \| X86_CR4_VMXE);
474	}
475
476	/*
477	* The only way of checking if we're in VMX root mode or not is to try and enter it.
478	* There is no instruction or control bit that tells us if we're in VMX root mode.
479	* Therefore, try and enter VMX root mode here.
480	*/
481	rc = VMXEnable(HCPhysScratchPage);
482	if (RT_SUCCESS(rc))
483	{
484	g_HvmR0.vmx.fSupported = true;
485	VMXDisable();
486	}
487	else
488	{
489	/*
490	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
491	* it will crash the host when we enter raw mode, because:
492	*
493	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
494	* this bit), and
495	* (b) turning off paging causes a #GP (unavoidable when switching
496	* from long to 32 bits mode or 32 bits to PAE).
497	*
498	* They should fix their code, but until they do we simply refuse to run.
499	*/
500	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
501	}
502
503	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
504	if it wasn't so before (some software could incorrectly
505	think it's in VMX mode). */
506	ASMSetCR4(g_HvmR0.vmx.hostCR4);
507	ASMSetFlags(fFlags);
508
509	RTR0MemObjFree(hScatchMemObj, false);
510	}
511	}
512	else
513	{
514	AssertFailed(); /* can't hit this case anymore */
515	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
516	}
517
518	if (g_HvmR0.vmx.fSupported)
519	{
520	/* Call the global VT-x initialization routine. */
521	rc = VMXR0GlobalInit();
522	if (RT_FAILURE(rc))
523	g_HvmR0.lLastError = rc;
524
525	/*
526	* Install the VT-x methods.
527	*/
528	g_HvmR0.pfnEnterSession = VMXR0Enter;
529	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
530	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
531	g_HvmR0.pfnLoadGuestState = VMXR0LoadGuestState;
532	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
533	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
534	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
535	g_HvmR0.pfnInitVM = VMXR0InitVM;
536	g_HvmR0.pfnTermVM = VMXR0TermVM;
537	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
538
539	/*
540	* Check for the VMX-Preemption Timer and adjust for the * "VMX-Preemption
541	* Timer Does Not Count Down at the Rate Specified" erratum.
542	*/
543	if (g_HvmR0.vmx.msr.vmx_pin_ctls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
544	{
545	g_HvmR0.vmx.fUsePreemptTimer = true;
546	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.vmx_misc);
547	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
548	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
549	}
550	}
551	}
552	#ifdef LOG_ENABLED
553	else
554	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
555	#endif
556	}
557	else
558	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
559	return VINF_SUCCESS;
560	}
561
562
563	/**
564	* AMD-specific initialization code.
565	*
566	* @returns VBox status code.
567	*/
568	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
569	{
570	/*
571	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
572	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
573	*/
574	int rc;
575	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
576	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
577	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
578	&& ASMIsValidExtRange(uMaxExtLeaf)
579	&& uMaxExtLeaf >= 0x8000000a
580	)
581	{
582	/* Call the global AMD-V initialization routine. */
583	rc = SVMR0GlobalInit();
584	if (RT_FAILURE(rc))
585	{
586	g_HvmR0.lLastError = rc;
587	return rc;
588	}
589
590	/*
591	* Install the AMD-V methods.
592	*/
593	g_HvmR0.pfnEnterSession = SVMR0Enter;
594	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
595	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
596	g_HvmR0.pfnLoadGuestState = SVMR0LoadGuestState;
597	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
598	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
599	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
600	g_HvmR0.pfnInitVM = SVMR0InitVM;
601	g_HvmR0.pfnTermVM = SVMR0TermVM;
602	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
603
604	/* Query AMD features. */
605	uint32_t u32Dummy;
606	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
607
608	/*
609	* We need to check if AMD-V has been properly initialized on all CPUs.
610	* Some BIOSes might do a poor job.
611	*/
612	HMR0FIRSTRC FirstRc;
613	hmR0FirstRcInit(&FirstRc);
614	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
615	AssertRC(rc);
616	if (RT_SUCCESS(rc))
617	rc = hmR0FirstRcGetStatus(&FirstRc);
618	#ifndef DEBUG_bird
619	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
620	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
621	#endif
622	if (RT_SUCCESS(rc))
623	{
624	/* Read the HWCR MSR for diagnostics. */
625	g_HvmR0.svm.msrHwcr = ASMRdMsr(MSR_K8_HWCR);
626	g_HvmR0.svm.fSupported = true;
627	}
628	else
629	g_HvmR0.lLastError = rc;
630	}
631	else
632	{
633	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
634	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
635	}
636	return rc;
637	}
638
639
640	/**
641	* Does global Ring-0 HM initialization (at module init).
642	*
643	* @returns VBox status code.
644	*/
645	VMMR0_INT_DECL(int) HMR0Init(void)
646	{
647	/*
648	* Initialize the globals.
649	*/
650	g_HvmR0.fEnabled = false;
651	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
652	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
653	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
654	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
655
656	/* Fill in all callbacks with placeholders. */
657	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
658	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
659	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
660	g_HvmR0.pfnLoadGuestState = hmR0DummyLoadGuestState;
661	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
662	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
663	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
664	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
665	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
666	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
667
668	/* Default is global VT-x/AMD-V init. */
669	g_HvmR0.fGlobalInit = true;
670
671	/*
672	* Make sure aCpuInfo is big enough for all the CPUs on this system.
673	*/
674	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
675	{
676	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
677	return VERR_TOO_MANY_CPUS;
678	}
679
680	/*
681	* Check for VT-x and AMD-V capabilities.
682	*/
683	int rc;
684	if (ASMHasCpuId())
685	{
686	/* Standard features. */
687	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
688	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
689	if (ASMIsValidStdRange(uMaxLeaf))
690	{
691	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
692	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
693
694	/* Query AMD features. */
695	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
696	if (ASMIsValidExtRange(uMaxExtLeaf))
697	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
698	&g_HvmR0.cpuid.u32AMDFeatureECX,
699	&g_HvmR0.cpuid.u32AMDFeatureEDX);
700	else
701	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
702
703	/* Go to CPU specific initialization code. */
704	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
705	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
706	{
707	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
708	if (RT_FAILURE(rc))
709	return rc;
710	}
711	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
712	{
713	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
714	if (RT_FAILURE(rc))
715	return rc;
716	}
717	else
718	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
719	}
720	else
721	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
722	}
723	else
724	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
725
726	/*
727	* Register notification callbacks that we can use to disable/enable CPUs
728	* when brought offline/online or suspending/resuming.
729	*/
730	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
731	{
732	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
733	AssertRC(rc);
734
735	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
736	AssertRC(rc);
737	}
738
739	/* We return success here because module init shall not fail if HM
740	fails to initialize. */
741	return VINF_SUCCESS;
742	}
743
744
745	/**
746	* Does global Ring-0 HM termination (at module termination).
747	*
748	* @returns VBox status code.
749	*/
750	VMMR0_INT_DECL(int) HMR0Term(void)
751	{
752	int rc;
753	if ( g_HvmR0.vmx.fSupported
754	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
755	{
756	/*
757	* Simple if the host OS manages VT-x.
758	*/
759	Assert(g_HvmR0.fGlobalInit);
760	rc = SUPR0EnableVTx(false /* fEnable */);
761
762	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
763	{
764	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
765	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
766	}
767	}
768	else
769	{
770	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
771	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
772	{
773	/* Doesn't really matter if this fails. */
774	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
775	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
776	}
777	else
778	rc = VINF_SUCCESS;
779
780	/*
781	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
782	*/
783	if (g_HvmR0.fGlobalInit)
784	{
785	HMR0FIRSTRC FirstRc;
786	hmR0FirstRcInit(&FirstRc);
787	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
788	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
789	if (RT_SUCCESS(rc))
790	{
791	rc = hmR0FirstRcGetStatus(&FirstRc);
792	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
793	}
794	}
795
796	/*
797	* Free the per-cpu pages used for VT-x and AMD-V.
798	*/
799	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
800	{
801	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
802	{
803	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
804	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
805	}
806	}
807	}
808
809	/** @todo This needs cleaning up. There's no matching
810	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
811	* should move into their respective modules. */
812	/* Finally, call global VT-x/AMD-V termination. */
813	if (g_HvmR0.vmx.fSupported)
814	VMXR0GlobalTerm();
815	else if (g_HvmR0.svm.fSupported)
816	SVMR0GlobalTerm();
817
818	return rc;
819	}
820
821
822	/**
823	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
824	* VT-x on a CPU.
825	*
826	* @param idCpu The identifier for the CPU the function is called on.
827	* @param pvUser1 Pointer to the first RC structure.
828	* @param pvUser2 Ignored.
829	*/
830	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
831	{
832	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
833	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
834	NOREF(pvUser2);
835
836	/*
837	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
838	* Once the lock bit is set, this MSR can no longer be modified.
839	*/
840	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
841	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
842	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
843	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
844	)
845	{
846	/* MSR is not yet locked; we can change it ourselves here. */
847	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
848	g_HvmR0.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
849	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
850	}
851
852	int rc;
853	if ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
854	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
855	rc = VINF_SUCCESS;
856	else
857	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
858
859	hmR0FirstRcSetStatus(pFirstRc, rc);
860	}
861
862
863	/**
864	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
865	* on a CPU.
866	*
867	* @param idCpu The identifier for the CPU the function is called on.
868	* @param pvUser1 Pointer to the first RC structure.
869	* @param pvUser2 Ignored.
870	*/
871	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
872	{
873	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
874	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
875	NOREF(pvUser2);
876
877	/* Check if SVM is disabled. */
878	int rc;
879	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
880	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
881	{
882	/* Turn on SVM in the EFER MSR. */
883	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
884	if (fEfer & MSR_K6_EFER_SVME)
885	rc = VERR_SVM_IN_USE;
886	else
887	{
888	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
889
890	/* Paranoia. */
891	fEfer = ASMRdMsr(MSR_K6_EFER);
892	if (fEfer & MSR_K6_EFER_SVME)
893	{
894	/* Restore previous value. */
895	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
896	rc = VINF_SUCCESS;
897	}
898	else
899	rc = VERR_SVM_ILLEGAL_EFER_MSR;
900	}
901	}
902	else
903	rc = VERR_SVM_DISABLED;
904
905	hmR0FirstRcSetStatus(pFirstRc, rc);
906	}
907
908
909	/**
910	* Enable VT-x or AMD-V on the current CPU
911	*
912	* @returns VBox status code.
913	* @param pVM Pointer to the VM (can be 0).
914	* @param idCpu The identifier for the CPU the function is called on.
915	*/
916	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
917	{
918	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
919
920	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
921	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
922	Assert(!pCpu->fConfigured);
923
924	pCpu->idCpu = idCpu;
925	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
926	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
927
928	int rc;
929	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
930	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL, NIL_RTHCPHYS, true);
931	else
932	{
933	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
934	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
935	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
936	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
937	}
938	AssertRC(rc);
939	if (RT_SUCCESS(rc))
940	pCpu->fConfigured = true;
941
942	return rc;
943	}
944
945
946	/**
947	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
948	* is to be called on the target cpus.
949	*
950	* @param idCpu The identifier for the CPU the function is called on.
951	* @param pvUser1 The 1st user argument.
952	* @param pvUser2 The 2nd user argument.
953	*/
954	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
955	{
956	PVM pVM = (PVM)pvUser1; /* can be NULL! */
957	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
958	AssertReturnVoid(g_HvmR0.fGlobalInit);
959	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
960	}
961
962
963	/**
964	* RTOnce callback employed by HMR0EnableAllCpus.
965	*
966	* @returns VBox status code.
967	* @param pvUser Pointer to the VM.
968	* @param pvUserIgnore NULL, ignored.
969	*/
970	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
971	{
972	PVM pVM = (PVM)pvUser;
973
974	/*
975	* Indicate that we've initialized.
976	*
977	* Note! There is a potential race between this function and the suspend
978	* notification. Kind of unlikely though, so ignored for now.
979	*/
980	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
981	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
982
983	/*
984	* The global init variable is set by the first VM.
985	*/
986	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
987
988	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
989	{
990	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
991	g_HvmR0.aCpuInfo[i].fConfigured = false;
992	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
993	g_HvmR0.aCpuInfo[i].uCurrentAsid = 0;
994	}
995
996	int rc;
997	if ( g_HvmR0.vmx.fSupported
998	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
999	{
1000	/*
1001	* Global VT-x initialization API (only darwin for now).
1002	*/
1003	rc = SUPR0EnableVTx(true /* fEnable */);
1004	if (RT_SUCCESS(rc))
1005	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
1006	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
1007	else
1008	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
1009	}
1010	else
1011	{
1012	/*
1013	* We're doing the job ourselves.
1014	*/
1015	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
1016	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1017	{
1018	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1019
1020	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1021	{
1022	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1023	AssertLogRelRCReturn(rc, rc);
1024
1025	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1026	ASMMemZeroPage(pvR0);
1027	}
1028	}
1029
1030	rc = VINF_SUCCESS;
1031	}
1032
1033	if ( RT_SUCCESS(rc)
1034	&& g_HvmR0.fGlobalInit)
1035	{
1036	/* First time, so initialize each cpu/core. */
1037	HMR0FIRSTRC FirstRc;
1038	hmR0FirstRcInit(&FirstRc);
1039	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1040	if (RT_SUCCESS(rc))
1041	rc = hmR0FirstRcGetStatus(&FirstRc);
1042	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1043	}
1044
1045	return rc;
1046	}
1047
1048
1049	/**
1050	* Sets up HM on all cpus.
1051	*
1052	* @returns VBox status code.
1053	* @param pVM Pointer to the VM.
1054	*/
1055	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1056	{
1057	/* Make sure we don't touch HM after we've disabled HM in
1058	preparation of a suspend. */
1059	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1060	return VERR_HM_SUSPEND_PENDING;
1061
1062	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1063	}
1064
1065
1066	/**
1067	* Disable VT-x or AMD-V on the current CPU.
1068	*
1069	* @returns VBox status code.
1070	* @param idCpu The identifier for the CPU the function is called on.
1071	*/
1072	static int hmR0DisableCpu(RTCPUID idCpu)
1073	{
1074	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1075
1076	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1077	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1078	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1079	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1080
1081	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1082	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1083
1084	int rc;
1085	if (pCpu->fConfigured)
1086	{
1087	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1088	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1089	if (idCpu == RTMpCpuId())
1090	{
1091	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1092	AssertRC(rc);
1093	}
1094	else
1095	{
1096	pCpu->fIgnoreAMDVInUseError = true;
1097	rc = VINF_SUCCESS;
1098	}
1099
1100	pCpu->fConfigured = false;
1101	}
1102	else
1103	rc = VINF_SUCCESS; /* nothing to do */
1104
1105	pCpu->uCurrentAsid = 0;
1106	return rc;
1107	}
1108
1109
1110	/**
1111	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1112	* is to be called on the target cpus.
1113	*
1114	* @param idCpu The identifier for the CPU the function is called on.
1115	* @param pvUser1 The 1st user argument.
1116	* @param pvUser2 The 2nd user argument.
1117	*/
1118	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1119	{
1120	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1121	AssertReturnVoid(g_HvmR0.fGlobalInit);
1122	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1123	}
1124
1125
1126	/**
1127	* Callback function invoked when a cpu goes online or offline.
1128	*
1129	* @param enmEvent The Mp event.
1130	* @param idCpu The identifier for the CPU the function is called on.
1131	* @param pvData Opaque data (PVM pointer).
1132	*/
1133	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1134	{
1135	NOREF(pvData);
1136
1137	/*
1138	* We only care about uninitializing a CPU that is going offline. When a
1139	* CPU comes online, the initialization is done lazily in HMR0Enter().
1140	*/
1141	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1142	switch (enmEvent)
1143	{
1144	case RTMPEVENT_OFFLINE:
1145	{
1146	int rc = hmR0DisableCpu(idCpu);
1147	AssertRC(rc);
1148	break;
1149	}
1150
1151	default:
1152	break;
1153	}
1154	}
1155
1156
1157	/**
1158	* Called whenever a system power state change occurs.
1159	*
1160	* @param enmEvent The Power event.
1161	* @param pvUser User argument.
1162	*/
1163	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1164	{
1165	NOREF(pvUser);
1166	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1167
1168	#ifdef LOG_ENABLED
1169	if (enmEvent == RTPOWEREVENT_SUSPEND)
1170	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1171	else
1172	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1173	#endif
1174
1175	if (enmEvent == RTPOWEREVENT_SUSPEND)
1176	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1177
1178	if (g_HvmR0.fEnabled)
1179	{
1180	int rc;
1181	HMR0FIRSTRC FirstRc;
1182	hmR0FirstRcInit(&FirstRc);
1183
1184	if (enmEvent == RTPOWEREVENT_SUSPEND)
1185	{
1186	if (g_HvmR0.fGlobalInit)
1187	{
1188	/* Turn off VT-x or AMD-V on all CPUs. */
1189	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
1190	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1191	}
1192	/* else nothing to do here for the local init case */
1193	}
1194	else
1195	{
1196	/* Reinit the CPUs from scratch as the suspend state might have
1197	messed with the MSRs. (lousy BIOSes as usual) */
1198	if (g_HvmR0.vmx.fSupported)
1199	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1200	else
1201	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1202	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1203	if (RT_SUCCESS(rc))
1204	rc = hmR0FirstRcGetStatus(&FirstRc);
1205	#ifdef LOG_ENABLED
1206	if (RT_FAILURE(rc))
1207	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1208	#endif
1209	if (g_HvmR0.fGlobalInit)
1210	{
1211	/* Turn VT-x or AMD-V back on on all CPUs. */
1212	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
1213	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1214	}
1215	/* else nothing to do here for the local init case */
1216	}
1217	}
1218
1219	if (enmEvent == RTPOWEREVENT_RESUME)
1220	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1221	}
1222
1223
1224	/**
1225	* Does Ring-0 per VM HM initialization.
1226	*
1227	* This will copy HM global into the VM structure and call the CPU specific
1228	* init routine which will allocate resources for each virtual CPU and such.
1229	*
1230	* @returns VBox status code.
1231	* @param pVM Pointer to the VM.
1232	*/
1233	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1234	{
1235	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1236
1237	#ifdef LOG_ENABLED
1238	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1239	#endif
1240
1241	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1242	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1243	return VERR_HM_SUSPEND_PENDING;
1244
1245	/*
1246	* Copy globals to the VM structure.
1247	*/
1248	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1249	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1250
1251	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1252	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1253	pVM->hm.s.vmx.msr.feature_ctrl = g_HvmR0.vmx.msr.feature_ctrl;
1254	pVM->hm.s.vmx.hostCR4 = g_HvmR0.vmx.hostCR4;
1255	pVM->hm.s.vmx.hostEFER = g_HvmR0.vmx.hostEFER;
1256	pVM->hm.s.vmx.msr.vmx_basic_info = g_HvmR0.vmx.msr.vmx_basic_info;
1257	pVM->hm.s.vmx.msr.vmx_pin_ctls = g_HvmR0.vmx.msr.vmx_pin_ctls;
1258	pVM->hm.s.vmx.msr.vmx_proc_ctls = g_HvmR0.vmx.msr.vmx_proc_ctls;
1259	pVM->hm.s.vmx.msr.vmx_proc_ctls2 = g_HvmR0.vmx.msr.vmx_proc_ctls2;
1260	pVM->hm.s.vmx.msr.vmx_exit = g_HvmR0.vmx.msr.vmx_exit;
1261	pVM->hm.s.vmx.msr.vmx_entry = g_HvmR0.vmx.msr.vmx_entry;
1262	pVM->hm.s.vmx.msr.vmx_misc = g_HvmR0.vmx.msr.vmx_misc;
1263	pVM->hm.s.vmx.msr.vmx_cr0_fixed0 = g_HvmR0.vmx.msr.vmx_cr0_fixed0;
1264	pVM->hm.s.vmx.msr.vmx_cr0_fixed1 = g_HvmR0.vmx.msr.vmx_cr0_fixed1;
1265	pVM->hm.s.vmx.msr.vmx_cr4_fixed0 = g_HvmR0.vmx.msr.vmx_cr4_fixed0;
1266	pVM->hm.s.vmx.msr.vmx_cr4_fixed1 = g_HvmR0.vmx.msr.vmx_cr4_fixed1;
1267	pVM->hm.s.vmx.msr.vmx_vmcs_enum = g_HvmR0.vmx.msr.vmx_vmcs_enum;
1268	pVM->hm.s.vmx.msr.vmx_vmfunc = g_HvmR0.vmx.msr.vmx_vmfunc;
1269	pVM->hm.s.vmx.msr.vmx_ept_vpid_caps = g_HvmR0.vmx.msr.vmx_ept_vpid_caps;
1270	pVM->hm.s.svm.msrHwcr = g_HvmR0.svm.msrHwcr;
1271	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1272	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1273	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1274	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1275	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1276
1277	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1278
1279
1280	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1281	{
1282	pVM->hm.s.cMaxResumeLoops = 1024;
1283	if (RTThreadPreemptIsPendingTrusty())
1284	pVM->hm.s.cMaxResumeLoops = 8192;
1285	}
1286
1287	/*
1288	* Initialize some per CPU fields.
1289	*/
1290	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1291	{
1292	PVMCPU pVCpu = &pVM->aCpus[i];
1293
1294	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1295
1296	/* Invalidate the last cpu we were running on. */
1297	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1298
1299	/* We'll aways increment this the first time (host uses ASID 0) */
1300	pVCpu->hm.s.uCurrentAsid = 0;
1301	}
1302
1303	/*
1304	* Call the hardware specific initialization method.
1305	*/
1306	RTCCUINTREG fFlags = ASMIntDisableFlags();
1307	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1308	ASMSetFlags(fFlags);
1309
1310	int rc = g_HvmR0.pfnInitVM(pVM);
1311	return rc;
1312	}
1313
1314
1315	/**
1316	* Does Ring-0 per VM HM termination.
1317	*
1318	* @returns VBox status code.
1319	* @param pVM Pointer to the VM.
1320	*/
1321	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1322	{
1323	Log(("HMR0TermVM: %p\n", pVM));
1324	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1325
1326	/* Make sure we don't touch HM after we've disabled HM in preparation
1327	of a suspend. */
1328	/** @todo r=bird: This cannot be right, the termination functions are
1329	* just freeing memory and resetting pVM/pVCpu members...
1330	* ==> memory leak. */
1331	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1332
1333	/*
1334	* Call the hardware specific method.
1335	*/
1336	RTCCUINTREG fFlags = ASMIntDisableFlags();
1337	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1338	ASMSetFlags(fFlags);
1339
1340	int rc = g_HvmR0.pfnTermVM(pVM);
1341	return rc;
1342	}
1343
1344
1345	/**
1346	* Sets up a VT-x or AMD-V session.
1347	*
1348	* This is mostly about setting up the hardware VM state.
1349	*
1350	* @returns VBox status code.
1351	* @param pVM Pointer to the VM.
1352	*/
1353	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1354	{
1355	Log(("HMR0SetupVM: %p\n", pVM));
1356	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1357
1358	/* Make sure we don't touch HM after we've disabled HM in
1359	preparation of a suspend. */
1360	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1361
1362	/*
1363	* Call the hardware specific setup VM method. This requires the CPU to be
1364	* enabled for AMD-V/VT-x and preemption to be prevented.
1365	*/
1366	RTCCUINTREG fFlags = ASMIntDisableFlags();
1367	RTCPUID idCpu = RTMpCpuId();
1368	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1369
1370	/* On first entry we'll sync everything. */
1371	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1372	pVM->aCpus[i].hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1373
1374	/* Enable VT-x or AMD-V if local init is required. */
1375	int rc;
1376	if (!g_HvmR0.fGlobalInit)
1377	{
1378	rc = hmR0EnableCpu(pVM, idCpu);
1379	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1380	}
1381
1382	/* Setup VT-x or AMD-V. */
1383	rc = g_HvmR0.pfnSetupVM(pVM);
1384
1385	/* Disable VT-x or AMD-V if local init was done before. */
1386	if (!g_HvmR0.fGlobalInit)
1387	{
1388	int rc2 = hmR0DisableCpu(idCpu);
1389	AssertRC(rc2);
1390	}
1391
1392	ASMSetFlags(fFlags);
1393	return rc;
1394	}
1395
1396
1397	/**
1398	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1399	* required for entering HM context.
1400	*
1401	* @returns VBox status code.
1402	* @param pvCpu Pointer to the VMCPU.
1403	*
1404	* @remarks No-long-jump zone!!!
1405	*/
1406	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1407	{
1408	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1409
1410	int rc = VINF_SUCCESS;
1411	RTCPUID idCpu = RTMpCpuId();
1412	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1413	AssertPtr(pCpu);
1414
1415	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1416	if (!pCpu->fConfigured)
1417	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1418
1419	/* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
1420	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE;
1421	pVCpu->hm.s.idEnteredCpu = idCpu;
1422	return rc;
1423	}
1424
1425
1426	/**
1427	* Enters the VT-x or AMD-V session.
1428	*
1429	* @returns VBox status code.
1430	* @param pVM Pointer to the VM.
1431	* @param pVCpu Pointer to the VMCPU.
1432	*
1433	* @remarks This is called with preemption disabled.
1434	*/
1435	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1436	{
1437	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1438	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1439	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1440
1441	/* Load the bare minimum state required for entering HM. */
1442	int rc = HMR0EnterCpu(pVCpu);
1443	AssertRCReturn(rc, rc);
1444
1445	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1446	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1447	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1448	#endif
1449
1450	RTCPUID idCpu = RTMpCpuId();
1451	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1452	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1453	Assert(pCpu);
1454	Assert(pCtx);
1455	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1456
1457	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1458	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1459
1460	/* Load the host as we may be resuming code after a longjmp and quite
1461	possibly be scheduled on a different CPU. */
1462	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1463	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1464
1465	/** @todo This is not needed to be done here anymore, can fix/optimize later. */
1466	rc = g_HvmR0.pfnLoadGuestState(pVM, pVCpu, pCtx);
1467	AssertMsgRCReturn(rc, ("pfnLoadGuestState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1468
1469	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1470	if (fStartedSet)
1471	PGMRZDynMapReleaseAutoSet(pVCpu);
1472	#endif
1473
1474	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1475	and ring-3 calls. */
1476	if (RT_FAILURE(rc))
1477	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1478	return rc;
1479	}
1480
1481
1482	/**
1483	* Deinitializes the bare minimum state used for HM context and if necessary
1484	* disable HM on the CPU.
1485	*
1486	* @returns VBox status code.
1487	* @param pVCpu Pointer to the VMCPU.
1488	*
1489	* @remarks No-long-jump zone!!!
1490	*/
1491	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1492	{
1493	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1494
1495	RTCPUID idCpu = RTMpCpuId();
1496	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1497
1498	if ( !g_HvmR0.fGlobalInit
1499	&& pCpu->fConfigured)
1500	{
1501	int rc = hmR0DisableCpu(idCpu);
1502	AssertRCReturn(rc, rc);
1503	Assert(!pCpu->fConfigured);
1504	}
1505
1506	/* Reset these to force a TLB flush for the next entry. */
1507	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1508	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1509	pVCpu->hm.s.uCurrentAsid = 0;
1510	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1511
1512	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1513	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1514
1515	return VINF_SUCCESS;
1516	}
1517
1518
1519	/**
1520	* Thread-context hook for HM.
1521	*
1522	* @param enmEvent The thread-context event.
1523	* @param pvUser Opaque pointer to the VMCPU.
1524	*/
1525	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1526	{
1527	PVMCPU pVCpu = (PVMCPU)pvUser;
1528	Assert(pVCpu);
1529	Assert(g_HvmR0.pfnThreadCtxCallback);
1530
1531	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1532	}
1533
1534
1535	/**
1536	* Runs guest code in a hardware accelerated VM.
1537	*
1538	* @returns VBox status code.
1539	* @param pVM Pointer to the VM.
1540	* @param pVCpu Pointer to the VMCPU.
1541	*
1542	* @remarks Called with preemption disabled and after first having called
1543	* HMR0Enter.
1544	*/
1545	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1546	{
1547	#ifdef VBOX_STRICT
1548	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1549	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1550	Assert(pCpu->fConfigured);
1551	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1552	#endif
1553
1554	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1555	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1556	PGMRZDynMapStartAutoSet(pVCpu);
1557	#endif
1558
1559	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1560
1561	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1562	PGMRZDynMapReleaseAutoSet(pVCpu);
1563	#endif
1564	return rc;
1565	}
1566
1567	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1568
1569	/**
1570	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1571	*
1572	* @returns VBox status code.
1573	* @param pVM Pointer to the VM.
1574	* @param pVCpu Pointer to the VMCPU.
1575	* @param pCtx Pointer to the guest CPU context.
1576	*/
1577	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1578	{
1579	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1580	if (pVM->hm.s.vmx.fSupported)
1581	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1582	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1583	}
1584
1585
1586	/**
1587	* Save guest debug state (64 bits guest mode & 32 bits host only)
1588	*
1589	* @returns VBox status code.
1590	* @param pVM Pointer to the VM.
1591	* @param pVCpu Pointer to the VMCPU.
1592	* @param pCtx Pointer to the guest CPU context.
1593	*/
1594	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1595	{
1596	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1597	if (pVM->hm.s.vmx.fSupported)
1598	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1599	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1600	}
1601
1602
1603	/**
1604	* Test the 32->64 bits switcher.
1605	*
1606	* @returns VBox status code.
1607	* @param pVM Pointer to the VM.
1608	*/
1609	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1610	{
1611	PVMCPU pVCpu = &pVM->aCpus[0];
1612	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1613	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1614	int rc;
1615
1616	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1617	if (pVM->hm.s.vmx.fSupported)
1618	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1619	else
1620	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1621	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1622
1623	return rc;
1624	}
1625
1626	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1627
1628	/**
1629	* Returns suspend status of the host.
1630	*
1631	* @returns Suspend pending or not.
1632	*/
1633	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1634	{
1635	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1636	}
1637
1638
1639	/**
1640	* Returns the cpu structure for the current cpu.
1641	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1642	*
1643	* @returns The cpu structure pointer.
1644	*/
1645	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1646	{
1647	RTCPUID idCpu = RTMpCpuId();
1648	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1649	return &g_HvmR0.aCpuInfo[idCpu];
1650	}
1651
1652
1653	/**
1654	* Returns the cpu structure for the current cpu.
1655	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1656	*
1657	* @returns The cpu structure pointer.
1658	* @param idCpu id of the VCPU.
1659	*/
1660	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1661	{
1662	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1663	return &g_HvmR0.aCpuInfo[idCpu];
1664	}
1665
1666
1667	/**
1668	* Save a pending IO read.
1669	*
1670	* @param pVCpu Pointer to the VMCPU.
1671	* @param GCPtrRip Address of IO instruction.
1672	* @param GCPtrRipNext Address of the next instruction.
1673	* @param uPort Port address.
1674	* @param uAndVal AND mask for saving the result in eax.
1675	* @param cbSize Read size.
1676	*/
1677	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1678	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1679	{
1680	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1681	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1682	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1683	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1684	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1685	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1686	return;
1687	}
1688
1689
1690	/**
1691	* Save a pending IO write.
1692	*
1693	* @param pVCpu Pointer to the VMCPU.
1694	* @param GCPtrRIP Address of IO instruction.
1695	* @param uPort Port address.
1696	* @param uAndVal AND mask for fetching the result from eax.
1697	* @param cbSize Read size.
1698	*/
1699	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1700	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1701	{
1702	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1703	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1704	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1705	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1706	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1707	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1708	return;
1709	}
1710
1711
1712	/**
1713	* Raw-mode switcher hook - disable VT-x if it's active and the current
1714	* switcher turns off paging.
1715	*
1716	* @returns VBox status code.
1717	* @param pVM Pointer to the VM.
1718	* @param enmSwitcher The switcher we're about to use.
1719	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1720	*/
1721	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1722	{
1723	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1724
1725	*pfVTxDisabled = false;
1726
1727	/* No such issues with AMD-V */
1728	if (!g_HvmR0.vmx.fSupported)
1729	return VINF_SUCCESS;
1730
1731	/* Check if the swithcing we're up to is safe. */
1732	switch (enmSwitcher)
1733	{
1734	case VMMSWITCHER_32_TO_32:
1735	case VMMSWITCHER_PAE_TO_PAE:
1736	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1737
1738	case VMMSWITCHER_32_TO_PAE:
1739	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1740	case VMMSWITCHER_AMD64_TO_32:
1741	case VMMSWITCHER_AMD64_TO_PAE:
1742	break; /* unsafe switchers */
1743
1744	default:
1745	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1746	}
1747
1748	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1749	regardless of whether we're currently using VT-x or not. */
1750	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1751	{
1752	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1753	return VINF_SUCCESS;
1754	}
1755
1756	/** @todo Check if this code is presumtive wrt other VT-x users on the
1757	* system... */
1758
1759	/* Nothing to do if we haven't enabled VT-x. */
1760	if (!g_HvmR0.fEnabled)
1761	return VINF_SUCCESS;
1762
1763	/* Local init implies the CPU is currently not in VMX root mode. */
1764	if (!g_HvmR0.fGlobalInit)
1765	return VINF_SUCCESS;
1766
1767	/* Ok, disable VT-x. */
1768	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1769	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1770
1771	*pfVTxDisabled = true;
1772	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1773	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1774	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1775	}
1776
1777
1778	/**
1779	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1780	* switcher turned off paging.
1781	*
1782	* @param pVM Pointer to the VM.
1783	* @param fVTxDisabled Whether VT-x was disabled or not.
1784	*/
1785	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1786	{
1787	Assert(!(ASMGetFlags() & X86_EFL_IF));
1788
1789	if (!fVTxDisabled)
1790	return; /* nothing to do */
1791
1792	Assert(g_HvmR0.vmx.fSupported);
1793	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1794	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1795	else
1796	{
1797	Assert(g_HvmR0.fEnabled);
1798	Assert(g_HvmR0.fGlobalInit);
1799
1800	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1801	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1802
1803	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1804	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1805	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
1806	}
1807	}
1808
1809	#ifdef VBOX_STRICT
1810
1811	/**
1812	* Dumps a descriptor.
1813	*
1814	* @param pDesc Descriptor to dump.
1815	* @param Sel Selector number.
1816	* @param pszMsg Message to prepend the log entry with.
1817	*/
1818	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1819	{
1820	/*
1821	* Make variable description string.
1822	*/
1823	static struct
1824	{
1825	unsigned cch;
1826	const char *psz;
1827	} const s_aTypes[32] =
1828	{
1829	# define STRENTRY(str) { sizeof(str) - 1, str }
1830
1831	/* system */
1832	# if HC_ARCH_BITS == 64
1833	STRENTRY("Reserved0 "), /* 0x00 */
1834	STRENTRY("Reserved1 "), /* 0x01 */
1835	STRENTRY("LDT "), /* 0x02 */
1836	STRENTRY("Reserved3 "), /* 0x03 */
1837	STRENTRY("Reserved4 "), /* 0x04 */
1838	STRENTRY("Reserved5 "), /* 0x05 */
1839	STRENTRY("Reserved6 "), /* 0x06 */
1840	STRENTRY("Reserved7 "), /* 0x07 */
1841	STRENTRY("Reserved8 "), /* 0x08 */
1842	STRENTRY("TSS64Avail "), /* 0x09 */
1843	STRENTRY("ReservedA "), /* 0x0a */
1844	STRENTRY("TSS64Busy "), /* 0x0b */
1845	STRENTRY("Call64 "), /* 0x0c */
1846	STRENTRY("ReservedD "), /* 0x0d */
1847	STRENTRY("Int64 "), /* 0x0e */
1848	STRENTRY("Trap64 "), /* 0x0f */
1849	# else
1850	STRENTRY("Reserved0 "), /* 0x00 */
1851	STRENTRY("TSS16Avail "), /* 0x01 */
1852	STRENTRY("LDT "), /* 0x02 */
1853	STRENTRY("TSS16Busy "), /* 0x03 */
1854	STRENTRY("Call16 "), /* 0x04 */
1855	STRENTRY("Task "), /* 0x05 */
1856	STRENTRY("Int16 "), /* 0x06 */
1857	STRENTRY("Trap16 "), /* 0x07 */
1858	STRENTRY("Reserved8 "), /* 0x08 */
1859	STRENTRY("TSS32Avail "), /* 0x09 */
1860	STRENTRY("ReservedA "), /* 0x0a */
1861	STRENTRY("TSS32Busy "), /* 0x0b */
1862	STRENTRY("Call32 "), /* 0x0c */
1863	STRENTRY("ReservedD "), /* 0x0d */
1864	STRENTRY("Int32 "), /* 0x0e */
1865	STRENTRY("Trap32 "), /* 0x0f */
1866	# endif
1867	/* non system */
1868	STRENTRY("DataRO "), /* 0x10 */
1869	STRENTRY("DataRO Accessed "), /* 0x11 */
1870	STRENTRY("DataRW "), /* 0x12 */
1871	STRENTRY("DataRW Accessed "), /* 0x13 */
1872	STRENTRY("DataDownRO "), /* 0x14 */
1873	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1874	STRENTRY("DataDownRW "), /* 0x16 */
1875	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1876	STRENTRY("CodeEO "), /* 0x18 */
1877	STRENTRY("CodeEO Accessed "), /* 0x19 */
1878	STRENTRY("CodeER "), /* 0x1a */
1879	STRENTRY("CodeER Accessed "), /* 0x1b */
1880	STRENTRY("CodeConfEO "), /* 0x1c */
1881	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1882	STRENTRY("CodeConfER "), /* 0x1e */
1883	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1884	# undef SYSENTRY
1885	};
1886	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1887	char szMsg[128];
1888	char *psz = &szMsg[0];
1889	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1890	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1891	psz += s_aTypes[i].cch;
1892
1893	if (pDesc->Gen.u1Present)
1894	ADD_STR(psz, "Present ");
1895	else
1896	ADD_STR(psz, "Not-Present ");
1897	# if HC_ARCH_BITS == 64
1898	if (pDesc->Gen.u1Long)
1899	ADD_STR(psz, "64-bit ");
1900	else
1901	ADD_STR(psz, "Comp ");
1902	# else
1903	if (pDesc->Gen.u1Granularity)
1904	ADD_STR(psz, "Page ");
1905	if (pDesc->Gen.u1DefBig)
1906	ADD_STR(psz, "32-bit ");
1907	else
1908	ADD_STR(psz, "16-bit ");
1909	# endif
1910	# undef ADD_STR
1911	*psz = '\0';
1912
1913	/*
1914	* Limit and Base and format the output.
1915	*/
1916	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1917
1918	# if HC_ARCH_BITS == 64
1919	uint64_t u32Base = X86DESC64_BASE(pDesc);
1920
1921	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1922	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1923	# else
1924	uint32_t u32Base = X86DESC_BASE(pDesc);
1925
1926	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1927	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1928	# endif
1929	}
1930
1931
1932	/**
1933	* Formats a full register dump.
1934	*
1935	* @param pVM Pointer to the VM.
1936	* @param pVCpu Pointer to the VMCPU.
1937	* @param pCtx Pointer to the CPU context.
1938	*/
1939	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1940	{
1941	NOREF(pVM);
1942
1943	/*
1944	* Format the flags.
1945	*/
1946	static struct
1947	{
1948	const char pszSet; const char pszClear; uint32_t fFlag;
1949	} const s_aFlags[] =
1950	{
1951	{ "vip",NULL, X86_EFL_VIP },
1952	{ "vif",NULL, X86_EFL_VIF },
1953	{ "ac", NULL, X86_EFL_AC },
1954	{ "vm", NULL, X86_EFL_VM },
1955	{ "rf", NULL, X86_EFL_RF },
1956	{ "nt", NULL, X86_EFL_NT },
1957	{ "ov", "nv", X86_EFL_OF },
1958	{ "dn", "up", X86_EFL_DF },
1959	{ "ei", "di", X86_EFL_IF },
1960	{ "tf", NULL, X86_EFL_TF },
1961	{ "nt", "pl", X86_EFL_SF },
1962	{ "nz", "zr", X86_EFL_ZF },
1963	{ "ac", "na", X86_EFL_AF },
1964	{ "po", "pe", X86_EFL_PF },
1965	{ "cy", "nc", X86_EFL_CF },
1966	};
1967	char szEFlags[80];
1968	char *psz = szEFlags;
1969	uint32_t efl = pCtx->eflags.u32;
1970	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1971	{
1972	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1973	if (pszAdd)
1974	{
1975	strcpy(psz, pszAdd);
1976	psz += strlen(pszAdd);
1977	*psz++ = ' ';
1978	}
1979	}
1980	psz[-1] = '\0';
1981
1982
1983	/*
1984	* Format the registers.
1985	*/
1986	if (CPUMIsGuestIn64BitCode(pVCpu))
1987	{
1988	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1989	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1990	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1991	"r14=%016RX64 r15=%016RX64\n"
1992	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1993	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1994	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1995	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1996	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1997	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1998	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1999	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
2000	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
2001	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
2002	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2003	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2004	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2005	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2006	,
2007	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
2008	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
2009	pCtx->r14, pCtx->r15,
2010	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2011	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2012	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2013	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2014	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2015	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2016	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2017	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
2018	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
2019	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2020	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2021	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2022	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2023	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2024	}
2025	else
2026	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2027	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2028	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2029	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2030	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2031	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2032	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2033	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2034	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2035	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2036	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2037	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2038	,
2039	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2040	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2041	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2042	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2043	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2044	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2045	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2046	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2047	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2048	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2049	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2050	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2051
2052	Log(("FPU:\n"
2053	"FCW=%04x FSW=%04x FTW=%02x\n"
2054	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2055	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2056	,
2057	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2058	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2059	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2060	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2061
2062
2063	Log(("MSR:\n"
2064	"EFER =%016RX64\n"
2065	"PAT =%016RX64\n"
2066	"STAR =%016RX64\n"
2067	"CSTAR =%016RX64\n"
2068	"LSTAR =%016RX64\n"
2069	"SFMASK =%016RX64\n"
2070	"KERNELGSBASE =%016RX64\n",
2071	pCtx->msrEFER,
2072	pCtx->msrPAT,
2073	pCtx->msrSTAR,
2074	pCtx->msrCSTAR,
2075	pCtx->msrLSTAR,
2076	pCtx->msrSFMASK,
2077	pCtx->msrKERNELGSBASE));
2078
2079	}
2080
2081	#endif /* VBOX_STRICT */
2082

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 48140

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