HMR0.cpp@ 48201

Last change on this file since 48201 was 48153, checked in by vboxsync, 11 years ago
VMM/HM: More dead code path elimination.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 73.5 KB

Line
1	/* $Id: HMR0.cpp 48153 2013-08-29 12:57:00Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	uint64_t hostCR4;
117
118	/** Host EFER value (set by ring-0 VMX init) */
119	uint64_t hostEFER;
120
121	/** VMX MSR values */
122	struct
123	{
124	uint64_t feature_ctrl;
125	uint64_t vmx_basic_info;
126	VMX_CAPABILITY vmx_pin_ctls;
127	VMX_CAPABILITY vmx_proc_ctls;
128	VMX_CAPABILITY vmx_proc_ctls2;
129	VMX_CAPABILITY vmx_exit;
130	VMX_CAPABILITY vmx_entry;
131	uint64_t vmx_misc;
132	uint64_t vmx_cr0_fixed0;
133	uint64_t vmx_cr0_fixed1;
134	uint64_t vmx_cr4_fixed0;
135	uint64_t vmx_cr4_fixed1;
136	uint64_t vmx_vmcs_enum;
137	uint64_t vmx_vmfunc;
138	uint64_t vmx_ept_vpid_caps;
139	} msr;
140	/* Last instruction error */
141	uint32_t ulLastInstrError;
142	} vmx;
143
144	/** AMD-V information. */
145	struct
146	{
147	/* HWCR MSR (for diagnostics) */
148	uint64_t msrHwcr;
149
150	/** SVM revision. */
151	uint32_t u32Rev;
152
153	/** SVM feature bits from cpuid 0x8000000a */
154	uint32_t u32Features;
155
156	/** Set by us to indicate SVM is supported by the CPU. */
157	bool fSupported;
158	} svm;
159	/** Saved error from detection */
160	int32_t lLastError;
161
162	struct
163	{
164	uint32_t u32AMDFeatureECX;
165	uint32_t u32AMDFeatureEDX;
166	} cpuid;
167
168	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
169	* enabled and disabled each time it's used to execute guest code. */
170	bool fGlobalInit;
171	/** Indicates whether the host is suspending or not. We'll refuse a few
172	* actions when the host is being suspended to speed up the suspending and
173	* avoid trouble. */
174	volatile bool fSuspended;
175
176	/** Whether we've already initialized all CPUs.
177	* @remarks We could check the EnableAllCpusOnce state, but this is
178	* simpler and hopefully easier to understand. */
179	bool fEnabled;
180	/** Serialize initialization in HMR0EnableAllCpus. */
181	RTONCE EnableAllCpusOnce;
182	} g_HvmR0;
183
184
185
186	/**
187	* Initializes a first return code structure.
188	*
189	* @param pFirstRc The structure to init.
190	*/
191	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
192	{
193	pFirstRc->rc = VINF_SUCCESS;
194	pFirstRc->idCpu = NIL_RTCPUID;
195	}
196
197
198	/**
199	* Try set the status code (success ignored).
200	*
201	* @param pFirstRc The first return code structure.
202	* @param rc The status code.
203	*/
204	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
205	{
206	if ( RT_FAILURE(rc)
207	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
208	pFirstRc->idCpu = RTMpCpuId();
209	}
210
211
212	/**
213	* Get the status code of a first return code structure.
214	*
215	* @returns The status code; VINF_SUCCESS or error status, no informational or
216	* warning errors.
217	* @param pFirstRc The first return code structure.
218	*/
219	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
220	{
221	return pFirstRc->rc;
222	}
223
224
225	#ifdef VBOX_STRICT
226	/**
227	* Get the CPU ID on which the failure status code was reported.
228	*
229	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
230	* @param pFirstRc The first return code structure.
231	*/
232	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
233	{
234	return pFirstRc->idCpu;
235	}
236	#endif /* VBOX_STRICT */
237
238
239	/** @name Dummy callback handlers.
240	* @{ */
241
242	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
243	{
244	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
245	return VINF_SUCCESS;
246	}
247
248	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
249	{
250	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
251	return VINF_SUCCESS;
252	}
253
254	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
255	{
256	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
257	}
258
259	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
260	bool fEnabledBySystem)
261	{
262	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem);
263	return VINF_SUCCESS;
264	}
265
266	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
267	{
268	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
269	return VINF_SUCCESS;
270	}
271
272	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
273	{
274	NOREF(pVM);
275	return VINF_SUCCESS;
276	}
277
278	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
279	{
280	NOREF(pVM);
281	return VINF_SUCCESS;
282	}
283
284	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
285	{
286	NOREF(pVM);
287	return VINF_SUCCESS;
288	}
289
290	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
291	{
292	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
293	return VINF_SUCCESS;
294	}
295
296	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
297	{
298	NOREF(pVM); NOREF(pVCpu);
299	return VINF_SUCCESS;
300	}
301
302	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
303	{
304	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
305	return VINF_SUCCESS;
306	}
307
308	/** @} */
309
310
311	/**
312	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
313	* Down at the Rate Specified" erratum.
314	*
315	* Errata names and related steppings:
316	* - BA86 - D0.
317	* - AAX65 - C2.
318	* - AAU65 - C2, K0.
319	* - AAO95 - B1.
320	* - AAT59 - C2.
321	* - AAK139 - D0.
322	* - AAM126 - C0, C1, D0.
323	* - AAN92 - B1.
324	* - AAJ124 - C0, D0.
325	*
326	* - AAP86 - B1.
327	*
328	* Steppings: B1, C0, C1, C2, D0, K0.
329	*
330	* @returns true if subject to it, false if not.
331	*/
332	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
333	{
334	uint32_t u = ASMCpuId_EAX(1);
335	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
336	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
337	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
338	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
339	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
340	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
341	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
342	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
343	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
344	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
345	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
346	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
347	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
348	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
349	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
350	)
351	return true;
352	return false;
353	}
354
355
356	/**
357	* Intel specific initialization code.
358	*
359	* @returns VBox status code (will only fail if out of memory).
360	*/
361	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
362	{
363	/*
364	* Check that all the required VT-x features are present.
365	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
366	*/
367	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
368	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
369	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
370	)
371	{
372	/** @todo move this into a separate function. */
373	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
374
375	/*
376	* First try use native kernel API for controlling VT-x.
377	* (This is only supported by some Mac OS X kernels atm.)
378	*/
379	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
380	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
381	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
382	{
383	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
384	if (RT_SUCCESS(rc))
385	{
386	g_HvmR0.vmx.fSupported = true;
387	rc = SUPR0EnableVTx(false /* fEnable */);
388	AssertLogRelRC(rc);
389	}
390	}
391	else
392	{
393	/* We need to check if VT-x has been properly initialized on all
394	CPUs. Some BIOSes do a lousy job. */
395	HMR0FIRSTRC FirstRc;
396	hmR0FirstRcInit(&FirstRc);
397	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
398	if (RT_SUCCESS(g_HvmR0.lLastError))
399	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
400	}
401	if (RT_SUCCESS(g_HvmR0.lLastError))
402	{
403	/* Reread in case we've changed it. */
404	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
405
406	if ( (g_HvmR0.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
407	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
408	{
409	/*
410	* Read all relevant MSR.
411	*/
412	g_HvmR0.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
413	g_HvmR0.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
414	g_HvmR0.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
415	g_HvmR0.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
416	g_HvmR0.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
417	g_HvmR0.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
418	g_HvmR0.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
419	g_HvmR0.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
420	g_HvmR0.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
421	g_HvmR0.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
422	g_HvmR0.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
423	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
424	g_HvmR0.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
425	/* VPID 16 bits ASID. */
426	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
427
428	if (g_HvmR0.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
429	{
430	g_HvmR0.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
431	if ( g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1
432	& (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
433	{
434	g_HvmR0.vmx.msr.vmx_ept_vpid_caps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
435	}
436
437	if (g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
438	g_HvmR0.vmx.msr.vmx_vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
439	}
440
441	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
442	{
443	/*
444	* Enter root mode
445	*/
446	RTR0MEMOBJ hScatchMemObj;
447	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
448	if (RT_FAILURE(rc))
449	{
450	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
451	return rc;
452	}
453
454	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
455	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
456	ASMMemZeroPage(pvScatchPage);
457
458	/* Set revision dword at the beginning of the structure. */
459	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.vmx_basic_info);
460
461	/* Make sure we don't get rescheduled to another cpu during this probe. */
462	RTCCUINTREG fFlags = ASMIntDisableFlags();
463
464	/*
465	* Check CR4.VMXE
466	*/
467	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
468	if (!(g_HvmR0.vmx.hostCR4 & X86_CR4_VMXE))
469	{
470	/* In theory this bit could be cleared behind our back. Which would cause
471	#UD faults when we try to execute the VMX instructions... */
472	ASMSetCR4(g_HvmR0.vmx.hostCR4 \| X86_CR4_VMXE);
473	}
474
475	/*
476	* The only way of checking if we're in VMX root mode or not is to try and enter it.
477	* There is no instruction or control bit that tells us if we're in VMX root mode.
478	* Therefore, try and enter VMX root mode here.
479	*/
480	rc = VMXEnable(HCPhysScratchPage);
481	if (RT_SUCCESS(rc))
482	{
483	g_HvmR0.vmx.fSupported = true;
484	VMXDisable();
485	}
486	else
487	{
488	/*
489	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
490	* it will crash the host when we enter raw mode, because:
491	*
492	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
493	* this bit), and
494	* (b) turning off paging causes a #GP (unavoidable when switching
495	* from long to 32 bits mode or 32 bits to PAE).
496	*
497	* They should fix their code, but until they do we simply refuse to run.
498	*/
499	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
500	}
501
502	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
503	if it wasn't so before (some software could incorrectly
504	think it's in VMX mode). */
505	ASMSetCR4(g_HvmR0.vmx.hostCR4);
506	ASMSetFlags(fFlags);
507
508	RTR0MemObjFree(hScatchMemObj, false);
509	}
510	}
511	else
512	{
513	AssertFailed(); /* can't hit this case anymore */
514	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
515	}
516
517	if (g_HvmR0.vmx.fSupported)
518	{
519	/* Call the global VT-x initialization routine. */
520	rc = VMXR0GlobalInit();
521	if (RT_FAILURE(rc))
522	g_HvmR0.lLastError = rc;
523
524	/*
525	* Install the VT-x methods.
526	*/
527	g_HvmR0.pfnEnterSession = VMXR0Enter;
528	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
529	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
530	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
531	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
532	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
533	g_HvmR0.pfnInitVM = VMXR0InitVM;
534	g_HvmR0.pfnTermVM = VMXR0TermVM;
535	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
536
537	/*
538	* Check for the VMX-Preemption Timer and adjust for the * "VMX-Preemption
539	* Timer Does Not Count Down at the Rate Specified" erratum.
540	*/
541	if (g_HvmR0.vmx.msr.vmx_pin_ctls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
542	{
543	g_HvmR0.vmx.fUsePreemptTimer = true;
544	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.vmx_misc);
545	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
546	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
547	}
548	}
549	}
550	#ifdef LOG_ENABLED
551	else
552	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
553	#endif
554	}
555	else
556	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
557	return VINF_SUCCESS;
558	}
559
560
561	/**
562	* AMD-specific initialization code.
563	*
564	* @returns VBox status code.
565	*/
566	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
567	{
568	/*
569	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
570	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
571	*/
572	int rc;
573	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
574	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
575	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
576	&& ASMIsValidExtRange(uMaxExtLeaf)
577	&& uMaxExtLeaf >= 0x8000000a
578	)
579	{
580	/* Call the global AMD-V initialization routine. */
581	rc = SVMR0GlobalInit();
582	if (RT_FAILURE(rc))
583	{
584	g_HvmR0.lLastError = rc;
585	return rc;
586	}
587
588	/*
589	* Install the AMD-V methods.
590	*/
591	g_HvmR0.pfnEnterSession = SVMR0Enter;
592	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
593	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
594	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
595	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
596	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
597	g_HvmR0.pfnInitVM = SVMR0InitVM;
598	g_HvmR0.pfnTermVM = SVMR0TermVM;
599	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
600
601	/* Query AMD features. */
602	uint32_t u32Dummy;
603	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
604
605	/*
606	* We need to check if AMD-V has been properly initialized on all CPUs.
607	* Some BIOSes might do a poor job.
608	*/
609	HMR0FIRSTRC FirstRc;
610	hmR0FirstRcInit(&FirstRc);
611	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
612	AssertRC(rc);
613	if (RT_SUCCESS(rc))
614	rc = hmR0FirstRcGetStatus(&FirstRc);
615	#ifndef DEBUG_bird
616	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
617	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
618	#endif
619	if (RT_SUCCESS(rc))
620	{
621	/* Read the HWCR MSR for diagnostics. */
622	g_HvmR0.svm.msrHwcr = ASMRdMsr(MSR_K8_HWCR);
623	g_HvmR0.svm.fSupported = true;
624	}
625	else
626	g_HvmR0.lLastError = rc;
627	}
628	else
629	{
630	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
631	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
632	}
633	return rc;
634	}
635
636
637	/**
638	* Does global Ring-0 HM initialization (at module init).
639	*
640	* @returns VBox status code.
641	*/
642	VMMR0_INT_DECL(int) HMR0Init(void)
643	{
644	/*
645	* Initialize the globals.
646	*/
647	g_HvmR0.fEnabled = false;
648	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
649	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
650	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
651	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
652
653	/* Fill in all callbacks with placeholders. */
654	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
655	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
656	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
657	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
658	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
659	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
660	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
661	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
662	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
663
664	/* Default is global VT-x/AMD-V init. */
665	g_HvmR0.fGlobalInit = true;
666
667	/*
668	* Make sure aCpuInfo is big enough for all the CPUs on this system.
669	*/
670	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
671	{
672	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
673	return VERR_TOO_MANY_CPUS;
674	}
675
676	/*
677	* Check for VT-x and AMD-V capabilities.
678	*/
679	int rc;
680	if (ASMHasCpuId())
681	{
682	/* Standard features. */
683	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
684	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
685	if (ASMIsValidStdRange(uMaxLeaf))
686	{
687	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
688	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
689
690	/* Query AMD features. */
691	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
692	if (ASMIsValidExtRange(uMaxExtLeaf))
693	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
694	&g_HvmR0.cpuid.u32AMDFeatureECX,
695	&g_HvmR0.cpuid.u32AMDFeatureEDX);
696	else
697	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
698
699	/* Go to CPU specific initialization code. */
700	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
701	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
702	{
703	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
704	if (RT_FAILURE(rc))
705	return rc;
706	}
707	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
708	{
709	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
710	if (RT_FAILURE(rc))
711	return rc;
712	}
713	else
714	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
715	}
716	else
717	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
718	}
719	else
720	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
721
722	/*
723	* Register notification callbacks that we can use to disable/enable CPUs
724	* when brought offline/online or suspending/resuming.
725	*/
726	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
727	{
728	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
729	AssertRC(rc);
730
731	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
732	AssertRC(rc);
733	}
734
735	/* We return success here because module init shall not fail if HM
736	fails to initialize. */
737	return VINF_SUCCESS;
738	}
739
740
741	/**
742	* Does global Ring-0 HM termination (at module termination).
743	*
744	* @returns VBox status code.
745	*/
746	VMMR0_INT_DECL(int) HMR0Term(void)
747	{
748	int rc;
749	if ( g_HvmR0.vmx.fSupported
750	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
751	{
752	/*
753	* Simple if the host OS manages VT-x.
754	*/
755	Assert(g_HvmR0.fGlobalInit);
756	rc = SUPR0EnableVTx(false /* fEnable */);
757
758	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
759	{
760	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
761	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
762	}
763	}
764	else
765	{
766	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
767	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
768	{
769	/* Doesn't really matter if this fails. */
770	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
771	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
772	}
773	else
774	rc = VINF_SUCCESS;
775
776	/*
777	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
778	*/
779	if (g_HvmR0.fGlobalInit)
780	{
781	HMR0FIRSTRC FirstRc;
782	hmR0FirstRcInit(&FirstRc);
783	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
784	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
785	if (RT_SUCCESS(rc))
786	{
787	rc = hmR0FirstRcGetStatus(&FirstRc);
788	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
789	}
790	}
791
792	/*
793	* Free the per-cpu pages used for VT-x and AMD-V.
794	*/
795	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
796	{
797	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
798	{
799	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
800	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
801	}
802	}
803	}
804
805	/** @todo This needs cleaning up. There's no matching
806	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
807	* should move into their respective modules. */
808	/* Finally, call global VT-x/AMD-V termination. */
809	if (g_HvmR0.vmx.fSupported)
810	VMXR0GlobalTerm();
811	else if (g_HvmR0.svm.fSupported)
812	SVMR0GlobalTerm();
813
814	return rc;
815	}
816
817
818	/**
819	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
820	* VT-x on a CPU.
821	*
822	* @param idCpu The identifier for the CPU the function is called on.
823	* @param pvUser1 Pointer to the first RC structure.
824	* @param pvUser2 Ignored.
825	*/
826	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
827	{
828	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
829	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
830	NOREF(pvUser2);
831
832	/*
833	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
834	* Once the lock bit is set, this MSR can no longer be modified.
835	*/
836	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
837	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
838	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
839	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
840	)
841	{
842	/* MSR is not yet locked; we can change it ourselves here. */
843	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
844	g_HvmR0.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
845	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
846	}
847
848	int rc;
849	if ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
850	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
851	rc = VINF_SUCCESS;
852	else
853	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
854
855	hmR0FirstRcSetStatus(pFirstRc, rc);
856	}
857
858
859	/**
860	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
861	* on a CPU.
862	*
863	* @param idCpu The identifier for the CPU the function is called on.
864	* @param pvUser1 Pointer to the first RC structure.
865	* @param pvUser2 Ignored.
866	*/
867	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
868	{
869	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
870	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
871	NOREF(pvUser2);
872
873	/* Check if SVM is disabled. */
874	int rc;
875	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
876	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
877	{
878	/* Turn on SVM in the EFER MSR. */
879	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
880	if (fEfer & MSR_K6_EFER_SVME)
881	rc = VERR_SVM_IN_USE;
882	else
883	{
884	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
885
886	/* Paranoia. */
887	fEfer = ASMRdMsr(MSR_K6_EFER);
888	if (fEfer & MSR_K6_EFER_SVME)
889	{
890	/* Restore previous value. */
891	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
892	rc = VINF_SUCCESS;
893	}
894	else
895	rc = VERR_SVM_ILLEGAL_EFER_MSR;
896	}
897	}
898	else
899	rc = VERR_SVM_DISABLED;
900
901	hmR0FirstRcSetStatus(pFirstRc, rc);
902	}
903
904
905	/**
906	* Enable VT-x or AMD-V on the current CPU
907	*
908	* @returns VBox status code.
909	* @param pVM Pointer to the VM (can be 0).
910	* @param idCpu The identifier for the CPU the function is called on.
911	*/
912	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
913	{
914	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
915
916	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
917	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
918	Assert(!pCpu->fConfigured);
919
920	pCpu->idCpu = idCpu;
921	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
922	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
923
924	int rc;
925	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
926	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL, NIL_RTHCPHYS, true);
927	else
928	{
929	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
930	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
931	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
932	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
933	}
934	AssertRC(rc);
935	if (RT_SUCCESS(rc))
936	pCpu->fConfigured = true;
937
938	return rc;
939	}
940
941
942	/**
943	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
944	* is to be called on the target cpus.
945	*
946	* @param idCpu The identifier for the CPU the function is called on.
947	* @param pvUser1 The 1st user argument.
948	* @param pvUser2 The 2nd user argument.
949	*/
950	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
951	{
952	PVM pVM = (PVM)pvUser1; /* can be NULL! */
953	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
954	AssertReturnVoid(g_HvmR0.fGlobalInit);
955	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
956	}
957
958
959	/**
960	* RTOnce callback employed by HMR0EnableAllCpus.
961	*
962	* @returns VBox status code.
963	* @param pvUser Pointer to the VM.
964	* @param pvUserIgnore NULL, ignored.
965	*/
966	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
967	{
968	PVM pVM = (PVM)pvUser;
969
970	/*
971	* Indicate that we've initialized.
972	*
973	* Note! There is a potential race between this function and the suspend
974	* notification. Kind of unlikely though, so ignored for now.
975	*/
976	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
977	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
978
979	/*
980	* The global init variable is set by the first VM.
981	*/
982	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
983
984	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
985	{
986	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
987	g_HvmR0.aCpuInfo[i].fConfigured = false;
988	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
989	g_HvmR0.aCpuInfo[i].uCurrentAsid = 0;
990	}
991
992	int rc;
993	if ( g_HvmR0.vmx.fSupported
994	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
995	{
996	/*
997	* Global VT-x initialization API (only darwin for now).
998	*/
999	rc = SUPR0EnableVTx(true /* fEnable */);
1000	if (RT_SUCCESS(rc))
1001	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
1002	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
1003	else
1004	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
1005	}
1006	else
1007	{
1008	/*
1009	* We're doing the job ourselves.
1010	*/
1011	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
1012	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1013	{
1014	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1015
1016	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1017	{
1018	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1019	AssertLogRelRCReturn(rc, rc);
1020
1021	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1022	ASMMemZeroPage(pvR0);
1023	}
1024	}
1025
1026	rc = VINF_SUCCESS;
1027	}
1028
1029	if ( RT_SUCCESS(rc)
1030	&& g_HvmR0.fGlobalInit)
1031	{
1032	/* First time, so initialize each cpu/core. */
1033	HMR0FIRSTRC FirstRc;
1034	hmR0FirstRcInit(&FirstRc);
1035	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1036	if (RT_SUCCESS(rc))
1037	rc = hmR0FirstRcGetStatus(&FirstRc);
1038	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1039	}
1040
1041	return rc;
1042	}
1043
1044
1045	/**
1046	* Sets up HM on all cpus.
1047	*
1048	* @returns VBox status code.
1049	* @param pVM Pointer to the VM.
1050	*/
1051	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1052	{
1053	/* Make sure we don't touch HM after we've disabled HM in
1054	preparation of a suspend. */
1055	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1056	return VERR_HM_SUSPEND_PENDING;
1057
1058	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1059	}
1060
1061
1062	/**
1063	* Disable VT-x or AMD-V on the current CPU.
1064	*
1065	* @returns VBox status code.
1066	* @param idCpu The identifier for the CPU the function is called on.
1067	*/
1068	static int hmR0DisableCpu(RTCPUID idCpu)
1069	{
1070	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1071
1072	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1073	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1074	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1075	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1076
1077	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1078	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1079
1080	int rc;
1081	if (pCpu->fConfigured)
1082	{
1083	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1084	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1085	if (idCpu == RTMpCpuId())
1086	{
1087	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1088	AssertRC(rc);
1089	}
1090	else
1091	{
1092	pCpu->fIgnoreAMDVInUseError = true;
1093	rc = VINF_SUCCESS;
1094	}
1095
1096	pCpu->fConfigured = false;
1097	}
1098	else
1099	rc = VINF_SUCCESS; /* nothing to do */
1100
1101	pCpu->uCurrentAsid = 0;
1102	return rc;
1103	}
1104
1105
1106	/**
1107	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1108	* is to be called on the target cpus.
1109	*
1110	* @param idCpu The identifier for the CPU the function is called on.
1111	* @param pvUser1 The 1st user argument.
1112	* @param pvUser2 The 2nd user argument.
1113	*/
1114	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1115	{
1116	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1117	AssertReturnVoid(g_HvmR0.fGlobalInit);
1118	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1119	}
1120
1121
1122	/**
1123	* Callback function invoked when a cpu goes online or offline.
1124	*
1125	* @param enmEvent The Mp event.
1126	* @param idCpu The identifier for the CPU the function is called on.
1127	* @param pvData Opaque data (PVM pointer).
1128	*/
1129	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1130	{
1131	NOREF(pvData);
1132
1133	/*
1134	* We only care about uninitializing a CPU that is going offline. When a
1135	* CPU comes online, the initialization is done lazily in HMR0Enter().
1136	*/
1137	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1138	switch (enmEvent)
1139	{
1140	case RTMPEVENT_OFFLINE:
1141	{
1142	int rc = hmR0DisableCpu(idCpu);
1143	AssertRC(rc);
1144	break;
1145	}
1146
1147	default:
1148	break;
1149	}
1150	}
1151
1152
1153	/**
1154	* Called whenever a system power state change occurs.
1155	*
1156	* @param enmEvent The Power event.
1157	* @param pvUser User argument.
1158	*/
1159	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1160	{
1161	NOREF(pvUser);
1162	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1163
1164	#ifdef LOG_ENABLED
1165	if (enmEvent == RTPOWEREVENT_SUSPEND)
1166	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1167	else
1168	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1169	#endif
1170
1171	if (enmEvent == RTPOWEREVENT_SUSPEND)
1172	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1173
1174	if (g_HvmR0.fEnabled)
1175	{
1176	int rc;
1177	HMR0FIRSTRC FirstRc;
1178	hmR0FirstRcInit(&FirstRc);
1179
1180	if (enmEvent == RTPOWEREVENT_SUSPEND)
1181	{
1182	if (g_HvmR0.fGlobalInit)
1183	{
1184	/* Turn off VT-x or AMD-V on all CPUs. */
1185	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
1186	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1187	}
1188	/* else nothing to do here for the local init case */
1189	}
1190	else
1191	{
1192	/* Reinit the CPUs from scratch as the suspend state might have
1193	messed with the MSRs. (lousy BIOSes as usual) */
1194	if (g_HvmR0.vmx.fSupported)
1195	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1196	else
1197	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1198	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1199	if (RT_SUCCESS(rc))
1200	rc = hmR0FirstRcGetStatus(&FirstRc);
1201	#ifdef LOG_ENABLED
1202	if (RT_FAILURE(rc))
1203	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1204	#endif
1205	if (g_HvmR0.fGlobalInit)
1206	{
1207	/* Turn VT-x or AMD-V back on on all CPUs. */
1208	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
1209	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1210	}
1211	/* else nothing to do here for the local init case */
1212	}
1213	}
1214
1215	if (enmEvent == RTPOWEREVENT_RESUME)
1216	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1217	}
1218
1219
1220	/**
1221	* Does Ring-0 per VM HM initialization.
1222	*
1223	* This will copy HM global into the VM structure and call the CPU specific
1224	* init routine which will allocate resources for each virtual CPU and such.
1225	*
1226	* @returns VBox status code.
1227	* @param pVM Pointer to the VM.
1228	*/
1229	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1230	{
1231	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1232
1233	#ifdef LOG_ENABLED
1234	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1235	#endif
1236
1237	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1238	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1239	return VERR_HM_SUSPEND_PENDING;
1240
1241	/*
1242	* Copy globals to the VM structure.
1243	*/
1244	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1245	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1246
1247	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1248	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1249	pVM->hm.s.vmx.msr.feature_ctrl = g_HvmR0.vmx.msr.feature_ctrl;
1250	pVM->hm.s.vmx.hostCR4 = g_HvmR0.vmx.hostCR4;
1251	pVM->hm.s.vmx.hostEFER = g_HvmR0.vmx.hostEFER;
1252	pVM->hm.s.vmx.msr.vmx_basic_info = g_HvmR0.vmx.msr.vmx_basic_info;
1253	pVM->hm.s.vmx.msr.vmx_pin_ctls = g_HvmR0.vmx.msr.vmx_pin_ctls;
1254	pVM->hm.s.vmx.msr.vmx_proc_ctls = g_HvmR0.vmx.msr.vmx_proc_ctls;
1255	pVM->hm.s.vmx.msr.vmx_proc_ctls2 = g_HvmR0.vmx.msr.vmx_proc_ctls2;
1256	pVM->hm.s.vmx.msr.vmx_exit = g_HvmR0.vmx.msr.vmx_exit;
1257	pVM->hm.s.vmx.msr.vmx_entry = g_HvmR0.vmx.msr.vmx_entry;
1258	pVM->hm.s.vmx.msr.vmx_misc = g_HvmR0.vmx.msr.vmx_misc;
1259	pVM->hm.s.vmx.msr.vmx_cr0_fixed0 = g_HvmR0.vmx.msr.vmx_cr0_fixed0;
1260	pVM->hm.s.vmx.msr.vmx_cr0_fixed1 = g_HvmR0.vmx.msr.vmx_cr0_fixed1;
1261	pVM->hm.s.vmx.msr.vmx_cr4_fixed0 = g_HvmR0.vmx.msr.vmx_cr4_fixed0;
1262	pVM->hm.s.vmx.msr.vmx_cr4_fixed1 = g_HvmR0.vmx.msr.vmx_cr4_fixed1;
1263	pVM->hm.s.vmx.msr.vmx_vmcs_enum = g_HvmR0.vmx.msr.vmx_vmcs_enum;
1264	pVM->hm.s.vmx.msr.vmx_vmfunc = g_HvmR0.vmx.msr.vmx_vmfunc;
1265	pVM->hm.s.vmx.msr.vmx_ept_vpid_caps = g_HvmR0.vmx.msr.vmx_ept_vpid_caps;
1266	pVM->hm.s.svm.msrHwcr = g_HvmR0.svm.msrHwcr;
1267	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1268	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1269	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1270	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1271	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1272
1273	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1274
1275
1276	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1277	{
1278	pVM->hm.s.cMaxResumeLoops = 1024;
1279	if (RTThreadPreemptIsPendingTrusty())
1280	pVM->hm.s.cMaxResumeLoops = 8192;
1281	}
1282
1283	/*
1284	* Initialize some per CPU fields.
1285	*/
1286	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1287	{
1288	PVMCPU pVCpu = &pVM->aCpus[i];
1289
1290	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1291
1292	/* Invalidate the last cpu we were running on. */
1293	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1294
1295	/* We'll aways increment this the first time (host uses ASID 0) */
1296	pVCpu->hm.s.uCurrentAsid = 0;
1297	}
1298
1299	/*
1300	* Call the hardware specific initialization method.
1301	*/
1302	RTCCUINTREG fFlags = ASMIntDisableFlags();
1303	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1304	ASMSetFlags(fFlags);
1305
1306	int rc = g_HvmR0.pfnInitVM(pVM);
1307	return rc;
1308	}
1309
1310
1311	/**
1312	* Does Ring-0 per VM HM termination.
1313	*
1314	* @returns VBox status code.
1315	* @param pVM Pointer to the VM.
1316	*/
1317	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1318	{
1319	Log(("HMR0TermVM: %p\n", pVM));
1320	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1321
1322	/* Make sure we don't touch HM after we've disabled HM in preparation
1323	of a suspend. */
1324	/** @todo r=bird: This cannot be right, the termination functions are
1325	* just freeing memory and resetting pVM/pVCpu members...
1326	* ==> memory leak. */
1327	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1328
1329	/*
1330	* Call the hardware specific method.
1331	*/
1332	RTCCUINTREG fFlags = ASMIntDisableFlags();
1333	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1334	ASMSetFlags(fFlags);
1335
1336	int rc = g_HvmR0.pfnTermVM(pVM);
1337	return rc;
1338	}
1339
1340
1341	/**
1342	* Sets up a VT-x or AMD-V session.
1343	*
1344	* This is mostly about setting up the hardware VM state.
1345	*
1346	* @returns VBox status code.
1347	* @param pVM Pointer to the VM.
1348	*/
1349	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1350	{
1351	Log(("HMR0SetupVM: %p\n", pVM));
1352	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1353
1354	/* Make sure we don't touch HM after we've disabled HM in
1355	preparation of a suspend. */
1356	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1357
1358	/*
1359	* Call the hardware specific setup VM method. This requires the CPU to be
1360	* enabled for AMD-V/VT-x and preemption to be prevented.
1361	*/
1362	RTCCUINTREG fFlags = ASMIntDisableFlags();
1363	RTCPUID idCpu = RTMpCpuId();
1364	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1365
1366	/* On first entry we'll sync everything. */
1367	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1368	pVM->aCpus[i].hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1369
1370	/* Enable VT-x or AMD-V if local init is required. */
1371	int rc;
1372	if (!g_HvmR0.fGlobalInit)
1373	{
1374	rc = hmR0EnableCpu(pVM, idCpu);
1375	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1376	}
1377
1378	/* Setup VT-x or AMD-V. */
1379	rc = g_HvmR0.pfnSetupVM(pVM);
1380
1381	/* Disable VT-x or AMD-V if local init was done before. */
1382	if (!g_HvmR0.fGlobalInit)
1383	{
1384	int rc2 = hmR0DisableCpu(idCpu);
1385	AssertRC(rc2);
1386	}
1387
1388	ASMSetFlags(fFlags);
1389	return rc;
1390	}
1391
1392
1393	/**
1394	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1395	* required for entering HM context.
1396	*
1397	* @returns VBox status code.
1398	* @param pvCpu Pointer to the VMCPU.
1399	*
1400	* @remarks No-long-jump zone!!!
1401	*/
1402	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1403	{
1404	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1405
1406	int rc = VINF_SUCCESS;
1407	RTCPUID idCpu = RTMpCpuId();
1408	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1409	AssertPtr(pCpu);
1410
1411	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1412	if (!pCpu->fConfigured)
1413	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1414
1415	/* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
1416	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE;
1417	pVCpu->hm.s.idEnteredCpu = idCpu;
1418	return rc;
1419	}
1420
1421
1422	/**
1423	* Enters the VT-x or AMD-V session.
1424	*
1425	* @returns VBox status code.
1426	* @param pVM Pointer to the VM.
1427	* @param pVCpu Pointer to the VMCPU.
1428	*
1429	* @remarks This is called with preemption disabled.
1430	*/
1431	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1432	{
1433	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1434	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1435	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1436
1437	/* Load the bare minimum state required for entering HM. */
1438	int rc = HMR0EnterCpu(pVCpu);
1439	AssertRCReturn(rc, rc);
1440
1441	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1442	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1443	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1444	#endif
1445
1446	RTCPUID idCpu = RTMpCpuId();
1447	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1448	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1449	Assert(pCpu);
1450	Assert(pCtx);
1451	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1452
1453	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1454	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1455
1456	/* Load the host as we may be resuming code after a longjmp and quite
1457	possibly now be scheduled on a different CPU. */
1458	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1459	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1460
1461	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1462	if (fStartedSet)
1463	PGMRZDynMapReleaseAutoSet(pVCpu);
1464	#endif
1465
1466	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1467	and ring-3 calls. */
1468	if (RT_FAILURE(rc))
1469	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1470	return rc;
1471	}
1472
1473
1474	/**
1475	* Deinitializes the bare minimum state used for HM context and if necessary
1476	* disable HM on the CPU.
1477	*
1478	* @returns VBox status code.
1479	* @param pVCpu Pointer to the VMCPU.
1480	*
1481	* @remarks No-long-jump zone!!!
1482	*/
1483	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1484	{
1485	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1486
1487	RTCPUID idCpu = RTMpCpuId();
1488	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1489
1490	if ( !g_HvmR0.fGlobalInit
1491	&& pCpu->fConfigured)
1492	{
1493	int rc = hmR0DisableCpu(idCpu);
1494	AssertRCReturn(rc, rc);
1495	Assert(!pCpu->fConfigured);
1496	}
1497
1498	/* Reset these to force a TLB flush for the next entry. */
1499	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1500	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1501	pVCpu->hm.s.uCurrentAsid = 0;
1502	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1503
1504	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1505	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1506
1507	return VINF_SUCCESS;
1508	}
1509
1510
1511	/**
1512	* Thread-context hook for HM.
1513	*
1514	* @param enmEvent The thread-context event.
1515	* @param pvUser Opaque pointer to the VMCPU.
1516	*/
1517	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1518	{
1519	PVMCPU pVCpu = (PVMCPU)pvUser;
1520	Assert(pVCpu);
1521	Assert(g_HvmR0.pfnThreadCtxCallback);
1522
1523	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1524	}
1525
1526
1527	/**
1528	* Runs guest code in a hardware accelerated VM.
1529	*
1530	* @returns VBox status code.
1531	* @param pVM Pointer to the VM.
1532	* @param pVCpu Pointer to the VMCPU.
1533	*
1534	* @remarks Called with preemption disabled and after first having called
1535	* HMR0Enter.
1536	*/
1537	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1538	{
1539	#ifdef VBOX_STRICT
1540	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1541	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1542	Assert(pCpu->fConfigured);
1543	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1544	#endif
1545
1546	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1547	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1548	PGMRZDynMapStartAutoSet(pVCpu);
1549	#endif
1550
1551	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1552
1553	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1554	PGMRZDynMapReleaseAutoSet(pVCpu);
1555	#endif
1556	return rc;
1557	}
1558
1559	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1560
1561	/**
1562	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1563	*
1564	* @returns VBox status code.
1565	* @param pVM Pointer to the VM.
1566	* @param pVCpu Pointer to the VMCPU.
1567	* @param pCtx Pointer to the guest CPU context.
1568	*/
1569	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1570	{
1571	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1572	if (pVM->hm.s.vmx.fSupported)
1573	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1574	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1575	}
1576
1577
1578	/**
1579	* Save guest debug state (64 bits guest mode & 32 bits host only)
1580	*
1581	* @returns VBox status code.
1582	* @param pVM Pointer to the VM.
1583	* @param pVCpu Pointer to the VMCPU.
1584	* @param pCtx Pointer to the guest CPU context.
1585	*/
1586	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1587	{
1588	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1589	if (pVM->hm.s.vmx.fSupported)
1590	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1591	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1592	}
1593
1594
1595	/**
1596	* Test the 32->64 bits switcher.
1597	*
1598	* @returns VBox status code.
1599	* @param pVM Pointer to the VM.
1600	*/
1601	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1602	{
1603	PVMCPU pVCpu = &pVM->aCpus[0];
1604	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1605	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1606	int rc;
1607
1608	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1609	if (pVM->hm.s.vmx.fSupported)
1610	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1611	else
1612	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1613	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1614
1615	return rc;
1616	}
1617
1618	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1619
1620	/**
1621	* Returns suspend status of the host.
1622	*
1623	* @returns Suspend pending or not.
1624	*/
1625	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1626	{
1627	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1628	}
1629
1630
1631	/**
1632	* Returns the cpu structure for the current cpu.
1633	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1634	*
1635	* @returns The cpu structure pointer.
1636	*/
1637	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1638	{
1639	RTCPUID idCpu = RTMpCpuId();
1640	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1641	return &g_HvmR0.aCpuInfo[idCpu];
1642	}
1643
1644
1645	/**
1646	* Returns the cpu structure for the current cpu.
1647	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1648	*
1649	* @returns The cpu structure pointer.
1650	* @param idCpu id of the VCPU.
1651	*/
1652	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1653	{
1654	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1655	return &g_HvmR0.aCpuInfo[idCpu];
1656	}
1657
1658
1659	/**
1660	* Save a pending IO read.
1661	*
1662	* @param pVCpu Pointer to the VMCPU.
1663	* @param GCPtrRip Address of IO instruction.
1664	* @param GCPtrRipNext Address of the next instruction.
1665	* @param uPort Port address.
1666	* @param uAndVal AND mask for saving the result in eax.
1667	* @param cbSize Read size.
1668	*/
1669	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1670	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1671	{
1672	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1673	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1674	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1675	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1676	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1677	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1678	return;
1679	}
1680
1681
1682	/**
1683	* Save a pending IO write.
1684	*
1685	* @param pVCpu Pointer to the VMCPU.
1686	* @param GCPtrRIP Address of IO instruction.
1687	* @param uPort Port address.
1688	* @param uAndVal AND mask for fetching the result from eax.
1689	* @param cbSize Read size.
1690	*/
1691	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1692	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1693	{
1694	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1695	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1696	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1697	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1698	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1699	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1700	return;
1701	}
1702
1703
1704	/**
1705	* Raw-mode switcher hook - disable VT-x if it's active and the current
1706	* switcher turns off paging.
1707	*
1708	* @returns VBox status code.
1709	* @param pVM Pointer to the VM.
1710	* @param enmSwitcher The switcher we're about to use.
1711	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1712	*/
1713	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1714	{
1715	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1716
1717	*pfVTxDisabled = false;
1718
1719	/* No such issues with AMD-V */
1720	if (!g_HvmR0.vmx.fSupported)
1721	return VINF_SUCCESS;
1722
1723	/* Check if the swithcing we're up to is safe. */
1724	switch (enmSwitcher)
1725	{
1726	case VMMSWITCHER_32_TO_32:
1727	case VMMSWITCHER_PAE_TO_PAE:
1728	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1729
1730	case VMMSWITCHER_32_TO_PAE:
1731	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1732	case VMMSWITCHER_AMD64_TO_32:
1733	case VMMSWITCHER_AMD64_TO_PAE:
1734	break; /* unsafe switchers */
1735
1736	default:
1737	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1738	}
1739
1740	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1741	regardless of whether we're currently using VT-x or not. */
1742	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1743	{
1744	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1745	return VINF_SUCCESS;
1746	}
1747
1748	/** @todo Check if this code is presumtive wrt other VT-x users on the
1749	* system... */
1750
1751	/* Nothing to do if we haven't enabled VT-x. */
1752	if (!g_HvmR0.fEnabled)
1753	return VINF_SUCCESS;
1754
1755	/* Local init implies the CPU is currently not in VMX root mode. */
1756	if (!g_HvmR0.fGlobalInit)
1757	return VINF_SUCCESS;
1758
1759	/* Ok, disable VT-x. */
1760	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1761	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1762
1763	*pfVTxDisabled = true;
1764	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1765	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1766	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1767	}
1768
1769
1770	/**
1771	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1772	* switcher turned off paging.
1773	*
1774	* @param pVM Pointer to the VM.
1775	* @param fVTxDisabled Whether VT-x was disabled or not.
1776	*/
1777	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1778	{
1779	Assert(!(ASMGetFlags() & X86_EFL_IF));
1780
1781	if (!fVTxDisabled)
1782	return; /* nothing to do */
1783
1784	Assert(g_HvmR0.vmx.fSupported);
1785	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1786	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1787	else
1788	{
1789	Assert(g_HvmR0.fEnabled);
1790	Assert(g_HvmR0.fGlobalInit);
1791
1792	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1793	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1794
1795	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1796	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1797	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
1798	}
1799	}
1800
1801	#ifdef VBOX_STRICT
1802
1803	/**
1804	* Dumps a descriptor.
1805	*
1806	* @param pDesc Descriptor to dump.
1807	* @param Sel Selector number.
1808	* @param pszMsg Message to prepend the log entry with.
1809	*/
1810	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1811	{
1812	/*
1813	* Make variable description string.
1814	*/
1815	static struct
1816	{
1817	unsigned cch;
1818	const char *psz;
1819	} const s_aTypes[32] =
1820	{
1821	# define STRENTRY(str) { sizeof(str) - 1, str }
1822
1823	/* system */
1824	# if HC_ARCH_BITS == 64
1825	STRENTRY("Reserved0 "), /* 0x00 */
1826	STRENTRY("Reserved1 "), /* 0x01 */
1827	STRENTRY("LDT "), /* 0x02 */
1828	STRENTRY("Reserved3 "), /* 0x03 */
1829	STRENTRY("Reserved4 "), /* 0x04 */
1830	STRENTRY("Reserved5 "), /* 0x05 */
1831	STRENTRY("Reserved6 "), /* 0x06 */
1832	STRENTRY("Reserved7 "), /* 0x07 */
1833	STRENTRY("Reserved8 "), /* 0x08 */
1834	STRENTRY("TSS64Avail "), /* 0x09 */
1835	STRENTRY("ReservedA "), /* 0x0a */
1836	STRENTRY("TSS64Busy "), /* 0x0b */
1837	STRENTRY("Call64 "), /* 0x0c */
1838	STRENTRY("ReservedD "), /* 0x0d */
1839	STRENTRY("Int64 "), /* 0x0e */
1840	STRENTRY("Trap64 "), /* 0x0f */
1841	# else
1842	STRENTRY("Reserved0 "), /* 0x00 */
1843	STRENTRY("TSS16Avail "), /* 0x01 */
1844	STRENTRY("LDT "), /* 0x02 */
1845	STRENTRY("TSS16Busy "), /* 0x03 */
1846	STRENTRY("Call16 "), /* 0x04 */
1847	STRENTRY("Task "), /* 0x05 */
1848	STRENTRY("Int16 "), /* 0x06 */
1849	STRENTRY("Trap16 "), /* 0x07 */
1850	STRENTRY("Reserved8 "), /* 0x08 */
1851	STRENTRY("TSS32Avail "), /* 0x09 */
1852	STRENTRY("ReservedA "), /* 0x0a */
1853	STRENTRY("TSS32Busy "), /* 0x0b */
1854	STRENTRY("Call32 "), /* 0x0c */
1855	STRENTRY("ReservedD "), /* 0x0d */
1856	STRENTRY("Int32 "), /* 0x0e */
1857	STRENTRY("Trap32 "), /* 0x0f */
1858	# endif
1859	/* non system */
1860	STRENTRY("DataRO "), /* 0x10 */
1861	STRENTRY("DataRO Accessed "), /* 0x11 */
1862	STRENTRY("DataRW "), /* 0x12 */
1863	STRENTRY("DataRW Accessed "), /* 0x13 */
1864	STRENTRY("DataDownRO "), /* 0x14 */
1865	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1866	STRENTRY("DataDownRW "), /* 0x16 */
1867	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1868	STRENTRY("CodeEO "), /* 0x18 */
1869	STRENTRY("CodeEO Accessed "), /* 0x19 */
1870	STRENTRY("CodeER "), /* 0x1a */
1871	STRENTRY("CodeER Accessed "), /* 0x1b */
1872	STRENTRY("CodeConfEO "), /* 0x1c */
1873	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1874	STRENTRY("CodeConfER "), /* 0x1e */
1875	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1876	# undef SYSENTRY
1877	};
1878	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1879	char szMsg[128];
1880	char *psz = &szMsg[0];
1881	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1882	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1883	psz += s_aTypes[i].cch;
1884
1885	if (pDesc->Gen.u1Present)
1886	ADD_STR(psz, "Present ");
1887	else
1888	ADD_STR(psz, "Not-Present ");
1889	# if HC_ARCH_BITS == 64
1890	if (pDesc->Gen.u1Long)
1891	ADD_STR(psz, "64-bit ");
1892	else
1893	ADD_STR(psz, "Comp ");
1894	# else
1895	if (pDesc->Gen.u1Granularity)
1896	ADD_STR(psz, "Page ");
1897	if (pDesc->Gen.u1DefBig)
1898	ADD_STR(psz, "32-bit ");
1899	else
1900	ADD_STR(psz, "16-bit ");
1901	# endif
1902	# undef ADD_STR
1903	*psz = '\0';
1904
1905	/*
1906	* Limit and Base and format the output.
1907	*/
1908	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1909
1910	# if HC_ARCH_BITS == 64
1911	uint64_t u32Base = X86DESC64_BASE(pDesc);
1912
1913	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1914	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1915	# else
1916	uint32_t u32Base = X86DESC_BASE(pDesc);
1917
1918	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1919	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1920	# endif
1921	}
1922
1923
1924	/**
1925	* Formats a full register dump.
1926	*
1927	* @param pVM Pointer to the VM.
1928	* @param pVCpu Pointer to the VMCPU.
1929	* @param pCtx Pointer to the CPU context.
1930	*/
1931	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1932	{
1933	NOREF(pVM);
1934
1935	/*
1936	* Format the flags.
1937	*/
1938	static struct
1939	{
1940	const char pszSet; const char pszClear; uint32_t fFlag;
1941	} const s_aFlags[] =
1942	{
1943	{ "vip",NULL, X86_EFL_VIP },
1944	{ "vif",NULL, X86_EFL_VIF },
1945	{ "ac", NULL, X86_EFL_AC },
1946	{ "vm", NULL, X86_EFL_VM },
1947	{ "rf", NULL, X86_EFL_RF },
1948	{ "nt", NULL, X86_EFL_NT },
1949	{ "ov", "nv", X86_EFL_OF },
1950	{ "dn", "up", X86_EFL_DF },
1951	{ "ei", "di", X86_EFL_IF },
1952	{ "tf", NULL, X86_EFL_TF },
1953	{ "nt", "pl", X86_EFL_SF },
1954	{ "nz", "zr", X86_EFL_ZF },
1955	{ "ac", "na", X86_EFL_AF },
1956	{ "po", "pe", X86_EFL_PF },
1957	{ "cy", "nc", X86_EFL_CF },
1958	};
1959	char szEFlags[80];
1960	char *psz = szEFlags;
1961	uint32_t efl = pCtx->eflags.u32;
1962	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1963	{
1964	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1965	if (pszAdd)
1966	{
1967	strcpy(psz, pszAdd);
1968	psz += strlen(pszAdd);
1969	*psz++ = ' ';
1970	}
1971	}
1972	psz[-1] = '\0';
1973
1974
1975	/*
1976	* Format the registers.
1977	*/
1978	if (CPUMIsGuestIn64BitCode(pVCpu))
1979	{
1980	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1981	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1982	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1983	"r14=%016RX64 r15=%016RX64\n"
1984	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1985	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1986	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1987	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1988	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1989	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1990	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1991	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1992	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1993	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1994	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1995	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1996	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1997	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1998	,
1999	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
2000	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
2001	pCtx->r14, pCtx->r15,
2002	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2003	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2004	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2005	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2006	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2007	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2008	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2009	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
2010	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
2011	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2012	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2013	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2014	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2015	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2016	}
2017	else
2018	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2019	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2020	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2021	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2022	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2023	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2024	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2025	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2026	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2027	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2028	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2029	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2030	,
2031	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2032	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2033	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2034	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2035	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2036	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2037	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2038	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2039	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2040	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2041	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2042	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2043
2044	Log(("FPU:\n"
2045	"FCW=%04x FSW=%04x FTW=%02x\n"
2046	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2047	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2048	,
2049	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2050	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2051	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2052	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2053
2054
2055	Log(("MSR:\n"
2056	"EFER =%016RX64\n"
2057	"PAT =%016RX64\n"
2058	"STAR =%016RX64\n"
2059	"CSTAR =%016RX64\n"
2060	"LSTAR =%016RX64\n"
2061	"SFMASK =%016RX64\n"
2062	"KERNELGSBASE =%016RX64\n",
2063	pCtx->msrEFER,
2064	pCtx->msrPAT,
2065	pCtx->msrSTAR,
2066	pCtx->msrCSTAR,
2067	pCtx->msrLSTAR,
2068	pCtx->msrSFMASK,
2069	pCtx->msrKERNELGSBASE));
2070
2071	}
2072
2073	#endif /* VBOX_STRICT */
2074

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 48201

Download in other formats: