HMR0.cpp@ 48209

Last change on this file since 48209 was 48209, checked in by vboxsync, 11 years ago
VMM: Apparently we use underscores in unions/structs in other places. Revert.
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1	/* $Id: HMR0.cpp 48209 2013-08-30 22:13:19Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	uint64_t u64HostCr4;
117
118	/** Host EFER value (set by ring-0 VMX init) */
119	uint64_t u64HostEfer;
120
121	/** VMX MSR values */
122	struct
123	{
124	uint64_t u64FeatureCtrl;
125	uint64_t u64BasicInfo;
126	VMX_CAPABILITY vmxPinCtls;
127	VMX_CAPABILITY vmxProcCtls;
128	VMX_CAPABILITY vmxProcCtls2;
129	VMX_CAPABILITY vmxExit;
130	VMX_CAPABILITY vmxEntry;
131	uint64_t u64Misc;
132	uint64_t u64Cr0Fixed0;
133	uint64_t u64Cr0Fixed1;
134	uint64_t u64Cr4Fixed0;
135	uint64_t u64Cr4Fixed1;
136	uint64_t u64VmcsEnum;
137	uint64_t u64Vmfunc;
138	uint64_t u64EptVpidCaps;
139	} msr;
140	/* Last instruction error */
141	uint32_t ulLastInstrError;
142	} vmx;
143
144	/** AMD-V information. */
145	struct
146	{
147	/* HWCR MSR (for diagnostics) */
148	uint64_t msrHwcr;
149
150	/** SVM revision. */
151	uint32_t u32Rev;
152
153	/** SVM feature bits from cpuid 0x8000000a */
154	uint32_t u32Features;
155
156	/** Set by us to indicate SVM is supported by the CPU. */
157	bool fSupported;
158	} svm;
159	/** Saved error from detection */
160	int32_t lLastError;
161
162	struct
163	{
164	uint32_t u32AMDFeatureECX;
165	uint32_t u32AMDFeatureEDX;
166	} cpuid;
167
168	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
169	* enabled and disabled each time it's used to execute guest code. */
170	bool fGlobalInit;
171	/** Indicates whether the host is suspending or not. We'll refuse a few
172	* actions when the host is being suspended to speed up the suspending and
173	* avoid trouble. */
174	volatile bool fSuspended;
175
176	/** Whether we've already initialized all CPUs.
177	* @remarks We could check the EnableAllCpusOnce state, but this is
178	* simpler and hopefully easier to understand. */
179	bool fEnabled;
180	/** Serialize initialization in HMR0EnableAllCpus. */
181	RTONCE EnableAllCpusOnce;
182	} g_HvmR0;
183
184
185
186	/**
187	* Initializes a first return code structure.
188	*
189	* @param pFirstRc The structure to init.
190	*/
191	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
192	{
193	pFirstRc->rc = VINF_SUCCESS;
194	pFirstRc->idCpu = NIL_RTCPUID;
195	}
196
197
198	/**
199	* Try set the status code (success ignored).
200	*
201	* @param pFirstRc The first return code structure.
202	* @param rc The status code.
203	*/
204	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
205	{
206	if ( RT_FAILURE(rc)
207	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
208	pFirstRc->idCpu = RTMpCpuId();
209	}
210
211
212	/**
213	* Get the status code of a first return code structure.
214	*
215	* @returns The status code; VINF_SUCCESS or error status, no informational or
216	* warning errors.
217	* @param pFirstRc The first return code structure.
218	*/
219	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
220	{
221	return pFirstRc->rc;
222	}
223
224
225	#ifdef VBOX_STRICT
226	/**
227	* Get the CPU ID on which the failure status code was reported.
228	*
229	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
230	* @param pFirstRc The first return code structure.
231	*/
232	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
233	{
234	return pFirstRc->idCpu;
235	}
236	#endif /* VBOX_STRICT */
237
238
239	/** @name Dummy callback handlers.
240	* @{ */
241
242	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
243	{
244	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
245	return VINF_SUCCESS;
246	}
247
248	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
249	{
250	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
251	return VINF_SUCCESS;
252	}
253
254	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
255	{
256	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
257	}
258
259	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
260	bool fEnabledBySystem)
261	{
262	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem);
263	return VINF_SUCCESS;
264	}
265
266	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
267	{
268	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
269	return VINF_SUCCESS;
270	}
271
272	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
273	{
274	NOREF(pVM);
275	return VINF_SUCCESS;
276	}
277
278	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
279	{
280	NOREF(pVM);
281	return VINF_SUCCESS;
282	}
283
284	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
285	{
286	NOREF(pVM);
287	return VINF_SUCCESS;
288	}
289
290	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
291	{
292	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
293	return VINF_SUCCESS;
294	}
295
296	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
297	{
298	NOREF(pVM); NOREF(pVCpu);
299	return VINF_SUCCESS;
300	}
301
302	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
303	{
304	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
305	return VINF_SUCCESS;
306	}
307
308	/** @} */
309
310
311	/**
312	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
313	* Down at the Rate Specified" erratum.
314	*
315	* Errata names and related steppings:
316	* - BA86 - D0.
317	* - AAX65 - C2.
318	* - AAU65 - C2, K0.
319	* - AAO95 - B1.
320	* - AAT59 - C2.
321	* - AAK139 - D0.
322	* - AAM126 - C0, C1, D0.
323	* - AAN92 - B1.
324	* - AAJ124 - C0, D0.
325	*
326	* - AAP86 - B1.
327	*
328	* Steppings: B1, C0, C1, C2, D0, K0.
329	*
330	* @returns true if subject to it, false if not.
331	*/
332	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
333	{
334	uint32_t u = ASMCpuId_EAX(1);
335	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
336	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
337	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
338	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
339	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
340	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
341	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
342	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
343	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
344	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
345	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
346	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
347	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
348	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
349	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
350	)
351	return true;
352	return false;
353	}
354
355
356	/**
357	* Intel specific initialization code.
358	*
359	* @returns VBox status code (will only fail if out of memory).
360	*/
361	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
362	{
363	/*
364	* Check that all the required VT-x features are present.
365	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
366	*/
367	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
368	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
369	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
370	)
371	{
372	/** @todo move this into a separate function. */
373	g_HvmR0.vmx.msr.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
374
375	/*
376	* First try use native kernel API for controlling VT-x.
377	* (This is only supported by some Mac OS X kernels atm.)
378	*/
379	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
380	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
381	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
382	{
383	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
384	if (RT_SUCCESS(rc))
385	{
386	g_HvmR0.vmx.fSupported = true;
387	rc = SUPR0EnableVTx(false /* fEnable */);
388	AssertLogRelRC(rc);
389	}
390	}
391	else
392	{
393	/* We need to check if VT-x has been properly initialized on all
394	CPUs. Some BIOSes do a lousy job. */
395	HMR0FIRSTRC FirstRc;
396	hmR0FirstRcInit(&FirstRc);
397	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
398	if (RT_SUCCESS(g_HvmR0.lLastError))
399	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
400	}
401	if (RT_SUCCESS(g_HvmR0.lLastError))
402	{
403	/* Reread in case we've changed it. */
404	g_HvmR0.vmx.msr.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
405
406	if ( (g_HvmR0.vmx.msr.u64FeatureCtrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
407	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
408	{
409	/*
410	* Read all relevant MSRs.
411	*/
412	g_HvmR0.vmx.msr.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
413	g_HvmR0.vmx.msr.vmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
414	g_HvmR0.vmx.msr.vmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
415	g_HvmR0.vmx.msr.vmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
416	g_HvmR0.vmx.msr.vmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
417	g_HvmR0.vmx.msr.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
418	g_HvmR0.vmx.msr.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
419	g_HvmR0.vmx.msr.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
420	g_HvmR0.vmx.msr.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
421	g_HvmR0.vmx.msr.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
422	g_HvmR0.vmx.msr.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
423	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
424	g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
425	/* VPID 16 bits ASID. */
426	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
427
428	if (g_HvmR0.vmx.msr.vmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
429	{
430	g_HvmR0.vmx.msr.vmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
431	if (g_HvmR0.vmx.msr.vmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
432	g_HvmR0.vmx.msr.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
433
434	if (g_HvmR0.vmx.msr.vmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
435	g_HvmR0.vmx.msr.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
436	}
437
438	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
439	{
440	/*
441	* Enter root mode
442	*/
443	RTR0MEMOBJ hScatchMemObj;
444	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
445	if (RT_FAILURE(rc))
446	{
447	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
448	return rc;
449	}
450
451	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
452	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
453	ASMMemZeroPage(pvScatchPage);
454
455	/* Set revision dword at the beginning of the structure. */
456	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.u64BasicInfo);
457
458	/* Make sure we don't get rescheduled to another cpu during this probe. */
459	RTCCUINTREG fFlags = ASMIntDisableFlags();
460
461	/*
462	* Check CR4.VMXE
463	*/
464	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
465	if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
466	{
467	/* In theory this bit could be cleared behind our back. Which would cause
468	#UD faults when we try to execute the VMX instructions... */
469	ASMSetCR4(g_HvmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
470	}
471
472	/*
473	* The only way of checking if we're in VMX root mode or not is to try and enter it.
474	* There is no instruction or control bit that tells us if we're in VMX root mode.
475	* Therefore, try and enter VMX root mode here.
476	*/
477	rc = VMXEnable(HCPhysScratchPage);
478	if (RT_SUCCESS(rc))
479	{
480	g_HvmR0.vmx.fSupported = true;
481	VMXDisable();
482	}
483	else
484	{
485	/*
486	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
487	* it will crash the host when we enter raw mode, because:
488	*
489	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
490	* this bit), and
491	* (b) turning off paging causes a #GP (unavoidable when switching
492	* from long to 32 bits mode or 32 bits to PAE).
493	*
494	* They should fix their code, but until they do we simply refuse to run.
495	*/
496	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
497	}
498
499	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
500	if it wasn't so before (some software could incorrectly
501	think it's in VMX mode). */
502	ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
503	ASMSetFlags(fFlags);
504
505	RTR0MemObjFree(hScatchMemObj, false);
506	}
507	}
508	else
509	{
510	AssertFailed(); /* can't hit this case anymore */
511	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
512	}
513
514	if (g_HvmR0.vmx.fSupported)
515	{
516	/* Call the global VT-x initialization routine. */
517	rc = VMXR0GlobalInit();
518	if (RT_FAILURE(rc))
519	g_HvmR0.lLastError = rc;
520
521	/*
522	* Install the VT-x methods.
523	*/
524	g_HvmR0.pfnEnterSession = VMXR0Enter;
525	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
526	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
527	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
528	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
529	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
530	g_HvmR0.pfnInitVM = VMXR0InitVM;
531	g_HvmR0.pfnTermVM = VMXR0TermVM;
532	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
533
534	/*
535	* Check for the VMX-Preemption Timer and adjust for the * "VMX-Preemption
536	* Timer Does Not Count Down at the Rate Specified" erratum.
537	*/
538	if (g_HvmR0.vmx.msr.vmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
539	{
540	g_HvmR0.vmx.fUsePreemptTimer = true;
541	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.u64Misc);
542	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
543	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
544	}
545	}
546	}
547	#ifdef LOG_ENABLED
548	else
549	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
550	#endif
551	}
552	else
553	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
554	return VINF_SUCCESS;
555	}
556
557
558	/**
559	* AMD-specific initialization code.
560	*
561	* @returns VBox status code.
562	*/
563	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
564	{
565	/*
566	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
567	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
568	*/
569	int rc;
570	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
571	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
572	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
573	&& ASMIsValidExtRange(uMaxExtLeaf)
574	&& uMaxExtLeaf >= 0x8000000a
575	)
576	{
577	/* Call the global AMD-V initialization routine. */
578	rc = SVMR0GlobalInit();
579	if (RT_FAILURE(rc))
580	{
581	g_HvmR0.lLastError = rc;
582	return rc;
583	}
584
585	/*
586	* Install the AMD-V methods.
587	*/
588	g_HvmR0.pfnEnterSession = SVMR0Enter;
589	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
590	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
591	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
592	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
593	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
594	g_HvmR0.pfnInitVM = SVMR0InitVM;
595	g_HvmR0.pfnTermVM = SVMR0TermVM;
596	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
597
598	/* Query AMD features. */
599	uint32_t u32Dummy;
600	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
601
602	/*
603	* We need to check if AMD-V has been properly initialized on all CPUs.
604	* Some BIOSes might do a poor job.
605	*/
606	HMR0FIRSTRC FirstRc;
607	hmR0FirstRcInit(&FirstRc);
608	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
609	AssertRC(rc);
610	if (RT_SUCCESS(rc))
611	rc = hmR0FirstRcGetStatus(&FirstRc);
612	#ifndef DEBUG_bird
613	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
614	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
615	#endif
616	if (RT_SUCCESS(rc))
617	{
618	/* Read the HWCR MSR for diagnostics. */
619	g_HvmR0.svm.msrHwcr = ASMRdMsr(MSR_K8_HWCR);
620	g_HvmR0.svm.fSupported = true;
621	}
622	else
623	g_HvmR0.lLastError = rc;
624	}
625	else
626	{
627	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
628	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
629	}
630	return rc;
631	}
632
633
634	/**
635	* Does global Ring-0 HM initialization (at module init).
636	*
637	* @returns VBox status code.
638	*/
639	VMMR0_INT_DECL(int) HMR0Init(void)
640	{
641	/*
642	* Initialize the globals.
643	*/
644	g_HvmR0.fEnabled = false;
645	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
646	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
647	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
648	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
649
650	/* Fill in all callbacks with placeholders. */
651	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
652	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
653	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
654	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
655	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
656	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
657	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
658	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
659	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
660
661	/* Default is global VT-x/AMD-V init. */
662	g_HvmR0.fGlobalInit = true;
663
664	/*
665	* Make sure aCpuInfo is big enough for all the CPUs on this system.
666	*/
667	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
668	{
669	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
670	return VERR_TOO_MANY_CPUS;
671	}
672
673	/*
674	* Check for VT-x and AMD-V capabilities.
675	*/
676	int rc;
677	if (ASMHasCpuId())
678	{
679	/* Standard features. */
680	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
681	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
682	if (ASMIsValidStdRange(uMaxLeaf))
683	{
684	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
685	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
686
687	/* Query AMD features. */
688	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
689	if (ASMIsValidExtRange(uMaxExtLeaf))
690	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
691	&g_HvmR0.cpuid.u32AMDFeatureECX,
692	&g_HvmR0.cpuid.u32AMDFeatureEDX);
693	else
694	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
695
696	/* Go to CPU specific initialization code. */
697	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
698	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
699	{
700	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
701	if (RT_FAILURE(rc))
702	return rc;
703	}
704	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
705	{
706	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
707	if (RT_FAILURE(rc))
708	return rc;
709	}
710	else
711	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
712	}
713	else
714	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
715	}
716	else
717	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
718
719	/*
720	* Register notification callbacks that we can use to disable/enable CPUs
721	* when brought offline/online or suspending/resuming.
722	*/
723	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
724	{
725	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
726	AssertRC(rc);
727
728	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
729	AssertRC(rc);
730	}
731
732	/* We return success here because module init shall not fail if HM
733	fails to initialize. */
734	return VINF_SUCCESS;
735	}
736
737
738	/**
739	* Does global Ring-0 HM termination (at module termination).
740	*
741	* @returns VBox status code.
742	*/
743	VMMR0_INT_DECL(int) HMR0Term(void)
744	{
745	int rc;
746	if ( g_HvmR0.vmx.fSupported
747	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
748	{
749	/*
750	* Simple if the host OS manages VT-x.
751	*/
752	Assert(g_HvmR0.fGlobalInit);
753	rc = SUPR0EnableVTx(false /* fEnable */);
754
755	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
756	{
757	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
758	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
759	}
760	}
761	else
762	{
763	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
764	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
765	{
766	/* Doesn't really matter if this fails. */
767	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
768	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
769	}
770	else
771	rc = VINF_SUCCESS;
772
773	/*
774	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
775	*/
776	if (g_HvmR0.fGlobalInit)
777	{
778	HMR0FIRSTRC FirstRc;
779	hmR0FirstRcInit(&FirstRc);
780	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
781	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
782	if (RT_SUCCESS(rc))
783	{
784	rc = hmR0FirstRcGetStatus(&FirstRc);
785	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
786	}
787	}
788
789	/*
790	* Free the per-cpu pages used for VT-x and AMD-V.
791	*/
792	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
793	{
794	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
795	{
796	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
797	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
798	}
799	}
800	}
801
802	/** @todo This needs cleaning up. There's no matching
803	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
804	* should move into their respective modules. */
805	/* Finally, call global VT-x/AMD-V termination. */
806	if (g_HvmR0.vmx.fSupported)
807	VMXR0GlobalTerm();
808	else if (g_HvmR0.svm.fSupported)
809	SVMR0GlobalTerm();
810
811	return rc;
812	}
813
814
815	/**
816	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
817	* VT-x on a CPU.
818	*
819	* @param idCpu The identifier for the CPU the function is called on.
820	* @param pvUser1 Pointer to the first RC structure.
821	* @param pvUser2 Ignored.
822	*/
823	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
824	{
825	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
826	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
827	NOREF(pvUser2);
828
829	/*
830	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
831	* Once the lock bit is set, this MSR can no longer be modified.
832	*/
833	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
834	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
835	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
836	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
837	)
838	{
839	/* MSR is not yet locked; we can change it ourselves here. */
840	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
841	g_HvmR0.vmx.msr.u64FeatureCtrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
842	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
843	}
844
845	int rc;
846	if ((fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
847	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
848	{
849	rc = VINF_SUCCESS;
850	}
851	else
852	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
853
854	hmR0FirstRcSetStatus(pFirstRc, rc);
855	}
856
857
858	/**
859	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
860	* on a CPU.
861	*
862	* @param idCpu The identifier for the CPU the function is called on.
863	* @param pvUser1 Pointer to the first RC structure.
864	* @param pvUser2 Ignored.
865	*/
866	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
867	{
868	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
869	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
870	NOREF(pvUser2);
871
872	/* Check if SVM is disabled. */
873	int rc;
874	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
875	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
876	{
877	/* Turn on SVM in the EFER MSR. */
878	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
879	if (fEfer & MSR_K6_EFER_SVME)
880	rc = VERR_SVM_IN_USE;
881	else
882	{
883	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
884
885	/* Paranoia. */
886	fEfer = ASMRdMsr(MSR_K6_EFER);
887	if (fEfer & MSR_K6_EFER_SVME)
888	{
889	/* Restore previous value. */
890	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
891	rc = VINF_SUCCESS;
892	}
893	else
894	rc = VERR_SVM_ILLEGAL_EFER_MSR;
895	}
896	}
897	else
898	rc = VERR_SVM_DISABLED;
899
900	hmR0FirstRcSetStatus(pFirstRc, rc);
901	}
902
903
904	/**
905	* Enable VT-x or AMD-V on the current CPU
906	*
907	* @returns VBox status code.
908	* @param pVM Pointer to the VM (can be NULL).
909	* @param idCpu The identifier for the CPU the function is called on.
910	*/
911	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
912	{
913	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
914
915	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
916	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
917	Assert(!pCpu->fConfigured);
918
919	pCpu->idCpu = idCpu;
920	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
921	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
922
923	int rc;
924	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
925	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true);
926	else
927	{
928	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
929	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
930	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
931	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
932	}
933	AssertRC(rc);
934	if (RT_SUCCESS(rc))
935	pCpu->fConfigured = true;
936
937	return rc;
938	}
939
940
941	/**
942	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
943	* is to be called on the target cpus.
944	*
945	* @param idCpu The identifier for the CPU the function is called on.
946	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
947	* @param pvUser2 The 2nd user argument.
948	*/
949	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
950	{
951	PVM pVM = (PVM)pvUser1; /* can be NULL! */
952	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
953	AssertReturnVoid(g_HvmR0.fGlobalInit);
954	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
955	}
956
957
958	/**
959	* RTOnce callback employed by HMR0EnableAllCpus.
960	*
961	* @returns VBox status code.
962	* @param pvUser Pointer to the VM.
963	* @param pvUserIgnore NULL, ignored.
964	*/
965	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
966	{
967	PVM pVM = (PVM)pvUser;
968
969	/*
970	* Indicate that we've initialized.
971	*
972	* Note! There is a potential race between this function and the suspend
973	* notification. Kind of unlikely though, so ignored for now.
974	*/
975	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
976	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
977
978	/*
979	* The global init variable is set by the first VM.
980	*/
981	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
982
983	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
984	{
985	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
986	g_HvmR0.aCpuInfo[i].fConfigured = false;
987	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
988	g_HvmR0.aCpuInfo[i].uCurrentAsid = 0;
989	}
990
991	int rc;
992	if ( g_HvmR0.vmx.fSupported
993	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
994	{
995	/*
996	* Global VT-x initialization API (only darwin for now).
997	*/
998	rc = SUPR0EnableVTx(true /* fEnable */);
999	if (RT_SUCCESS(rc))
1000	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
1001	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
1002	else
1003	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
1004	}
1005	else
1006	{
1007	/*
1008	* We're doing the job ourselves.
1009	*/
1010	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
1011	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1012	{
1013	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1014
1015	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1016	{
1017	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1018	AssertLogRelRCReturn(rc, rc);
1019
1020	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1021	ASMMemZeroPage(pvR0);
1022	}
1023	}
1024
1025	rc = VINF_SUCCESS;
1026	}
1027
1028	if ( RT_SUCCESS(rc)
1029	&& g_HvmR0.fGlobalInit)
1030	{
1031	/* First time, so initialize each cpu/core. */
1032	HMR0FIRSTRC FirstRc;
1033	hmR0FirstRcInit(&FirstRc);
1034	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1035	if (RT_SUCCESS(rc))
1036	rc = hmR0FirstRcGetStatus(&FirstRc);
1037	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1038	}
1039
1040	return rc;
1041	}
1042
1043
1044	/**
1045	* Sets up HM on all cpus.
1046	*
1047	* @returns VBox status code.
1048	* @param pVM Pointer to the VM.
1049	*/
1050	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1051	{
1052	/* Make sure we don't touch HM after we've disabled HM in
1053	preparation of a suspend. */
1054	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1055	return VERR_HM_SUSPEND_PENDING;
1056
1057	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1058	}
1059
1060
1061	/**
1062	* Disable VT-x or AMD-V on the current CPU.
1063	*
1064	* @returns VBox status code.
1065	* @param idCpu The identifier for the CPU the function is called on.
1066	*/
1067	static int hmR0DisableCpu(RTCPUID idCpu)
1068	{
1069	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1070
1071	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1072	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1073	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1074	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1075
1076	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1077	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1078
1079	int rc;
1080	if (pCpu->fConfigured)
1081	{
1082	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1083	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1084	if (idCpu == RTMpCpuId())
1085	{
1086	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1087	AssertRC(rc);
1088	}
1089	else
1090	{
1091	pCpu->fIgnoreAMDVInUseError = true;
1092	rc = VINF_SUCCESS;
1093	}
1094
1095	pCpu->fConfigured = false;
1096	}
1097	else
1098	rc = VINF_SUCCESS; /* nothing to do */
1099
1100	pCpu->uCurrentAsid = 0;
1101	return rc;
1102	}
1103
1104
1105	/**
1106	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1107	* is to be called on the target CPUs.
1108	*
1109	* @param idCpu The identifier for the CPU the function is called on.
1110	* @param pvUser1 The 1st user argument.
1111	* @param pvUser2 Opaque pointer to the FirstRc.
1112	*/
1113	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1114	{
1115	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1116	AssertReturnVoid(g_HvmR0.fGlobalInit);
1117	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1118	}
1119
1120
1121	/**
1122	* Callback function invoked when a cpu goes online or offline.
1123	*
1124	* @param enmEvent The Mp event.
1125	* @param idCpu The identifier for the CPU the function is called on.
1126	* @param pvData Opaque data (PVM pointer).
1127	*/
1128	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1129	{
1130	NOREF(pvData);
1131
1132	/*
1133	* We only care about uninitializing a CPU that is going offline. When a
1134	* CPU comes online, the initialization is done lazily in HMR0Enter().
1135	*/
1136	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1137	switch (enmEvent)
1138	{
1139	case RTMPEVENT_OFFLINE:
1140	{
1141	int rc = hmR0DisableCpu(idCpu);
1142	AssertRC(rc);
1143	break;
1144	}
1145
1146	default:
1147	break;
1148	}
1149	}
1150
1151
1152	/**
1153	* Called whenever a system power state change occurs.
1154	*
1155	* @param enmEvent The Power event.
1156	* @param pvUser User argument.
1157	*/
1158	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1159	{
1160	NOREF(pvUser);
1161	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1162
1163	#ifdef LOG_ENABLED
1164	if (enmEvent == RTPOWEREVENT_SUSPEND)
1165	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1166	else
1167	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1168	#endif
1169
1170	if (enmEvent == RTPOWEREVENT_SUSPEND)
1171	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1172
1173	if (g_HvmR0.fEnabled)
1174	{
1175	int rc;
1176	HMR0FIRSTRC FirstRc;
1177	hmR0FirstRcInit(&FirstRc);
1178
1179	if (enmEvent == RTPOWEREVENT_SUSPEND)
1180	{
1181	if (g_HvmR0.fGlobalInit)
1182	{
1183	/* Turn off VT-x or AMD-V on all CPUs. */
1184	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1185	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1186	}
1187	/* else nothing to do here for the local init case */
1188	}
1189	else
1190	{
1191	/* Reinit the CPUs from scratch as the suspend state might have
1192	messed with the MSRs. (lousy BIOSes as usual) */
1193	if (g_HvmR0.vmx.fSupported)
1194	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1195	else
1196	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1197	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1198	if (RT_SUCCESS(rc))
1199	rc = hmR0FirstRcGetStatus(&FirstRc);
1200	#ifdef LOG_ENABLED
1201	if (RT_FAILURE(rc))
1202	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1203	#endif
1204	if (g_HvmR0.fGlobalInit)
1205	{
1206	/* Turn VT-x or AMD-V back on on all CPUs. */
1207	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1208	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1209	}
1210	/* else nothing to do here for the local init case */
1211	}
1212	}
1213
1214	if (enmEvent == RTPOWEREVENT_RESUME)
1215	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1216	}
1217
1218
1219	/**
1220	* Does Ring-0 per VM HM initialization.
1221	*
1222	* This will copy HM global into the VM structure and call the CPU specific
1223	* init routine which will allocate resources for each virtual CPU and such.
1224	*
1225	* @returns VBox status code.
1226	* @param pVM Pointer to the VM.
1227	*/
1228	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1229	{
1230	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1231
1232	#ifdef LOG_ENABLED
1233	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1234	#endif
1235
1236	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1237	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1238	return VERR_HM_SUSPEND_PENDING;
1239
1240	/*
1241	* Copy globals to the VM structure.
1242	*/
1243	/** @todo r=ramshankar: Why do we do this for MSRs? We never change them in the
1244	* per-VM structures anyway... */
1245	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1246	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1247
1248	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1249	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1250	pVM->hm.s.vmx.msr.feature_ctrl = g_HvmR0.vmx.msr.u64FeatureCtrl;
1251	pVM->hm.s.vmx.hostCR4 = g_HvmR0.vmx.u64HostCr4;
1252	pVM->hm.s.vmx.hostEFER = g_HvmR0.vmx.u64HostEfer;
1253	pVM->hm.s.vmx.msr.vmx_basic_info = g_HvmR0.vmx.msr.u64BasicInfo;
1254	pVM->hm.s.vmx.msr.vmx_pin_ctls = g_HvmR0.vmx.msr.vmxPinCtls;
1255	pVM->hm.s.vmx.msr.vmx_proc_ctls = g_HvmR0.vmx.msr.vmxProcCtls;
1256	pVM->hm.s.vmx.msr.vmx_proc_ctls2 = g_HvmR0.vmx.msr.vmxProcCtls2;
1257	pVM->hm.s.vmx.msr.vmx_exit = g_HvmR0.vmx.msr.vmxExit;
1258	pVM->hm.s.vmx.msr.vmx_entry = g_HvmR0.vmx.msr.vmxEntry;
1259	pVM->hm.s.vmx.msr.vmx_misc = g_HvmR0.vmx.msr.u64Misc;
1260	pVM->hm.s.vmx.msr.vmx_cr0_fixed0 = g_HvmR0.vmx.msr.u64Cr0Fixed0;
1261	pVM->hm.s.vmx.msr.vmx_cr0_fixed1 = g_HvmR0.vmx.msr.u64Cr0Fixed1;
1262	pVM->hm.s.vmx.msr.vmx_cr4_fixed0 = g_HvmR0.vmx.msr.u64Cr4Fixed0;
1263	pVM->hm.s.vmx.msr.vmx_cr4_fixed1 = g_HvmR0.vmx.msr.u64Cr4Fixed1;
1264	pVM->hm.s.vmx.msr.vmx_vmcs_enum = g_HvmR0.vmx.msr.u64VmcsEnum;
1265	pVM->hm.s.vmx.msr.vmx_vmfunc = g_HvmR0.vmx.msr.u64Vmfunc;
1266	pVM->hm.s.vmx.msr.vmx_ept_vpid_caps = g_HvmR0.vmx.msr.u64EptVpidCaps;
1267	pVM->hm.s.svm.msrHwcr = g_HvmR0.svm.msrHwcr;
1268	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1269	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1270	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1271	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1272	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1273
1274	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1275
1276
1277	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1278	{
1279	pVM->hm.s.cMaxResumeLoops = 1024;
1280	if (RTThreadPreemptIsPendingTrusty())
1281	pVM->hm.s.cMaxResumeLoops = 8192;
1282	}
1283
1284	/*
1285	* Initialize some per CPU fields.
1286	*/
1287	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1288	{
1289	PVMCPU pVCpu = &pVM->aCpus[i];
1290
1291	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1292
1293	/* Invalidate the last cpu we were running on. */
1294	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1295
1296	/* We'll aways increment this the first time (host uses ASID 0) */
1297	pVCpu->hm.s.uCurrentAsid = 0;
1298	}
1299
1300	/*
1301	* Call the hardware specific initialization method.
1302	*/
1303	RTCCUINTREG fFlags = ASMIntDisableFlags();
1304	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1305	ASMSetFlags(fFlags);
1306
1307	int rc = g_HvmR0.pfnInitVM(pVM);
1308	return rc;
1309	}
1310
1311
1312	/**
1313	* Does Ring-0 per VM HM termination.
1314	*
1315	* @returns VBox status code.
1316	* @param pVM Pointer to the VM.
1317	*/
1318	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1319	{
1320	Log(("HMR0TermVM: %p\n", pVM));
1321	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1322
1323	/* Make sure we don't touch HM after we've disabled HM in preparation
1324	of a suspend. */
1325	/** @todo r=bird: This cannot be right, the termination functions are
1326	* just freeing memory and resetting pVM/pVCpu members...
1327	* ==> memory leak. */
1328	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1329
1330	/*
1331	* Call the hardware specific method.
1332	*/
1333	RTCCUINTREG fFlags = ASMIntDisableFlags();
1334	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1335	ASMSetFlags(fFlags);
1336
1337	int rc = g_HvmR0.pfnTermVM(pVM);
1338	return rc;
1339	}
1340
1341
1342	/**
1343	* Sets up a VT-x or AMD-V session.
1344	*
1345	* This is mostly about setting up the hardware VM state.
1346	*
1347	* @returns VBox status code.
1348	* @param pVM Pointer to the VM.
1349	*/
1350	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1351	{
1352	Log(("HMR0SetupVM: %p\n", pVM));
1353	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1354
1355	/* Make sure we don't touch HM after we've disabled HM in
1356	preparation of a suspend. */
1357	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1358
1359	/*
1360	* Call the hardware specific setup VM method. This requires the CPU to be
1361	* enabled for AMD-V/VT-x and preemption to be prevented.
1362	*/
1363	RTCCUINTREG fFlags = ASMIntDisableFlags();
1364	RTCPUID idCpu = RTMpCpuId();
1365	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1366
1367	/* On first entry we'll sync everything. */
1368	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1369	pVM->aCpus[i].hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1370
1371	/* Enable VT-x or AMD-V if local init is required. */
1372	int rc;
1373	if (!g_HvmR0.fGlobalInit)
1374	{
1375	rc = hmR0EnableCpu(pVM, idCpu);
1376	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1377	}
1378
1379	/* Setup VT-x or AMD-V. */
1380	rc = g_HvmR0.pfnSetupVM(pVM);
1381
1382	/* Disable VT-x or AMD-V if local init was done before. */
1383	if (!g_HvmR0.fGlobalInit)
1384	{
1385	int rc2 = hmR0DisableCpu(idCpu);
1386	AssertRC(rc2);
1387	}
1388
1389	ASMSetFlags(fFlags);
1390	return rc;
1391	}
1392
1393
1394	/**
1395	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1396	* required for entering HM context.
1397	*
1398	* @returns VBox status code.
1399	* @param pvCpu Pointer to the VMCPU.
1400	*
1401	* @remarks No-long-jump zone!!!
1402	*/
1403	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1404	{
1405	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1406
1407	int rc = VINF_SUCCESS;
1408	RTCPUID idCpu = RTMpCpuId();
1409	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1410	AssertPtr(pCpu);
1411
1412	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1413	if (!pCpu->fConfigured)
1414	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1415
1416	/* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
1417	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE;
1418	pVCpu->hm.s.idEnteredCpu = idCpu;
1419	return rc;
1420	}
1421
1422
1423	/**
1424	* Enters the VT-x or AMD-V session.
1425	*
1426	* @returns VBox status code.
1427	* @param pVM Pointer to the VM.
1428	* @param pVCpu Pointer to the VMCPU.
1429	*
1430	* @remarks This is called with preemption disabled.
1431	*/
1432	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1433	{
1434	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1435	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1436	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1437
1438	/* Load the bare minimum state required for entering HM. */
1439	int rc = HMR0EnterCpu(pVCpu);
1440	AssertRCReturn(rc, rc);
1441
1442	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1443	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1444	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1445	#endif
1446
1447	RTCPUID idCpu = RTMpCpuId();
1448	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1449	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1450	Assert(pCpu);
1451	Assert(pCtx);
1452	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1453
1454	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1455	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1456
1457	/* Load the host as we may be resuming code after a longjmp and quite
1458	possibly now be scheduled on a different CPU. */
1459	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1460	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1461
1462	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1463	if (fStartedSet)
1464	PGMRZDynMapReleaseAutoSet(pVCpu);
1465	#endif
1466
1467	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1468	and ring-3 calls. */
1469	if (RT_FAILURE(rc))
1470	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1471	return rc;
1472	}
1473
1474
1475	/**
1476	* Deinitializes the bare minimum state used for HM context and if necessary
1477	* disable HM on the CPU.
1478	*
1479	* @returns VBox status code.
1480	* @param pVCpu Pointer to the VMCPU.
1481	*
1482	* @remarks No-long-jump zone!!!
1483	*/
1484	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1485	{
1486	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1487
1488	RTCPUID idCpu = RTMpCpuId();
1489	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1490
1491	if ( !g_HvmR0.fGlobalInit
1492	&& pCpu->fConfigured)
1493	{
1494	int rc = hmR0DisableCpu(idCpu);
1495	AssertRCReturn(rc, rc);
1496	Assert(!pCpu->fConfigured);
1497	}
1498
1499	/* Reset these to force a TLB flush for the next entry. */
1500	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1501	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1502	pVCpu->hm.s.uCurrentAsid = 0;
1503	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1504
1505	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1506	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1507
1508	return VINF_SUCCESS;
1509	}
1510
1511
1512	/**
1513	* Thread-context hook for HM.
1514	*
1515	* @param enmEvent The thread-context event.
1516	* @param pvUser Opaque pointer to the VMCPU.
1517	*/
1518	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1519	{
1520	PVMCPU pVCpu = (PVMCPU)pvUser;
1521	Assert(pVCpu);
1522	Assert(g_HvmR0.pfnThreadCtxCallback);
1523
1524	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1525	}
1526
1527
1528	/**
1529	* Runs guest code in a hardware accelerated VM.
1530	*
1531	* @returns VBox status code.
1532	* @param pVM Pointer to the VM.
1533	* @param pVCpu Pointer to the VMCPU.
1534	*
1535	* @remarks Called with preemption disabled and after first having called
1536	* HMR0Enter.
1537	*/
1538	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1539	{
1540	#ifdef VBOX_STRICT
1541	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1542	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1543	Assert(pCpu->fConfigured);
1544	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1545	#endif
1546
1547	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1548	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1549	PGMRZDynMapStartAutoSet(pVCpu);
1550	#endif
1551
1552	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1553
1554	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1555	PGMRZDynMapReleaseAutoSet(pVCpu);
1556	#endif
1557	return rc;
1558	}
1559
1560	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1561
1562	/**
1563	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1564	*
1565	* @returns VBox status code.
1566	* @param pVM Pointer to the VM.
1567	* @param pVCpu Pointer to the VMCPU.
1568	* @param pCtx Pointer to the guest CPU context.
1569	*/
1570	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1571	{
1572	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1573	if (pVM->hm.s.vmx.fSupported)
1574	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1575	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1576	}
1577
1578
1579	/**
1580	* Save guest debug state (64 bits guest mode & 32 bits host only)
1581	*
1582	* @returns VBox status code.
1583	* @param pVM Pointer to the VM.
1584	* @param pVCpu Pointer to the VMCPU.
1585	* @param pCtx Pointer to the guest CPU context.
1586	*/
1587	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1588	{
1589	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1590	if (pVM->hm.s.vmx.fSupported)
1591	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1592	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1593	}
1594
1595
1596	/**
1597	* Test the 32->64 bits switcher.
1598	*
1599	* @returns VBox status code.
1600	* @param pVM Pointer to the VM.
1601	*/
1602	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1603	{
1604	PVMCPU pVCpu = &pVM->aCpus[0];
1605	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1606	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1607	int rc;
1608
1609	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1610	if (pVM->hm.s.vmx.fSupported)
1611	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1612	else
1613	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1614	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1615
1616	return rc;
1617	}
1618
1619	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1620
1621	/**
1622	* Returns suspend status of the host.
1623	*
1624	* @returns Suspend pending or not.
1625	*/
1626	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1627	{
1628	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1629	}
1630
1631
1632	/**
1633	* Returns the cpu structure for the current cpu.
1634	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1635	*
1636	* @returns The cpu structure pointer.
1637	*/
1638	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1639	{
1640	RTCPUID idCpu = RTMpCpuId();
1641	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1642	return &g_HvmR0.aCpuInfo[idCpu];
1643	}
1644
1645
1646	/**
1647	* Returns the cpu structure for the current cpu.
1648	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1649	*
1650	* @returns The cpu structure pointer.
1651	* @param idCpu id of the VCPU.
1652	*/
1653	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1654	{
1655	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1656	return &g_HvmR0.aCpuInfo[idCpu];
1657	}
1658
1659
1660	/**
1661	* Save a pending IO read.
1662	*
1663	* @param pVCpu Pointer to the VMCPU.
1664	* @param GCPtrRip Address of IO instruction.
1665	* @param GCPtrRipNext Address of the next instruction.
1666	* @param uPort Port address.
1667	* @param uAndVal AND mask for saving the result in eax.
1668	* @param cbSize Read size.
1669	*/
1670	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1671	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1672	{
1673	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1674	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1675	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1676	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1677	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1678	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1679	return;
1680	}
1681
1682
1683	/**
1684	* Save a pending IO write.
1685	*
1686	* @param pVCpu Pointer to the VMCPU.
1687	* @param GCPtrRIP Address of IO instruction.
1688	* @param uPort Port address.
1689	* @param uAndVal AND mask for fetching the result from eax.
1690	* @param cbSize Read size.
1691	*/
1692	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1693	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1694	{
1695	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1696	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1697	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1698	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1699	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1700	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1701	return;
1702	}
1703
1704
1705	/**
1706	* Raw-mode switcher hook - disable VT-x if it's active and the current
1707	* switcher turns off paging.
1708	*
1709	* @returns VBox status code.
1710	* @param pVM Pointer to the VM.
1711	* @param enmSwitcher The switcher we're about to use.
1712	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1713	*/
1714	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1715	{
1716	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1717
1718	*pfVTxDisabled = false;
1719
1720	/* No such issues with AMD-V */
1721	if (!g_HvmR0.vmx.fSupported)
1722	return VINF_SUCCESS;
1723
1724	/* Check if the swithcing we're up to is safe. */
1725	switch (enmSwitcher)
1726	{
1727	case VMMSWITCHER_32_TO_32:
1728	case VMMSWITCHER_PAE_TO_PAE:
1729	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1730
1731	case VMMSWITCHER_32_TO_PAE:
1732	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1733	case VMMSWITCHER_AMD64_TO_32:
1734	case VMMSWITCHER_AMD64_TO_PAE:
1735	break; /* unsafe switchers */
1736
1737	default:
1738	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1739	}
1740
1741	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1742	regardless of whether we're currently using VT-x or not. */
1743	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1744	{
1745	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1746	return VINF_SUCCESS;
1747	}
1748
1749	/** @todo Check if this code is presumtive wrt other VT-x users on the
1750	* system... */
1751
1752	/* Nothing to do if we haven't enabled VT-x. */
1753	if (!g_HvmR0.fEnabled)
1754	return VINF_SUCCESS;
1755
1756	/* Local init implies the CPU is currently not in VMX root mode. */
1757	if (!g_HvmR0.fGlobalInit)
1758	return VINF_SUCCESS;
1759
1760	/* Ok, disable VT-x. */
1761	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1762	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1763
1764	*pfVTxDisabled = true;
1765	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1766	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1767	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1768	}
1769
1770
1771	/**
1772	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1773	* switcher turned off paging.
1774	*
1775	* @param pVM Pointer to the VM.
1776	* @param fVTxDisabled Whether VT-x was disabled or not.
1777	*/
1778	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1779	{
1780	Assert(!(ASMGetFlags() & X86_EFL_IF));
1781
1782	if (!fVTxDisabled)
1783	return; /* nothing to do */
1784
1785	Assert(g_HvmR0.vmx.fSupported);
1786	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1787	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1788	else
1789	{
1790	Assert(g_HvmR0.fEnabled);
1791	Assert(g_HvmR0.fGlobalInit);
1792
1793	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1794	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1795
1796	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1797	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1798	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
1799	}
1800	}
1801
1802	#ifdef VBOX_STRICT
1803
1804	/**
1805	* Dumps a descriptor.
1806	*
1807	* @param pDesc Descriptor to dump.
1808	* @param Sel Selector number.
1809	* @param pszMsg Message to prepend the log entry with.
1810	*/
1811	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1812	{
1813	/*
1814	* Make variable description string.
1815	*/
1816	static struct
1817	{
1818	unsigned cch;
1819	const char *psz;
1820	} const s_aTypes[32] =
1821	{
1822	# define STRENTRY(str) { sizeof(str) - 1, str }
1823
1824	/* system */
1825	# if HC_ARCH_BITS == 64
1826	STRENTRY("Reserved0 "), /* 0x00 */
1827	STRENTRY("Reserved1 "), /* 0x01 */
1828	STRENTRY("LDT "), /* 0x02 */
1829	STRENTRY("Reserved3 "), /* 0x03 */
1830	STRENTRY("Reserved4 "), /* 0x04 */
1831	STRENTRY("Reserved5 "), /* 0x05 */
1832	STRENTRY("Reserved6 "), /* 0x06 */
1833	STRENTRY("Reserved7 "), /* 0x07 */
1834	STRENTRY("Reserved8 "), /* 0x08 */
1835	STRENTRY("TSS64Avail "), /* 0x09 */
1836	STRENTRY("ReservedA "), /* 0x0a */
1837	STRENTRY("TSS64Busy "), /* 0x0b */
1838	STRENTRY("Call64 "), /* 0x0c */
1839	STRENTRY("ReservedD "), /* 0x0d */
1840	STRENTRY("Int64 "), /* 0x0e */
1841	STRENTRY("Trap64 "), /* 0x0f */
1842	# else
1843	STRENTRY("Reserved0 "), /* 0x00 */
1844	STRENTRY("TSS16Avail "), /* 0x01 */
1845	STRENTRY("LDT "), /* 0x02 */
1846	STRENTRY("TSS16Busy "), /* 0x03 */
1847	STRENTRY("Call16 "), /* 0x04 */
1848	STRENTRY("Task "), /* 0x05 */
1849	STRENTRY("Int16 "), /* 0x06 */
1850	STRENTRY("Trap16 "), /* 0x07 */
1851	STRENTRY("Reserved8 "), /* 0x08 */
1852	STRENTRY("TSS32Avail "), /* 0x09 */
1853	STRENTRY("ReservedA "), /* 0x0a */
1854	STRENTRY("TSS32Busy "), /* 0x0b */
1855	STRENTRY("Call32 "), /* 0x0c */
1856	STRENTRY("ReservedD "), /* 0x0d */
1857	STRENTRY("Int32 "), /* 0x0e */
1858	STRENTRY("Trap32 "), /* 0x0f */
1859	# endif
1860	/* non system */
1861	STRENTRY("DataRO "), /* 0x10 */
1862	STRENTRY("DataRO Accessed "), /* 0x11 */
1863	STRENTRY("DataRW "), /* 0x12 */
1864	STRENTRY("DataRW Accessed "), /* 0x13 */
1865	STRENTRY("DataDownRO "), /* 0x14 */
1866	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1867	STRENTRY("DataDownRW "), /* 0x16 */
1868	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1869	STRENTRY("CodeEO "), /* 0x18 */
1870	STRENTRY("CodeEO Accessed "), /* 0x19 */
1871	STRENTRY("CodeER "), /* 0x1a */
1872	STRENTRY("CodeER Accessed "), /* 0x1b */
1873	STRENTRY("CodeConfEO "), /* 0x1c */
1874	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1875	STRENTRY("CodeConfER "), /* 0x1e */
1876	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1877	# undef SYSENTRY
1878	};
1879	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1880	char szMsg[128];
1881	char *psz = &szMsg[0];
1882	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1883	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1884	psz += s_aTypes[i].cch;
1885
1886	if (pDesc->Gen.u1Present)
1887	ADD_STR(psz, "Present ");
1888	else
1889	ADD_STR(psz, "Not-Present ");
1890	# if HC_ARCH_BITS == 64
1891	if (pDesc->Gen.u1Long)
1892	ADD_STR(psz, "64-bit ");
1893	else
1894	ADD_STR(psz, "Comp ");
1895	# else
1896	if (pDesc->Gen.u1Granularity)
1897	ADD_STR(psz, "Page ");
1898	if (pDesc->Gen.u1DefBig)
1899	ADD_STR(psz, "32-bit ");
1900	else
1901	ADD_STR(psz, "16-bit ");
1902	# endif
1903	# undef ADD_STR
1904	*psz = '\0';
1905
1906	/*
1907	* Limit and Base and format the output.
1908	*/
1909	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1910
1911	# if HC_ARCH_BITS == 64
1912	uint64_t u32Base = X86DESC64_BASE(pDesc);
1913
1914	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1915	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1916	# else
1917	uint32_t u32Base = X86DESC_BASE(pDesc);
1918
1919	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1920	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1921	# endif
1922	}
1923
1924
1925	/**
1926	* Formats a full register dump.
1927	*
1928	* @param pVM Pointer to the VM.
1929	* @param pVCpu Pointer to the VMCPU.
1930	* @param pCtx Pointer to the CPU context.
1931	*/
1932	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1933	{
1934	NOREF(pVM);
1935
1936	/*
1937	* Format the flags.
1938	*/
1939	static struct
1940	{
1941	const char pszSet; const char pszClear; uint32_t fFlag;
1942	} const s_aFlags[] =
1943	{
1944	{ "vip",NULL, X86_EFL_VIP },
1945	{ "vif",NULL, X86_EFL_VIF },
1946	{ "ac", NULL, X86_EFL_AC },
1947	{ "vm", NULL, X86_EFL_VM },
1948	{ "rf", NULL, X86_EFL_RF },
1949	{ "nt", NULL, X86_EFL_NT },
1950	{ "ov", "nv", X86_EFL_OF },
1951	{ "dn", "up", X86_EFL_DF },
1952	{ "ei", "di", X86_EFL_IF },
1953	{ "tf", NULL, X86_EFL_TF },
1954	{ "nt", "pl", X86_EFL_SF },
1955	{ "nz", "zr", X86_EFL_ZF },
1956	{ "ac", "na", X86_EFL_AF },
1957	{ "po", "pe", X86_EFL_PF },
1958	{ "cy", "nc", X86_EFL_CF },
1959	};
1960	char szEFlags[80];
1961	char *psz = szEFlags;
1962	uint32_t efl = pCtx->eflags.u32;
1963	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1964	{
1965	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1966	if (pszAdd)
1967	{
1968	strcpy(psz, pszAdd);
1969	psz += strlen(pszAdd);
1970	*psz++ = ' ';
1971	}
1972	}
1973	psz[-1] = '\0';
1974
1975
1976	/*
1977	* Format the registers.
1978	*/
1979	if (CPUMIsGuestIn64BitCode(pVCpu))
1980	{
1981	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1982	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1983	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1984	"r14=%016RX64 r15=%016RX64\n"
1985	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1986	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1987	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1988	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1989	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1990	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1991	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1992	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1993	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1994	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1995	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1996	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1997	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1998	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1999	,
2000	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
2001	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
2002	pCtx->r14, pCtx->r15,
2003	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2004	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2005	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2006	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2007	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2008	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2009	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2010	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
2011	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
2012	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2013	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2014	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2015	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2016	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2017	}
2018	else
2019	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2020	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2021	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2022	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2023	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2024	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2025	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2026	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2027	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2028	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2029	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2030	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2031	,
2032	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2033	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2034	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2035	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2036	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2037	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2038	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2039	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2040	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2041	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2042	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2043	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2044
2045	Log(("FPU:\n"
2046	"FCW=%04x FSW=%04x FTW=%02x\n"
2047	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2048	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2049	,
2050	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2051	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2052	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2053	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2054
2055
2056	Log(("MSR:\n"
2057	"EFER =%016RX64\n"
2058	"PAT =%016RX64\n"
2059	"STAR =%016RX64\n"
2060	"CSTAR =%016RX64\n"
2061	"LSTAR =%016RX64\n"
2062	"SFMASK =%016RX64\n"
2063	"KERNELGSBASE =%016RX64\n",
2064	pCtx->msrEFER,
2065	pCtx->msrPAT,
2066	pCtx->msrSTAR,
2067	pCtx->msrCSTAR,
2068	pCtx->msrLSTAR,
2069	pCtx->msrSFMASK,
2070	pCtx->msrKERNELGSBASE));
2071
2072	}
2073
2074	#endif /* VBOX_STRICT */
2075

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 48209

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