HMR0.cpp@ 48213

Last change on this file since 48213 was 48213, checked in by vboxsync, 11 years ago
VMM: Naming fixes and log cosmetics.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 73.7 KB

Line
1	/* $Id: HMR0.cpp 48213 2013-08-30 23:17:51Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	/** @todo This isn't used for anything relevant. Remove later? */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** VMX MSR values */
123	struct
124	{
125	uint64_t u64FeatureCtrl;
126	uint64_t u64BasicInfo;
127	VMX_CAPABILITY VmxPinCtls;
128	VMX_CAPABILITY VmxProcCtls;
129	VMX_CAPABILITY VmxProcCtls2;
130	VMX_CAPABILITY VmxExit;
131	VMX_CAPABILITY VmxEntry;
132	uint64_t u64Misc;
133	uint64_t u64Cr0Fixed0;
134	uint64_t u64Cr0Fixed1;
135	uint64_t u64Cr4Fixed0;
136	uint64_t u64Cr4Fixed1;
137	uint64_t u64VmcsEnum;
138	uint64_t u64Vmfunc;
139	uint64_t u64EptVpidCaps;
140	} msr;
141	/* Last instruction error */
142	uint32_t ulLastInstrError;
143	} vmx;
144
145	/** AMD-V information. */
146	struct
147	{
148	/* HWCR MSR (for diagnostics) */
149	uint64_t u64MsrHwcr;
150
151	/** SVM revision. */
152	uint32_t u32Rev;
153
154	/** SVM feature bits from cpuid 0x8000000a */
155	uint32_t u32Features;
156
157	/** Set by us to indicate SVM is supported by the CPU. */
158	bool fSupported;
159	} svm;
160	/** Saved error from detection */
161	int32_t lLastError;
162
163	struct
164	{
165	uint32_t u32AMDFeatureECX;
166	uint32_t u32AMDFeatureEDX;
167	} cpuid;
168
169	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
170	* enabled and disabled each time it's used to execute guest code. */
171	bool fGlobalInit;
172	/** Indicates whether the host is suspending or not. We'll refuse a few
173	* actions when the host is being suspended to speed up the suspending and
174	* avoid trouble. */
175	volatile bool fSuspended;
176
177	/** Whether we've already initialized all CPUs.
178	* @remarks We could check the EnableAllCpusOnce state, but this is
179	* simpler and hopefully easier to understand. */
180	bool fEnabled;
181	/** Serialize initialization in HMR0EnableAllCpus. */
182	RTONCE EnableAllCpusOnce;
183	} g_HvmR0;
184
185
186
187	/**
188	* Initializes a first return code structure.
189	*
190	* @param pFirstRc The structure to init.
191	*/
192	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
193	{
194	pFirstRc->rc = VINF_SUCCESS;
195	pFirstRc->idCpu = NIL_RTCPUID;
196	}
197
198
199	/**
200	* Try set the status code (success ignored).
201	*
202	* @param pFirstRc The first return code structure.
203	* @param rc The status code.
204	*/
205	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
206	{
207	if ( RT_FAILURE(rc)
208	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
209	pFirstRc->idCpu = RTMpCpuId();
210	}
211
212
213	/**
214	* Get the status code of a first return code structure.
215	*
216	* @returns The status code; VINF_SUCCESS or error status, no informational or
217	* warning errors.
218	* @param pFirstRc The first return code structure.
219	*/
220	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
221	{
222	return pFirstRc->rc;
223	}
224
225
226	#ifdef VBOX_STRICT
227	/**
228	* Get the CPU ID on which the failure status code was reported.
229	*
230	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
231	* @param pFirstRc The first return code structure.
232	*/
233	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
234	{
235	return pFirstRc->idCpu;
236	}
237	#endif /* VBOX_STRICT */
238
239
240	/** @name Dummy callback handlers.
241	* @{ */
242
243	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
244	{
245	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
246	return VINF_SUCCESS;
247	}
248
249	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
250	{
251	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
252	return VINF_SUCCESS;
253	}
254
255	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
256	{
257	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
258	}
259
260	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
261	bool fEnabledBySystem)
262	{
263	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem);
264	return VINF_SUCCESS;
265	}
266
267	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
268	{
269	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
270	return VINF_SUCCESS;
271	}
272
273	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
274	{
275	NOREF(pVM);
276	return VINF_SUCCESS;
277	}
278
279	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
280	{
281	NOREF(pVM);
282	return VINF_SUCCESS;
283	}
284
285	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
286	{
287	NOREF(pVM);
288	return VINF_SUCCESS;
289	}
290
291	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
292	{
293	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
294	return VINF_SUCCESS;
295	}
296
297	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
298	{
299	NOREF(pVM); NOREF(pVCpu);
300	return VINF_SUCCESS;
301	}
302
303	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
304	{
305	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
306	return VINF_SUCCESS;
307	}
308
309	/** @} */
310
311
312	/**
313	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
314	* Down at the Rate Specified" erratum.
315	*
316	* Errata names and related steppings:
317	* - BA86 - D0.
318	* - AAX65 - C2.
319	* - AAU65 - C2, K0.
320	* - AAO95 - B1.
321	* - AAT59 - C2.
322	* - AAK139 - D0.
323	* - AAM126 - C0, C1, D0.
324	* - AAN92 - B1.
325	* - AAJ124 - C0, D0.
326	*
327	* - AAP86 - B1.
328	*
329	* Steppings: B1, C0, C1, C2, D0, K0.
330	*
331	* @returns true if subject to it, false if not.
332	*/
333	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
334	{
335	uint32_t u = ASMCpuId_EAX(1);
336	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
337	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
338	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
339	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
340	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
341	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
342	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
343	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
344	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
345	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
346	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
347	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
348	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
349	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
350	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
351	)
352	return true;
353	return false;
354	}
355
356
357	/**
358	* Intel specific initialization code.
359	*
360	* @returns VBox status code (will only fail if out of memory).
361	*/
362	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
363	{
364	/*
365	* Check that all the required VT-x features are present.
366	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
367	*/
368	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
369	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
370	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
371	)
372	{
373	/** @todo move this into a separate function. */
374	g_HvmR0.vmx.msr.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
375
376	/*
377	* First try use native kernel API for controlling VT-x.
378	* (This is only supported by some Mac OS X kernels atm.)
379	*/
380	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
381	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
382	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
383	{
384	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
385	if (RT_SUCCESS(rc))
386	{
387	g_HvmR0.vmx.fSupported = true;
388	rc = SUPR0EnableVTx(false /* fEnable */);
389	AssertLogRelRC(rc);
390	}
391	}
392	else
393	{
394	/* We need to check if VT-x has been properly initialized on all
395	CPUs. Some BIOSes do a lousy job. */
396	HMR0FIRSTRC FirstRc;
397	hmR0FirstRcInit(&FirstRc);
398	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
399	if (RT_SUCCESS(g_HvmR0.lLastError))
400	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
401	}
402	if (RT_SUCCESS(g_HvmR0.lLastError))
403	{
404	/* Reread in case we've changed it. */
405	g_HvmR0.vmx.msr.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
406
407	if ( (g_HvmR0.vmx.msr.u64FeatureCtrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
408	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
409	{
410	/*
411	* Read all relevant MSRs.
412	*/
413	g_HvmR0.vmx.msr.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
414	g_HvmR0.vmx.msr.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
415	g_HvmR0.vmx.msr.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
416	g_HvmR0.vmx.msr.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
417	g_HvmR0.vmx.msr.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
418	g_HvmR0.vmx.msr.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
419	g_HvmR0.vmx.msr.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
420	g_HvmR0.vmx.msr.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
421	g_HvmR0.vmx.msr.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
422	g_HvmR0.vmx.msr.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
423	g_HvmR0.vmx.msr.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
424	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
425	g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
426	/* VPID 16 bits ASID. */
427	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
428
429	if (g_HvmR0.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
430	{
431	g_HvmR0.vmx.msr.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
432	if (g_HvmR0.vmx.msr.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
433	g_HvmR0.vmx.msr.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
434
435	if (g_HvmR0.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
436	g_HvmR0.vmx.msr.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
437	}
438
439	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
440	{
441	/*
442	* Enter root mode
443	*/
444	RTR0MEMOBJ hScatchMemObj;
445	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
446	if (RT_FAILURE(rc))
447	{
448	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
449	return rc;
450	}
451
452	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
453	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
454	ASMMemZeroPage(pvScatchPage);
455
456	/* Set revision dword at the beginning of the structure. */
457	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.u64BasicInfo);
458
459	/* Make sure we don't get rescheduled to another cpu during this probe. */
460	RTCCUINTREG fFlags = ASMIntDisableFlags();
461
462	/*
463	* Check CR4.VMXE
464	*/
465	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
466	if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
467	{
468	/* In theory this bit could be cleared behind our back. Which would cause
469	#UD faults when we try to execute the VMX instructions... */
470	ASMSetCR4(g_HvmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
471	}
472
473	/*
474	* The only way of checking if we're in VMX root mode or not is to try and enter it.
475	* There is no instruction or control bit that tells us if we're in VMX root mode.
476	* Therefore, try and enter VMX root mode here.
477	*/
478	rc = VMXEnable(HCPhysScratchPage);
479	if (RT_SUCCESS(rc))
480	{
481	g_HvmR0.vmx.fSupported = true;
482	VMXDisable();
483	}
484	else
485	{
486	/*
487	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
488	* it will crash the host when we enter raw mode, because:
489	*
490	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
491	* this bit), and
492	* (b) turning off paging causes a #GP (unavoidable when switching
493	* from long to 32 bits mode or 32 bits to PAE).
494	*
495	* They should fix their code, but until they do we simply refuse to run.
496	*/
497	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
498	}
499
500	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
501	if it wasn't so before (some software could incorrectly
502	think it's in VMX mode). */
503	ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
504	ASMSetFlags(fFlags);
505
506	RTR0MemObjFree(hScatchMemObj, false);
507	}
508	}
509	else
510	{
511	AssertFailed(); /* can't hit this case anymore */
512	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
513	}
514
515	if (g_HvmR0.vmx.fSupported)
516	{
517	/* Call the global VT-x initialization routine. */
518	rc = VMXR0GlobalInit();
519	if (RT_FAILURE(rc))
520	g_HvmR0.lLastError = rc;
521
522	/*
523	* Install the VT-x methods.
524	*/
525	g_HvmR0.pfnEnterSession = VMXR0Enter;
526	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
527	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
528	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
529	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
530	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
531	g_HvmR0.pfnInitVM = VMXR0InitVM;
532	g_HvmR0.pfnTermVM = VMXR0TermVM;
533	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
534
535	/*
536	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
537	* Timer Does Not Count Down at the Rate Specified" erratum.
538	*/
539	if (g_HvmR0.vmx.msr.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
540	{
541	g_HvmR0.vmx.fUsePreemptTimer = true;
542	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.u64Misc);
543	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
544	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
545	}
546	}
547	}
548	#ifdef LOG_ENABLED
549	else
550	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
551	#endif
552	}
553	else
554	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
555	return VINF_SUCCESS;
556	}
557
558
559	/**
560	* AMD-specific initialization code.
561	*
562	* @returns VBox status code.
563	*/
564	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
565	{
566	/*
567	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
568	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
569	*/
570	int rc;
571	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
572	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
573	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
574	&& ASMIsValidExtRange(uMaxExtLeaf)
575	&& uMaxExtLeaf >= 0x8000000a
576	)
577	{
578	/* Call the global AMD-V initialization routine. */
579	rc = SVMR0GlobalInit();
580	if (RT_FAILURE(rc))
581	{
582	g_HvmR0.lLastError = rc;
583	return rc;
584	}
585
586	/*
587	* Install the AMD-V methods.
588	*/
589	g_HvmR0.pfnEnterSession = SVMR0Enter;
590	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
591	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
592	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
593	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
594	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
595	g_HvmR0.pfnInitVM = SVMR0InitVM;
596	g_HvmR0.pfnTermVM = SVMR0TermVM;
597	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
598
599	/* Query AMD features. */
600	uint32_t u32Dummy;
601	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
602
603	/*
604	* We need to check if AMD-V has been properly initialized on all CPUs.
605	* Some BIOSes might do a poor job.
606	*/
607	HMR0FIRSTRC FirstRc;
608	hmR0FirstRcInit(&FirstRc);
609	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
610	AssertRC(rc);
611	if (RT_SUCCESS(rc))
612	rc = hmR0FirstRcGetStatus(&FirstRc);
613	#ifndef DEBUG_bird
614	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
615	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
616	#endif
617	if (RT_SUCCESS(rc))
618	{
619	/* Read the HWCR MSR for diagnostics. */
620	g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
621	g_HvmR0.svm.fSupported = true;
622	}
623	else
624	g_HvmR0.lLastError = rc;
625	}
626	else
627	{
628	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
629	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
630	}
631	return rc;
632	}
633
634
635	/**
636	* Does global Ring-0 HM initialization (at module init).
637	*
638	* @returns VBox status code.
639	*/
640	VMMR0_INT_DECL(int) HMR0Init(void)
641	{
642	/*
643	* Initialize the globals.
644	*/
645	g_HvmR0.fEnabled = false;
646	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
647	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
648	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
649	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
650
651	/* Fill in all callbacks with placeholders. */
652	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
653	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
654	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
655	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
656	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
657	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
658	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
659	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
660	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
661
662	/* Default is global VT-x/AMD-V init. */
663	g_HvmR0.fGlobalInit = true;
664
665	/*
666	* Make sure aCpuInfo is big enough for all the CPUs on this system.
667	*/
668	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
669	{
670	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
671	return VERR_TOO_MANY_CPUS;
672	}
673
674	/*
675	* Check for VT-x and AMD-V capabilities.
676	*/
677	int rc;
678	if (ASMHasCpuId())
679	{
680	/* Standard features. */
681	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
682	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
683	if (ASMIsValidStdRange(uMaxLeaf))
684	{
685	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
686	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
687
688	/* Query AMD features. */
689	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
690	if (ASMIsValidExtRange(uMaxExtLeaf))
691	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
692	&g_HvmR0.cpuid.u32AMDFeatureECX,
693	&g_HvmR0.cpuid.u32AMDFeatureEDX);
694	else
695	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
696
697	/* Go to CPU specific initialization code. */
698	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
699	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
700	{
701	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
702	if (RT_FAILURE(rc))
703	return rc;
704	}
705	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
706	{
707	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
708	if (RT_FAILURE(rc))
709	return rc;
710	}
711	else
712	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
713	}
714	else
715	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
716	}
717	else
718	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
719
720	/*
721	* Register notification callbacks that we can use to disable/enable CPUs
722	* when brought offline/online or suspending/resuming.
723	*/
724	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
725	{
726	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
727	AssertRC(rc);
728
729	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
730	AssertRC(rc);
731	}
732
733	/* We return success here because module init shall not fail if HM
734	fails to initialize. */
735	return VINF_SUCCESS;
736	}
737
738
739	/**
740	* Does global Ring-0 HM termination (at module termination).
741	*
742	* @returns VBox status code.
743	*/
744	VMMR0_INT_DECL(int) HMR0Term(void)
745	{
746	int rc;
747	if ( g_HvmR0.vmx.fSupported
748	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
749	{
750	/*
751	* Simple if the host OS manages VT-x.
752	*/
753	Assert(g_HvmR0.fGlobalInit);
754	rc = SUPR0EnableVTx(false /* fEnable */);
755
756	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
757	{
758	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
759	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
760	}
761	}
762	else
763	{
764	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
765	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
766	{
767	/* Doesn't really matter if this fails. */
768	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
769	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
770	}
771	else
772	rc = VINF_SUCCESS;
773
774	/*
775	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
776	*/
777	if (g_HvmR0.fGlobalInit)
778	{
779	HMR0FIRSTRC FirstRc;
780	hmR0FirstRcInit(&FirstRc);
781	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
782	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
783	if (RT_SUCCESS(rc))
784	{
785	rc = hmR0FirstRcGetStatus(&FirstRc);
786	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
787	}
788	}
789
790	/*
791	* Free the per-cpu pages used for VT-x and AMD-V.
792	*/
793	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
794	{
795	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
796	{
797	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
798	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
799	}
800	}
801	}
802
803	/** @todo This needs cleaning up. There's no matching
804	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
805	* should move into their respective modules. */
806	/* Finally, call global VT-x/AMD-V termination. */
807	if (g_HvmR0.vmx.fSupported)
808	VMXR0GlobalTerm();
809	else if (g_HvmR0.svm.fSupported)
810	SVMR0GlobalTerm();
811
812	return rc;
813	}
814
815
816	/**
817	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
818	* VT-x on a CPU.
819	*
820	* @param idCpu The identifier for the CPU the function is called on.
821	* @param pvUser1 Pointer to the first RC structure.
822	* @param pvUser2 Ignored.
823	*/
824	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
825	{
826	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
827	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
828	NOREF(pvUser2);
829
830	/*
831	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
832	* Once the lock bit is set, this MSR can no longer be modified.
833	*/
834	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
835	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
836	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
837	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
838	)
839	{
840	/* MSR is not yet locked; we can change it ourselves here. */
841	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
842	g_HvmR0.vmx.msr.u64FeatureCtrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
843	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
844	}
845
846	int rc;
847	if ((fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
848	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
849	{
850	rc = VINF_SUCCESS;
851	}
852	else
853	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
854
855	hmR0FirstRcSetStatus(pFirstRc, rc);
856	}
857
858
859	/**
860	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
861	* on a CPU.
862	*
863	* @param idCpu The identifier for the CPU the function is called on.
864	* @param pvUser1 Pointer to the first RC structure.
865	* @param pvUser2 Ignored.
866	*/
867	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
868	{
869	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
870	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
871	NOREF(pvUser2);
872
873	/* Check if SVM is disabled. */
874	int rc;
875	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
876	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
877	{
878	/* Turn on SVM in the EFER MSR. */
879	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
880	if (fEfer & MSR_K6_EFER_SVME)
881	rc = VERR_SVM_IN_USE;
882	else
883	{
884	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
885
886	/* Paranoia. */
887	fEfer = ASMRdMsr(MSR_K6_EFER);
888	if (fEfer & MSR_K6_EFER_SVME)
889	{
890	/* Restore previous value. */
891	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
892	rc = VINF_SUCCESS;
893	}
894	else
895	rc = VERR_SVM_ILLEGAL_EFER_MSR;
896	}
897	}
898	else
899	rc = VERR_SVM_DISABLED;
900
901	hmR0FirstRcSetStatus(pFirstRc, rc);
902	}
903
904
905	/**
906	* Enable VT-x or AMD-V on the current CPU
907	*
908	* @returns VBox status code.
909	* @param pVM Pointer to the VM (can be NULL).
910	* @param idCpu The identifier for the CPU the function is called on.
911	*/
912	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
913	{
914	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
915
916	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
917	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
918	Assert(!pCpu->fConfigured);
919
920	pCpu->idCpu = idCpu;
921	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
922	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
923
924	int rc;
925	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
926	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true);
927	else
928	{
929	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
930	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
931	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
932	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
933	}
934	AssertRC(rc);
935	if (RT_SUCCESS(rc))
936	pCpu->fConfigured = true;
937
938	return rc;
939	}
940
941
942	/**
943	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
944	* is to be called on the target cpus.
945	*
946	* @param idCpu The identifier for the CPU the function is called on.
947	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
948	* @param pvUser2 The 2nd user argument.
949	*/
950	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
951	{
952	PVM pVM = (PVM)pvUser1; /* can be NULL! */
953	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
954	AssertReturnVoid(g_HvmR0.fGlobalInit);
955	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
956	}
957
958
959	/**
960	* RTOnce callback employed by HMR0EnableAllCpus.
961	*
962	* @returns VBox status code.
963	* @param pvUser Pointer to the VM.
964	* @param pvUserIgnore NULL, ignored.
965	*/
966	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
967	{
968	PVM pVM = (PVM)pvUser;
969
970	/*
971	* Indicate that we've initialized.
972	*
973	* Note! There is a potential race between this function and the suspend
974	* notification. Kind of unlikely though, so ignored for now.
975	*/
976	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
977	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
978
979	/*
980	* The global init variable is set by the first VM.
981	*/
982	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
983
984	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
985	{
986	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
987	g_HvmR0.aCpuInfo[i].fConfigured = false;
988	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
989	g_HvmR0.aCpuInfo[i].uCurrentAsid = 0;
990	}
991
992	int rc;
993	if ( g_HvmR0.vmx.fSupported
994	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
995	{
996	/*
997	* Global VT-x initialization API (only darwin for now).
998	*/
999	rc = SUPR0EnableVTx(true /* fEnable */);
1000	if (RT_SUCCESS(rc))
1001	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
1002	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
1003	else
1004	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
1005	}
1006	else
1007	{
1008	/*
1009	* We're doing the job ourselves.
1010	*/
1011	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
1012	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1013	{
1014	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1015
1016	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1017	{
1018	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1019	AssertLogRelRCReturn(rc, rc);
1020
1021	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1022	ASMMemZeroPage(pvR0);
1023	}
1024	}
1025
1026	rc = VINF_SUCCESS;
1027	}
1028
1029	if ( RT_SUCCESS(rc)
1030	&& g_HvmR0.fGlobalInit)
1031	{
1032	/* First time, so initialize each cpu/core. */
1033	HMR0FIRSTRC FirstRc;
1034	hmR0FirstRcInit(&FirstRc);
1035	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1036	if (RT_SUCCESS(rc))
1037	rc = hmR0FirstRcGetStatus(&FirstRc);
1038	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1039	}
1040
1041	return rc;
1042	}
1043
1044
1045	/**
1046	* Sets up HM on all cpus.
1047	*
1048	* @returns VBox status code.
1049	* @param pVM Pointer to the VM.
1050	*/
1051	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1052	{
1053	/* Make sure we don't touch HM after we've disabled HM in
1054	preparation of a suspend. */
1055	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1056	return VERR_HM_SUSPEND_PENDING;
1057
1058	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1059	}
1060
1061
1062	/**
1063	* Disable VT-x or AMD-V on the current CPU.
1064	*
1065	* @returns VBox status code.
1066	* @param idCpu The identifier for the CPU the function is called on.
1067	*/
1068	static int hmR0DisableCpu(RTCPUID idCpu)
1069	{
1070	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1071
1072	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1073	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1074	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1075	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1076
1077	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1078	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1079
1080	int rc;
1081	if (pCpu->fConfigured)
1082	{
1083	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1084	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1085	if (idCpu == RTMpCpuId())
1086	{
1087	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1088	AssertRC(rc);
1089	}
1090	else
1091	{
1092	pCpu->fIgnoreAMDVInUseError = true;
1093	rc = VINF_SUCCESS;
1094	}
1095
1096	pCpu->fConfigured = false;
1097	}
1098	else
1099	rc = VINF_SUCCESS; /* nothing to do */
1100
1101	pCpu->uCurrentAsid = 0;
1102	return rc;
1103	}
1104
1105
1106	/**
1107	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1108	* is to be called on the target CPUs.
1109	*
1110	* @param idCpu The identifier for the CPU the function is called on.
1111	* @param pvUser1 The 1st user argument.
1112	* @param pvUser2 Opaque pointer to the FirstRc.
1113	*/
1114	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1115	{
1116	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1117	AssertReturnVoid(g_HvmR0.fGlobalInit);
1118	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1119	}
1120
1121
1122	/**
1123	* Callback function invoked when a cpu goes online or offline.
1124	*
1125	* @param enmEvent The Mp event.
1126	* @param idCpu The identifier for the CPU the function is called on.
1127	* @param pvData Opaque data (PVM pointer).
1128	*/
1129	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1130	{
1131	NOREF(pvData);
1132
1133	/*
1134	* We only care about uninitializing a CPU that is going offline. When a
1135	* CPU comes online, the initialization is done lazily in HMR0Enter().
1136	*/
1137	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1138	switch (enmEvent)
1139	{
1140	case RTMPEVENT_OFFLINE:
1141	{
1142	int rc = hmR0DisableCpu(idCpu);
1143	AssertRC(rc);
1144	break;
1145	}
1146
1147	default:
1148	break;
1149	}
1150	}
1151
1152
1153	/**
1154	* Called whenever a system power state change occurs.
1155	*
1156	* @param enmEvent The Power event.
1157	* @param pvUser User argument.
1158	*/
1159	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1160	{
1161	NOREF(pvUser);
1162	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1163
1164	#ifdef LOG_ENABLED
1165	if (enmEvent == RTPOWEREVENT_SUSPEND)
1166	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1167	else
1168	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1169	#endif
1170
1171	if (enmEvent == RTPOWEREVENT_SUSPEND)
1172	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1173
1174	if (g_HvmR0.fEnabled)
1175	{
1176	int rc;
1177	HMR0FIRSTRC FirstRc;
1178	hmR0FirstRcInit(&FirstRc);
1179
1180	if (enmEvent == RTPOWEREVENT_SUSPEND)
1181	{
1182	if (g_HvmR0.fGlobalInit)
1183	{
1184	/* Turn off VT-x or AMD-V on all CPUs. */
1185	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1186	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1187	}
1188	/* else nothing to do here for the local init case */
1189	}
1190	else
1191	{
1192	/* Reinit the CPUs from scratch as the suspend state might have
1193	messed with the MSRs. (lousy BIOSes as usual) */
1194	if (g_HvmR0.vmx.fSupported)
1195	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1196	else
1197	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1198	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1199	if (RT_SUCCESS(rc))
1200	rc = hmR0FirstRcGetStatus(&FirstRc);
1201	#ifdef LOG_ENABLED
1202	if (RT_FAILURE(rc))
1203	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1204	#endif
1205	if (g_HvmR0.fGlobalInit)
1206	{
1207	/* Turn VT-x or AMD-V back on on all CPUs. */
1208	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1209	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1210	}
1211	/* else nothing to do here for the local init case */
1212	}
1213	}
1214
1215	if (enmEvent == RTPOWEREVENT_RESUME)
1216	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1217	}
1218
1219
1220	/**
1221	* Does Ring-0 per VM HM initialization.
1222	*
1223	* This will copy HM global into the VM structure and call the CPU specific
1224	* init routine which will allocate resources for each virtual CPU and such.
1225	*
1226	* @returns VBox status code.
1227	* @param pVM Pointer to the VM.
1228	*/
1229	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1230	{
1231	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1232
1233	#ifdef LOG_ENABLED
1234	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1235	#endif
1236
1237	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1238	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1239	return VERR_HM_SUSPEND_PENDING;
1240
1241	/*
1242	* Copy globals to the VM structure.
1243	*/
1244	/** @todo r=ramshankar: Why do we do this for MSRs? We never change them in the
1245	* per-VM structures anyway... */
1246	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1247	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1248
1249	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1250	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1251	pVM->hm.s.vmx.msr.u64FeatureCtrl = g_HvmR0.vmx.msr.u64FeatureCtrl;
1252	pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4;
1253	pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer;
1254	pVM->hm.s.vmx.msr.u64BasicInfo = g_HvmR0.vmx.msr.u64BasicInfo;
1255	pVM->hm.s.vmx.msr.VmxPinCtls = g_HvmR0.vmx.msr.VmxPinCtls;
1256	pVM->hm.s.vmx.msr.VmxProcCtls = g_HvmR0.vmx.msr.VmxProcCtls;
1257	pVM->hm.s.vmx.msr.VmxProcCtls2 = g_HvmR0.vmx.msr.VmxProcCtls2;
1258	pVM->hm.s.vmx.msr.VmxExit = g_HvmR0.vmx.msr.VmxExit;
1259	pVM->hm.s.vmx.msr.VmxEntry = g_HvmR0.vmx.msr.VmxEntry;
1260	pVM->hm.s.vmx.msr.u64Misc = g_HvmR0.vmx.msr.u64Misc;
1261	pVM->hm.s.vmx.msr.u64Cr0Fixed0 = g_HvmR0.vmx.msr.u64Cr0Fixed0;
1262	pVM->hm.s.vmx.msr.u64Cr0Fixed1 = g_HvmR0.vmx.msr.u64Cr0Fixed1;
1263	pVM->hm.s.vmx.msr.u64Cr4Fixed0 = g_HvmR0.vmx.msr.u64Cr4Fixed0;
1264	pVM->hm.s.vmx.msr.u64Cr4Fixed1 = g_HvmR0.vmx.msr.u64Cr4Fixed1;
1265	pVM->hm.s.vmx.msr.u64VmcsEnum = g_HvmR0.vmx.msr.u64VmcsEnum;
1266	pVM->hm.s.vmx.msr.u64Vmfunc = g_HvmR0.vmx.msr.u64Vmfunc;
1267	pVM->hm.s.vmx.msr.u64EptVpidCaps = g_HvmR0.vmx.msr.u64EptVpidCaps;
1268	pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr;
1269	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1270	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1271	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1272	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1273	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1274
1275	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1276
1277
1278	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1279	{
1280	pVM->hm.s.cMaxResumeLoops = 1024;
1281	if (RTThreadPreemptIsPendingTrusty())
1282	pVM->hm.s.cMaxResumeLoops = 8192;
1283	}
1284
1285	/*
1286	* Initialize some per CPU fields.
1287	*/
1288	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1289	{
1290	PVMCPU pVCpu = &pVM->aCpus[i];
1291
1292	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1293
1294	/* Invalidate the last cpu we were running on. */
1295	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1296
1297	/* We'll aways increment this the first time (host uses ASID 0) */
1298	pVCpu->hm.s.uCurrentAsid = 0;
1299	}
1300
1301	/*
1302	* Call the hardware specific initialization method.
1303	*/
1304	RTCCUINTREG fFlags = ASMIntDisableFlags();
1305	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1306	ASMSetFlags(fFlags);
1307
1308	int rc = g_HvmR0.pfnInitVM(pVM);
1309	return rc;
1310	}
1311
1312
1313	/**
1314	* Does Ring-0 per VM HM termination.
1315	*
1316	* @returns VBox status code.
1317	* @param pVM Pointer to the VM.
1318	*/
1319	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1320	{
1321	Log(("HMR0TermVM: %p\n", pVM));
1322	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1323
1324	/* Make sure we don't touch HM after we've disabled HM in preparation
1325	of a suspend. */
1326	/** @todo r=bird: This cannot be right, the termination functions are
1327	* just freeing memory and resetting pVM/pVCpu members...
1328	* ==> memory leak. */
1329	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1330
1331	/*
1332	* Call the hardware specific method.
1333	*/
1334	RTCCUINTREG fFlags = ASMIntDisableFlags();
1335	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1336	ASMSetFlags(fFlags);
1337
1338	int rc = g_HvmR0.pfnTermVM(pVM);
1339	return rc;
1340	}
1341
1342
1343	/**
1344	* Sets up a VT-x or AMD-V session.
1345	*
1346	* This is mostly about setting up the hardware VM state.
1347	*
1348	* @returns VBox status code.
1349	* @param pVM Pointer to the VM.
1350	*/
1351	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1352	{
1353	Log(("HMR0SetupVM: %p\n", pVM));
1354	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1355
1356	/* Make sure we don't touch HM after we've disabled HM in
1357	preparation of a suspend. */
1358	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1359
1360	/*
1361	* Call the hardware specific setup VM method. This requires the CPU to be
1362	* enabled for AMD-V/VT-x and preemption to be prevented.
1363	*/
1364	RTCCUINTREG fFlags = ASMIntDisableFlags();
1365	RTCPUID idCpu = RTMpCpuId();
1366	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1367
1368	/* On first entry we'll sync everything. */
1369	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1370	pVM->aCpus[i].hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1371
1372	/* Enable VT-x or AMD-V if local init is required. */
1373	int rc;
1374	if (!g_HvmR0.fGlobalInit)
1375	{
1376	rc = hmR0EnableCpu(pVM, idCpu);
1377	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1378	}
1379
1380	/* Setup VT-x or AMD-V. */
1381	rc = g_HvmR0.pfnSetupVM(pVM);
1382
1383	/* Disable VT-x or AMD-V if local init was done before. */
1384	if (!g_HvmR0.fGlobalInit)
1385	{
1386	int rc2 = hmR0DisableCpu(idCpu);
1387	AssertRC(rc2);
1388	}
1389
1390	ASMSetFlags(fFlags);
1391	return rc;
1392	}
1393
1394
1395	/**
1396	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1397	* required for entering HM context.
1398	*
1399	* @returns VBox status code.
1400	* @param pvCpu Pointer to the VMCPU.
1401	*
1402	* @remarks No-long-jump zone!!!
1403	*/
1404	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1405	{
1406	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1407
1408	int rc = VINF_SUCCESS;
1409	RTCPUID idCpu = RTMpCpuId();
1410	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1411	AssertPtr(pCpu);
1412
1413	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1414	if (!pCpu->fConfigured)
1415	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1416
1417	/* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
1418	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE;
1419	pVCpu->hm.s.idEnteredCpu = idCpu;
1420	return rc;
1421	}
1422
1423
1424	/**
1425	* Enters the VT-x or AMD-V session.
1426	*
1427	* @returns VBox status code.
1428	* @param pVM Pointer to the VM.
1429	* @param pVCpu Pointer to the VMCPU.
1430	*
1431	* @remarks This is called with preemption disabled.
1432	*/
1433	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1434	{
1435	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1436	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1437	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1438
1439	/* Load the bare minimum state required for entering HM. */
1440	int rc = HMR0EnterCpu(pVCpu);
1441	AssertRCReturn(rc, rc);
1442
1443	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1444	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1445	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1446	#endif
1447
1448	RTCPUID idCpu = RTMpCpuId();
1449	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1450	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1451	Assert(pCpu);
1452	Assert(pCtx);
1453	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1454
1455	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1456	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1457
1458	/* Load the host as we may be resuming code after a longjmp and quite
1459	possibly now be scheduled on a different CPU. */
1460	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1461	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1462
1463	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1464	if (fStartedSet)
1465	PGMRZDynMapReleaseAutoSet(pVCpu);
1466	#endif
1467
1468	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1469	and ring-3 calls. */
1470	if (RT_FAILURE(rc))
1471	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1472	return rc;
1473	}
1474
1475
1476	/**
1477	* Deinitializes the bare minimum state used for HM context and if necessary
1478	* disable HM on the CPU.
1479	*
1480	* @returns VBox status code.
1481	* @param pVCpu Pointer to the VMCPU.
1482	*
1483	* @remarks No-long-jump zone!!!
1484	*/
1485	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1486	{
1487	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1488
1489	RTCPUID idCpu = RTMpCpuId();
1490	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1491
1492	if ( !g_HvmR0.fGlobalInit
1493	&& pCpu->fConfigured)
1494	{
1495	int rc = hmR0DisableCpu(idCpu);
1496	AssertRCReturn(rc, rc);
1497	Assert(!pCpu->fConfigured);
1498	}
1499
1500	/* Reset these to force a TLB flush for the next entry. */
1501	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1502	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1503	pVCpu->hm.s.uCurrentAsid = 0;
1504	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1505
1506	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1507	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1508
1509	return VINF_SUCCESS;
1510	}
1511
1512
1513	/**
1514	* Thread-context hook for HM.
1515	*
1516	* @param enmEvent The thread-context event.
1517	* @param pvUser Opaque pointer to the VMCPU.
1518	*/
1519	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1520	{
1521	PVMCPU pVCpu = (PVMCPU)pvUser;
1522	Assert(pVCpu);
1523	Assert(g_HvmR0.pfnThreadCtxCallback);
1524
1525	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1526	}
1527
1528
1529	/**
1530	* Runs guest code in a hardware accelerated VM.
1531	*
1532	* @returns VBox status code.
1533	* @param pVM Pointer to the VM.
1534	* @param pVCpu Pointer to the VMCPU.
1535	*
1536	* @remarks Called with preemption disabled and after first having called
1537	* HMR0Enter.
1538	*/
1539	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1540	{
1541	#ifdef VBOX_STRICT
1542	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1543	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1544	Assert(pCpu->fConfigured);
1545	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1546	#endif
1547
1548	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1549	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1550	PGMRZDynMapStartAutoSet(pVCpu);
1551	#endif
1552
1553	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1554
1555	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1556	PGMRZDynMapReleaseAutoSet(pVCpu);
1557	#endif
1558	return rc;
1559	}
1560
1561	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1562
1563	/**
1564	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1565	*
1566	* @returns VBox status code.
1567	* @param pVM Pointer to the VM.
1568	* @param pVCpu Pointer to the VMCPU.
1569	* @param pCtx Pointer to the guest CPU context.
1570	*/
1571	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1572	{
1573	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1574	if (pVM->hm.s.vmx.fSupported)
1575	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1576	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1577	}
1578
1579
1580	/**
1581	* Save guest debug state (64 bits guest mode & 32 bits host only)
1582	*
1583	* @returns VBox status code.
1584	* @param pVM Pointer to the VM.
1585	* @param pVCpu Pointer to the VMCPU.
1586	* @param pCtx Pointer to the guest CPU context.
1587	*/
1588	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1589	{
1590	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1591	if (pVM->hm.s.vmx.fSupported)
1592	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1593	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1594	}
1595
1596
1597	/**
1598	* Test the 32->64 bits switcher.
1599	*
1600	* @returns VBox status code.
1601	* @param pVM Pointer to the VM.
1602	*/
1603	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1604	{
1605	PVMCPU pVCpu = &pVM->aCpus[0];
1606	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1607	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1608	int rc;
1609
1610	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1611	if (pVM->hm.s.vmx.fSupported)
1612	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1613	else
1614	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1615	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1616
1617	return rc;
1618	}
1619
1620	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1621
1622	/**
1623	* Returns suspend status of the host.
1624	*
1625	* @returns Suspend pending or not.
1626	*/
1627	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1628	{
1629	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1630	}
1631
1632
1633	/**
1634	* Returns the cpu structure for the current cpu.
1635	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1636	*
1637	* @returns The cpu structure pointer.
1638	*/
1639	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1640	{
1641	RTCPUID idCpu = RTMpCpuId();
1642	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1643	return &g_HvmR0.aCpuInfo[idCpu];
1644	}
1645
1646
1647	/**
1648	* Returns the cpu structure for the current cpu.
1649	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1650	*
1651	* @returns The cpu structure pointer.
1652	* @param idCpu id of the VCPU.
1653	*/
1654	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1655	{
1656	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1657	return &g_HvmR0.aCpuInfo[idCpu];
1658	}
1659
1660
1661	/**
1662	* Save a pending IO read.
1663	*
1664	* @param pVCpu Pointer to the VMCPU.
1665	* @param GCPtrRip Address of IO instruction.
1666	* @param GCPtrRipNext Address of the next instruction.
1667	* @param uPort Port address.
1668	* @param uAndVal AND mask for saving the result in eax.
1669	* @param cbSize Read size.
1670	*/
1671	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1672	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1673	{
1674	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1675	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1676	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1677	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1678	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1679	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1680	return;
1681	}
1682
1683
1684	/**
1685	* Save a pending IO write.
1686	*
1687	* @param pVCpu Pointer to the VMCPU.
1688	* @param GCPtrRIP Address of IO instruction.
1689	* @param uPort Port address.
1690	* @param uAndVal AND mask for fetching the result from eax.
1691	* @param cbSize Read size.
1692	*/
1693	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1694	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1695	{
1696	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1697	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1698	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1699	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1700	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1701	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1702	return;
1703	}
1704
1705
1706	/**
1707	* Raw-mode switcher hook - disable VT-x if it's active and the current
1708	* switcher turns off paging.
1709	*
1710	* @returns VBox status code.
1711	* @param pVM Pointer to the VM.
1712	* @param enmSwitcher The switcher we're about to use.
1713	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1714	*/
1715	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1716	{
1717	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1718
1719	*pfVTxDisabled = false;
1720
1721	/* No such issues with AMD-V */
1722	if (!g_HvmR0.vmx.fSupported)
1723	return VINF_SUCCESS;
1724
1725	/* Check if the swithcing we're up to is safe. */
1726	switch (enmSwitcher)
1727	{
1728	case VMMSWITCHER_32_TO_32:
1729	case VMMSWITCHER_PAE_TO_PAE:
1730	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1731
1732	case VMMSWITCHER_32_TO_PAE:
1733	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1734	case VMMSWITCHER_AMD64_TO_32:
1735	case VMMSWITCHER_AMD64_TO_PAE:
1736	break; /* unsafe switchers */
1737
1738	default:
1739	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1740	}
1741
1742	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1743	regardless of whether we're currently using VT-x or not. */
1744	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1745	{
1746	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1747	return VINF_SUCCESS;
1748	}
1749
1750	/** @todo Check if this code is presumtive wrt other VT-x users on the
1751	* system... */
1752
1753	/* Nothing to do if we haven't enabled VT-x. */
1754	if (!g_HvmR0.fEnabled)
1755	return VINF_SUCCESS;
1756
1757	/* Local init implies the CPU is currently not in VMX root mode. */
1758	if (!g_HvmR0.fGlobalInit)
1759	return VINF_SUCCESS;
1760
1761	/* Ok, disable VT-x. */
1762	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1763	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1764
1765	*pfVTxDisabled = true;
1766	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1767	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1768	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1769	}
1770
1771
1772	/**
1773	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1774	* switcher turned off paging.
1775	*
1776	* @param pVM Pointer to the VM.
1777	* @param fVTxDisabled Whether VT-x was disabled or not.
1778	*/
1779	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1780	{
1781	Assert(!(ASMGetFlags() & X86_EFL_IF));
1782
1783	if (!fVTxDisabled)
1784	return; /* nothing to do */
1785
1786	Assert(g_HvmR0.vmx.fSupported);
1787	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1788	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1789	else
1790	{
1791	Assert(g_HvmR0.fEnabled);
1792	Assert(g_HvmR0.fGlobalInit);
1793
1794	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1795	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1796
1797	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1798	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1799	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
1800	}
1801	}
1802
1803	#ifdef VBOX_STRICT
1804
1805	/**
1806	* Dumps a descriptor.
1807	*
1808	* @param pDesc Descriptor to dump.
1809	* @param Sel Selector number.
1810	* @param pszMsg Message to prepend the log entry with.
1811	*/
1812	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1813	{
1814	/*
1815	* Make variable description string.
1816	*/
1817	static struct
1818	{
1819	unsigned cch;
1820	const char *psz;
1821	} const s_aTypes[32] =
1822	{
1823	# define STRENTRY(str) { sizeof(str) - 1, str }
1824
1825	/* system */
1826	# if HC_ARCH_BITS == 64
1827	STRENTRY("Reserved0 "), /* 0x00 */
1828	STRENTRY("Reserved1 "), /* 0x01 */
1829	STRENTRY("LDT "), /* 0x02 */
1830	STRENTRY("Reserved3 "), /* 0x03 */
1831	STRENTRY("Reserved4 "), /* 0x04 */
1832	STRENTRY("Reserved5 "), /* 0x05 */
1833	STRENTRY("Reserved6 "), /* 0x06 */
1834	STRENTRY("Reserved7 "), /* 0x07 */
1835	STRENTRY("Reserved8 "), /* 0x08 */
1836	STRENTRY("TSS64Avail "), /* 0x09 */
1837	STRENTRY("ReservedA "), /* 0x0a */
1838	STRENTRY("TSS64Busy "), /* 0x0b */
1839	STRENTRY("Call64 "), /* 0x0c */
1840	STRENTRY("ReservedD "), /* 0x0d */
1841	STRENTRY("Int64 "), /* 0x0e */
1842	STRENTRY("Trap64 "), /* 0x0f */
1843	# else
1844	STRENTRY("Reserved0 "), /* 0x00 */
1845	STRENTRY("TSS16Avail "), /* 0x01 */
1846	STRENTRY("LDT "), /* 0x02 */
1847	STRENTRY("TSS16Busy "), /* 0x03 */
1848	STRENTRY("Call16 "), /* 0x04 */
1849	STRENTRY("Task "), /* 0x05 */
1850	STRENTRY("Int16 "), /* 0x06 */
1851	STRENTRY("Trap16 "), /* 0x07 */
1852	STRENTRY("Reserved8 "), /* 0x08 */
1853	STRENTRY("TSS32Avail "), /* 0x09 */
1854	STRENTRY("ReservedA "), /* 0x0a */
1855	STRENTRY("TSS32Busy "), /* 0x0b */
1856	STRENTRY("Call32 "), /* 0x0c */
1857	STRENTRY("ReservedD "), /* 0x0d */
1858	STRENTRY("Int32 "), /* 0x0e */
1859	STRENTRY("Trap32 "), /* 0x0f */
1860	# endif
1861	/* non system */
1862	STRENTRY("DataRO "), /* 0x10 */
1863	STRENTRY("DataRO Accessed "), /* 0x11 */
1864	STRENTRY("DataRW "), /* 0x12 */
1865	STRENTRY("DataRW Accessed "), /* 0x13 */
1866	STRENTRY("DataDownRO "), /* 0x14 */
1867	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1868	STRENTRY("DataDownRW "), /* 0x16 */
1869	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1870	STRENTRY("CodeEO "), /* 0x18 */
1871	STRENTRY("CodeEO Accessed "), /* 0x19 */
1872	STRENTRY("CodeER "), /* 0x1a */
1873	STRENTRY("CodeER Accessed "), /* 0x1b */
1874	STRENTRY("CodeConfEO "), /* 0x1c */
1875	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1876	STRENTRY("CodeConfER "), /* 0x1e */
1877	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1878	# undef SYSENTRY
1879	};
1880	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1881	char szMsg[128];
1882	char *psz = &szMsg[0];
1883	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1884	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1885	psz += s_aTypes[i].cch;
1886
1887	if (pDesc->Gen.u1Present)
1888	ADD_STR(psz, "Present ");
1889	else
1890	ADD_STR(psz, "Not-Present ");
1891	# if HC_ARCH_BITS == 64
1892	if (pDesc->Gen.u1Long)
1893	ADD_STR(psz, "64-bit ");
1894	else
1895	ADD_STR(psz, "Comp ");
1896	# else
1897	if (pDesc->Gen.u1Granularity)
1898	ADD_STR(psz, "Page ");
1899	if (pDesc->Gen.u1DefBig)
1900	ADD_STR(psz, "32-bit ");
1901	else
1902	ADD_STR(psz, "16-bit ");
1903	# endif
1904	# undef ADD_STR
1905	*psz = '\0';
1906
1907	/*
1908	* Limit and Base and format the output.
1909	*/
1910	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1911
1912	# if HC_ARCH_BITS == 64
1913	uint64_t u32Base = X86DESC64_BASE(pDesc);
1914
1915	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1916	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1917	# else
1918	uint32_t u32Base = X86DESC_BASE(pDesc);
1919
1920	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1921	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1922	# endif
1923	}
1924
1925
1926	/**
1927	* Formats a full register dump.
1928	*
1929	* @param pVM Pointer to the VM.
1930	* @param pVCpu Pointer to the VMCPU.
1931	* @param pCtx Pointer to the CPU context.
1932	*/
1933	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1934	{
1935	NOREF(pVM);
1936
1937	/*
1938	* Format the flags.
1939	*/
1940	static struct
1941	{
1942	const char pszSet; const char pszClear; uint32_t fFlag;
1943	} const s_aFlags[] =
1944	{
1945	{ "vip",NULL, X86_EFL_VIP },
1946	{ "vif",NULL, X86_EFL_VIF },
1947	{ "ac", NULL, X86_EFL_AC },
1948	{ "vm", NULL, X86_EFL_VM },
1949	{ "rf", NULL, X86_EFL_RF },
1950	{ "nt", NULL, X86_EFL_NT },
1951	{ "ov", "nv", X86_EFL_OF },
1952	{ "dn", "up", X86_EFL_DF },
1953	{ "ei", "di", X86_EFL_IF },
1954	{ "tf", NULL, X86_EFL_TF },
1955	{ "nt", "pl", X86_EFL_SF },
1956	{ "nz", "zr", X86_EFL_ZF },
1957	{ "ac", "na", X86_EFL_AF },
1958	{ "po", "pe", X86_EFL_PF },
1959	{ "cy", "nc", X86_EFL_CF },
1960	};
1961	char szEFlags[80];
1962	char *psz = szEFlags;
1963	uint32_t efl = pCtx->eflags.u32;
1964	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1965	{
1966	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1967	if (pszAdd)
1968	{
1969	strcpy(psz, pszAdd);
1970	psz += strlen(pszAdd);
1971	*psz++ = ' ';
1972	}
1973	}
1974	psz[-1] = '\0';
1975
1976
1977	/*
1978	* Format the registers.
1979	*/
1980	if (CPUMIsGuestIn64BitCode(pVCpu))
1981	{
1982	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1983	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1984	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1985	"r14=%016RX64 r15=%016RX64\n"
1986	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1987	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1988	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1989	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1990	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1991	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1992	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1993	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1994	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1995	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1996	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1997	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1998	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1999	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2000	,
2001	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
2002	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
2003	pCtx->r14, pCtx->r15,
2004	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2005	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2006	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2007	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2008	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2009	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2010	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2011	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
2012	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
2013	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2014	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2015	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2016	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2017	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2018	}
2019	else
2020	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2021	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2022	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2023	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2024	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2025	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2026	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2027	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2028	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2029	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2030	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2031	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2032	,
2033	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2034	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2035	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2036	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2037	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2038	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2039	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2040	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2041	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2042	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2043	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2044	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2045
2046	Log(("FPU:\n"
2047	"FCW=%04x FSW=%04x FTW=%02x\n"
2048	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2049	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2050	,
2051	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2052	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2053	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2054	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2055
2056
2057	Log(("MSR:\n"
2058	"EFER =%016RX64\n"
2059	"PAT =%016RX64\n"
2060	"STAR =%016RX64\n"
2061	"CSTAR =%016RX64\n"
2062	"LSTAR =%016RX64\n"
2063	"SFMASK =%016RX64\n"
2064	"KERNELGSBASE =%016RX64\n",
2065	pCtx->msrEFER,
2066	pCtx->msrPAT,
2067	pCtx->msrSTAR,
2068	pCtx->msrCSTAR,
2069	pCtx->msrLSTAR,
2070	pCtx->msrSFMASK,
2071	pCtx->msrKERNELGSBASE));
2072
2073	}
2074
2075	#endif /* VBOX_STRICT */
2076

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 48213

Download in other formats: