HMR0.cpp@ 48217

Last change on this file since 48217 was 48217, checked in by vboxsync, 11 years ago
VMM/HMR0: Spaces and populate struct members in the same order as their declaration whenever possible.
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1	/* $Id: HMR0.cpp 48217 2013-08-31 19:04:14Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	/** @todo This isn't used for anything relevant. Remove later? */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** VMX MSR values */
123	VMXMSRS Msrs;
124
125	/* Last instruction error */
126	uint32_t ulLastInstrError;
127	} vmx;
128
129	/** AMD-V information. */
130	struct
131	{
132	/* HWCR MSR (for diagnostics) */
133	uint64_t u64MsrHwcr;
134
135	/** SVM revision. */
136	uint32_t u32Rev;
137
138	/** SVM feature bits from cpuid 0x8000000a */
139	uint32_t u32Features;
140
141	/** Set by us to indicate SVM is supported by the CPU. */
142	bool fSupported;
143	} svm;
144	/** Saved error from detection */
145	int32_t lLastError;
146
147	struct
148	{
149	uint32_t u32AMDFeatureECX;
150	uint32_t u32AMDFeatureEDX;
151	} cpuid;
152
153	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
154	* enabled and disabled each time it's used to execute guest code. */
155	bool fGlobalInit;
156	/** Indicates whether the host is suspending or not. We'll refuse a few
157	* actions when the host is being suspended to speed up the suspending and
158	* avoid trouble. */
159	volatile bool fSuspended;
160
161	/** Whether we've already initialized all CPUs.
162	* @remarks We could check the EnableAllCpusOnce state, but this is
163	* simpler and hopefully easier to understand. */
164	bool fEnabled;
165	/** Serialize initialization in HMR0EnableAllCpus. */
166	RTONCE EnableAllCpusOnce;
167	} g_HvmR0;
168
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	/**
212	* Get the CPU ID on which the failure status code was reported.
213	*
214	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
215	* @param pFirstRc The first return code structure.
216	*/
217	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
218	{
219	return pFirstRc->idCpu;
220	}
221	#endif /* VBOX_STRICT */
222
223
224	/** @name Dummy callback handlers.
225	* @{ */
226
227	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
228	{
229	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
234	{
235	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
236	return VINF_SUCCESS;
237	}
238
239	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
240	{
241	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
242	}
243
244	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
245	bool fEnabledBySystem)
246	{
247	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem);
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
252	{
253	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
254	return VINF_SUCCESS;
255	}
256
257	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
258	{
259	NOREF(pVM);
260	return VINF_SUCCESS;
261	}
262
263	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
264	{
265	NOREF(pVM);
266	return VINF_SUCCESS;
267	}
268
269	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
270	{
271	NOREF(pVM);
272	return VINF_SUCCESS;
273	}
274
275	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
276	{
277	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
278	return VINF_SUCCESS;
279	}
280
281	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
282	{
283	NOREF(pVM); NOREF(pVCpu);
284	return VINF_SUCCESS;
285	}
286
287	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
288	{
289	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
290	return VINF_SUCCESS;
291	}
292
293	/** @} */
294
295
296	/**
297	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
298	* Down at the Rate Specified" erratum.
299	*
300	* Errata names and related steppings:
301	* - BA86 - D0.
302	* - AAX65 - C2.
303	* - AAU65 - C2, K0.
304	* - AAO95 - B1.
305	* - AAT59 - C2.
306	* - AAK139 - D0.
307	* - AAM126 - C0, C1, D0.
308	* - AAN92 - B1.
309	* - AAJ124 - C0, D0.
310	*
311	* - AAP86 - B1.
312	*
313	* Steppings: B1, C0, C1, C2, D0, K0.
314	*
315	* @returns true if subject to it, false if not.
316	*/
317	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
318	{
319	uint32_t u = ASMCpuId_EAX(1);
320	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
321	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
322	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
323	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
324	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
325	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
326	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
327	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
328	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
329	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
330	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
331	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
332	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
333	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
334	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
335	)
336	return true;
337	return false;
338	}
339
340
341	/**
342	* Intel specific initialization code.
343	*
344	* @returns VBox status code (will only fail if out of memory).
345	*/
346	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
347	{
348	/*
349	* Check that all the required VT-x features are present.
350	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
351	*/
352	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
353	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
354	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
355	)
356	{
357	/** @todo move this into a separate function. */
358	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
359
360	/*
361	* First try use native kernel API for controlling VT-x.
362	* (This is only supported by some Mac OS X kernels atm.)
363	*/
364	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
365	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
366	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
367	{
368	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
369	if (RT_SUCCESS(rc))
370	{
371	g_HvmR0.vmx.fSupported = true;
372	rc = SUPR0EnableVTx(false /* fEnable */);
373	AssertLogRelRC(rc);
374	}
375	}
376	else
377	{
378	/* We need to check if VT-x has been properly initialized on all
379	CPUs. Some BIOSes do a lousy job. */
380	HMR0FIRSTRC FirstRc;
381	hmR0FirstRcInit(&FirstRc);
382	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
383	if (RT_SUCCESS(g_HvmR0.lLastError))
384	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
385	}
386	if (RT_SUCCESS(g_HvmR0.lLastError))
387	{
388	/* Reread in case we've changed it. */
389	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
390
391	if ( (g_HvmR0.vmx.Msrs.u64FeatureCtrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
392	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
393	{
394	/*
395	* Read all relevant registers and MSRs.
396	*/
397	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
398	g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
399	g_HvmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
400	g_HvmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
401	g_HvmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
402	g_HvmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
403	g_HvmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
404	g_HvmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
405	g_HvmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
406	g_HvmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
407	g_HvmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
408	g_HvmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
409	g_HvmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
410	/* VPID 16 bits ASID. */
411	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
412
413	if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
414	{
415	g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
416	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
417	g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
418
419	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
420	g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
421	}
422
423	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
424	{
425	/*
426	* Enter root mode
427	*/
428	RTR0MEMOBJ hScatchMemObj;
429	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
430	if (RT_FAILURE(rc))
431	{
432	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
433	return rc;
434	}
435
436	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
437	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
438	ASMMemZeroPage(pvScatchPage);
439
440	/* Set revision dword at the beginning of the structure. */
441	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo);
442
443	/* Make sure we don't get rescheduled to another cpu during this probe. */
444	RTCCUINTREG fFlags = ASMIntDisableFlags();
445
446	/*
447	* Check CR4.VMXE
448	*/
449	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
450	if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
451	{
452	/* In theory this bit could be cleared behind our back. Which would cause
453	#UD faults when we try to execute the VMX instructions... */
454	ASMSetCR4(g_HvmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
455	}
456
457	/*
458	* The only way of checking if we're in VMX root mode or not is to try and enter it.
459	* There is no instruction or control bit that tells us if we're in VMX root mode.
460	* Therefore, try and enter VMX root mode here.
461	*/
462	rc = VMXEnable(HCPhysScratchPage);
463	if (RT_SUCCESS(rc))
464	{
465	g_HvmR0.vmx.fSupported = true;
466	VMXDisable();
467	}
468	else
469	{
470	/*
471	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
472	* it will crash the host when we enter raw mode, because:
473	*
474	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
475	* this bit), and
476	* (b) turning off paging causes a #GP (unavoidable when switching
477	* from long to 32 bits mode or 32 bits to PAE).
478	*
479	* They should fix their code, but until they do we simply refuse to run.
480	*/
481	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
482	}
483
484	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
485	if it wasn't so before (some software could incorrectly
486	think it's in VMX mode). */
487	ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
488	ASMSetFlags(fFlags);
489
490	RTR0MemObjFree(hScatchMemObj, false);
491	}
492	}
493	else
494	{
495	AssertFailed(); /* can't hit this case anymore */
496	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
497	}
498
499	if (g_HvmR0.vmx.fSupported)
500	{
501	/* Call the global VT-x initialization routine. */
502	rc = VMXR0GlobalInit();
503	if (RT_FAILURE(rc))
504	g_HvmR0.lLastError = rc;
505
506	/*
507	* Install the VT-x methods.
508	*/
509	g_HvmR0.pfnEnterSession = VMXR0Enter;
510	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
511	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
512	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
513	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
514	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
515	g_HvmR0.pfnInitVM = VMXR0InitVM;
516	g_HvmR0.pfnTermVM = VMXR0TermVM;
517	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
518
519	/*
520	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
521	* Timer Does Not Count Down at the Rate Specified" erratum.
522	*/
523	if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
524	{
525	g_HvmR0.vmx.fUsePreemptTimer = true;
526	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc);
527	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
528	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
529	}
530	}
531	}
532	#ifdef LOG_ENABLED
533	else
534	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
535	#endif
536	}
537	else
538	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
539	return VINF_SUCCESS;
540	}
541
542
543	/**
544	* AMD-specific initialization code.
545	*
546	* @returns VBox status code.
547	*/
548	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
549	{
550	/*
551	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
552	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
553	*/
554	int rc;
555	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
556	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
557	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
558	&& ASMIsValidExtRange(uMaxExtLeaf)
559	&& uMaxExtLeaf >= 0x8000000a
560	)
561	{
562	/* Call the global AMD-V initialization routine. */
563	rc = SVMR0GlobalInit();
564	if (RT_FAILURE(rc))
565	{
566	g_HvmR0.lLastError = rc;
567	return rc;
568	}
569
570	/*
571	* Install the AMD-V methods.
572	*/
573	g_HvmR0.pfnEnterSession = SVMR0Enter;
574	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
575	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
576	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
577	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
578	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
579	g_HvmR0.pfnInitVM = SVMR0InitVM;
580	g_HvmR0.pfnTermVM = SVMR0TermVM;
581	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
582
583	/* Query AMD features. */
584	uint32_t u32Dummy;
585	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
586
587	/*
588	* We need to check if AMD-V has been properly initialized on all CPUs.
589	* Some BIOSes might do a poor job.
590	*/
591	HMR0FIRSTRC FirstRc;
592	hmR0FirstRcInit(&FirstRc);
593	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
594	AssertRC(rc);
595	if (RT_SUCCESS(rc))
596	rc = hmR0FirstRcGetStatus(&FirstRc);
597	#ifndef DEBUG_bird
598	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
599	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
600	#endif
601	if (RT_SUCCESS(rc))
602	{
603	/* Read the HWCR MSR for diagnostics. */
604	g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
605	g_HvmR0.svm.fSupported = true;
606	}
607	else
608	g_HvmR0.lLastError = rc;
609	}
610	else
611	{
612	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
613	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
614	}
615	return rc;
616	}
617
618
619	/**
620	* Does global Ring-0 HM initialization (at module init).
621	*
622	* @returns VBox status code.
623	*/
624	VMMR0_INT_DECL(int) HMR0Init(void)
625	{
626	/*
627	* Initialize the globals.
628	*/
629	g_HvmR0.fEnabled = false;
630	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
631	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
632	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
633	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
634
635	/* Fill in all callbacks with placeholders. */
636	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
637	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
638	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
639	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
640	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
641	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
642	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
643	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
644	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
645
646	/* Default is global VT-x/AMD-V init. */
647	g_HvmR0.fGlobalInit = true;
648
649	/*
650	* Make sure aCpuInfo is big enough for all the CPUs on this system.
651	*/
652	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
653	{
654	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
655	return VERR_TOO_MANY_CPUS;
656	}
657
658	/*
659	* Check for VT-x and AMD-V capabilities.
660	*/
661	int rc;
662	if (ASMHasCpuId())
663	{
664	/* Standard features. */
665	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
666	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
667	if (ASMIsValidStdRange(uMaxLeaf))
668	{
669	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
670	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
671
672	/* Query AMD features. */
673	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
674	if (ASMIsValidExtRange(uMaxExtLeaf))
675	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
676	&g_HvmR0.cpuid.u32AMDFeatureECX,
677	&g_HvmR0.cpuid.u32AMDFeatureEDX);
678	else
679	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
680
681	/* Go to CPU specific initialization code. */
682	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
683	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
684	{
685	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
686	if (RT_FAILURE(rc))
687	return rc;
688	}
689	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
690	{
691	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
692	if (RT_FAILURE(rc))
693	return rc;
694	}
695	else
696	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
697	}
698	else
699	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
700	}
701	else
702	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
703
704	/*
705	* Register notification callbacks that we can use to disable/enable CPUs
706	* when brought offline/online or suspending/resuming.
707	*/
708	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
709	{
710	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
711	AssertRC(rc);
712
713	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
714	AssertRC(rc);
715	}
716
717	/* We return success here because module init shall not fail if HM
718	fails to initialize. */
719	return VINF_SUCCESS;
720	}
721
722
723	/**
724	* Does global Ring-0 HM termination (at module termination).
725	*
726	* @returns VBox status code.
727	*/
728	VMMR0_INT_DECL(int) HMR0Term(void)
729	{
730	int rc;
731	if ( g_HvmR0.vmx.fSupported
732	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
733	{
734	/*
735	* Simple if the host OS manages VT-x.
736	*/
737	Assert(g_HvmR0.fGlobalInit);
738	rc = SUPR0EnableVTx(false /* fEnable */);
739
740	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
741	{
742	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
743	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
744	}
745	}
746	else
747	{
748	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
749	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
750	{
751	/* Doesn't really matter if this fails. */
752	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
753	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
754	}
755	else
756	rc = VINF_SUCCESS;
757
758	/*
759	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
760	*/
761	if (g_HvmR0.fGlobalInit)
762	{
763	HMR0FIRSTRC FirstRc;
764	hmR0FirstRcInit(&FirstRc);
765	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
766	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
767	if (RT_SUCCESS(rc))
768	{
769	rc = hmR0FirstRcGetStatus(&FirstRc);
770	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
771	}
772	}
773
774	/*
775	* Free the per-cpu pages used for VT-x and AMD-V.
776	*/
777	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
778	{
779	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
780	{
781	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
782	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
783	}
784	}
785	}
786
787	/** @todo This needs cleaning up. There's no matching
788	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
789	* should move into their respective modules. */
790	/* Finally, call global VT-x/AMD-V termination. */
791	if (g_HvmR0.vmx.fSupported)
792	VMXR0GlobalTerm();
793	else if (g_HvmR0.svm.fSupported)
794	SVMR0GlobalTerm();
795
796	return rc;
797	}
798
799
800	/**
801	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
802	* VT-x on a CPU.
803	*
804	* @param idCpu The identifier for the CPU the function is called on.
805	* @param pvUser1 Pointer to the first RC structure.
806	* @param pvUser2 Ignored.
807	*/
808	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
809	{
810	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
811	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
812	NOREF(pvUser2);
813
814	/*
815	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
816	* Once the lock bit is set, this MSR can no longer be modified.
817	*/
818	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
819	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
820	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
821	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
822	)
823	{
824	/* MSR is not yet locked; we can change it ourselves here. */
825	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
826	g_HvmR0.vmx.Msrs.u64FeatureCtrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
827	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
828	}
829
830	int rc;
831	if ((fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
832	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
833	{
834	rc = VINF_SUCCESS;
835	}
836	else
837	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
838
839	hmR0FirstRcSetStatus(pFirstRc, rc);
840	}
841
842
843	/**
844	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
845	* on a CPU.
846	*
847	* @param idCpu The identifier for the CPU the function is called on.
848	* @param pvUser1 Pointer to the first RC structure.
849	* @param pvUser2 Ignored.
850	*/
851	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
852	{
853	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
854	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
855	NOREF(pvUser2);
856
857	/* Check if SVM is disabled. */
858	int rc;
859	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
860	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
861	{
862	/* Turn on SVM in the EFER MSR. */
863	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
864	if (fEfer & MSR_K6_EFER_SVME)
865	rc = VERR_SVM_IN_USE;
866	else
867	{
868	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
869
870	/* Paranoia. */
871	fEfer = ASMRdMsr(MSR_K6_EFER);
872	if (fEfer & MSR_K6_EFER_SVME)
873	{
874	/* Restore previous value. */
875	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
876	rc = VINF_SUCCESS;
877	}
878	else
879	rc = VERR_SVM_ILLEGAL_EFER_MSR;
880	}
881	}
882	else
883	rc = VERR_SVM_DISABLED;
884
885	hmR0FirstRcSetStatus(pFirstRc, rc);
886	}
887
888
889	/**
890	* Enable VT-x or AMD-V on the current CPU
891	*
892	* @returns VBox status code.
893	* @param pVM Pointer to the VM (can be NULL).
894	* @param idCpu The identifier for the CPU the function is called on.
895	*/
896	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
897	{
898	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
899
900	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
901	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
902	Assert(!pCpu->fConfigured);
903
904	pCpu->idCpu = idCpu;
905	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
906	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
907
908	int rc;
909	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
910	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true);
911	else
912	{
913	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
914	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
915	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
916	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
917	}
918	AssertRC(rc);
919	if (RT_SUCCESS(rc))
920	pCpu->fConfigured = true;
921
922	return rc;
923	}
924
925
926	/**
927	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
928	* is to be called on the target cpus.
929	*
930	* @param idCpu The identifier for the CPU the function is called on.
931	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
932	* @param pvUser2 The 2nd user argument.
933	*/
934	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
935	{
936	PVM pVM = (PVM)pvUser1; /* can be NULL! */
937	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
938	AssertReturnVoid(g_HvmR0.fGlobalInit);
939	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
940	}
941
942
943	/**
944	* RTOnce callback employed by HMR0EnableAllCpus.
945	*
946	* @returns VBox status code.
947	* @param pvUser Pointer to the VM.
948	* @param pvUserIgnore NULL, ignored.
949	*/
950	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
951	{
952	PVM pVM = (PVM)pvUser;
953
954	/*
955	* Indicate that we've initialized.
956	*
957	* Note! There is a potential race between this function and the suspend
958	* notification. Kind of unlikely though, so ignored for now.
959	*/
960	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
961	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
962
963	/*
964	* The global init variable is set by the first VM.
965	*/
966	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
967
968	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
969	{
970	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
971	g_HvmR0.aCpuInfo[i].fConfigured = false;
972	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
973	g_HvmR0.aCpuInfo[i].uCurrentAsid = 0;
974	}
975
976	int rc;
977	if ( g_HvmR0.vmx.fSupported
978	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
979	{
980	/*
981	* Global VT-x initialization API (only darwin for now).
982	*/
983	rc = SUPR0EnableVTx(true /* fEnable */);
984	if (RT_SUCCESS(rc))
985	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
986	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
987	else
988	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
989	}
990	else
991	{
992	/*
993	* We're doing the job ourselves.
994	*/
995	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
996	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
997	{
998	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
999
1000	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1001	{
1002	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1003	AssertLogRelRCReturn(rc, rc);
1004
1005	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1006	ASMMemZeroPage(pvR0);
1007	}
1008	}
1009
1010	rc = VINF_SUCCESS;
1011	}
1012
1013	if ( RT_SUCCESS(rc)
1014	&& g_HvmR0.fGlobalInit)
1015	{
1016	/* First time, so initialize each cpu/core. */
1017	HMR0FIRSTRC FirstRc;
1018	hmR0FirstRcInit(&FirstRc);
1019	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1020	if (RT_SUCCESS(rc))
1021	rc = hmR0FirstRcGetStatus(&FirstRc);
1022	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1023	}
1024
1025	return rc;
1026	}
1027
1028
1029	/**
1030	* Sets up HM on all cpus.
1031	*
1032	* @returns VBox status code.
1033	* @param pVM Pointer to the VM.
1034	*/
1035	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1036	{
1037	/* Make sure we don't touch HM after we've disabled HM in
1038	preparation of a suspend. */
1039	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1040	return VERR_HM_SUSPEND_PENDING;
1041
1042	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1043	}
1044
1045
1046	/**
1047	* Disable VT-x or AMD-V on the current CPU.
1048	*
1049	* @returns VBox status code.
1050	* @param idCpu The identifier for the CPU the function is called on.
1051	*/
1052	static int hmR0DisableCpu(RTCPUID idCpu)
1053	{
1054	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1055
1056	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1057	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1058	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1059	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1060
1061	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1062	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1063
1064	int rc;
1065	if (pCpu->fConfigured)
1066	{
1067	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1068	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1069	if (idCpu == RTMpCpuId())
1070	{
1071	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1072	AssertRC(rc);
1073	}
1074	else
1075	{
1076	pCpu->fIgnoreAMDVInUseError = true;
1077	rc = VINF_SUCCESS;
1078	}
1079
1080	pCpu->fConfigured = false;
1081	}
1082	else
1083	rc = VINF_SUCCESS; /* nothing to do */
1084
1085	pCpu->uCurrentAsid = 0;
1086	return rc;
1087	}
1088
1089
1090	/**
1091	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1092	* is to be called on the target CPUs.
1093	*
1094	* @param idCpu The identifier for the CPU the function is called on.
1095	* @param pvUser1 The 1st user argument.
1096	* @param pvUser2 Opaque pointer to the FirstRc.
1097	*/
1098	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1099	{
1100	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1101	AssertReturnVoid(g_HvmR0.fGlobalInit);
1102	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1103	}
1104
1105
1106	/**
1107	* Callback function invoked when a cpu goes online or offline.
1108	*
1109	* @param enmEvent The Mp event.
1110	* @param idCpu The identifier for the CPU the function is called on.
1111	* @param pvData Opaque data (PVM pointer).
1112	*/
1113	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1114	{
1115	NOREF(pvData);
1116
1117	/*
1118	* We only care about uninitializing a CPU that is going offline. When a
1119	* CPU comes online, the initialization is done lazily in HMR0Enter().
1120	*/
1121	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1122	switch (enmEvent)
1123	{
1124	case RTMPEVENT_OFFLINE:
1125	{
1126	int rc = hmR0DisableCpu(idCpu);
1127	AssertRC(rc);
1128	break;
1129	}
1130
1131	default:
1132	break;
1133	}
1134	}
1135
1136
1137	/**
1138	* Called whenever a system power state change occurs.
1139	*
1140	* @param enmEvent The Power event.
1141	* @param pvUser User argument.
1142	*/
1143	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1144	{
1145	NOREF(pvUser);
1146	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1147
1148	#ifdef LOG_ENABLED
1149	if (enmEvent == RTPOWEREVENT_SUSPEND)
1150	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1151	else
1152	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1153	#endif
1154
1155	if (enmEvent == RTPOWEREVENT_SUSPEND)
1156	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1157
1158	if (g_HvmR0.fEnabled)
1159	{
1160	int rc;
1161	HMR0FIRSTRC FirstRc;
1162	hmR0FirstRcInit(&FirstRc);
1163
1164	if (enmEvent == RTPOWEREVENT_SUSPEND)
1165	{
1166	if (g_HvmR0.fGlobalInit)
1167	{
1168	/* Turn off VT-x or AMD-V on all CPUs. */
1169	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1170	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1171	}
1172	/* else nothing to do here for the local init case */
1173	}
1174	else
1175	{
1176	/* Reinit the CPUs from scratch as the suspend state might have
1177	messed with the MSRs. (lousy BIOSes as usual) */
1178	if (g_HvmR0.vmx.fSupported)
1179	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1180	else
1181	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1182	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1183	if (RT_SUCCESS(rc))
1184	rc = hmR0FirstRcGetStatus(&FirstRc);
1185	#ifdef LOG_ENABLED
1186	if (RT_FAILURE(rc))
1187	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1188	#endif
1189	if (g_HvmR0.fGlobalInit)
1190	{
1191	/* Turn VT-x or AMD-V back on on all CPUs. */
1192	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1193	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1194	}
1195	/* else nothing to do here for the local init case */
1196	}
1197	}
1198
1199	if (enmEvent == RTPOWEREVENT_RESUME)
1200	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1201	}
1202
1203
1204	/**
1205	* Does Ring-0 per VM HM initialization.
1206	*
1207	* This will copy HM global into the VM structure and call the CPU specific
1208	* init routine which will allocate resources for each virtual CPU and such.
1209	*
1210	* @returns VBox status code.
1211	* @param pVM Pointer to the VM.
1212	*/
1213	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1214	{
1215	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1216
1217	#ifdef LOG_ENABLED
1218	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1219	#endif
1220
1221	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1222	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1223	return VERR_HM_SUSPEND_PENDING;
1224
1225	/*
1226	* Copy globals to the VM structure.
1227	*/
1228	/** @todo r=ramshankar: Why do we do this for MSRs? We never change them in the
1229	* per-VM structures anyway... */
1230	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1231	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1232
1233	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1234	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1235	pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4;
1236	pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer;
1237	pVM->hm.s.vmx.Msrs = g_HvmR0.vmx.Msrs;
1238	pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr;
1239	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1240	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1241	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1242	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1243	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1244
1245	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1246
1247
1248	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1249	{
1250	pVM->hm.s.cMaxResumeLoops = 1024;
1251	if (RTThreadPreemptIsPendingTrusty())
1252	pVM->hm.s.cMaxResumeLoops = 8192;
1253	}
1254
1255	/*
1256	* Initialize some per CPU fields.
1257	*/
1258	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1259	{
1260	PVMCPU pVCpu = &pVM->aCpus[i];
1261
1262	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1263
1264	/* Invalidate the last cpu we were running on. */
1265	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1266
1267	/* We'll aways increment this the first time (host uses ASID 0) */
1268	pVCpu->hm.s.uCurrentAsid = 0;
1269	}
1270
1271	/*
1272	* Call the hardware specific initialization method.
1273	*/
1274	RTCCUINTREG fFlags = ASMIntDisableFlags();
1275	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1276	ASMSetFlags(fFlags);
1277
1278	int rc = g_HvmR0.pfnInitVM(pVM);
1279	return rc;
1280	}
1281
1282
1283	/**
1284	* Does Ring-0 per VM HM termination.
1285	*
1286	* @returns VBox status code.
1287	* @param pVM Pointer to the VM.
1288	*/
1289	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1290	{
1291	Log(("HMR0TermVM: %p\n", pVM));
1292	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1293
1294	/* Make sure we don't touch HM after we've disabled HM in preparation
1295	of a suspend. */
1296	/** @todo r=bird: This cannot be right, the termination functions are
1297	* just freeing memory and resetting pVM/pVCpu members...
1298	* ==> memory leak. */
1299	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1300
1301	/*
1302	* Call the hardware specific method.
1303	*/
1304	RTCCUINTREG fFlags = ASMIntDisableFlags();
1305	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1306	ASMSetFlags(fFlags);
1307
1308	int rc = g_HvmR0.pfnTermVM(pVM);
1309	return rc;
1310	}
1311
1312
1313	/**
1314	* Sets up a VT-x or AMD-V session.
1315	*
1316	* This is mostly about setting up the hardware VM state.
1317	*
1318	* @returns VBox status code.
1319	* @param pVM Pointer to the VM.
1320	*/
1321	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1322	{
1323	Log(("HMR0SetupVM: %p\n", pVM));
1324	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1325
1326	/* Make sure we don't touch HM after we've disabled HM in
1327	preparation of a suspend. */
1328	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1329
1330	/*
1331	* Call the hardware specific setup VM method. This requires the CPU to be
1332	* enabled for AMD-V/VT-x and preemption to be prevented.
1333	*/
1334	RTCCUINTREG fFlags = ASMIntDisableFlags();
1335	RTCPUID idCpu = RTMpCpuId();
1336	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1337
1338	/* On first entry we'll sync everything. */
1339	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1340	pVM->aCpus[i].hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1341
1342	/* Enable VT-x or AMD-V if local init is required. */
1343	int rc;
1344	if (!g_HvmR0.fGlobalInit)
1345	{
1346	rc = hmR0EnableCpu(pVM, idCpu);
1347	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1348	}
1349
1350	/* Setup VT-x or AMD-V. */
1351	rc = g_HvmR0.pfnSetupVM(pVM);
1352
1353	/* Disable VT-x or AMD-V if local init was done before. */
1354	if (!g_HvmR0.fGlobalInit)
1355	{
1356	int rc2 = hmR0DisableCpu(idCpu);
1357	AssertRC(rc2);
1358	}
1359
1360	ASMSetFlags(fFlags);
1361	return rc;
1362	}
1363
1364
1365	/**
1366	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1367	* required for entering HM context.
1368	*
1369	* @returns VBox status code.
1370	* @param pvCpu Pointer to the VMCPU.
1371	*
1372	* @remarks No-long-jump zone!!!
1373	*/
1374	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1375	{
1376	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1377
1378	int rc = VINF_SUCCESS;
1379	RTCPUID idCpu = RTMpCpuId();
1380	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1381	AssertPtr(pCpu);
1382
1383	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1384	if (!pCpu->fConfigured)
1385	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1386
1387	/* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
1388	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE;
1389	pVCpu->hm.s.idEnteredCpu = idCpu;
1390	return rc;
1391	}
1392
1393
1394	/**
1395	* Enters the VT-x or AMD-V session.
1396	*
1397	* @returns VBox status code.
1398	* @param pVM Pointer to the VM.
1399	* @param pVCpu Pointer to the VMCPU.
1400	*
1401	* @remarks This is called with preemption disabled.
1402	*/
1403	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1404	{
1405	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1406	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1407	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1408
1409	/* Load the bare minimum state required for entering HM. */
1410	int rc = HMR0EnterCpu(pVCpu);
1411	AssertRCReturn(rc, rc);
1412
1413	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1414	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1415	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1416	#endif
1417
1418	RTCPUID idCpu = RTMpCpuId();
1419	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1420	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1421	Assert(pCpu);
1422	Assert(pCtx);
1423	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1424
1425	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1426	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1427
1428	/* Load the host as we may be resuming code after a longjmp and quite
1429	possibly now be scheduled on a different CPU. */
1430	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1431	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1432
1433	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1434	if (fStartedSet)
1435	PGMRZDynMapReleaseAutoSet(pVCpu);
1436	#endif
1437
1438	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1439	and ring-3 calls. */
1440	if (RT_FAILURE(rc))
1441	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1442	return rc;
1443	}
1444
1445
1446	/**
1447	* Deinitializes the bare minimum state used for HM context and if necessary
1448	* disable HM on the CPU.
1449	*
1450	* @returns VBox status code.
1451	* @param pVCpu Pointer to the VMCPU.
1452	*
1453	* @remarks No-long-jump zone!!!
1454	*/
1455	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1456	{
1457	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1458
1459	RTCPUID idCpu = RTMpCpuId();
1460	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1461
1462	if ( !g_HvmR0.fGlobalInit
1463	&& pCpu->fConfigured)
1464	{
1465	int rc = hmR0DisableCpu(idCpu);
1466	AssertRCReturn(rc, rc);
1467	Assert(!pCpu->fConfigured);
1468	}
1469
1470	/* Reset these to force a TLB flush for the next entry. */
1471	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1472	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1473	pVCpu->hm.s.uCurrentAsid = 0;
1474	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1475
1476	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1477	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1478
1479	return VINF_SUCCESS;
1480	}
1481
1482
1483	/**
1484	* Thread-context hook for HM.
1485	*
1486	* @param enmEvent The thread-context event.
1487	* @param pvUser Opaque pointer to the VMCPU.
1488	*/
1489	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1490	{
1491	PVMCPU pVCpu = (PVMCPU)pvUser;
1492	Assert(pVCpu);
1493	Assert(g_HvmR0.pfnThreadCtxCallback);
1494
1495	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1496	}
1497
1498
1499	/**
1500	* Runs guest code in a hardware accelerated VM.
1501	*
1502	* @returns VBox status code.
1503	* @param pVM Pointer to the VM.
1504	* @param pVCpu Pointer to the VMCPU.
1505	*
1506	* @remarks Called with preemption disabled and after first having called
1507	* HMR0Enter.
1508	*/
1509	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1510	{
1511	#ifdef VBOX_STRICT
1512	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1513	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1514	Assert(pCpu->fConfigured);
1515	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1516	#endif
1517
1518	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1519	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1520	PGMRZDynMapStartAutoSet(pVCpu);
1521	#endif
1522
1523	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1524
1525	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1526	PGMRZDynMapReleaseAutoSet(pVCpu);
1527	#endif
1528	return rc;
1529	}
1530
1531	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1532
1533	/**
1534	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1535	*
1536	* @returns VBox status code.
1537	* @param pVM Pointer to the VM.
1538	* @param pVCpu Pointer to the VMCPU.
1539	* @param pCtx Pointer to the guest CPU context.
1540	*/
1541	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1542	{
1543	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1544	if (pVM->hm.s.vmx.fSupported)
1545	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1546	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1547	}
1548
1549
1550	/**
1551	* Save guest debug state (64 bits guest mode & 32 bits host only)
1552	*
1553	* @returns VBox status code.
1554	* @param pVM Pointer to the VM.
1555	* @param pVCpu Pointer to the VMCPU.
1556	* @param pCtx Pointer to the guest CPU context.
1557	*/
1558	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1559	{
1560	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1561	if (pVM->hm.s.vmx.fSupported)
1562	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1563	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1564	}
1565
1566
1567	/**
1568	* Test the 32->64 bits switcher.
1569	*
1570	* @returns VBox status code.
1571	* @param pVM Pointer to the VM.
1572	*/
1573	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1574	{
1575	PVMCPU pVCpu = &pVM->aCpus[0];
1576	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1577	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1578	int rc;
1579
1580	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1581	if (pVM->hm.s.vmx.fSupported)
1582	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1583	else
1584	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1585	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1586
1587	return rc;
1588	}
1589
1590	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1591
1592	/**
1593	* Returns suspend status of the host.
1594	*
1595	* @returns Suspend pending or not.
1596	*/
1597	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1598	{
1599	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1600	}
1601
1602
1603	/**
1604	* Returns the cpu structure for the current cpu.
1605	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1606	*
1607	* @returns The cpu structure pointer.
1608	*/
1609	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1610	{
1611	RTCPUID idCpu = RTMpCpuId();
1612	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1613	return &g_HvmR0.aCpuInfo[idCpu];
1614	}
1615
1616
1617	/**
1618	* Returns the cpu structure for the current cpu.
1619	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1620	*
1621	* @returns The cpu structure pointer.
1622	* @param idCpu id of the VCPU.
1623	*/
1624	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1625	{
1626	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1627	return &g_HvmR0.aCpuInfo[idCpu];
1628	}
1629
1630
1631	/**
1632	* Save a pending IO read.
1633	*
1634	* @param pVCpu Pointer to the VMCPU.
1635	* @param GCPtrRip Address of IO instruction.
1636	* @param GCPtrRipNext Address of the next instruction.
1637	* @param uPort Port address.
1638	* @param uAndVal AND mask for saving the result in eax.
1639	* @param cbSize Read size.
1640	*/
1641	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1642	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1643	{
1644	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1645	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1646	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1647	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1648	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1649	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1650	return;
1651	}
1652
1653
1654	/**
1655	* Save a pending IO write.
1656	*
1657	* @param pVCpu Pointer to the VMCPU.
1658	* @param GCPtrRIP Address of IO instruction.
1659	* @param uPort Port address.
1660	* @param uAndVal AND mask for fetching the result from eax.
1661	* @param cbSize Read size.
1662	*/
1663	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1664	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1665	{
1666	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1667	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1668	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1669	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1670	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1671	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1672	return;
1673	}
1674
1675
1676	/**
1677	* Raw-mode switcher hook - disable VT-x if it's active and the current
1678	* switcher turns off paging.
1679	*
1680	* @returns VBox status code.
1681	* @param pVM Pointer to the VM.
1682	* @param enmSwitcher The switcher we're about to use.
1683	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1684	*/
1685	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1686	{
1687	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1688
1689	*pfVTxDisabled = false;
1690
1691	/* No such issues with AMD-V */
1692	if (!g_HvmR0.vmx.fSupported)
1693	return VINF_SUCCESS;
1694
1695	/* Check if the swithcing we're up to is safe. */
1696	switch (enmSwitcher)
1697	{
1698	case VMMSWITCHER_32_TO_32:
1699	case VMMSWITCHER_PAE_TO_PAE:
1700	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1701
1702	case VMMSWITCHER_32_TO_PAE:
1703	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1704	case VMMSWITCHER_AMD64_TO_32:
1705	case VMMSWITCHER_AMD64_TO_PAE:
1706	break; /* unsafe switchers */
1707
1708	default:
1709	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1710	}
1711
1712	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1713	regardless of whether we're currently using VT-x or not. */
1714	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1715	{
1716	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1717	return VINF_SUCCESS;
1718	}
1719
1720	/** @todo Check if this code is presumtive wrt other VT-x users on the
1721	* system... */
1722
1723	/* Nothing to do if we haven't enabled VT-x. */
1724	if (!g_HvmR0.fEnabled)
1725	return VINF_SUCCESS;
1726
1727	/* Local init implies the CPU is currently not in VMX root mode. */
1728	if (!g_HvmR0.fGlobalInit)
1729	return VINF_SUCCESS;
1730
1731	/* Ok, disable VT-x. */
1732	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1733	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1734
1735	*pfVTxDisabled = true;
1736	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1737	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1738	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1739	}
1740
1741
1742	/**
1743	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1744	* switcher turned off paging.
1745	*
1746	* @param pVM Pointer to the VM.
1747	* @param fVTxDisabled Whether VT-x was disabled or not.
1748	*/
1749	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1750	{
1751	Assert(!(ASMGetFlags() & X86_EFL_IF));
1752
1753	if (!fVTxDisabled)
1754	return; /* nothing to do */
1755
1756	Assert(g_HvmR0.vmx.fSupported);
1757	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1758	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1759	else
1760	{
1761	Assert(g_HvmR0.fEnabled);
1762	Assert(g_HvmR0.fGlobalInit);
1763
1764	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1765	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1766
1767	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1768	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1769	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
1770	}
1771	}
1772
1773	#ifdef VBOX_STRICT
1774
1775	/**
1776	* Dumps a descriptor.
1777	*
1778	* @param pDesc Descriptor to dump.
1779	* @param Sel Selector number.
1780	* @param pszMsg Message to prepend the log entry with.
1781	*/
1782	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1783	{
1784	/*
1785	* Make variable description string.
1786	*/
1787	static struct
1788	{
1789	unsigned cch;
1790	const char *psz;
1791	} const s_aTypes[32] =
1792	{
1793	# define STRENTRY(str) { sizeof(str) - 1, str }
1794
1795	/* system */
1796	# if HC_ARCH_BITS == 64
1797	STRENTRY("Reserved0 "), /* 0x00 */
1798	STRENTRY("Reserved1 "), /* 0x01 */
1799	STRENTRY("LDT "), /* 0x02 */
1800	STRENTRY("Reserved3 "), /* 0x03 */
1801	STRENTRY("Reserved4 "), /* 0x04 */
1802	STRENTRY("Reserved5 "), /* 0x05 */
1803	STRENTRY("Reserved6 "), /* 0x06 */
1804	STRENTRY("Reserved7 "), /* 0x07 */
1805	STRENTRY("Reserved8 "), /* 0x08 */
1806	STRENTRY("TSS64Avail "), /* 0x09 */
1807	STRENTRY("ReservedA "), /* 0x0a */
1808	STRENTRY("TSS64Busy "), /* 0x0b */
1809	STRENTRY("Call64 "), /* 0x0c */
1810	STRENTRY("ReservedD "), /* 0x0d */
1811	STRENTRY("Int64 "), /* 0x0e */
1812	STRENTRY("Trap64 "), /* 0x0f */
1813	# else
1814	STRENTRY("Reserved0 "), /* 0x00 */
1815	STRENTRY("TSS16Avail "), /* 0x01 */
1816	STRENTRY("LDT "), /* 0x02 */
1817	STRENTRY("TSS16Busy "), /* 0x03 */
1818	STRENTRY("Call16 "), /* 0x04 */
1819	STRENTRY("Task "), /* 0x05 */
1820	STRENTRY("Int16 "), /* 0x06 */
1821	STRENTRY("Trap16 "), /* 0x07 */
1822	STRENTRY("Reserved8 "), /* 0x08 */
1823	STRENTRY("TSS32Avail "), /* 0x09 */
1824	STRENTRY("ReservedA "), /* 0x0a */
1825	STRENTRY("TSS32Busy "), /* 0x0b */
1826	STRENTRY("Call32 "), /* 0x0c */
1827	STRENTRY("ReservedD "), /* 0x0d */
1828	STRENTRY("Int32 "), /* 0x0e */
1829	STRENTRY("Trap32 "), /* 0x0f */
1830	# endif
1831	/* non system */
1832	STRENTRY("DataRO "), /* 0x10 */
1833	STRENTRY("DataRO Accessed "), /* 0x11 */
1834	STRENTRY("DataRW "), /* 0x12 */
1835	STRENTRY("DataRW Accessed "), /* 0x13 */
1836	STRENTRY("DataDownRO "), /* 0x14 */
1837	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1838	STRENTRY("DataDownRW "), /* 0x16 */
1839	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1840	STRENTRY("CodeEO "), /* 0x18 */
1841	STRENTRY("CodeEO Accessed "), /* 0x19 */
1842	STRENTRY("CodeER "), /* 0x1a */
1843	STRENTRY("CodeER Accessed "), /* 0x1b */
1844	STRENTRY("CodeConfEO "), /* 0x1c */
1845	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1846	STRENTRY("CodeConfER "), /* 0x1e */
1847	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1848	# undef SYSENTRY
1849	};
1850	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1851	char szMsg[128];
1852	char *psz = &szMsg[0];
1853	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1854	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1855	psz += s_aTypes[i].cch;
1856
1857	if (pDesc->Gen.u1Present)
1858	ADD_STR(psz, "Present ");
1859	else
1860	ADD_STR(psz, "Not-Present ");
1861	# if HC_ARCH_BITS == 64
1862	if (pDesc->Gen.u1Long)
1863	ADD_STR(psz, "64-bit ");
1864	else
1865	ADD_STR(psz, "Comp ");
1866	# else
1867	if (pDesc->Gen.u1Granularity)
1868	ADD_STR(psz, "Page ");
1869	if (pDesc->Gen.u1DefBig)
1870	ADD_STR(psz, "32-bit ");
1871	else
1872	ADD_STR(psz, "16-bit ");
1873	# endif
1874	# undef ADD_STR
1875	*psz = '\0';
1876
1877	/*
1878	* Limit and Base and format the output.
1879	*/
1880	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1881
1882	# if HC_ARCH_BITS == 64
1883	uint64_t u32Base = X86DESC64_BASE(pDesc);
1884
1885	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1886	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1887	# else
1888	uint32_t u32Base = X86DESC_BASE(pDesc);
1889
1890	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1891	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1892	# endif
1893	}
1894
1895
1896	/**
1897	* Formats a full register dump.
1898	*
1899	* @param pVM Pointer to the VM.
1900	* @param pVCpu Pointer to the VMCPU.
1901	* @param pCtx Pointer to the CPU context.
1902	*/
1903	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1904	{
1905	NOREF(pVM);
1906
1907	/*
1908	* Format the flags.
1909	*/
1910	static struct
1911	{
1912	const char pszSet; const char pszClear; uint32_t fFlag;
1913	} const s_aFlags[] =
1914	{
1915	{ "vip",NULL, X86_EFL_VIP },
1916	{ "vif",NULL, X86_EFL_VIF },
1917	{ "ac", NULL, X86_EFL_AC },
1918	{ "vm", NULL, X86_EFL_VM },
1919	{ "rf", NULL, X86_EFL_RF },
1920	{ "nt", NULL, X86_EFL_NT },
1921	{ "ov", "nv", X86_EFL_OF },
1922	{ "dn", "up", X86_EFL_DF },
1923	{ "ei", "di", X86_EFL_IF },
1924	{ "tf", NULL, X86_EFL_TF },
1925	{ "nt", "pl", X86_EFL_SF },
1926	{ "nz", "zr", X86_EFL_ZF },
1927	{ "ac", "na", X86_EFL_AF },
1928	{ "po", "pe", X86_EFL_PF },
1929	{ "cy", "nc", X86_EFL_CF },
1930	};
1931	char szEFlags[80];
1932	char *psz = szEFlags;
1933	uint32_t efl = pCtx->eflags.u32;
1934	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1935	{
1936	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1937	if (pszAdd)
1938	{
1939	strcpy(psz, pszAdd);
1940	psz += strlen(pszAdd);
1941	*psz++ = ' ';
1942	}
1943	}
1944	psz[-1] = '\0';
1945
1946
1947	/*
1948	* Format the registers.
1949	*/
1950	if (CPUMIsGuestIn64BitCode(pVCpu))
1951	{
1952	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1953	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1954	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1955	"r14=%016RX64 r15=%016RX64\n"
1956	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1957	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1958	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1959	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1960	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1961	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1962	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1963	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1964	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1965	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1966	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1967	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1968	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1969	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1970	,
1971	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1972	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1973	pCtx->r14, pCtx->r15,
1974	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1975	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1976	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1977	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1978	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1979	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1980	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1981	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1982	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1983	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1984	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1985	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1986	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1987	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1988	}
1989	else
1990	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1991	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1992	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1993	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1994	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1995	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1996	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1997	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1998	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1999	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2000	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2001	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2002	,
2003	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2004	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2005	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2006	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2007	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2008	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2009	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2010	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2011	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2012	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2013	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2014	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2015
2016	Log(("FPU:\n"
2017	"FCW=%04x FSW=%04x FTW=%02x\n"
2018	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2019	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2020	,
2021	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2022	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2023	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2024	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2025
2026
2027	Log(("MSR:\n"
2028	"EFER =%016RX64\n"
2029	"PAT =%016RX64\n"
2030	"STAR =%016RX64\n"
2031	"CSTAR =%016RX64\n"
2032	"LSTAR =%016RX64\n"
2033	"SFMASK =%016RX64\n"
2034	"KERNELGSBASE =%016RX64\n",
2035	pCtx->msrEFER,
2036	pCtx->msrPAT,
2037	pCtx->msrSTAR,
2038	pCtx->msrCSTAR,
2039	pCtx->msrLSTAR,
2040	pCtx->msrSFMASK,
2041	pCtx->msrKERNELGSBASE));
2042
2043	}
2044
2045	#endif /* VBOX_STRICT */
2046

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 48217

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