HMR0.cpp@ 48227

Last change on this file since 48227 was 48218, checked in by vboxsync, 11 years ago
VMM: Addressed a rare corner case stale TLB entry issue.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 72.3 KB

Line
1	/* $Id: HMR0.cpp 48218 2013-09-01 16:31:26Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost, void *pvArg));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	/** @todo This isn't used for anything relevant. Remove later? */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** VMX MSR values */
123	VMXMSRS Msrs;
124
125	/* Last instruction error */
126	uint32_t ulLastInstrError;
127	} vmx;
128
129	/** AMD-V information. */
130	struct
131	{
132	/* HWCR MSR (for diagnostics) */
133	uint64_t u64MsrHwcr;
134
135	/** SVM revision. */
136	uint32_t u32Rev;
137
138	/** SVM feature bits from cpuid 0x8000000a */
139	uint32_t u32Features;
140
141	/** Set by us to indicate SVM is supported by the CPU. */
142	bool fSupported;
143	} svm;
144	/** Saved error from detection */
145	int32_t lLastError;
146
147	struct
148	{
149	uint32_t u32AMDFeatureECX;
150	uint32_t u32AMDFeatureEDX;
151	} cpuid;
152
153	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
154	* enabled and disabled each time it's used to execute guest code. */
155	bool fGlobalInit;
156	/** Indicates whether the host is suspending or not. We'll refuse a few
157	* actions when the host is being suspended to speed up the suspending and
158	* avoid trouble. */
159	volatile bool fSuspended;
160
161	/** Whether we've already initialized all CPUs.
162	* @remarks We could check the EnableAllCpusOnce state, but this is
163	* simpler and hopefully easier to understand. */
164	bool fEnabled;
165	/** Serialize initialization in HMR0EnableAllCpus. */
166	RTONCE EnableAllCpusOnce;
167	} g_HvmR0;
168
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	/**
212	* Get the CPU ID on which the failure status code was reported.
213	*
214	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
215	* @param pFirstRc The first return code structure.
216	*/
217	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
218	{
219	return pFirstRc->idCpu;
220	}
221	#endif /* VBOX_STRICT */
222
223
224	/** @name Dummy callback handlers.
225	* @{ */
226
227	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
228	{
229	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
234	{
235	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
236	return VINF_SUCCESS;
237	}
238
239	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
240	{
241	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
242	}
243
244	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
245	bool fEnabledBySystem, void *pvArg)
246	{
247	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
252	{
253	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
254	return VINF_SUCCESS;
255	}
256
257	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
258	{
259	NOREF(pVM);
260	return VINF_SUCCESS;
261	}
262
263	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
264	{
265	NOREF(pVM);
266	return VINF_SUCCESS;
267	}
268
269	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
270	{
271	NOREF(pVM);
272	return VINF_SUCCESS;
273	}
274
275	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
276	{
277	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
278	return VINF_SUCCESS;
279	}
280
281	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
282	{
283	NOREF(pVM); NOREF(pVCpu);
284	return VINF_SUCCESS;
285	}
286
287	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
288	{
289	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
290	return VINF_SUCCESS;
291	}
292
293	/** @} */
294
295
296	/**
297	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
298	* Down at the Rate Specified" erratum.
299	*
300	* Errata names and related steppings:
301	* - BA86 - D0.
302	* - AAX65 - C2.
303	* - AAU65 - C2, K0.
304	* - AAO95 - B1.
305	* - AAT59 - C2.
306	* - AAK139 - D0.
307	* - AAM126 - C0, C1, D0.
308	* - AAN92 - B1.
309	* - AAJ124 - C0, D0.
310	*
311	* - AAP86 - B1.
312	*
313	* Steppings: B1, C0, C1, C2, D0, K0.
314	*
315	* @returns true if subject to it, false if not.
316	*/
317	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
318	{
319	uint32_t u = ASMCpuId_EAX(1);
320	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
321	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
322	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
323	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
324	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
325	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
326	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
327	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
328	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
329	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
330	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
331	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
332	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
333	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
334	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
335	)
336	return true;
337	return false;
338	}
339
340
341	/**
342	* Intel specific initialization code.
343	*
344	* @returns VBox status code (will only fail if out of memory).
345	*/
346	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
347	{
348	/*
349	* Check that all the required VT-x features are present.
350	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
351	*/
352	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
353	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
354	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
355	)
356	{
357	/** @todo move this into a separate function. */
358	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
359
360	/*
361	* First try use native kernel API for controlling VT-x.
362	* (This is only supported by some Mac OS X kernels atm.)
363	*/
364	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
365	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
366	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
367	{
368	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
369	if (RT_SUCCESS(rc))
370	{
371	g_HvmR0.vmx.fSupported = true;
372	rc = SUPR0EnableVTx(false /* fEnable */);
373	AssertLogRelRC(rc);
374	}
375	}
376	else
377	{
378	/* We need to check if VT-x has been properly initialized on all
379	CPUs. Some BIOSes do a lousy job. */
380	HMR0FIRSTRC FirstRc;
381	hmR0FirstRcInit(&FirstRc);
382	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
383	if (RT_SUCCESS(g_HvmR0.lLastError))
384	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
385	}
386	if (RT_SUCCESS(g_HvmR0.lLastError))
387	{
388	/* Reread in case we've changed it. */
389	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
390
391	if ( (g_HvmR0.vmx.Msrs.u64FeatureCtrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
392	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
393	{
394	/*
395	* Read all relevant registers and MSRs.
396	*/
397	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
398	g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
399	g_HvmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
400	g_HvmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
401	g_HvmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
402	g_HvmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
403	g_HvmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
404	g_HvmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
405	g_HvmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
406	g_HvmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
407	g_HvmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
408	g_HvmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
409	g_HvmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
410	/* VPID 16 bits ASID. */
411	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
412
413	if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
414	{
415	g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
416	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
417	g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
418
419	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
420	g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
421	}
422
423	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
424	{
425	/*
426	* Enter root mode
427	*/
428	RTR0MEMOBJ hScatchMemObj;
429	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
430	if (RT_FAILURE(rc))
431	{
432	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
433	return rc;
434	}
435
436	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
437	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
438	ASMMemZeroPage(pvScatchPage);
439
440	/* Set revision dword at the beginning of the structure. */
441	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo);
442
443	/* Make sure we don't get rescheduled to another cpu during this probe. */
444	RTCCUINTREG fFlags = ASMIntDisableFlags();
445
446	/*
447	* Check CR4.VMXE
448	*/
449	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
450	if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
451	{
452	/* In theory this bit could be cleared behind our back. Which would cause
453	#UD faults when we try to execute the VMX instructions... */
454	ASMSetCR4(g_HvmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
455	}
456
457	/*
458	* The only way of checking if we're in VMX root mode or not is to try and enter it.
459	* There is no instruction or control bit that tells us if we're in VMX root mode.
460	* Therefore, try and enter VMX root mode here.
461	*/
462	rc = VMXEnable(HCPhysScratchPage);
463	if (RT_SUCCESS(rc))
464	{
465	g_HvmR0.vmx.fSupported = true;
466	VMXDisable();
467	}
468	else
469	{
470	/*
471	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
472	* it will crash the host when we enter raw mode, because:
473	*
474	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
475	* this bit), and
476	* (b) turning off paging causes a #GP (unavoidable when switching
477	* from long to 32 bits mode or 32 bits to PAE).
478	*
479	* They should fix their code, but until they do we simply refuse to run.
480	*/
481	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
482	}
483
484	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
485	if it wasn't so before (some software could incorrectly
486	think it's in VMX mode). */
487	ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
488	ASMSetFlags(fFlags);
489
490	RTR0MemObjFree(hScatchMemObj, false);
491	}
492	}
493	else
494	{
495	AssertFailed(); /* can't hit this case anymore */
496	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
497	}
498
499	if (g_HvmR0.vmx.fSupported)
500	{
501	/* Call the global VT-x initialization routine. */
502	rc = VMXR0GlobalInit();
503	if (RT_FAILURE(rc))
504	g_HvmR0.lLastError = rc;
505
506	/*
507	* Install the VT-x methods.
508	*/
509	g_HvmR0.pfnEnterSession = VMXR0Enter;
510	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
511	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
512	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
513	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
514	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
515	g_HvmR0.pfnInitVM = VMXR0InitVM;
516	g_HvmR0.pfnTermVM = VMXR0TermVM;
517	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
518
519	/*
520	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
521	* Timer Does Not Count Down at the Rate Specified" erratum.
522	*/
523	if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
524	{
525	g_HvmR0.vmx.fUsePreemptTimer = true;
526	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc);
527	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
528	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
529	}
530	}
531	}
532	#ifdef LOG_ENABLED
533	else
534	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
535	#endif
536	}
537	else
538	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
539	return VINF_SUCCESS;
540	}
541
542
543	/**
544	* AMD-specific initialization code.
545	*
546	* @returns VBox status code.
547	*/
548	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
549	{
550	/*
551	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
552	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
553	*/
554	int rc;
555	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
556	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
557	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
558	&& ASMIsValidExtRange(uMaxExtLeaf)
559	&& uMaxExtLeaf >= 0x8000000a
560	)
561	{
562	/* Call the global AMD-V initialization routine. */
563	rc = SVMR0GlobalInit();
564	if (RT_FAILURE(rc))
565	{
566	g_HvmR0.lLastError = rc;
567	return rc;
568	}
569
570	/*
571	* Install the AMD-V methods.
572	*/
573	g_HvmR0.pfnEnterSession = SVMR0Enter;
574	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
575	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
576	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
577	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
578	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
579	g_HvmR0.pfnInitVM = SVMR0InitVM;
580	g_HvmR0.pfnTermVM = SVMR0TermVM;
581	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
582
583	/* Query AMD features. */
584	uint32_t u32Dummy;
585	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
586
587	/*
588	* We need to check if AMD-V has been properly initialized on all CPUs.
589	* Some BIOSes might do a poor job.
590	*/
591	HMR0FIRSTRC FirstRc;
592	hmR0FirstRcInit(&FirstRc);
593	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
594	AssertRC(rc);
595	if (RT_SUCCESS(rc))
596	rc = hmR0FirstRcGetStatus(&FirstRc);
597	#ifndef DEBUG_bird
598	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
599	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
600	#endif
601	if (RT_SUCCESS(rc))
602	{
603	/* Read the HWCR MSR for diagnostics. */
604	g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
605	g_HvmR0.svm.fSupported = true;
606	}
607	else
608	g_HvmR0.lLastError = rc;
609	}
610	else
611	{
612	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
613	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
614	}
615	return rc;
616	}
617
618
619	/**
620	* Does global Ring-0 HM initialization (at module init).
621	*
622	* @returns VBox status code.
623	*/
624	VMMR0_INT_DECL(int) HMR0Init(void)
625	{
626	/*
627	* Initialize the globals.
628	*/
629	g_HvmR0.fEnabled = false;
630	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
631	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
632	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
633	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
634
635	/* Fill in all callbacks with placeholders. */
636	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
637	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
638	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
639	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
640	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
641	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
642	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
643	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
644	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
645
646	/* Default is global VT-x/AMD-V init. */
647	g_HvmR0.fGlobalInit = true;
648
649	/*
650	* Make sure aCpuInfo is big enough for all the CPUs on this system.
651	*/
652	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
653	{
654	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
655	return VERR_TOO_MANY_CPUS;
656	}
657
658	/*
659	* Check for VT-x and AMD-V capabilities.
660	*/
661	int rc;
662	if (ASMHasCpuId())
663	{
664	/* Standard features. */
665	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
666	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
667	if (ASMIsValidStdRange(uMaxLeaf))
668	{
669	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
670	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
671
672	/* Query AMD features. */
673	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
674	if (ASMIsValidExtRange(uMaxExtLeaf))
675	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
676	&g_HvmR0.cpuid.u32AMDFeatureECX,
677	&g_HvmR0.cpuid.u32AMDFeatureEDX);
678	else
679	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
680
681	/* Go to CPU specific initialization code. */
682	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
683	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
684	{
685	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
686	if (RT_FAILURE(rc))
687	return rc;
688	}
689	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
690	{
691	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
692	if (RT_FAILURE(rc))
693	return rc;
694	}
695	else
696	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
697	}
698	else
699	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
700	}
701	else
702	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
703
704	/*
705	* Register notification callbacks that we can use to disable/enable CPUs
706	* when brought offline/online or suspending/resuming.
707	*/
708	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
709	{
710	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
711	AssertRC(rc);
712
713	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
714	AssertRC(rc);
715	}
716
717	/* We return success here because module init shall not fail if HM
718	fails to initialize. */
719	return VINF_SUCCESS;
720	}
721
722
723	/**
724	* Does global Ring-0 HM termination (at module termination).
725	*
726	* @returns VBox status code.
727	*/
728	VMMR0_INT_DECL(int) HMR0Term(void)
729	{
730	int rc;
731	if ( g_HvmR0.vmx.fSupported
732	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
733	{
734	/*
735	* Simple if the host OS manages VT-x.
736	*/
737	Assert(g_HvmR0.fGlobalInit);
738	rc = SUPR0EnableVTx(false /* fEnable */);
739
740	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
741	{
742	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
743	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
744	}
745	}
746	else
747	{
748	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
749	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
750	{
751	/* Doesn't really matter if this fails. */
752	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
753	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
754	}
755	else
756	rc = VINF_SUCCESS;
757
758	/*
759	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
760	*/
761	if (g_HvmR0.fGlobalInit)
762	{
763	HMR0FIRSTRC FirstRc;
764	hmR0FirstRcInit(&FirstRc);
765	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
766	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
767	if (RT_SUCCESS(rc))
768	{
769	rc = hmR0FirstRcGetStatus(&FirstRc);
770	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
771	}
772	}
773
774	/*
775	* Free the per-cpu pages used for VT-x and AMD-V.
776	*/
777	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
778	{
779	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
780	{
781	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
782	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
783	}
784	}
785	}
786
787	/** @todo This needs cleaning up. There's no matching
788	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
789	* should move into their respective modules. */
790	/* Finally, call global VT-x/AMD-V termination. */
791	if (g_HvmR0.vmx.fSupported)
792	VMXR0GlobalTerm();
793	else if (g_HvmR0.svm.fSupported)
794	SVMR0GlobalTerm();
795
796	return rc;
797	}
798
799
800	/**
801	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
802	* VT-x on a CPU.
803	*
804	* @param idCpu The identifier for the CPU the function is called on.
805	* @param pvUser1 Pointer to the first RC structure.
806	* @param pvUser2 Ignored.
807	*/
808	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
809	{
810	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
811	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
812	NOREF(pvUser2);
813
814	/*
815	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
816	* Once the lock bit is set, this MSR can no longer be modified.
817	*/
818	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
819	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
820	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
821	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
822	)
823	{
824	/* MSR is not yet locked; we can change it ourselves here. */
825	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
826	g_HvmR0.vmx.Msrs.u64FeatureCtrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
827	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
828	}
829
830	int rc;
831	if ((fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
832	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
833	{
834	rc = VINF_SUCCESS;
835	}
836	else
837	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
838
839	hmR0FirstRcSetStatus(pFirstRc, rc);
840	}
841
842
843	/**
844	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
845	* on a CPU.
846	*
847	* @param idCpu The identifier for the CPU the function is called on.
848	* @param pvUser1 Pointer to the first RC structure.
849	* @param pvUser2 Ignored.
850	*/
851	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
852	{
853	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
854	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
855	NOREF(pvUser2);
856
857	/* Check if SVM is disabled. */
858	int rc;
859	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
860	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
861	{
862	/* Turn on SVM in the EFER MSR. */
863	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
864	if (fEfer & MSR_K6_EFER_SVME)
865	rc = VERR_SVM_IN_USE;
866	else
867	{
868	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
869
870	/* Paranoia. */
871	fEfer = ASMRdMsr(MSR_K6_EFER);
872	if (fEfer & MSR_K6_EFER_SVME)
873	{
874	/* Restore previous value. */
875	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
876	rc = VINF_SUCCESS;
877	}
878	else
879	rc = VERR_SVM_ILLEGAL_EFER_MSR;
880	}
881	}
882	else
883	rc = VERR_SVM_DISABLED;
884
885	hmR0FirstRcSetStatus(pFirstRc, rc);
886	}
887
888
889	/**
890	* Enable VT-x or AMD-V on the current CPU
891	*
892	* @returns VBox status code.
893	* @param pVM Pointer to the VM (can be NULL).
894	* @param idCpu The identifier for the CPU the function is called on.
895	*/
896	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
897	{
898	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
899
900	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
901	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
902	Assert(!pCpu->fConfigured);
903
904	pCpu->idCpu = idCpu;
905	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
906	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
907
908	int rc;
909	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
910	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HvmR0.vmx.Msrs);
911	else
912	{
913	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
914	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
915	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
916
917	if (g_HvmR0.vmx.fSupported)
918	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
919	else
920	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
921	}
922	AssertRC(rc);
923	if (RT_SUCCESS(rc))
924	pCpu->fConfigured = true;
925
926	return rc;
927	}
928
929
930	/**
931	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
932	* is to be called on the target cpus.
933	*
934	* @param idCpu The identifier for the CPU the function is called on.
935	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
936	* @param pvUser2 The 2nd user argument.
937	*/
938	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
939	{
940	PVM pVM = (PVM)pvUser1; /* can be NULL! */
941	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
942	AssertReturnVoid(g_HvmR0.fGlobalInit);
943	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
944	}
945
946
947	/**
948	* RTOnce callback employed by HMR0EnableAllCpus.
949	*
950	* @returns VBox status code.
951	* @param pvUser Pointer to the VM.
952	* @param pvUserIgnore NULL, ignored.
953	*/
954	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
955	{
956	PVM pVM = (PVM)pvUser;
957
958	/*
959	* Indicate that we've initialized.
960	*
961	* Note! There is a potential race between this function and the suspend
962	* notification. Kind of unlikely though, so ignored for now.
963	*/
964	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
965	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
966
967	/*
968	* The global init variable is set by the first VM.
969	*/
970	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
971
972	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
973	{
974	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
975	g_HvmR0.aCpuInfo[i].fConfigured = false;
976	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
977	g_HvmR0.aCpuInfo[i].uCurrentAsid = 0;
978	}
979
980	int rc;
981	if ( g_HvmR0.vmx.fSupported
982	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
983	{
984	/*
985	* Global VT-x initialization API (only darwin for now).
986	*/
987	rc = SUPR0EnableVTx(true /* fEnable */);
988	if (RT_SUCCESS(rc))
989	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
990	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
991	else
992	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
993	}
994	else
995	{
996	/*
997	* We're doing the job ourselves.
998	*/
999	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
1000	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1001	{
1002	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1003
1004	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1005	{
1006	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1007	AssertLogRelRCReturn(rc, rc);
1008
1009	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1010	ASMMemZeroPage(pvR0);
1011	}
1012	}
1013
1014	rc = VINF_SUCCESS;
1015	}
1016
1017	if ( RT_SUCCESS(rc)
1018	&& g_HvmR0.fGlobalInit)
1019	{
1020	/* First time, so initialize each cpu/core. */
1021	HMR0FIRSTRC FirstRc;
1022	hmR0FirstRcInit(&FirstRc);
1023	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1024	if (RT_SUCCESS(rc))
1025	rc = hmR0FirstRcGetStatus(&FirstRc);
1026	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1027	}
1028
1029	return rc;
1030	}
1031
1032
1033	/**
1034	* Sets up HM on all cpus.
1035	*
1036	* @returns VBox status code.
1037	* @param pVM Pointer to the VM.
1038	*/
1039	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1040	{
1041	/* Make sure we don't touch HM after we've disabled HM in
1042	preparation of a suspend. */
1043	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1044	return VERR_HM_SUSPEND_PENDING;
1045
1046	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1047	}
1048
1049
1050	/**
1051	* Disable VT-x or AMD-V on the current CPU.
1052	*
1053	* @returns VBox status code.
1054	* @param idCpu The identifier for the CPU the function is called on.
1055	*/
1056	static int hmR0DisableCpu(RTCPUID idCpu)
1057	{
1058	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1059
1060	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1061	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1062	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1063	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1064
1065	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1066	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1067
1068	int rc;
1069	if (pCpu->fConfigured)
1070	{
1071	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1072	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1073	if (idCpu == RTMpCpuId())
1074	{
1075	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1076	AssertRC(rc);
1077	}
1078	else
1079	{
1080	pCpu->fIgnoreAMDVInUseError = true;
1081	rc = VINF_SUCCESS;
1082	}
1083
1084	pCpu->fConfigured = false;
1085	}
1086	else
1087	rc = VINF_SUCCESS; /* nothing to do */
1088
1089	pCpu->uCurrentAsid = 0;
1090	return rc;
1091	}
1092
1093
1094	/**
1095	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1096	* is to be called on the target CPUs.
1097	*
1098	* @param idCpu The identifier for the CPU the function is called on.
1099	* @param pvUser1 The 1st user argument.
1100	* @param pvUser2 Opaque pointer to the FirstRc.
1101	*/
1102	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1103	{
1104	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1105	AssertReturnVoid(g_HvmR0.fGlobalInit);
1106	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1107	}
1108
1109
1110	/**
1111	* Callback function invoked when a cpu goes online or offline.
1112	*
1113	* @param enmEvent The Mp event.
1114	* @param idCpu The identifier for the CPU the function is called on.
1115	* @param pvData Opaque data (PVM pointer).
1116	*/
1117	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1118	{
1119	NOREF(pvData);
1120
1121	/*
1122	* We only care about uninitializing a CPU that is going offline. When a
1123	* CPU comes online, the initialization is done lazily in HMR0Enter().
1124	*/
1125	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1126	switch (enmEvent)
1127	{
1128	case RTMPEVENT_OFFLINE:
1129	{
1130	int rc = hmR0DisableCpu(idCpu);
1131	AssertRC(rc);
1132	break;
1133	}
1134
1135	default:
1136	break;
1137	}
1138	}
1139
1140
1141	/**
1142	* Called whenever a system power state change occurs.
1143	*
1144	* @param enmEvent The Power event.
1145	* @param pvUser User argument.
1146	*/
1147	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1148	{
1149	NOREF(pvUser);
1150	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1151
1152	#ifdef LOG_ENABLED
1153	if (enmEvent == RTPOWEREVENT_SUSPEND)
1154	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1155	else
1156	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1157	#endif
1158
1159	if (enmEvent == RTPOWEREVENT_SUSPEND)
1160	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1161
1162	if (g_HvmR0.fEnabled)
1163	{
1164	int rc;
1165	HMR0FIRSTRC FirstRc;
1166	hmR0FirstRcInit(&FirstRc);
1167
1168	if (enmEvent == RTPOWEREVENT_SUSPEND)
1169	{
1170	if (g_HvmR0.fGlobalInit)
1171	{
1172	/* Turn off VT-x or AMD-V on all CPUs. */
1173	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1174	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1175	}
1176	/* else nothing to do here for the local init case */
1177	}
1178	else
1179	{
1180	/* Reinit the CPUs from scratch as the suspend state might have
1181	messed with the MSRs. (lousy BIOSes as usual) */
1182	if (g_HvmR0.vmx.fSupported)
1183	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1184	else
1185	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1186	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1187	if (RT_SUCCESS(rc))
1188	rc = hmR0FirstRcGetStatus(&FirstRc);
1189	#ifdef LOG_ENABLED
1190	if (RT_FAILURE(rc))
1191	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1192	#endif
1193	if (g_HvmR0.fGlobalInit)
1194	{
1195	/* Turn VT-x or AMD-V back on on all CPUs. */
1196	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1197	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1198	}
1199	/* else nothing to do here for the local init case */
1200	}
1201	}
1202
1203	if (enmEvent == RTPOWEREVENT_RESUME)
1204	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1205	}
1206
1207
1208	/**
1209	* Does Ring-0 per VM HM initialization.
1210	*
1211	* This will copy HM global into the VM structure and call the CPU specific
1212	* init routine which will allocate resources for each virtual CPU and such.
1213	*
1214	* @returns VBox status code.
1215	* @param pVM Pointer to the VM.
1216	*/
1217	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1218	{
1219	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1220
1221	#ifdef LOG_ENABLED
1222	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1223	#endif
1224
1225	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1226	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1227	return VERR_HM_SUSPEND_PENDING;
1228
1229	/*
1230	* Copy globals to the VM structure.
1231	*/
1232	/** @todo r=ramshankar: Why do we do this for MSRs? We never change them in the
1233	* per-VM structures anyway... */
1234	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1235	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1236
1237	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1238	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1239	pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4;
1240	pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer;
1241	pVM->hm.s.vmx.Msrs = g_HvmR0.vmx.Msrs;
1242	pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr;
1243	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1244	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1245	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1246	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1247	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1248
1249	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1250
1251
1252	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1253	{
1254	pVM->hm.s.cMaxResumeLoops = 1024;
1255	if (RTThreadPreemptIsPendingTrusty())
1256	pVM->hm.s.cMaxResumeLoops = 8192;
1257	}
1258
1259	/*
1260	* Initialize some per CPU fields.
1261	*/
1262	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1263	{
1264	PVMCPU pVCpu = &pVM->aCpus[i];
1265
1266	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1267
1268	/* Invalidate the last cpu we were running on. */
1269	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1270
1271	/* We'll aways increment this the first time (host uses ASID 0) */
1272	pVCpu->hm.s.uCurrentAsid = 0;
1273	}
1274
1275	/*
1276	* Call the hardware specific initialization method.
1277	*/
1278	RTCCUINTREG fFlags = ASMIntDisableFlags();
1279	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1280	ASMSetFlags(fFlags);
1281
1282	int rc = g_HvmR0.pfnInitVM(pVM);
1283	return rc;
1284	}
1285
1286
1287	/**
1288	* Does Ring-0 per VM HM termination.
1289	*
1290	* @returns VBox status code.
1291	* @param pVM Pointer to the VM.
1292	*/
1293	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1294	{
1295	Log(("HMR0TermVM: %p\n", pVM));
1296	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1297
1298	/* Make sure we don't touch HM after we've disabled HM in preparation
1299	of a suspend. */
1300	/** @todo r=bird: This cannot be right, the termination functions are
1301	* just freeing memory and resetting pVM/pVCpu members...
1302	* ==> memory leak. */
1303	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1304
1305	/*
1306	* Call the hardware specific method.
1307	*/
1308	RTCCUINTREG fFlags = ASMIntDisableFlags();
1309	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1310	ASMSetFlags(fFlags);
1311
1312	int rc = g_HvmR0.pfnTermVM(pVM);
1313	return rc;
1314	}
1315
1316
1317	/**
1318	* Sets up a VT-x or AMD-V session.
1319	*
1320	* This is mostly about setting up the hardware VM state.
1321	*
1322	* @returns VBox status code.
1323	* @param pVM Pointer to the VM.
1324	*/
1325	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1326	{
1327	Log(("HMR0SetupVM: %p\n", pVM));
1328	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1329
1330	/* Make sure we don't touch HM after we've disabled HM in
1331	preparation of a suspend. */
1332	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1333
1334	/*
1335	* Call the hardware specific setup VM method. This requires the CPU to be
1336	* enabled for AMD-V/VT-x and preemption to be prevented.
1337	*/
1338	RTCCUINTREG fFlags = ASMIntDisableFlags();
1339	RTCPUID idCpu = RTMpCpuId();
1340	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1341
1342	/* On first entry we'll sync everything. */
1343	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1344	pVM->aCpus[i].hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1345
1346	/* Enable VT-x or AMD-V if local init is required. */
1347	int rc;
1348	if (!g_HvmR0.fGlobalInit)
1349	{
1350	rc = hmR0EnableCpu(pVM, idCpu);
1351	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1352	}
1353
1354	/* Setup VT-x or AMD-V. */
1355	rc = g_HvmR0.pfnSetupVM(pVM);
1356
1357	/* Disable VT-x or AMD-V if local init was done before. */
1358	if (!g_HvmR0.fGlobalInit)
1359	{
1360	int rc2 = hmR0DisableCpu(idCpu);
1361	AssertRC(rc2);
1362	}
1363
1364	ASMSetFlags(fFlags);
1365	return rc;
1366	}
1367
1368
1369	/**
1370	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1371	* required for entering HM context.
1372	*
1373	* @returns VBox status code.
1374	* @param pvCpu Pointer to the VMCPU.
1375	*
1376	* @remarks No-long-jump zone!!!
1377	*/
1378	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1379	{
1380	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1381
1382	int rc = VINF_SUCCESS;
1383	RTCPUID idCpu = RTMpCpuId();
1384	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1385	AssertPtr(pCpu);
1386
1387	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1388	if (!pCpu->fConfigured)
1389	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1390
1391	/* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
1392	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE;
1393	pVCpu->hm.s.idEnteredCpu = idCpu;
1394	return rc;
1395	}
1396
1397
1398	/**
1399	* Enters the VT-x or AMD-V session.
1400	*
1401	* @returns VBox status code.
1402	* @param pVM Pointer to the VM.
1403	* @param pVCpu Pointer to the VMCPU.
1404	*
1405	* @remarks This is called with preemption disabled.
1406	*/
1407	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1408	{
1409	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1410	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1411	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1412
1413	/* Load the bare minimum state required for entering HM. */
1414	int rc = HMR0EnterCpu(pVCpu);
1415	AssertRCReturn(rc, rc);
1416
1417	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1418	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1419	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1420	#endif
1421
1422	RTCPUID idCpu = RTMpCpuId();
1423	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1424	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1425	Assert(pCpu);
1426	Assert(pCtx);
1427	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1428
1429	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1430	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1431
1432	/* Load the host as we may be resuming code after a longjmp and quite
1433	possibly now be scheduled on a different CPU. */
1434	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1435	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1436
1437	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1438	if (fStartedSet)
1439	PGMRZDynMapReleaseAutoSet(pVCpu);
1440	#endif
1441
1442	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1443	and ring-3 calls. */
1444	if (RT_FAILURE(rc))
1445	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1446	return rc;
1447	}
1448
1449
1450	/**
1451	* Deinitializes the bare minimum state used for HM context and if necessary
1452	* disable HM on the CPU.
1453	*
1454	* @returns VBox status code.
1455	* @param pVCpu Pointer to the VMCPU.
1456	*
1457	* @remarks No-long-jump zone!!!
1458	*/
1459	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1460	{
1461	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1462
1463	RTCPUID idCpu = RTMpCpuId();
1464	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1465
1466	if ( !g_HvmR0.fGlobalInit
1467	&& pCpu->fConfigured)
1468	{
1469	int rc = hmR0DisableCpu(idCpu);
1470	AssertRCReturn(rc, rc);
1471	Assert(!pCpu->fConfigured);
1472	}
1473
1474	/* Reset these to force a TLB flush for the next entry. */
1475	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1476	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1477	pVCpu->hm.s.uCurrentAsid = 0;
1478	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1479
1480	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1481	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1482
1483	return VINF_SUCCESS;
1484	}
1485
1486
1487	/**
1488	* Thread-context hook for HM.
1489	*
1490	* @param enmEvent The thread-context event.
1491	* @param pvUser Opaque pointer to the VMCPU.
1492	*/
1493	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1494	{
1495	PVMCPU pVCpu = (PVMCPU)pvUser;
1496	Assert(pVCpu);
1497	Assert(g_HvmR0.pfnThreadCtxCallback);
1498
1499	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1500	}
1501
1502
1503	/**
1504	* Runs guest code in a hardware accelerated VM.
1505	*
1506	* @returns VBox status code.
1507	* @param pVM Pointer to the VM.
1508	* @param pVCpu Pointer to the VMCPU.
1509	*
1510	* @remarks Called with preemption disabled and after first having called
1511	* HMR0Enter.
1512	*/
1513	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1514	{
1515	#ifdef VBOX_STRICT
1516	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1517	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1518	Assert(pCpu->fConfigured);
1519	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1520	#endif
1521
1522	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1523	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1524	PGMRZDynMapStartAutoSet(pVCpu);
1525	#endif
1526
1527	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1528
1529	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1530	PGMRZDynMapReleaseAutoSet(pVCpu);
1531	#endif
1532	return rc;
1533	}
1534
1535	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1536
1537	/**
1538	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1539	*
1540	* @returns VBox status code.
1541	* @param pVM Pointer to the VM.
1542	* @param pVCpu Pointer to the VMCPU.
1543	* @param pCtx Pointer to the guest CPU context.
1544	*/
1545	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1546	{
1547	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1548	if (pVM->hm.s.vmx.fSupported)
1549	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1550	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1551	}
1552
1553
1554	/**
1555	* Save guest debug state (64 bits guest mode & 32 bits host only)
1556	*
1557	* @returns VBox status code.
1558	* @param pVM Pointer to the VM.
1559	* @param pVCpu Pointer to the VMCPU.
1560	* @param pCtx Pointer to the guest CPU context.
1561	*/
1562	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1563	{
1564	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1565	if (pVM->hm.s.vmx.fSupported)
1566	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1567	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1568	}
1569
1570
1571	/**
1572	* Test the 32->64 bits switcher.
1573	*
1574	* @returns VBox status code.
1575	* @param pVM Pointer to the VM.
1576	*/
1577	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1578	{
1579	PVMCPU pVCpu = &pVM->aCpus[0];
1580	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1581	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1582	int rc;
1583
1584	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1585	if (pVM->hm.s.vmx.fSupported)
1586	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1587	else
1588	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1589	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1590
1591	return rc;
1592	}
1593
1594	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1595
1596	/**
1597	* Returns suspend status of the host.
1598	*
1599	* @returns Suspend pending or not.
1600	*/
1601	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1602	{
1603	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1604	}
1605
1606
1607	/**
1608	* Returns the cpu structure for the current cpu.
1609	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1610	*
1611	* @returns The cpu structure pointer.
1612	*/
1613	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1614	{
1615	RTCPUID idCpu = RTMpCpuId();
1616	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1617	return &g_HvmR0.aCpuInfo[idCpu];
1618	}
1619
1620
1621	/**
1622	* Returns the cpu structure for the current cpu.
1623	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1624	*
1625	* @returns The cpu structure pointer.
1626	* @param idCpu id of the VCPU.
1627	*/
1628	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1629	{
1630	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1631	return &g_HvmR0.aCpuInfo[idCpu];
1632	}
1633
1634
1635	/**
1636	* Save a pending IO read.
1637	*
1638	* @param pVCpu Pointer to the VMCPU.
1639	* @param GCPtrRip Address of IO instruction.
1640	* @param GCPtrRipNext Address of the next instruction.
1641	* @param uPort Port address.
1642	* @param uAndVal AND mask for saving the result in eax.
1643	* @param cbSize Read size.
1644	*/
1645	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1646	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1647	{
1648	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1649	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1650	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1651	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1652	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1653	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1654	return;
1655	}
1656
1657
1658	/**
1659	* Save a pending IO write.
1660	*
1661	* @param pVCpu Pointer to the VMCPU.
1662	* @param GCPtrRIP Address of IO instruction.
1663	* @param uPort Port address.
1664	* @param uAndVal AND mask for fetching the result from eax.
1665	* @param cbSize Read size.
1666	*/
1667	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1668	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1669	{
1670	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1671	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1672	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1673	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1674	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1675	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1676	return;
1677	}
1678
1679
1680	/**
1681	* Raw-mode switcher hook - disable VT-x if it's active and the current
1682	* switcher turns off paging.
1683	*
1684	* @returns VBox status code.
1685	* @param pVM Pointer to the VM.
1686	* @param enmSwitcher The switcher we're about to use.
1687	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1688	*/
1689	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1690	{
1691	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1692
1693	*pfVTxDisabled = false;
1694
1695	/* No such issues with AMD-V */
1696	if (!g_HvmR0.vmx.fSupported)
1697	return VINF_SUCCESS;
1698
1699	/* Check if the swithcing we're up to is safe. */
1700	switch (enmSwitcher)
1701	{
1702	case VMMSWITCHER_32_TO_32:
1703	case VMMSWITCHER_PAE_TO_PAE:
1704	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1705
1706	case VMMSWITCHER_32_TO_PAE:
1707	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1708	case VMMSWITCHER_AMD64_TO_32:
1709	case VMMSWITCHER_AMD64_TO_PAE:
1710	break; /* unsafe switchers */
1711
1712	default:
1713	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1714	}
1715
1716	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1717	regardless of whether we're currently using VT-x or not. */
1718	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1719	{
1720	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1721	return VINF_SUCCESS;
1722	}
1723
1724	/** @todo Check if this code is presumtive wrt other VT-x users on the
1725	* system... */
1726
1727	/* Nothing to do if we haven't enabled VT-x. */
1728	if (!g_HvmR0.fEnabled)
1729	return VINF_SUCCESS;
1730
1731	/* Local init implies the CPU is currently not in VMX root mode. */
1732	if (!g_HvmR0.fGlobalInit)
1733	return VINF_SUCCESS;
1734
1735	/* Ok, disable VT-x. */
1736	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1737	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1738
1739	*pfVTxDisabled = true;
1740	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1741	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1742	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1743	}
1744
1745
1746	/**
1747	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1748	* switcher turned off paging.
1749	*
1750	* @param pVM Pointer to the VM.
1751	* @param fVTxDisabled Whether VT-x was disabled or not.
1752	*/
1753	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1754	{
1755	Assert(!(ASMGetFlags() & X86_EFL_IF));
1756
1757	if (!fVTxDisabled)
1758	return; /* nothing to do */
1759
1760	Assert(g_HvmR0.vmx.fSupported);
1761	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1762	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1763	else
1764	{
1765	Assert(g_HvmR0.fEnabled);
1766	Assert(g_HvmR0.fGlobalInit);
1767
1768	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1769	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1770
1771	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1772	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1773	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
1774	}
1775	}
1776
1777	#ifdef VBOX_STRICT
1778
1779	/**
1780	* Dumps a descriptor.
1781	*
1782	* @param pDesc Descriptor to dump.
1783	* @param Sel Selector number.
1784	* @param pszMsg Message to prepend the log entry with.
1785	*/
1786	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1787	{
1788	/*
1789	* Make variable description string.
1790	*/
1791	static struct
1792	{
1793	unsigned cch;
1794	const char *psz;
1795	} const s_aTypes[32] =
1796	{
1797	# define STRENTRY(str) { sizeof(str) - 1, str }
1798
1799	/* system */
1800	# if HC_ARCH_BITS == 64
1801	STRENTRY("Reserved0 "), /* 0x00 */
1802	STRENTRY("Reserved1 "), /* 0x01 */
1803	STRENTRY("LDT "), /* 0x02 */
1804	STRENTRY("Reserved3 "), /* 0x03 */
1805	STRENTRY("Reserved4 "), /* 0x04 */
1806	STRENTRY("Reserved5 "), /* 0x05 */
1807	STRENTRY("Reserved6 "), /* 0x06 */
1808	STRENTRY("Reserved7 "), /* 0x07 */
1809	STRENTRY("Reserved8 "), /* 0x08 */
1810	STRENTRY("TSS64Avail "), /* 0x09 */
1811	STRENTRY("ReservedA "), /* 0x0a */
1812	STRENTRY("TSS64Busy "), /* 0x0b */
1813	STRENTRY("Call64 "), /* 0x0c */
1814	STRENTRY("ReservedD "), /* 0x0d */
1815	STRENTRY("Int64 "), /* 0x0e */
1816	STRENTRY("Trap64 "), /* 0x0f */
1817	# else
1818	STRENTRY("Reserved0 "), /* 0x00 */
1819	STRENTRY("TSS16Avail "), /* 0x01 */
1820	STRENTRY("LDT "), /* 0x02 */
1821	STRENTRY("TSS16Busy "), /* 0x03 */
1822	STRENTRY("Call16 "), /* 0x04 */
1823	STRENTRY("Task "), /* 0x05 */
1824	STRENTRY("Int16 "), /* 0x06 */
1825	STRENTRY("Trap16 "), /* 0x07 */
1826	STRENTRY("Reserved8 "), /* 0x08 */
1827	STRENTRY("TSS32Avail "), /* 0x09 */
1828	STRENTRY("ReservedA "), /* 0x0a */
1829	STRENTRY("TSS32Busy "), /* 0x0b */
1830	STRENTRY("Call32 "), /* 0x0c */
1831	STRENTRY("ReservedD "), /* 0x0d */
1832	STRENTRY("Int32 "), /* 0x0e */
1833	STRENTRY("Trap32 "), /* 0x0f */
1834	# endif
1835	/* non system */
1836	STRENTRY("DataRO "), /* 0x10 */
1837	STRENTRY("DataRO Accessed "), /* 0x11 */
1838	STRENTRY("DataRW "), /* 0x12 */
1839	STRENTRY("DataRW Accessed "), /* 0x13 */
1840	STRENTRY("DataDownRO "), /* 0x14 */
1841	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1842	STRENTRY("DataDownRW "), /* 0x16 */
1843	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1844	STRENTRY("CodeEO "), /* 0x18 */
1845	STRENTRY("CodeEO Accessed "), /* 0x19 */
1846	STRENTRY("CodeER "), /* 0x1a */
1847	STRENTRY("CodeER Accessed "), /* 0x1b */
1848	STRENTRY("CodeConfEO "), /* 0x1c */
1849	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1850	STRENTRY("CodeConfER "), /* 0x1e */
1851	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1852	# undef SYSENTRY
1853	};
1854	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1855	char szMsg[128];
1856	char *psz = &szMsg[0];
1857	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1858	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1859	psz += s_aTypes[i].cch;
1860
1861	if (pDesc->Gen.u1Present)
1862	ADD_STR(psz, "Present ");
1863	else
1864	ADD_STR(psz, "Not-Present ");
1865	# if HC_ARCH_BITS == 64
1866	if (pDesc->Gen.u1Long)
1867	ADD_STR(psz, "64-bit ");
1868	else
1869	ADD_STR(psz, "Comp ");
1870	# else
1871	if (pDesc->Gen.u1Granularity)
1872	ADD_STR(psz, "Page ");
1873	if (pDesc->Gen.u1DefBig)
1874	ADD_STR(psz, "32-bit ");
1875	else
1876	ADD_STR(psz, "16-bit ");
1877	# endif
1878	# undef ADD_STR
1879	*psz = '\0';
1880
1881	/*
1882	* Limit and Base and format the output.
1883	*/
1884	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1885
1886	# if HC_ARCH_BITS == 64
1887	uint64_t u32Base = X86DESC64_BASE(pDesc);
1888
1889	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1890	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1891	# else
1892	uint32_t u32Base = X86DESC_BASE(pDesc);
1893
1894	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1895	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1896	# endif
1897	}
1898
1899
1900	/**
1901	* Formats a full register dump.
1902	*
1903	* @param pVM Pointer to the VM.
1904	* @param pVCpu Pointer to the VMCPU.
1905	* @param pCtx Pointer to the CPU context.
1906	*/
1907	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1908	{
1909	NOREF(pVM);
1910
1911	/*
1912	* Format the flags.
1913	*/
1914	static struct
1915	{
1916	const char pszSet; const char pszClear; uint32_t fFlag;
1917	} const s_aFlags[] =
1918	{
1919	{ "vip",NULL, X86_EFL_VIP },
1920	{ "vif",NULL, X86_EFL_VIF },
1921	{ "ac", NULL, X86_EFL_AC },
1922	{ "vm", NULL, X86_EFL_VM },
1923	{ "rf", NULL, X86_EFL_RF },
1924	{ "nt", NULL, X86_EFL_NT },
1925	{ "ov", "nv", X86_EFL_OF },
1926	{ "dn", "up", X86_EFL_DF },
1927	{ "ei", "di", X86_EFL_IF },
1928	{ "tf", NULL, X86_EFL_TF },
1929	{ "nt", "pl", X86_EFL_SF },
1930	{ "nz", "zr", X86_EFL_ZF },
1931	{ "ac", "na", X86_EFL_AF },
1932	{ "po", "pe", X86_EFL_PF },
1933	{ "cy", "nc", X86_EFL_CF },
1934	};
1935	char szEFlags[80];
1936	char *psz = szEFlags;
1937	uint32_t efl = pCtx->eflags.u32;
1938	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1939	{
1940	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1941	if (pszAdd)
1942	{
1943	strcpy(psz, pszAdd);
1944	psz += strlen(pszAdd);
1945	*psz++ = ' ';
1946	}
1947	}
1948	psz[-1] = '\0';
1949
1950
1951	/*
1952	* Format the registers.
1953	*/
1954	if (CPUMIsGuestIn64BitCode(pVCpu))
1955	{
1956	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1957	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1958	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1959	"r14=%016RX64 r15=%016RX64\n"
1960	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1961	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1962	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1963	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1964	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1965	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1966	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1967	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1968	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1969	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1970	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1971	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1972	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1973	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1974	,
1975	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1976	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1977	pCtx->r14, pCtx->r15,
1978	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1979	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1980	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1981	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1982	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1983	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1984	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1985	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1986	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1987	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1988	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1989	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1990	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1991	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1992	}
1993	else
1994	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1995	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1996	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1997	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1998	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1999	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2000	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2001	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2002	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2003	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2004	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2005	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2006	,
2007	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2008	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2009	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2010	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2011	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2012	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2013	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2014	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2015	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2016	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2017	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2018	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2019
2020	Log(("FPU:\n"
2021	"FCW=%04x FSW=%04x FTW=%02x\n"
2022	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2023	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2024	,
2025	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2026	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2027	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2028	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2029
2030
2031	Log(("MSR:\n"
2032	"EFER =%016RX64\n"
2033	"PAT =%016RX64\n"
2034	"STAR =%016RX64\n"
2035	"CSTAR =%016RX64\n"
2036	"LSTAR =%016RX64\n"
2037	"SFMASK =%016RX64\n"
2038	"KERNELGSBASE =%016RX64\n",
2039	pCtx->msrEFER,
2040	pCtx->msrPAT,
2041	pCtx->msrSTAR,
2042	pCtx->msrCSTAR,
2043	pCtx->msrLSTAR,
2044	pCtx->msrSFMASK,
2045	pCtx->msrKERNELGSBASE));
2046
2047	}
2048
2049	#endif /* VBOX_STRICT */
2050

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 48227

Download in other formats: