HMR0.cpp@ 48280

Last change on this file since 48280 was 48280, checked in by vboxsync, 11 years ago
VMM/HMR0: Todo comment. SMX mode.
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1	/* $Id: HMR0.cpp 48280 2013-09-04 18:02:22Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost, void *pvArg));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	/** @todo This isn't used for anything relevant. Remove later? */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** VMX MSR values */
123	VMXMSRS Msrs;
124
125	/* Last instruction error */
126	uint32_t ulLastInstrError;
127	} vmx;
128
129	/** AMD-V information. */
130	struct
131	{
132	/* HWCR MSR (for diagnostics) */
133	uint64_t u64MsrHwcr;
134
135	/** SVM revision. */
136	uint32_t u32Rev;
137
138	/** SVM feature bits from cpuid 0x8000000a */
139	uint32_t u32Features;
140
141	/** Set by us to indicate SVM is supported by the CPU. */
142	bool fSupported;
143	} svm;
144	/** Saved error from detection */
145	int32_t lLastError;
146
147	struct
148	{
149	uint32_t u32AMDFeatureECX;
150	uint32_t u32AMDFeatureEDX;
151	} cpuid;
152
153	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
154	* enabled and disabled each time it's used to execute guest code. */
155	bool fGlobalInit;
156	/** Indicates whether the host is suspending or not. We'll refuse a few
157	* actions when the host is being suspended to speed up the suspending and
158	* avoid trouble. */
159	volatile bool fSuspended;
160
161	/** Whether we've already initialized all CPUs.
162	* @remarks We could check the EnableAllCpusOnce state, but this is
163	* simpler and hopefully easier to understand. */
164	bool fEnabled;
165	/** Serialize initialization in HMR0EnableAllCpus. */
166	RTONCE EnableAllCpusOnce;
167	} g_HvmR0;
168
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	/**
212	* Get the CPU ID on which the failure status code was reported.
213	*
214	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
215	* @param pFirstRc The first return code structure.
216	*/
217	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
218	{
219	return pFirstRc->idCpu;
220	}
221	#endif /* VBOX_STRICT */
222
223
224	/** @name Dummy callback handlers.
225	* @{ */
226
227	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
228	{
229	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
234	{
235	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
236	return VINF_SUCCESS;
237	}
238
239	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
240	{
241	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
242	}
243
244	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
245	bool fEnabledBySystem, void *pvArg)
246	{
247	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
252	{
253	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
254	return VINF_SUCCESS;
255	}
256
257	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
258	{
259	NOREF(pVM);
260	return VINF_SUCCESS;
261	}
262
263	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
264	{
265	NOREF(pVM);
266	return VINF_SUCCESS;
267	}
268
269	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
270	{
271	NOREF(pVM);
272	return VINF_SUCCESS;
273	}
274
275	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
276	{
277	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
278	return VINF_SUCCESS;
279	}
280
281	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
282	{
283	NOREF(pVM); NOREF(pVCpu);
284	return VINF_SUCCESS;
285	}
286
287	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
288	{
289	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
290	return VINF_SUCCESS;
291	}
292
293	/** @} */
294
295
296	/**
297	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
298	* Down at the Rate Specified" erratum.
299	*
300	* Errata names and related steppings:
301	* - BA86 - D0.
302	* - AAX65 - C2.
303	* - AAU65 - C2, K0.
304	* - AAO95 - B1.
305	* - AAT59 - C2.
306	* - AAK139 - D0.
307	* - AAM126 - C0, C1, D0.
308	* - AAN92 - B1.
309	* - AAJ124 - C0, D0.
310	*
311	* - AAP86 - B1.
312	*
313	* Steppings: B1, C0, C1, C2, D0, K0.
314	*
315	* @returns true if subject to it, false if not.
316	*/
317	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
318	{
319	uint32_t u = ASMCpuId_EAX(1);
320	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
321	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
322	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
323	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
324	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
325	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
326	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
327	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
328	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
329	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
330	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
331	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
332	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
333	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
334	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
335	)
336	return true;
337	return false;
338	}
339
340
341	/**
342	* Intel specific initialization code.
343	*
344	* @returns VBox status code (will only fail if out of memory).
345	*/
346	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
347	{
348	/*
349	* Check that all the required VT-x features are present.
350	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
351	*/
352	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
353	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
354	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
355	)
356	{
357	/** @todo move this into a separate function. */
358	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
359
360	/*
361	* First try use native kernel API for controlling VT-x.
362	* (This is only supported by some Mac OS X kernels atm.)
363	*/
364	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
365	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
366	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
367	{
368	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
369	if (RT_SUCCESS(rc))
370	{
371	g_HvmR0.vmx.fSupported = true;
372	rc = SUPR0EnableVTx(false /* fEnable */);
373	AssertLogRelRC(rc);
374	}
375	}
376	else
377	{
378	/* We need to check if VT-x has been properly initialized on all
379	CPUs. Some BIOSes do a lousy job. */
380	HMR0FIRSTRC FirstRc;
381	hmR0FirstRcInit(&FirstRc);
382	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
383	if (RT_SUCCESS(g_HvmR0.lLastError))
384	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
385	}
386	if (RT_SUCCESS(g_HvmR0.lLastError))
387	{
388	/* Reread in case we've changed it. */
389	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
390
391	/** @todo r=ramshankar: This should be fixed for when the host is in SMX mode.
392	* Probably don't need to recheck it here. It's done in
393	* hmR0InitIntelCpu(). */
394	if ( (g_HvmR0.vmx.Msrs.u64FeatureCtrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
395	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
396	{
397	/*
398	* Read all relevant registers and MSRs.
399	*/
400	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
401	g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
402	g_HvmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
403	g_HvmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
404	g_HvmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
405	g_HvmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
406	g_HvmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
407	g_HvmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
408	g_HvmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
409	g_HvmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
410	g_HvmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
411	g_HvmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
412	g_HvmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
413	/* VPID 16 bits ASID. */
414	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
415
416	if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
417	{
418	g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
419	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
420	g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
421
422	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
423	g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
424	}
425
426	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
427	{
428	/*
429	* Enter root mode
430	*/
431	RTR0MEMOBJ hScatchMemObj;
432	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
433	if (RT_FAILURE(rc))
434	{
435	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
436	return rc;
437	}
438
439	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
440	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
441	ASMMemZeroPage(pvScatchPage);
442
443	/* Set revision dword at the beginning of the structure. */
444	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo);
445
446	/* Make sure we don't get rescheduled to another cpu during this probe. */
447	RTCCUINTREG fFlags = ASMIntDisableFlags();
448
449	/*
450	* Check CR4.VMXE
451	*/
452	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
453	if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
454	{
455	/* In theory this bit could be cleared behind our back. Which would cause
456	#UD faults when we try to execute the VMX instructions... */
457	ASMSetCR4(g_HvmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
458	}
459
460	/*
461	* The only way of checking if we're in VMX root mode or not is to try and enter it.
462	* There is no instruction or control bit that tells us if we're in VMX root mode.
463	* Therefore, try and enter VMX root mode here.
464	*/
465	rc = VMXEnable(HCPhysScratchPage);
466	if (RT_SUCCESS(rc))
467	{
468	g_HvmR0.vmx.fSupported = true;
469	VMXDisable();
470	}
471	else
472	{
473	/*
474	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
475	* it will crash the host when we enter raw mode, because:
476	*
477	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
478	* this bit), and
479	* (b) turning off paging causes a #GP (unavoidable when switching
480	* from long to 32 bits mode or 32 bits to PAE).
481	*
482	* They should fix their code, but until they do we simply refuse to run.
483	*/
484	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
485	}
486
487	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
488	if it wasn't so before (some software could incorrectly
489	think it's in VMX mode). */
490	ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
491	ASMSetFlags(fFlags);
492
493	RTR0MemObjFree(hScatchMemObj, false);
494	}
495	}
496	else
497	{
498	AssertFailed(); /* can't hit this case anymore */
499	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
500	}
501
502	if (g_HvmR0.vmx.fSupported)
503	{
504	/* Call the global VT-x initialization routine. */
505	rc = VMXR0GlobalInit();
506	if (RT_FAILURE(rc))
507	g_HvmR0.lLastError = rc;
508
509	/*
510	* Install the VT-x methods.
511	*/
512	g_HvmR0.pfnEnterSession = VMXR0Enter;
513	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
514	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
515	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
516	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
517	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
518	g_HvmR0.pfnInitVM = VMXR0InitVM;
519	g_HvmR0.pfnTermVM = VMXR0TermVM;
520	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
521
522	/*
523	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
524	* Timer Does Not Count Down at the Rate Specified" erratum.
525	*/
526	if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
527	{
528	g_HvmR0.vmx.fUsePreemptTimer = true;
529	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc);
530	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
531	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
532	}
533	}
534	}
535	#ifdef LOG_ENABLED
536	else
537	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
538	#endif
539	}
540	else
541	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
542	return VINF_SUCCESS;
543	}
544
545
546	/**
547	* AMD-specific initialization code.
548	*
549	* @returns VBox status code.
550	*/
551	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
552	{
553	/*
554	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
555	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
556	*/
557	int rc;
558	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
559	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
560	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
561	&& ASMIsValidExtRange(uMaxExtLeaf)
562	&& uMaxExtLeaf >= 0x8000000a
563	)
564	{
565	/* Call the global AMD-V initialization routine. */
566	rc = SVMR0GlobalInit();
567	if (RT_FAILURE(rc))
568	{
569	g_HvmR0.lLastError = rc;
570	return rc;
571	}
572
573	/*
574	* Install the AMD-V methods.
575	*/
576	g_HvmR0.pfnEnterSession = SVMR0Enter;
577	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
578	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
579	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
580	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
581	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
582	g_HvmR0.pfnInitVM = SVMR0InitVM;
583	g_HvmR0.pfnTermVM = SVMR0TermVM;
584	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
585
586	/* Query AMD features. */
587	uint32_t u32Dummy;
588	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
589
590	/*
591	* We need to check if AMD-V has been properly initialized on all CPUs.
592	* Some BIOSes might do a poor job.
593	*/
594	HMR0FIRSTRC FirstRc;
595	hmR0FirstRcInit(&FirstRc);
596	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
597	AssertRC(rc);
598	if (RT_SUCCESS(rc))
599	rc = hmR0FirstRcGetStatus(&FirstRc);
600	#ifndef DEBUG_bird
601	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
602	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
603	#endif
604	if (RT_SUCCESS(rc))
605	{
606	/* Read the HWCR MSR for diagnostics. */
607	g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
608	g_HvmR0.svm.fSupported = true;
609	}
610	else
611	g_HvmR0.lLastError = rc;
612	}
613	else
614	{
615	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
616	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
617	}
618	return rc;
619	}
620
621
622	/**
623	* Does global Ring-0 HM initialization (at module init).
624	*
625	* @returns VBox status code.
626	*/
627	VMMR0_INT_DECL(int) HMR0Init(void)
628	{
629	/*
630	* Initialize the globals.
631	*/
632	g_HvmR0.fEnabled = false;
633	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
634	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
635	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
636	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
637
638	/* Fill in all callbacks with placeholders. */
639	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
640	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
641	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
642	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
643	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
644	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
645	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
646	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
647	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
648
649	/* Default is global VT-x/AMD-V init. */
650	g_HvmR0.fGlobalInit = true;
651
652	/*
653	* Make sure aCpuInfo is big enough for all the CPUs on this system.
654	*/
655	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
656	{
657	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
658	return VERR_TOO_MANY_CPUS;
659	}
660
661	/*
662	* Check for VT-x and AMD-V capabilities.
663	*/
664	int rc;
665	if (ASMHasCpuId())
666	{
667	/* Standard features. */
668	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
669	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
670	if (ASMIsValidStdRange(uMaxLeaf))
671	{
672	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
673	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
674
675	/* Query AMD features. */
676	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
677	if (ASMIsValidExtRange(uMaxExtLeaf))
678	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
679	&g_HvmR0.cpuid.u32AMDFeatureECX,
680	&g_HvmR0.cpuid.u32AMDFeatureEDX);
681	else
682	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
683
684	/* Go to CPU specific initialization code. */
685	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
686	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
687	{
688	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
689	if (RT_FAILURE(rc))
690	return rc;
691	}
692	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
693	{
694	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
695	if (RT_FAILURE(rc))
696	return rc;
697	}
698	else
699	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
700	}
701	else
702	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
703	}
704	else
705	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
706
707	/*
708	* Register notification callbacks that we can use to disable/enable CPUs
709	* when brought offline/online or suspending/resuming.
710	*/
711	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
712	{
713	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
714	AssertRC(rc);
715
716	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
717	AssertRC(rc);
718	}
719
720	/* We return success here because module init shall not fail if HM
721	fails to initialize. */
722	return VINF_SUCCESS;
723	}
724
725
726	/**
727	* Does global Ring-0 HM termination (at module termination).
728	*
729	* @returns VBox status code.
730	*/
731	VMMR0_INT_DECL(int) HMR0Term(void)
732	{
733	int rc;
734	if ( g_HvmR0.vmx.fSupported
735	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
736	{
737	/*
738	* Simple if the host OS manages VT-x.
739	*/
740	Assert(g_HvmR0.fGlobalInit);
741	rc = SUPR0EnableVTx(false /* fEnable */);
742
743	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
744	{
745	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
746	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
747	}
748	}
749	else
750	{
751	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
752	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
753	{
754	/* Doesn't really matter if this fails. */
755	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
756	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
757	}
758	else
759	rc = VINF_SUCCESS;
760
761	/*
762	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
763	*/
764	if (g_HvmR0.fGlobalInit)
765	{
766	HMR0FIRSTRC FirstRc;
767	hmR0FirstRcInit(&FirstRc);
768	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
769	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
770	if (RT_SUCCESS(rc))
771	{
772	rc = hmR0FirstRcGetStatus(&FirstRc);
773	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
774	}
775	}
776
777	/*
778	* Free the per-cpu pages used for VT-x and AMD-V.
779	*/
780	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
781	{
782	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
783	{
784	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
785	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
786	}
787	}
788	}
789
790	/** @todo This needs cleaning up. There's no matching
791	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
792	* should move into their respective modules. */
793	/* Finally, call global VT-x/AMD-V termination. */
794	if (g_HvmR0.vmx.fSupported)
795	VMXR0GlobalTerm();
796	else if (g_HvmR0.svm.fSupported)
797	SVMR0GlobalTerm();
798
799	return rc;
800	}
801
802
803	/**
804	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
805	* on a CPU.
806	*
807	* @param idCpu The identifier for the CPU the function is called on.
808	* @param pvUser1 Pointer to the first RC structure.
809	* @param pvUser2 Ignored.
810	*/
811	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
812	{
813	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
814	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
815	NOREF(pvUser2);
816
817	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
818	bool const fInSmxMode = !!(ASMGetCR4() & X86_CR4_SMXE);
819	bool fMsrLocked = !!(fFC & MSR_IA32_FEATURE_CONTROL_LOCK);
820	bool fSmxVmxAllowed = !!(fFC & MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
821	bool fVmxAllowed = !!(fFC & MSR_IA32_FEATURE_CONTROL_VMXON);
822
823	/* Check if the LOCK bit is set but excludes the required VMXON bit. */
824	int rc = VERR_HM_IPE_1;
825	if (fMsrLocked)
826	{
827	if (fInSmxMode && !fSmxVmxAllowed)
828	rc = VERR_VMX_MSR_SMX_VMXON_DISABLED;
829	else if (!fVmxAllowed)
830	rc = VERR_VMX_MSR_VMXON_DISABLED;
831	else
832	rc = VINF_SUCCESS;
833	}
834	else
835	{
836	/*
837	* MSR is not yet locked; we can change it ourselves here.
838	* Once the lock bit is set, this MSR can no longer be modified.
839	*/
840	fFC \|= MSR_IA32_FEATURE_CONTROL_LOCK;
841	if (fInSmxMode)
842	fFC \|= MSR_IA32_FEATURE_CONTROL_SMX_VMXON;
843	else
844	fFC \|= MSR_IA32_FEATURE_CONTROL_VMXON;
845
846	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, fFC);
847
848	/* Verify. */
849	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
850	fMsrLocked = !!(fFC & MSR_IA32_FEATURE_CONTROL_LOCK);
851	fSmxVmxAllowed = fMsrLocked && !!(fFC & MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
852	fVmxAllowed = fMsrLocked && !!(fFC & MSR_IA32_FEATURE_CONTROL_VMXON);
853	bool const fAllowed = fInSmxMode ? fSmxVmxAllowed : fVmxAllowed;
854	if (fAllowed)
855	rc = VINF_SUCCESS;
856	else
857	rc = VERR_VMX_MSR_LOCKING_FAILED;
858	}
859
860	hmR0FirstRcSetStatus(pFirstRc, rc);
861	}
862
863
864	/**
865	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
866	* on a CPU.
867	*
868	* @param idCpu The identifier for the CPU the function is called on.
869	* @param pvUser1 Pointer to the first RC structure.
870	* @param pvUser2 Ignored.
871	*/
872	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
873	{
874	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
875	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
876	NOREF(pvUser2);
877
878	/* Check if SVM is disabled. */
879	int rc;
880	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
881	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
882	{
883	/* Turn on SVM in the EFER MSR. */
884	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
885	if (fEfer & MSR_K6_EFER_SVME)
886	rc = VERR_SVM_IN_USE;
887	else
888	{
889	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
890
891	/* Paranoia. */
892	fEfer = ASMRdMsr(MSR_K6_EFER);
893	if (fEfer & MSR_K6_EFER_SVME)
894	{
895	/* Restore previous value. */
896	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
897	rc = VINF_SUCCESS;
898	}
899	else
900	rc = VERR_SVM_ILLEGAL_EFER_MSR;
901	}
902	}
903	else
904	rc = VERR_SVM_DISABLED;
905
906	hmR0FirstRcSetStatus(pFirstRc, rc);
907	}
908
909
910	/**
911	* Enable VT-x or AMD-V on the current CPU
912	*
913	* @returns VBox status code.
914	* @param pVM Pointer to the VM (can be NULL).
915	* @param idCpu The identifier for the CPU the function is called on.
916	*/
917	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
918	{
919	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
920
921	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
922	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
923	Assert(!pCpu->fConfigured);
924
925	pCpu->idCpu = idCpu;
926	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
927	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
928
929	int rc;
930	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
931	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HvmR0.vmx.Msrs);
932	else
933	{
934	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
935	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
936	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
937
938	if (g_HvmR0.vmx.fSupported)
939	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
940	else
941	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
942	}
943	AssertRC(rc);
944	if (RT_SUCCESS(rc))
945	pCpu->fConfigured = true;
946
947	return rc;
948	}
949
950
951	/**
952	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
953	*
954	* @param idCpu The identifier for the CPU the function is called on.
955	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
956	* @param pvUser2 The 2nd user argument.
957	*/
958	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
959	{
960	PVM pVM = (PVM)pvUser1; /* can be NULL! */
961	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
962	AssertReturnVoid(g_HvmR0.fGlobalInit);
963	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
964	}
965
966
967	/**
968	* RTOnce callback employed by HMR0EnableAllCpus.
969	*
970	* @returns VBox status code.
971	* @param pvUser Pointer to the VM.
972	* @param pvUserIgnore NULL, ignored.
973	*/
974	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
975	{
976	PVM pVM = (PVM)pvUser;
977
978	/*
979	* Indicate that we've initialized.
980	*
981	* Note! There is a potential race between this function and the suspend
982	* notification. Kind of unlikely though, so ignored for now.
983	*/
984	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
985	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
986
987	/*
988	* The global init variable is set by the first VM.
989	*/
990	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
991
992	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
993	{
994	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
995	g_HvmR0.aCpuInfo[i].fConfigured = false;
996	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
997	g_HvmR0.aCpuInfo[i].uCurrentAsid = 0;
998	}
999
1000	int rc;
1001	if ( g_HvmR0.vmx.fSupported
1002	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1003	{
1004	/*
1005	* Global VT-x initialization API (only darwin for now).
1006	*/
1007	rc = SUPR0EnableVTx(true /* fEnable */);
1008	if (RT_SUCCESS(rc))
1009	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
1010	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
1011	else
1012	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
1013	}
1014	else
1015	{
1016	/*
1017	* We're doing the job ourselves.
1018	*/
1019	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
1020	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1021	{
1022	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1023
1024	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1025	{
1026	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1027	AssertLogRelRCReturn(rc, rc);
1028
1029	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1030	ASMMemZeroPage(pvR0);
1031	}
1032	}
1033
1034	rc = VINF_SUCCESS;
1035	}
1036
1037	if ( RT_SUCCESS(rc)
1038	&& g_HvmR0.fGlobalInit)
1039	{
1040	/* First time, so initialize each cpu/core. */
1041	HMR0FIRSTRC FirstRc;
1042	hmR0FirstRcInit(&FirstRc);
1043	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1044	if (RT_SUCCESS(rc))
1045	rc = hmR0FirstRcGetStatus(&FirstRc);
1046	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1047	}
1048
1049	return rc;
1050	}
1051
1052
1053	/**
1054	* Sets up HM on all cpus.
1055	*
1056	* @returns VBox status code.
1057	* @param pVM Pointer to the VM.
1058	*/
1059	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1060	{
1061	/* Make sure we don't touch HM after we've disabled HM in
1062	preparation of a suspend. */
1063	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1064	return VERR_HM_SUSPEND_PENDING;
1065
1066	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1067	}
1068
1069
1070	/**
1071	* Disable VT-x or AMD-V on the current CPU.
1072	*
1073	* @returns VBox status code.
1074	* @param idCpu The identifier for the CPU the function is called on.
1075	*/
1076	static int hmR0DisableCpu(RTCPUID idCpu)
1077	{
1078	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1079
1080	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1081	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1082	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1083	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1084
1085	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1086	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1087
1088	int rc;
1089	if (pCpu->fConfigured)
1090	{
1091	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1092	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1093	if (idCpu == RTMpCpuId())
1094	{
1095	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1096	AssertRCReturn(rc, rc);
1097	}
1098	else
1099	{
1100	pCpu->fIgnoreAMDVInUseError = true;
1101	rc = VINF_SUCCESS;
1102	}
1103
1104	pCpu->fConfigured = false;
1105	}
1106	else
1107	rc = VINF_SUCCESS; /* nothing to do */
1108
1109	pCpu->uCurrentAsid = 0;
1110	return rc;
1111	}
1112
1113
1114	/**
1115	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1116	* is to be called on the target CPUs.
1117	*
1118	* @param idCpu The identifier for the CPU the function is called on.
1119	* @param pvUser1 The 1st user argument.
1120	* @param pvUser2 Opaque pointer to the FirstRc.
1121	*/
1122	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1123	{
1124	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1125	AssertReturnVoid(g_HvmR0.fGlobalInit);
1126	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1127	}
1128
1129
1130	/**
1131	* Callback function invoked when a cpu goes online or offline.
1132	*
1133	* @param enmEvent The Mp event.
1134	* @param idCpu The identifier for the CPU the function is called on.
1135	* @param pvData Opaque data (PVM pointer).
1136	*/
1137	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1138	{
1139	NOREF(pvData);
1140
1141	/*
1142	* We only care about uninitializing a CPU that is going offline. When a
1143	* CPU comes online, the initialization is done lazily in HMR0Enter().
1144	*/
1145	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1146	switch (enmEvent)
1147	{
1148	case RTMPEVENT_OFFLINE:
1149	{
1150	int rc = hmR0DisableCpu(idCpu);
1151	AssertRC(rc);
1152	break;
1153	}
1154
1155	default:
1156	break;
1157	}
1158	}
1159
1160
1161	/**
1162	* Called whenever a system power state change occurs.
1163	*
1164	* @param enmEvent The Power event.
1165	* @param pvUser User argument.
1166	*/
1167	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1168	{
1169	NOREF(pvUser);
1170	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1171
1172	#ifdef LOG_ENABLED
1173	if (enmEvent == RTPOWEREVENT_SUSPEND)
1174	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1175	else
1176	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1177	#endif
1178
1179	if (enmEvent == RTPOWEREVENT_SUSPEND)
1180	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1181
1182	if (g_HvmR0.fEnabled)
1183	{
1184	int rc;
1185	HMR0FIRSTRC FirstRc;
1186	hmR0FirstRcInit(&FirstRc);
1187
1188	if (enmEvent == RTPOWEREVENT_SUSPEND)
1189	{
1190	if (g_HvmR0.fGlobalInit)
1191	{
1192	/* Turn off VT-x or AMD-V on all CPUs. */
1193	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1194	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1195	}
1196	/* else nothing to do here for the local init case */
1197	}
1198	else
1199	{
1200	/* Reinit the CPUs from scratch as the suspend state might have
1201	messed with the MSRs. (lousy BIOSes as usual) */
1202	if (g_HvmR0.vmx.fSupported)
1203	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1204	else
1205	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1206	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1207	if (RT_SUCCESS(rc))
1208	rc = hmR0FirstRcGetStatus(&FirstRc);
1209	#ifdef LOG_ENABLED
1210	if (RT_FAILURE(rc))
1211	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1212	#endif
1213	if (g_HvmR0.fGlobalInit)
1214	{
1215	/* Turn VT-x or AMD-V back on on all CPUs. */
1216	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1217	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1218	}
1219	/* else nothing to do here for the local init case */
1220	}
1221	}
1222
1223	if (enmEvent == RTPOWEREVENT_RESUME)
1224	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1225	}
1226
1227
1228	/**
1229	* Does Ring-0 per VM HM initialization.
1230	*
1231	* This will copy HM global into the VM structure and call the CPU specific
1232	* init routine which will allocate resources for each virtual CPU and such.
1233	*
1234	* @returns VBox status code.
1235	* @param pVM Pointer to the VM.
1236	*/
1237	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1238	{
1239	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1240
1241	#ifdef LOG_ENABLED
1242	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1243	#endif
1244
1245	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1246	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1247	return VERR_HM_SUSPEND_PENDING;
1248
1249	/*
1250	* Copy globals to the VM structure.
1251	*/
1252	/** @todo r=ramshankar: Why do we do this for MSRs? We never change them in the
1253	* per-VM structures anyway... */
1254	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1255	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1256
1257	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1258	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1259	pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4;
1260	pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer;
1261	pVM->hm.s.vmx.Msrs = g_HvmR0.vmx.Msrs;
1262	pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr;
1263	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1264	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1265	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1266	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1267	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1268
1269	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1270
1271
1272	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1273	{
1274	pVM->hm.s.cMaxResumeLoops = 1024;
1275	if (RTThreadPreemptIsPendingTrusty())
1276	pVM->hm.s.cMaxResumeLoops = 8192;
1277	}
1278
1279	/*
1280	* Initialize some per CPU fields.
1281	*/
1282	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1283	{
1284	PVMCPU pVCpu = &pVM->aCpus[i];
1285
1286	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1287
1288	/* Invalidate the last cpu we were running on. */
1289	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1290
1291	/* We'll aways increment this the first time (host uses ASID 0) */
1292	pVCpu->hm.s.uCurrentAsid = 0;
1293	}
1294
1295	/*
1296	* Call the hardware specific initialization method.
1297	*/
1298	RTCCUINTREG fFlags = ASMIntDisableFlags();
1299	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1300	ASMSetFlags(fFlags);
1301
1302	int rc = g_HvmR0.pfnInitVM(pVM);
1303	return rc;
1304	}
1305
1306
1307	/**
1308	* Does Ring-0 per VM HM termination.
1309	*
1310	* @returns VBox status code.
1311	* @param pVM Pointer to the VM.
1312	*/
1313	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1314	{
1315	Log(("HMR0TermVM: %p\n", pVM));
1316	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1317
1318	/* Make sure we don't touch HM after we've disabled HM in preparation
1319	of a suspend. */
1320	/** @todo r=bird: This cannot be right, the termination functions are
1321	* just freeing memory and resetting pVM/pVCpu members...
1322	* ==> memory leak. */
1323	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1324
1325	/*
1326	* Call the hardware specific method.
1327	*/
1328	RTCCUINTREG fFlags = ASMIntDisableFlags();
1329	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1330	ASMSetFlags(fFlags);
1331
1332	int rc = g_HvmR0.pfnTermVM(pVM);
1333	return rc;
1334	}
1335
1336
1337	/**
1338	* Sets up a VT-x or AMD-V session.
1339	*
1340	* This is mostly about setting up the hardware VM state.
1341	*
1342	* @returns VBox status code.
1343	* @param pVM Pointer to the VM.
1344	*/
1345	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1346	{
1347	Log(("HMR0SetupVM: %p\n", pVM));
1348	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1349
1350	/* Make sure we don't touch HM after we've disabled HM in
1351	preparation of a suspend. */
1352	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1353
1354	/*
1355	* Call the hardware specific setup VM method. This requires the CPU to be
1356	* enabled for AMD-V/VT-x and preemption to be prevented.
1357	*/
1358	RTCCUINTREG fFlags = ASMIntDisableFlags();
1359	RTCPUID idCpu = RTMpCpuId();
1360	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1361
1362	/* On first entry we'll sync everything. */
1363	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1364	pVM->aCpus[i].hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1365
1366	/* Enable VT-x or AMD-V if local init is required. */
1367	int rc;
1368	if (!g_HvmR0.fGlobalInit)
1369	{
1370	rc = hmR0EnableCpu(pVM, idCpu);
1371	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1372	}
1373
1374	/* Setup VT-x or AMD-V. */
1375	rc = g_HvmR0.pfnSetupVM(pVM);
1376
1377	/* Disable VT-x or AMD-V if local init was done before. */
1378	if (!g_HvmR0.fGlobalInit)
1379	{
1380	int rc2 = hmR0DisableCpu(idCpu);
1381	AssertRC(rc2);
1382	}
1383
1384	ASMSetFlags(fFlags);
1385	return rc;
1386	}
1387
1388
1389	/**
1390	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1391	* required for entering HM context.
1392	*
1393	* @returns VBox status code.
1394	* @param pvCpu Pointer to the VMCPU.
1395	*
1396	* @remarks No-long-jump zone!!!
1397	*/
1398	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1399	{
1400	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1401
1402	int rc = VINF_SUCCESS;
1403	RTCPUID idCpu = RTMpCpuId();
1404	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1405	AssertPtr(pCpu);
1406
1407	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1408	if (!pCpu->fConfigured)
1409	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1410
1411	/* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
1412	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE;
1413	pVCpu->hm.s.idEnteredCpu = idCpu;
1414	return rc;
1415	}
1416
1417
1418	/**
1419	* Enters the VT-x or AMD-V session.
1420	*
1421	* @returns VBox status code.
1422	* @param pVM Pointer to the VM.
1423	* @param pVCpu Pointer to the VMCPU.
1424	*
1425	* @remarks This is called with preemption disabled.
1426	*/
1427	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1428	{
1429	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1430	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1431	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1432
1433	/* Load the bare minimum state required for entering HM. */
1434	int rc = HMR0EnterCpu(pVCpu);
1435	AssertRCReturn(rc, rc);
1436
1437	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1438	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1439	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1440	#endif
1441
1442	RTCPUID idCpu = RTMpCpuId();
1443	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1444	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1445	Assert(pCpu);
1446	Assert(pCtx);
1447	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1448
1449	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1450	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1451
1452	/* Load the host as we may be resuming code after a longjmp and quite
1453	possibly now be scheduled on a different CPU. */
1454	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1455	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1456
1457	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1458	if (fStartedSet)
1459	PGMRZDynMapReleaseAutoSet(pVCpu);
1460	#endif
1461
1462	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1463	and ring-3 calls. */
1464	if (RT_FAILURE(rc))
1465	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1466	return rc;
1467	}
1468
1469
1470	/**
1471	* Deinitializes the bare minimum state used for HM context and if necessary
1472	* disable HM on the CPU.
1473	*
1474	* @returns VBox status code.
1475	* @param pVCpu Pointer to the VMCPU.
1476	*
1477	* @remarks No-long-jump zone!!!
1478	*/
1479	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1480	{
1481	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1482
1483	RTCPUID idCpu = RTMpCpuId();
1484	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1485
1486	if ( !g_HvmR0.fGlobalInit
1487	&& pCpu->fConfigured)
1488	{
1489	int rc = hmR0DisableCpu(idCpu);
1490	AssertRCReturn(rc, rc);
1491	Assert(!pCpu->fConfigured);
1492	}
1493
1494	/* Reset these to force a TLB flush for the next entry. */
1495	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1496	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1497	pVCpu->hm.s.uCurrentAsid = 0;
1498	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1499
1500	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1501	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1502
1503	return VINF_SUCCESS;
1504	}
1505
1506
1507	/**
1508	* Thread-context hook for HM.
1509	*
1510	* @param enmEvent The thread-context event.
1511	* @param pvUser Opaque pointer to the VMCPU.
1512	*/
1513	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1514	{
1515	PVMCPU pVCpu = (PVMCPU)pvUser;
1516	Assert(pVCpu);
1517	Assert(g_HvmR0.pfnThreadCtxCallback);
1518
1519	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1520	}
1521
1522
1523	/**
1524	* Runs guest code in a hardware accelerated VM.
1525	*
1526	* @returns VBox status code.
1527	* @param pVM Pointer to the VM.
1528	* @param pVCpu Pointer to the VMCPU.
1529	*
1530	* @remarks Called with preemption disabled and after first having called
1531	* HMR0Enter.
1532	*/
1533	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1534	{
1535	#ifdef VBOX_STRICT
1536	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1537	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1538	Assert(pCpu->fConfigured);
1539	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1540	#endif
1541
1542	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1543	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1544	PGMRZDynMapStartAutoSet(pVCpu);
1545	#endif
1546
1547	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1548
1549	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1550	PGMRZDynMapReleaseAutoSet(pVCpu);
1551	#endif
1552	return rc;
1553	}
1554
1555	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1556
1557	/**
1558	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1559	*
1560	* @returns VBox status code.
1561	* @param pVM Pointer to the VM.
1562	* @param pVCpu Pointer to the VMCPU.
1563	* @param pCtx Pointer to the guest CPU context.
1564	*/
1565	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1566	{
1567	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1568	if (pVM->hm.s.vmx.fSupported)
1569	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1570	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1571	}
1572
1573
1574	/**
1575	* Save guest debug state (64 bits guest mode & 32 bits host only)
1576	*
1577	* @returns VBox status code.
1578	* @param pVM Pointer to the VM.
1579	* @param pVCpu Pointer to the VMCPU.
1580	* @param pCtx Pointer to the guest CPU context.
1581	*/
1582	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1583	{
1584	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1585	if (pVM->hm.s.vmx.fSupported)
1586	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1587	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1588	}
1589
1590
1591	/**
1592	* Test the 32->64 bits switcher.
1593	*
1594	* @returns VBox status code.
1595	* @param pVM Pointer to the VM.
1596	*/
1597	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1598	{
1599	PVMCPU pVCpu = &pVM->aCpus[0];
1600	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1601	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1602	int rc;
1603
1604	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1605	if (pVM->hm.s.vmx.fSupported)
1606	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1607	else
1608	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1609	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1610
1611	return rc;
1612	}
1613
1614	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1615
1616	/**
1617	* Returns suspend status of the host.
1618	*
1619	* @returns Suspend pending or not.
1620	*/
1621	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1622	{
1623	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1624	}
1625
1626
1627	/**
1628	* Returns the cpu structure for the current cpu.
1629	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1630	*
1631	* @returns The cpu structure pointer.
1632	*/
1633	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1634	{
1635	RTCPUID idCpu = RTMpCpuId();
1636	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1637	return &g_HvmR0.aCpuInfo[idCpu];
1638	}
1639
1640
1641	/**
1642	* Returns the cpu structure for the current cpu.
1643	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1644	*
1645	* @returns The cpu structure pointer.
1646	* @param idCpu id of the VCPU.
1647	*/
1648	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1649	{
1650	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1651	return &g_HvmR0.aCpuInfo[idCpu];
1652	}
1653
1654
1655	/**
1656	* Save a pending IO read.
1657	*
1658	* @param pVCpu Pointer to the VMCPU.
1659	* @param GCPtrRip Address of IO instruction.
1660	* @param GCPtrRipNext Address of the next instruction.
1661	* @param uPort Port address.
1662	* @param uAndVal AND mask for saving the result in eax.
1663	* @param cbSize Read size.
1664	*/
1665	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1666	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1667	{
1668	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1669	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1670	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1671	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1672	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1673	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1674	return;
1675	}
1676
1677
1678	/**
1679	* Save a pending IO write.
1680	*
1681	* @param pVCpu Pointer to the VMCPU.
1682	* @param GCPtrRIP Address of IO instruction.
1683	* @param uPort Port address.
1684	* @param uAndVal AND mask for fetching the result from eax.
1685	* @param cbSize Read size.
1686	*/
1687	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1688	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1689	{
1690	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1691	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1692	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1693	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1694	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1695	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1696	return;
1697	}
1698
1699
1700	/**
1701	* Raw-mode switcher hook - disable VT-x if it's active and the current
1702	* switcher turns off paging.
1703	*
1704	* @returns VBox status code.
1705	* @param pVM Pointer to the VM.
1706	* @param enmSwitcher The switcher we're about to use.
1707	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1708	*/
1709	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1710	{
1711	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1712
1713	*pfVTxDisabled = false;
1714
1715	/* No such issues with AMD-V */
1716	if (!g_HvmR0.vmx.fSupported)
1717	return VINF_SUCCESS;
1718
1719	/* Check if the swithcing we're up to is safe. */
1720	switch (enmSwitcher)
1721	{
1722	case VMMSWITCHER_32_TO_32:
1723	case VMMSWITCHER_PAE_TO_PAE:
1724	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1725
1726	case VMMSWITCHER_32_TO_PAE:
1727	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1728	case VMMSWITCHER_AMD64_TO_32:
1729	case VMMSWITCHER_AMD64_TO_PAE:
1730	break; /* unsafe switchers */
1731
1732	default:
1733	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1734	}
1735
1736	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1737	regardless of whether we're currently using VT-x or not. */
1738	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1739	{
1740	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1741	return VINF_SUCCESS;
1742	}
1743
1744	/** @todo Check if this code is presumtive wrt other VT-x users on the
1745	* system... */
1746
1747	/* Nothing to do if we haven't enabled VT-x. */
1748	if (!g_HvmR0.fEnabled)
1749	return VINF_SUCCESS;
1750
1751	/* Local init implies the CPU is currently not in VMX root mode. */
1752	if (!g_HvmR0.fGlobalInit)
1753	return VINF_SUCCESS;
1754
1755	/* Ok, disable VT-x. */
1756	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1757	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1758
1759	*pfVTxDisabled = true;
1760	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1761	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1762	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1763	}
1764
1765
1766	/**
1767	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1768	* switcher turned off paging.
1769	*
1770	* @param pVM Pointer to the VM.
1771	* @param fVTxDisabled Whether VT-x was disabled or not.
1772	*/
1773	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1774	{
1775	Assert(!(ASMGetFlags() & X86_EFL_IF));
1776
1777	if (!fVTxDisabled)
1778	return; /* nothing to do */
1779
1780	Assert(g_HvmR0.vmx.fSupported);
1781	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1782	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1783	else
1784	{
1785	Assert(g_HvmR0.fEnabled);
1786	Assert(g_HvmR0.fGlobalInit);
1787
1788	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1789	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1790
1791	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1792	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1793	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
1794	}
1795	}
1796
1797	#ifdef VBOX_STRICT
1798
1799	/**
1800	* Dumps a descriptor.
1801	*
1802	* @param pDesc Descriptor to dump.
1803	* @param Sel Selector number.
1804	* @param pszMsg Message to prepend the log entry with.
1805	*/
1806	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1807	{
1808	/*
1809	* Make variable description string.
1810	*/
1811	static struct
1812	{
1813	unsigned cch;
1814	const char *psz;
1815	} const s_aTypes[32] =
1816	{
1817	# define STRENTRY(str) { sizeof(str) - 1, str }
1818
1819	/* system */
1820	# if HC_ARCH_BITS == 64
1821	STRENTRY("Reserved0 "), /* 0x00 */
1822	STRENTRY("Reserved1 "), /* 0x01 */
1823	STRENTRY("LDT "), /* 0x02 */
1824	STRENTRY("Reserved3 "), /* 0x03 */
1825	STRENTRY("Reserved4 "), /* 0x04 */
1826	STRENTRY("Reserved5 "), /* 0x05 */
1827	STRENTRY("Reserved6 "), /* 0x06 */
1828	STRENTRY("Reserved7 "), /* 0x07 */
1829	STRENTRY("Reserved8 "), /* 0x08 */
1830	STRENTRY("TSS64Avail "), /* 0x09 */
1831	STRENTRY("ReservedA "), /* 0x0a */
1832	STRENTRY("TSS64Busy "), /* 0x0b */
1833	STRENTRY("Call64 "), /* 0x0c */
1834	STRENTRY("ReservedD "), /* 0x0d */
1835	STRENTRY("Int64 "), /* 0x0e */
1836	STRENTRY("Trap64 "), /* 0x0f */
1837	# else
1838	STRENTRY("Reserved0 "), /* 0x00 */
1839	STRENTRY("TSS16Avail "), /* 0x01 */
1840	STRENTRY("LDT "), /* 0x02 */
1841	STRENTRY("TSS16Busy "), /* 0x03 */
1842	STRENTRY("Call16 "), /* 0x04 */
1843	STRENTRY("Task "), /* 0x05 */
1844	STRENTRY("Int16 "), /* 0x06 */
1845	STRENTRY("Trap16 "), /* 0x07 */
1846	STRENTRY("Reserved8 "), /* 0x08 */
1847	STRENTRY("TSS32Avail "), /* 0x09 */
1848	STRENTRY("ReservedA "), /* 0x0a */
1849	STRENTRY("TSS32Busy "), /* 0x0b */
1850	STRENTRY("Call32 "), /* 0x0c */
1851	STRENTRY("ReservedD "), /* 0x0d */
1852	STRENTRY("Int32 "), /* 0x0e */
1853	STRENTRY("Trap32 "), /* 0x0f */
1854	# endif
1855	/* non system */
1856	STRENTRY("DataRO "), /* 0x10 */
1857	STRENTRY("DataRO Accessed "), /* 0x11 */
1858	STRENTRY("DataRW "), /* 0x12 */
1859	STRENTRY("DataRW Accessed "), /* 0x13 */
1860	STRENTRY("DataDownRO "), /* 0x14 */
1861	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1862	STRENTRY("DataDownRW "), /* 0x16 */
1863	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1864	STRENTRY("CodeEO "), /* 0x18 */
1865	STRENTRY("CodeEO Accessed "), /* 0x19 */
1866	STRENTRY("CodeER "), /* 0x1a */
1867	STRENTRY("CodeER Accessed "), /* 0x1b */
1868	STRENTRY("CodeConfEO "), /* 0x1c */
1869	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1870	STRENTRY("CodeConfER "), /* 0x1e */
1871	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1872	# undef SYSENTRY
1873	};
1874	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1875	char szMsg[128];
1876	char *psz = &szMsg[0];
1877	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1878	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1879	psz += s_aTypes[i].cch;
1880
1881	if (pDesc->Gen.u1Present)
1882	ADD_STR(psz, "Present ");
1883	else
1884	ADD_STR(psz, "Not-Present ");
1885	# if HC_ARCH_BITS == 64
1886	if (pDesc->Gen.u1Long)
1887	ADD_STR(psz, "64-bit ");
1888	else
1889	ADD_STR(psz, "Comp ");
1890	# else
1891	if (pDesc->Gen.u1Granularity)
1892	ADD_STR(psz, "Page ");
1893	if (pDesc->Gen.u1DefBig)
1894	ADD_STR(psz, "32-bit ");
1895	else
1896	ADD_STR(psz, "16-bit ");
1897	# endif
1898	# undef ADD_STR
1899	*psz = '\0';
1900
1901	/*
1902	* Limit and Base and format the output.
1903	*/
1904	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1905
1906	# if HC_ARCH_BITS == 64
1907	uint64_t u32Base = X86DESC64_BASE(pDesc);
1908
1909	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1910	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1911	# else
1912	uint32_t u32Base = X86DESC_BASE(pDesc);
1913
1914	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1915	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1916	# endif
1917	}
1918
1919
1920	/**
1921	* Formats a full register dump.
1922	*
1923	* @param pVM Pointer to the VM.
1924	* @param pVCpu Pointer to the VMCPU.
1925	* @param pCtx Pointer to the CPU context.
1926	*/
1927	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1928	{
1929	NOREF(pVM);
1930
1931	/*
1932	* Format the flags.
1933	*/
1934	static struct
1935	{
1936	const char pszSet; const char pszClear; uint32_t fFlag;
1937	} const s_aFlags[] =
1938	{
1939	{ "vip",NULL, X86_EFL_VIP },
1940	{ "vif",NULL, X86_EFL_VIF },
1941	{ "ac", NULL, X86_EFL_AC },
1942	{ "vm", NULL, X86_EFL_VM },
1943	{ "rf", NULL, X86_EFL_RF },
1944	{ "nt", NULL, X86_EFL_NT },
1945	{ "ov", "nv", X86_EFL_OF },
1946	{ "dn", "up", X86_EFL_DF },
1947	{ "ei", "di", X86_EFL_IF },
1948	{ "tf", NULL, X86_EFL_TF },
1949	{ "nt", "pl", X86_EFL_SF },
1950	{ "nz", "zr", X86_EFL_ZF },
1951	{ "ac", "na", X86_EFL_AF },
1952	{ "po", "pe", X86_EFL_PF },
1953	{ "cy", "nc", X86_EFL_CF },
1954	};
1955	char szEFlags[80];
1956	char *psz = szEFlags;
1957	uint32_t efl = pCtx->eflags.u32;
1958	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1959	{
1960	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1961	if (pszAdd)
1962	{
1963	strcpy(psz, pszAdd);
1964	psz += strlen(pszAdd);
1965	*psz++ = ' ';
1966	}
1967	}
1968	psz[-1] = '\0';
1969
1970
1971	/*
1972	* Format the registers.
1973	*/
1974	if (CPUMIsGuestIn64BitCode(pVCpu))
1975	{
1976	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1977	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1978	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1979	"r14=%016RX64 r15=%016RX64\n"
1980	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1981	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1982	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1983	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1984	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1985	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1986	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1987	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1988	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1989	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1990	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1991	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1992	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1993	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1994	,
1995	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1996	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1997	pCtx->r14, pCtx->r15,
1998	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1999	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2000	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2001	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2002	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2003	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2004	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2005	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
2006	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
2007	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2008	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2009	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2010	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2011	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2012	}
2013	else
2014	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2015	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2016	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2017	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2018	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2019	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2020	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2021	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2022	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2023	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2024	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2025	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2026	,
2027	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2028	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2029	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2030	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2031	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2032	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2033	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2034	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2035	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2036	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2037	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2038	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2039
2040	Log(("FPU:\n"
2041	"FCW=%04x FSW=%04x FTW=%02x\n"
2042	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2043	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2044	,
2045	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2046	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2047	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2048	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2049
2050
2051	Log(("MSR:\n"
2052	"EFER =%016RX64\n"
2053	"PAT =%016RX64\n"
2054	"STAR =%016RX64\n"
2055	"CSTAR =%016RX64\n"
2056	"LSTAR =%016RX64\n"
2057	"SFMASK =%016RX64\n"
2058	"KERNELGSBASE =%016RX64\n",
2059	pCtx->msrEFER,
2060	pCtx->msrPAT,
2061	pCtx->msrSTAR,
2062	pCtx->msrCSTAR,
2063	pCtx->msrLSTAR,
2064	pCtx->msrSFMASK,
2065	pCtx->msrKERNELGSBASE));
2066
2067	}
2068
2069	#endif /* VBOX_STRICT */
2070

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 48280

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