HMR0.cpp@ 48402

Last change on this file since 48402 was 48328, checked in by vboxsync, 11 years ago
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1	/* $Id: HMR0.cpp 48328 2013-09-05 22:20:18Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost, void *pvArg));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	/** @todo This isn't used for anything relevant. Remove later? */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** VMX MSR values */
123	VMXMSRS Msrs;
124
125	/* Last instruction error */
126	uint32_t ulLastInstrError;
127	} vmx;
128
129	/** AMD-V information. */
130	struct
131	{
132	/* HWCR MSR (for diagnostics) */
133	uint64_t u64MsrHwcr;
134
135	/** SVM revision. */
136	uint32_t u32Rev;
137
138	/** SVM feature bits from cpuid 0x8000000a */
139	uint32_t u32Features;
140
141	/** Set by us to indicate SVM is supported by the CPU. */
142	bool fSupported;
143	} svm;
144	/** Saved error from detection */
145	int32_t lLastError;
146
147	struct
148	{
149	uint32_t u32AMDFeatureECX;
150	uint32_t u32AMDFeatureEDX;
151	} cpuid;
152
153	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
154	* enabled and disabled each time it's used to execute guest code. */
155	bool fGlobalInit;
156	/** Indicates whether the host is suspending or not. We'll refuse a few
157	* actions when the host is being suspended to speed up the suspending and
158	* avoid trouble. */
159	volatile bool fSuspended;
160
161	/** Whether we've already initialized all CPUs.
162	* @remarks We could check the EnableAllCpusOnce state, but this is
163	* simpler and hopefully easier to understand. */
164	bool fEnabled;
165	/** Serialize initialization in HMR0EnableAllCpus. */
166	RTONCE EnableAllCpusOnce;
167	} g_HvmR0;
168
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	/**
212	* Get the CPU ID on which the failure status code was reported.
213	*
214	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
215	* @param pFirstRc The first return code structure.
216	*/
217	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
218	{
219	return pFirstRc->idCpu;
220	}
221	#endif /* VBOX_STRICT */
222
223
224	/** @name Dummy callback handlers.
225	* @{ */
226
227	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
228	{
229	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
234	{
235	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
236	return VINF_SUCCESS;
237	}
238
239	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
240	{
241	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
242	}
243
244	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
245	bool fEnabledBySystem, void *pvArg)
246	{
247	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
252	{
253	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
254	return VINF_SUCCESS;
255	}
256
257	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
258	{
259	NOREF(pVM);
260	return VINF_SUCCESS;
261	}
262
263	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
264	{
265	NOREF(pVM);
266	return VINF_SUCCESS;
267	}
268
269	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
270	{
271	NOREF(pVM);
272	return VINF_SUCCESS;
273	}
274
275	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
276	{
277	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
278	return VINF_SUCCESS;
279	}
280
281	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
282	{
283	NOREF(pVM); NOREF(pVCpu);
284	return VINF_SUCCESS;
285	}
286
287	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
288	{
289	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
290	return VINF_SUCCESS;
291	}
292
293	/** @} */
294
295
296	/**
297	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
298	* Down at the Rate Specified" erratum.
299	*
300	* Errata names and related steppings:
301	* - BA86 - D0.
302	* - AAX65 - C2.
303	* - AAU65 - C2, K0.
304	* - AAO95 - B1.
305	* - AAT59 - C2.
306	* - AAK139 - D0.
307	* - AAM126 - C0, C1, D0.
308	* - AAN92 - B1.
309	* - AAJ124 - C0, D0.
310	*
311	* - AAP86 - B1.
312	*
313	* Steppings: B1, C0, C1, C2, D0, K0.
314	*
315	* @returns true if subject to it, false if not.
316	*/
317	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
318	{
319	uint32_t u = ASMCpuId_EAX(1);
320	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
321	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
322	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
323	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
324	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
325	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
326	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
327	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
328	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
329	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
330	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
331	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
332	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
333	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
334	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
335	)
336	return true;
337	return false;
338	}
339
340
341	/**
342	* Intel specific initialization code.
343	*
344	* @returns VBox status code (will only fail if out of memory).
345	*/
346	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
347	{
348	/*
349	* Check that all the required VT-x features are present.
350	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
351	*/
352	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
353	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
354	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
355	)
356	{
357	/** @todo move this into a separate function. */
358	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
359
360	/*
361	* First try use native kernel API for controlling VT-x.
362	* (This is only supported by some Mac OS X kernels atm.)
363	*/
364	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
365	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
366	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
367	{
368	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
369	if (RT_SUCCESS(rc))
370	{
371	g_HvmR0.vmx.fSupported = true;
372	rc = SUPR0EnableVTx(false /* fEnable */);
373	AssertLogRelRC(rc);
374	}
375	}
376	else
377	{
378	/* We need to check if VT-x has been properly initialized on all
379	CPUs. Some BIOSes do a lousy job. */
380	HMR0FIRSTRC FirstRc;
381	hmR0FirstRcInit(&FirstRc);
382	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
383	if (RT_SUCCESS(g_HvmR0.lLastError))
384	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
385	}
386	if (RT_SUCCESS(g_HvmR0.lLastError))
387	{
388	/* Reread in case it was changed by hmR0InitIntelCpu(). */
389	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
390
391	/*
392	* Read all relevant registers and MSRs.
393	*/
394	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
395	g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
396	g_HvmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
397	g_HvmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
398	g_HvmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
399	g_HvmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
400	g_HvmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
401	g_HvmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
402	g_HvmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
403	g_HvmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
404	g_HvmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
405	g_HvmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
406	g_HvmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
407	/* VPID 16 bits ASID. */
408	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
409
410	if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
411	{
412	g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
413	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
414	g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
415
416	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
417	g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
418	}
419
420	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
421	{
422	/*
423	* Enter root mode
424	*/
425	RTR0MEMOBJ hScatchMemObj;
426	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
427	if (RT_FAILURE(rc))
428	{
429	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
430	return rc;
431	}
432
433	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
434	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
435	ASMMemZeroPage(pvScatchPage);
436
437	/* Set revision dword at the beginning of the structure. */
438	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo);
439
440	/* Make sure we don't get rescheduled to another cpu during this probe. */
441	RTCCUINTREG fFlags = ASMIntDisableFlags();
442
443	/*
444	* Check CR4.VMXE
445	*/
446	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
447	if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
448	{
449	/* In theory this bit could be cleared behind our back. Which would cause
450	#UD faults when we try to execute the VMX instructions... */
451	ASMSetCR4(g_HvmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
452	}
453
454	/*
455	* The only way of checking if we're in VMX root mode or not is to try and enter it.
456	* There is no instruction or control bit that tells us if we're in VMX root mode.
457	* Therefore, try and enter VMX root mode here.
458	*/
459	rc = VMXEnable(HCPhysScratchPage);
460	if (RT_SUCCESS(rc))
461	{
462	g_HvmR0.vmx.fSupported = true;
463	VMXDisable();
464	}
465	else
466	{
467	/*
468	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
469	* it will crash the host when we enter raw mode, because:
470	*
471	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
472	* this bit), and
473	* (b) turning off paging causes a #GP (unavoidable when switching
474	* from long to 32 bits mode or 32 bits to PAE).
475	*
476	* They should fix their code, but until they do we simply refuse to run.
477	*/
478	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
479	Assert(g_HvmR0.vmx.fSupported == false);
480	}
481
482	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
483	if it wasn't so before (some software could incorrectly
484	think it's in VMX mode). */
485	ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
486	ASMSetFlags(fFlags);
487
488	RTR0MemObjFree(hScatchMemObj, false);
489	}
490
491	if (g_HvmR0.vmx.fSupported)
492	{
493	rc = VMXR0GlobalInit();
494	if (RT_FAILURE(rc))
495	g_HvmR0.lLastError = rc;
496
497	/*
498	* Install the VT-x methods.
499	*/
500	g_HvmR0.pfnEnterSession = VMXR0Enter;
501	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
502	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
503	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
504	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
505	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
506	g_HvmR0.pfnInitVM = VMXR0InitVM;
507	g_HvmR0.pfnTermVM = VMXR0TermVM;
508	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
509
510	/*
511	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
512	* Timer Does Not Count Down at the Rate Specified" erratum.
513	*/
514	if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
515	{
516	g_HvmR0.vmx.fUsePreemptTimer = true;
517	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc);
518	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
519	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
520	}
521	}
522	}
523	#ifdef LOG_ENABLED
524	else
525	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
526	#endif
527	}
528	else
529	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
530	return VINF_SUCCESS;
531	}
532
533
534	/**
535	* AMD-specific initialization code.
536	*
537	* @returns VBox status code.
538	*/
539	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
540	{
541	/*
542	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
543	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
544	*/
545	int rc;
546	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
547	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
548	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
549	&& ASMIsValidExtRange(uMaxExtLeaf)
550	&& uMaxExtLeaf >= 0x8000000a
551	)
552	{
553	/* Call the global AMD-V initialization routine. */
554	rc = SVMR0GlobalInit();
555	if (RT_FAILURE(rc))
556	{
557	g_HvmR0.lLastError = rc;
558	return rc;
559	}
560
561	/*
562	* Install the AMD-V methods.
563	*/
564	g_HvmR0.pfnEnterSession = SVMR0Enter;
565	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
566	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
567	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
568	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
569	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
570	g_HvmR0.pfnInitVM = SVMR0InitVM;
571	g_HvmR0.pfnTermVM = SVMR0TermVM;
572	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
573
574	/* Query AMD features. */
575	uint32_t u32Dummy;
576	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
577
578	/*
579	* We need to check if AMD-V has been properly initialized on all CPUs.
580	* Some BIOSes might do a poor job.
581	*/
582	HMR0FIRSTRC FirstRc;
583	hmR0FirstRcInit(&FirstRc);
584	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
585	AssertRC(rc);
586	if (RT_SUCCESS(rc))
587	rc = hmR0FirstRcGetStatus(&FirstRc);
588	#ifndef DEBUG_bird
589	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
590	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
591	#endif
592	if (RT_SUCCESS(rc))
593	{
594	/* Read the HWCR MSR for diagnostics. */
595	g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
596	g_HvmR0.svm.fSupported = true;
597	}
598	else
599	g_HvmR0.lLastError = rc;
600	}
601	else
602	{
603	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
604	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
605	}
606	return rc;
607	}
608
609
610	/**
611	* Does global Ring-0 HM initialization (at module init).
612	*
613	* @returns VBox status code.
614	*/
615	VMMR0_INT_DECL(int) HMR0Init(void)
616	{
617	/*
618	* Initialize the globals.
619	*/
620	g_HvmR0.fEnabled = false;
621	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
622	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
623	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
624	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
625
626	/* Fill in all callbacks with placeholders. */
627	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
628	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
629	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
630	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
631	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
632	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
633	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
634	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
635	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
636
637	/* Default is global VT-x/AMD-V init. */
638	g_HvmR0.fGlobalInit = true;
639
640	/*
641	* Make sure aCpuInfo is big enough for all the CPUs on this system.
642	*/
643	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
644	{
645	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
646	return VERR_TOO_MANY_CPUS;
647	}
648
649	/*
650	* Check for VT-x and AMD-V capabilities.
651	*/
652	int rc;
653	if (ASMHasCpuId())
654	{
655	/* Standard features. */
656	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
657	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
658	if (ASMIsValidStdRange(uMaxLeaf))
659	{
660	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
661	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
662
663	/* Query AMD features. */
664	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
665	if (ASMIsValidExtRange(uMaxExtLeaf))
666	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
667	&g_HvmR0.cpuid.u32AMDFeatureECX,
668	&g_HvmR0.cpuid.u32AMDFeatureEDX);
669	else
670	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
671
672	/* Go to CPU specific initialization code. */
673	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
674	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
675	{
676	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
677	if (RT_FAILURE(rc))
678	return rc;
679	}
680	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
681	{
682	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
683	if (RT_FAILURE(rc))
684	return rc;
685	}
686	else
687	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
688	}
689	else
690	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
691	}
692	else
693	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
694
695	/*
696	* Register notification callbacks that we can use to disable/enable CPUs
697	* when brought offline/online or suspending/resuming.
698	*/
699	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
700	{
701	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
702	AssertRC(rc);
703
704	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
705	AssertRC(rc);
706	}
707
708	/* We return success here because module init shall not fail if HM
709	fails to initialize. */
710	return VINF_SUCCESS;
711	}
712
713
714	/**
715	* Does global Ring-0 HM termination (at module termination).
716	*
717	* @returns VBox status code.
718	*/
719	VMMR0_INT_DECL(int) HMR0Term(void)
720	{
721	int rc;
722	if ( g_HvmR0.vmx.fSupported
723	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
724	{
725	/*
726	* Simple if the host OS manages VT-x.
727	*/
728	Assert(g_HvmR0.fGlobalInit);
729	rc = SUPR0EnableVTx(false /* fEnable */);
730
731	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
732	{
733	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
734	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
735	}
736	}
737	else
738	{
739	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
740	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
741	{
742	/* Doesn't really matter if this fails. */
743	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
744	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
745	}
746	else
747	rc = VINF_SUCCESS;
748
749	/*
750	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
751	*/
752	if (g_HvmR0.fGlobalInit)
753	{
754	HMR0FIRSTRC FirstRc;
755	hmR0FirstRcInit(&FirstRc);
756	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
757	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
758	if (RT_SUCCESS(rc))
759	{
760	rc = hmR0FirstRcGetStatus(&FirstRc);
761	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
762	}
763	}
764
765	/*
766	* Free the per-cpu pages used for VT-x and AMD-V.
767	*/
768	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
769	{
770	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
771	{
772	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
773	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
774	}
775	}
776	}
777
778	/** @todo This needs cleaning up. There's no matching
779	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
780	* should move into their respective modules. */
781	/* Finally, call global VT-x/AMD-V termination. */
782	if (g_HvmR0.vmx.fSupported)
783	VMXR0GlobalTerm();
784	else if (g_HvmR0.svm.fSupported)
785	SVMR0GlobalTerm();
786
787	return rc;
788	}
789
790
791	/**
792	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
793	* on a CPU.
794	*
795	* @param idCpu The identifier for the CPU the function is called on.
796	* @param pvUser1 Pointer to the first RC structure.
797	* @param pvUser2 Ignored.
798	*/
799	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
800	{
801	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
802	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
803	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
804	NOREF(pvUser2);
805
806	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
807	bool const fInSmxMode = !!(ASMGetCR4() & X86_CR4_SMXE);
808	bool fMsrLocked = !!(fFC & MSR_IA32_FEATURE_CONTROL_LOCK);
809	bool fSmxVmxAllowed = !!(fFC & MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
810	bool fVmxAllowed = !!(fFC & MSR_IA32_FEATURE_CONTROL_VMXON);
811
812	/* Check if the LOCK bit is set but excludes the required VMXON bit. */
813	int rc = VERR_HM_IPE_1;
814	if (fMsrLocked)
815	{
816	if (fInSmxMode && !fSmxVmxAllowed)
817	rc = VERR_VMX_MSR_SMX_VMXON_DISABLED;
818	else if (!fVmxAllowed)
819	rc = VERR_VMX_MSR_VMXON_DISABLED;
820	else
821	rc = VINF_SUCCESS;
822	}
823	else
824	{
825	/*
826	* MSR is not yet locked; we can change it ourselves here.
827	* Once the lock bit is set, this MSR can no longer be modified.
828	*/
829	fFC \|= MSR_IA32_FEATURE_CONTROL_LOCK;
830	if (fInSmxMode)
831	fFC \|= MSR_IA32_FEATURE_CONTROL_SMX_VMXON;
832	else
833	fFC \|= MSR_IA32_FEATURE_CONTROL_VMXON;
834
835	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, fFC);
836
837	/* Verify. */
838	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
839	fMsrLocked = !!(fFC & MSR_IA32_FEATURE_CONTROL_LOCK);
840	fSmxVmxAllowed = fMsrLocked && !!(fFC & MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
841	fVmxAllowed = fMsrLocked && !!(fFC & MSR_IA32_FEATURE_CONTROL_VMXON);
842	bool const fAllowed = fInSmxMode ? fSmxVmxAllowed : fVmxAllowed;
843	if (fAllowed)
844	rc = VINF_SUCCESS;
845	else
846	rc = VERR_VMX_MSR_LOCKING_FAILED;
847	}
848
849	hmR0FirstRcSetStatus(pFirstRc, rc);
850	}
851
852
853	/**
854	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
855	* on a CPU.
856	*
857	* @param idCpu The identifier for the CPU the function is called on.
858	* @param pvUser1 Pointer to the first RC structure.
859	* @param pvUser2 Ignored.
860	*/
861	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
862	{
863	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
864	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
865	NOREF(pvUser2);
866
867	/* Check if SVM is disabled. */
868	int rc;
869	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
870	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
871	{
872	/* Turn on SVM in the EFER MSR. */
873	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
874	if (fEfer & MSR_K6_EFER_SVME)
875	rc = VERR_SVM_IN_USE;
876	else
877	{
878	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
879
880	/* Paranoia. */
881	fEfer = ASMRdMsr(MSR_K6_EFER);
882	if (fEfer & MSR_K6_EFER_SVME)
883	{
884	/* Restore previous value. */
885	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
886	rc = VINF_SUCCESS;
887	}
888	else
889	rc = VERR_SVM_ILLEGAL_EFER_MSR;
890	}
891	}
892	else
893	rc = VERR_SVM_DISABLED;
894
895	hmR0FirstRcSetStatus(pFirstRc, rc);
896	}
897
898
899	/**
900	* Enable VT-x or AMD-V on the current CPU
901	*
902	* @returns VBox status code.
903	* @param pVM Pointer to the VM (can be NULL).
904	* @param idCpu The identifier for the CPU the function is called on.
905	*/
906	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
907	{
908	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
909
910	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
911	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
912	Assert(!pCpu->fConfigured);
913
914	pCpu->idCpu = idCpu;
915	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
916	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
917
918	int rc;
919	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
920	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HvmR0.vmx.Msrs);
921	else
922	{
923	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
924	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
925	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
926
927	if (g_HvmR0.vmx.fSupported)
928	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
929	else
930	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
931	}
932	AssertRC(rc);
933	if (RT_SUCCESS(rc))
934	pCpu->fConfigured = true;
935
936	return rc;
937	}
938
939
940	/**
941	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
942	*
943	* @param idCpu The identifier for the CPU the function is called on.
944	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
945	* @param pvUser2 The 2nd user argument.
946	*/
947	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
948	{
949	PVM pVM = (PVM)pvUser1; /* can be NULL! */
950	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
951	AssertReturnVoid(g_HvmR0.fGlobalInit);
952	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
953	}
954
955
956	/**
957	* RTOnce callback employed by HMR0EnableAllCpus.
958	*
959	* @returns VBox status code.
960	* @param pvUser Pointer to the VM.
961	* @param pvUserIgnore NULL, ignored.
962	*/
963	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
964	{
965	PVM pVM = (PVM)pvUser;
966
967	/*
968	* Indicate that we've initialized.
969	*
970	* Note! There is a potential race between this function and the suspend
971	* notification. Kind of unlikely though, so ignored for now.
972	*/
973	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
974	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
975
976	/*
977	* The global init variable is set by the first VM.
978	*/
979	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
980
981	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
982	{
983	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
984	g_HvmR0.aCpuInfo[i].fConfigured = false;
985	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
986	g_HvmR0.aCpuInfo[i].uCurrentAsid = 0;
987	}
988
989	int rc;
990	if ( g_HvmR0.vmx.fSupported
991	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
992	{
993	/*
994	* Global VT-x initialization API (only darwin for now).
995	*/
996	rc = SUPR0EnableVTx(true /* fEnable */);
997	if (RT_SUCCESS(rc))
998	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
999	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
1000	else
1001	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
1002	}
1003	else
1004	{
1005	/*
1006	* We're doing the job ourselves.
1007	*/
1008	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
1009	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1010	{
1011	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1012
1013	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1014	{
1015	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1016	AssertLogRelRCReturn(rc, rc);
1017
1018	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1019	ASMMemZeroPage(pvR0);
1020	}
1021	}
1022
1023	rc = VINF_SUCCESS;
1024	}
1025
1026	if ( RT_SUCCESS(rc)
1027	&& g_HvmR0.fGlobalInit)
1028	{
1029	/* First time, so initialize each cpu/core. */
1030	HMR0FIRSTRC FirstRc;
1031	hmR0FirstRcInit(&FirstRc);
1032	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1033	if (RT_SUCCESS(rc))
1034	rc = hmR0FirstRcGetStatus(&FirstRc);
1035	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1036	}
1037
1038	return rc;
1039	}
1040
1041
1042	/**
1043	* Sets up HM on all cpus.
1044	*
1045	* @returns VBox status code.
1046	* @param pVM Pointer to the VM.
1047	*/
1048	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1049	{
1050	/* Make sure we don't touch HM after we've disabled HM in
1051	preparation of a suspend. */
1052	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1053	return VERR_HM_SUSPEND_PENDING;
1054
1055	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1056	}
1057
1058
1059	/**
1060	* Disable VT-x or AMD-V on the current CPU.
1061	*
1062	* @returns VBox status code.
1063	* @param idCpu The identifier for the CPU the function is called on.
1064	*/
1065	static int hmR0DisableCpu(RTCPUID idCpu)
1066	{
1067	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1068
1069	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1070	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1071	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1072	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1073
1074	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1075	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1076
1077	int rc;
1078	if (pCpu->fConfigured)
1079	{
1080	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1081	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1082	if (idCpu == RTMpCpuId())
1083	{
1084	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1085	AssertRCReturn(rc, rc);
1086	}
1087	else
1088	{
1089	pCpu->fIgnoreAMDVInUseError = true;
1090	rc = VINF_SUCCESS;
1091	}
1092
1093	pCpu->fConfigured = false;
1094	}
1095	else
1096	rc = VINF_SUCCESS; /* nothing to do */
1097
1098	pCpu->uCurrentAsid = 0;
1099	return rc;
1100	}
1101
1102
1103	/**
1104	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1105	* is to be called on the target CPUs.
1106	*
1107	* @param idCpu The identifier for the CPU the function is called on.
1108	* @param pvUser1 The 1st user argument.
1109	* @param pvUser2 Opaque pointer to the FirstRc.
1110	*/
1111	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1112	{
1113	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1114	AssertReturnVoid(g_HvmR0.fGlobalInit);
1115	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1116	}
1117
1118
1119	/**
1120	* Callback function invoked when a cpu goes online or offline.
1121	*
1122	* @param enmEvent The Mp event.
1123	* @param idCpu The identifier for the CPU the function is called on.
1124	* @param pvData Opaque data (PVM pointer).
1125	*/
1126	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1127	{
1128	NOREF(pvData);
1129
1130	/*
1131	* We only care about uninitializing a CPU that is going offline. When a
1132	* CPU comes online, the initialization is done lazily in HMR0Enter().
1133	*/
1134	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1135	switch (enmEvent)
1136	{
1137	case RTMPEVENT_OFFLINE:
1138	{
1139	int rc = hmR0DisableCpu(idCpu);
1140	AssertRC(rc);
1141	break;
1142	}
1143
1144	default:
1145	break;
1146	}
1147	}
1148
1149
1150	/**
1151	* Called whenever a system power state change occurs.
1152	*
1153	* @param enmEvent The Power event.
1154	* @param pvUser User argument.
1155	*/
1156	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1157	{
1158	NOREF(pvUser);
1159	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1160
1161	#ifdef LOG_ENABLED
1162	if (enmEvent == RTPOWEREVENT_SUSPEND)
1163	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1164	else
1165	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1166	#endif
1167
1168	if (enmEvent == RTPOWEREVENT_SUSPEND)
1169	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1170
1171	if (g_HvmR0.fEnabled)
1172	{
1173	int rc;
1174	HMR0FIRSTRC FirstRc;
1175	hmR0FirstRcInit(&FirstRc);
1176
1177	if (enmEvent == RTPOWEREVENT_SUSPEND)
1178	{
1179	if (g_HvmR0.fGlobalInit)
1180	{
1181	/* Turn off VT-x or AMD-V on all CPUs. */
1182	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1183	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1184	}
1185	/* else nothing to do here for the local init case */
1186	}
1187	else
1188	{
1189	/* Reinit the CPUs from scratch as the suspend state might have
1190	messed with the MSRs. (lousy BIOSes as usual) */
1191	if (g_HvmR0.vmx.fSupported)
1192	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1193	else
1194	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1195	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1196	if (RT_SUCCESS(rc))
1197	rc = hmR0FirstRcGetStatus(&FirstRc);
1198	#ifdef LOG_ENABLED
1199	if (RT_FAILURE(rc))
1200	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1201	#endif
1202	if (g_HvmR0.fGlobalInit)
1203	{
1204	/* Turn VT-x or AMD-V back on on all CPUs. */
1205	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1206	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1207	}
1208	/* else nothing to do here for the local init case */
1209	}
1210	}
1211
1212	if (enmEvent == RTPOWEREVENT_RESUME)
1213	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1214	}
1215
1216
1217	/**
1218	* Does Ring-0 per VM HM initialization.
1219	*
1220	* This will copy HM global into the VM structure and call the CPU specific
1221	* init routine which will allocate resources for each virtual CPU and such.
1222	*
1223	* @returns VBox status code.
1224	* @param pVM Pointer to the VM.
1225	*/
1226	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1227	{
1228	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1229
1230	#ifdef LOG_ENABLED
1231	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1232	#endif
1233
1234	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1235	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1236	return VERR_HM_SUSPEND_PENDING;
1237
1238	/*
1239	* Copy globals to the VM structure.
1240	*/
1241	/** @todo r=ramshankar: Why do we do this for MSRs? We never change them in the
1242	* per-VM structures anyway... */
1243	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1244	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1245
1246	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1247	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1248	pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4;
1249	pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer;
1250	pVM->hm.s.vmx.Msrs = g_HvmR0.vmx.Msrs;
1251	pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr;
1252	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1253	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1254	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1255	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1256	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1257
1258	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1259
1260
1261	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1262	{
1263	pVM->hm.s.cMaxResumeLoops = 1024;
1264	if (RTThreadPreemptIsPendingTrusty())
1265	pVM->hm.s.cMaxResumeLoops = 8192;
1266	}
1267
1268	/*
1269	* Initialize some per CPU fields.
1270	*/
1271	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1272	{
1273	PVMCPU pVCpu = &pVM->aCpus[i];
1274
1275	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1276
1277	/* Invalidate the last cpu we were running on. */
1278	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1279
1280	/* We'll aways increment this the first time (host uses ASID 0) */
1281	pVCpu->hm.s.uCurrentAsid = 0;
1282	}
1283
1284	/*
1285	* Call the hardware specific initialization method.
1286	*/
1287	RTCCUINTREG fFlags = ASMIntDisableFlags();
1288	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1289	ASMSetFlags(fFlags);
1290
1291	int rc = g_HvmR0.pfnInitVM(pVM);
1292	return rc;
1293	}
1294
1295
1296	/**
1297	* Does Ring-0 per VM HM termination.
1298	*
1299	* @returns VBox status code.
1300	* @param pVM Pointer to the VM.
1301	*/
1302	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1303	{
1304	Log(("HMR0TermVM: %p\n", pVM));
1305	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1306
1307	/* Make sure we don't touch HM after we've disabled HM in preparation
1308	of a suspend. */
1309	/** @todo r=bird: This cannot be right, the termination functions are
1310	* just freeing memory and resetting pVM/pVCpu members...
1311	* ==> memory leak. */
1312	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1313
1314	/*
1315	* Call the hardware specific method.
1316	*/
1317	RTCCUINTREG fFlags = ASMIntDisableFlags();
1318	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1319	ASMSetFlags(fFlags);
1320
1321	int rc = g_HvmR0.pfnTermVM(pVM);
1322	return rc;
1323	}
1324
1325
1326	/**
1327	* Sets up a VT-x or AMD-V session.
1328	*
1329	* This is mostly about setting up the hardware VM state.
1330	*
1331	* @returns VBox status code.
1332	* @param pVM Pointer to the VM.
1333	*/
1334	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1335	{
1336	Log(("HMR0SetupVM: %p\n", pVM));
1337	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1338
1339	/* Make sure we don't touch HM after we've disabled HM in
1340	preparation of a suspend. */
1341	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1342
1343	/*
1344	* Call the hardware specific setup VM method. This requires the CPU to be
1345	* enabled for AMD-V/VT-x and preemption to be prevented.
1346	*/
1347	RTCCUINTREG fFlags = ASMIntDisableFlags();
1348	RTCPUID idCpu = RTMpCpuId();
1349	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1350
1351	/* On first entry we'll sync everything. */
1352	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1353	pVM->aCpus[i].hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1354
1355	/* Enable VT-x or AMD-V if local init is required. */
1356	int rc;
1357	if (!g_HvmR0.fGlobalInit)
1358	{
1359	rc = hmR0EnableCpu(pVM, idCpu);
1360	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1361	}
1362
1363	/* Setup VT-x or AMD-V. */
1364	rc = g_HvmR0.pfnSetupVM(pVM);
1365
1366	/* Disable VT-x or AMD-V if local init was done before. */
1367	if (!g_HvmR0.fGlobalInit)
1368	{
1369	int rc2 = hmR0DisableCpu(idCpu);
1370	AssertRC(rc2);
1371	}
1372
1373	ASMSetFlags(fFlags);
1374	return rc;
1375	}
1376
1377
1378	/**
1379	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1380	* required for entering HM context.
1381	*
1382	* @returns VBox status code.
1383	* @param pvCpu Pointer to the VMCPU.
1384	*
1385	* @remarks No-long-jump zone!!!
1386	*/
1387	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1388	{
1389	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1390
1391	int rc = VINF_SUCCESS;
1392	RTCPUID idCpu = RTMpCpuId();
1393	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1394	AssertPtr(pCpu);
1395
1396	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1397	if (!pCpu->fConfigured)
1398	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1399
1400	/* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
1401	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE;
1402	pVCpu->hm.s.idEnteredCpu = idCpu;
1403	return rc;
1404	}
1405
1406
1407	/**
1408	* Enters the VT-x or AMD-V session.
1409	*
1410	* @returns VBox status code.
1411	* @param pVM Pointer to the VM.
1412	* @param pVCpu Pointer to the VMCPU.
1413	*
1414	* @remarks This is called with preemption disabled.
1415	*/
1416	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1417	{
1418	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1419	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1420	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1421
1422	/* Load the bare minimum state required for entering HM. */
1423	int rc = HMR0EnterCpu(pVCpu);
1424	AssertRCReturn(rc, rc);
1425
1426	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1427	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1428	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1429	#endif
1430
1431	RTCPUID idCpu = RTMpCpuId();
1432	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1433	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1434	Assert(pCpu);
1435	Assert(pCtx);
1436	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1437
1438	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1439	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1440
1441	/* Load the host as we may be resuming code after a longjmp and quite
1442	possibly now be scheduled on a different CPU. */
1443	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1444	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1445
1446	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1447	if (fStartedSet)
1448	PGMRZDynMapReleaseAutoSet(pVCpu);
1449	#endif
1450
1451	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1452	and ring-3 calls. */
1453	if (RT_FAILURE(rc))
1454	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1455	return rc;
1456	}
1457
1458
1459	/**
1460	* Deinitializes the bare minimum state used for HM context and if necessary
1461	* disable HM on the CPU.
1462	*
1463	* @returns VBox status code.
1464	* @param pVCpu Pointer to the VMCPU.
1465	*
1466	* @remarks No-long-jump zone!!!
1467	*/
1468	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1469	{
1470	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1471
1472	RTCPUID idCpu = RTMpCpuId();
1473	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1474
1475	if ( !g_HvmR0.fGlobalInit
1476	&& pCpu->fConfigured)
1477	{
1478	int rc = hmR0DisableCpu(idCpu);
1479	AssertRCReturn(rc, rc);
1480	Assert(!pCpu->fConfigured);
1481	}
1482
1483	/* Reset these to force a TLB flush for the next entry. */
1484	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1485	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1486	pVCpu->hm.s.uCurrentAsid = 0;
1487	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1488
1489	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1490	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1491
1492	return VINF_SUCCESS;
1493	}
1494
1495
1496	/**
1497	* Thread-context hook for HM.
1498	*
1499	* @param enmEvent The thread-context event.
1500	* @param pvUser Opaque pointer to the VMCPU.
1501	*/
1502	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1503	{
1504	PVMCPU pVCpu = (PVMCPU)pvUser;
1505	Assert(pVCpu);
1506	Assert(g_HvmR0.pfnThreadCtxCallback);
1507
1508	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1509	}
1510
1511
1512	/**
1513	* Runs guest code in a hardware accelerated VM.
1514	*
1515	* @returns VBox status code.
1516	* @param pVM Pointer to the VM.
1517	* @param pVCpu Pointer to the VMCPU.
1518	*
1519	* @remarks Called with preemption disabled and after first having called
1520	* HMR0Enter.
1521	*/
1522	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1523	{
1524	#ifdef VBOX_STRICT
1525	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1526	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1527	Assert(pCpu->fConfigured);
1528	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1529	#endif
1530
1531	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1532	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1533	PGMRZDynMapStartAutoSet(pVCpu);
1534	#endif
1535
1536	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1537
1538	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1539	PGMRZDynMapReleaseAutoSet(pVCpu);
1540	#endif
1541	return rc;
1542	}
1543
1544	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1545
1546	/**
1547	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1548	*
1549	* @returns VBox status code.
1550	* @param pVM Pointer to the VM.
1551	* @param pVCpu Pointer to the VMCPU.
1552	* @param pCtx Pointer to the guest CPU context.
1553	*/
1554	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1555	{
1556	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1557	if (pVM->hm.s.vmx.fSupported)
1558	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1559	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1560	}
1561
1562
1563	/**
1564	* Save guest debug state (64 bits guest mode & 32 bits host only)
1565	*
1566	* @returns VBox status code.
1567	* @param pVM Pointer to the VM.
1568	* @param pVCpu Pointer to the VMCPU.
1569	* @param pCtx Pointer to the guest CPU context.
1570	*/
1571	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1572	{
1573	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1574	if (pVM->hm.s.vmx.fSupported)
1575	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1576	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1577	}
1578
1579
1580	/**
1581	* Test the 32->64 bits switcher.
1582	*
1583	* @returns VBox status code.
1584	* @param pVM Pointer to the VM.
1585	*/
1586	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1587	{
1588	PVMCPU pVCpu = &pVM->aCpus[0];
1589	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1590	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1591	int rc;
1592
1593	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1594	if (pVM->hm.s.vmx.fSupported)
1595	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1596	else
1597	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1598	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1599
1600	return rc;
1601	}
1602
1603	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1604
1605	/**
1606	* Returns suspend status of the host.
1607	*
1608	* @returns Suspend pending or not.
1609	*/
1610	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1611	{
1612	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1613	}
1614
1615
1616	/**
1617	* Returns the cpu structure for the current cpu.
1618	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1619	*
1620	* @returns The cpu structure pointer.
1621	*/
1622	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1623	{
1624	RTCPUID idCpu = RTMpCpuId();
1625	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1626	return &g_HvmR0.aCpuInfo[idCpu];
1627	}
1628
1629
1630	/**
1631	* Returns the cpu structure for the current cpu.
1632	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1633	*
1634	* @returns The cpu structure pointer.
1635	* @param idCpu id of the VCPU.
1636	*/
1637	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1638	{
1639	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1640	return &g_HvmR0.aCpuInfo[idCpu];
1641	}
1642
1643
1644	/**
1645	* Save a pending IO read.
1646	*
1647	* @param pVCpu Pointer to the VMCPU.
1648	* @param GCPtrRip Address of IO instruction.
1649	* @param GCPtrRipNext Address of the next instruction.
1650	* @param uPort Port address.
1651	* @param uAndVal AND mask for saving the result in eax.
1652	* @param cbSize Read size.
1653	*/
1654	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1655	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1656	{
1657	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1658	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1659	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1660	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1661	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1662	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1663	return;
1664	}
1665
1666
1667	/**
1668	* Save a pending IO write.
1669	*
1670	* @param pVCpu Pointer to the VMCPU.
1671	* @param GCPtrRIP Address of IO instruction.
1672	* @param uPort Port address.
1673	* @param uAndVal AND mask for fetching the result from eax.
1674	* @param cbSize Read size.
1675	*/
1676	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1677	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1678	{
1679	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1680	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1681	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1682	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1683	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1684	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1685	return;
1686	}
1687
1688
1689	/**
1690	* Raw-mode switcher hook - disable VT-x if it's active and the current
1691	* switcher turns off paging.
1692	*
1693	* @returns VBox status code.
1694	* @param pVM Pointer to the VM.
1695	* @param enmSwitcher The switcher we're about to use.
1696	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1697	*/
1698	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1699	{
1700	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1701
1702	*pfVTxDisabled = false;
1703
1704	/* No such issues with AMD-V */
1705	if (!g_HvmR0.vmx.fSupported)
1706	return VINF_SUCCESS;
1707
1708	/* Check if the swithcing we're up to is safe. */
1709	switch (enmSwitcher)
1710	{
1711	case VMMSWITCHER_32_TO_32:
1712	case VMMSWITCHER_PAE_TO_PAE:
1713	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1714
1715	case VMMSWITCHER_32_TO_PAE:
1716	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1717	case VMMSWITCHER_AMD64_TO_32:
1718	case VMMSWITCHER_AMD64_TO_PAE:
1719	break; /* unsafe switchers */
1720
1721	default:
1722	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1723	}
1724
1725	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1726	regardless of whether we're currently using VT-x or not. */
1727	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1728	{
1729	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1730	return VINF_SUCCESS;
1731	}
1732
1733	/** @todo Check if this code is presumtive wrt other VT-x users on the
1734	* system... */
1735
1736	/* Nothing to do if we haven't enabled VT-x. */
1737	if (!g_HvmR0.fEnabled)
1738	return VINF_SUCCESS;
1739
1740	/* Local init implies the CPU is currently not in VMX root mode. */
1741	if (!g_HvmR0.fGlobalInit)
1742	return VINF_SUCCESS;
1743
1744	/* Ok, disable VT-x. */
1745	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1746	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1747
1748	*pfVTxDisabled = true;
1749	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1750	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1751	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1752	}
1753
1754
1755	/**
1756	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1757	* switcher turned off paging.
1758	*
1759	* @param pVM Pointer to the VM.
1760	* @param fVTxDisabled Whether VT-x was disabled or not.
1761	*/
1762	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1763	{
1764	Assert(!(ASMGetFlags() & X86_EFL_IF));
1765
1766	if (!fVTxDisabled)
1767	return; /* nothing to do */
1768
1769	Assert(g_HvmR0.vmx.fSupported);
1770	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1771	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1772	else
1773	{
1774	Assert(g_HvmR0.fEnabled);
1775	Assert(g_HvmR0.fGlobalInit);
1776
1777	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1778	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1779
1780	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1781	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1782	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
1783	}
1784	}
1785
1786	#ifdef VBOX_STRICT
1787
1788	/**
1789	* Dumps a descriptor.
1790	*
1791	* @param pDesc Descriptor to dump.
1792	* @param Sel Selector number.
1793	* @param pszMsg Message to prepend the log entry with.
1794	*/
1795	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1796	{
1797	/*
1798	* Make variable description string.
1799	*/
1800	static struct
1801	{
1802	unsigned cch;
1803	const char *psz;
1804	} const s_aTypes[32] =
1805	{
1806	# define STRENTRY(str) { sizeof(str) - 1, str }
1807
1808	/* system */
1809	# if HC_ARCH_BITS == 64
1810	STRENTRY("Reserved0 "), /* 0x00 */
1811	STRENTRY("Reserved1 "), /* 0x01 */
1812	STRENTRY("LDT "), /* 0x02 */
1813	STRENTRY("Reserved3 "), /* 0x03 */
1814	STRENTRY("Reserved4 "), /* 0x04 */
1815	STRENTRY("Reserved5 "), /* 0x05 */
1816	STRENTRY("Reserved6 "), /* 0x06 */
1817	STRENTRY("Reserved7 "), /* 0x07 */
1818	STRENTRY("Reserved8 "), /* 0x08 */
1819	STRENTRY("TSS64Avail "), /* 0x09 */
1820	STRENTRY("ReservedA "), /* 0x0a */
1821	STRENTRY("TSS64Busy "), /* 0x0b */
1822	STRENTRY("Call64 "), /* 0x0c */
1823	STRENTRY("ReservedD "), /* 0x0d */
1824	STRENTRY("Int64 "), /* 0x0e */
1825	STRENTRY("Trap64 "), /* 0x0f */
1826	# else
1827	STRENTRY("Reserved0 "), /* 0x00 */
1828	STRENTRY("TSS16Avail "), /* 0x01 */
1829	STRENTRY("LDT "), /* 0x02 */
1830	STRENTRY("TSS16Busy "), /* 0x03 */
1831	STRENTRY("Call16 "), /* 0x04 */
1832	STRENTRY("Task "), /* 0x05 */
1833	STRENTRY("Int16 "), /* 0x06 */
1834	STRENTRY("Trap16 "), /* 0x07 */
1835	STRENTRY("Reserved8 "), /* 0x08 */
1836	STRENTRY("TSS32Avail "), /* 0x09 */
1837	STRENTRY("ReservedA "), /* 0x0a */
1838	STRENTRY("TSS32Busy "), /* 0x0b */
1839	STRENTRY("Call32 "), /* 0x0c */
1840	STRENTRY("ReservedD "), /* 0x0d */
1841	STRENTRY("Int32 "), /* 0x0e */
1842	STRENTRY("Trap32 "), /* 0x0f */
1843	# endif
1844	/* non system */
1845	STRENTRY("DataRO "), /* 0x10 */
1846	STRENTRY("DataRO Accessed "), /* 0x11 */
1847	STRENTRY("DataRW "), /* 0x12 */
1848	STRENTRY("DataRW Accessed "), /* 0x13 */
1849	STRENTRY("DataDownRO "), /* 0x14 */
1850	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1851	STRENTRY("DataDownRW "), /* 0x16 */
1852	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1853	STRENTRY("CodeEO "), /* 0x18 */
1854	STRENTRY("CodeEO Accessed "), /* 0x19 */
1855	STRENTRY("CodeER "), /* 0x1a */
1856	STRENTRY("CodeER Accessed "), /* 0x1b */
1857	STRENTRY("CodeConfEO "), /* 0x1c */
1858	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1859	STRENTRY("CodeConfER "), /* 0x1e */
1860	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1861	# undef SYSENTRY
1862	};
1863	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1864	char szMsg[128];
1865	char *psz = &szMsg[0];
1866	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1867	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1868	psz += s_aTypes[i].cch;
1869
1870	if (pDesc->Gen.u1Present)
1871	ADD_STR(psz, "Present ");
1872	else
1873	ADD_STR(psz, "Not-Present ");
1874	# if HC_ARCH_BITS == 64
1875	if (pDesc->Gen.u1Long)
1876	ADD_STR(psz, "64-bit ");
1877	else
1878	ADD_STR(psz, "Comp ");
1879	# else
1880	if (pDesc->Gen.u1Granularity)
1881	ADD_STR(psz, "Page ");
1882	if (pDesc->Gen.u1DefBig)
1883	ADD_STR(psz, "32-bit ");
1884	else
1885	ADD_STR(psz, "16-bit ");
1886	# endif
1887	# undef ADD_STR
1888	*psz = '\0';
1889
1890	/*
1891	* Limit and Base and format the output.
1892	*/
1893	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1894
1895	# if HC_ARCH_BITS == 64
1896	uint64_t u32Base = X86DESC64_BASE(pDesc);
1897
1898	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1899	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1900	# else
1901	uint32_t u32Base = X86DESC_BASE(pDesc);
1902
1903	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1904	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1905	# endif
1906	}
1907
1908
1909	/**
1910	* Formats a full register dump.
1911	*
1912	* @param pVM Pointer to the VM.
1913	* @param pVCpu Pointer to the VMCPU.
1914	* @param pCtx Pointer to the CPU context.
1915	*/
1916	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1917	{
1918	NOREF(pVM);
1919
1920	/*
1921	* Format the flags.
1922	*/
1923	static struct
1924	{
1925	const char pszSet; const char pszClear; uint32_t fFlag;
1926	} const s_aFlags[] =
1927	{
1928	{ "vip",NULL, X86_EFL_VIP },
1929	{ "vif",NULL, X86_EFL_VIF },
1930	{ "ac", NULL, X86_EFL_AC },
1931	{ "vm", NULL, X86_EFL_VM },
1932	{ "rf", NULL, X86_EFL_RF },
1933	{ "nt", NULL, X86_EFL_NT },
1934	{ "ov", "nv", X86_EFL_OF },
1935	{ "dn", "up", X86_EFL_DF },
1936	{ "ei", "di", X86_EFL_IF },
1937	{ "tf", NULL, X86_EFL_TF },
1938	{ "nt", "pl", X86_EFL_SF },
1939	{ "nz", "zr", X86_EFL_ZF },
1940	{ "ac", "na", X86_EFL_AF },
1941	{ "po", "pe", X86_EFL_PF },
1942	{ "cy", "nc", X86_EFL_CF },
1943	};
1944	char szEFlags[80];
1945	char *psz = szEFlags;
1946	uint32_t efl = pCtx->eflags.u32;
1947	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1948	{
1949	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1950	if (pszAdd)
1951	{
1952	strcpy(psz, pszAdd);
1953	psz += strlen(pszAdd);
1954	*psz++ = ' ';
1955	}
1956	}
1957	psz[-1] = '\0';
1958
1959
1960	/*
1961	* Format the registers.
1962	*/
1963	if (CPUMIsGuestIn64BitCode(pVCpu))
1964	{
1965	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1966	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1967	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1968	"r14=%016RX64 r15=%016RX64\n"
1969	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1970	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1971	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1972	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1973	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1974	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1975	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1976	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1977	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1978	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1979	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1980	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1981	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1982	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1983	,
1984	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1985	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1986	pCtx->r14, pCtx->r15,
1987	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1988	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1989	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1990	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1991	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1992	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1993	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1994	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1995	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1996	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1997	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1998	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1999	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2000	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2001	}
2002	else
2003	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2004	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2005	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2006	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2007	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2008	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2009	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2010	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2011	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2012	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2013	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2014	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2015	,
2016	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2017	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2018	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2019	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2020	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2021	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2022	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2023	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2024	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2025	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2026	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2027	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2028
2029	Log(("FPU:\n"
2030	"FCW=%04x FSW=%04x FTW=%02x\n"
2031	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2032	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2033	,
2034	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2035	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2036	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2037	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2038
2039
2040	Log(("MSR:\n"
2041	"EFER =%016RX64\n"
2042	"PAT =%016RX64\n"
2043	"STAR =%016RX64\n"
2044	"CSTAR =%016RX64\n"
2045	"LSTAR =%016RX64\n"
2046	"SFMASK =%016RX64\n"
2047	"KERNELGSBASE =%016RX64\n",
2048	pCtx->msrEFER,
2049	pCtx->msrPAT,
2050	pCtx->msrSTAR,
2051	pCtx->msrCSTAR,
2052	pCtx->msrLSTAR,
2053	pCtx->msrSFMASK,
2054	pCtx->msrKERNELGSBASE));
2055
2056	}
2057
2058	#endif /* VBOX_STRICT */
2059

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 48402

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