HMR0.cpp@ 49407

Last change on this file since 49407 was 49310, checked in by vboxsync, 11 years ago
HMR0.cpp: Ignore VERR_SVM_DISABLED an VERR_SVM_IN_USE status codes during module load. Old problem exposed by r86045.
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File size: 72.2 KB

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1	/* $Id: HMR0.cpp 49310 2013-10-28 15:58:48Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost, void *pvArg));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	/** @todo This isn't used for anything relevant. Remove later? */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** VMX MSR values */
123	VMXMSRS Msrs;
124
125	/* Last instruction error */
126	uint32_t ulLastInstrError;
127	} vmx;
128
129	/** AMD-V information. */
130	struct
131	{
132	/* HWCR MSR (for diagnostics) */
133	uint64_t u64MsrHwcr;
134
135	/** SVM revision. */
136	uint32_t u32Rev;
137
138	/** SVM feature bits from cpuid 0x8000000a */
139	uint32_t u32Features;
140
141	/** Set by us to indicate SVM is supported by the CPU. */
142	bool fSupported;
143	} svm;
144	/** Saved error from detection */
145	int32_t lLastError;
146
147	struct
148	{
149	uint32_t u32AMDFeatureECX;
150	uint32_t u32AMDFeatureEDX;
151	} cpuid;
152
153	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
154	* enabled and disabled each time it's used to execute guest code. */
155	bool fGlobalInit;
156	/** Indicates whether the host is suspending or not. We'll refuse a few
157	* actions when the host is being suspended to speed up the suspending and
158	* avoid trouble. */
159	volatile bool fSuspended;
160
161	/** Whether we've already initialized all CPUs.
162	* @remarks We could check the EnableAllCpusOnce state, but this is
163	* simpler and hopefully easier to understand. */
164	bool fEnabled;
165	/** Serialize initialization in HMR0EnableAllCpus. */
166	RTONCE EnableAllCpusOnce;
167	} g_HvmR0;
168
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	/**
212	* Get the CPU ID on which the failure status code was reported.
213	*
214	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
215	* @param pFirstRc The first return code structure.
216	*/
217	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
218	{
219	return pFirstRc->idCpu;
220	}
221	#endif /* VBOX_STRICT */
222
223
224	/** @name Dummy callback handlers.
225	* @{ */
226
227	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
228	{
229	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
234	{
235	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
236	return VINF_SUCCESS;
237	}
238
239	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
240	{
241	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
242	}
243
244	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
245	bool fEnabledBySystem, void *pvArg)
246	{
247	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
252	{
253	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
254	return VINF_SUCCESS;
255	}
256
257	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
258	{
259	NOREF(pVM);
260	return VINF_SUCCESS;
261	}
262
263	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
264	{
265	NOREF(pVM);
266	return VINF_SUCCESS;
267	}
268
269	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
270	{
271	NOREF(pVM);
272	return VINF_SUCCESS;
273	}
274
275	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
276	{
277	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
278	return VINF_SUCCESS;
279	}
280
281	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
282	{
283	NOREF(pVM); NOREF(pVCpu);
284	return VINF_SUCCESS;
285	}
286
287	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
288	{
289	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
290	return VINF_SUCCESS;
291	}
292
293	/** @} */
294
295
296	/**
297	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
298	* Down at the Rate Specified" erratum.
299	*
300	* Errata names and related steppings:
301	* - BA86 - D0.
302	* - AAX65 - C2.
303	* - AAU65 - C2, K0.
304	* - AAO95 - B1.
305	* - AAT59 - C2.
306	* - AAK139 - D0.
307	* - AAM126 - C0, C1, D0.
308	* - AAN92 - B1.
309	* - AAJ124 - C0, D0.
310	*
311	* - AAP86 - B1.
312	*
313	* Steppings: B1, C0, C1, C2, D0, K0.
314	*
315	* @returns true if subject to it, false if not.
316	*/
317	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
318	{
319	uint32_t u = ASMCpuId_EAX(1);
320	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
321	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
322	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
323	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
324	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
325	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
326	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
327	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
328	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
329	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
330	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
331	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
332	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
333	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
334	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
335	)
336	return true;
337	return false;
338	}
339
340
341	/**
342	* Intel specific initialization code.
343	*
344	* @returns VBox status code (will only fail if out of memory).
345	*/
346	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
347	{
348	/*
349	* Check that all the required VT-x features are present.
350	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
351	*/
352	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
353	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
354	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
355	)
356	{
357	/** @todo move this into a separate function. */
358	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
359
360	/*
361	* First try use native kernel API for controlling VT-x.
362	* (This is only supported by some Mac OS X kernels atm.)
363	*/
364	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
365	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
366	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
367	{
368	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
369	if (RT_SUCCESS(rc))
370	{
371	g_HvmR0.vmx.fSupported = true;
372	rc = SUPR0EnableVTx(false /* fEnable */);
373	AssertLogRelRC(rc);
374	}
375	}
376	else
377	{
378	/* We need to check if VT-x has been properly initialized on all
379	CPUs. Some BIOSes do a lousy job. */
380	HMR0FIRSTRC FirstRc;
381	hmR0FirstRcInit(&FirstRc);
382	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
383	if (RT_SUCCESS(g_HvmR0.lLastError))
384	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
385	}
386	if (RT_SUCCESS(g_HvmR0.lLastError))
387	{
388	/* Reread in case it was changed by hmR0InitIntelCpu(). */
389	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
390
391	/*
392	* Read all relevant registers and MSRs.
393	*/
394	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
395	g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
396	g_HvmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
397	g_HvmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
398	g_HvmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
399	g_HvmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
400	g_HvmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
401	g_HvmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
402	g_HvmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
403	g_HvmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
404	g_HvmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
405	g_HvmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
406	g_HvmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
407	/* VPID 16 bits ASID. */
408	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
409
410	if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
411	{
412	g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
413	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
414	g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
415
416	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
417	g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
418	}
419
420	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
421	{
422	/*
423	* Enter root mode
424	*/
425	RTR0MEMOBJ hScatchMemObj;
426	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
427	if (RT_FAILURE(rc))
428	{
429	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
430	return rc;
431	}
432
433	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
434	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
435	ASMMemZeroPage(pvScatchPage);
436
437	/* Set revision dword at the beginning of the structure. */
438	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo);
439
440	/* Make sure we don't get rescheduled to another cpu during this probe. */
441	RTCCUINTREG fFlags = ASMIntDisableFlags();
442
443	/*
444	* Check CR4.VMXE
445	*/
446	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
447	if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
448	{
449	/* In theory this bit could be cleared behind our back. Which would cause
450	#UD faults when we try to execute the VMX instructions... */
451	ASMSetCR4(g_HvmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
452	}
453
454	/*
455	* The only way of checking if we're in VMX root mode or not is to try and enter it.
456	* There is no instruction or control bit that tells us if we're in VMX root mode.
457	* Therefore, try and enter VMX root mode here.
458	*/
459	rc = VMXEnable(HCPhysScratchPage);
460	if (RT_SUCCESS(rc))
461	{
462	g_HvmR0.vmx.fSupported = true;
463	VMXDisable();
464	}
465	else
466	{
467	/*
468	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
469	* it will crash the host when we enter raw mode, because:
470	*
471	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
472	* this bit), and
473	* (b) turning off paging causes a #GP (unavoidable when switching
474	* from long to 32 bits mode or 32 bits to PAE).
475	*
476	* They should fix their code, but until they do we simply refuse to run.
477	*/
478	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
479	Assert(g_HvmR0.vmx.fSupported == false);
480	}
481
482	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
483	if it wasn't so before (some software could incorrectly
484	think it's in VMX mode). */
485	ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
486	ASMSetFlags(fFlags);
487
488	RTR0MemObjFree(hScatchMemObj, false);
489	}
490
491	if (g_HvmR0.vmx.fSupported)
492	{
493	rc = VMXR0GlobalInit();
494	if (RT_FAILURE(rc))
495	g_HvmR0.lLastError = rc;
496
497	/*
498	* Install the VT-x methods.
499	*/
500	g_HvmR0.pfnEnterSession = VMXR0Enter;
501	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
502	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
503	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
504	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
505	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
506	g_HvmR0.pfnInitVM = VMXR0InitVM;
507	g_HvmR0.pfnTermVM = VMXR0TermVM;
508	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
509
510	/*
511	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
512	* Timer Does Not Count Down at the Rate Specified" erratum.
513	*/
514	if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
515	{
516	g_HvmR0.vmx.fUsePreemptTimer = true;
517	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc);
518	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
519	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
520	}
521	}
522	}
523	#ifdef LOG_ENABLED
524	else
525	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
526	#endif
527	}
528	else
529	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
530	return VINF_SUCCESS;
531	}
532
533
534	/**
535	* AMD-specific initialization code.
536	*
537	* @returns VBox status code.
538	*/
539	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
540	{
541	/*
542	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
543	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
544	*/
545	int rc;
546	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
547	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
548	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
549	&& ASMIsValidExtRange(uMaxExtLeaf)
550	&& uMaxExtLeaf >= 0x8000000a
551	)
552	{
553	/* Call the global AMD-V initialization routine. */
554	rc = SVMR0GlobalInit();
555	if (RT_FAILURE(rc))
556	{
557	g_HvmR0.lLastError = rc;
558	return rc;
559	}
560
561	/*
562	* Install the AMD-V methods.
563	*/
564	g_HvmR0.pfnEnterSession = SVMR0Enter;
565	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
566	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
567	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
568	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
569	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
570	g_HvmR0.pfnInitVM = SVMR0InitVM;
571	g_HvmR0.pfnTermVM = SVMR0TermVM;
572	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
573
574	/* Query AMD features. */
575	uint32_t u32Dummy;
576	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
577
578	/*
579	* We need to check if AMD-V has been properly initialized on all CPUs.
580	* Some BIOSes might do a poor job.
581	*/
582	HMR0FIRSTRC FirstRc;
583	hmR0FirstRcInit(&FirstRc);
584	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
585	AssertRC(rc);
586	if (RT_SUCCESS(rc))
587	rc = hmR0FirstRcGetStatus(&FirstRc);
588	#ifndef DEBUG_bird
589	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
590	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
591	#endif
592	if (RT_SUCCESS(rc))
593	{
594	/* Read the HWCR MSR for diagnostics. */
595	g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
596	g_HvmR0.svm.fSupported = true;
597	}
598	else
599	{
600	g_HvmR0.lLastError = rc;
601	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
602	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
603	}
604	}
605	else
606	{
607	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
608	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
609	}
610	return rc;
611	}
612
613
614	/**
615	* Does global Ring-0 HM initialization (at module init).
616	*
617	* @returns VBox status code.
618	*/
619	VMMR0_INT_DECL(int) HMR0Init(void)
620	{
621	/*
622	* Initialize the globals.
623	*/
624	g_HvmR0.fEnabled = false;
625	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
626	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
627	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
628	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
629
630	/* Fill in all callbacks with placeholders. */
631	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
632	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
633	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
634	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
635	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
636	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
637	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
638	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
639	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
640
641	/* Default is global VT-x/AMD-V init. */
642	g_HvmR0.fGlobalInit = true;
643
644	/*
645	* Make sure aCpuInfo is big enough for all the CPUs on this system.
646	*/
647	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
648	{
649	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
650	return VERR_TOO_MANY_CPUS;
651	}
652
653	/*
654	* Check for VT-x and AMD-V capabilities.
655	*/
656	int rc;
657	if (ASMHasCpuId())
658	{
659	/* Standard features. */
660	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
661	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
662	if (ASMIsValidStdRange(uMaxLeaf))
663	{
664	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
665	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
666
667	/* Query AMD features. */
668	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
669	if (ASMIsValidExtRange(uMaxExtLeaf))
670	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
671	&g_HvmR0.cpuid.u32AMDFeatureECX,
672	&g_HvmR0.cpuid.u32AMDFeatureEDX);
673	else
674	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
675
676	/* Go to CPU specific initialization code. */
677	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
678	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
679	{
680	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
681	if (RT_FAILURE(rc))
682	return rc;
683	}
684	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
685	{
686	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
687	if (RT_FAILURE(rc))
688	return rc;
689	}
690	else
691	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
692	}
693	else
694	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
695	}
696	else
697	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
698
699	/*
700	* Register notification callbacks that we can use to disable/enable CPUs
701	* when brought offline/online or suspending/resuming.
702	*/
703	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
704	{
705	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
706	AssertRC(rc);
707
708	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
709	AssertRC(rc);
710	}
711
712	/* We return success here because module init shall not fail if HM
713	fails to initialize. */
714	return VINF_SUCCESS;
715	}
716
717
718	/**
719	* Does global Ring-0 HM termination (at module termination).
720	*
721	* @returns VBox status code.
722	*/
723	VMMR0_INT_DECL(int) HMR0Term(void)
724	{
725	int rc;
726	if ( g_HvmR0.vmx.fSupported
727	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
728	{
729	/*
730	* Simple if the host OS manages VT-x.
731	*/
732	Assert(g_HvmR0.fGlobalInit);
733	rc = SUPR0EnableVTx(false /* fEnable */);
734
735	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
736	{
737	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
738	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
739	}
740	}
741	else
742	{
743	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
744	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
745	{
746	/* Doesn't really matter if this fails. */
747	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
748	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
749	}
750	else
751	rc = VINF_SUCCESS;
752
753	/*
754	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
755	*/
756	if (g_HvmR0.fGlobalInit)
757	{
758	HMR0FIRSTRC FirstRc;
759	hmR0FirstRcInit(&FirstRc);
760	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
761	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
762	if (RT_SUCCESS(rc))
763	{
764	rc = hmR0FirstRcGetStatus(&FirstRc);
765	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
766	}
767	}
768
769	/*
770	* Free the per-cpu pages used for VT-x and AMD-V.
771	*/
772	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
773	{
774	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
775	{
776	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
777	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
778	}
779	}
780	}
781
782	/** @todo This needs cleaning up. There's no matching
783	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
784	* should move into their respective modules. */
785	/* Finally, call global VT-x/AMD-V termination. */
786	if (g_HvmR0.vmx.fSupported)
787	VMXR0GlobalTerm();
788	else if (g_HvmR0.svm.fSupported)
789	SVMR0GlobalTerm();
790
791	return rc;
792	}
793
794
795	/**
796	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
797	* on a CPU.
798	*
799	* @param idCpu The identifier for the CPU the function is called on.
800	* @param pvUser1 Pointer to the first RC structure.
801	* @param pvUser2 Ignored.
802	*/
803	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
804	{
805	/** @todo Unify code with SUPR0QueryVTCaps(). */
806	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
807	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
808	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
809	NOREF(pvUser2);
810
811	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
812	bool const fInSmxMode = RT_BOOL(ASMGetCR4() & X86_CR4_SMXE);
813	bool fMsrLocked = RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_LOCK);
814	bool fSmxVmxAllowed = RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
815	bool fVmxAllowed = RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_VMXON);
816
817	/* Check if the LOCK bit is set but excludes the required VMXON bit. */
818	int rc = VERR_HM_IPE_1;
819	if (fMsrLocked)
820	{
821	if (fInSmxMode && !fSmxVmxAllowed)
822	rc = VERR_VMX_MSR_SMX_VMXON_DISABLED;
823	else if (!fVmxAllowed)
824	rc = VERR_VMX_MSR_VMXON_DISABLED;
825	else
826	rc = VINF_SUCCESS;
827	}
828	else
829	{
830	/*
831	* MSR is not yet locked; we can change it ourselves here.
832	* Once the lock bit is set, this MSR can no longer be modified.
833	*/
834	fFC \|= MSR_IA32_FEATURE_CONTROL_LOCK;
835	if (fInSmxMode)
836	fFC \|= MSR_IA32_FEATURE_CONTROL_SMX_VMXON;
837	else
838	fFC \|= MSR_IA32_FEATURE_CONTROL_VMXON;
839
840	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, fFC);
841
842	/* Verify. */
843	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
844	fMsrLocked = RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_LOCK);
845	fSmxVmxAllowed = fMsrLocked && RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
846	fVmxAllowed = fMsrLocked && RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_VMXON);
847	bool const fAllowed = fInSmxMode ? fSmxVmxAllowed : fVmxAllowed;
848	if (fAllowed)
849	rc = VINF_SUCCESS;
850	else
851	rc = VERR_VMX_MSR_LOCKING_FAILED;
852	}
853
854	hmR0FirstRcSetStatus(pFirstRc, rc);
855	}
856
857
858	/**
859	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
860	* on a CPU.
861	*
862	* @param idCpu The identifier for the CPU the function is called on.
863	* @param pvUser1 Pointer to the first RC structure.
864	* @param pvUser2 Ignored.
865	*/
866	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
867	{
868	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
869	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
870	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
871	NOREF(pvUser2);
872
873	/* Check if SVM is disabled. */
874	int rc;
875	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
876	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
877	{
878	/* Turn on SVM in the EFER MSR. */
879	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
880	if (fEfer & MSR_K6_EFER_SVME)
881	rc = VERR_SVM_IN_USE;
882	else
883	{
884	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
885
886	/* Paranoia. */
887	fEfer = ASMRdMsr(MSR_K6_EFER);
888	if (fEfer & MSR_K6_EFER_SVME)
889	{
890	/* Restore previous value. */
891	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
892	rc = VINF_SUCCESS;
893	}
894	else
895	rc = VERR_SVM_ILLEGAL_EFER_MSR;
896	}
897	}
898	else
899	rc = VERR_SVM_DISABLED;
900
901	hmR0FirstRcSetStatus(pFirstRc, rc);
902	}
903
904
905	/**
906	* Enable VT-x or AMD-V on the current CPU
907	*
908	* @returns VBox status code.
909	* @param pVM Pointer to the VM (can be NULL).
910	* @param idCpu The identifier for the CPU the function is called on.
911	*
912	* @remarks Maybe called with interrupts disabled!
913	*/
914	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
915	{
916	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
917
918	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
919	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
920	Assert(!pCpu->fConfigured);
921
922	pCpu->idCpu = idCpu;
923	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
924	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
925
926	int rc;
927	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
928	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HvmR0.vmx.Msrs);
929	else
930	{
931	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
932	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
933	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
934
935	if (g_HvmR0.vmx.fSupported)
936	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
937	else
938	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
939	}
940	AssertRC(rc);
941	if (RT_SUCCESS(rc))
942	pCpu->fConfigured = true;
943
944	return rc;
945	}
946
947
948	/**
949	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
950	*
951	* @param idCpu The identifier for the CPU the function is called on.
952	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
953	* @param pvUser2 The 2nd user argument.
954	*/
955	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
956	{
957	PVM pVM = (PVM)pvUser1; /* can be NULL! */
958	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
959	AssertReturnVoid(g_HvmR0.fGlobalInit);
960	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
961	}
962
963
964	/**
965	* RTOnce callback employed by HMR0EnableAllCpus.
966	*
967	* @returns VBox status code.
968	* @param pvUser Pointer to the VM.
969	* @param pvUserIgnore NULL, ignored.
970	*/
971	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
972	{
973	PVM pVM = (PVM)pvUser;
974
975	/*
976	* Indicate that we've initialized.
977	*
978	* Note! There is a potential race between this function and the suspend
979	* notification. Kind of unlikely though, so ignored for now.
980	*/
981	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
982	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
983
984	/*
985	* The global init variable is set by the first VM.
986	*/
987	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
988
989	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
990	{
991	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
992	g_HvmR0.aCpuInfo[i].fConfigured = false;
993	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
994	g_HvmR0.aCpuInfo[i].uCurrentAsid = 0;
995	}
996
997	int rc;
998	if ( g_HvmR0.vmx.fSupported
999	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1000	{
1001	/*
1002	* Global VT-x initialization API (only darwin for now).
1003	*/
1004	rc = SUPR0EnableVTx(true /* fEnable */);
1005	if (RT_SUCCESS(rc))
1006	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
1007	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
1008	else
1009	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
1010	}
1011	else
1012	{
1013	/*
1014	* We're doing the job ourselves.
1015	*/
1016	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
1017	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1018	{
1019	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1020
1021	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1022	{
1023	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1024	AssertLogRelRCReturn(rc, rc);
1025
1026	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1027	ASMMemZeroPage(pvR0);
1028	}
1029	}
1030
1031	rc = VINF_SUCCESS;
1032	}
1033
1034	if ( RT_SUCCESS(rc)
1035	&& g_HvmR0.fGlobalInit)
1036	{
1037	/* First time, so initialize each cpu/core. */
1038	HMR0FIRSTRC FirstRc;
1039	hmR0FirstRcInit(&FirstRc);
1040	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1041	if (RT_SUCCESS(rc))
1042	rc = hmR0FirstRcGetStatus(&FirstRc);
1043	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1044	}
1045
1046	return rc;
1047	}
1048
1049
1050	/**
1051	* Sets up HM on all cpus.
1052	*
1053	* @returns VBox status code.
1054	* @param pVM Pointer to the VM.
1055	*/
1056	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1057	{
1058	/* Make sure we don't touch HM after we've disabled HM in
1059	preparation of a suspend. */
1060	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1061	return VERR_HM_SUSPEND_PENDING;
1062
1063	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1064	}
1065
1066
1067	/**
1068	* Disable VT-x or AMD-V on the current CPU.
1069	*
1070	* @returns VBox status code.
1071	* @param idCpu The identifier for the CPU the function is called on.
1072	*
1073	* @remarks Must be called with preemption disabled.
1074	*/
1075	static int hmR0DisableCpu(RTCPUID idCpu)
1076	{
1077	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1078
1079	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1080	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1081	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1082	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1083	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1084
1085	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1086	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1087
1088	int rc;
1089	if (pCpu->fConfigured)
1090	{
1091	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1092	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1093
1094	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1095	AssertRCReturn(rc, rc);
1096
1097	pCpu->fConfigured = false;
1098	}
1099	else
1100	rc = VINF_SUCCESS; /* nothing to do */
1101
1102	pCpu->uCurrentAsid = 0;
1103	return rc;
1104	}
1105
1106
1107	/**
1108	* Worker function passed to RTMpOnAll() that is to be called on the target
1109	* CPUs.
1110	*
1111	* @param idCpu The identifier for the CPU the function is called on.
1112	* @param pvUser1 The 1st user argument.
1113	* @param pvUser2 Opaque pointer to the FirstRc.
1114	*/
1115	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1116	{
1117	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1118	AssertReturnVoid(g_HvmR0.fGlobalInit);
1119	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1120	}
1121
1122
1123	/**
1124	* Callback function invoked when a cpu goes online or offline.
1125	*
1126	* @param enmEvent The Mp event.
1127	* @param idCpu The identifier for the CPU the function is called on.
1128	* @param pvData Opaque data (PVM pointer).
1129	*/
1130	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1131	{
1132	NOREF(pvData);
1133
1134	/*
1135	* We only care about uninitializing a CPU that is going offline. When a
1136	* CPU comes online, the initialization is done lazily in HMR0Enter().
1137	*/
1138	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1139	switch (enmEvent)
1140	{
1141	case RTMPEVENT_OFFLINE:
1142	{
1143	int rc = hmR0DisableCpu(idCpu);
1144	AssertRC(rc);
1145	break;
1146	}
1147
1148	default:
1149	break;
1150	}
1151	}
1152
1153
1154	/**
1155	* Called whenever a system power state change occurs.
1156	*
1157	* @param enmEvent The Power event.
1158	* @param pvUser User argument.
1159	*/
1160	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1161	{
1162	NOREF(pvUser);
1163	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1164
1165	#ifdef LOG_ENABLED
1166	if (enmEvent == RTPOWEREVENT_SUSPEND)
1167	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1168	else
1169	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1170	#endif
1171
1172	if (enmEvent == RTPOWEREVENT_SUSPEND)
1173	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1174
1175	if (g_HvmR0.fEnabled)
1176	{
1177	int rc;
1178	HMR0FIRSTRC FirstRc;
1179	hmR0FirstRcInit(&FirstRc);
1180
1181	if (enmEvent == RTPOWEREVENT_SUSPEND)
1182	{
1183	if (g_HvmR0.fGlobalInit)
1184	{
1185	/* Turn off VT-x or AMD-V on all CPUs. */
1186	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1187	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1188	}
1189	/* else nothing to do here for the local init case */
1190	}
1191	else
1192	{
1193	/* Reinit the CPUs from scratch as the suspend state might have
1194	messed with the MSRs. (lousy BIOSes as usual) */
1195	if (g_HvmR0.vmx.fSupported)
1196	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1197	else
1198	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1199	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1200	if (RT_SUCCESS(rc))
1201	rc = hmR0FirstRcGetStatus(&FirstRc);
1202	#ifdef LOG_ENABLED
1203	if (RT_FAILURE(rc))
1204	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1205	#endif
1206	if (g_HvmR0.fGlobalInit)
1207	{
1208	/* Turn VT-x or AMD-V back on on all CPUs. */
1209	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1210	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1211	}
1212	/* else nothing to do here for the local init case */
1213	}
1214	}
1215
1216	if (enmEvent == RTPOWEREVENT_RESUME)
1217	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1218	}
1219
1220
1221	/**
1222	* Does Ring-0 per VM HM initialization.
1223	*
1224	* This will copy HM global into the VM structure and call the CPU specific
1225	* init routine which will allocate resources for each virtual CPU and such.
1226	*
1227	* @returns VBox status code.
1228	* @param pVM Pointer to the VM.
1229	*/
1230	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1231	{
1232	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1233
1234	#ifdef LOG_ENABLED
1235	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1236	#endif
1237
1238	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1239	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1240	return VERR_HM_SUSPEND_PENDING;
1241
1242	/*
1243	* Copy globals to the VM structure.
1244	*/
1245	/** @todo r=ramshankar: Why do we do this for MSRs? We never change them in the
1246	* per-VM structures anyway... */
1247	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1248	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1249
1250	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1251	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1252	pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4;
1253	pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer;
1254	pVM->hm.s.vmx.Msrs = g_HvmR0.vmx.Msrs;
1255	pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr;
1256	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1257	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1258	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1259	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1260	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1261
1262	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1263
1264
1265	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1266	{
1267	pVM->hm.s.cMaxResumeLoops = 1024;
1268	if (RTThreadPreemptIsPendingTrusty())
1269	pVM->hm.s.cMaxResumeLoops = 8192;
1270	}
1271
1272	/*
1273	* Initialize some per CPU fields.
1274	*/
1275	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1276	{
1277	PVMCPU pVCpu = &pVM->aCpus[i];
1278
1279	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1280
1281	/* Invalidate the last cpu we were running on. */
1282	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1283
1284	/* We'll aways increment this the first time (host uses ASID 0) */
1285	pVCpu->hm.s.uCurrentAsid = 0;
1286	}
1287
1288	/*
1289	* Call the hardware specific initialization method.
1290	*/
1291	return g_HvmR0.pfnInitVM(pVM);
1292	}
1293
1294
1295	/**
1296	* Does Ring-0 per VM HM termination.
1297	*
1298	* @returns VBox status code.
1299	* @param pVM Pointer to the VM.
1300	*/
1301	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1302	{
1303	Log(("HMR0TermVM: %p\n", pVM));
1304	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1305
1306	/*
1307	* Call the hardware specific method.
1308	*
1309	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1310	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1311	*/
1312	return g_HvmR0.pfnTermVM(pVM);
1313	}
1314
1315
1316	/**
1317	* Sets up a VT-x or AMD-V session.
1318	*
1319	* This is mostly about setting up the hardware VM state.
1320	*
1321	* @returns VBox status code.
1322	* @param pVM Pointer to the VM.
1323	*/
1324	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1325	{
1326	Log(("HMR0SetupVM: %p\n", pVM));
1327	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1328
1329	/* Make sure we don't touch HM after we've disabled HM in
1330	preparation of a suspend. */
1331	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1332
1333	/* On first entry we'll sync everything. */
1334	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1335	VMCPU_HMCF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1336
1337	/*
1338	* Call the hardware specific setup VM method. This requires the CPU to be
1339	* enabled for AMD-V/VT-x and preemption to be prevented.
1340	*/
1341	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1342	RTThreadPreemptDisable(&PreemptState);
1343	RTCPUID idCpu = RTMpCpuId();
1344	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1345
1346	/* Enable VT-x or AMD-V if local init is required. */
1347	int rc;
1348	if (!g_HvmR0.fGlobalInit)
1349	{
1350	rc = hmR0EnableCpu(pVM, idCpu);
1351	AssertRCReturnStmt(rc, RTThreadPreemptRestore(&PreemptState), rc);
1352	}
1353
1354	/* Setup VT-x or AMD-V. */
1355	rc = g_HvmR0.pfnSetupVM(pVM);
1356
1357	/* Disable VT-x or AMD-V if local init was done before. */
1358	if (!g_HvmR0.fGlobalInit)
1359	{
1360	int rc2 = hmR0DisableCpu(idCpu);
1361	AssertRC(rc2);
1362	}
1363
1364	RTThreadPreemptRestore(&PreemptState);
1365	return rc;
1366	}
1367
1368
1369	/**
1370	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1371	* required for entering HM context.
1372	*
1373	* @returns VBox status code.
1374	* @param pvCpu Pointer to the VMCPU.
1375	*
1376	* @remarks No-long-jump zone!!!
1377	*/
1378	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1379	{
1380	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1381
1382	int rc = VINF_SUCCESS;
1383	RTCPUID idCpu = RTMpCpuId();
1384	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1385	AssertPtr(pCpu);
1386
1387	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1388	if (!pCpu->fConfigured)
1389	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1390
1391	/* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
1392	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1393	pVCpu->hm.s.idEnteredCpu = idCpu;
1394	return rc;
1395	}
1396
1397
1398	/**
1399	* Enters the VT-x or AMD-V session.
1400	*
1401	* @returns VBox status code.
1402	* @param pVM Pointer to the VM.
1403	* @param pVCpu Pointer to the VMCPU.
1404	*
1405	* @remarks This is called with preemption disabled.
1406	*/
1407	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1408	{
1409	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1410	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1411	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1412
1413	/* Load the bare minimum state required for entering HM. */
1414	int rc = HMR0EnterCpu(pVCpu);
1415	AssertRCReturn(rc, rc);
1416
1417	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1418	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1419	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1420	#endif
1421
1422	RTCPUID idCpu = RTMpCpuId();
1423	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1424	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1425	Assert(pCpu);
1426	Assert(pCtx);
1427	Assert(VMCPU_HMCF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1428
1429	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1430	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1431
1432	/* Load the host as we may be resuming code after a longjmp and quite
1433	possibly now be scheduled on a different CPU. */
1434	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1435	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1436
1437	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1438	if (fStartedSet)
1439	PGMRZDynMapReleaseAutoSet(pVCpu);
1440	#endif
1441
1442	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1443	and ring-3 calls. */
1444	if (RT_FAILURE(rc))
1445	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1446	return rc;
1447	}
1448
1449
1450	/**
1451	* Deinitializes the bare minimum state used for HM context and if necessary
1452	* disable HM on the CPU.
1453	*
1454	* @returns VBox status code.
1455	* @param pVCpu Pointer to the VMCPU.
1456	*
1457	* @remarks No-long-jump zone!!!
1458	*/
1459	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1460	{
1461	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1462
1463	RTCPUID idCpu = RTMpCpuId();
1464	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1465
1466	if ( !g_HvmR0.fGlobalInit
1467	&& pCpu->fConfigured)
1468	{
1469	int rc = hmR0DisableCpu(idCpu);
1470	AssertRCReturn(rc, rc);
1471	Assert(!pCpu->fConfigured);
1472	}
1473
1474	/* Reset these to force a TLB flush for the next entry. */
1475	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1476	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1477	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1478
1479	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1480	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1481
1482	return VINF_SUCCESS;
1483	}
1484
1485
1486	/**
1487	* Thread-context hook for HM.
1488	*
1489	* @param enmEvent The thread-context event.
1490	* @param pvUser Opaque pointer to the VMCPU.
1491	*/
1492	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1493	{
1494	PVMCPU pVCpu = (PVMCPU)pvUser;
1495	Assert(pVCpu);
1496	Assert(g_HvmR0.pfnThreadCtxCallback);
1497
1498	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1499	}
1500
1501
1502	/**
1503	* Runs guest code in a hardware accelerated VM.
1504	*
1505	* @returns VBox status code.
1506	* @param pVM Pointer to the VM.
1507	* @param pVCpu Pointer to the VMCPU.
1508	*
1509	* @remarks Can be called with preemption enabled if thread-context hooks are
1510	* used!!!
1511	*/
1512	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1513	{
1514	#ifdef VBOX_STRICT
1515	/* With thread-context hooks we would be running this code with preemption enabled. */
1516	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1517	{
1518	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1519	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1520	Assert(pCpu->fConfigured);
1521	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1522	}
1523	#endif
1524
1525	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1526	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1527	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1528	PGMRZDynMapStartAutoSet(pVCpu);
1529	#endif
1530
1531	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1532
1533	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1534	PGMRZDynMapReleaseAutoSet(pVCpu);
1535	#endif
1536	return rc;
1537	}
1538
1539	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1540
1541	/**
1542	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1543	*
1544	* @returns VBox status code.
1545	* @param pVM Pointer to the VM.
1546	* @param pVCpu Pointer to the VMCPU.
1547	* @param pCtx Pointer to the guest CPU context.
1548	*/
1549	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1550	{
1551	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1552	if (pVM->hm.s.vmx.fSupported)
1553	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1554	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1555	}
1556
1557
1558	/**
1559	* Save guest debug state (64 bits guest mode & 32 bits host only)
1560	*
1561	* @returns VBox status code.
1562	* @param pVM Pointer to the VM.
1563	* @param pVCpu Pointer to the VMCPU.
1564	* @param pCtx Pointer to the guest CPU context.
1565	*/
1566	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1567	{
1568	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1569	if (pVM->hm.s.vmx.fSupported)
1570	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1571	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1572	}
1573
1574
1575	/**
1576	* Test the 32->64 bits switcher.
1577	*
1578	* @returns VBox status code.
1579	* @param pVM Pointer to the VM.
1580	*/
1581	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1582	{
1583	PVMCPU pVCpu = &pVM->aCpus[0];
1584	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1585	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1586	int rc;
1587
1588	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1589	if (pVM->hm.s.vmx.fSupported)
1590	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1591	else
1592	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1593	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1594
1595	return rc;
1596	}
1597
1598	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1599
1600	/**
1601	* Returns suspend status of the host.
1602	*
1603	* @returns Suspend pending or not.
1604	*/
1605	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1606	{
1607	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1608	}
1609
1610
1611	/**
1612	* Returns the cpu structure for the current cpu.
1613	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1614	*
1615	* @returns The cpu structure pointer.
1616	*/
1617	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1618	{
1619	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1620	RTCPUID idCpu = RTMpCpuId();
1621	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1622	return &g_HvmR0.aCpuInfo[idCpu];
1623	}
1624
1625
1626	/**
1627	* Returns the cpu structure for the current cpu.
1628	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1629	*
1630	* @returns The cpu structure pointer.
1631	* @param idCpu id of the VCPU.
1632	*/
1633	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1634	{
1635	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1636	return &g_HvmR0.aCpuInfo[idCpu];
1637	}
1638
1639
1640	/**
1641	* Save a pending IO read.
1642	*
1643	* @param pVCpu Pointer to the VMCPU.
1644	* @param GCPtrRip Address of IO instruction.
1645	* @param GCPtrRipNext Address of the next instruction.
1646	* @param uPort Port address.
1647	* @param uAndVal AND mask for saving the result in eax.
1648	* @param cbSize Read size.
1649	*/
1650	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1651	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1652	{
1653	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1654	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1655	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1656	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1657	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1658	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1659	return;
1660	}
1661
1662
1663	/**
1664	* Save a pending IO write.
1665	*
1666	* @param pVCpu Pointer to the VMCPU.
1667	* @param GCPtrRIP Address of IO instruction.
1668	* @param uPort Port address.
1669	* @param uAndVal AND mask for fetching the result from eax.
1670	* @param cbSize Read size.
1671	*/
1672	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1673	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1674	{
1675	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1676	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1677	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1678	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1679	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1680	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1681	return;
1682	}
1683
1684
1685	/**
1686	* Raw-mode switcher hook - disable VT-x if it's active and the current
1687	* switcher turns off paging.
1688	*
1689	* @returns VBox status code.
1690	* @param pVM Pointer to the VM.
1691	* @param enmSwitcher The switcher we're about to use.
1692	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1693	*/
1694	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1695	{
1696	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1697
1698	*pfVTxDisabled = false;
1699
1700	/* No such issues with AMD-V */
1701	if (!g_HvmR0.vmx.fSupported)
1702	return VINF_SUCCESS;
1703
1704	/* Check if the swithcing we're up to is safe. */
1705	switch (enmSwitcher)
1706	{
1707	case VMMSWITCHER_32_TO_32:
1708	case VMMSWITCHER_PAE_TO_PAE:
1709	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1710
1711	case VMMSWITCHER_32_TO_PAE:
1712	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1713	case VMMSWITCHER_AMD64_TO_32:
1714	case VMMSWITCHER_AMD64_TO_PAE:
1715	break; /* unsafe switchers */
1716
1717	default:
1718	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1719	}
1720
1721	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1722	regardless of whether we're currently using VT-x or not. */
1723	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1724	{
1725	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1726	return VINF_SUCCESS;
1727	}
1728
1729	/** @todo Check if this code is presumtive wrt other VT-x users on the
1730	* system... */
1731
1732	/* Nothing to do if we haven't enabled VT-x. */
1733	if (!g_HvmR0.fEnabled)
1734	return VINF_SUCCESS;
1735
1736	/* Local init implies the CPU is currently not in VMX root mode. */
1737	if (!g_HvmR0.fGlobalInit)
1738	return VINF_SUCCESS;
1739
1740	/* Ok, disable VT-x. */
1741	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1742	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1743
1744	*pfVTxDisabled = true;
1745	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1746	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1747	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1748	}
1749
1750
1751	/**
1752	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1753	* switcher turned off paging.
1754	*
1755	* @param pVM Pointer to the VM.
1756	* @param fVTxDisabled Whether VT-x was disabled or not.
1757	*/
1758	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1759	{
1760	Assert(!(ASMGetFlags() & X86_EFL_IF));
1761
1762	if (!fVTxDisabled)
1763	return; /* nothing to do */
1764
1765	Assert(g_HvmR0.vmx.fSupported);
1766	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1767	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1768	else
1769	{
1770	Assert(g_HvmR0.fEnabled);
1771	Assert(g_HvmR0.fGlobalInit);
1772
1773	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1774	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1775
1776	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1777	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1778	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
1779	}
1780	}
1781
1782	#ifdef VBOX_STRICT
1783
1784	/**
1785	* Dumps a descriptor.
1786	*
1787	* @param pDesc Descriptor to dump.
1788	* @param Sel Selector number.
1789	* @param pszMsg Message to prepend the log entry with.
1790	*/
1791	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1792	{
1793	/*
1794	* Make variable description string.
1795	*/
1796	static struct
1797	{
1798	unsigned cch;
1799	const char *psz;
1800	} const s_aTypes[32] =
1801	{
1802	# define STRENTRY(str) { sizeof(str) - 1, str }
1803
1804	/* system */
1805	# if HC_ARCH_BITS == 64
1806	STRENTRY("Reserved0 "), /* 0x00 */
1807	STRENTRY("Reserved1 "), /* 0x01 */
1808	STRENTRY("LDT "), /* 0x02 */
1809	STRENTRY("Reserved3 "), /* 0x03 */
1810	STRENTRY("Reserved4 "), /* 0x04 */
1811	STRENTRY("Reserved5 "), /* 0x05 */
1812	STRENTRY("Reserved6 "), /* 0x06 */
1813	STRENTRY("Reserved7 "), /* 0x07 */
1814	STRENTRY("Reserved8 "), /* 0x08 */
1815	STRENTRY("TSS64Avail "), /* 0x09 */
1816	STRENTRY("ReservedA "), /* 0x0a */
1817	STRENTRY("TSS64Busy "), /* 0x0b */
1818	STRENTRY("Call64 "), /* 0x0c */
1819	STRENTRY("ReservedD "), /* 0x0d */
1820	STRENTRY("Int64 "), /* 0x0e */
1821	STRENTRY("Trap64 "), /* 0x0f */
1822	# else
1823	STRENTRY("Reserved0 "), /* 0x00 */
1824	STRENTRY("TSS16Avail "), /* 0x01 */
1825	STRENTRY("LDT "), /* 0x02 */
1826	STRENTRY("TSS16Busy "), /* 0x03 */
1827	STRENTRY("Call16 "), /* 0x04 */
1828	STRENTRY("Task "), /* 0x05 */
1829	STRENTRY("Int16 "), /* 0x06 */
1830	STRENTRY("Trap16 "), /* 0x07 */
1831	STRENTRY("Reserved8 "), /* 0x08 */
1832	STRENTRY("TSS32Avail "), /* 0x09 */
1833	STRENTRY("ReservedA "), /* 0x0a */
1834	STRENTRY("TSS32Busy "), /* 0x0b */
1835	STRENTRY("Call32 "), /* 0x0c */
1836	STRENTRY("ReservedD "), /* 0x0d */
1837	STRENTRY("Int32 "), /* 0x0e */
1838	STRENTRY("Trap32 "), /* 0x0f */
1839	# endif
1840	/* non system */
1841	STRENTRY("DataRO "), /* 0x10 */
1842	STRENTRY("DataRO Accessed "), /* 0x11 */
1843	STRENTRY("DataRW "), /* 0x12 */
1844	STRENTRY("DataRW Accessed "), /* 0x13 */
1845	STRENTRY("DataDownRO "), /* 0x14 */
1846	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1847	STRENTRY("DataDownRW "), /* 0x16 */
1848	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1849	STRENTRY("CodeEO "), /* 0x18 */
1850	STRENTRY("CodeEO Accessed "), /* 0x19 */
1851	STRENTRY("CodeER "), /* 0x1a */
1852	STRENTRY("CodeER Accessed "), /* 0x1b */
1853	STRENTRY("CodeConfEO "), /* 0x1c */
1854	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1855	STRENTRY("CodeConfER "), /* 0x1e */
1856	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1857	# undef SYSENTRY
1858	};
1859	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1860	char szMsg[128];
1861	char *psz = &szMsg[0];
1862	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1863	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1864	psz += s_aTypes[i].cch;
1865
1866	if (pDesc->Gen.u1Present)
1867	ADD_STR(psz, "Present ");
1868	else
1869	ADD_STR(psz, "Not-Present ");
1870	# if HC_ARCH_BITS == 64
1871	if (pDesc->Gen.u1Long)
1872	ADD_STR(psz, "64-bit ");
1873	else
1874	ADD_STR(psz, "Comp ");
1875	# else
1876	if (pDesc->Gen.u1Granularity)
1877	ADD_STR(psz, "Page ");
1878	if (pDesc->Gen.u1DefBig)
1879	ADD_STR(psz, "32-bit ");
1880	else
1881	ADD_STR(psz, "16-bit ");
1882	# endif
1883	# undef ADD_STR
1884	*psz = '\0';
1885
1886	/*
1887	* Limit and Base and format the output.
1888	*/
1889	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1890
1891	# if HC_ARCH_BITS == 64
1892	uint64_t u32Base = X86DESC64_BASE(pDesc);
1893
1894	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1895	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1896	# else
1897	uint32_t u32Base = X86DESC_BASE(pDesc);
1898
1899	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1900	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1901	# endif
1902	}
1903
1904
1905	/**
1906	* Formats a full register dump.
1907	*
1908	* @param pVM Pointer to the VM.
1909	* @param pVCpu Pointer to the VMCPU.
1910	* @param pCtx Pointer to the CPU context.
1911	*/
1912	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1913	{
1914	NOREF(pVM);
1915
1916	/*
1917	* Format the flags.
1918	*/
1919	static struct
1920	{
1921	const char pszSet; const char pszClear; uint32_t fFlag;
1922	} const s_aFlags[] =
1923	{
1924	{ "vip",NULL, X86_EFL_VIP },
1925	{ "vif",NULL, X86_EFL_VIF },
1926	{ "ac", NULL, X86_EFL_AC },
1927	{ "vm", NULL, X86_EFL_VM },
1928	{ "rf", NULL, X86_EFL_RF },
1929	{ "nt", NULL, X86_EFL_NT },
1930	{ "ov", "nv", X86_EFL_OF },
1931	{ "dn", "up", X86_EFL_DF },
1932	{ "ei", "di", X86_EFL_IF },
1933	{ "tf", NULL, X86_EFL_TF },
1934	{ "nt", "pl", X86_EFL_SF },
1935	{ "nz", "zr", X86_EFL_ZF },
1936	{ "ac", "na", X86_EFL_AF },
1937	{ "po", "pe", X86_EFL_PF },
1938	{ "cy", "nc", X86_EFL_CF },
1939	};
1940	char szEFlags[80];
1941	char *psz = szEFlags;
1942	uint32_t efl = pCtx->eflags.u32;
1943	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1944	{
1945	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1946	if (pszAdd)
1947	{
1948	strcpy(psz, pszAdd);
1949	psz += strlen(pszAdd);
1950	*psz++ = ' ';
1951	}
1952	}
1953	psz[-1] = '\0';
1954
1955
1956	/*
1957	* Format the registers.
1958	*/
1959	if (CPUMIsGuestIn64BitCode(pVCpu))
1960	{
1961	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1962	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1963	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1964	"r14=%016RX64 r15=%016RX64\n"
1965	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1966	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1967	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1968	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1969	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1970	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1971	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1972	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1973	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1974	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1975	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1976	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1977	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1978	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1979	,
1980	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1981	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1982	pCtx->r14, pCtx->r15,
1983	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1984	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1985	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1986	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1987	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1988	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1989	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1990	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1991	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1992	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1993	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1994	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1995	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1996	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1997	}
1998	else
1999	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2000	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2001	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2002	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2003	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2004	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2005	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2006	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2007	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2008	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2009	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2010	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2011	,
2012	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2013	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2014	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2015	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2016	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2017	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2018	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2019	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2020	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2021	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2022	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2023	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2024
2025	Log(("FPU:\n"
2026	"FCW=%04x FSW=%04x FTW=%02x\n"
2027	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2028	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2029	,
2030	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2031	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2032	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2033	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2034
2035
2036	Log(("MSR:\n"
2037	"EFER =%016RX64\n"
2038	"PAT =%016RX64\n"
2039	"STAR =%016RX64\n"
2040	"CSTAR =%016RX64\n"
2041	"LSTAR =%016RX64\n"
2042	"SFMASK =%016RX64\n"
2043	"KERNELGSBASE =%016RX64\n",
2044	pCtx->msrEFER,
2045	pCtx->msrPAT,
2046	pCtx->msrSTAR,
2047	pCtx->msrCSTAR,
2048	pCtx->msrLSTAR,
2049	pCtx->msrSFMASK,
2050	pCtx->msrKERNELGSBASE));
2051
2052	}
2053
2054	#endif /* VBOX_STRICT */
2055

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 49407

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