HMR0.cpp@ 49828

Last change on this file since 49828 was 49729, checked in by vboxsync, 11 years ago
VMM/HM: VMCPU_HMCF -> HMCPU_CF macro renaming.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 71.9 KB

Line
1	/* $Id: HMR0.cpp 49729 2013-11-29 14:20:44Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost, void *pvArg));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	/** @todo This isn't used for anything relevant. Remove later? */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** VMX MSR values */
123	VMXMSRS Msrs;
124
125	/* Last instruction error */
126	uint32_t ulLastInstrError;
127	} vmx;
128
129	/** AMD-V information. */
130	struct
131	{
132	/* HWCR MSR (for diagnostics) */
133	uint64_t u64MsrHwcr;
134
135	/** SVM revision. */
136	uint32_t u32Rev;
137
138	/** SVM feature bits from cpuid 0x8000000a */
139	uint32_t u32Features;
140
141	/** Set by us to indicate SVM is supported by the CPU. */
142	bool fSupported;
143	} svm;
144	/** Saved error from detection */
145	int32_t lLastError;
146
147	struct
148	{
149	uint32_t u32AMDFeatureECX;
150	uint32_t u32AMDFeatureEDX;
151	} cpuid;
152
153	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
154	* enabled and disabled each time it's used to execute guest code. */
155	bool fGlobalInit;
156	/** Indicates whether the host is suspending or not. We'll refuse a few
157	* actions when the host is being suspended to speed up the suspending and
158	* avoid trouble. */
159	volatile bool fSuspended;
160
161	/** Whether we've already initialized all CPUs.
162	* @remarks We could check the EnableAllCpusOnce state, but this is
163	* simpler and hopefully easier to understand. */
164	bool fEnabled;
165	/** Serialize initialization in HMR0EnableAllCpus. */
166	RTONCE EnableAllCpusOnce;
167	} g_HvmR0;
168
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	/**
212	* Get the CPU ID on which the failure status code was reported.
213	*
214	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
215	* @param pFirstRc The first return code structure.
216	*/
217	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
218	{
219	return pFirstRc->idCpu;
220	}
221	#endif /* VBOX_STRICT */
222
223
224	/** @name Dummy callback handlers.
225	* @{ */
226
227	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
228	{
229	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
234	{
235	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
236	}
237
238	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
239	bool fEnabledBySystem, void *pvArg)
240	{
241	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
242	return VINF_SUCCESS;
243	}
244
245	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
246	{
247	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
252	{
253	NOREF(pVM);
254	return VINF_SUCCESS;
255	}
256
257	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
258	{
259	NOREF(pVM);
260	return VINF_SUCCESS;
261	}
262
263	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
264	{
265	NOREF(pVM);
266	return VINF_SUCCESS;
267	}
268
269	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
270	{
271	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
272	return VINF_SUCCESS;
273	}
274
275	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
276	{
277	NOREF(pVM); NOREF(pVCpu);
278	return VINF_SUCCESS;
279	}
280
281	/** @} */
282
283
284	/**
285	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
286	* Down at the Rate Specified" erratum.
287	*
288	* Errata names and related steppings:
289	* - BA86 - D0.
290	* - AAX65 - C2.
291	* - AAU65 - C2, K0.
292	* - AAO95 - B1.
293	* - AAT59 - C2.
294	* - AAK139 - D0.
295	* - AAM126 - C0, C1, D0.
296	* - AAN92 - B1.
297	* - AAJ124 - C0, D0.
298	*
299	* - AAP86 - B1.
300	*
301	* Steppings: B1, C0, C1, C2, D0, K0.
302	*
303	* @returns true if subject to it, false if not.
304	*/
305	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
306	{
307	uint32_t u = ASMCpuId_EAX(1);
308	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
309	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
310	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
311	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
312	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
313	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
314	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
315	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
316	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
317	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
318	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
319	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
320	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
321	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
322	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
323	)
324	return true;
325	return false;
326	}
327
328
329	/**
330	* Intel specific initialization code.
331	*
332	* @returns VBox status code (will only fail if out of memory).
333	*/
334	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
335	{
336	/*
337	* Check that all the required VT-x features are present.
338	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
339	*/
340	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
341	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
342	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
343	)
344	{
345	/** @todo move this into a separate function. */
346	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
347
348	/*
349	* First try use native kernel API for controlling VT-x.
350	* (This is only supported by some Mac OS X kernels atm.)
351	*/
352	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
353	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
354	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
355	{
356	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
357	if (RT_SUCCESS(rc))
358	{
359	g_HvmR0.vmx.fSupported = true;
360	rc = SUPR0EnableVTx(false /* fEnable */);
361	AssertLogRelRC(rc);
362	}
363	}
364	else
365	{
366	/* We need to check if VT-x has been properly initialized on all
367	CPUs. Some BIOSes do a lousy job. */
368	HMR0FIRSTRC FirstRc;
369	hmR0FirstRcInit(&FirstRc);
370	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
371	if (RT_SUCCESS(g_HvmR0.lLastError))
372	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
373	}
374	if (RT_SUCCESS(g_HvmR0.lLastError))
375	{
376	/* Reread in case it was changed by hmR0InitIntelCpu(). */
377	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
378
379	/*
380	* Read all relevant registers and MSRs.
381	*/
382	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
383	g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
384	g_HvmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
385	g_HvmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
386	g_HvmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
387	g_HvmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
388	g_HvmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
389	g_HvmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
390	g_HvmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
391	g_HvmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
392	g_HvmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
393	g_HvmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
394	g_HvmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
395	/* VPID 16 bits ASID. */
396	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
397
398	if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
399	{
400	g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
401	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
402	g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
403
404	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
405	g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
406	}
407
408	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
409	{
410	/*
411	* Enter root mode
412	*/
413	RTR0MEMOBJ hScatchMemObj;
414	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
415	if (RT_FAILURE(rc))
416	{
417	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
418	return rc;
419	}
420
421	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
422	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
423	ASMMemZeroPage(pvScatchPage);
424
425	/* Set revision dword at the beginning of the structure. */
426	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo);
427
428	/* Make sure we don't get rescheduled to another cpu during this probe. */
429	RTCCUINTREG fFlags = ASMIntDisableFlags();
430
431	/*
432	* Check CR4.VMXE
433	*/
434	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
435	if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
436	{
437	/* In theory this bit could be cleared behind our back. Which would cause
438	#UD faults when we try to execute the VMX instructions... */
439	ASMSetCR4(g_HvmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
440	}
441
442	/*
443	* The only way of checking if we're in VMX root mode or not is to try and enter it.
444	* There is no instruction or control bit that tells us if we're in VMX root mode.
445	* Therefore, try and enter VMX root mode here.
446	*/
447	rc = VMXEnable(HCPhysScratchPage);
448	if (RT_SUCCESS(rc))
449	{
450	g_HvmR0.vmx.fSupported = true;
451	VMXDisable();
452	}
453	else
454	{
455	/*
456	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
457	* it will crash the host when we enter raw mode, because:
458	*
459	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
460	* this bit), and
461	* (b) turning off paging causes a #GP (unavoidable when switching
462	* from long to 32 bits mode or 32 bits to PAE).
463	*
464	* They should fix their code, but until they do we simply refuse to run.
465	*/
466	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
467	Assert(g_HvmR0.vmx.fSupported == false);
468	}
469
470	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
471	if it wasn't so before (some software could incorrectly
472	think it's in VMX mode). */
473	ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
474	ASMSetFlags(fFlags);
475
476	RTR0MemObjFree(hScatchMemObj, false);
477	}
478
479	if (g_HvmR0.vmx.fSupported)
480	{
481	rc = VMXR0GlobalInit();
482	if (RT_FAILURE(rc))
483	g_HvmR0.lLastError = rc;
484
485	/*
486	* Install the VT-x methods.
487	*/
488	g_HvmR0.pfnEnterSession = VMXR0Enter;
489	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
490	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
491	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
492	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
493	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
494	g_HvmR0.pfnInitVM = VMXR0InitVM;
495	g_HvmR0.pfnTermVM = VMXR0TermVM;
496	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
497
498	/*
499	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
500	* Timer Does Not Count Down at the Rate Specified" erratum.
501	*/
502	if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
503	{
504	g_HvmR0.vmx.fUsePreemptTimer = true;
505	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc);
506	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
507	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
508	}
509	}
510	}
511	#ifdef LOG_ENABLED
512	else
513	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
514	#endif
515	}
516	else
517	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
518	return VINF_SUCCESS;
519	}
520
521
522	/**
523	* AMD-specific initialization code.
524	*
525	* @returns VBox status code.
526	*/
527	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
528	{
529	/*
530	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
531	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
532	*/
533	int rc;
534	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
535	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
536	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
537	&& ASMIsValidExtRange(uMaxExtLeaf)
538	&& uMaxExtLeaf >= 0x8000000a
539	)
540	{
541	/* Call the global AMD-V initialization routine. */
542	rc = SVMR0GlobalInit();
543	if (RT_FAILURE(rc))
544	{
545	g_HvmR0.lLastError = rc;
546	return rc;
547	}
548
549	/*
550	* Install the AMD-V methods.
551	*/
552	g_HvmR0.pfnEnterSession = SVMR0Enter;
553	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
554	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
555	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
556	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
557	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
558	g_HvmR0.pfnInitVM = SVMR0InitVM;
559	g_HvmR0.pfnTermVM = SVMR0TermVM;
560	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
561
562	/* Query AMD features. */
563	uint32_t u32Dummy;
564	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
565
566	/*
567	* We need to check if AMD-V has been properly initialized on all CPUs.
568	* Some BIOSes might do a poor job.
569	*/
570	HMR0FIRSTRC FirstRc;
571	hmR0FirstRcInit(&FirstRc);
572	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
573	AssertRC(rc);
574	if (RT_SUCCESS(rc))
575	rc = hmR0FirstRcGetStatus(&FirstRc);
576	#ifndef DEBUG_bird
577	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
578	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
579	#endif
580	if (RT_SUCCESS(rc))
581	{
582	/* Read the HWCR MSR for diagnostics. */
583	g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
584	g_HvmR0.svm.fSupported = true;
585	}
586	else
587	{
588	g_HvmR0.lLastError = rc;
589	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
590	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
591	}
592	}
593	else
594	{
595	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
596	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
597	}
598	return rc;
599	}
600
601
602	/**
603	* Does global Ring-0 HM initialization (at module init).
604	*
605	* @returns VBox status code.
606	*/
607	VMMR0_INT_DECL(int) HMR0Init(void)
608	{
609	/*
610	* Initialize the globals.
611	*/
612	g_HvmR0.fEnabled = false;
613	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
614	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
615	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
616	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
617
618	/* Fill in all callbacks with placeholders. */
619	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
620	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
621	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
622	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
623	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
624	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
625	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
626	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
627	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
628
629	/* Default is global VT-x/AMD-V init. */
630	g_HvmR0.fGlobalInit = true;
631
632	/*
633	* Make sure aCpuInfo is big enough for all the CPUs on this system.
634	*/
635	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
636	{
637	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
638	return VERR_TOO_MANY_CPUS;
639	}
640
641	/*
642	* Check for VT-x and AMD-V capabilities.
643	*/
644	int rc;
645	if (ASMHasCpuId())
646	{
647	/* Standard features. */
648	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
649	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
650	if (ASMIsValidStdRange(uMaxLeaf))
651	{
652	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
653	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
654
655	/* Query AMD features. */
656	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
657	if (ASMIsValidExtRange(uMaxExtLeaf))
658	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
659	&g_HvmR0.cpuid.u32AMDFeatureECX,
660	&g_HvmR0.cpuid.u32AMDFeatureEDX);
661	else
662	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
663
664	/* Go to CPU specific initialization code. */
665	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
666	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
667	{
668	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
669	if (RT_FAILURE(rc))
670	return rc;
671	}
672	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
673	{
674	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
675	if (RT_FAILURE(rc))
676	return rc;
677	}
678	else
679	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
680	}
681	else
682	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
683	}
684	else
685	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
686
687	/*
688	* Register notification callbacks that we can use to disable/enable CPUs
689	* when brought offline/online or suspending/resuming.
690	*/
691	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
692	{
693	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
694	AssertRC(rc);
695
696	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
697	AssertRC(rc);
698	}
699
700	/* We return success here because module init shall not fail if HM
701	fails to initialize. */
702	return VINF_SUCCESS;
703	}
704
705
706	/**
707	* Does global Ring-0 HM termination (at module termination).
708	*
709	* @returns VBox status code.
710	*/
711	VMMR0_INT_DECL(int) HMR0Term(void)
712	{
713	int rc;
714	if ( g_HvmR0.vmx.fSupported
715	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
716	{
717	/*
718	* Simple if the host OS manages VT-x.
719	*/
720	Assert(g_HvmR0.fGlobalInit);
721	rc = SUPR0EnableVTx(false /* fEnable */);
722
723	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
724	{
725	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
726	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
727	}
728	}
729	else
730	{
731	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
732	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
733	{
734	/* Doesn't really matter if this fails. */
735	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
736	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
737	}
738	else
739	rc = VINF_SUCCESS;
740
741	/*
742	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
743	*/
744	if (g_HvmR0.fGlobalInit)
745	{
746	HMR0FIRSTRC FirstRc;
747	hmR0FirstRcInit(&FirstRc);
748	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
749	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
750	if (RT_SUCCESS(rc))
751	{
752	rc = hmR0FirstRcGetStatus(&FirstRc);
753	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
754	}
755	}
756
757	/*
758	* Free the per-cpu pages used for VT-x and AMD-V.
759	*/
760	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
761	{
762	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
763	{
764	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
765	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
766	}
767	}
768	}
769
770	/** @todo This needs cleaning up. There's no matching
771	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
772	* should move into their respective modules. */
773	/* Finally, call global VT-x/AMD-V termination. */
774	if (g_HvmR0.vmx.fSupported)
775	VMXR0GlobalTerm();
776	else if (g_HvmR0.svm.fSupported)
777	SVMR0GlobalTerm();
778
779	return rc;
780	}
781
782
783	/**
784	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
785	* on a CPU.
786	*
787	* @param idCpu The identifier for the CPU the function is called on.
788	* @param pvUser1 Pointer to the first RC structure.
789	* @param pvUser2 Ignored.
790	*/
791	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
792	{
793	/** @todo Unify code with SUPR0QueryVTCaps(). */
794	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
795	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
796	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
797	NOREF(idCpu); NOREF(pvUser2);
798
799	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
800	bool const fInSmxMode = RT_BOOL(ASMGetCR4() & X86_CR4_SMXE);
801	bool fMsrLocked = RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_LOCK);
802	bool fSmxVmxAllowed = RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
803	bool fVmxAllowed = RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_VMXON);
804
805	/* Check if the LOCK bit is set but excludes the required VMXON bit. */
806	int rc = VERR_HM_IPE_1;
807	if (fMsrLocked)
808	{
809	if (fInSmxMode && !fSmxVmxAllowed)
810	rc = VERR_VMX_MSR_SMX_VMXON_DISABLED;
811	else if (!fVmxAllowed)
812	rc = VERR_VMX_MSR_VMXON_DISABLED;
813	else
814	rc = VINF_SUCCESS;
815	}
816	else
817	{
818	/*
819	* MSR is not yet locked; we can change it ourselves here.
820	* Once the lock bit is set, this MSR can no longer be modified.
821	*/
822	fFC \|= MSR_IA32_FEATURE_CONTROL_LOCK;
823	if (fInSmxMode)
824	fFC \|= MSR_IA32_FEATURE_CONTROL_SMX_VMXON;
825	else
826	fFC \|= MSR_IA32_FEATURE_CONTROL_VMXON;
827
828	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, fFC);
829
830	/* Verify. */
831	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
832	fMsrLocked = RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_LOCK);
833	fSmxVmxAllowed = fMsrLocked && RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
834	fVmxAllowed = fMsrLocked && RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_VMXON);
835	bool const fAllowed = fInSmxMode ? fSmxVmxAllowed : fVmxAllowed;
836	if (fAllowed)
837	rc = VINF_SUCCESS;
838	else
839	rc = VERR_VMX_MSR_LOCKING_FAILED;
840	}
841
842	hmR0FirstRcSetStatus(pFirstRc, rc);
843	}
844
845
846	/**
847	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
848	* on a CPU.
849	*
850	* @param idCpu The identifier for the CPU the function is called on.
851	* @param pvUser1 Pointer to the first RC structure.
852	* @param pvUser2 Ignored.
853	*/
854	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
855	{
856	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
857	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
858	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
859	NOREF(idCpu); NOREF(pvUser2);
860
861	/* Check if SVM is disabled. */
862	int rc;
863	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
864	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
865	{
866	/* Turn on SVM in the EFER MSR. */
867	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
868	if (fEfer & MSR_K6_EFER_SVME)
869	rc = VERR_SVM_IN_USE;
870	else
871	{
872	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
873
874	/* Paranoia. */
875	fEfer = ASMRdMsr(MSR_K6_EFER);
876	if (fEfer & MSR_K6_EFER_SVME)
877	{
878	/* Restore previous value. */
879	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
880	rc = VINF_SUCCESS;
881	}
882	else
883	rc = VERR_SVM_ILLEGAL_EFER_MSR;
884	}
885	}
886	else
887	rc = VERR_SVM_DISABLED;
888
889	hmR0FirstRcSetStatus(pFirstRc, rc);
890	}
891
892
893	/**
894	* Enable VT-x or AMD-V on the current CPU
895	*
896	* @returns VBox status code.
897	* @param pVM Pointer to the VM (can be NULL).
898	* @param idCpu The identifier for the CPU the function is called on.
899	*
900	* @remarks Maybe called with interrupts disabled!
901	*/
902	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
903	{
904	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
905
906	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
907	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
908	Assert(!pCpu->fConfigured);
909
910	pCpu->idCpu = idCpu;
911	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
912	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
913
914	int rc;
915	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
916	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HvmR0.vmx.Msrs);
917	else
918	{
919	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
920	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
921	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
922
923	if (g_HvmR0.vmx.fSupported)
924	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
925	else
926	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
927	}
928	AssertRC(rc);
929	if (RT_SUCCESS(rc))
930	pCpu->fConfigured = true;
931
932	return rc;
933	}
934
935
936	/**
937	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
938	*
939	* @param idCpu The identifier for the CPU the function is called on.
940	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
941	* @param pvUser2 The 2nd user argument.
942	*/
943	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
944	{
945	PVM pVM = (PVM)pvUser1; /* can be NULL! */
946	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
947	AssertReturnVoid(g_HvmR0.fGlobalInit);
948	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
949	}
950
951
952	/**
953	* RTOnce callback employed by HMR0EnableAllCpus.
954	*
955	* @returns VBox status code.
956	* @param pvUser Pointer to the VM.
957	* @param pvUserIgnore NULL, ignored.
958	*/
959	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
960	{
961	PVM pVM = (PVM)pvUser;
962
963	/*
964	* Indicate that we've initialized.
965	*
966	* Note! There is a potential race between this function and the suspend
967	* notification. Kind of unlikely though, so ignored for now.
968	*/
969	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
970	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
971
972	/*
973	* The global init variable is set by the first VM.
974	*/
975	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
976
977	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
978	{
979	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
980	g_HvmR0.aCpuInfo[i].fConfigured = false;
981	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
982	g_HvmR0.aCpuInfo[i].uCurrentAsid = 0;
983	}
984
985	int rc;
986	if ( g_HvmR0.vmx.fSupported
987	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
988	{
989	/*
990	* Global VT-x initialization API (only darwin for now).
991	*/
992	rc = SUPR0EnableVTx(true /* fEnable */);
993	if (RT_SUCCESS(rc))
994	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
995	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
996	else
997	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
998	}
999	else
1000	{
1001	/*
1002	* We're doing the job ourselves.
1003	*/
1004	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
1005	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1006	{
1007	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1008
1009	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1010	{
1011	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1012	AssertLogRelRCReturn(rc, rc);
1013
1014	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1015	ASMMemZeroPage(pvR0);
1016	}
1017	}
1018
1019	rc = VINF_SUCCESS;
1020	}
1021
1022	if ( RT_SUCCESS(rc)
1023	&& g_HvmR0.fGlobalInit)
1024	{
1025	/* First time, so initialize each cpu/core. */
1026	HMR0FIRSTRC FirstRc;
1027	hmR0FirstRcInit(&FirstRc);
1028	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1029	if (RT_SUCCESS(rc))
1030	rc = hmR0FirstRcGetStatus(&FirstRc);
1031	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1032	}
1033
1034	return rc;
1035	}
1036
1037
1038	/**
1039	* Sets up HM on all cpus.
1040	*
1041	* @returns VBox status code.
1042	* @param pVM Pointer to the VM.
1043	*/
1044	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1045	{
1046	/* Make sure we don't touch HM after we've disabled HM in
1047	preparation of a suspend. */
1048	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1049	return VERR_HM_SUSPEND_PENDING;
1050
1051	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1052	}
1053
1054
1055	/**
1056	* Disable VT-x or AMD-V on the current CPU.
1057	*
1058	* @returns VBox status code.
1059	* @param idCpu The identifier for the CPU the function is called on.
1060	*
1061	* @remarks Must be called with preemption disabled.
1062	*/
1063	static int hmR0DisableCpu(RTCPUID idCpu)
1064	{
1065	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1066
1067	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1068	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1069	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1070	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1071	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1072
1073	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1074	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1075
1076	int rc;
1077	if (pCpu->fConfigured)
1078	{
1079	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1080	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1081
1082	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1083	AssertRCReturn(rc, rc);
1084
1085	pCpu->fConfigured = false;
1086	}
1087	else
1088	rc = VINF_SUCCESS; /* nothing to do */
1089
1090	pCpu->uCurrentAsid = 0;
1091	return rc;
1092	}
1093
1094
1095	/**
1096	* Worker function passed to RTMpOnAll() that is to be called on the target
1097	* CPUs.
1098	*
1099	* @param idCpu The identifier for the CPU the function is called on.
1100	* @param pvUser1 The 1st user argument.
1101	* @param pvUser2 Opaque pointer to the FirstRc.
1102	*/
1103	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1104	{
1105	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1106	AssertReturnVoid(g_HvmR0.fGlobalInit);
1107	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1108	}
1109
1110
1111	/**
1112	* Callback function invoked when a cpu goes online or offline.
1113	*
1114	* @param enmEvent The Mp event.
1115	* @param idCpu The identifier for the CPU the function is called on.
1116	* @param pvData Opaque data (PVM pointer).
1117	*/
1118	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1119	{
1120	NOREF(pvData);
1121
1122	/*
1123	* We only care about uninitializing a CPU that is going offline. When a
1124	* CPU comes online, the initialization is done lazily in HMR0Enter().
1125	*/
1126	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1127	switch (enmEvent)
1128	{
1129	case RTMPEVENT_OFFLINE:
1130	{
1131	int rc = hmR0DisableCpu(idCpu);
1132	AssertRC(rc);
1133	break;
1134	}
1135
1136	default:
1137	break;
1138	}
1139	}
1140
1141
1142	/**
1143	* Called whenever a system power state change occurs.
1144	*
1145	* @param enmEvent The Power event.
1146	* @param pvUser User argument.
1147	*/
1148	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1149	{
1150	NOREF(pvUser);
1151	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1152
1153	#ifdef LOG_ENABLED
1154	if (enmEvent == RTPOWEREVENT_SUSPEND)
1155	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1156	else
1157	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1158	#endif
1159
1160	if (enmEvent == RTPOWEREVENT_SUSPEND)
1161	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1162
1163	if (g_HvmR0.fEnabled)
1164	{
1165	int rc;
1166	HMR0FIRSTRC FirstRc;
1167	hmR0FirstRcInit(&FirstRc);
1168
1169	if (enmEvent == RTPOWEREVENT_SUSPEND)
1170	{
1171	if (g_HvmR0.fGlobalInit)
1172	{
1173	/* Turn off VT-x or AMD-V on all CPUs. */
1174	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1175	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1176	}
1177	/* else nothing to do here for the local init case */
1178	}
1179	else
1180	{
1181	/* Reinit the CPUs from scratch as the suspend state might have
1182	messed with the MSRs. (lousy BIOSes as usual) */
1183	if (g_HvmR0.vmx.fSupported)
1184	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1185	else
1186	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1187	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1188	if (RT_SUCCESS(rc))
1189	rc = hmR0FirstRcGetStatus(&FirstRc);
1190	#ifdef LOG_ENABLED
1191	if (RT_FAILURE(rc))
1192	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1193	#endif
1194	if (g_HvmR0.fGlobalInit)
1195	{
1196	/* Turn VT-x or AMD-V back on on all CPUs. */
1197	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1198	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1199	}
1200	/* else nothing to do here for the local init case */
1201	}
1202	}
1203
1204	if (enmEvent == RTPOWEREVENT_RESUME)
1205	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1206	}
1207
1208
1209	/**
1210	* Does Ring-0 per VM HM initialization.
1211	*
1212	* This will copy HM global into the VM structure and call the CPU specific
1213	* init routine which will allocate resources for each virtual CPU and such.
1214	*
1215	* @returns VBox status code.
1216	* @param pVM Pointer to the VM.
1217	*/
1218	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1219	{
1220	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1221
1222	#ifdef LOG_ENABLED
1223	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1224	#endif
1225
1226	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1227	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1228	return VERR_HM_SUSPEND_PENDING;
1229
1230	/*
1231	* Copy globals to the VM structure.
1232	*/
1233	/** @todo r=ramshankar: Why do we do this for MSRs? We never change them in the
1234	* per-VM structures anyway... */
1235	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1236	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1237
1238	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1239	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1240	pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4;
1241	pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer;
1242	pVM->hm.s.vmx.Msrs = g_HvmR0.vmx.Msrs;
1243	pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr;
1244	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1245	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1246	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1247	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1248	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1249
1250	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1251
1252
1253	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1254	{
1255	pVM->hm.s.cMaxResumeLoops = 1024;
1256	if (RTThreadPreemptIsPendingTrusty())
1257	pVM->hm.s.cMaxResumeLoops = 8192;
1258	}
1259
1260	/*
1261	* Initialize some per CPU fields.
1262	*/
1263	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1264	{
1265	PVMCPU pVCpu = &pVM->aCpus[i];
1266
1267	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1268
1269	/* Invalidate the last cpu we were running on. */
1270	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1271
1272	/* We'll aways increment this the first time (host uses ASID 0) */
1273	pVCpu->hm.s.uCurrentAsid = 0;
1274	}
1275
1276	/*
1277	* Call the hardware specific initialization method.
1278	*/
1279	return g_HvmR0.pfnInitVM(pVM);
1280	}
1281
1282
1283	/**
1284	* Does Ring-0 per VM HM termination.
1285	*
1286	* @returns VBox status code.
1287	* @param pVM Pointer to the VM.
1288	*/
1289	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1290	{
1291	Log(("HMR0TermVM: %p\n", pVM));
1292	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1293
1294	/*
1295	* Call the hardware specific method.
1296	*
1297	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1298	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1299	*/
1300	return g_HvmR0.pfnTermVM(pVM);
1301	}
1302
1303
1304	/**
1305	* Sets up a VT-x or AMD-V session.
1306	*
1307	* This is mostly about setting up the hardware VM state.
1308	*
1309	* @returns VBox status code.
1310	* @param pVM Pointer to the VM.
1311	*/
1312	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1313	{
1314	Log(("HMR0SetupVM: %p\n", pVM));
1315	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1316
1317	/* Make sure we don't touch HM after we've disabled HM in
1318	preparation of a suspend. */
1319	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1320
1321	/* On first entry we'll sync everything. */
1322	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1323	HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1324
1325	/*
1326	* Call the hardware specific setup VM method. This requires the CPU to be
1327	* enabled for AMD-V/VT-x and preemption to be prevented.
1328	*/
1329	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1330	RTThreadPreemptDisable(&PreemptState);
1331	RTCPUID idCpu = RTMpCpuId();
1332
1333	/* Enable VT-x or AMD-V if local init is required. */
1334	int rc;
1335	if (!g_HvmR0.fGlobalInit)
1336	{
1337	rc = hmR0EnableCpu(pVM, idCpu);
1338	AssertRCReturnStmt(rc, RTThreadPreemptRestore(&PreemptState), rc);
1339	}
1340
1341	/* Setup VT-x or AMD-V. */
1342	rc = g_HvmR0.pfnSetupVM(pVM);
1343
1344	/* Disable VT-x or AMD-V if local init was done before. */
1345	if (!g_HvmR0.fGlobalInit)
1346	{
1347	int rc2 = hmR0DisableCpu(idCpu);
1348	AssertRC(rc2);
1349	}
1350
1351	RTThreadPreemptRestore(&PreemptState);
1352	return rc;
1353	}
1354
1355
1356	/**
1357	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1358	* required for entering HM context.
1359	*
1360	* @returns VBox status code.
1361	* @param pvCpu Pointer to the VMCPU.
1362	*
1363	* @remarks No-long-jump zone!!!
1364	*/
1365	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1366	{
1367	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1368
1369	int rc = VINF_SUCCESS;
1370	RTCPUID idCpu = RTMpCpuId();
1371	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1372	AssertPtr(pCpu);
1373
1374	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1375	if (!pCpu->fConfigured)
1376	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1377
1378	/* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
1379	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1380	pVCpu->hm.s.idEnteredCpu = idCpu;
1381	return rc;
1382	}
1383
1384
1385	/**
1386	* Enters the VT-x or AMD-V session.
1387	*
1388	* @returns VBox status code.
1389	* @param pVM Pointer to the VM.
1390	* @param pVCpu Pointer to the VMCPU.
1391	*
1392	* @remarks This is called with preemption disabled.
1393	*/
1394	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1395	{
1396	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1397	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1398	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1399
1400	/* Load the bare minimum state required for entering HM. */
1401	int rc = HMR0EnterCpu(pVCpu);
1402	AssertRCReturn(rc, rc);
1403
1404	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1405	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1406	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1407	#endif
1408
1409	RTCPUID idCpu = RTMpCpuId();
1410	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1411	Assert(pCpu);
1412	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1413
1414	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1415	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1416
1417	/* Load the host as we may be resuming code after a longjmp and quite
1418	possibly now be scheduled on a different CPU. */
1419	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1420	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1421
1422	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1423	if (fStartedSet)
1424	PGMRZDynMapReleaseAutoSet(pVCpu);
1425	#endif
1426
1427	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1428	and ring-3 calls. */
1429	if (RT_FAILURE(rc))
1430	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1431	return rc;
1432	}
1433
1434
1435	/**
1436	* Deinitializes the bare minimum state used for HM context and if necessary
1437	* disable HM on the CPU.
1438	*
1439	* @returns VBox status code.
1440	* @param pVCpu Pointer to the VMCPU.
1441	*
1442	* @remarks No-long-jump zone!!!
1443	*/
1444	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1445	{
1446	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1447	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU_1);
1448
1449	RTCPUID idCpu = RTMpCpuId();
1450	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1451
1452	if ( !g_HvmR0.fGlobalInit
1453	&& pCpu->fConfigured)
1454	{
1455	int rc = hmR0DisableCpu(idCpu);
1456	AssertRCReturn(rc, rc);
1457	Assert(!pCpu->fConfigured);
1458	}
1459
1460	/* Reset these to force a TLB flush for the next entry. */
1461	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1462	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1463	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1464
1465	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1466	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1467
1468	return VINF_SUCCESS;
1469	}
1470
1471
1472	/**
1473	* Thread-context hook for HM.
1474	*
1475	* @param enmEvent The thread-context event.
1476	* @param pvUser Opaque pointer to the VMCPU.
1477	*/
1478	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1479	{
1480	PVMCPU pVCpu = (PVMCPU)pvUser;
1481	Assert(pVCpu);
1482	Assert(g_HvmR0.pfnThreadCtxCallback);
1483
1484	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1485	}
1486
1487
1488	/**
1489	* Runs guest code in a hardware accelerated VM.
1490	*
1491	* @returns VBox status code.
1492	* @param pVM Pointer to the VM.
1493	* @param pVCpu Pointer to the VMCPU.
1494	*
1495	* @remarks Can be called with preemption enabled if thread-context hooks are
1496	* used!!!
1497	*/
1498	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1499	{
1500	#ifdef VBOX_STRICT
1501	/* With thread-context hooks we would be running this code with preemption enabled. */
1502	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1503	{
1504	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1505	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1506	Assert(pCpu->fConfigured);
1507	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1508	}
1509	#endif
1510
1511	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1512	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1513	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1514	PGMRZDynMapStartAutoSet(pVCpu);
1515	#endif
1516
1517	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1518
1519	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1520	PGMRZDynMapReleaseAutoSet(pVCpu);
1521	#endif
1522	return rc;
1523	}
1524
1525	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1526
1527	/**
1528	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1529	*
1530	* @returns VBox status code.
1531	* @param pVM Pointer to the VM.
1532	* @param pVCpu Pointer to the VMCPU.
1533	* @param pCtx Pointer to the guest CPU context.
1534	*/
1535	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1536	{
1537	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1538	if (pVM->hm.s.vmx.fSupported)
1539	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1540	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1541	}
1542
1543
1544	/**
1545	* Save guest debug state (64 bits guest mode & 32 bits host only)
1546	*
1547	* @returns VBox status code.
1548	* @param pVM Pointer to the VM.
1549	* @param pVCpu Pointer to the VMCPU.
1550	* @param pCtx Pointer to the guest CPU context.
1551	*/
1552	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1553	{
1554	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1555	if (pVM->hm.s.vmx.fSupported)
1556	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1557	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1558	}
1559
1560
1561	/**
1562	* Test the 32->64 bits switcher.
1563	*
1564	* @returns VBox status code.
1565	* @param pVM Pointer to the VM.
1566	*/
1567	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1568	{
1569	PVMCPU pVCpu = &pVM->aCpus[0];
1570	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1571	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1572	int rc;
1573
1574	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1575	if (pVM->hm.s.vmx.fSupported)
1576	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1577	else
1578	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1579	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1580
1581	return rc;
1582	}
1583
1584	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1585
1586	/**
1587	* Returns suspend status of the host.
1588	*
1589	* @returns Suspend pending or not.
1590	*/
1591	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1592	{
1593	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1594	}
1595
1596
1597	/**
1598	* Returns the cpu structure for the current cpu.
1599	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1600	*
1601	* @returns The cpu structure pointer.
1602	*/
1603	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1604	{
1605	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1606	RTCPUID idCpu = RTMpCpuId();
1607	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1608	return &g_HvmR0.aCpuInfo[idCpu];
1609	}
1610
1611
1612	/**
1613	* Returns the cpu structure for the current cpu.
1614	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1615	*
1616	* @returns The cpu structure pointer.
1617	* @param idCpu id of the VCPU.
1618	*/
1619	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1620	{
1621	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1622	return &g_HvmR0.aCpuInfo[idCpu];
1623	}
1624
1625
1626	/**
1627	* Save a pending IO read.
1628	*
1629	* @param pVCpu Pointer to the VMCPU.
1630	* @param GCPtrRip Address of IO instruction.
1631	* @param GCPtrRipNext Address of the next instruction.
1632	* @param uPort Port address.
1633	* @param uAndVal AND mask for saving the result in eax.
1634	* @param cbSize Read size.
1635	*/
1636	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1637	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1638	{
1639	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1640	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1641	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1642	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1643	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1644	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1645	return;
1646	}
1647
1648
1649	/**
1650	* Save a pending IO write.
1651	*
1652	* @param pVCpu Pointer to the VMCPU.
1653	* @param GCPtrRIP Address of IO instruction.
1654	* @param uPort Port address.
1655	* @param uAndVal AND mask for fetching the result from eax.
1656	* @param cbSize Read size.
1657	*/
1658	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1659	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1660	{
1661	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1662	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1663	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1664	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1665	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1666	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1667	return;
1668	}
1669
1670
1671	/**
1672	* Raw-mode switcher hook - disable VT-x if it's active and the current
1673	* switcher turns off paging.
1674	*
1675	* @returns VBox status code.
1676	* @param pVM Pointer to the VM.
1677	* @param enmSwitcher The switcher we're about to use.
1678	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1679	*/
1680	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1681	{
1682	NOREF(pVM);
1683
1684	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1685
1686	*pfVTxDisabled = false;
1687
1688	/* No such issues with AMD-V */
1689	if (!g_HvmR0.vmx.fSupported)
1690	return VINF_SUCCESS;
1691
1692	/* Check if the swithcing we're up to is safe. */
1693	switch (enmSwitcher)
1694	{
1695	case VMMSWITCHER_32_TO_32:
1696	case VMMSWITCHER_PAE_TO_PAE:
1697	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1698
1699	case VMMSWITCHER_32_TO_PAE:
1700	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1701	case VMMSWITCHER_AMD64_TO_32:
1702	case VMMSWITCHER_AMD64_TO_PAE:
1703	break; /* unsafe switchers */
1704
1705	default:
1706	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1707	}
1708
1709	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1710	regardless of whether we're currently using VT-x or not. */
1711	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1712	{
1713	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1714	return VINF_SUCCESS;
1715	}
1716
1717	/** @todo Check if this code is presumtive wrt other VT-x users on the
1718	* system... */
1719
1720	/* Nothing to do if we haven't enabled VT-x. */
1721	if (!g_HvmR0.fEnabled)
1722	return VINF_SUCCESS;
1723
1724	/* Local init implies the CPU is currently not in VMX root mode. */
1725	if (!g_HvmR0.fGlobalInit)
1726	return VINF_SUCCESS;
1727
1728	/* Ok, disable VT-x. */
1729	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1730	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1731
1732	*pfVTxDisabled = true;
1733	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1734	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1735	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1736	}
1737
1738
1739	/**
1740	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1741	* switcher turned off paging.
1742	*
1743	* @param pVM Pointer to the VM.
1744	* @param fVTxDisabled Whether VT-x was disabled or not.
1745	*/
1746	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1747	{
1748	Assert(!(ASMGetFlags() & X86_EFL_IF));
1749
1750	if (!fVTxDisabled)
1751	return; /* nothing to do */
1752
1753	Assert(g_HvmR0.vmx.fSupported);
1754	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1755	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1756	else
1757	{
1758	Assert(g_HvmR0.fEnabled);
1759	Assert(g_HvmR0.fGlobalInit);
1760
1761	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1762	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1763
1764	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1765	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1766	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
1767	}
1768	}
1769
1770	#ifdef VBOX_STRICT
1771
1772	/**
1773	* Dumps a descriptor.
1774	*
1775	* @param pDesc Descriptor to dump.
1776	* @param Sel Selector number.
1777	* @param pszMsg Message to prepend the log entry with.
1778	*/
1779	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1780	{
1781	/*
1782	* Make variable description string.
1783	*/
1784	static struct
1785	{
1786	unsigned cch;
1787	const char *psz;
1788	} const s_aTypes[32] =
1789	{
1790	# define STRENTRY(str) { sizeof(str) - 1, str }
1791
1792	/* system */
1793	# if HC_ARCH_BITS == 64
1794	STRENTRY("Reserved0 "), /* 0x00 */
1795	STRENTRY("Reserved1 "), /* 0x01 */
1796	STRENTRY("LDT "), /* 0x02 */
1797	STRENTRY("Reserved3 "), /* 0x03 */
1798	STRENTRY("Reserved4 "), /* 0x04 */
1799	STRENTRY("Reserved5 "), /* 0x05 */
1800	STRENTRY("Reserved6 "), /* 0x06 */
1801	STRENTRY("Reserved7 "), /* 0x07 */
1802	STRENTRY("Reserved8 "), /* 0x08 */
1803	STRENTRY("TSS64Avail "), /* 0x09 */
1804	STRENTRY("ReservedA "), /* 0x0a */
1805	STRENTRY("TSS64Busy "), /* 0x0b */
1806	STRENTRY("Call64 "), /* 0x0c */
1807	STRENTRY("ReservedD "), /* 0x0d */
1808	STRENTRY("Int64 "), /* 0x0e */
1809	STRENTRY("Trap64 "), /* 0x0f */
1810	# else
1811	STRENTRY("Reserved0 "), /* 0x00 */
1812	STRENTRY("TSS16Avail "), /* 0x01 */
1813	STRENTRY("LDT "), /* 0x02 */
1814	STRENTRY("TSS16Busy "), /* 0x03 */
1815	STRENTRY("Call16 "), /* 0x04 */
1816	STRENTRY("Task "), /* 0x05 */
1817	STRENTRY("Int16 "), /* 0x06 */
1818	STRENTRY("Trap16 "), /* 0x07 */
1819	STRENTRY("Reserved8 "), /* 0x08 */
1820	STRENTRY("TSS32Avail "), /* 0x09 */
1821	STRENTRY("ReservedA "), /* 0x0a */
1822	STRENTRY("TSS32Busy "), /* 0x0b */
1823	STRENTRY("Call32 "), /* 0x0c */
1824	STRENTRY("ReservedD "), /* 0x0d */
1825	STRENTRY("Int32 "), /* 0x0e */
1826	STRENTRY("Trap32 "), /* 0x0f */
1827	# endif
1828	/* non system */
1829	STRENTRY("DataRO "), /* 0x10 */
1830	STRENTRY("DataRO Accessed "), /* 0x11 */
1831	STRENTRY("DataRW "), /* 0x12 */
1832	STRENTRY("DataRW Accessed "), /* 0x13 */
1833	STRENTRY("DataDownRO "), /* 0x14 */
1834	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1835	STRENTRY("DataDownRW "), /* 0x16 */
1836	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1837	STRENTRY("CodeEO "), /* 0x18 */
1838	STRENTRY("CodeEO Accessed "), /* 0x19 */
1839	STRENTRY("CodeER "), /* 0x1a */
1840	STRENTRY("CodeER Accessed "), /* 0x1b */
1841	STRENTRY("CodeConfEO "), /* 0x1c */
1842	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1843	STRENTRY("CodeConfER "), /* 0x1e */
1844	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1845	# undef SYSENTRY
1846	};
1847	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1848	char szMsg[128];
1849	char *psz = &szMsg[0];
1850	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1851	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1852	psz += s_aTypes[i].cch;
1853
1854	if (pDesc->Gen.u1Present)
1855	ADD_STR(psz, "Present ");
1856	else
1857	ADD_STR(psz, "Not-Present ");
1858	# if HC_ARCH_BITS == 64
1859	if (pDesc->Gen.u1Long)
1860	ADD_STR(psz, "64-bit ");
1861	else
1862	ADD_STR(psz, "Comp ");
1863	# else
1864	if (pDesc->Gen.u1Granularity)
1865	ADD_STR(psz, "Page ");
1866	if (pDesc->Gen.u1DefBig)
1867	ADD_STR(psz, "32-bit ");
1868	else
1869	ADD_STR(psz, "16-bit ");
1870	# endif
1871	# undef ADD_STR
1872	*psz = '\0';
1873
1874	/*
1875	* Limit and Base and format the output.
1876	*/
1877	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1878
1879	# if HC_ARCH_BITS == 64
1880	uint64_t u32Base = X86DESC64_BASE(pDesc);
1881
1882	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1883	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1884	# else
1885	uint32_t u32Base = X86DESC_BASE(pDesc);
1886
1887	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1888	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1889	# endif
1890	}
1891
1892
1893	/**
1894	* Formats a full register dump.
1895	*
1896	* @param pVM Pointer to the VM.
1897	* @param pVCpu Pointer to the VMCPU.
1898	* @param pCtx Pointer to the CPU context.
1899	*/
1900	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1901	{
1902	NOREF(pVM);
1903
1904	/*
1905	* Format the flags.
1906	*/
1907	static struct
1908	{
1909	const char pszSet; const char pszClear; uint32_t fFlag;
1910	} const s_aFlags[] =
1911	{
1912	{ "vip",NULL, X86_EFL_VIP },
1913	{ "vif",NULL, X86_EFL_VIF },
1914	{ "ac", NULL, X86_EFL_AC },
1915	{ "vm", NULL, X86_EFL_VM },
1916	{ "rf", NULL, X86_EFL_RF },
1917	{ "nt", NULL, X86_EFL_NT },
1918	{ "ov", "nv", X86_EFL_OF },
1919	{ "dn", "up", X86_EFL_DF },
1920	{ "ei", "di", X86_EFL_IF },
1921	{ "tf", NULL, X86_EFL_TF },
1922	{ "nt", "pl", X86_EFL_SF },
1923	{ "nz", "zr", X86_EFL_ZF },
1924	{ "ac", "na", X86_EFL_AF },
1925	{ "po", "pe", X86_EFL_PF },
1926	{ "cy", "nc", X86_EFL_CF },
1927	};
1928	char szEFlags[80];
1929	char *psz = szEFlags;
1930	uint32_t efl = pCtx->eflags.u32;
1931	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1932	{
1933	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1934	if (pszAdd)
1935	{
1936	strcpy(psz, pszAdd);
1937	psz += strlen(pszAdd);
1938	*psz++ = ' ';
1939	}
1940	}
1941	psz[-1] = '\0';
1942
1943
1944	/*
1945	* Format the registers.
1946	*/
1947	if (CPUMIsGuestIn64BitCode(pVCpu))
1948	{
1949	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1950	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1951	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1952	"r14=%016RX64 r15=%016RX64\n"
1953	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1954	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1955	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1956	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1957	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1958	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1959	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1960	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1961	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1962	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1963	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1964	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1965	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1966	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1967	,
1968	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1969	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1970	pCtx->r14, pCtx->r15,
1971	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1972	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1973	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1974	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1975	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1976	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1977	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1978	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1979	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1980	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1981	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1982	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1983	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1984	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1985	}
1986	else
1987	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1988	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1989	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1990	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1991	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1992	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1993	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1994	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1995	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1996	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1997	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1998	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1999	,
2000	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2001	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2002	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2003	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2004	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2005	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2006	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2007	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2008	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2009	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2010	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2011	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2012
2013	Log(("FPU:\n"
2014	"FCW=%04x FSW=%04x FTW=%02x\n"
2015	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2016	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2017	,
2018	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2019	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2020	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2021	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2022
2023
2024	Log(("MSR:\n"
2025	"EFER =%016RX64\n"
2026	"PAT =%016RX64\n"
2027	"STAR =%016RX64\n"
2028	"CSTAR =%016RX64\n"
2029	"LSTAR =%016RX64\n"
2030	"SFMASK =%016RX64\n"
2031	"KERNELGSBASE =%016RX64\n",
2032	pCtx->msrEFER,
2033	pCtx->msrPAT,
2034	pCtx->msrSTAR,
2035	pCtx->msrCSTAR,
2036	pCtx->msrLSTAR,
2037	pCtx->msrSFMASK,
2038	pCtx->msrKERNELGSBASE));
2039
2040	}
2041
2042	#endif /* VBOX_STRICT */
2043

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 49828

Download in other formats: