HMR0.cpp@ 52023

Last change on this file since 52023 was 51560, checked in by vboxsync, 11 years ago
VMM/GIM: Mapping of GIM MMIO2 regions and Hyper-V provider work.
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1	/* $Id: HMR0.cpp 51560 2014-06-06 05:17:02Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2014 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <VBox/vmm/hm.h>
23	#include <VBox/vmm/pgm.h>
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/hm_vmx.h>
27	#include <VBox/vmm/hm_svm.h>
28	#include <VBox/err.h>
29	#include <VBox/log.h>
30	#include <iprt/assert.h>
31	#include <iprt/asm.h>
32	#include <iprt/asm-amd64-x86.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mem.h>
35	#include <iprt/memobj.h>
36	#include <iprt/once.h>
37	#include <iprt/param.h>
38	#include <iprt/power.h>
39	#include <iprt/string.h>
40	#include <iprt/thread.h>
41	#include <iprt/x86.h>
42	#include "HMVMXR0.h"
43	#include "HMSVMR0.h"
44
45
46	/*******************************************************************************
47	* Internal Functions *
48	*******************************************************************************/
49	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
50	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
54	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
55
56
57	/*******************************************************************************
58	* Structures and Typedefs *
59	*******************************************************************************/
60	/**
61	* This is used to manage the status code of a RTMpOnAll in HM.
62	*/
63	typedef struct HMR0FIRSTRC
64	{
65	/** The status code. */
66	int32_t volatile rc;
67	/** The ID of the CPU reporting the first failure. */
68	RTCPUID volatile idCpu;
69	} HMR0FIRSTRC;
70	/** Pointer to a first return code structure. */
71	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
72
73
74	/*******************************************************************************
75	* Global Variables *
76	*******************************************************************************/
77	/**
78	* Global data.
79	*/
80	static struct
81	{
82	/** Per CPU globals. */
83	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
84
85	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
86	* @{ */
87	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
88	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
89	DECLR0CALLBACKMEMBER(int, pfnSaveHostState, (PVM pVM, PVMCPU pVCpu));
90	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
91	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
92	bool fEnabledByHost, void *pvArg));
93	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
94	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
95	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnSetupVM ,(PVM pVM));
97	/** @} */
98
99	/** Maximum ASID allowed. */
100	uint32_t uMaxAsid;
101
102	/** VT-x data. */
103	struct
104	{
105	/** Set to by us to indicate VMX is supported by the CPU. */
106	bool fSupported;
107	/** Whether we're using SUPR0EnableVTx or not. */
108	bool fUsingSUPR0EnableVTx;
109	/** Whether we're using the preemption timer or not. */
110	bool fUsePreemptTimer;
111	/** The shift mask employed by the VMX-Preemption timer. */
112	uint8_t cPreemptTimerShift;
113
114	/** Host CR4 value (set by ring-0 VMX init) */
115	/** @todo This isn't used for anything relevant. Remove later? */
116	uint64_t u64HostCr4;
117
118	/** Host EFER value (set by ring-0 VMX init) */
119	uint64_t u64HostEfer;
120
121	/** VMX MSR values */
122	VMXMSRS Msrs;
123
124	/* Last instruction error */
125	uint32_t ulLastInstrError;
126	} vmx;
127
128	/** AMD-V information. */
129	struct
130	{
131	/* HWCR MSR (for diagnostics) */
132	uint64_t u64MsrHwcr;
133
134	/** SVM revision. */
135	uint32_t u32Rev;
136
137	/** SVM feature bits from cpuid 0x8000000a */
138	uint32_t u32Features;
139
140	/** Set by us to indicate SVM is supported by the CPU. */
141	bool fSupported;
142	} svm;
143	/** Saved error from detection */
144	int32_t lLastError;
145
146	struct
147	{
148	uint32_t u32AMDFeatureECX;
149	uint32_t u32AMDFeatureEDX;
150	} cpuid;
151
152	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
153	* enabled and disabled each time it's used to execute guest code. */
154	bool fGlobalInit;
155	/** Indicates whether the host is suspending or not. We'll refuse a few
156	* actions when the host is being suspended to speed up the suspending and
157	* avoid trouble. */
158	volatile bool fSuspended;
159
160	/** Whether we've already initialized all CPUs.
161	* @remarks We could check the EnableAllCpusOnce state, but this is
162	* simpler and hopefully easier to understand. */
163	bool fEnabled;
164	/** Serialize initialization in HMR0EnableAllCpus. */
165	RTONCE EnableAllCpusOnce;
166	} g_HvmR0;
167
168
169
170	/**
171	* Initializes a first return code structure.
172	*
173	* @param pFirstRc The structure to init.
174	*/
175	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
176	{
177	pFirstRc->rc = VINF_SUCCESS;
178	pFirstRc->idCpu = NIL_RTCPUID;
179	}
180
181
182	/**
183	* Try set the status code (success ignored).
184	*
185	* @param pFirstRc The first return code structure.
186	* @param rc The status code.
187	*/
188	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
189	{
190	if ( RT_FAILURE(rc)
191	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
192	pFirstRc->idCpu = RTMpCpuId();
193	}
194
195
196	/**
197	* Get the status code of a first return code structure.
198	*
199	* @returns The status code; VINF_SUCCESS or error status, no informational or
200	* warning errors.
201	* @param pFirstRc The first return code structure.
202	*/
203	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
204	{
205	return pFirstRc->rc;
206	}
207
208
209	#ifdef VBOX_STRICT
210	/**
211	* Get the CPU ID on which the failure status code was reported.
212	*
213	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
214	* @param pFirstRc The first return code structure.
215	*/
216	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
217	{
218	return pFirstRc->idCpu;
219	}
220	#endif /* VBOX_STRICT */
221
222
223	/** @name Dummy callback handlers.
224	* @{ */
225
226	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
227	{
228	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
229	return VINF_SUCCESS;
230	}
231
232	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
233	{
234	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
235	}
236
237	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
238	bool fEnabledBySystem, void *pvArg)
239	{
240	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
241	return VINF_SUCCESS;
242	}
243
244	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
245	{
246	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
247	return VINF_SUCCESS;
248	}
249
250	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
251	{
252	NOREF(pVM);
253	return VINF_SUCCESS;
254	}
255
256	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
257	{
258	NOREF(pVM);
259	return VINF_SUCCESS;
260	}
261
262	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
263	{
264	NOREF(pVM);
265	return VINF_SUCCESS;
266	}
267
268	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
269	{
270	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
271	return VINF_SUCCESS;
272	}
273
274	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
275	{
276	NOREF(pVM); NOREF(pVCpu);
277	return VINF_SUCCESS;
278	}
279
280	/** @} */
281
282
283	/**
284	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
285	* Down at the Rate Specified" erratum.
286	*
287	* Errata names and related steppings:
288	* - BA86 - D0.
289	* - AAX65 - C2.
290	* - AAU65 - C2, K0.
291	* - AAO95 - B1.
292	* - AAT59 - C2.
293	* - AAK139 - D0.
294	* - AAM126 - C0, C1, D0.
295	* - AAN92 - B1.
296	* - AAJ124 - C0, D0.
297	*
298	* - AAP86 - B1.
299	*
300	* Steppings: B1, C0, C1, C2, D0, K0.
301	*
302	* @returns true if subject to it, false if not.
303	*/
304	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
305	{
306	uint32_t u = ASMCpuId_EAX(1);
307	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
308	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
309	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
310	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
311	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
312	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
313	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
314	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
315	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
316	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
317	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
318	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
319	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
320	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
321	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
322	)
323	return true;
324	return false;
325	}
326
327
328	/**
329	* Intel specific initialization code.
330	*
331	* @returns VBox status code (will only fail if out of memory).
332	*/
333	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
334	{
335	/*
336	* Check that all the required VT-x features are present.
337	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
338	*/
339	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
340	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
341	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
342	)
343	{
344	/** @todo move this into a separate function. */
345	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
346
347	/*
348	* First try use native kernel API for controlling VT-x.
349	* (This is only supported by some Mac OS X kernels atm.)
350	*/
351	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
352	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
353	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
354	{
355	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
356	if (RT_SUCCESS(rc))
357	{
358	g_HvmR0.vmx.fSupported = true;
359	rc = SUPR0EnableVTx(false /* fEnable */);
360	AssertLogRelRC(rc);
361	}
362	}
363	else
364	{
365	/* We need to check if VT-x has been properly initialized on all
366	CPUs. Some BIOSes do a lousy job. */
367	HMR0FIRSTRC FirstRc;
368	hmR0FirstRcInit(&FirstRc);
369	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
370	if (RT_SUCCESS(g_HvmR0.lLastError))
371	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
372	}
373	if (RT_SUCCESS(g_HvmR0.lLastError))
374	{
375	/* Reread in case it was changed by hmR0InitIntelCpu(). */
376	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
377
378	/*
379	* Read all relevant registers and MSRs.
380	*/
381	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
382	g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
383	g_HvmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
384	g_HvmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
385	g_HvmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
386	g_HvmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
387	g_HvmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
388	g_HvmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
389	g_HvmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
390	g_HvmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
391	g_HvmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
392	g_HvmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
393	g_HvmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
394	/* VPID 16 bits ASID. */
395	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
396
397	if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
398	{
399	g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
400	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
401	g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
402
403	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
404	g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
405	}
406
407	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
408	{
409	/*
410	* Enter root mode
411	*/
412	RTR0MEMOBJ hScatchMemObj;
413	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
414	if (RT_FAILURE(rc))
415	{
416	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
417	return rc;
418	}
419
420	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
421	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
422	ASMMemZeroPage(pvScatchPage);
423
424	/* Set revision dword at the beginning of the structure. */
425	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo);
426
427	/* Make sure we don't get rescheduled to another cpu during this probe. */
428	RTCCUINTREG fFlags = ASMIntDisableFlags();
429
430	/*
431	* Check CR4.VMXE
432	*/
433	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
434	if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
435	{
436	/* In theory this bit could be cleared behind our back. Which would cause
437	#UD faults when we try to execute the VMX instructions... */
438	ASMSetCR4(g_HvmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
439	}
440
441	/*
442	* The only way of checking if we're in VMX root mode or not is to try and enter it.
443	* There is no instruction or control bit that tells us if we're in VMX root mode.
444	* Therefore, try and enter VMX root mode here.
445	*/
446	rc = VMXEnable(HCPhysScratchPage);
447	if (RT_SUCCESS(rc))
448	{
449	g_HvmR0.vmx.fSupported = true;
450	VMXDisable();
451	}
452	else
453	{
454	/*
455	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
456	* it will crash the host when we enter raw mode, because:
457	*
458	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
459	* this bit), and
460	* (b) turning off paging causes a #GP (unavoidable when switching
461	* from long to 32 bits mode or 32 bits to PAE).
462	*
463	* They should fix their code, but until they do we simply refuse to run.
464	*/
465	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
466	Assert(g_HvmR0.vmx.fSupported == false);
467	}
468
469	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
470	if it wasn't so before (some software could incorrectly
471	think it's in VMX mode). */
472	ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
473	ASMSetFlags(fFlags);
474
475	RTR0MemObjFree(hScatchMemObj, false);
476	}
477
478	if (g_HvmR0.vmx.fSupported)
479	{
480	rc = VMXR0GlobalInit();
481	if (RT_FAILURE(rc))
482	g_HvmR0.lLastError = rc;
483
484	/*
485	* Install the VT-x methods.
486	*/
487	g_HvmR0.pfnEnterSession = VMXR0Enter;
488	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
489	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
490	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
491	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
492	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
493	g_HvmR0.pfnInitVM = VMXR0InitVM;
494	g_HvmR0.pfnTermVM = VMXR0TermVM;
495	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
496
497	/*
498	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
499	* Timer Does Not Count Down at the Rate Specified" erratum.
500	*/
501	if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
502	{
503	g_HvmR0.vmx.fUsePreemptTimer = true;
504	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc);
505	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
506	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
507	}
508	}
509	}
510	#ifdef LOG_ENABLED
511	else
512	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
513	#endif
514	}
515	else
516	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
517	return VINF_SUCCESS;
518	}
519
520
521	/**
522	* AMD-specific initialization code.
523	*
524	* @returns VBox status code.
525	*/
526	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
527	{
528	/*
529	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
530	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
531	*/
532	int rc;
533	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
534	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
535	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
536	&& ASMIsValidExtRange(uMaxExtLeaf)
537	&& uMaxExtLeaf >= 0x8000000a
538	)
539	{
540	/* Call the global AMD-V initialization routine. */
541	rc = SVMR0GlobalInit();
542	if (RT_FAILURE(rc))
543	{
544	g_HvmR0.lLastError = rc;
545	return rc;
546	}
547
548	/*
549	* Install the AMD-V methods.
550	*/
551	g_HvmR0.pfnEnterSession = SVMR0Enter;
552	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
553	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
554	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
555	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
556	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
557	g_HvmR0.pfnInitVM = SVMR0InitVM;
558	g_HvmR0.pfnTermVM = SVMR0TermVM;
559	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
560
561	/* Query AMD features. */
562	uint32_t u32Dummy;
563	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
564
565	/*
566	* We need to check if AMD-V has been properly initialized on all CPUs.
567	* Some BIOSes might do a poor job.
568	*/
569	HMR0FIRSTRC FirstRc;
570	hmR0FirstRcInit(&FirstRc);
571	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
572	AssertRC(rc);
573	if (RT_SUCCESS(rc))
574	rc = hmR0FirstRcGetStatus(&FirstRc);
575	#ifndef DEBUG_bird
576	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
577	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
578	#endif
579	if (RT_SUCCESS(rc))
580	{
581	/* Read the HWCR MSR for diagnostics. */
582	g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
583	g_HvmR0.svm.fSupported = true;
584	}
585	else
586	{
587	g_HvmR0.lLastError = rc;
588	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
589	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
590	}
591	}
592	else
593	{
594	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
595	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
596	}
597	return rc;
598	}
599
600
601	/**
602	* Does global Ring-0 HM initialization (at module init).
603	*
604	* @returns VBox status code.
605	*/
606	VMMR0_INT_DECL(int) HMR0Init(void)
607	{
608	/*
609	* Initialize the globals.
610	*/
611	g_HvmR0.fEnabled = false;
612	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
613	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
614	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
615	{
616	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
617	g_HvmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
618	}
619
620	/* Fill in all callbacks with placeholders. */
621	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
622	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
623	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
624	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
625	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
626	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
627	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
628	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
629	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
630
631	/* Default is global VT-x/AMD-V init. */
632	g_HvmR0.fGlobalInit = true;
633
634	/*
635	* Make sure aCpuInfo is big enough for all the CPUs on this system.
636	*/
637	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
638	{
639	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
640	return VERR_TOO_MANY_CPUS;
641	}
642
643	/*
644	* Check for VT-x and AMD-V capabilities.
645	*/
646	int rc;
647	if (ASMHasCpuId())
648	{
649	/* Standard features. */
650	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
651	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
652	if (ASMIsValidStdRange(uMaxLeaf))
653	{
654	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
655	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
656
657	/* Query AMD features. */
658	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
659	if (ASMIsValidExtRange(uMaxExtLeaf))
660	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
661	&g_HvmR0.cpuid.u32AMDFeatureECX,
662	&g_HvmR0.cpuid.u32AMDFeatureEDX);
663	else
664	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
665
666	/* Go to CPU specific initialization code. */
667	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
668	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
669	{
670	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
671	if (RT_FAILURE(rc))
672	return rc;
673	}
674	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
675	{
676	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
677	if (RT_FAILURE(rc))
678	return rc;
679	}
680	else
681	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
682	}
683	else
684	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
685	}
686	else
687	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
688
689	/*
690	* Register notification callbacks that we can use to disable/enable CPUs
691	* when brought offline/online or suspending/resuming.
692	*/
693	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
694	{
695	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
696	AssertRC(rc);
697
698	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
699	AssertRC(rc);
700	}
701
702	/* We return success here because module init shall not fail if HM
703	fails to initialize. */
704	return VINF_SUCCESS;
705	}
706
707
708	/**
709	* Does global Ring-0 HM termination (at module termination).
710	*
711	* @returns VBox status code.
712	*/
713	VMMR0_INT_DECL(int) HMR0Term(void)
714	{
715	int rc;
716	if ( g_HvmR0.vmx.fSupported
717	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
718	{
719	/*
720	* Simple if the host OS manages VT-x.
721	*/
722	Assert(g_HvmR0.fGlobalInit);
723	rc = SUPR0EnableVTx(false /* fEnable */);
724
725	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
726	{
727	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
728	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
729	}
730	}
731	else
732	{
733	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
734	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
735	{
736	/* Doesn't really matter if this fails. */
737	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
738	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
739	}
740	else
741	rc = VINF_SUCCESS;
742
743	/*
744	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
745	*/
746	if (g_HvmR0.fGlobalInit)
747	{
748	HMR0FIRSTRC FirstRc;
749	hmR0FirstRcInit(&FirstRc);
750	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
751	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
752	if (RT_SUCCESS(rc))
753	{
754	rc = hmR0FirstRcGetStatus(&FirstRc);
755	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
756	}
757	}
758
759	/*
760	* Free the per-cpu pages used for VT-x and AMD-V.
761	*/
762	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
763	{
764	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
765	{
766	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
767	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
768	}
769	}
770	}
771
772	/** @todo This needs cleaning up. There's no matching
773	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
774	* should move into their respective modules. */
775	/* Finally, call global VT-x/AMD-V termination. */
776	if (g_HvmR0.vmx.fSupported)
777	VMXR0GlobalTerm();
778	else if (g_HvmR0.svm.fSupported)
779	SVMR0GlobalTerm();
780
781	return rc;
782	}
783
784
785	/**
786	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
787	* on a CPU.
788	*
789	* @param idCpu The identifier for the CPU the function is called on.
790	* @param pvUser1 Pointer to the first RC structure.
791	* @param pvUser2 Ignored.
792	*/
793	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
794	{
795	/** @todo Unify code with SUPR0QueryVTCaps(). */
796	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
797	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
798	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
799	NOREF(idCpu); NOREF(pvUser2);
800
801	uint64_t u64FeatMsr = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
802	bool const fMaybeSmxMode = RT_BOOL(ASMGetCR4() & X86_CR4_SMXE);
803	bool fMsrLocked = RT_BOOL(u64FeatMsr & MSR_IA32_FEATURE_CONTROL_LOCK);
804	bool fSmxVmxAllowed = RT_BOOL(u64FeatMsr & MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
805	bool fVmxAllowed = RT_BOOL(u64FeatMsr & MSR_IA32_FEATURE_CONTROL_VMXON);
806
807	/* Check if the LOCK bit is set but excludes the required VMXON bit. */
808	int rc = VERR_HM_IPE_1;
809	if (fMsrLocked)
810	{
811	if (fVmxAllowed && fSmxVmxAllowed)
812	rc = VINF_SUCCESS;
813	else if (!fVmxAllowed && !fSmxVmxAllowed)
814	rc = VERR_VMX_MSR_ALL_VMXON_DISABLED;
815	else if (!fMaybeSmxMode)
816	{
817	if (fVmxAllowed)
818	rc = VINF_SUCCESS;
819	else
820	rc = VERR_VMX_MSR_VMXON_DISABLED;
821	}
822	else
823	{
824	/*
825	* CR4.SMXE is set but this doesn't mean the CPU is necessarily in SMX mode. We shall assume
826	* that it is -not- and that it is a stupid BIOS/OS setting CR4.SMXE for no good reason.
827	* See @bugref{6873}.
828	*/
829	Assert(fMaybeSmxMode == true);
830	rc = VINF_SUCCESS;
831	}
832	}
833	else
834	{
835	/*
836	* MSR is not yet locked; we can change it ourselves here.
837	* Once the lock bit is set, this MSR can no longer be modified.
838	*
839	* Set both the VMXON and SMX_VMXON bits as we can't determine SMX mode
840	* accurately. See @bugref{6873}.
841	*/
842	u64FeatMsr \|= MSR_IA32_FEATURE_CONTROL_LOCK
843	\| MSR_IA32_FEATURE_CONTROL_SMX_VMXON
844	\| MSR_IA32_FEATURE_CONTROL_VMXON;
845	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, u64FeatMsr);
846
847	/* Verify. */
848	u64FeatMsr = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
849	fMsrLocked = RT_BOOL(u64FeatMsr & MSR_IA32_FEATURE_CONTROL_LOCK);
850	fSmxVmxAllowed = fMsrLocked && RT_BOOL(u64FeatMsr & MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
851	fVmxAllowed = fMsrLocked && RT_BOOL(u64FeatMsr & MSR_IA32_FEATURE_CONTROL_VMXON);
852	if (fSmxVmxAllowed && fVmxAllowed)
853	rc = VINF_SUCCESS;
854	else
855	rc = VERR_VMX_MSR_LOCKING_FAILED;
856	}
857
858	hmR0FirstRcSetStatus(pFirstRc, rc);
859	}
860
861
862	/**
863	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
864	* on a CPU.
865	*
866	* @param idCpu The identifier for the CPU the function is called on.
867	* @param pvUser1 Pointer to the first RC structure.
868	* @param pvUser2 Ignored.
869	*/
870	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
871	{
872	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
873	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
874	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
875	NOREF(idCpu); NOREF(pvUser2);
876
877	/* Check if SVM is disabled. */
878	int rc;
879	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
880	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
881	{
882	/* Turn on SVM in the EFER MSR. */
883	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
884	if (fEfer & MSR_K6_EFER_SVME)
885	rc = VERR_SVM_IN_USE;
886	else
887	{
888	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
889
890	/* Paranoia. */
891	fEfer = ASMRdMsr(MSR_K6_EFER);
892	if (fEfer & MSR_K6_EFER_SVME)
893	{
894	/* Restore previous value. */
895	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
896	rc = VINF_SUCCESS;
897	}
898	else
899	rc = VERR_SVM_ILLEGAL_EFER_MSR;
900	}
901	}
902	else
903	rc = VERR_SVM_DISABLED;
904
905	hmR0FirstRcSetStatus(pFirstRc, rc);
906	}
907
908
909	/**
910	* Enable VT-x or AMD-V on the current CPU
911	*
912	* @returns VBox status code.
913	* @param pVM Pointer to the VM (can be NULL).
914	* @param idCpu The identifier for the CPU the function is called on.
915	*
916	* @remarks Maybe called with interrupts disabled!
917	*/
918	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
919	{
920	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
921
922	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
923	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
924	Assert(!pCpu->fConfigured);
925	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
926
927	pCpu->idCpu = idCpu;
928	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
929
930	int rc;
931	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
932	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HvmR0.vmx.Msrs);
933	else
934	{
935	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
936	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
937	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0 /* iPage */);
938
939	if (g_HvmR0.vmx.fSupported)
940	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
941	else
942	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
943	}
944	AssertRC(rc);
945	if (RT_SUCCESS(rc))
946	pCpu->fConfigured = true;
947
948	return rc;
949	}
950
951
952	/**
953	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
954	*
955	* @param idCpu The identifier for the CPU the function is called on.
956	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
957	* @param pvUser2 The 2nd user argument.
958	*/
959	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
960	{
961	PVM pVM = (PVM)pvUser1; /* can be NULL! */
962	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
963	AssertReturnVoid(g_HvmR0.fGlobalInit);
964	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
965	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
966	}
967
968
969	/**
970	* RTOnce callback employed by HMR0EnableAllCpus.
971	*
972	* @returns VBox status code.
973	* @param pvUser Pointer to the VM.
974	* @param pvUserIgnore NULL, ignored.
975	*/
976	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
977	{
978	PVM pVM = (PVM)pvUser;
979
980	/*
981	* Indicate that we've initialized.
982	*
983	* Note! There is a potential race between this function and the suspend
984	* notification. Kind of unlikely though, so ignored for now.
985	*/
986	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
987	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
988
989	/*
990	* The global init variable is set by the first VM.
991	*/
992	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
993
994	#ifdef VBOX_STRICT
995	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
996	{
997	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
998	Assert(!g_HvmR0.aCpuInfo[i].fConfigured);
999	Assert(!g_HvmR0.aCpuInfo[i].cTlbFlushes);
1000	Assert(!g_HvmR0.aCpuInfo[i].uCurrentAsid);
1001	}
1002	#endif
1003
1004	int rc;
1005	if ( g_HvmR0.vmx.fSupported
1006	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1007	{
1008	/*
1009	* Global VT-x initialization API (only darwin for now).
1010	*/
1011	rc = SUPR0EnableVTx(true /* fEnable */);
1012	if (RT_SUCCESS(rc))
1013	{
1014	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
1015	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
1016	}
1017	else
1018	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
1019	}
1020	else
1021	{
1022	/*
1023	* We're doing the job ourselves.
1024	*/
1025	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
1026	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1027	{
1028	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1029
1030	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1031	{
1032	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
1033	AssertLogRelRCReturn(rc, rc);
1034
1035	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1036	ASMMemZeroPage(pvR0);
1037	}
1038	}
1039
1040	rc = VINF_SUCCESS;
1041	}
1042
1043	if ( RT_SUCCESS(rc)
1044	&& g_HvmR0.fGlobalInit)
1045	{
1046	/* First time, so initialize each cpu/core. */
1047	HMR0FIRSTRC FirstRc;
1048	hmR0FirstRcInit(&FirstRc);
1049	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1050	if (RT_SUCCESS(rc))
1051	rc = hmR0FirstRcGetStatus(&FirstRc);
1052	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1053	}
1054
1055	return rc;
1056	}
1057
1058
1059	/**
1060	* Sets up HM on all cpus.
1061	*
1062	* @returns VBox status code.
1063	* @param pVM Pointer to the VM.
1064	*/
1065	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1066	{
1067	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1068	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1069	return VERR_HM_SUSPEND_PENDING;
1070
1071	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1072	}
1073
1074
1075	/**
1076	* Disable VT-x or AMD-V on the current CPU.
1077	*
1078	* @returns VBox status code.
1079	* @param idCpu The identifier for the CPU the function is called on.
1080	*
1081	* @remarks Must be called with preemption disabled.
1082	*/
1083	static int hmR0DisableCpu(RTCPUID idCpu)
1084	{
1085	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1086
1087	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1088	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1089	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1090	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1091	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1092
1093	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1094	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1095
1096	int rc;
1097	if (pCpu->fConfigured)
1098	{
1099	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1100	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1101
1102	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1103	AssertRCReturn(rc, rc);
1104
1105	pCpu->fConfigured = false;
1106	pCpu->idCpu = NIL_RTCPUID;
1107	}
1108	else
1109	rc = VINF_SUCCESS; /* nothing to do */
1110
1111	return rc;
1112	}
1113
1114
1115	/**
1116	* Worker function passed to RTMpOnAll() that is to be called on the target
1117	* CPUs.
1118	*
1119	* @param idCpu The identifier for the CPU the function is called on.
1120	* @param pvUser1 The 1st user argument.
1121	* @param pvUser2 Opaque pointer to the FirstRc.
1122	*/
1123	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1124	{
1125	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1126	AssertReturnVoid(g_HvmR0.fGlobalInit);
1127	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1128	}
1129
1130
1131	/**
1132	* Callback function invoked when a cpu goes online or offline.
1133	*
1134	* @param enmEvent The Mp event.
1135	* @param idCpu The identifier for the CPU the function is called on.
1136	* @param pvData Opaque data (PVM pointer).
1137	*/
1138	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1139	{
1140	NOREF(pvData);
1141
1142	/*
1143	* We only care about uninitializing a CPU that is going offline. When a
1144	* CPU comes online, the initialization is done lazily in HMR0Enter().
1145	*/
1146	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1147	switch (enmEvent)
1148	{
1149	case RTMPEVENT_OFFLINE:
1150	{
1151	int rc = hmR0DisableCpu(idCpu);
1152	AssertRC(rc);
1153	break;
1154	}
1155
1156	default:
1157	break;
1158	}
1159	}
1160
1161
1162	/**
1163	* Called whenever a system power state change occurs.
1164	*
1165	* @param enmEvent The Power event.
1166	* @param pvUser User argument.
1167	*/
1168	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1169	{
1170	NOREF(pvUser);
1171	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1172
1173	#ifdef LOG_ENABLED
1174	if (enmEvent == RTPOWEREVENT_SUSPEND)
1175	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1176	else
1177	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1178	#endif
1179
1180	if (enmEvent == RTPOWEREVENT_SUSPEND)
1181	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1182
1183	if (g_HvmR0.fEnabled)
1184	{
1185	int rc;
1186	HMR0FIRSTRC FirstRc;
1187	hmR0FirstRcInit(&FirstRc);
1188
1189	if (enmEvent == RTPOWEREVENT_SUSPEND)
1190	{
1191	if (g_HvmR0.fGlobalInit)
1192	{
1193	/* Turn off VT-x or AMD-V on all CPUs. */
1194	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1195	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1196	}
1197	/* else nothing to do here for the local init case */
1198	}
1199	else
1200	{
1201	/* Reinit the CPUs from scratch as the suspend state might have
1202	messed with the MSRs. (lousy BIOSes as usual) */
1203	if (g_HvmR0.vmx.fSupported)
1204	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1205	else
1206	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1207	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1208	if (RT_SUCCESS(rc))
1209	rc = hmR0FirstRcGetStatus(&FirstRc);
1210	#ifdef LOG_ENABLED
1211	if (RT_FAILURE(rc))
1212	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1213	#endif
1214	if (g_HvmR0.fGlobalInit)
1215	{
1216	/* Turn VT-x or AMD-V back on on all CPUs. */
1217	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1218	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1219	}
1220	/* else nothing to do here for the local init case */
1221	}
1222	}
1223
1224	if (enmEvent == RTPOWEREVENT_RESUME)
1225	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1226	}
1227
1228
1229	/**
1230	* Does ring-0 per-VM HM initialization.
1231	*
1232	* This will copy HM global into the VM structure and call the CPU specific
1233	* init routine which will allocate resources for each virtual CPU and such.
1234	*
1235	* @returns VBox status code.
1236	* @param pVM Pointer to the VM.
1237	*/
1238	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1239	{
1240	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1241
1242	#ifdef LOG_ENABLED
1243	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1244	#endif
1245
1246	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1247	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1248	return VERR_HM_SUSPEND_PENDING;
1249
1250	/*
1251	* Copy globals to the VM structure.
1252	*/
1253	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1254	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1255
1256	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1257	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1258	pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4;
1259	pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer;
1260	pVM->hm.s.vmx.Msrs = g_HvmR0.vmx.Msrs;
1261	pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr;
1262	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1263	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1264	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1265	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1266	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1267
1268	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1269
1270
1271	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1272	{
1273	pVM->hm.s.cMaxResumeLoops = 1024;
1274	if (RTThreadPreemptIsPendingTrusty())
1275	pVM->hm.s.cMaxResumeLoops = 8192;
1276	}
1277
1278	/*
1279	* Initialize some per CPU fields.
1280	*/
1281	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1282	{
1283	PVMCPU pVCpu = &pVM->aCpus[i];
1284	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1285	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1286
1287	/* We'll aways increment this the first time (host uses ASID 0). */
1288	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1289	}
1290
1291	/*
1292	* Call the hardware specific initialization method.
1293	*/
1294	return g_HvmR0.pfnInitVM(pVM);
1295	}
1296
1297
1298	/**
1299	* Does ring-0 per VM HM termination.
1300	*
1301	* @returns VBox status code.
1302	* @param pVM Pointer to the VM.
1303	*/
1304	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1305	{
1306	Log(("HMR0TermVM: %p\n", pVM));
1307	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1308
1309	/*
1310	* Call the hardware specific method.
1311	*
1312	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1313	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1314	*/
1315	return g_HvmR0.pfnTermVM(pVM);
1316	}
1317
1318
1319	/**
1320	* Sets up a VT-x or AMD-V session.
1321	*
1322	* This is mostly about setting up the hardware VM state.
1323	*
1324	* @returns VBox status code.
1325	* @param pVM Pointer to the VM.
1326	*/
1327	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1328	{
1329	Log(("HMR0SetupVM: %p\n", pVM));
1330	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1331
1332	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1333	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1334
1335	/* On first entry we'll sync everything. */
1336	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1337	HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1338
1339	/*
1340	* Call the hardware specific setup VM method. This requires the CPU to be
1341	* enabled for AMD-V/VT-x and preemption to be prevented.
1342	*/
1343	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1344	RTThreadPreemptDisable(&PreemptState);
1345	RTCPUID idCpu = RTMpCpuId();
1346
1347	/* Enable VT-x or AMD-V if local init is required. */
1348	int rc;
1349	if (!g_HvmR0.fGlobalInit)
1350	{
1351	rc = hmR0EnableCpu(pVM, idCpu);
1352	AssertRCReturnStmt(rc, RTThreadPreemptRestore(&PreemptState), rc);
1353	}
1354
1355	/* Setup VT-x or AMD-V. */
1356	rc = g_HvmR0.pfnSetupVM(pVM);
1357
1358	/* Disable VT-x or AMD-V if local init was done before. */
1359	if (!g_HvmR0.fGlobalInit)
1360	{
1361	int rc2 = hmR0DisableCpu(idCpu);
1362	AssertRC(rc2);
1363	}
1364
1365	RTThreadPreemptRestore(&PreemptState);
1366	return rc;
1367	}
1368
1369
1370	/**
1371	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1372	* required for entering HM context.
1373	*
1374	* @returns VBox status code.
1375	* @param pvCpu Pointer to the VMCPU.
1376	*
1377	* @remarks No-long-jump zone!!!
1378	*/
1379	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1380	{
1381	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1382
1383	int rc = VINF_SUCCESS;
1384	RTCPUID idCpu = RTMpCpuId();
1385	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1386	AssertPtr(pCpu);
1387
1388	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1389	if (!pCpu->fConfigured)
1390	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1391
1392	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1393	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1394
1395	Assert(pCpu->idCpu == idCpu && pCpu->idCpu != NIL_RTCPUID);
1396	pVCpu->hm.s.idEnteredCpu = idCpu;
1397	return rc;
1398	}
1399
1400
1401	/**
1402	* Enters the VT-x or AMD-V session.
1403	*
1404	* @returns VBox status code.
1405	* @param pVM Pointer to the VM.
1406	* @param pVCpu Pointer to the VMCPU.
1407	*
1408	* @remarks This is called with preemption disabled.
1409	*/
1410	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1411	{
1412	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1413	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1414	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1415
1416	/* Load the bare minimum state required for entering HM. */
1417	int rc = HMR0EnterCpu(pVCpu);
1418	AssertRCReturn(rc, rc);
1419
1420	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1421	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1422	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1423	#endif
1424
1425	RTCPUID idCpu = RTMpCpuId();
1426	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1427	Assert(pCpu);
1428	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1429
1430	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1431	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1432
1433	/* Load the host-state as we may be resuming code after a longjmp and quite
1434	possibly now be scheduled on a different CPU. */
1435	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1436	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1437
1438	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1439	if (fStartedSet)
1440	PGMRZDynMapReleaseAutoSet(pVCpu);
1441	#endif
1442
1443	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1444	if (RT_FAILURE(rc))
1445	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1446	return rc;
1447	}
1448
1449
1450	/**
1451	* Deinitializes the bare minimum state used for HM context and if necessary
1452	* disable HM on the CPU.
1453	*
1454	* @returns VBox status code.
1455	* @param pVCpu Pointer to the VMCPU.
1456	*
1457	* @remarks No-long-jump zone!!!
1458	*/
1459	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1460	{
1461	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1462	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1463
1464	RTCPUID idCpu = RTMpCpuId();
1465	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1466
1467	if ( !g_HvmR0.fGlobalInit
1468	&& pCpu->fConfigured)
1469	{
1470	int rc = hmR0DisableCpu(idCpu);
1471	AssertRCReturn(rc, rc);
1472	Assert(!pCpu->fConfigured);
1473	Assert(pCpu->idCpu == NIL_RTCPUID);
1474
1475	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1476	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1477	}
1478
1479	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1480	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1481
1482	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1483	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1484
1485	return VINF_SUCCESS;
1486	}
1487
1488
1489	/**
1490	* Thread-context hook for HM.
1491	*
1492	* @param enmEvent The thread-context event.
1493	* @param pvUser Opaque pointer to the VMCPU.
1494	*/
1495	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1496	{
1497	PVMCPU pVCpu = (PVMCPU)pvUser;
1498	Assert(pVCpu);
1499	Assert(g_HvmR0.pfnThreadCtxCallback);
1500
1501	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1502	}
1503
1504
1505	/**
1506	* Runs guest code in a hardware accelerated VM.
1507	*
1508	* @returns VBox status code.
1509	* @param pVM Pointer to the VM.
1510	* @param pVCpu Pointer to the VMCPU.
1511	*
1512	* @remarks Can be called with preemption enabled if thread-context hooks are
1513	* used!!!
1514	*/
1515	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1516	{
1517	#ifdef VBOX_STRICT
1518	/* With thread-context hooks we would be running this code with preemption enabled. */
1519	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1520	{
1521	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1522	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1523	Assert(pCpu->fConfigured);
1524	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1525	}
1526	#endif
1527
1528	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1529	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1530	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1531	PGMRZDynMapStartAutoSet(pVCpu);
1532	#endif
1533
1534	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1535
1536	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1537	PGMRZDynMapReleaseAutoSet(pVCpu);
1538	#endif
1539	return rc;
1540	}
1541
1542	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1543
1544	/**
1545	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1546	*
1547	* @returns VBox status code.
1548	* @param pVM Pointer to the VM.
1549	* @param pVCpu Pointer to the VMCPU.
1550	* @param pCtx Pointer to the guest CPU context.
1551	*/
1552	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1553	{
1554	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1555	if (pVM->hm.s.vmx.fSupported)
1556	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1557	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1558	}
1559
1560
1561	/**
1562	* Save guest debug state (64 bits guest mode & 32 bits host only)
1563	*
1564	* @returns VBox status code.
1565	* @param pVM Pointer to the VM.
1566	* @param pVCpu Pointer to the VMCPU.
1567	* @param pCtx Pointer to the guest CPU context.
1568	*/
1569	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1570	{
1571	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1572	if (pVM->hm.s.vmx.fSupported)
1573	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1574	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1575	}
1576
1577
1578	/**
1579	* Test the 32->64 bits switcher.
1580	*
1581	* @returns VBox status code.
1582	* @param pVM Pointer to the VM.
1583	*/
1584	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1585	{
1586	PVMCPU pVCpu = &pVM->aCpus[0];
1587	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1588	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1589	int rc;
1590
1591	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1592	if (pVM->hm.s.vmx.fSupported)
1593	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1594	else
1595	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1596	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1597
1598	return rc;
1599	}
1600
1601	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1602
1603	/**
1604	* Returns suspend status of the host.
1605	*
1606	* @returns Suspend pending or not.
1607	*/
1608	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1609	{
1610	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1611	}
1612
1613
1614	/**
1615	* Returns the cpu structure for the current cpu.
1616	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1617	*
1618	* @returns The cpu structure pointer.
1619	*/
1620	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1621	{
1622	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1623	RTCPUID idCpu = RTMpCpuId();
1624	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1625	return &g_HvmR0.aCpuInfo[idCpu];
1626	}
1627
1628
1629	/**
1630	* Returns the cpu structure for the current cpu.
1631	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1632	*
1633	* @returns The cpu structure pointer.
1634	* @param idCpu id of the VCPU.
1635	*/
1636	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1637	{
1638	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1639	return &g_HvmR0.aCpuInfo[idCpu];
1640	}
1641
1642
1643	/**
1644	* Save a pending IO read.
1645	*
1646	* @param pVCpu Pointer to the VMCPU.
1647	* @param GCPtrRip Address of IO instruction.
1648	* @param GCPtrRipNext Address of the next instruction.
1649	* @param uPort Port address.
1650	* @param uAndVal AND mask for saving the result in eax.
1651	* @param cbSize Read size.
1652	*/
1653	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1654	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1655	{
1656	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1657	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1658	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1659	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1660	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1661	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1662	return;
1663	}
1664
1665
1666	/**
1667	* Save a pending IO write.
1668	*
1669	* @param pVCpu Pointer to the VMCPU.
1670	* @param GCPtrRIP Address of IO instruction.
1671	* @param uPort Port address.
1672	* @param uAndVal AND mask for fetching the result from eax.
1673	* @param cbSize Read size.
1674	*/
1675	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1676	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1677	{
1678	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1679	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1680	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1681	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1682	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1683	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1684	return;
1685	}
1686
1687
1688	/**
1689	* Raw-mode switcher hook - disable VT-x if it's active and the current
1690	* switcher turns off paging.
1691	*
1692	* @returns VBox status code.
1693	* @param pVM Pointer to the VM.
1694	* @param enmSwitcher The switcher we're about to use.
1695	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1696	*/
1697	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1698	{
1699	NOREF(pVM);
1700
1701	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1702
1703	*pfVTxDisabled = false;
1704
1705	/* No such issues with AMD-V */
1706	if (!g_HvmR0.vmx.fSupported)
1707	return VINF_SUCCESS;
1708
1709	/* Check if the swithcing we're up to is safe. */
1710	switch (enmSwitcher)
1711	{
1712	case VMMSWITCHER_32_TO_32:
1713	case VMMSWITCHER_PAE_TO_PAE:
1714	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1715
1716	case VMMSWITCHER_32_TO_PAE:
1717	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1718	case VMMSWITCHER_AMD64_TO_32:
1719	case VMMSWITCHER_AMD64_TO_PAE:
1720	break; /* unsafe switchers */
1721
1722	default:
1723	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1724	}
1725
1726	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1727	regardless of whether we're currently using VT-x or not. */
1728	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1729	{
1730	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1731	return VINF_SUCCESS;
1732	}
1733
1734	/** @todo Check if this code is presumtive wrt other VT-x users on the
1735	* system... */
1736
1737	/* Nothing to do if we haven't enabled VT-x. */
1738	if (!g_HvmR0.fEnabled)
1739	return VINF_SUCCESS;
1740
1741	/* Local init implies the CPU is currently not in VMX root mode. */
1742	if (!g_HvmR0.fGlobalInit)
1743	return VINF_SUCCESS;
1744
1745	/* Ok, disable VT-x. */
1746	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1747	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1748
1749	*pfVTxDisabled = true;
1750	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1751	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1752	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1753	}
1754
1755
1756	/**
1757	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1758	* switcher turned off paging.
1759	*
1760	* @param pVM Pointer to the VM.
1761	* @param fVTxDisabled Whether VT-x was disabled or not.
1762	*/
1763	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1764	{
1765	Assert(!ASMIntAreEnabled());
1766
1767	if (!fVTxDisabled)
1768	return; /* nothing to do */
1769
1770	Assert(g_HvmR0.vmx.fSupported);
1771	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1772	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1773	else
1774	{
1775	Assert(g_HvmR0.fEnabled);
1776	Assert(g_HvmR0.fGlobalInit);
1777
1778	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1779	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1780
1781	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1782	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1783	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
1784	}
1785	}
1786
1787	#ifdef VBOX_STRICT
1788
1789	/**
1790	* Dumps a descriptor.
1791	*
1792	* @param pDesc Descriptor to dump.
1793	* @param Sel Selector number.
1794	* @param pszMsg Message to prepend the log entry with.
1795	*/
1796	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1797	{
1798	/*
1799	* Make variable description string.
1800	*/
1801	static struct
1802	{
1803	unsigned cch;
1804	const char *psz;
1805	} const s_aTypes[32] =
1806	{
1807	# define STRENTRY(str) { sizeof(str) - 1, str }
1808
1809	/* system */
1810	# if HC_ARCH_BITS == 64
1811	STRENTRY("Reserved0 "), /* 0x00 */
1812	STRENTRY("Reserved1 "), /* 0x01 */
1813	STRENTRY("LDT "), /* 0x02 */
1814	STRENTRY("Reserved3 "), /* 0x03 */
1815	STRENTRY("Reserved4 "), /* 0x04 */
1816	STRENTRY("Reserved5 "), /* 0x05 */
1817	STRENTRY("Reserved6 "), /* 0x06 */
1818	STRENTRY("Reserved7 "), /* 0x07 */
1819	STRENTRY("Reserved8 "), /* 0x08 */
1820	STRENTRY("TSS64Avail "), /* 0x09 */
1821	STRENTRY("ReservedA "), /* 0x0a */
1822	STRENTRY("TSS64Busy "), /* 0x0b */
1823	STRENTRY("Call64 "), /* 0x0c */
1824	STRENTRY("ReservedD "), /* 0x0d */
1825	STRENTRY("Int64 "), /* 0x0e */
1826	STRENTRY("Trap64 "), /* 0x0f */
1827	# else
1828	STRENTRY("Reserved0 "), /* 0x00 */
1829	STRENTRY("TSS16Avail "), /* 0x01 */
1830	STRENTRY("LDT "), /* 0x02 */
1831	STRENTRY("TSS16Busy "), /* 0x03 */
1832	STRENTRY("Call16 "), /* 0x04 */
1833	STRENTRY("Task "), /* 0x05 */
1834	STRENTRY("Int16 "), /* 0x06 */
1835	STRENTRY("Trap16 "), /* 0x07 */
1836	STRENTRY("Reserved8 "), /* 0x08 */
1837	STRENTRY("TSS32Avail "), /* 0x09 */
1838	STRENTRY("ReservedA "), /* 0x0a */
1839	STRENTRY("TSS32Busy "), /* 0x0b */
1840	STRENTRY("Call32 "), /* 0x0c */
1841	STRENTRY("ReservedD "), /* 0x0d */
1842	STRENTRY("Int32 "), /* 0x0e */
1843	STRENTRY("Trap32 "), /* 0x0f */
1844	# endif
1845	/* non system */
1846	STRENTRY("DataRO "), /* 0x10 */
1847	STRENTRY("DataRO Accessed "), /* 0x11 */
1848	STRENTRY("DataRW "), /* 0x12 */
1849	STRENTRY("DataRW Accessed "), /* 0x13 */
1850	STRENTRY("DataDownRO "), /* 0x14 */
1851	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1852	STRENTRY("DataDownRW "), /* 0x16 */
1853	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1854	STRENTRY("CodeEO "), /* 0x18 */
1855	STRENTRY("CodeEO Accessed "), /* 0x19 */
1856	STRENTRY("CodeER "), /* 0x1a */
1857	STRENTRY("CodeER Accessed "), /* 0x1b */
1858	STRENTRY("CodeConfEO "), /* 0x1c */
1859	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1860	STRENTRY("CodeConfER "), /* 0x1e */
1861	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1862	# undef SYSENTRY
1863	};
1864	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1865	char szMsg[128];
1866	char *psz = &szMsg[0];
1867	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1868	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1869	psz += s_aTypes[i].cch;
1870
1871	if (pDesc->Gen.u1Present)
1872	ADD_STR(psz, "Present ");
1873	else
1874	ADD_STR(psz, "Not-Present ");
1875	# if HC_ARCH_BITS == 64
1876	if (pDesc->Gen.u1Long)
1877	ADD_STR(psz, "64-bit ");
1878	else
1879	ADD_STR(psz, "Comp ");
1880	# else
1881	if (pDesc->Gen.u1Granularity)
1882	ADD_STR(psz, "Page ");
1883	if (pDesc->Gen.u1DefBig)
1884	ADD_STR(psz, "32-bit ");
1885	else
1886	ADD_STR(psz, "16-bit ");
1887	# endif
1888	# undef ADD_STR
1889	*psz = '\0';
1890
1891	/*
1892	* Limit and Base and format the output.
1893	*/
1894	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1895
1896	# if HC_ARCH_BITS == 64
1897	uint64_t u32Base = X86DESC64_BASE(pDesc);
1898	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1899	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1900	# else
1901	uint32_t u32Base = X86DESC_BASE(pDesc);
1902	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1903	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1904	# endif
1905	}
1906
1907
1908	/**
1909	* Formats a full register dump.
1910	*
1911	* @param pVM Pointer to the VM.
1912	* @param pVCpu Pointer to the VMCPU.
1913	* @param pCtx Pointer to the CPU context.
1914	*/
1915	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1916	{
1917	NOREF(pVM);
1918
1919	/*
1920	* Format the flags.
1921	*/
1922	static struct
1923	{
1924	const char pszSet; const char pszClear; uint32_t fFlag;
1925	} const s_aFlags[] =
1926	{
1927	{ "vip", NULL, X86_EFL_VIP },
1928	{ "vif", NULL, X86_EFL_VIF },
1929	{ "ac", NULL, X86_EFL_AC },
1930	{ "vm", NULL, X86_EFL_VM },
1931	{ "rf", NULL, X86_EFL_RF },
1932	{ "nt", NULL, X86_EFL_NT },
1933	{ "ov", "nv", X86_EFL_OF },
1934	{ "dn", "up", X86_EFL_DF },
1935	{ "ei", "di", X86_EFL_IF },
1936	{ "tf", NULL, X86_EFL_TF },
1937	{ "nt", "pl", X86_EFL_SF },
1938	{ "nz", "zr", X86_EFL_ZF },
1939	{ "ac", "na", X86_EFL_AF },
1940	{ "po", "pe", X86_EFL_PF },
1941	{ "cy", "nc", X86_EFL_CF },
1942	};
1943	char szEFlags[80];
1944	char *psz = szEFlags;
1945	uint32_t uEFlags = pCtx->eflags.u32;
1946	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1947	{
1948	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1949	if (pszAdd)
1950	{
1951	strcpy(psz, pszAdd);
1952	psz += strlen(pszAdd);
1953	*psz++ = ' ';
1954	}
1955	}
1956	psz[-1] = '\0';
1957
1958
1959	/*
1960	* Format the registers.
1961	*/
1962	if (CPUMIsGuestIn64BitCode(pVCpu))
1963	{
1964	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1965	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1966	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1967	"r14=%016RX64 r15=%016RX64\n"
1968	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1969	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1970	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1971	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1972	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1973	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1974	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1975	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1976	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1977	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1978	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1979	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1980	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1981	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1982	,
1983	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1984	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1985	pCtx->r14, pCtx->r15,
1986	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1987	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1988	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1989	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1990	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1991	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1992	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1993	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1994	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1995	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1996	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1997	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1998	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1999	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2000	}
2001	else
2002	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2003	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2004	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2005	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2006	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2007	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2008	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2009	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2010	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2011	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2012	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2013	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2014	,
2015	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2016	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
2017	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2018	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2019	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2020	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2021	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2022	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2023	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
2024	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2025	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2026	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2027
2028	Log(("FPU:\n"
2029	"FCW=%04x FSW=%04x FTW=%02x\n"
2030	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2031	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2032	,
2033	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2034	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2035	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2036	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2037
2038	Log(("MSR:\n"
2039	"EFER =%016RX64\n"
2040	"PAT =%016RX64\n"
2041	"STAR =%016RX64\n"
2042	"CSTAR =%016RX64\n"
2043	"LSTAR =%016RX64\n"
2044	"SFMASK =%016RX64\n"
2045	"KERNELGSBASE =%016RX64\n",
2046	pCtx->msrEFER,
2047	pCtx->msrPAT,
2048	pCtx->msrSTAR,
2049	pCtx->msrCSTAR,
2050	pCtx->msrLSTAR,
2051	pCtx->msrSFMASK,
2052	pCtx->msrKERNELGSBASE));
2053	}
2054
2055	#endif /* VBOX_STRICT */
2056

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 52023

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