HMR0.cpp@ 55384

Last change on this file since 55384 was 55129, checked in by vboxsync, 10 years ago
VMM/GIM: Allow dynamic enabling of #UD traps and per-VCPU hypercalls.
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1	/* $Id: HMR0.cpp 55129 2015-04-08 11:31:47Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <VBox/vmm/hm.h>
23	#include <VBox/vmm/pgm.h>
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/hm_vmx.h>
27	#include <VBox/vmm/hm_svm.h>
28	#include <VBox/vmm/gim.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState, (PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost, void *pvArg));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM ,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	/** @todo This isn't used for anything relevant. Remove later? */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** VMX MSR values */
123	VMXMSRS Msrs;
124
125	/* Last instruction error */
126	uint32_t ulLastInstrError;
127	} vmx;
128
129	/** AMD-V information. */
130	struct
131	{
132	/* HWCR MSR (for diagnostics) */
133	uint64_t u64MsrHwcr;
134
135	/** SVM revision. */
136	uint32_t u32Rev;
137
138	/** SVM feature bits from cpuid 0x8000000a */
139	uint32_t u32Features;
140
141	/** Set by us to indicate SVM is supported by the CPU. */
142	bool fSupported;
143	} svm;
144	/** Saved error from detection */
145	int32_t lLastError;
146
147	struct
148	{
149	uint32_t u32AMDFeatureECX;
150	uint32_t u32AMDFeatureEDX;
151	} cpuid;
152
153	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
154	* enabled and disabled each time it's used to execute guest code. */
155	bool fGlobalInit;
156	/** Indicates whether the host is suspending or not. We'll refuse a few
157	* actions when the host is being suspended to speed up the suspending and
158	* avoid trouble. */
159	volatile bool fSuspended;
160
161	/** Whether we've already initialized all CPUs.
162	* @remarks We could check the EnableAllCpusOnce state, but this is
163	* simpler and hopefully easier to understand. */
164	bool fEnabled;
165	/** Serialize initialization in HMR0EnableAllCpus. */
166	RTONCE EnableAllCpusOnce;
167	} g_HvmR0;
168
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	/**
212	* Get the CPU ID on which the failure status code was reported.
213	*
214	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
215	* @param pFirstRc The first return code structure.
216	*/
217	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
218	{
219	return pFirstRc->idCpu;
220	}
221	#endif /* VBOX_STRICT */
222
223
224	/** @name Dummy callback handlers.
225	* @{ */
226
227	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
228	{
229	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
234	{
235	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
236	}
237
238	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
239	bool fEnabledBySystem, void *pvArg)
240	{
241	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
242	return VINF_SUCCESS;
243	}
244
245	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
246	{
247	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
252	{
253	NOREF(pVM);
254	return VINF_SUCCESS;
255	}
256
257	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
258	{
259	NOREF(pVM);
260	return VINF_SUCCESS;
261	}
262
263	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
264	{
265	NOREF(pVM);
266	return VINF_SUCCESS;
267	}
268
269	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
270	{
271	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
272	return VINF_SUCCESS;
273	}
274
275	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
276	{
277	NOREF(pVM); NOREF(pVCpu);
278	return VINF_SUCCESS;
279	}
280
281	/** @} */
282
283
284	/**
285	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
286	* Down at the Rate Specified" erratum.
287	*
288	* Errata names and related steppings:
289	* - BA86 - D0.
290	* - AAX65 - C2.
291	* - AAU65 - C2, K0.
292	* - AAO95 - B1.
293	* - AAT59 - C2.
294	* - AAK139 - D0.
295	* - AAM126 - C0, C1, D0.
296	* - AAN92 - B1.
297	* - AAJ124 - C0, D0.
298	*
299	* - AAP86 - B1.
300	*
301	* Steppings: B1, C0, C1, C2, D0, K0.
302	*
303	* @returns true if subject to it, false if not.
304	*/
305	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
306	{
307	uint32_t u = ASMCpuId_EAX(1);
308	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
309	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
310	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
311	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
312	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
313	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
314	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
315	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
316	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
317	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
318	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
319	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
320	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
321	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
322	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
323	)
324	return true;
325	return false;
326	}
327
328
329	/**
330	* Intel specific initialization code.
331	*
332	* @returns VBox status code (will only fail if out of memory).
333	*/
334	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
335	{
336	/*
337	* Check that all the required VT-x features are present.
338	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
339	*/
340	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
341	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
342	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
343	)
344	{
345	/** @todo move this into a separate function. */
346	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
347
348	/*
349	* First try use native kernel API for controlling VT-x.
350	* (This is only supported by some Mac OS X kernels atm.)
351	*/
352	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
353	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
354	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
355	{
356	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
357	if (RT_SUCCESS(rc))
358	{
359	g_HvmR0.vmx.fSupported = true;
360	rc = SUPR0EnableVTx(false /* fEnable */);
361	AssertLogRelRC(rc);
362	}
363	}
364	else
365	{
366	/* We need to check if VT-x has been properly initialized on all
367	CPUs. Some BIOSes do a lousy job. */
368	HMR0FIRSTRC FirstRc;
369	hmR0FirstRcInit(&FirstRc);
370	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
371	if (RT_SUCCESS(g_HvmR0.lLastError))
372	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
373	}
374	if (RT_SUCCESS(g_HvmR0.lLastError))
375	{
376	/* Reread in case it was changed by hmR0InitIntelCpu(). */
377	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
378
379	/*
380	* Read all relevant registers and MSRs.
381	*/
382	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
383	g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
384	g_HvmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
385	g_HvmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
386	g_HvmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
387	g_HvmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
388	g_HvmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
389	g_HvmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
390	g_HvmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
391	g_HvmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
392	g_HvmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
393	g_HvmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
394	g_HvmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
395	/* VPID 16 bits ASID. */
396	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
397
398	if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
399	{
400	g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
401	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
402	g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
403
404	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
405	g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
406	}
407
408	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
409	{
410	/*
411	* Enter root mode
412	*/
413	RTR0MEMOBJ hScatchMemObj;
414	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
415	if (RT_FAILURE(rc))
416	{
417	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
418	return rc;
419	}
420
421	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
422	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
423	ASMMemZeroPage(pvScatchPage);
424
425	/* Set revision dword at the beginning of the structure. */
426	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo);
427
428	/* Make sure we don't get rescheduled to another cpu during this probe. */
429	RTCCUINTREG fFlags = ASMIntDisableFlags();
430
431	/*
432	* Check CR4.VMXE
433	*/
434	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
435	if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
436	{
437	/* In theory this bit could be cleared behind our back. Which would cause
438	#UD faults when we try to execute the VMX instructions... */
439	ASMSetCR4(g_HvmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
440	}
441
442	/*
443	* The only way of checking if we're in VMX root mode or not is to try and enter it.
444	* There is no instruction or control bit that tells us if we're in VMX root mode.
445	* Therefore, try and enter VMX root mode here.
446	*/
447	rc = VMXEnable(HCPhysScratchPage);
448	if (RT_SUCCESS(rc))
449	{
450	g_HvmR0.vmx.fSupported = true;
451	VMXDisable();
452	}
453	else
454	{
455	/*
456	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
457	* it will crash the host when we enter raw mode, because:
458	*
459	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
460	* this bit), and
461	* (b) turning off paging causes a #GP (unavoidable when switching
462	* from long to 32 bits mode or 32 bits to PAE).
463	*
464	* They should fix their code, but until they do we simply refuse to run.
465	*/
466	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
467	Assert(g_HvmR0.vmx.fSupported == false);
468	}
469
470	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
471	if it wasn't so before (some software could incorrectly
472	think it's in VMX mode). */
473	ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
474	ASMSetFlags(fFlags);
475
476	RTR0MemObjFree(hScatchMemObj, false);
477	}
478
479	if (g_HvmR0.vmx.fSupported)
480	{
481	rc = VMXR0GlobalInit();
482	if (RT_FAILURE(rc))
483	g_HvmR0.lLastError = rc;
484
485	/*
486	* Install the VT-x methods.
487	*/
488	g_HvmR0.pfnEnterSession = VMXR0Enter;
489	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
490	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
491	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
492	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
493	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
494	g_HvmR0.pfnInitVM = VMXR0InitVM;
495	g_HvmR0.pfnTermVM = VMXR0TermVM;
496	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
497
498	/*
499	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
500	* Timer Does Not Count Down at the Rate Specified" erratum.
501	*/
502	if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
503	{
504	g_HvmR0.vmx.fUsePreemptTimer = true;
505	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc);
506	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
507	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
508	}
509	}
510	}
511	#ifdef LOG_ENABLED
512	else
513	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
514	#endif
515	}
516	else
517	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
518	return VINF_SUCCESS;
519	}
520
521
522	/**
523	* AMD-specific initialization code.
524	*
525	* @returns VBox status code.
526	*/
527	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
528	{
529	/*
530	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
531	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
532	*/
533	int rc;
534	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
535	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
536	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
537	&& ASMIsValidExtRange(uMaxExtLeaf)
538	&& uMaxExtLeaf >= 0x8000000a
539	)
540	{
541	/* Call the global AMD-V initialization routine. */
542	rc = SVMR0GlobalInit();
543	if (RT_FAILURE(rc))
544	{
545	g_HvmR0.lLastError = rc;
546	return rc;
547	}
548
549	/*
550	* Install the AMD-V methods.
551	*/
552	g_HvmR0.pfnEnterSession = SVMR0Enter;
553	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
554	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
555	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
556	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
557	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
558	g_HvmR0.pfnInitVM = SVMR0InitVM;
559	g_HvmR0.pfnTermVM = SVMR0TermVM;
560	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
561
562	/* Query AMD features. */
563	uint32_t u32Dummy;
564	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
565
566	/*
567	* We need to check if AMD-V has been properly initialized on all CPUs.
568	* Some BIOSes might do a poor job.
569	*/
570	HMR0FIRSTRC FirstRc;
571	hmR0FirstRcInit(&FirstRc);
572	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
573	AssertRC(rc);
574	if (RT_SUCCESS(rc))
575	rc = hmR0FirstRcGetStatus(&FirstRc);
576	#ifndef DEBUG_bird
577	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
578	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
579	#endif
580	if (RT_SUCCESS(rc))
581	{
582	/* Read the HWCR MSR for diagnostics. */
583	g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
584	g_HvmR0.svm.fSupported = true;
585	}
586	else
587	{
588	g_HvmR0.lLastError = rc;
589	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
590	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
591	}
592	}
593	else
594	{
595	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
596	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
597	}
598	return rc;
599	}
600
601
602	/**
603	* Does global Ring-0 HM initialization (at module init).
604	*
605	* @returns VBox status code.
606	*/
607	VMMR0_INT_DECL(int) HMR0Init(void)
608	{
609	/*
610	* Initialize the globals.
611	*/
612	g_HvmR0.fEnabled = false;
613	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
614	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
615	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
616	{
617	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
618	g_HvmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
619	}
620
621	/* Fill in all callbacks with placeholders. */
622	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
623	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
624	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
625	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
626	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
627	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
628	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
629	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
630	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
631
632	/* Default is global VT-x/AMD-V init. */
633	g_HvmR0.fGlobalInit = true;
634
635	/*
636	* Make sure aCpuInfo is big enough for all the CPUs on this system.
637	*/
638	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
639	{
640	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
641	return VERR_TOO_MANY_CPUS;
642	}
643
644	/*
645	* Check for VT-x and AMD-V capabilities.
646	*/
647	int rc;
648	if (ASMHasCpuId())
649	{
650	/* Standard features. */
651	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
652	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
653	if (ASMIsValidStdRange(uMaxLeaf))
654	{
655	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
656	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
657
658	/* Query AMD features. */
659	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
660	if (ASMIsValidExtRange(uMaxExtLeaf))
661	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
662	&g_HvmR0.cpuid.u32AMDFeatureECX,
663	&g_HvmR0.cpuid.u32AMDFeatureEDX);
664	else
665	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
666
667	/* Go to CPU specific initialization code. */
668	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
669	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
670	{
671	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
672	if (RT_FAILURE(rc))
673	return rc;
674	}
675	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
676	{
677	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
678	if (RT_FAILURE(rc))
679	return rc;
680	}
681	else
682	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
683	}
684	else
685	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
686	}
687	else
688	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
689
690	/*
691	* Register notification callbacks that we can use to disable/enable CPUs
692	* when brought offline/online or suspending/resuming.
693	*/
694	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
695	{
696	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
697	AssertRC(rc);
698
699	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
700	AssertRC(rc);
701	}
702
703	/* We return success here because module init shall not fail if HM
704	fails to initialize. */
705	return VINF_SUCCESS;
706	}
707
708
709	/**
710	* Does global Ring-0 HM termination (at module termination).
711	*
712	* @returns VBox status code.
713	*/
714	VMMR0_INT_DECL(int) HMR0Term(void)
715	{
716	int rc;
717	if ( g_HvmR0.vmx.fSupported
718	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
719	{
720	/*
721	* Simple if the host OS manages VT-x.
722	*/
723	Assert(g_HvmR0.fGlobalInit);
724	rc = SUPR0EnableVTx(false /* fEnable */);
725
726	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
727	{
728	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
729	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
730	}
731	}
732	else
733	{
734	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
735	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
736	{
737	/* Doesn't really matter if this fails. */
738	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
739	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
740	}
741	else
742	rc = VINF_SUCCESS;
743
744	/*
745	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
746	*/
747	if (g_HvmR0.fGlobalInit)
748	{
749	HMR0FIRSTRC FirstRc;
750	hmR0FirstRcInit(&FirstRc);
751	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
752	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
753	if (RT_SUCCESS(rc))
754	{
755	rc = hmR0FirstRcGetStatus(&FirstRc);
756	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
757	}
758	}
759
760	/*
761	* Free the per-cpu pages used for VT-x and AMD-V.
762	*/
763	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
764	{
765	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
766	{
767	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
768	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
769	}
770	}
771	}
772
773	/** @todo This needs cleaning up. There's no matching
774	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
775	* should move into their respective modules. */
776	/* Finally, call global VT-x/AMD-V termination. */
777	if (g_HvmR0.vmx.fSupported)
778	VMXR0GlobalTerm();
779	else if (g_HvmR0.svm.fSupported)
780	SVMR0GlobalTerm();
781
782	return rc;
783	}
784
785
786	/**
787	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
788	* on a CPU.
789	*
790	* @param idCpu The identifier for the CPU the function is called on.
791	* @param pvUser1 Pointer to the first RC structure.
792	* @param pvUser2 Ignored.
793	*/
794	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
795	{
796	/** @todo Unify code with SUPR0QueryVTCaps(). */
797	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
798	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
799	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
800	NOREF(idCpu); NOREF(pvUser2);
801
802	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
803	hmR0FirstRcSetStatus(pFirstRc, rc);
804	}
805
806
807	/**
808	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
809	* on a CPU.
810	*
811	* @param idCpu The identifier for the CPU the function is called on.
812	* @param pvUser1 Pointer to the first RC structure.
813	* @param pvUser2 Ignored.
814	*/
815	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
816	{
817	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
818	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
819	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
820	NOREF(idCpu); NOREF(pvUser2);
821
822	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
823	hmR0FirstRcSetStatus(pFirstRc, rc);
824	}
825
826
827	/**
828	* Enable VT-x or AMD-V on the current CPU
829	*
830	* @returns VBox status code.
831	* @param pVM Pointer to the VM (can be NULL).
832	* @param idCpu The identifier for the CPU the function is called on.
833	*
834	* @remarks Maybe called with interrupts disabled!
835	*/
836	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
837	{
838	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
839
840	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
841	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
842	Assert(!pCpu->fConfigured);
843	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
844
845	pCpu->idCpu = idCpu;
846	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
847
848	int rc;
849	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
850	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HvmR0.vmx.Msrs);
851	else
852	{
853	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
854	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
855	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0 /* iPage */);
856
857	if (g_HvmR0.vmx.fSupported)
858	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
859	else
860	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
861	}
862	AssertRC(rc);
863	if (RT_SUCCESS(rc))
864	pCpu->fConfigured = true;
865
866	return rc;
867	}
868
869
870	/**
871	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
872	*
873	* @param idCpu The identifier for the CPU the function is called on.
874	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
875	* @param pvUser2 The 2nd user argument.
876	*/
877	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
878	{
879	PVM pVM = (PVM)pvUser1; /* can be NULL! */
880	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
881	AssertReturnVoid(g_HvmR0.fGlobalInit);
882	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
883	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
884	}
885
886
887	/**
888	* RTOnce callback employed by HMR0EnableAllCpus.
889	*
890	* @returns VBox status code.
891	* @param pvUser Pointer to the VM.
892	* @param pvUserIgnore NULL, ignored.
893	*/
894	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
895	{
896	PVM pVM = (PVM)pvUser;
897
898	/*
899	* Indicate that we've initialized.
900	*
901	* Note! There is a potential race between this function and the suspend
902	* notification. Kind of unlikely though, so ignored for now.
903	*/
904	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
905	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
906
907	/*
908	* The global init variable is set by the first VM.
909	*/
910	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
911
912	#ifdef VBOX_STRICT
913	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
914	{
915	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
916	Assert(!g_HvmR0.aCpuInfo[i].fConfigured);
917	Assert(!g_HvmR0.aCpuInfo[i].cTlbFlushes);
918	Assert(!g_HvmR0.aCpuInfo[i].uCurrentAsid);
919	}
920	#endif
921
922	int rc;
923	if ( g_HvmR0.vmx.fSupported
924	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
925	{
926	/*
927	* Global VT-x initialization API (only darwin for now).
928	*/
929	rc = SUPR0EnableVTx(true /* fEnable */);
930	if (RT_SUCCESS(rc))
931	{
932	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
933	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
934	}
935	else
936	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
937	}
938	else
939	{
940	/*
941	* We're doing the job ourselves.
942	*/
943	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
944	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
945	{
946	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
947
948	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
949	{
950	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
951	AssertLogRelRCReturn(rc, rc);
952
953	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
954	ASMMemZeroPage(pvR0);
955	}
956	}
957
958	rc = VINF_SUCCESS;
959	}
960
961	if ( RT_SUCCESS(rc)
962	&& g_HvmR0.fGlobalInit)
963	{
964	/* First time, so initialize each cpu/core. */
965	HMR0FIRSTRC FirstRc;
966	hmR0FirstRcInit(&FirstRc);
967	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
968	if (RT_SUCCESS(rc))
969	rc = hmR0FirstRcGetStatus(&FirstRc);
970	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
971	}
972
973	return rc;
974	}
975
976
977	/**
978	* Sets up HM on all cpus.
979	*
980	* @returns VBox status code.
981	* @param pVM Pointer to the VM.
982	*/
983	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
984	{
985	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
986	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
987	return VERR_HM_SUSPEND_PENDING;
988
989	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
990	}
991
992
993	/**
994	* Disable VT-x or AMD-V on the current CPU.
995	*
996	* @returns VBox status code.
997	* @param idCpu The identifier for the CPU this function is called on.
998	*
999	* @remarks Must be called with preemption disabled.
1000	*/
1001	static int hmR0DisableCpu(RTCPUID idCpu)
1002	{
1003	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1004
1005	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1006	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1007	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1008	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1009	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1010	AssertRelease(idCpu == RTMpCpuId());
1011
1012	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1013	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1014
1015	int rc;
1016	if (pCpu->fConfigured)
1017	{
1018	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1019	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1020
1021	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1022	AssertRCReturn(rc, rc);
1023
1024	pCpu->fConfigured = false;
1025	pCpu->idCpu = NIL_RTCPUID;
1026	}
1027	else
1028	rc = VINF_SUCCESS; /* nothing to do */
1029	return rc;
1030	}
1031
1032
1033	/**
1034	* Worker function passed to RTMpOnAll() that is to be called on the target
1035	* CPUs.
1036	*
1037	* @param idCpu The identifier for the CPU the function is called on.
1038	* @param pvUser1 The 1st user argument.
1039	* @param pvUser2 Opaque pointer to the FirstRc.
1040	*/
1041	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1042	{
1043	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1044	AssertReturnVoid(g_HvmR0.fGlobalInit);
1045	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1046	}
1047
1048
1049	/**
1050	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1051	* CPU.
1052	*
1053	* @param idCpu The identifier for the CPU the function is called on.
1054	* @param pvUser1 Null, not used.
1055	* @param pvUser2 Null, not used.
1056	*/
1057	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1058	{
1059	NOREF(pvUser1);
1060	NOREF(pvUser2);
1061	hmR0DisableCpu(idCpu);
1062	}
1063
1064
1065	/**
1066	* Callback function invoked when a cpu goes online or offline.
1067	*
1068	* @param enmEvent The Mp event.
1069	* @param idCpu The identifier for the CPU the function is called on.
1070	* @param pvData Opaque data (PVM pointer).
1071	*/
1072	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1073	{
1074	NOREF(pvData);
1075
1076	/*
1077	* We only care about uninitializing a CPU that is going offline. When a
1078	* CPU comes online, the initialization is done lazily in HMR0Enter().
1079	*/
1080	switch (enmEvent)
1081	{
1082	case RTMPEVENT_OFFLINE:
1083	{
1084	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1085	RTThreadPreemptDisable(&PreemptState);
1086	if (idCpu == RTMpCpuId())
1087	{
1088	int rc = hmR0DisableCpu(idCpu);
1089	AssertRC(rc);
1090	RTThreadPreemptRestore(&PreemptState);
1091	}
1092	else
1093	{
1094	RTThreadPreemptRestore(&PreemptState);
1095	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1096	}
1097	break;
1098	}
1099
1100	default:
1101	break;
1102	}
1103	}
1104
1105
1106	/**
1107	* Called whenever a system power state change occurs.
1108	*
1109	* @param enmEvent The Power event.
1110	* @param pvUser User argument.
1111	*/
1112	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1113	{
1114	NOREF(pvUser);
1115	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1116
1117	#ifdef LOG_ENABLED
1118	if (enmEvent == RTPOWEREVENT_SUSPEND)
1119	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1120	else
1121	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1122	#endif
1123
1124	if (enmEvent == RTPOWEREVENT_SUSPEND)
1125	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1126
1127	if (g_HvmR0.fEnabled)
1128	{
1129	int rc;
1130	HMR0FIRSTRC FirstRc;
1131	hmR0FirstRcInit(&FirstRc);
1132
1133	if (enmEvent == RTPOWEREVENT_SUSPEND)
1134	{
1135	if (g_HvmR0.fGlobalInit)
1136	{
1137	/* Turn off VT-x or AMD-V on all CPUs. */
1138	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1139	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1140	}
1141	/* else nothing to do here for the local init case */
1142	}
1143	else
1144	{
1145	/* Reinit the CPUs from scratch as the suspend state might have
1146	messed with the MSRs. (lousy BIOSes as usual) */
1147	if (g_HvmR0.vmx.fSupported)
1148	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1149	else
1150	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1151	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1152	if (RT_SUCCESS(rc))
1153	rc = hmR0FirstRcGetStatus(&FirstRc);
1154	#ifdef LOG_ENABLED
1155	if (RT_FAILURE(rc))
1156	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1157	#endif
1158	if (g_HvmR0.fGlobalInit)
1159	{
1160	/* Turn VT-x or AMD-V back on on all CPUs. */
1161	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1162	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1163	}
1164	/* else nothing to do here for the local init case */
1165	}
1166	}
1167
1168	if (enmEvent == RTPOWEREVENT_RESUME)
1169	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1170	}
1171
1172
1173	/**
1174	* Does ring-0 per-VM HM initialization.
1175	*
1176	* This will copy HM global into the VM structure and call the CPU specific
1177	* init routine which will allocate resources for each virtual CPU and such.
1178	*
1179	* @returns VBox status code.
1180	* @param pVM Pointer to the VM.
1181	*
1182	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1183	* vmR3InitRing3().
1184	*/
1185	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1186	{
1187	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1188
1189	#ifdef LOG_ENABLED
1190	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1191	#endif
1192
1193	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1194	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1195	return VERR_HM_SUSPEND_PENDING;
1196
1197	/*
1198	* Copy globals to the VM structure.
1199	*/
1200	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1201	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1202
1203	pVM->hm.s.vmx.fUsePreemptTimer &= g_HvmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1204	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1205	pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4;
1206	pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer;
1207	pVM->hm.s.vmx.Msrs = g_HvmR0.vmx.Msrs;
1208	pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr;
1209	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1210	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1211	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1212	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1213	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1214	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1215
1216	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1217	{
1218	pVM->hm.s.cMaxResumeLoops = 1024;
1219	if (RTThreadPreemptIsPendingTrusty())
1220	pVM->hm.s.cMaxResumeLoops = 8192;
1221	}
1222
1223	/*
1224	* Initialize some per CPU fields.
1225	*/
1226	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1227	{
1228	PVMCPU pVCpu = &pVM->aCpus[i];
1229	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1230	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1231	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1232
1233	/* We'll aways increment this the first time (host uses ASID 0). */
1234	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1235	}
1236
1237	pVM->hm.s.uHostKernelFeatures = SUPR0GetKernelFeatures();
1238
1239	/*
1240	* Call the hardware specific initialization method.
1241	*/
1242	return g_HvmR0.pfnInitVM(pVM);
1243	}
1244
1245
1246	/**
1247	* Does ring-0 per VM HM termination.
1248	*
1249	* @returns VBox status code.
1250	* @param pVM Pointer to the VM.
1251	*/
1252	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1253	{
1254	Log(("HMR0TermVM: %p\n", pVM));
1255	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1256
1257	/*
1258	* Call the hardware specific method.
1259	*
1260	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1261	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1262	*/
1263	return g_HvmR0.pfnTermVM(pVM);
1264	}
1265
1266
1267	/**
1268	* Sets up a VT-x or AMD-V session.
1269	*
1270	* This is mostly about setting up the hardware VM state.
1271	*
1272	* @returns VBox status code.
1273	* @param pVM Pointer to the VM.
1274	*/
1275	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1276	{
1277	Log(("HMR0SetupVM: %p\n", pVM));
1278	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1279
1280	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1281	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1282
1283	/* On first entry we'll sync everything. */
1284	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1285	HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1286
1287	/*
1288	* Call the hardware specific setup VM method. This requires the CPU to be
1289	* enabled for AMD-V/VT-x and preemption to be prevented.
1290	*/
1291	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1292	RTThreadPreemptDisable(&PreemptState);
1293	RTCPUID idCpu = RTMpCpuId();
1294
1295	/* Enable VT-x or AMD-V if local init is required. */
1296	int rc;
1297	if (!g_HvmR0.fGlobalInit)
1298	{
1299	rc = hmR0EnableCpu(pVM, idCpu);
1300	AssertRCReturnStmt(rc, RTThreadPreemptRestore(&PreemptState), rc);
1301	}
1302
1303	/* Setup VT-x or AMD-V. */
1304	rc = g_HvmR0.pfnSetupVM(pVM);
1305
1306	/* Disable VT-x or AMD-V if local init was done before. */
1307	if (!g_HvmR0.fGlobalInit)
1308	{
1309	int rc2 = hmR0DisableCpu(idCpu);
1310	AssertRC(rc2);
1311	}
1312
1313	RTThreadPreemptRestore(&PreemptState);
1314	return rc;
1315	}
1316
1317
1318	/**
1319	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1320	* required for entering HM context.
1321	*
1322	* @returns VBox status code.
1323	* @param pvCpu Pointer to the VMCPU.
1324	*
1325	* @remarks No-long-jump zone!!!
1326	*/
1327	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1328	{
1329	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1330
1331	int rc = VINF_SUCCESS;
1332	RTCPUID idCpu = RTMpCpuId();
1333	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1334	AssertPtr(pCpu);
1335
1336	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1337	if (!pCpu->fConfigured)
1338	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1339
1340	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1341	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1342
1343	Assert(pCpu->idCpu == idCpu && pCpu->idCpu != NIL_RTCPUID);
1344	pVCpu->hm.s.idEnteredCpu = idCpu;
1345	return rc;
1346	}
1347
1348
1349	/**
1350	* Enters the VT-x or AMD-V session.
1351	*
1352	* @returns VBox status code.
1353	* @param pVM Pointer to the VM.
1354	* @param pVCpu Pointer to the VMCPU.
1355	*
1356	* @remarks This is called with preemption disabled.
1357	*/
1358	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1359	{
1360	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1361	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1362	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1363
1364	/* Load the bare minimum state required for entering HM. */
1365	int rc = HMR0EnterCpu(pVCpu);
1366	AssertRCReturn(rc, rc);
1367
1368	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1369	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1370	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1371	#endif
1372
1373	RTCPUID idCpu = RTMpCpuId();
1374	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1375	Assert(pCpu);
1376	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1377
1378	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1379	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1380
1381	/* Load the host-state as we may be resuming code after a longjmp and quite
1382	possibly now be scheduled on a different CPU. */
1383	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1384	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1385
1386	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1387	if (fStartedSet)
1388	PGMRZDynMapReleaseAutoSet(pVCpu);
1389	#endif
1390
1391	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1392	if (RT_FAILURE(rc))
1393	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1394	return rc;
1395	}
1396
1397
1398	/**
1399	* Deinitializes the bare minimum state used for HM context and if necessary
1400	* disable HM on the CPU.
1401	*
1402	* @returns VBox status code.
1403	* @param pVCpu Pointer to the VMCPU.
1404	*
1405	* @remarks No-long-jump zone!!!
1406	*/
1407	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1408	{
1409	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1410	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1411
1412	RTCPUID idCpu = RTMpCpuId();
1413	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1414
1415	if ( !g_HvmR0.fGlobalInit
1416	&& pCpu->fConfigured)
1417	{
1418	int rc = hmR0DisableCpu(idCpu);
1419	AssertRCReturn(rc, rc);
1420	Assert(!pCpu->fConfigured);
1421	Assert(pCpu->idCpu == NIL_RTCPUID);
1422
1423	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1424	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1425	}
1426
1427	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1428	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1429
1430	return VINF_SUCCESS;
1431	}
1432
1433
1434	/**
1435	* Thread-context hook for HM.
1436	*
1437	* @param enmEvent The thread-context event.
1438	* @param pvUser Opaque pointer to the VMCPU.
1439	*/
1440	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1441	{
1442	PVMCPU pVCpu = (PVMCPU)pvUser;
1443	Assert(pVCpu);
1444	Assert(g_HvmR0.pfnThreadCtxCallback);
1445
1446	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1447	}
1448
1449
1450	/**
1451	* Runs guest code in a hardware accelerated VM.
1452	*
1453	* @returns VBox status code.
1454	* @param pVM Pointer to the VM.
1455	* @param pVCpu Pointer to the VMCPU.
1456	*
1457	* @remarks Can be called with preemption enabled if thread-context hooks are
1458	* used!!!
1459	*/
1460	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1461	{
1462	#ifdef VBOX_STRICT
1463	/* With thread-context hooks we would be running this code with preemption enabled. */
1464	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1465	{
1466	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1467	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1468	Assert(pCpu->fConfigured);
1469	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1470	}
1471	#endif
1472
1473	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1474	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1475	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1476	PGMRZDynMapStartAutoSet(pVCpu);
1477	#endif
1478
1479	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1480
1481	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1482	PGMRZDynMapReleaseAutoSet(pVCpu);
1483	#endif
1484	return rc;
1485	}
1486
1487	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1488
1489	/**
1490	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1491	*
1492	* @returns VBox status code.
1493	* @param pVM Pointer to the VM.
1494	* @param pVCpu Pointer to the VMCPU.
1495	* @param pCtx Pointer to the guest CPU context.
1496	*/
1497	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1498	{
1499	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1500	if (pVM->hm.s.vmx.fSupported)
1501	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1502	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1503	}
1504
1505
1506	/**
1507	* Save guest debug state (64 bits guest mode & 32 bits host only)
1508	*
1509	* @returns VBox status code.
1510	* @param pVM Pointer to the VM.
1511	* @param pVCpu Pointer to the VMCPU.
1512	* @param pCtx Pointer to the guest CPU context.
1513	*/
1514	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1515	{
1516	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1517	if (pVM->hm.s.vmx.fSupported)
1518	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1519	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1520	}
1521
1522
1523	/**
1524	* Test the 32->64 bits switcher.
1525	*
1526	* @returns VBox status code.
1527	* @param pVM Pointer to the VM.
1528	*/
1529	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1530	{
1531	PVMCPU pVCpu = &pVM->aCpus[0];
1532	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1533	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1534	int rc;
1535
1536	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1537	if (pVM->hm.s.vmx.fSupported)
1538	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1539	else
1540	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1541	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1542
1543	return rc;
1544	}
1545
1546	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1547
1548	/**
1549	* Returns suspend status of the host.
1550	*
1551	* @returns Suspend pending or not.
1552	*/
1553	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1554	{
1555	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1556	}
1557
1558
1559	/**
1560	* Returns the cpu structure for the current cpu.
1561	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1562	*
1563	* @returns The cpu structure pointer.
1564	*/
1565	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1566	{
1567	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1568	RTCPUID idCpu = RTMpCpuId();
1569	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1570	return &g_HvmR0.aCpuInfo[idCpu];
1571	}
1572
1573
1574	/**
1575	* Returns the cpu structure for the current cpu.
1576	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1577	*
1578	* @returns The cpu structure pointer.
1579	* @param idCpu id of the VCPU.
1580	*/
1581	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1582	{
1583	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1584	return &g_HvmR0.aCpuInfo[idCpu];
1585	}
1586
1587
1588	/**
1589	* Save a pending IO read.
1590	*
1591	* @param pVCpu Pointer to the VMCPU.
1592	* @param GCPtrRip Address of IO instruction.
1593	* @param GCPtrRipNext Address of the next instruction.
1594	* @param uPort Port address.
1595	* @param uAndVal AND mask for saving the result in eax.
1596	* @param cbSize Read size.
1597	*/
1598	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1599	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1600	{
1601	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1602	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1603	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1604	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1605	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1606	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1607	return;
1608	}
1609
1610
1611	/**
1612	* Save a pending IO write.
1613	*
1614	* @param pVCpu Pointer to the VMCPU.
1615	* @param GCPtrRIP Address of IO instruction.
1616	* @param uPort Port address.
1617	* @param uAndVal AND mask for fetching the result from eax.
1618	* @param cbSize Read size.
1619	*/
1620	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1621	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1622	{
1623	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1624	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1625	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1626	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1627	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1628	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1629	return;
1630	}
1631
1632
1633	/**
1634	* Raw-mode switcher hook - disable VT-x if it's active and the current
1635	* switcher turns off paging.
1636	*
1637	* @returns VBox status code.
1638	* @param pVM Pointer to the VM.
1639	* @param enmSwitcher The switcher we're about to use.
1640	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1641	*/
1642	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1643	{
1644	NOREF(pVM);
1645
1646	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1647
1648	*pfVTxDisabled = false;
1649
1650	/* No such issues with AMD-V */
1651	if (!g_HvmR0.vmx.fSupported)
1652	return VINF_SUCCESS;
1653
1654	/* Check if the swithcing we're up to is safe. */
1655	switch (enmSwitcher)
1656	{
1657	case VMMSWITCHER_32_TO_32:
1658	case VMMSWITCHER_PAE_TO_PAE:
1659	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1660
1661	case VMMSWITCHER_32_TO_PAE:
1662	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1663	case VMMSWITCHER_AMD64_TO_32:
1664	case VMMSWITCHER_AMD64_TO_PAE:
1665	break; /* unsafe switchers */
1666
1667	default:
1668	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1669	}
1670
1671	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1672	regardless of whether we're currently using VT-x or not. */
1673	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1674	{
1675	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1676	return VINF_SUCCESS;
1677	}
1678
1679	/** @todo Check if this code is presumtive wrt other VT-x users on the
1680	* system... */
1681
1682	/* Nothing to do if we haven't enabled VT-x. */
1683	if (!g_HvmR0.fEnabled)
1684	return VINF_SUCCESS;
1685
1686	/* Local init implies the CPU is currently not in VMX root mode. */
1687	if (!g_HvmR0.fGlobalInit)
1688	return VINF_SUCCESS;
1689
1690	/* Ok, disable VT-x. */
1691	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1692	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1693
1694	*pfVTxDisabled = true;
1695	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1696	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1697	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1698	}
1699
1700
1701	/**
1702	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1703	* switcher turned off paging.
1704	*
1705	* @param pVM Pointer to the VM.
1706	* @param fVTxDisabled Whether VT-x was disabled or not.
1707	*/
1708	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1709	{
1710	Assert(!ASMIntAreEnabled());
1711
1712	if (!fVTxDisabled)
1713	return; /* nothing to do */
1714
1715	Assert(g_HvmR0.vmx.fSupported);
1716	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1717	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1718	else
1719	{
1720	Assert(g_HvmR0.fEnabled);
1721	Assert(g_HvmR0.fGlobalInit);
1722
1723	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1724	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1725
1726	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1727	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1728	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
1729	}
1730	}
1731
1732	#ifdef VBOX_STRICT
1733
1734	/**
1735	* Dumps a descriptor.
1736	*
1737	* @param pDesc Descriptor to dump.
1738	* @param Sel Selector number.
1739	* @param pszMsg Message to prepend the log entry with.
1740	*/
1741	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1742	{
1743	/*
1744	* Make variable description string.
1745	*/
1746	static struct
1747	{
1748	unsigned cch;
1749	const char *psz;
1750	} const s_aTypes[32] =
1751	{
1752	# define STRENTRY(str) { sizeof(str) - 1, str }
1753
1754	/* system */
1755	# if HC_ARCH_BITS == 64
1756	STRENTRY("Reserved0 "), /* 0x00 */
1757	STRENTRY("Reserved1 "), /* 0x01 */
1758	STRENTRY("LDT "), /* 0x02 */
1759	STRENTRY("Reserved3 "), /* 0x03 */
1760	STRENTRY("Reserved4 "), /* 0x04 */
1761	STRENTRY("Reserved5 "), /* 0x05 */
1762	STRENTRY("Reserved6 "), /* 0x06 */
1763	STRENTRY("Reserved7 "), /* 0x07 */
1764	STRENTRY("Reserved8 "), /* 0x08 */
1765	STRENTRY("TSS64Avail "), /* 0x09 */
1766	STRENTRY("ReservedA "), /* 0x0a */
1767	STRENTRY("TSS64Busy "), /* 0x0b */
1768	STRENTRY("Call64 "), /* 0x0c */
1769	STRENTRY("ReservedD "), /* 0x0d */
1770	STRENTRY("Int64 "), /* 0x0e */
1771	STRENTRY("Trap64 "), /* 0x0f */
1772	# else
1773	STRENTRY("Reserved0 "), /* 0x00 */
1774	STRENTRY("TSS16Avail "), /* 0x01 */
1775	STRENTRY("LDT "), /* 0x02 */
1776	STRENTRY("TSS16Busy "), /* 0x03 */
1777	STRENTRY("Call16 "), /* 0x04 */
1778	STRENTRY("Task "), /* 0x05 */
1779	STRENTRY("Int16 "), /* 0x06 */
1780	STRENTRY("Trap16 "), /* 0x07 */
1781	STRENTRY("Reserved8 "), /* 0x08 */
1782	STRENTRY("TSS32Avail "), /* 0x09 */
1783	STRENTRY("ReservedA "), /* 0x0a */
1784	STRENTRY("TSS32Busy "), /* 0x0b */
1785	STRENTRY("Call32 "), /* 0x0c */
1786	STRENTRY("ReservedD "), /* 0x0d */
1787	STRENTRY("Int32 "), /* 0x0e */
1788	STRENTRY("Trap32 "), /* 0x0f */
1789	# endif
1790	/* non system */
1791	STRENTRY("DataRO "), /* 0x10 */
1792	STRENTRY("DataRO Accessed "), /* 0x11 */
1793	STRENTRY("DataRW "), /* 0x12 */
1794	STRENTRY("DataRW Accessed "), /* 0x13 */
1795	STRENTRY("DataDownRO "), /* 0x14 */
1796	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1797	STRENTRY("DataDownRW "), /* 0x16 */
1798	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1799	STRENTRY("CodeEO "), /* 0x18 */
1800	STRENTRY("CodeEO Accessed "), /* 0x19 */
1801	STRENTRY("CodeER "), /* 0x1a */
1802	STRENTRY("CodeER Accessed "), /* 0x1b */
1803	STRENTRY("CodeConfEO "), /* 0x1c */
1804	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1805	STRENTRY("CodeConfER "), /* 0x1e */
1806	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1807	# undef SYSENTRY
1808	};
1809	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1810	char szMsg[128];
1811	char *psz = &szMsg[0];
1812	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1813	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1814	psz += s_aTypes[i].cch;
1815
1816	if (pDesc->Gen.u1Present)
1817	ADD_STR(psz, "Present ");
1818	else
1819	ADD_STR(psz, "Not-Present ");
1820	# if HC_ARCH_BITS == 64
1821	if (pDesc->Gen.u1Long)
1822	ADD_STR(psz, "64-bit ");
1823	else
1824	ADD_STR(psz, "Comp ");
1825	# else
1826	if (pDesc->Gen.u1Granularity)
1827	ADD_STR(psz, "Page ");
1828	if (pDesc->Gen.u1DefBig)
1829	ADD_STR(psz, "32-bit ");
1830	else
1831	ADD_STR(psz, "16-bit ");
1832	# endif
1833	# undef ADD_STR
1834	*psz = '\0';
1835
1836	/*
1837	* Limit and Base and format the output.
1838	*/
1839	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1840
1841	# if HC_ARCH_BITS == 64
1842	uint64_t u32Base = X86DESC64_BASE(pDesc);
1843	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1844	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1845	# else
1846	uint32_t u32Base = X86DESC_BASE(pDesc);
1847	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1848	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1849	# endif
1850	}
1851
1852
1853	/**
1854	* Formats a full register dump.
1855	*
1856	* @param pVM Pointer to the VM.
1857	* @param pVCpu Pointer to the VMCPU.
1858	* @param pCtx Pointer to the CPU context.
1859	*/
1860	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1861	{
1862	NOREF(pVM);
1863
1864	/*
1865	* Format the flags.
1866	*/
1867	static struct
1868	{
1869	const char pszSet; const char pszClear; uint32_t fFlag;
1870	} const s_aFlags[] =
1871	{
1872	{ "vip", NULL, X86_EFL_VIP },
1873	{ "vif", NULL, X86_EFL_VIF },
1874	{ "ac", NULL, X86_EFL_AC },
1875	{ "vm", NULL, X86_EFL_VM },
1876	{ "rf", NULL, X86_EFL_RF },
1877	{ "nt", NULL, X86_EFL_NT },
1878	{ "ov", "nv", X86_EFL_OF },
1879	{ "dn", "up", X86_EFL_DF },
1880	{ "ei", "di", X86_EFL_IF },
1881	{ "tf", NULL, X86_EFL_TF },
1882	{ "nt", "pl", X86_EFL_SF },
1883	{ "nz", "zr", X86_EFL_ZF },
1884	{ "ac", "na", X86_EFL_AF },
1885	{ "po", "pe", X86_EFL_PF },
1886	{ "cy", "nc", X86_EFL_CF },
1887	};
1888	char szEFlags[80];
1889	char *psz = szEFlags;
1890	uint32_t uEFlags = pCtx->eflags.u32;
1891	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1892	{
1893	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1894	if (pszAdd)
1895	{
1896	strcpy(psz, pszAdd);
1897	psz += strlen(pszAdd);
1898	*psz++ = ' ';
1899	}
1900	}
1901	psz[-1] = '\0';
1902
1903
1904	/*
1905	* Format the registers.
1906	*/
1907	if (CPUMIsGuestIn64BitCode(pVCpu))
1908	{
1909	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1910	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1911	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1912	"r14=%016RX64 r15=%016RX64\n"
1913	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1914	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1915	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1916	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1917	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1918	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1919	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1920	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1921	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1922	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1923	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1924	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1925	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1926	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1927	,
1928	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1929	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1930	pCtx->r14, pCtx->r15,
1931	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1932	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1933	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1934	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1935	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1936	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1937	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1938	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1939	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1940	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1941	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1942	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1943	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1944	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1945	}
1946	else
1947	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1948	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1949	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1950	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1951	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1952	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1953	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1954	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1955	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1956	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1957	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1958	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1959	,
1960	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1961	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1962	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1963	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1964	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1965	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1966	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1967	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1968	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1969	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1970	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1971	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1972
1973	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1974	Log(("FPU:\n"
1975	"FCW=%04x FSW=%04x FTW=%02x\n"
1976	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1977	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1978	,
1979	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1980	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1981	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1982	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1983
1984	Log(("MSR:\n"
1985	"EFER =%016RX64\n"
1986	"PAT =%016RX64\n"
1987	"STAR =%016RX64\n"
1988	"CSTAR =%016RX64\n"
1989	"LSTAR =%016RX64\n"
1990	"SFMASK =%016RX64\n"
1991	"KERNELGSBASE =%016RX64\n",
1992	pCtx->msrEFER,
1993	pCtx->msrPAT,
1994	pCtx->msrSTAR,
1995	pCtx->msrCSTAR,
1996	pCtx->msrLSTAR,
1997	pCtx->msrSFMASK,
1998	pCtx->msrKERNELGSBASE));
1999	}
2000
2001	#endif /* VBOX_STRICT */
2002

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 55384

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