HMR0.cpp@ 56364

Last change on this file since 56364 was 56364, checked in by vboxsync, 10 years ago
VMM/HM: g_HvmR0 -> g_HmR0.
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1	/* $Id: HMR0.cpp 56364 2015-06-11 14:52:57Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <VBox/vmm/hm.h>
23	#include <VBox/vmm/pgm.h>
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/hm_vmx.h>
27	#include <VBox/vmm/hm_svm.h>
28	#include <VBox/vmm/gim.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState, (PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost, void *pvArg));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM ,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	/** @todo This isn't used for anything relevant. Remove later? */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** VMX MSR values */
123	VMXMSRS Msrs;
124
125	/* Last instruction error */
126	uint32_t ulLastInstrError;
127	} vmx;
128
129	/** AMD-V information. */
130	struct
131	{
132	/* HWCR MSR (for diagnostics) */
133	uint64_t u64MsrHwcr;
134
135	/** SVM revision. */
136	uint32_t u32Rev;
137
138	/** SVM feature bits from cpuid 0x8000000a */
139	uint32_t u32Features;
140
141	/** Set by us to indicate SVM is supported by the CPU. */
142	bool fSupported;
143	} svm;
144	/** Saved error from detection */
145	int32_t lLastError;
146
147	struct
148	{
149	uint32_t u32AMDFeatureECX;
150	uint32_t u32AMDFeatureEDX;
151	} cpuid;
152
153	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
154	* enabled and disabled each time it's used to execute guest code. */
155	bool fGlobalInit;
156	/** Indicates whether the host is suspending or not. We'll refuse a few
157	* actions when the host is being suspended to speed up the suspending and
158	* avoid trouble. */
159	volatile bool fSuspended;
160
161	/** Whether we've already initialized all CPUs.
162	* @remarks We could check the EnableAllCpusOnce state, but this is
163	* simpler and hopefully easier to understand. */
164	bool fEnabled;
165	/** Serialize initialization in HMR0EnableAllCpus. */
166	RTONCE EnableAllCpusOnce;
167	} g_HmR0;
168
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	/**
212	* Get the CPU ID on which the failure status code was reported.
213	*
214	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
215	* @param pFirstRc The first return code structure.
216	*/
217	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
218	{
219	return pFirstRc->idCpu;
220	}
221	#endif /* VBOX_STRICT */
222
223
224	/** @name Dummy callback handlers.
225	* @{ */
226
227	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
228	{
229	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
234	{
235	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
236	}
237
238	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
239	bool fEnabledBySystem, void *pvArg)
240	{
241	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
242	return VINF_SUCCESS;
243	}
244
245	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
246	{
247	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
252	{
253	NOREF(pVM);
254	return VINF_SUCCESS;
255	}
256
257	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
258	{
259	NOREF(pVM);
260	return VINF_SUCCESS;
261	}
262
263	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
264	{
265	NOREF(pVM);
266	return VINF_SUCCESS;
267	}
268
269	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
270	{
271	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
272	return VINF_SUCCESS;
273	}
274
275	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
276	{
277	NOREF(pVM); NOREF(pVCpu);
278	return VINF_SUCCESS;
279	}
280
281	/** @} */
282
283
284	/**
285	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
286	* Down at the Rate Specified" erratum.
287	*
288	* Errata names and related steppings:
289	* - BA86 - D0.
290	* - AAX65 - C2.
291	* - AAU65 - C2, K0.
292	* - AAO95 - B1.
293	* - AAT59 - C2.
294	* - AAK139 - D0.
295	* - AAM126 - C0, C1, D0.
296	* - AAN92 - B1.
297	* - AAJ124 - C0, D0.
298	*
299	* - AAP86 - B1.
300	*
301	* Steppings: B1, C0, C1, C2, D0, K0.
302	*
303	* @returns true if subject to it, false if not.
304	*/
305	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
306	{
307	uint32_t u = ASMCpuId_EAX(1);
308	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
309	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
310	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
311	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
312	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
313	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
314	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
315	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
316	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
317	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
318	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
319	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
320	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
321	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
322	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
323	)
324	return true;
325	return false;
326	}
327
328
329	/**
330	* Intel specific initialization code.
331	*
332	* @returns VBox status code (will only fail if out of memory).
333	*/
334	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
335	{
336	/*
337	* Check that all the required VT-x features are present.
338	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
339	*/
340	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
341	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
342	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
343	)
344	{
345	/** @todo move this into a separate function. */
346	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
347
348	/*
349	* First try use native kernel API for controlling VT-x.
350	* (This is only supported by some Mac OS X kernels atm.)
351	*/
352	int rc = g_HmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
353	g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
354	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
355	{
356	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
357	if (RT_SUCCESS(rc))
358	{
359	g_HmR0.vmx.fSupported = true;
360	rc = SUPR0EnableVTx(false /* fEnable */);
361	AssertLogRelRC(rc);
362	}
363	}
364	else
365	{
366	/* We need to check if VT-x has been properly initialized on all
367	CPUs. Some BIOSes do a lousy job. */
368	HMR0FIRSTRC FirstRc;
369	hmR0FirstRcInit(&FirstRc);
370	g_HmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
371	if (RT_SUCCESS(g_HmR0.lLastError))
372	g_HmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
373	}
374	if (RT_SUCCESS(g_HmR0.lLastError))
375	{
376	/* Reread in case it was changed by hmR0InitIntelCpu(). */
377	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
378
379	/*
380	* Read all relevant registers and MSRs.
381	*/
382	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
383	g_HmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
384	g_HmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
385	g_HmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
386	g_HmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
387	g_HmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
388	g_HmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
389	g_HmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
390	g_HmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
391	g_HmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
392	g_HmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
393	g_HmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
394	g_HmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
395	/* VPID 16 bits ASID. */
396	g_HmR0.uMaxAsid = 0x10000; /* exclusive */
397
398	if (g_HmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
399	{
400	g_HmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
401	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
402	g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
403
404	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
405	g_HmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
406	}
407
408	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
409	{
410	/*
411	* Enter root mode
412	*/
413	RTR0MEMOBJ hScatchMemObj;
414	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
415	if (RT_FAILURE(rc))
416	{
417	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
418	return rc;
419	}
420
421	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
422	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
423	ASMMemZeroPage(pvScatchPage);
424
425	/* Set revision dword at the beginning of the structure. */
426	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HmR0.vmx.Msrs.u64BasicInfo);
427
428	/* Make sure we don't get rescheduled to another cpu during this probe. */
429	RTCCUINTREG fFlags = ASMIntDisableFlags();
430
431	/*
432	* Check CR4.VMXE
433	*/
434	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
435	if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
436	{
437	/* In theory this bit could be cleared behind our back. Which would cause
438	#UD faults when we try to execute the VMX instructions... */
439	ASMSetCR4(g_HmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
440	}
441
442	/*
443	* The only way of checking if we're in VMX root mode or not is to try and enter it.
444	* There is no instruction or control bit that tells us if we're in VMX root mode.
445	* Therefore, try and enter VMX root mode here.
446	*/
447	rc = VMXEnable(HCPhysScratchPage);
448	if (RT_SUCCESS(rc))
449	{
450	g_HmR0.vmx.fSupported = true;
451	VMXDisable();
452	}
453	else
454	{
455	/*
456	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
457	* it will crash the host when we enter raw mode, because:
458	*
459	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
460	* this bit), and
461	* (b) turning off paging causes a #GP (unavoidable when switching
462	* from long to 32 bits mode or 32 bits to PAE).
463	*
464	* They should fix their code, but until they do we simply refuse to run.
465	*/
466	g_HmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
467	Assert(g_HmR0.vmx.fSupported == false);
468	}
469
470	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
471	if it wasn't so before (some software could incorrectly
472	think it's in VMX mode). */
473	ASMSetCR4(g_HmR0.vmx.u64HostCr4);
474	ASMSetFlags(fFlags);
475
476	RTR0MemObjFree(hScatchMemObj, false);
477	}
478
479	if (g_HmR0.vmx.fSupported)
480	{
481	rc = VMXR0GlobalInit();
482	if (RT_FAILURE(rc))
483	g_HmR0.lLastError = rc;
484
485	/*
486	* Install the VT-x methods.
487	*/
488	g_HmR0.pfnEnterSession = VMXR0Enter;
489	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
490	g_HmR0.pfnSaveHostState = VMXR0SaveHostState;
491	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
492	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
493	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
494	g_HmR0.pfnInitVM = VMXR0InitVM;
495	g_HmR0.pfnTermVM = VMXR0TermVM;
496	g_HmR0.pfnSetupVM = VMXR0SetupVM;
497
498	/*
499	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
500	* Timer Does Not Count Down at the Rate Specified" erratum.
501	*/
502	if (g_HmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
503	{
504	g_HmR0.vmx.fUsePreemptTimer = true;
505	g_HmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HmR0.vmx.Msrs.u64Misc);
506	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
507	g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
508	}
509	}
510	}
511	#ifdef LOG_ENABLED
512	else
513	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HmR0.lLastError);
514	#endif
515	}
516	else
517	g_HmR0.lLastError = VERR_VMX_NO_VMX;
518	return VINF_SUCCESS;
519	}
520
521
522	/**
523	* AMD-specific initialization code.
524	*
525	* @returns VBox status code.
526	*/
527	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
528	{
529	/*
530	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
531	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
532	*/
533	int rc;
534	if ( (g_HmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
535	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
536	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
537	&& ASMIsValidExtRange(uMaxExtLeaf)
538	&& uMaxExtLeaf >= 0x8000000a
539	)
540	{
541	/* Call the global AMD-V initialization routine. */
542	rc = SVMR0GlobalInit();
543	if (RT_FAILURE(rc))
544	{
545	g_HmR0.lLastError = rc;
546	return rc;
547	}
548
549	/*
550	* Install the AMD-V methods.
551	*/
552	g_HmR0.pfnEnterSession = SVMR0Enter;
553	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
554	g_HmR0.pfnSaveHostState = SVMR0SaveHostState;
555	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
556	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
557	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
558	g_HmR0.pfnInitVM = SVMR0InitVM;
559	g_HmR0.pfnTermVM = SVMR0TermVM;
560	g_HmR0.pfnSetupVM = SVMR0SetupVM;
561
562	/* Query AMD features. */
563	uint32_t u32Dummy;
564	ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
565
566	/*
567	* We need to check if AMD-V has been properly initialized on all CPUs.
568	* Some BIOSes might do a poor job.
569	*/
570	HMR0FIRSTRC FirstRc;
571	hmR0FirstRcInit(&FirstRc);
572	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
573	AssertRC(rc);
574	if (RT_SUCCESS(rc))
575	rc = hmR0FirstRcGetStatus(&FirstRc);
576	#ifndef DEBUG_bird
577	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
578	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
579	#endif
580	if (RT_SUCCESS(rc))
581	{
582	/* Read the HWCR MSR for diagnostics. */
583	g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
584	g_HmR0.svm.fSupported = true;
585	}
586	else
587	{
588	g_HmR0.lLastError = rc;
589	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
590	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
591	}
592	}
593	else
594	{
595	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
596	g_HmR0.lLastError = VERR_SVM_NO_SVM;
597	}
598	return rc;
599	}
600
601
602	/**
603	* Does global Ring-0 HM initialization (at module init).
604	*
605	* @returns VBox status code.
606	*/
607	VMMR0_INT_DECL(int) HMR0Init(void)
608	{
609	/*
610	* Initialize the globals.
611	*/
612	g_HmR0.fEnabled = false;
613	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
614	g_HmR0.EnableAllCpusOnce = s_OnceInit;
615	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
616	{
617	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
618	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
619	}
620
621	/* Fill in all callbacks with placeholders. */
622	g_HmR0.pfnEnterSession = hmR0DummyEnter;
623	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
624	g_HmR0.pfnSaveHostState = hmR0DummySaveHostState;
625	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
626	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
627	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
628	g_HmR0.pfnInitVM = hmR0DummyInitVM;
629	g_HmR0.pfnTermVM = hmR0DummyTermVM;
630	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
631
632	/* Default is global VT-x/AMD-V init. */
633	g_HmR0.fGlobalInit = true;
634
635	/*
636	* Make sure aCpuInfo is big enough for all the CPUs on this system.
637	*/
638	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
639	{
640	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
641	return VERR_TOO_MANY_CPUS;
642	}
643
644	/*
645	* Check for VT-x and AMD-V capabilities.
646	*/
647	int rc;
648	if (ASMHasCpuId())
649	{
650	/* Standard features. */
651	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
652	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
653	if (ASMIsValidStdRange(uMaxLeaf))
654	{
655	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
656	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
657
658	/* Query AMD features. */
659	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
660	if (ASMIsValidExtRange(uMaxExtLeaf))
661	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
662	&g_HmR0.cpuid.u32AMDFeatureECX,
663	&g_HmR0.cpuid.u32AMDFeatureEDX);
664	else
665	g_HmR0.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureEDX = 0;
666
667	/* Go to CPU specific initialization code. */
668	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
669	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
670	{
671	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
672	if (RT_FAILURE(rc))
673	return rc;
674	}
675	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
676	{
677	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
678	if (RT_FAILURE(rc))
679	return rc;
680	}
681	else
682	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
683	}
684	else
685	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
686	}
687	else
688	g_HmR0.lLastError = VERR_HM_NO_CPUID;
689
690	/*
691	* Register notification callbacks that we can use to disable/enable CPUs
692	* when brought offline/online or suspending/resuming.
693	*/
694	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
695	{
696	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
697	AssertRC(rc);
698
699	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
700	AssertRC(rc);
701	}
702
703	/* We return success here because module init shall not fail if HM
704	fails to initialize. */
705	return VINF_SUCCESS;
706	}
707
708
709	/**
710	* Does global Ring-0 HM termination (at module termination).
711	*
712	* @returns VBox status code.
713	*/
714	VMMR0_INT_DECL(int) HMR0Term(void)
715	{
716	int rc;
717	if ( g_HmR0.vmx.fSupported
718	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
719	{
720	/*
721	* Simple if the host OS manages VT-x.
722	*/
723	Assert(g_HmR0.fGlobalInit);
724	rc = SUPR0EnableVTx(false /* fEnable */);
725
726	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
727	{
728	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
729	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
730	}
731	}
732	else
733	{
734	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
735
736	/* Doesn't really matter if this fails. */
737	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
738	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
739
740	/*
741	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
742	*/
743	if (g_HmR0.fGlobalInit)
744	{
745	HMR0FIRSTRC FirstRc;
746	hmR0FirstRcInit(&FirstRc);
747	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
748	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
749	if (RT_SUCCESS(rc))
750	rc = hmR0FirstRcGetStatus(&FirstRc);
751	}
752
753	/*
754	* Free the per-cpu pages used for VT-x and AMD-V.
755	*/
756	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
757	{
758	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
759	{
760	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
761	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
762	}
763	}
764	}
765
766	/** @todo This needs cleaning up. There's no matching
767	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
768	* should move into their respective modules. */
769	/* Finally, call global VT-x/AMD-V termination. */
770	if (g_HmR0.vmx.fSupported)
771	VMXR0GlobalTerm();
772	else if (g_HmR0.svm.fSupported)
773	SVMR0GlobalTerm();
774
775	return rc;
776	}
777
778
779	/**
780	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
781	* on a CPU.
782	*
783	* @param idCpu The identifier for the CPU the function is called on.
784	* @param pvUser1 Pointer to the first RC structure.
785	* @param pvUser2 Ignored.
786	*/
787	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
788	{
789	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
790	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
791	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
792	NOREF(idCpu); NOREF(pvUser2);
793
794	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
795	hmR0FirstRcSetStatus(pFirstRc, rc);
796	}
797
798
799	/**
800	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
801	* on a CPU.
802	*
803	* @param idCpu The identifier for the CPU the function is called on.
804	* @param pvUser1 Pointer to the first RC structure.
805	* @param pvUser2 Ignored.
806	*/
807	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
808	{
809	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
810	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
811	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
812	NOREF(idCpu); NOREF(pvUser2);
813
814	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
815	hmR0FirstRcSetStatus(pFirstRc, rc);
816	}
817
818
819	/**
820	* Enable VT-x or AMD-V on the current CPU
821	*
822	* @returns VBox status code.
823	* @param pVM Pointer to the VM (can be NULL).
824	* @param idCpu The identifier for the CPU the function is called on.
825	*
826	* @remarks Maybe called with interrupts disabled!
827	*/
828	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
829	{
830	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
831
832	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
833	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
834	Assert(!pCpu->fConfigured);
835	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
836
837	pCpu->idCpu = idCpu;
838	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
839
840	int rc;
841	if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
842	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
843	else
844	{
845	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
846	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
847	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0 /* iPage */);
848
849	if (g_HmR0.vmx.fSupported)
850	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HmR0.vmx.Msrs);
851	else
852	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
853	}
854	if (RT_SUCCESS(rc))
855	pCpu->fConfigured = true;
856
857	return rc;
858	}
859
860
861	/**
862	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
863	*
864	* @param idCpu The identifier for the CPU the function is called on.
865	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
866	* @param pvUser2 The 2nd user argument.
867	*/
868	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
869	{
870	PVM pVM = (PVM)pvUser1; /* can be NULL! */
871	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
872	AssertReturnVoid(g_HmR0.fGlobalInit);
873	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
874	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
875	}
876
877
878	/**
879	* RTOnce callback employed by HMR0EnableAllCpus.
880	*
881	* @returns VBox status code.
882	* @param pvUser Pointer to the VM.
883	* @param pvUserIgnore NULL, ignored.
884	*/
885	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
886	{
887	PVM pVM = (PVM)pvUser;
888
889	/*
890	* Indicate that we've initialized.
891	*
892	* Note! There is a potential race between this function and the suspend
893	* notification. Kind of unlikely though, so ignored for now.
894	*/
895	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
896	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
897
898	/*
899	* The global init variable is set by the first VM.
900	*/
901	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
902
903	#ifdef VBOX_STRICT
904	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
905	{
906	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
907	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
908	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
909	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
910	}
911	#endif
912
913	int rc;
914	if ( g_HmR0.vmx.fSupported
915	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
916	{
917	/*
918	* Global VT-x initialization API (only darwin for now).
919	*/
920	rc = SUPR0EnableVTx(true /* fEnable */);
921	if (RT_SUCCESS(rc))
922	{
923	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
924	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
925	}
926	else
927	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
928	}
929	else
930	{
931	/*
932	* We're doing the job ourselves.
933	*/
934	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
935	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
936	{
937	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
938
939	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
940	{
941	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
942	AssertLogRelRCReturn(rc, rc);
943
944	void *pvR0 = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
945	ASMMemZeroPage(pvR0);
946	}
947	}
948
949	rc = VINF_SUCCESS;
950	}
951
952	if ( RT_SUCCESS(rc)
953	&& g_HmR0.fGlobalInit)
954	{
955	/* First time, so initialize each cpu/core. */
956	HMR0FIRSTRC FirstRc;
957	hmR0FirstRcInit(&FirstRc);
958	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
959	if (RT_SUCCESS(rc))
960	rc = hmR0FirstRcGetStatus(&FirstRc);
961	}
962
963	return rc;
964	}
965
966
967	/**
968	* Sets up HM on all cpus.
969	*
970	* @returns VBox status code.
971	* @param pVM Pointer to the VM.
972	*/
973	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
974	{
975	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
976	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
977	return VERR_HM_SUSPEND_PENDING;
978
979	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
980	}
981
982
983	/**
984	* Disable VT-x or AMD-V on the current CPU.
985	*
986	* @returns VBox status code.
987	* @param idCpu The identifier for the CPU this function is called on.
988	*
989	* @remarks Must be called with preemption disabled.
990	*/
991	static int hmR0DisableCpu(RTCPUID idCpu)
992	{
993	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
994
995	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
996	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
997	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
998	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
999	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1000	AssertRelease(idCpu == RTMpCpuId());
1001
1002	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1003	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1004
1005	int rc;
1006	if (pCpu->fConfigured)
1007	{
1008	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1009	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1010
1011	rc = g_HmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1012	AssertRCReturn(rc, rc);
1013
1014	pCpu->fConfigured = false;
1015	pCpu->idCpu = NIL_RTCPUID;
1016	}
1017	else
1018	rc = VINF_SUCCESS; /* nothing to do */
1019	return rc;
1020	}
1021
1022
1023	/**
1024	* Worker function passed to RTMpOnAll() that is to be called on the target
1025	* CPUs.
1026	*
1027	* @param idCpu The identifier for the CPU the function is called on.
1028	* @param pvUser1 The 1st user argument.
1029	* @param pvUser2 Opaque pointer to the FirstRc.
1030	*/
1031	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1032	{
1033	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1034	AssertReturnVoid(g_HmR0.fGlobalInit);
1035	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1036	}
1037
1038
1039	/**
1040	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1041	* CPU.
1042	*
1043	* @param idCpu The identifier for the CPU the function is called on.
1044	* @param pvUser1 Null, not used.
1045	* @param pvUser2 Null, not used.
1046	*/
1047	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1048	{
1049	NOREF(pvUser1);
1050	NOREF(pvUser2);
1051	hmR0DisableCpu(idCpu);
1052	}
1053
1054
1055	/**
1056	* Callback function invoked when a cpu goes online or offline.
1057	*
1058	* @param enmEvent The Mp event.
1059	* @param idCpu The identifier for the CPU the function is called on.
1060	* @param pvData Opaque data (PVM pointer).
1061	*/
1062	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1063	{
1064	NOREF(pvData);
1065	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1066
1067	/*
1068	* We only care about uninitializing a CPU that is going offline. When a
1069	* CPU comes online, the initialization is done lazily in HMR0Enter().
1070	*/
1071	switch (enmEvent)
1072	{
1073	case RTMPEVENT_OFFLINE:
1074	{
1075	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1076	RTThreadPreemptDisable(&PreemptState);
1077	if (idCpu == RTMpCpuId())
1078	{
1079	int rc = hmR0DisableCpu(idCpu);
1080	AssertRC(rc);
1081	RTThreadPreemptRestore(&PreemptState);
1082	}
1083	else
1084	{
1085	RTThreadPreemptRestore(&PreemptState);
1086	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1087	}
1088	break;
1089	}
1090
1091	default:
1092	break;
1093	}
1094	}
1095
1096
1097	/**
1098	* Called whenever a system power state change occurs.
1099	*
1100	* @param enmEvent The Power event.
1101	* @param pvUser User argument.
1102	*/
1103	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1104	{
1105	NOREF(pvUser);
1106	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1107
1108	#ifdef LOG_ENABLED
1109	if (enmEvent == RTPOWEREVENT_SUSPEND)
1110	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1111	else
1112	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1113	#endif
1114
1115	if (enmEvent == RTPOWEREVENT_SUSPEND)
1116	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1117
1118	if (g_HmR0.fEnabled)
1119	{
1120	int rc;
1121	HMR0FIRSTRC FirstRc;
1122	hmR0FirstRcInit(&FirstRc);
1123
1124	if (enmEvent == RTPOWEREVENT_SUSPEND)
1125	{
1126	if (g_HmR0.fGlobalInit)
1127	{
1128	/* Turn off VT-x or AMD-V on all CPUs. */
1129	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1130	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1131	}
1132	/* else nothing to do here for the local init case */
1133	}
1134	else
1135	{
1136	/* Reinit the CPUs from scratch as the suspend state might have
1137	messed with the MSRs. (lousy BIOSes as usual) */
1138	if (g_HmR0.vmx.fSupported)
1139	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1140	else
1141	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1142	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1143	if (RT_SUCCESS(rc))
1144	rc = hmR0FirstRcGetStatus(&FirstRc);
1145	#ifdef LOG_ENABLED
1146	if (RT_FAILURE(rc))
1147	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1148	#endif
1149	if (g_HmR0.fGlobalInit)
1150	{
1151	/* Turn VT-x or AMD-V back on on all CPUs. */
1152	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1153	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1154	}
1155	/* else nothing to do here for the local init case */
1156	}
1157	}
1158
1159	if (enmEvent == RTPOWEREVENT_RESUME)
1160	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1161	}
1162
1163
1164	/**
1165	* Does ring-0 per-VM HM initialization.
1166	*
1167	* This will copy HM global into the VM structure and call the CPU specific
1168	* init routine which will allocate resources for each virtual CPU and such.
1169	*
1170	* @returns VBox status code.
1171	* @param pVM Pointer to the VM.
1172	*
1173	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1174	* vmR3InitRing3().
1175	*/
1176	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1177	{
1178	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1179
1180	#ifdef LOG_ENABLED
1181	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1182	#endif
1183
1184	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1185	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1186	return VERR_HM_SUSPEND_PENDING;
1187
1188	/*
1189	* Copy globals to the VM structure.
1190	*/
1191	pVM->hm.s.vmx.fSupported = g_HmR0.vmx.fSupported;
1192	pVM->hm.s.svm.fSupported = g_HmR0.svm.fSupported;
1193
1194	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1195	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.vmx.cPreemptTimerShift;
1196	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.vmx.u64HostCr4;
1197	pVM->hm.s.vmx.u64HostEfer = g_HmR0.vmx.u64HostEfer;
1198	pVM->hm.s.vmx.Msrs = g_HmR0.vmx.Msrs;
1199	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.svm.u64MsrHwcr;
1200	pVM->hm.s.svm.u32Rev = g_HmR0.svm.u32Rev;
1201	pVM->hm.s.svm.u32Features = g_HmR0.svm.u32Features;
1202	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureECX;
1203	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HmR0.cpuid.u32AMDFeatureEDX;
1204	pVM->hm.s.lLastError = g_HmR0.lLastError;
1205	pVM->hm.s.uMaxAsid = g_HmR0.uMaxAsid;
1206
1207	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1208	{
1209	pVM->hm.s.cMaxResumeLoops = 1024;
1210	if (RTThreadPreemptIsPendingTrusty())
1211	pVM->hm.s.cMaxResumeLoops = 8192;
1212	}
1213
1214	/*
1215	* Initialize some per-VCPU fields.
1216	*/
1217	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1218	{
1219	PVMCPU pVCpu = &pVM->aCpus[i];
1220	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1221	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1222	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1223
1224	/* We'll aways increment this the first time (host uses ASID 0). */
1225	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1226	}
1227
1228	pVM->hm.s.uHostKernelFeatures = SUPR0GetKernelFeatures();
1229
1230	/*
1231	* Call the hardware specific initialization method.
1232	*/
1233	return g_HmR0.pfnInitVM(pVM);
1234	}
1235
1236
1237	/**
1238	* Does ring-0 per VM HM termination.
1239	*
1240	* @returns VBox status code.
1241	* @param pVM Pointer to the VM.
1242	*/
1243	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1244	{
1245	Log(("HMR0TermVM: %p\n", pVM));
1246	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1247
1248	/*
1249	* Call the hardware specific method.
1250	*
1251	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1252	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1253	*/
1254	return g_HmR0.pfnTermVM(pVM);
1255	}
1256
1257
1258	/**
1259	* Sets up a VT-x or AMD-V session.
1260	*
1261	* This is mostly about setting up the hardware VM state.
1262	*
1263	* @returns VBox status code.
1264	* @param pVM Pointer to the VM.
1265	*/
1266	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1267	{
1268	Log(("HMR0SetupVM: %p\n", pVM));
1269	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1270
1271	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1272	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1273
1274	/* On first entry we'll sync everything. */
1275	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1276	HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1277
1278	/*
1279	* Call the hardware specific setup VM method. This requires the CPU to be
1280	* enabled for AMD-V/VT-x and preemption to be prevented.
1281	*/
1282	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1283	RTThreadPreemptDisable(&PreemptState);
1284	RTCPUID idCpu = RTMpCpuId();
1285
1286	/* Enable VT-x or AMD-V if local init is required. */
1287	int rc;
1288	if (!g_HmR0.fGlobalInit)
1289	{
1290	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1291	rc = hmR0EnableCpu(pVM, idCpu);
1292	if (RT_FAILURE(rc))
1293	{
1294	RTThreadPreemptRestore(&PreemptState);
1295	return rc;
1296	}
1297	}
1298
1299	/* Setup VT-x or AMD-V. */
1300	rc = g_HmR0.pfnSetupVM(pVM);
1301
1302	/* Disable VT-x or AMD-V if local init was done before. */
1303	if (!g_HmR0.fGlobalInit)
1304	{
1305	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1306	int rc2 = hmR0DisableCpu(idCpu);
1307	AssertRC(rc2);
1308	}
1309
1310	RTThreadPreemptRestore(&PreemptState);
1311	return rc;
1312	}
1313
1314
1315	/**
1316	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1317	* required for entering HM context.
1318	*
1319	* @returns VBox status code.
1320	* @param pvCpu Pointer to the VMCPU.
1321	*
1322	* @remarks No-long-jump zone!!!
1323	*/
1324	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1325	{
1326	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1327
1328	int rc = VINF_SUCCESS;
1329	RTCPUID idCpu = RTMpCpuId();
1330	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1331	AssertPtr(pCpu);
1332
1333	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1334	if (!pCpu->fConfigured)
1335	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1336
1337	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1338	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1339
1340	Assert(pCpu->idCpu == idCpu && pCpu->idCpu != NIL_RTCPUID);
1341	pVCpu->hm.s.idEnteredCpu = idCpu;
1342	return rc;
1343	}
1344
1345
1346	/**
1347	* Enters the VT-x or AMD-V session.
1348	*
1349	* @returns VBox status code.
1350	* @param pVM Pointer to the VM.
1351	* @param pVCpu Pointer to the VMCPU.
1352	*
1353	* @remarks This is called with preemption disabled.
1354	*/
1355	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1356	{
1357	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1358	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1359	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1360
1361	/* Load the bare minimum state required for entering HM. */
1362	int rc = HMR0EnterCpu(pVCpu);
1363	AssertRCReturn(rc, rc);
1364
1365	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1366	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1367	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1368	#endif
1369
1370	RTCPUID idCpu = RTMpCpuId();
1371	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1372	Assert(pCpu);
1373	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1374
1375	rc = g_HmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1376	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1377
1378	/* Load the host-state as we may be resuming code after a longjmp and quite
1379	possibly now be scheduled on a different CPU. */
1380	rc = g_HmR0.pfnSaveHostState(pVM, pVCpu);
1381	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1382
1383	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1384	if (fStartedSet)
1385	PGMRZDynMapReleaseAutoSet(pVCpu);
1386	#endif
1387
1388	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1389	if (RT_FAILURE(rc))
1390	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1391	return rc;
1392	}
1393
1394
1395	/**
1396	* Deinitializes the bare minimum state used for HM context and if necessary
1397	* disable HM on the CPU.
1398	*
1399	* @returns VBox status code.
1400	* @param pVCpu Pointer to the VMCPU.
1401	*
1402	* @remarks No-long-jump zone!!!
1403	*/
1404	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1405	{
1406	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1407	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1408
1409	RTCPUID idCpu = RTMpCpuId();
1410	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1411
1412	if ( !g_HmR0.fGlobalInit
1413	&& pCpu->fConfigured)
1414	{
1415	int rc = hmR0DisableCpu(idCpu);
1416	AssertRCReturn(rc, rc);
1417	Assert(!pCpu->fConfigured);
1418	Assert(pCpu->idCpu == NIL_RTCPUID);
1419
1420	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1421	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1422	}
1423
1424	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1425	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1426
1427	return VINF_SUCCESS;
1428	}
1429
1430
1431	/**
1432	* Thread-context hook for HM.
1433	*
1434	* @param enmEvent The thread-context event.
1435	* @param pvUser Opaque pointer to the VMCPU.
1436	*/
1437	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1438	{
1439	PVMCPU pVCpu = (PVMCPU)pvUser;
1440	Assert(pVCpu);
1441	Assert(g_HmR0.pfnThreadCtxCallback);
1442
1443	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1444	}
1445
1446
1447	/**
1448	* Runs guest code in a hardware accelerated VM.
1449	*
1450	* @returns VBox status code.
1451	* @param pVM Pointer to the VM.
1452	* @param pVCpu Pointer to the VMCPU.
1453	*
1454	* @remarks Can be called with preemption enabled if thread-context hooks are
1455	* used!!!
1456	*/
1457	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1458	{
1459	#ifdef VBOX_STRICT
1460	/* With thread-context hooks we would be running this code with preemption enabled. */
1461	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1462	{
1463	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1464	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1465	Assert(pCpu->fConfigured);
1466	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1467	}
1468	#endif
1469
1470	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1471	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1472	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1473	PGMRZDynMapStartAutoSet(pVCpu);
1474	#endif
1475
1476	int rc = g_HmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1477
1478	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1479	PGMRZDynMapReleaseAutoSet(pVCpu);
1480	#endif
1481	return rc;
1482	}
1483
1484	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1485
1486	/**
1487	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1488	*
1489	* @returns VBox status code.
1490	* @param pVM Pointer to the VM.
1491	* @param pVCpu Pointer to the VMCPU.
1492	* @param pCtx Pointer to the guest CPU context.
1493	*/
1494	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1495	{
1496	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1497	if (pVM->hm.s.vmx.fSupported)
1498	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1499	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1500	}
1501
1502
1503	/**
1504	* Save guest debug state (64 bits guest mode & 32 bits host only)
1505	*
1506	* @returns VBox status code.
1507	* @param pVM Pointer to the VM.
1508	* @param pVCpu Pointer to the VMCPU.
1509	* @param pCtx Pointer to the guest CPU context.
1510	*/
1511	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1512	{
1513	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1514	if (pVM->hm.s.vmx.fSupported)
1515	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1516	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1517	}
1518
1519
1520	/**
1521	* Test the 32->64 bits switcher.
1522	*
1523	* @returns VBox status code.
1524	* @param pVM Pointer to the VM.
1525	*/
1526	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1527	{
1528	PVMCPU pVCpu = &pVM->aCpus[0];
1529	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1530	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1531	int rc;
1532
1533	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1534	if (pVM->hm.s.vmx.fSupported)
1535	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1536	else
1537	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1538	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1539
1540	return rc;
1541	}
1542
1543	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1544
1545	/**
1546	* Returns suspend status of the host.
1547	*
1548	* @returns Suspend pending or not.
1549	*/
1550	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1551	{
1552	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1553	}
1554
1555
1556	/**
1557	* Returns the cpu structure for the current cpu.
1558	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1559	*
1560	* @returns The cpu structure pointer.
1561	*/
1562	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1563	{
1564	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1565	RTCPUID idCpu = RTMpCpuId();
1566	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1567	return &g_HmR0.aCpuInfo[idCpu];
1568	}
1569
1570
1571	/**
1572	* Returns the cpu structure for the current cpu.
1573	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1574	*
1575	* @returns The cpu structure pointer.
1576	* @param idCpu id of the VCPU.
1577	*/
1578	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1579	{
1580	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1581	return &g_HmR0.aCpuInfo[idCpu];
1582	}
1583
1584
1585	/**
1586	* Save a pending IO read.
1587	*
1588	* @param pVCpu Pointer to the VMCPU.
1589	* @param GCPtrRip Address of IO instruction.
1590	* @param GCPtrRipNext Address of the next instruction.
1591	* @param uPort Port address.
1592	* @param uAndVal AND mask for saving the result in eax.
1593	* @param cbSize Read size.
1594	*/
1595	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1596	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1597	{
1598	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1599	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1600	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1601	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1602	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1603	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1604	return;
1605	}
1606
1607
1608	/**
1609	* Save a pending IO write.
1610	*
1611	* @param pVCpu Pointer to the VMCPU.
1612	* @param GCPtrRIP Address of IO instruction.
1613	* @param uPort Port address.
1614	* @param uAndVal AND mask for fetching the result from eax.
1615	* @param cbSize Read size.
1616	*/
1617	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1618	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1619	{
1620	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1621	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1622	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1623	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1624	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1625	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1626	return;
1627	}
1628
1629
1630	/**
1631	* Raw-mode switcher hook - disable VT-x if it's active and the current
1632	* switcher turns off paging.
1633	*
1634	* @returns VBox status code.
1635	* @param pVM Pointer to the VM.
1636	* @param enmSwitcher The switcher we're about to use.
1637	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1638	*/
1639	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1640	{
1641	NOREF(pVM);
1642
1643	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1644
1645	*pfVTxDisabled = false;
1646
1647	/* No such issues with AMD-V */
1648	if (!g_HmR0.vmx.fSupported)
1649	return VINF_SUCCESS;
1650
1651	/* Check if the switching we're up to is safe. */
1652	switch (enmSwitcher)
1653	{
1654	case VMMSWITCHER_32_TO_32:
1655	case VMMSWITCHER_PAE_TO_PAE:
1656	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1657
1658	case VMMSWITCHER_32_TO_PAE:
1659	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1660	case VMMSWITCHER_AMD64_TO_32:
1661	case VMMSWITCHER_AMD64_TO_PAE:
1662	break; /* unsafe switchers */
1663
1664	default:
1665	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1666	}
1667
1668	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1669	regardless of whether we're currently using VT-x or not. */
1670	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1671	{
1672	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1673	return VINF_SUCCESS;
1674	}
1675
1676	/** @todo Check if this code is presumptive wrt other VT-x users on the
1677	* system... */
1678
1679	/* Nothing to do if we haven't enabled VT-x. */
1680	if (!g_HmR0.fEnabled)
1681	return VINF_SUCCESS;
1682
1683	/* Local init implies the CPU is currently not in VMX root mode. */
1684	if (!g_HmR0.fGlobalInit)
1685	return VINF_SUCCESS;
1686
1687	/* Ok, disable VT-x. */
1688	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1689	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1690
1691	*pfVTxDisabled = true;
1692	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1693	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1694	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1695	}
1696
1697
1698	/**
1699	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1700	* switcher turned off paging.
1701	*
1702	* @param pVM Pointer to the VM.
1703	* @param fVTxDisabled Whether VT-x was disabled or not.
1704	*/
1705	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1706	{
1707	Assert(!ASMIntAreEnabled());
1708
1709	if (!fVTxDisabled)
1710	return; /* nothing to do */
1711
1712	Assert(g_HmR0.vmx.fSupported);
1713	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1714	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1715	else
1716	{
1717	Assert(g_HmR0.fEnabled);
1718	Assert(g_HmR0.fGlobalInit);
1719
1720	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1721	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1722
1723	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1724	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1725	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HmR0.vmx.Msrs);
1726	}
1727	}
1728
1729	#ifdef VBOX_STRICT
1730
1731	/**
1732	* Dumps a descriptor.
1733	*
1734	* @param pDesc Descriptor to dump.
1735	* @param Sel Selector number.
1736	* @param pszMsg Message to prepend the log entry with.
1737	*/
1738	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1739	{
1740	/*
1741	* Make variable description string.
1742	*/
1743	static struct
1744	{
1745	unsigned cch;
1746	const char *psz;
1747	} const s_aTypes[32] =
1748	{
1749	# define STRENTRY(str) { sizeof(str) - 1, str }
1750
1751	/* system */
1752	# if HC_ARCH_BITS == 64
1753	STRENTRY("Reserved0 "), /* 0x00 */
1754	STRENTRY("Reserved1 "), /* 0x01 */
1755	STRENTRY("LDT "), /* 0x02 */
1756	STRENTRY("Reserved3 "), /* 0x03 */
1757	STRENTRY("Reserved4 "), /* 0x04 */
1758	STRENTRY("Reserved5 "), /* 0x05 */
1759	STRENTRY("Reserved6 "), /* 0x06 */
1760	STRENTRY("Reserved7 "), /* 0x07 */
1761	STRENTRY("Reserved8 "), /* 0x08 */
1762	STRENTRY("TSS64Avail "), /* 0x09 */
1763	STRENTRY("ReservedA "), /* 0x0a */
1764	STRENTRY("TSS64Busy "), /* 0x0b */
1765	STRENTRY("Call64 "), /* 0x0c */
1766	STRENTRY("ReservedD "), /* 0x0d */
1767	STRENTRY("Int64 "), /* 0x0e */
1768	STRENTRY("Trap64 "), /* 0x0f */
1769	# else
1770	STRENTRY("Reserved0 "), /* 0x00 */
1771	STRENTRY("TSS16Avail "), /* 0x01 */
1772	STRENTRY("LDT "), /* 0x02 */
1773	STRENTRY("TSS16Busy "), /* 0x03 */
1774	STRENTRY("Call16 "), /* 0x04 */
1775	STRENTRY("Task "), /* 0x05 */
1776	STRENTRY("Int16 "), /* 0x06 */
1777	STRENTRY("Trap16 "), /* 0x07 */
1778	STRENTRY("Reserved8 "), /* 0x08 */
1779	STRENTRY("TSS32Avail "), /* 0x09 */
1780	STRENTRY("ReservedA "), /* 0x0a */
1781	STRENTRY("TSS32Busy "), /* 0x0b */
1782	STRENTRY("Call32 "), /* 0x0c */
1783	STRENTRY("ReservedD "), /* 0x0d */
1784	STRENTRY("Int32 "), /* 0x0e */
1785	STRENTRY("Trap32 "), /* 0x0f */
1786	# endif
1787	/* non system */
1788	STRENTRY("DataRO "), /* 0x10 */
1789	STRENTRY("DataRO Accessed "), /* 0x11 */
1790	STRENTRY("DataRW "), /* 0x12 */
1791	STRENTRY("DataRW Accessed "), /* 0x13 */
1792	STRENTRY("DataDownRO "), /* 0x14 */
1793	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1794	STRENTRY("DataDownRW "), /* 0x16 */
1795	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1796	STRENTRY("CodeEO "), /* 0x18 */
1797	STRENTRY("CodeEO Accessed "), /* 0x19 */
1798	STRENTRY("CodeER "), /* 0x1a */
1799	STRENTRY("CodeER Accessed "), /* 0x1b */
1800	STRENTRY("CodeConfEO "), /* 0x1c */
1801	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1802	STRENTRY("CodeConfER "), /* 0x1e */
1803	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1804	# undef SYSENTRY
1805	};
1806	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1807	char szMsg[128];
1808	char *psz = &szMsg[0];
1809	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1810	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1811	psz += s_aTypes[i].cch;
1812
1813	if (pDesc->Gen.u1Present)
1814	ADD_STR(psz, "Present ");
1815	else
1816	ADD_STR(psz, "Not-Present ");
1817	# if HC_ARCH_BITS == 64
1818	if (pDesc->Gen.u1Long)
1819	ADD_STR(psz, "64-bit ");
1820	else
1821	ADD_STR(psz, "Comp ");
1822	# else
1823	if (pDesc->Gen.u1Granularity)
1824	ADD_STR(psz, "Page ");
1825	if (pDesc->Gen.u1DefBig)
1826	ADD_STR(psz, "32-bit ");
1827	else
1828	ADD_STR(psz, "16-bit ");
1829	# endif
1830	# undef ADD_STR
1831	*psz = '\0';
1832
1833	/*
1834	* Limit and Base and format the output.
1835	*/
1836	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1837
1838	# if HC_ARCH_BITS == 64
1839	uint64_t u32Base = X86DESC64_BASE(pDesc);
1840	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1841	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1842	# else
1843	uint32_t u32Base = X86DESC_BASE(pDesc);
1844	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1845	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1846	# endif
1847	}
1848
1849
1850	/**
1851	* Formats a full register dump.
1852	*
1853	* @param pVM Pointer to the VM.
1854	* @param pVCpu Pointer to the VMCPU.
1855	* @param pCtx Pointer to the CPU context.
1856	*/
1857	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1858	{
1859	NOREF(pVM);
1860
1861	/*
1862	* Format the flags.
1863	*/
1864	static struct
1865	{
1866	const char pszSet; const char pszClear; uint32_t fFlag;
1867	} const s_aFlags[] =
1868	{
1869	{ "vip", NULL, X86_EFL_VIP },
1870	{ "vif", NULL, X86_EFL_VIF },
1871	{ "ac", NULL, X86_EFL_AC },
1872	{ "vm", NULL, X86_EFL_VM },
1873	{ "rf", NULL, X86_EFL_RF },
1874	{ "nt", NULL, X86_EFL_NT },
1875	{ "ov", "nv", X86_EFL_OF },
1876	{ "dn", "up", X86_EFL_DF },
1877	{ "ei", "di", X86_EFL_IF },
1878	{ "tf", NULL, X86_EFL_TF },
1879	{ "nt", "pl", X86_EFL_SF },
1880	{ "nz", "zr", X86_EFL_ZF },
1881	{ "ac", "na", X86_EFL_AF },
1882	{ "po", "pe", X86_EFL_PF },
1883	{ "cy", "nc", X86_EFL_CF },
1884	};
1885	char szEFlags[80];
1886	char *psz = szEFlags;
1887	uint32_t uEFlags = pCtx->eflags.u32;
1888	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1889	{
1890	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1891	if (pszAdd)
1892	{
1893	strcpy(psz, pszAdd);
1894	psz += strlen(pszAdd);
1895	*psz++ = ' ';
1896	}
1897	}
1898	psz[-1] = '\0';
1899
1900
1901	/*
1902	* Format the registers.
1903	*/
1904	if (CPUMIsGuestIn64BitCode(pVCpu))
1905	{
1906	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1907	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1908	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1909	"r14=%016RX64 r15=%016RX64\n"
1910	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1911	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1912	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1913	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1914	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1915	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1916	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1917	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1918	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1919	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1920	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1921	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1922	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1923	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1924	,
1925	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1926	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1927	pCtx->r14, pCtx->r15,
1928	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1929	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1930	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1931	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1932	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1933	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1934	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1935	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1936	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1937	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1938	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1939	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1940	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1941	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1942	}
1943	else
1944	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1945	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1946	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1947	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1948	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1949	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1950	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1951	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1952	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1953	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1954	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1955	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1956	,
1957	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1958	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1959	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1960	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1961	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1962	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1963	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1964	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1965	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1966	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1967	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1968	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1969
1970	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1971	Log(("FPU:\n"
1972	"FCW=%04x FSW=%04x FTW=%02x\n"
1973	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1974	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1975	,
1976	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1977	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1978	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1979	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1980
1981	Log(("MSR:\n"
1982	"EFER =%016RX64\n"
1983	"PAT =%016RX64\n"
1984	"STAR =%016RX64\n"
1985	"CSTAR =%016RX64\n"
1986	"LSTAR =%016RX64\n"
1987	"SFMASK =%016RX64\n"
1988	"KERNELGSBASE =%016RX64\n",
1989	pCtx->msrEFER,
1990	pCtx->msrPAT,
1991	pCtx->msrSTAR,
1992	pCtx->msrCSTAR,
1993	pCtx->msrLSTAR,
1994	pCtx->msrSFMASK,
1995	pCtx->msrKERNELGSBASE));
1996	}
1997
1998	#endif /* VBOX_STRICT */
1999

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 56364

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