HMR0.cpp@ 56365

Last change on this file since 56365 was 56365, checked in by vboxsync, 9 years ago
VMM/HM: removed obsolete todo.
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1	/* $Id: HMR0.cpp 56365 2015-06-11 14:53:50Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <VBox/vmm/hm.h>
23	#include <VBox/vmm/pgm.h>
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/hm_vmx.h>
27	#include <VBox/vmm/hm_svm.h>
28	#include <VBox/vmm/gim.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState, (PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost, void *pvArg));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM ,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	uint64_t u64HostCr4;
117
118	/** Host EFER value (set by ring-0 VMX init) */
119	uint64_t u64HostEfer;
120
121	/** VMX MSR values */
122	VMXMSRS Msrs;
123
124	/* Last instruction error */
125	uint32_t ulLastInstrError;
126	} vmx;
127
128	/** AMD-V information. */
129	struct
130	{
131	/* HWCR MSR (for diagnostics) */
132	uint64_t u64MsrHwcr;
133
134	/** SVM revision. */
135	uint32_t u32Rev;
136
137	/** SVM feature bits from cpuid 0x8000000a */
138	uint32_t u32Features;
139
140	/** Set by us to indicate SVM is supported by the CPU. */
141	bool fSupported;
142	} svm;
143	/** Saved error from detection */
144	int32_t lLastError;
145
146	struct
147	{
148	uint32_t u32AMDFeatureECX;
149	uint32_t u32AMDFeatureEDX;
150	} cpuid;
151
152	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
153	* enabled and disabled each time it's used to execute guest code. */
154	bool fGlobalInit;
155	/** Indicates whether the host is suspending or not. We'll refuse a few
156	* actions when the host is being suspended to speed up the suspending and
157	* avoid trouble. */
158	volatile bool fSuspended;
159
160	/** Whether we've already initialized all CPUs.
161	* @remarks We could check the EnableAllCpusOnce state, but this is
162	* simpler and hopefully easier to understand. */
163	bool fEnabled;
164	/** Serialize initialization in HMR0EnableAllCpus. */
165	RTONCE EnableAllCpusOnce;
166	} g_HmR0;
167
168
169
170	/**
171	* Initializes a first return code structure.
172	*
173	* @param pFirstRc The structure to init.
174	*/
175	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
176	{
177	pFirstRc->rc = VINF_SUCCESS;
178	pFirstRc->idCpu = NIL_RTCPUID;
179	}
180
181
182	/**
183	* Try set the status code (success ignored).
184	*
185	* @param pFirstRc The first return code structure.
186	* @param rc The status code.
187	*/
188	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
189	{
190	if ( RT_FAILURE(rc)
191	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
192	pFirstRc->idCpu = RTMpCpuId();
193	}
194
195
196	/**
197	* Get the status code of a first return code structure.
198	*
199	* @returns The status code; VINF_SUCCESS or error status, no informational or
200	* warning errors.
201	* @param pFirstRc The first return code structure.
202	*/
203	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
204	{
205	return pFirstRc->rc;
206	}
207
208
209	#ifdef VBOX_STRICT
210	/**
211	* Get the CPU ID on which the failure status code was reported.
212	*
213	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
214	* @param pFirstRc The first return code structure.
215	*/
216	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
217	{
218	return pFirstRc->idCpu;
219	}
220	#endif /* VBOX_STRICT */
221
222
223	/** @name Dummy callback handlers.
224	* @{ */
225
226	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
227	{
228	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
229	return VINF_SUCCESS;
230	}
231
232	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
233	{
234	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
235	}
236
237	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
238	bool fEnabledBySystem, void *pvArg)
239	{
240	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
241	return VINF_SUCCESS;
242	}
243
244	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
245	{
246	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
247	return VINF_SUCCESS;
248	}
249
250	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
251	{
252	NOREF(pVM);
253	return VINF_SUCCESS;
254	}
255
256	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
257	{
258	NOREF(pVM);
259	return VINF_SUCCESS;
260	}
261
262	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
263	{
264	NOREF(pVM);
265	return VINF_SUCCESS;
266	}
267
268	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
269	{
270	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
271	return VINF_SUCCESS;
272	}
273
274	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
275	{
276	NOREF(pVM); NOREF(pVCpu);
277	return VINF_SUCCESS;
278	}
279
280	/** @} */
281
282
283	/**
284	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
285	* Down at the Rate Specified" erratum.
286	*
287	* Errata names and related steppings:
288	* - BA86 - D0.
289	* - AAX65 - C2.
290	* - AAU65 - C2, K0.
291	* - AAO95 - B1.
292	* - AAT59 - C2.
293	* - AAK139 - D0.
294	* - AAM126 - C0, C1, D0.
295	* - AAN92 - B1.
296	* - AAJ124 - C0, D0.
297	*
298	* - AAP86 - B1.
299	*
300	* Steppings: B1, C0, C1, C2, D0, K0.
301	*
302	* @returns true if subject to it, false if not.
303	*/
304	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
305	{
306	uint32_t u = ASMCpuId_EAX(1);
307	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
308	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
309	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
310	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
311	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
312	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
313	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
314	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
315	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
316	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
317	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
318	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
319	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
320	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
321	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
322	)
323	return true;
324	return false;
325	}
326
327
328	/**
329	* Intel specific initialization code.
330	*
331	* @returns VBox status code (will only fail if out of memory).
332	*/
333	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
334	{
335	/*
336	* Check that all the required VT-x features are present.
337	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
338	*/
339	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
340	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
341	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
342	)
343	{
344	/** @todo move this into a separate function. */
345	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
346
347	/*
348	* First try use native kernel API for controlling VT-x.
349	* (This is only supported by some Mac OS X kernels atm.)
350	*/
351	int rc = g_HmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
352	g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
353	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
354	{
355	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
356	if (RT_SUCCESS(rc))
357	{
358	g_HmR0.vmx.fSupported = true;
359	rc = SUPR0EnableVTx(false /* fEnable */);
360	AssertLogRelRC(rc);
361	}
362	}
363	else
364	{
365	/* We need to check if VT-x has been properly initialized on all
366	CPUs. Some BIOSes do a lousy job. */
367	HMR0FIRSTRC FirstRc;
368	hmR0FirstRcInit(&FirstRc);
369	g_HmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
370	if (RT_SUCCESS(g_HmR0.lLastError))
371	g_HmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
372	}
373	if (RT_SUCCESS(g_HmR0.lLastError))
374	{
375	/* Reread in case it was changed by hmR0InitIntelCpu(). */
376	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
377
378	/*
379	* Read all relevant registers and MSRs.
380	*/
381	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
382	g_HmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
383	g_HmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
384	g_HmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
385	g_HmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
386	g_HmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
387	g_HmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
388	g_HmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
389	g_HmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
390	g_HmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
391	g_HmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
392	g_HmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
393	g_HmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
394	/* VPID 16 bits ASID. */
395	g_HmR0.uMaxAsid = 0x10000; /* exclusive */
396
397	if (g_HmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
398	{
399	g_HmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
400	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
401	g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
402
403	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
404	g_HmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
405	}
406
407	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
408	{
409	/*
410	* Enter root mode
411	*/
412	RTR0MEMOBJ hScatchMemObj;
413	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
414	if (RT_FAILURE(rc))
415	{
416	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
417	return rc;
418	}
419
420	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
421	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
422	ASMMemZeroPage(pvScatchPage);
423
424	/* Set revision dword at the beginning of the structure. */
425	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HmR0.vmx.Msrs.u64BasicInfo);
426
427	/* Make sure we don't get rescheduled to another cpu during this probe. */
428	RTCCUINTREG fFlags = ASMIntDisableFlags();
429
430	/*
431	* Check CR4.VMXE
432	*/
433	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
434	if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
435	{
436	/* In theory this bit could be cleared behind our back. Which would cause
437	#UD faults when we try to execute the VMX instructions... */
438	ASMSetCR4(g_HmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
439	}
440
441	/*
442	* The only way of checking if we're in VMX root mode or not is to try and enter it.
443	* There is no instruction or control bit that tells us if we're in VMX root mode.
444	* Therefore, try and enter VMX root mode here.
445	*/
446	rc = VMXEnable(HCPhysScratchPage);
447	if (RT_SUCCESS(rc))
448	{
449	g_HmR0.vmx.fSupported = true;
450	VMXDisable();
451	}
452	else
453	{
454	/*
455	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
456	* it will crash the host when we enter raw mode, because:
457	*
458	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
459	* this bit), and
460	* (b) turning off paging causes a #GP (unavoidable when switching
461	* from long to 32 bits mode or 32 bits to PAE).
462	*
463	* They should fix their code, but until they do we simply refuse to run.
464	*/
465	g_HmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
466	Assert(g_HmR0.vmx.fSupported == false);
467	}
468
469	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
470	if it wasn't so before (some software could incorrectly
471	think it's in VMX mode). */
472	ASMSetCR4(g_HmR0.vmx.u64HostCr4);
473	ASMSetFlags(fFlags);
474
475	RTR0MemObjFree(hScatchMemObj, false);
476	}
477
478	if (g_HmR0.vmx.fSupported)
479	{
480	rc = VMXR0GlobalInit();
481	if (RT_FAILURE(rc))
482	g_HmR0.lLastError = rc;
483
484	/*
485	* Install the VT-x methods.
486	*/
487	g_HmR0.pfnEnterSession = VMXR0Enter;
488	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
489	g_HmR0.pfnSaveHostState = VMXR0SaveHostState;
490	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
491	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
492	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
493	g_HmR0.pfnInitVM = VMXR0InitVM;
494	g_HmR0.pfnTermVM = VMXR0TermVM;
495	g_HmR0.pfnSetupVM = VMXR0SetupVM;
496
497	/*
498	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
499	* Timer Does Not Count Down at the Rate Specified" erratum.
500	*/
501	if (g_HmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
502	{
503	g_HmR0.vmx.fUsePreemptTimer = true;
504	g_HmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HmR0.vmx.Msrs.u64Misc);
505	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
506	g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
507	}
508	}
509	}
510	#ifdef LOG_ENABLED
511	else
512	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HmR0.lLastError);
513	#endif
514	}
515	else
516	g_HmR0.lLastError = VERR_VMX_NO_VMX;
517	return VINF_SUCCESS;
518	}
519
520
521	/**
522	* AMD-specific initialization code.
523	*
524	* @returns VBox status code.
525	*/
526	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
527	{
528	/*
529	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
530	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
531	*/
532	int rc;
533	if ( (g_HmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
534	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
535	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
536	&& ASMIsValidExtRange(uMaxExtLeaf)
537	&& uMaxExtLeaf >= 0x8000000a
538	)
539	{
540	/* Call the global AMD-V initialization routine. */
541	rc = SVMR0GlobalInit();
542	if (RT_FAILURE(rc))
543	{
544	g_HmR0.lLastError = rc;
545	return rc;
546	}
547
548	/*
549	* Install the AMD-V methods.
550	*/
551	g_HmR0.pfnEnterSession = SVMR0Enter;
552	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
553	g_HmR0.pfnSaveHostState = SVMR0SaveHostState;
554	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
555	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
556	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
557	g_HmR0.pfnInitVM = SVMR0InitVM;
558	g_HmR0.pfnTermVM = SVMR0TermVM;
559	g_HmR0.pfnSetupVM = SVMR0SetupVM;
560
561	/* Query AMD features. */
562	uint32_t u32Dummy;
563	ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
564
565	/*
566	* We need to check if AMD-V has been properly initialized on all CPUs.
567	* Some BIOSes might do a poor job.
568	*/
569	HMR0FIRSTRC FirstRc;
570	hmR0FirstRcInit(&FirstRc);
571	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
572	AssertRC(rc);
573	if (RT_SUCCESS(rc))
574	rc = hmR0FirstRcGetStatus(&FirstRc);
575	#ifndef DEBUG_bird
576	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
577	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
578	#endif
579	if (RT_SUCCESS(rc))
580	{
581	/* Read the HWCR MSR for diagnostics. */
582	g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
583	g_HmR0.svm.fSupported = true;
584	}
585	else
586	{
587	g_HmR0.lLastError = rc;
588	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
589	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
590	}
591	}
592	else
593	{
594	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
595	g_HmR0.lLastError = VERR_SVM_NO_SVM;
596	}
597	return rc;
598	}
599
600
601	/**
602	* Does global Ring-0 HM initialization (at module init).
603	*
604	* @returns VBox status code.
605	*/
606	VMMR0_INT_DECL(int) HMR0Init(void)
607	{
608	/*
609	* Initialize the globals.
610	*/
611	g_HmR0.fEnabled = false;
612	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
613	g_HmR0.EnableAllCpusOnce = s_OnceInit;
614	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
615	{
616	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
617	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
618	}
619
620	/* Fill in all callbacks with placeholders. */
621	g_HmR0.pfnEnterSession = hmR0DummyEnter;
622	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
623	g_HmR0.pfnSaveHostState = hmR0DummySaveHostState;
624	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
625	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
626	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
627	g_HmR0.pfnInitVM = hmR0DummyInitVM;
628	g_HmR0.pfnTermVM = hmR0DummyTermVM;
629	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
630
631	/* Default is global VT-x/AMD-V init. */
632	g_HmR0.fGlobalInit = true;
633
634	/*
635	* Make sure aCpuInfo is big enough for all the CPUs on this system.
636	*/
637	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
638	{
639	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
640	return VERR_TOO_MANY_CPUS;
641	}
642
643	/*
644	* Check for VT-x and AMD-V capabilities.
645	*/
646	int rc;
647	if (ASMHasCpuId())
648	{
649	/* Standard features. */
650	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
651	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
652	if (ASMIsValidStdRange(uMaxLeaf))
653	{
654	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
655	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
656
657	/* Query AMD features. */
658	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
659	if (ASMIsValidExtRange(uMaxExtLeaf))
660	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
661	&g_HmR0.cpuid.u32AMDFeatureECX,
662	&g_HmR0.cpuid.u32AMDFeatureEDX);
663	else
664	g_HmR0.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureEDX = 0;
665
666	/* Go to CPU specific initialization code. */
667	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
668	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
669	{
670	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
671	if (RT_FAILURE(rc))
672	return rc;
673	}
674	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
675	{
676	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
677	if (RT_FAILURE(rc))
678	return rc;
679	}
680	else
681	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
682	}
683	else
684	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
685	}
686	else
687	g_HmR0.lLastError = VERR_HM_NO_CPUID;
688
689	/*
690	* Register notification callbacks that we can use to disable/enable CPUs
691	* when brought offline/online or suspending/resuming.
692	*/
693	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
694	{
695	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
696	AssertRC(rc);
697
698	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
699	AssertRC(rc);
700	}
701
702	/* We return success here because module init shall not fail if HM
703	fails to initialize. */
704	return VINF_SUCCESS;
705	}
706
707
708	/**
709	* Does global Ring-0 HM termination (at module termination).
710	*
711	* @returns VBox status code.
712	*/
713	VMMR0_INT_DECL(int) HMR0Term(void)
714	{
715	int rc;
716	if ( g_HmR0.vmx.fSupported
717	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
718	{
719	/*
720	* Simple if the host OS manages VT-x.
721	*/
722	Assert(g_HmR0.fGlobalInit);
723	rc = SUPR0EnableVTx(false /* fEnable */);
724
725	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
726	{
727	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
728	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
729	}
730	}
731	else
732	{
733	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
734
735	/* Doesn't really matter if this fails. */
736	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
737	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
738
739	/*
740	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
741	*/
742	if (g_HmR0.fGlobalInit)
743	{
744	HMR0FIRSTRC FirstRc;
745	hmR0FirstRcInit(&FirstRc);
746	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
747	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
748	if (RT_SUCCESS(rc))
749	rc = hmR0FirstRcGetStatus(&FirstRc);
750	}
751
752	/*
753	* Free the per-cpu pages used for VT-x and AMD-V.
754	*/
755	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
756	{
757	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
758	{
759	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
760	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
761	}
762	}
763	}
764
765	/** @todo This needs cleaning up. There's no matching
766	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
767	* should move into their respective modules. */
768	/* Finally, call global VT-x/AMD-V termination. */
769	if (g_HmR0.vmx.fSupported)
770	VMXR0GlobalTerm();
771	else if (g_HmR0.svm.fSupported)
772	SVMR0GlobalTerm();
773
774	return rc;
775	}
776
777
778	/**
779	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
780	* on a CPU.
781	*
782	* @param idCpu The identifier for the CPU the function is called on.
783	* @param pvUser1 Pointer to the first RC structure.
784	* @param pvUser2 Ignored.
785	*/
786	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
787	{
788	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
789	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
790	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
791	NOREF(idCpu); NOREF(pvUser2);
792
793	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
794	hmR0FirstRcSetStatus(pFirstRc, rc);
795	}
796
797
798	/**
799	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
800	* on a CPU.
801	*
802	* @param idCpu The identifier for the CPU the function is called on.
803	* @param pvUser1 Pointer to the first RC structure.
804	* @param pvUser2 Ignored.
805	*/
806	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
807	{
808	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
809	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
810	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
811	NOREF(idCpu); NOREF(pvUser2);
812
813	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
814	hmR0FirstRcSetStatus(pFirstRc, rc);
815	}
816
817
818	/**
819	* Enable VT-x or AMD-V on the current CPU
820	*
821	* @returns VBox status code.
822	* @param pVM Pointer to the VM (can be NULL).
823	* @param idCpu The identifier for the CPU the function is called on.
824	*
825	* @remarks Maybe called with interrupts disabled!
826	*/
827	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
828	{
829	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
830
831	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
832	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
833	Assert(!pCpu->fConfigured);
834	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
835
836	pCpu->idCpu = idCpu;
837	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
838
839	int rc;
840	if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
841	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
842	else
843	{
844	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
845	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
846	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0 /* iPage */);
847
848	if (g_HmR0.vmx.fSupported)
849	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HmR0.vmx.Msrs);
850	else
851	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
852	}
853	if (RT_SUCCESS(rc))
854	pCpu->fConfigured = true;
855
856	return rc;
857	}
858
859
860	/**
861	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
862	*
863	* @param idCpu The identifier for the CPU the function is called on.
864	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
865	* @param pvUser2 The 2nd user argument.
866	*/
867	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
868	{
869	PVM pVM = (PVM)pvUser1; /* can be NULL! */
870	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
871	AssertReturnVoid(g_HmR0.fGlobalInit);
872	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
873	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
874	}
875
876
877	/**
878	* RTOnce callback employed by HMR0EnableAllCpus.
879	*
880	* @returns VBox status code.
881	* @param pvUser Pointer to the VM.
882	* @param pvUserIgnore NULL, ignored.
883	*/
884	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
885	{
886	PVM pVM = (PVM)pvUser;
887
888	/*
889	* Indicate that we've initialized.
890	*
891	* Note! There is a potential race between this function and the suspend
892	* notification. Kind of unlikely though, so ignored for now.
893	*/
894	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
895	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
896
897	/*
898	* The global init variable is set by the first VM.
899	*/
900	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
901
902	#ifdef VBOX_STRICT
903	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
904	{
905	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
906	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
907	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
908	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
909	}
910	#endif
911
912	int rc;
913	if ( g_HmR0.vmx.fSupported
914	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
915	{
916	/*
917	* Global VT-x initialization API (only darwin for now).
918	*/
919	rc = SUPR0EnableVTx(true /* fEnable */);
920	if (RT_SUCCESS(rc))
921	{
922	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
923	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
924	}
925	else
926	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
927	}
928	else
929	{
930	/*
931	* We're doing the job ourselves.
932	*/
933	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
934	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
935	{
936	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
937
938	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
939	{
940	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
941	AssertLogRelRCReturn(rc, rc);
942
943	void *pvR0 = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
944	ASMMemZeroPage(pvR0);
945	}
946	}
947
948	rc = VINF_SUCCESS;
949	}
950
951	if ( RT_SUCCESS(rc)
952	&& g_HmR0.fGlobalInit)
953	{
954	/* First time, so initialize each cpu/core. */
955	HMR0FIRSTRC FirstRc;
956	hmR0FirstRcInit(&FirstRc);
957	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
958	if (RT_SUCCESS(rc))
959	rc = hmR0FirstRcGetStatus(&FirstRc);
960	}
961
962	return rc;
963	}
964
965
966	/**
967	* Sets up HM on all cpus.
968	*
969	* @returns VBox status code.
970	* @param pVM Pointer to the VM.
971	*/
972	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
973	{
974	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
975	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
976	return VERR_HM_SUSPEND_PENDING;
977
978	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
979	}
980
981
982	/**
983	* Disable VT-x or AMD-V on the current CPU.
984	*
985	* @returns VBox status code.
986	* @param idCpu The identifier for the CPU this function is called on.
987	*
988	* @remarks Must be called with preemption disabled.
989	*/
990	static int hmR0DisableCpu(RTCPUID idCpu)
991	{
992	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
993
994	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
995	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
996	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
997	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
998	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
999	AssertRelease(idCpu == RTMpCpuId());
1000
1001	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1002	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1003
1004	int rc;
1005	if (pCpu->fConfigured)
1006	{
1007	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1008	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1009
1010	rc = g_HmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1011	AssertRCReturn(rc, rc);
1012
1013	pCpu->fConfigured = false;
1014	pCpu->idCpu = NIL_RTCPUID;
1015	}
1016	else
1017	rc = VINF_SUCCESS; /* nothing to do */
1018	return rc;
1019	}
1020
1021
1022	/**
1023	* Worker function passed to RTMpOnAll() that is to be called on the target
1024	* CPUs.
1025	*
1026	* @param idCpu The identifier for the CPU the function is called on.
1027	* @param pvUser1 The 1st user argument.
1028	* @param pvUser2 Opaque pointer to the FirstRc.
1029	*/
1030	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1031	{
1032	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1033	AssertReturnVoid(g_HmR0.fGlobalInit);
1034	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1035	}
1036
1037
1038	/**
1039	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1040	* CPU.
1041	*
1042	* @param idCpu The identifier for the CPU the function is called on.
1043	* @param pvUser1 Null, not used.
1044	* @param pvUser2 Null, not used.
1045	*/
1046	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1047	{
1048	NOREF(pvUser1);
1049	NOREF(pvUser2);
1050	hmR0DisableCpu(idCpu);
1051	}
1052
1053
1054	/**
1055	* Callback function invoked when a cpu goes online or offline.
1056	*
1057	* @param enmEvent The Mp event.
1058	* @param idCpu The identifier for the CPU the function is called on.
1059	* @param pvData Opaque data (PVM pointer).
1060	*/
1061	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1062	{
1063	NOREF(pvData);
1064	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1065
1066	/*
1067	* We only care about uninitializing a CPU that is going offline. When a
1068	* CPU comes online, the initialization is done lazily in HMR0Enter().
1069	*/
1070	switch (enmEvent)
1071	{
1072	case RTMPEVENT_OFFLINE:
1073	{
1074	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1075	RTThreadPreemptDisable(&PreemptState);
1076	if (idCpu == RTMpCpuId())
1077	{
1078	int rc = hmR0DisableCpu(idCpu);
1079	AssertRC(rc);
1080	RTThreadPreemptRestore(&PreemptState);
1081	}
1082	else
1083	{
1084	RTThreadPreemptRestore(&PreemptState);
1085	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1086	}
1087	break;
1088	}
1089
1090	default:
1091	break;
1092	}
1093	}
1094
1095
1096	/**
1097	* Called whenever a system power state change occurs.
1098	*
1099	* @param enmEvent The Power event.
1100	* @param pvUser User argument.
1101	*/
1102	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1103	{
1104	NOREF(pvUser);
1105	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1106
1107	#ifdef LOG_ENABLED
1108	if (enmEvent == RTPOWEREVENT_SUSPEND)
1109	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1110	else
1111	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1112	#endif
1113
1114	if (enmEvent == RTPOWEREVENT_SUSPEND)
1115	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1116
1117	if (g_HmR0.fEnabled)
1118	{
1119	int rc;
1120	HMR0FIRSTRC FirstRc;
1121	hmR0FirstRcInit(&FirstRc);
1122
1123	if (enmEvent == RTPOWEREVENT_SUSPEND)
1124	{
1125	if (g_HmR0.fGlobalInit)
1126	{
1127	/* Turn off VT-x or AMD-V on all CPUs. */
1128	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1129	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1130	}
1131	/* else nothing to do here for the local init case */
1132	}
1133	else
1134	{
1135	/* Reinit the CPUs from scratch as the suspend state might have
1136	messed with the MSRs. (lousy BIOSes as usual) */
1137	if (g_HmR0.vmx.fSupported)
1138	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1139	else
1140	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1141	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1142	if (RT_SUCCESS(rc))
1143	rc = hmR0FirstRcGetStatus(&FirstRc);
1144	#ifdef LOG_ENABLED
1145	if (RT_FAILURE(rc))
1146	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1147	#endif
1148	if (g_HmR0.fGlobalInit)
1149	{
1150	/* Turn VT-x or AMD-V back on on all CPUs. */
1151	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1152	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1153	}
1154	/* else nothing to do here for the local init case */
1155	}
1156	}
1157
1158	if (enmEvent == RTPOWEREVENT_RESUME)
1159	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1160	}
1161
1162
1163	/**
1164	* Does ring-0 per-VM HM initialization.
1165	*
1166	* This will copy HM global into the VM structure and call the CPU specific
1167	* init routine which will allocate resources for each virtual CPU and such.
1168	*
1169	* @returns VBox status code.
1170	* @param pVM Pointer to the VM.
1171	*
1172	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1173	* vmR3InitRing3().
1174	*/
1175	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1176	{
1177	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1178
1179	#ifdef LOG_ENABLED
1180	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1181	#endif
1182
1183	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1184	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1185	return VERR_HM_SUSPEND_PENDING;
1186
1187	/*
1188	* Copy globals to the VM structure.
1189	*/
1190	pVM->hm.s.vmx.fSupported = g_HmR0.vmx.fSupported;
1191	pVM->hm.s.svm.fSupported = g_HmR0.svm.fSupported;
1192
1193	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1194	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.vmx.cPreemptTimerShift;
1195	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.vmx.u64HostCr4;
1196	pVM->hm.s.vmx.u64HostEfer = g_HmR0.vmx.u64HostEfer;
1197	pVM->hm.s.vmx.Msrs = g_HmR0.vmx.Msrs;
1198	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.svm.u64MsrHwcr;
1199	pVM->hm.s.svm.u32Rev = g_HmR0.svm.u32Rev;
1200	pVM->hm.s.svm.u32Features = g_HmR0.svm.u32Features;
1201	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureECX;
1202	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HmR0.cpuid.u32AMDFeatureEDX;
1203	pVM->hm.s.lLastError = g_HmR0.lLastError;
1204	pVM->hm.s.uMaxAsid = g_HmR0.uMaxAsid;
1205
1206	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1207	{
1208	pVM->hm.s.cMaxResumeLoops = 1024;
1209	if (RTThreadPreemptIsPendingTrusty())
1210	pVM->hm.s.cMaxResumeLoops = 8192;
1211	}
1212
1213	/*
1214	* Initialize some per-VCPU fields.
1215	*/
1216	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1217	{
1218	PVMCPU pVCpu = &pVM->aCpus[i];
1219	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1220	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1221	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1222
1223	/* We'll aways increment this the first time (host uses ASID 0). */
1224	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1225	}
1226
1227	pVM->hm.s.uHostKernelFeatures = SUPR0GetKernelFeatures();
1228
1229	/*
1230	* Call the hardware specific initialization method.
1231	*/
1232	return g_HmR0.pfnInitVM(pVM);
1233	}
1234
1235
1236	/**
1237	* Does ring-0 per VM HM termination.
1238	*
1239	* @returns VBox status code.
1240	* @param pVM Pointer to the VM.
1241	*/
1242	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1243	{
1244	Log(("HMR0TermVM: %p\n", pVM));
1245	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1246
1247	/*
1248	* Call the hardware specific method.
1249	*
1250	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1251	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1252	*/
1253	return g_HmR0.pfnTermVM(pVM);
1254	}
1255
1256
1257	/**
1258	* Sets up a VT-x or AMD-V session.
1259	*
1260	* This is mostly about setting up the hardware VM state.
1261	*
1262	* @returns VBox status code.
1263	* @param pVM Pointer to the VM.
1264	*/
1265	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1266	{
1267	Log(("HMR0SetupVM: %p\n", pVM));
1268	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1269
1270	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1271	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1272
1273	/* On first entry we'll sync everything. */
1274	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1275	HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1276
1277	/*
1278	* Call the hardware specific setup VM method. This requires the CPU to be
1279	* enabled for AMD-V/VT-x and preemption to be prevented.
1280	*/
1281	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1282	RTThreadPreemptDisable(&PreemptState);
1283	RTCPUID idCpu = RTMpCpuId();
1284
1285	/* Enable VT-x or AMD-V if local init is required. */
1286	int rc;
1287	if (!g_HmR0.fGlobalInit)
1288	{
1289	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1290	rc = hmR0EnableCpu(pVM, idCpu);
1291	if (RT_FAILURE(rc))
1292	{
1293	RTThreadPreemptRestore(&PreemptState);
1294	return rc;
1295	}
1296	}
1297
1298	/* Setup VT-x or AMD-V. */
1299	rc = g_HmR0.pfnSetupVM(pVM);
1300
1301	/* Disable VT-x or AMD-V if local init was done before. */
1302	if (!g_HmR0.fGlobalInit)
1303	{
1304	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1305	int rc2 = hmR0DisableCpu(idCpu);
1306	AssertRC(rc2);
1307	}
1308
1309	RTThreadPreemptRestore(&PreemptState);
1310	return rc;
1311	}
1312
1313
1314	/**
1315	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1316	* required for entering HM context.
1317	*
1318	* @returns VBox status code.
1319	* @param pvCpu Pointer to the VMCPU.
1320	*
1321	* @remarks No-long-jump zone!!!
1322	*/
1323	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1324	{
1325	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1326
1327	int rc = VINF_SUCCESS;
1328	RTCPUID idCpu = RTMpCpuId();
1329	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1330	AssertPtr(pCpu);
1331
1332	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1333	if (!pCpu->fConfigured)
1334	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1335
1336	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1337	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1338
1339	Assert(pCpu->idCpu == idCpu && pCpu->idCpu != NIL_RTCPUID);
1340	pVCpu->hm.s.idEnteredCpu = idCpu;
1341	return rc;
1342	}
1343
1344
1345	/**
1346	* Enters the VT-x or AMD-V session.
1347	*
1348	* @returns VBox status code.
1349	* @param pVM Pointer to the VM.
1350	* @param pVCpu Pointer to the VMCPU.
1351	*
1352	* @remarks This is called with preemption disabled.
1353	*/
1354	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1355	{
1356	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1357	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1358	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1359
1360	/* Load the bare minimum state required for entering HM. */
1361	int rc = HMR0EnterCpu(pVCpu);
1362	AssertRCReturn(rc, rc);
1363
1364	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1365	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1366	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1367	#endif
1368
1369	RTCPUID idCpu = RTMpCpuId();
1370	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1371	Assert(pCpu);
1372	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1373
1374	rc = g_HmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1375	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1376
1377	/* Load the host-state as we may be resuming code after a longjmp and quite
1378	possibly now be scheduled on a different CPU. */
1379	rc = g_HmR0.pfnSaveHostState(pVM, pVCpu);
1380	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1381
1382	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1383	if (fStartedSet)
1384	PGMRZDynMapReleaseAutoSet(pVCpu);
1385	#endif
1386
1387	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1388	if (RT_FAILURE(rc))
1389	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1390	return rc;
1391	}
1392
1393
1394	/**
1395	* Deinitializes the bare minimum state used for HM context and if necessary
1396	* disable HM on the CPU.
1397	*
1398	* @returns VBox status code.
1399	* @param pVCpu Pointer to the VMCPU.
1400	*
1401	* @remarks No-long-jump zone!!!
1402	*/
1403	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1404	{
1405	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1406	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1407
1408	RTCPUID idCpu = RTMpCpuId();
1409	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1410
1411	if ( !g_HmR0.fGlobalInit
1412	&& pCpu->fConfigured)
1413	{
1414	int rc = hmR0DisableCpu(idCpu);
1415	AssertRCReturn(rc, rc);
1416	Assert(!pCpu->fConfigured);
1417	Assert(pCpu->idCpu == NIL_RTCPUID);
1418
1419	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1420	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1421	}
1422
1423	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1424	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1425
1426	return VINF_SUCCESS;
1427	}
1428
1429
1430	/**
1431	* Thread-context hook for HM.
1432	*
1433	* @param enmEvent The thread-context event.
1434	* @param pvUser Opaque pointer to the VMCPU.
1435	*/
1436	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1437	{
1438	PVMCPU pVCpu = (PVMCPU)pvUser;
1439	Assert(pVCpu);
1440	Assert(g_HmR0.pfnThreadCtxCallback);
1441
1442	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1443	}
1444
1445
1446	/**
1447	* Runs guest code in a hardware accelerated VM.
1448	*
1449	* @returns VBox status code.
1450	* @param pVM Pointer to the VM.
1451	* @param pVCpu Pointer to the VMCPU.
1452	*
1453	* @remarks Can be called with preemption enabled if thread-context hooks are
1454	* used!!!
1455	*/
1456	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1457	{
1458	#ifdef VBOX_STRICT
1459	/* With thread-context hooks we would be running this code with preemption enabled. */
1460	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1461	{
1462	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1463	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1464	Assert(pCpu->fConfigured);
1465	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1466	}
1467	#endif
1468
1469	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1470	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1471	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1472	PGMRZDynMapStartAutoSet(pVCpu);
1473	#endif
1474
1475	int rc = g_HmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1476
1477	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1478	PGMRZDynMapReleaseAutoSet(pVCpu);
1479	#endif
1480	return rc;
1481	}
1482
1483	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1484
1485	/**
1486	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1487	*
1488	* @returns VBox status code.
1489	* @param pVM Pointer to the VM.
1490	* @param pVCpu Pointer to the VMCPU.
1491	* @param pCtx Pointer to the guest CPU context.
1492	*/
1493	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1494	{
1495	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1496	if (pVM->hm.s.vmx.fSupported)
1497	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1498	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1499	}
1500
1501
1502	/**
1503	* Save guest debug state (64 bits guest mode & 32 bits host only)
1504	*
1505	* @returns VBox status code.
1506	* @param pVM Pointer to the VM.
1507	* @param pVCpu Pointer to the VMCPU.
1508	* @param pCtx Pointer to the guest CPU context.
1509	*/
1510	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1511	{
1512	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1513	if (pVM->hm.s.vmx.fSupported)
1514	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1515	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1516	}
1517
1518
1519	/**
1520	* Test the 32->64 bits switcher.
1521	*
1522	* @returns VBox status code.
1523	* @param pVM Pointer to the VM.
1524	*/
1525	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1526	{
1527	PVMCPU pVCpu = &pVM->aCpus[0];
1528	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1529	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1530	int rc;
1531
1532	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1533	if (pVM->hm.s.vmx.fSupported)
1534	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1535	else
1536	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1537	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1538
1539	return rc;
1540	}
1541
1542	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1543
1544	/**
1545	* Returns suspend status of the host.
1546	*
1547	* @returns Suspend pending or not.
1548	*/
1549	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1550	{
1551	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1552	}
1553
1554
1555	/**
1556	* Returns the cpu structure for the current cpu.
1557	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1558	*
1559	* @returns The cpu structure pointer.
1560	*/
1561	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1562	{
1563	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1564	RTCPUID idCpu = RTMpCpuId();
1565	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1566	return &g_HmR0.aCpuInfo[idCpu];
1567	}
1568
1569
1570	/**
1571	* Returns the cpu structure for the current cpu.
1572	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1573	*
1574	* @returns The cpu structure pointer.
1575	* @param idCpu id of the VCPU.
1576	*/
1577	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1578	{
1579	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1580	return &g_HmR0.aCpuInfo[idCpu];
1581	}
1582
1583
1584	/**
1585	* Save a pending IO read.
1586	*
1587	* @param pVCpu Pointer to the VMCPU.
1588	* @param GCPtrRip Address of IO instruction.
1589	* @param GCPtrRipNext Address of the next instruction.
1590	* @param uPort Port address.
1591	* @param uAndVal AND mask for saving the result in eax.
1592	* @param cbSize Read size.
1593	*/
1594	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1595	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1596	{
1597	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1598	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1599	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1600	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1601	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1602	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1603	return;
1604	}
1605
1606
1607	/**
1608	* Save a pending IO write.
1609	*
1610	* @param pVCpu Pointer to the VMCPU.
1611	* @param GCPtrRIP Address of IO instruction.
1612	* @param uPort Port address.
1613	* @param uAndVal AND mask for fetching the result from eax.
1614	* @param cbSize Read size.
1615	*/
1616	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1617	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1618	{
1619	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1620	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1621	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1622	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1623	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1624	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1625	return;
1626	}
1627
1628
1629	/**
1630	* Raw-mode switcher hook - disable VT-x if it's active and the current
1631	* switcher turns off paging.
1632	*
1633	* @returns VBox status code.
1634	* @param pVM Pointer to the VM.
1635	* @param enmSwitcher The switcher we're about to use.
1636	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1637	*/
1638	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1639	{
1640	NOREF(pVM);
1641
1642	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1643
1644	*pfVTxDisabled = false;
1645
1646	/* No such issues with AMD-V */
1647	if (!g_HmR0.vmx.fSupported)
1648	return VINF_SUCCESS;
1649
1650	/* Check if the switching we're up to is safe. */
1651	switch (enmSwitcher)
1652	{
1653	case VMMSWITCHER_32_TO_32:
1654	case VMMSWITCHER_PAE_TO_PAE:
1655	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1656
1657	case VMMSWITCHER_32_TO_PAE:
1658	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1659	case VMMSWITCHER_AMD64_TO_32:
1660	case VMMSWITCHER_AMD64_TO_PAE:
1661	break; /* unsafe switchers */
1662
1663	default:
1664	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1665	}
1666
1667	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1668	regardless of whether we're currently using VT-x or not. */
1669	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1670	{
1671	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1672	return VINF_SUCCESS;
1673	}
1674
1675	/** @todo Check if this code is presumptive wrt other VT-x users on the
1676	* system... */
1677
1678	/* Nothing to do if we haven't enabled VT-x. */
1679	if (!g_HmR0.fEnabled)
1680	return VINF_SUCCESS;
1681
1682	/* Local init implies the CPU is currently not in VMX root mode. */
1683	if (!g_HmR0.fGlobalInit)
1684	return VINF_SUCCESS;
1685
1686	/* Ok, disable VT-x. */
1687	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1688	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1689
1690	*pfVTxDisabled = true;
1691	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1692	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1693	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1694	}
1695
1696
1697	/**
1698	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1699	* switcher turned off paging.
1700	*
1701	* @param pVM Pointer to the VM.
1702	* @param fVTxDisabled Whether VT-x was disabled or not.
1703	*/
1704	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1705	{
1706	Assert(!ASMIntAreEnabled());
1707
1708	if (!fVTxDisabled)
1709	return; /* nothing to do */
1710
1711	Assert(g_HmR0.vmx.fSupported);
1712	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1713	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1714	else
1715	{
1716	Assert(g_HmR0.fEnabled);
1717	Assert(g_HmR0.fGlobalInit);
1718
1719	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1720	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1721
1722	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1723	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1724	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HmR0.vmx.Msrs);
1725	}
1726	}
1727
1728	#ifdef VBOX_STRICT
1729
1730	/**
1731	* Dumps a descriptor.
1732	*
1733	* @param pDesc Descriptor to dump.
1734	* @param Sel Selector number.
1735	* @param pszMsg Message to prepend the log entry with.
1736	*/
1737	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1738	{
1739	/*
1740	* Make variable description string.
1741	*/
1742	static struct
1743	{
1744	unsigned cch;
1745	const char *psz;
1746	} const s_aTypes[32] =
1747	{
1748	# define STRENTRY(str) { sizeof(str) - 1, str }
1749
1750	/* system */
1751	# if HC_ARCH_BITS == 64
1752	STRENTRY("Reserved0 "), /* 0x00 */
1753	STRENTRY("Reserved1 "), /* 0x01 */
1754	STRENTRY("LDT "), /* 0x02 */
1755	STRENTRY("Reserved3 "), /* 0x03 */
1756	STRENTRY("Reserved4 "), /* 0x04 */
1757	STRENTRY("Reserved5 "), /* 0x05 */
1758	STRENTRY("Reserved6 "), /* 0x06 */
1759	STRENTRY("Reserved7 "), /* 0x07 */
1760	STRENTRY("Reserved8 "), /* 0x08 */
1761	STRENTRY("TSS64Avail "), /* 0x09 */
1762	STRENTRY("ReservedA "), /* 0x0a */
1763	STRENTRY("TSS64Busy "), /* 0x0b */
1764	STRENTRY("Call64 "), /* 0x0c */
1765	STRENTRY("ReservedD "), /* 0x0d */
1766	STRENTRY("Int64 "), /* 0x0e */
1767	STRENTRY("Trap64 "), /* 0x0f */
1768	# else
1769	STRENTRY("Reserved0 "), /* 0x00 */
1770	STRENTRY("TSS16Avail "), /* 0x01 */
1771	STRENTRY("LDT "), /* 0x02 */
1772	STRENTRY("TSS16Busy "), /* 0x03 */
1773	STRENTRY("Call16 "), /* 0x04 */
1774	STRENTRY("Task "), /* 0x05 */
1775	STRENTRY("Int16 "), /* 0x06 */
1776	STRENTRY("Trap16 "), /* 0x07 */
1777	STRENTRY("Reserved8 "), /* 0x08 */
1778	STRENTRY("TSS32Avail "), /* 0x09 */
1779	STRENTRY("ReservedA "), /* 0x0a */
1780	STRENTRY("TSS32Busy "), /* 0x0b */
1781	STRENTRY("Call32 "), /* 0x0c */
1782	STRENTRY("ReservedD "), /* 0x0d */
1783	STRENTRY("Int32 "), /* 0x0e */
1784	STRENTRY("Trap32 "), /* 0x0f */
1785	# endif
1786	/* non system */
1787	STRENTRY("DataRO "), /* 0x10 */
1788	STRENTRY("DataRO Accessed "), /* 0x11 */
1789	STRENTRY("DataRW "), /* 0x12 */
1790	STRENTRY("DataRW Accessed "), /* 0x13 */
1791	STRENTRY("DataDownRO "), /* 0x14 */
1792	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1793	STRENTRY("DataDownRW "), /* 0x16 */
1794	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1795	STRENTRY("CodeEO "), /* 0x18 */
1796	STRENTRY("CodeEO Accessed "), /* 0x19 */
1797	STRENTRY("CodeER "), /* 0x1a */
1798	STRENTRY("CodeER Accessed "), /* 0x1b */
1799	STRENTRY("CodeConfEO "), /* 0x1c */
1800	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1801	STRENTRY("CodeConfER "), /* 0x1e */
1802	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1803	# undef SYSENTRY
1804	};
1805	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1806	char szMsg[128];
1807	char *psz = &szMsg[0];
1808	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1809	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1810	psz += s_aTypes[i].cch;
1811
1812	if (pDesc->Gen.u1Present)
1813	ADD_STR(psz, "Present ");
1814	else
1815	ADD_STR(psz, "Not-Present ");
1816	# if HC_ARCH_BITS == 64
1817	if (pDesc->Gen.u1Long)
1818	ADD_STR(psz, "64-bit ");
1819	else
1820	ADD_STR(psz, "Comp ");
1821	# else
1822	if (pDesc->Gen.u1Granularity)
1823	ADD_STR(psz, "Page ");
1824	if (pDesc->Gen.u1DefBig)
1825	ADD_STR(psz, "32-bit ");
1826	else
1827	ADD_STR(psz, "16-bit ");
1828	# endif
1829	# undef ADD_STR
1830	*psz = '\0';
1831
1832	/*
1833	* Limit and Base and format the output.
1834	*/
1835	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1836
1837	# if HC_ARCH_BITS == 64
1838	uint64_t u32Base = X86DESC64_BASE(pDesc);
1839	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1840	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1841	# else
1842	uint32_t u32Base = X86DESC_BASE(pDesc);
1843	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1844	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1845	# endif
1846	}
1847
1848
1849	/**
1850	* Formats a full register dump.
1851	*
1852	* @param pVM Pointer to the VM.
1853	* @param pVCpu Pointer to the VMCPU.
1854	* @param pCtx Pointer to the CPU context.
1855	*/
1856	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1857	{
1858	NOREF(pVM);
1859
1860	/*
1861	* Format the flags.
1862	*/
1863	static struct
1864	{
1865	const char pszSet; const char pszClear; uint32_t fFlag;
1866	} const s_aFlags[] =
1867	{
1868	{ "vip", NULL, X86_EFL_VIP },
1869	{ "vif", NULL, X86_EFL_VIF },
1870	{ "ac", NULL, X86_EFL_AC },
1871	{ "vm", NULL, X86_EFL_VM },
1872	{ "rf", NULL, X86_EFL_RF },
1873	{ "nt", NULL, X86_EFL_NT },
1874	{ "ov", "nv", X86_EFL_OF },
1875	{ "dn", "up", X86_EFL_DF },
1876	{ "ei", "di", X86_EFL_IF },
1877	{ "tf", NULL, X86_EFL_TF },
1878	{ "nt", "pl", X86_EFL_SF },
1879	{ "nz", "zr", X86_EFL_ZF },
1880	{ "ac", "na", X86_EFL_AF },
1881	{ "po", "pe", X86_EFL_PF },
1882	{ "cy", "nc", X86_EFL_CF },
1883	};
1884	char szEFlags[80];
1885	char *psz = szEFlags;
1886	uint32_t uEFlags = pCtx->eflags.u32;
1887	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1888	{
1889	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1890	if (pszAdd)
1891	{
1892	strcpy(psz, pszAdd);
1893	psz += strlen(pszAdd);
1894	*psz++ = ' ';
1895	}
1896	}
1897	psz[-1] = '\0';
1898
1899
1900	/*
1901	* Format the registers.
1902	*/
1903	if (CPUMIsGuestIn64BitCode(pVCpu))
1904	{
1905	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1906	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1907	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1908	"r14=%016RX64 r15=%016RX64\n"
1909	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1910	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1911	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1912	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1913	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1914	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1915	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1916	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1917	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1918	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1919	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1920	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1921	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1922	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1923	,
1924	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1925	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1926	pCtx->r14, pCtx->r15,
1927	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1928	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1929	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1930	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1931	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1932	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1933	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1934	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1935	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1936	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1937	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1938	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1939	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1940	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1941	}
1942	else
1943	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1944	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1945	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1946	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1947	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1948	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1949	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1950	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1951	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1952	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1953	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1954	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1955	,
1956	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1957	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1958	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1959	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1960	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1961	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1962	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1963	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1964	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1965	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1966	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1967	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1968
1969	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1970	Log(("FPU:\n"
1971	"FCW=%04x FSW=%04x FTW=%02x\n"
1972	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1973	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1974	,
1975	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1976	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1977	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1978	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1979
1980	Log(("MSR:\n"
1981	"EFER =%016RX64\n"
1982	"PAT =%016RX64\n"
1983	"STAR =%016RX64\n"
1984	"CSTAR =%016RX64\n"
1985	"LSTAR =%016RX64\n"
1986	"SFMASK =%016RX64\n"
1987	"KERNELGSBASE =%016RX64\n",
1988	pCtx->msrEFER,
1989	pCtx->msrPAT,
1990	pCtx->msrSTAR,
1991	pCtx->msrCSTAR,
1992	pCtx->msrLSTAR,
1993	pCtx->msrSFMASK,
1994	pCtx->msrKERNELGSBASE));
1995	}
1996
1997	#endif /* VBOX_STRICT */
1998

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 56365

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