HMR0.cpp@ 56619

Last change on this file since 56619 was 56619, checked in by vboxsync, 9 years ago
VMM/HMR0: revert r101249, added comment to clarify usage.
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1	/* $Id: HMR0.cpp 56619 2015-06-24 12:15:18Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <VBox/vmm/hm.h>
23	#include <VBox/vmm/pgm.h>
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/hm_vmx.h>
27	#include <VBox/vmm/hm_svm.h>
28	#include <VBox/vmm/gim.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState, (PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost, void *pvArg));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM ,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	uint64_t u64HostCr4;
117
118	/** Host EFER value (set by ring-0 VMX init) */
119	uint64_t u64HostEfer;
120
121	/** VMX MSR values */
122	VMXMSRS Msrs;
123
124	/* Last instruction error */
125	uint32_t ulLastInstrError;
126	} vmx;
127
128	/** AMD-V information. */
129	struct
130	{
131	/* HWCR MSR (for diagnostics) */
132	uint64_t u64MsrHwcr;
133
134	/** SVM revision. */
135	uint32_t u32Rev;
136
137	/** SVM feature bits from cpuid 0x8000000a */
138	uint32_t u32Features;
139
140	/** Set by us to indicate SVM is supported by the CPU. */
141	bool fSupported;
142	} svm;
143	/** Saved error from detection */
144	int32_t lLastError;
145
146	/** CPUID 0x80000001 ecx:edx features */
147	struct
148	{
149	uint32_t u32AMDFeatureECX;
150	uint32_t u32AMDFeatureEDX;
151	} cpuid;
152
153	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
154	* enabled and disabled each time it's used to execute guest code. */
155	bool fGlobalInit;
156	/** Indicates whether the host is suspending or not. We'll refuse a few
157	* actions when the host is being suspended to speed up the suspending and
158	* avoid trouble. */
159	volatile bool fSuspended;
160
161	/** Whether we've already initialized all CPUs.
162	* @remarks We could check the EnableAllCpusOnce state, but this is
163	* simpler and hopefully easier to understand. */
164	bool fEnabled;
165	/** Serialize initialization in HMR0EnableAllCpus. */
166	RTONCE EnableAllCpusOnce;
167	} g_HmR0;
168
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	/**
212	* Get the CPU ID on which the failure status code was reported.
213	*
214	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
215	* @param pFirstRc The first return code structure.
216	*/
217	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
218	{
219	return pFirstRc->idCpu;
220	}
221	#endif /* VBOX_STRICT */
222
223
224	/** @name Dummy callback handlers.
225	* @{ */
226
227	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
228	{
229	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
234	{
235	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
236	}
237
238	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
239	bool fEnabledBySystem, void *pvArg)
240	{
241	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
242	return VINF_SUCCESS;
243	}
244
245	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
246	{
247	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
252	{
253	NOREF(pVM);
254	return VINF_SUCCESS;
255	}
256
257	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
258	{
259	NOREF(pVM);
260	return VINF_SUCCESS;
261	}
262
263	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
264	{
265	NOREF(pVM);
266	return VINF_SUCCESS;
267	}
268
269	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
270	{
271	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
272	return VINF_SUCCESS;
273	}
274
275	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
276	{
277	NOREF(pVM); NOREF(pVCpu);
278	return VINF_SUCCESS;
279	}
280
281	/** @} */
282
283
284	/**
285	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
286	* Down at the Rate Specified" erratum.
287	*
288	* Errata names and related steppings:
289	* - BA86 - D0.
290	* - AAX65 - C2.
291	* - AAU65 - C2, K0.
292	* - AAO95 - B1.
293	* - AAT59 - C2.
294	* - AAK139 - D0.
295	* - AAM126 - C0, C1, D0.
296	* - AAN92 - B1.
297	* - AAJ124 - C0, D0.
298	*
299	* - AAP86 - B1.
300	*
301	* Steppings: B1, C0, C1, C2, D0, K0.
302	*
303	* @returns true if subject to it, false if not.
304	*/
305	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
306	{
307	uint32_t u = ASMCpuId_EAX(1);
308	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
309	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
310	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
311	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
312	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
313	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
314	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
315	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
316	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
317	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
318	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
319	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
320	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
321	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
322	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
323	)
324	return true;
325	return false;
326	}
327
328
329	/**
330	* Intel specific initialization code.
331	*
332	* @returns VBox status code (will only fail if out of memory).
333	*/
334	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
335	{
336	/*
337	* Check that all the required VT-x features are present.
338	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
339	*/
340	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
341	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
342	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
343	)
344	{
345	/** @todo move this into a separate function. */
346	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
347	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
348
349	/*
350	* First try use native kernel API for controlling VT-x.
351	* (This is only supported by some Mac OS X kernels atm.)
352	*/
353	int rc = g_HmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
354	g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
355	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
356	{
357	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
358	if (RT_SUCCESS(rc))
359	{
360	g_HmR0.vmx.fSupported = true;
361	rc = SUPR0EnableVTx(false /* fEnable */);
362	AssertLogRelRC(rc);
363	}
364	}
365	else
366	{
367	/* We need to check if VT-x has been properly initialized on all
368	CPUs. Some BIOSes do a lousy job. */
369	HMR0FIRSTRC FirstRc;
370	hmR0FirstRcInit(&FirstRc);
371	g_HmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
372	if (RT_SUCCESS(g_HmR0.lLastError))
373	g_HmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
374	}
375	if (RT_SUCCESS(g_HmR0.lLastError))
376	{
377	/* Reread in case it was changed by SUPR0GetVmxUsability(). */
378	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
379
380	/*
381	* Read all relevant registers and MSRs.
382	*/
383	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
384	g_HmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
385	g_HmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
386	g_HmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
387	g_HmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
388	g_HmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
389	g_HmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
390	g_HmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
391	g_HmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
392	g_HmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
393	g_HmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
394	g_HmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
395	g_HmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
396	/* VPID 16 bits ASID. */
397	g_HmR0.uMaxAsid = 0x10000; /* exclusive */
398
399	if (g_HmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
400	{
401	g_HmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
402	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
403	g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
404
405	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
406	g_HmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
407	}
408
409	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
410	{
411	/*
412	* Enter root mode
413	*/
414	RTR0MEMOBJ hScatchMemObj;
415	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
416	if (RT_FAILURE(rc))
417	{
418	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
419	return rc;
420	}
421
422	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
423	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
424	ASMMemZeroPage(pvScatchPage);
425
426	/* Set revision dword at the beginning of the structure. */
427	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HmR0.vmx.Msrs.u64BasicInfo);
428
429	/* Make sure we don't get rescheduled to another cpu during this probe. */
430	RTCCUINTREG fFlags = ASMIntDisableFlags();
431
432	/*
433	* Check CR4.VMXE
434	*/
435	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
436	if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
437	{
438	/* In theory this bit could be cleared behind our back. Which would cause
439	#UD faults when we try to execute the VMX instructions... */
440	ASMSetCR4(g_HmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
441	}
442
443	/*
444	* The only way of checking if we're in VMX root mode or not is to try and enter it.
445	* There is no instruction or control bit that tells us if we're in VMX root mode.
446	* Therefore, try and enter VMX root mode here.
447	*/
448	rc = VMXEnable(HCPhysScratchPage);
449	if (RT_SUCCESS(rc))
450	{
451	g_HmR0.vmx.fSupported = true;
452	VMXDisable();
453	}
454	else
455	{
456	/*
457	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
458	* it will crash the host when we enter raw mode, because:
459	*
460	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
461	* this bit), and
462	* (b) turning off paging causes a #GP (unavoidable when switching
463	* from long to 32 bits mode or 32 bits to PAE).
464	*
465	* They should fix their code, but until they do we simply refuse to run.
466	*/
467	g_HmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
468	Assert(g_HmR0.vmx.fSupported == false);
469	}
470
471	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
472	if it wasn't so before (some software could incorrectly
473	think it's in VMX mode). */
474	ASMSetCR4(g_HmR0.vmx.u64HostCr4);
475	ASMSetFlags(fFlags);
476
477	RTR0MemObjFree(hScatchMemObj, false);
478	}
479
480	if (g_HmR0.vmx.fSupported)
481	{
482	rc = VMXR0GlobalInit();
483	if (RT_FAILURE(rc))
484	g_HmR0.lLastError = rc;
485
486	/*
487	* Install the VT-x methods.
488	*/
489	g_HmR0.pfnEnterSession = VMXR0Enter;
490	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
491	g_HmR0.pfnSaveHostState = VMXR0SaveHostState;
492	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
493	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
494	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
495	g_HmR0.pfnInitVM = VMXR0InitVM;
496	g_HmR0.pfnTermVM = VMXR0TermVM;
497	g_HmR0.pfnSetupVM = VMXR0SetupVM;
498
499	/*
500	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
501	* Timer Does Not Count Down at the Rate Specified" erratum.
502	*/
503	if (g_HmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
504	{
505	g_HmR0.vmx.fUsePreemptTimer = true;
506	g_HmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HmR0.vmx.Msrs.u64Misc);
507	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
508	g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
509	}
510	}
511	}
512	#ifdef LOG_ENABLED
513	else
514	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HmR0.lLastError);
515	#endif
516	}
517	else
518	g_HmR0.lLastError = VERR_VMX_NO_VMX;
519	return VINF_SUCCESS;
520	}
521
522
523	/**
524	* AMD-specific initialization code.
525	*
526	* @returns VBox status code.
527	*/
528	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
529	{
530	/*
531	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
532	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
533	*/
534	int rc;
535	if ( (g_HmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
536	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
537	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
538	&& ASMIsValidExtRange(uMaxExtLeaf)
539	&& uMaxExtLeaf >= 0x8000000a
540	)
541	{
542	/* Call the global AMD-V initialization routine. */
543	rc = SVMR0GlobalInit();
544	if (RT_FAILURE(rc))
545	{
546	g_HmR0.lLastError = rc;
547	return rc;
548	}
549
550	/*
551	* Install the AMD-V methods.
552	*/
553	g_HmR0.pfnEnterSession = SVMR0Enter;
554	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
555	g_HmR0.pfnSaveHostState = SVMR0SaveHostState;
556	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
557	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
558	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
559	g_HmR0.pfnInitVM = SVMR0InitVM;
560	g_HmR0.pfnTermVM = SVMR0TermVM;
561	g_HmR0.pfnSetupVM = SVMR0SetupVM;
562
563	/* Query AMD features. */
564	uint32_t u32Dummy;
565	ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
566
567	/*
568	* We need to check if AMD-V has been properly initialized on all CPUs.
569	* Some BIOSes might do a poor job.
570	*/
571	HMR0FIRSTRC FirstRc;
572	hmR0FirstRcInit(&FirstRc);
573	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
574	AssertRC(rc);
575	if (RT_SUCCESS(rc))
576	rc = hmR0FirstRcGetStatus(&FirstRc);
577	#ifndef DEBUG_bird
578	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
579	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
580	#endif
581	if (RT_SUCCESS(rc))
582	{
583	/* Read the HWCR MSR for diagnostics. */
584	g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
585	g_HmR0.svm.fSupported = true;
586	}
587	else
588	{
589	g_HmR0.lLastError = rc;
590	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
591	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
592	}
593	}
594	else
595	{
596	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
597	g_HmR0.lLastError = VERR_SVM_NO_SVM;
598	}
599	return rc;
600	}
601
602
603	/**
604	* Does global Ring-0 HM initialization (at module init).
605	*
606	* @returns VBox status code.
607	*/
608	VMMR0_INT_DECL(int) HMR0Init(void)
609	{
610	/*
611	* Initialize the globals.
612	*/
613	g_HmR0.fEnabled = false;
614	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
615	g_HmR0.EnableAllCpusOnce = s_OnceInit;
616	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
617	{
618	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
619	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
620	}
621
622	/* Fill in all callbacks with placeholders. */
623	g_HmR0.pfnEnterSession = hmR0DummyEnter;
624	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
625	g_HmR0.pfnSaveHostState = hmR0DummySaveHostState;
626	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
627	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
628	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
629	g_HmR0.pfnInitVM = hmR0DummyInitVM;
630	g_HmR0.pfnTermVM = hmR0DummyTermVM;
631	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
632
633	/* Default is global VT-x/AMD-V init. */
634	g_HmR0.fGlobalInit = true;
635
636	/*
637	* Make sure aCpuInfo is big enough for all the CPUs on this system.
638	*/
639	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
640	{
641	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
642	return VERR_TOO_MANY_CPUS;
643	}
644
645	/*
646	* Check for VT-x and AMD-V capabilities.
647	*/
648	int rc;
649	if (ASMHasCpuId())
650	{
651	/* Standard features. */
652	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
653	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
654	if (ASMIsValidStdRange(uMaxLeaf))
655	{
656	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
657	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
658
659	/* Query AMD features. */
660	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
661	if (ASMIsValidExtRange(uMaxExtLeaf))
662	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
663	&g_HmR0.cpuid.u32AMDFeatureECX,
664	&g_HmR0.cpuid.u32AMDFeatureEDX);
665	else
666	g_HmR0.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureEDX = 0;
667
668	/* Go to CPU specific initialization code. */
669	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
670	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
671	{
672	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
673	if (RT_FAILURE(rc))
674	return rc;
675	}
676	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
677	{
678	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
679	if (RT_FAILURE(rc))
680	return rc;
681	}
682	else
683	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
684	}
685	else
686	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
687	}
688	else
689	g_HmR0.lLastError = VERR_HM_NO_CPUID;
690
691	/*
692	* Register notification callbacks that we can use to disable/enable CPUs
693	* when brought offline/online or suspending/resuming.
694	*/
695	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
696	{
697	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
698	AssertRC(rc);
699
700	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
701	AssertRC(rc);
702	}
703
704	/* We return success here because module init shall not fail if HM
705	fails to initialize. */
706	return VINF_SUCCESS;
707	}
708
709
710	/**
711	* Does global Ring-0 HM termination (at module termination).
712	*
713	* @returns VBox status code.
714	*/
715	VMMR0_INT_DECL(int) HMR0Term(void)
716	{
717	int rc;
718	if ( g_HmR0.vmx.fSupported
719	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
720	{
721	/*
722	* Simple if the host OS manages VT-x.
723	*/
724	Assert(g_HmR0.fGlobalInit);
725	rc = SUPR0EnableVTx(false /* fEnable */);
726
727	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
728	{
729	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
730	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
731	}
732	}
733	else
734	{
735	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
736
737	/* Doesn't really matter if this fails. */
738	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
739	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
740
741	/*
742	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
743	*/
744	if (g_HmR0.fGlobalInit)
745	{
746	HMR0FIRSTRC FirstRc;
747	hmR0FirstRcInit(&FirstRc);
748	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
749	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
750	if (RT_SUCCESS(rc))
751	rc = hmR0FirstRcGetStatus(&FirstRc);
752	}
753
754	/*
755	* Free the per-cpu pages used for VT-x and AMD-V.
756	*/
757	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
758	{
759	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
760	{
761	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
762	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
763	}
764	}
765	}
766
767	/** @todo This needs cleaning up. There's no matching
768	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
769	* should move into their respective modules. */
770	/* Finally, call global VT-x/AMD-V termination. */
771	if (g_HmR0.vmx.fSupported)
772	VMXR0GlobalTerm();
773	else if (g_HmR0.svm.fSupported)
774	SVMR0GlobalTerm();
775
776	return rc;
777	}
778
779
780	/**
781	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
782	* on a CPU.
783	*
784	* @param idCpu The identifier for the CPU the function is called on.
785	* @param pvUser1 Pointer to the first RC structure.
786	* @param pvUser2 Ignored.
787	*/
788	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
789	{
790	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
791	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
792	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
793	NOREF(idCpu); NOREF(pvUser2);
794
795	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
796	hmR0FirstRcSetStatus(pFirstRc, rc);
797	}
798
799
800	/**
801	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
802	* on a CPU.
803	*
804	* @param idCpu The identifier for the CPU the function is called on.
805	* @param pvUser1 Pointer to the first RC structure.
806	* @param pvUser2 Ignored.
807	*/
808	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
809	{
810	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
811	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
812	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
813	NOREF(idCpu); NOREF(pvUser2);
814
815	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
816	hmR0FirstRcSetStatus(pFirstRc, rc);
817	}
818
819
820	/**
821	* Enable VT-x or AMD-V on the current CPU
822	*
823	* @returns VBox status code.
824	* @param pVM Pointer to the VM (can be NULL).
825	* @param idCpu The identifier for the CPU the function is called on.
826	*
827	* @remarks Maybe called with interrupts disabled!
828	*/
829	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
830	{
831	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
832
833	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
834	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
835	Assert(!pCpu->fConfigured);
836	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
837
838	pCpu->idCpu = idCpu;
839	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
840
841	int rc;
842	if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
843	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
844	else
845	{
846	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
847	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
848	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0 /* iPage */);
849
850	if (g_HmR0.vmx.fSupported)
851	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HmR0.vmx.Msrs);
852	else
853	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
854	}
855	if (RT_SUCCESS(rc))
856	pCpu->fConfigured = true;
857
858	return rc;
859	}
860
861
862	/**
863	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
864	*
865	* @param idCpu The identifier for the CPU the function is called on.
866	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
867	* @param pvUser2 The 2nd user argument.
868	*/
869	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
870	{
871	PVM pVM = (PVM)pvUser1; /* can be NULL! */
872	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
873	AssertReturnVoid(g_HmR0.fGlobalInit);
874	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
875	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
876	}
877
878
879	/**
880	* RTOnce callback employed by HMR0EnableAllCpus.
881	*
882	* @returns VBox status code.
883	* @param pvUser Pointer to the VM.
884	* @param pvUserIgnore NULL, ignored.
885	*/
886	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
887	{
888	PVM pVM = (PVM)pvUser;
889
890	/*
891	* Indicate that we've initialized.
892	*
893	* Note! There is a potential race between this function and the suspend
894	* notification. Kind of unlikely though, so ignored for now.
895	*/
896	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
897	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
898
899	/*
900	* The global init variable is set by the first VM.
901	*/
902	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
903
904	#ifdef VBOX_STRICT
905	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
906	{
907	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
908	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
909	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
910	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
911	}
912	#endif
913
914	int rc;
915	if ( g_HmR0.vmx.fSupported
916	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
917	{
918	/*
919	* Global VT-x initialization API (only darwin for now).
920	*/
921	rc = SUPR0EnableVTx(true /* fEnable */);
922	if (RT_SUCCESS(rc))
923	{
924	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
925	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
926	}
927	else
928	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
929	}
930	else
931	{
932	/*
933	* We're doing the job ourselves.
934	*/
935	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
936	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
937	{
938	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
939
940	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
941	{
942	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
943	AssertLogRelRCReturn(rc, rc);
944
945	void *pvR0 = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
946	ASMMemZeroPage(pvR0);
947	}
948	}
949
950	rc = VINF_SUCCESS;
951	}
952
953	if ( RT_SUCCESS(rc)
954	&& g_HmR0.fGlobalInit)
955	{
956	/* First time, so initialize each cpu/core. */
957	HMR0FIRSTRC FirstRc;
958	hmR0FirstRcInit(&FirstRc);
959	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
960	if (RT_SUCCESS(rc))
961	rc = hmR0FirstRcGetStatus(&FirstRc);
962	}
963
964	return rc;
965	}
966
967
968	/**
969	* Sets up HM on all cpus.
970	*
971	* @returns VBox status code.
972	* @param pVM Pointer to the VM.
973	*/
974	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
975	{
976	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
977	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
978	return VERR_HM_SUSPEND_PENDING;
979
980	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
981	}
982
983
984	/**
985	* Disable VT-x or AMD-V on the current CPU.
986	*
987	* @returns VBox status code.
988	* @param idCpu The identifier for the CPU this function is called on.
989	*
990	* @remarks Must be called with preemption disabled.
991	*/
992	static int hmR0DisableCpu(RTCPUID idCpu)
993	{
994	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
995
996	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
997	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
998	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
999	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1000	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1001	AssertRelease(idCpu == RTMpCpuId());
1002
1003	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1004	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1005
1006	int rc;
1007	if (pCpu->fConfigured)
1008	{
1009	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1010	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1011
1012	rc = g_HmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1013	AssertRCReturn(rc, rc);
1014
1015	pCpu->fConfigured = false;
1016	pCpu->idCpu = NIL_RTCPUID;
1017	}
1018	else
1019	rc = VINF_SUCCESS; /* nothing to do */
1020	return rc;
1021	}
1022
1023
1024	/**
1025	* Worker function passed to RTMpOnAll() that is to be called on the target
1026	* CPUs.
1027	*
1028	* @param idCpu The identifier for the CPU the function is called on.
1029	* @param pvUser1 The 1st user argument.
1030	* @param pvUser2 Opaque pointer to the FirstRc.
1031	*/
1032	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1033	{
1034	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1035	AssertReturnVoid(g_HmR0.fGlobalInit);
1036	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1037	}
1038
1039
1040	/**
1041	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1042	* CPU.
1043	*
1044	* @param idCpu The identifier for the CPU the function is called on.
1045	* @param pvUser1 Null, not used.
1046	* @param pvUser2 Null, not used.
1047	*/
1048	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1049	{
1050	NOREF(pvUser1);
1051	NOREF(pvUser2);
1052	hmR0DisableCpu(idCpu);
1053	}
1054
1055
1056	/**
1057	* Callback function invoked when a cpu goes online or offline.
1058	*
1059	* @param enmEvent The Mp event.
1060	* @param idCpu The identifier for the CPU the function is called on.
1061	* @param pvData Opaque data (PVM pointer).
1062	*/
1063	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1064	{
1065	NOREF(pvData);
1066	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1067
1068	/*
1069	* We only care about uninitializing a CPU that is going offline. When a
1070	* CPU comes online, the initialization is done lazily in HMR0Enter().
1071	*/
1072	switch (enmEvent)
1073	{
1074	case RTMPEVENT_OFFLINE:
1075	{
1076	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1077	RTThreadPreemptDisable(&PreemptState);
1078	if (idCpu == RTMpCpuId())
1079	{
1080	int rc = hmR0DisableCpu(idCpu);
1081	AssertRC(rc);
1082	RTThreadPreemptRestore(&PreemptState);
1083	}
1084	else
1085	{
1086	RTThreadPreemptRestore(&PreemptState);
1087	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1088	}
1089	break;
1090	}
1091
1092	default:
1093	break;
1094	}
1095	}
1096
1097
1098	/**
1099	* Called whenever a system power state change occurs.
1100	*
1101	* @param enmEvent The Power event.
1102	* @param pvUser User argument.
1103	*/
1104	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1105	{
1106	NOREF(pvUser);
1107	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1108
1109	#ifdef LOG_ENABLED
1110	if (enmEvent == RTPOWEREVENT_SUSPEND)
1111	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1112	else
1113	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1114	#endif
1115
1116	if (enmEvent == RTPOWEREVENT_SUSPEND)
1117	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1118
1119	if (g_HmR0.fEnabled)
1120	{
1121	int rc;
1122	HMR0FIRSTRC FirstRc;
1123	hmR0FirstRcInit(&FirstRc);
1124
1125	if (enmEvent == RTPOWEREVENT_SUSPEND)
1126	{
1127	if (g_HmR0.fGlobalInit)
1128	{
1129	/* Turn off VT-x or AMD-V on all CPUs. */
1130	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1131	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1132	}
1133	/* else nothing to do here for the local init case */
1134	}
1135	else
1136	{
1137	/* Reinit the CPUs from scratch as the suspend state might have
1138	messed with the MSRs. (lousy BIOSes as usual) */
1139	if (g_HmR0.vmx.fSupported)
1140	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1141	else
1142	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1143	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1144	if (RT_SUCCESS(rc))
1145	rc = hmR0FirstRcGetStatus(&FirstRc);
1146	#ifdef LOG_ENABLED
1147	if (RT_FAILURE(rc))
1148	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1149	#endif
1150	if (g_HmR0.fGlobalInit)
1151	{
1152	/* Turn VT-x or AMD-V back on on all CPUs. */
1153	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1154	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1155	}
1156	/* else nothing to do here for the local init case */
1157	}
1158	}
1159
1160	if (enmEvent == RTPOWEREVENT_RESUME)
1161	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1162	}
1163
1164
1165	/**
1166	* Does ring-0 per-VM HM initialization.
1167	*
1168	* This will copy HM global into the VM structure and call the CPU specific
1169	* init routine which will allocate resources for each virtual CPU and such.
1170	*
1171	* @returns VBox status code.
1172	* @param pVM Pointer to the VM.
1173	*
1174	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1175	* vmR3InitRing3().
1176	*/
1177	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1178	{
1179	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1180
1181	#ifdef LOG_ENABLED
1182	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1183	#endif
1184
1185	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1186	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1187	return VERR_HM_SUSPEND_PENDING;
1188
1189	/*
1190	* Copy globals to the VM structure.
1191	*/
1192	pVM->hm.s.vmx.fSupported = g_HmR0.vmx.fSupported;
1193	pVM->hm.s.svm.fSupported = g_HmR0.svm.fSupported;
1194
1195	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1196	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.vmx.cPreemptTimerShift;
1197	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.vmx.u64HostCr4;
1198	pVM->hm.s.vmx.u64HostEfer = g_HmR0.vmx.u64HostEfer;
1199	pVM->hm.s.vmx.Msrs = g_HmR0.vmx.Msrs;
1200	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.svm.u64MsrHwcr;
1201	pVM->hm.s.svm.u32Rev = g_HmR0.svm.u32Rev;
1202	pVM->hm.s.svm.u32Features = g_HmR0.svm.u32Features;
1203	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureECX;
1204	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HmR0.cpuid.u32AMDFeatureEDX;
1205	pVM->hm.s.lLastError = g_HmR0.lLastError;
1206	pVM->hm.s.uMaxAsid = g_HmR0.uMaxAsid;
1207
1208	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1209	{
1210	pVM->hm.s.cMaxResumeLoops = 1024;
1211	if (RTThreadPreemptIsPendingTrusty())
1212	pVM->hm.s.cMaxResumeLoops = 8192;
1213	}
1214
1215	/*
1216	* Initialize some per-VCPU fields.
1217	*/
1218	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1219	{
1220	PVMCPU pVCpu = &pVM->aCpus[i];
1221	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1222	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1223	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1224
1225	/* We'll aways increment this the first time (host uses ASID 0). */
1226	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1227	}
1228
1229	pVM->hm.s.uHostKernelFeatures = SUPR0GetKernelFeatures();
1230
1231	/*
1232	* Call the hardware specific initialization method.
1233	*/
1234	return g_HmR0.pfnInitVM(pVM);
1235	}
1236
1237
1238	/**
1239	* Does ring-0 per VM HM termination.
1240	*
1241	* @returns VBox status code.
1242	* @param pVM Pointer to the VM.
1243	*/
1244	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1245	{
1246	Log(("HMR0TermVM: %p\n", pVM));
1247	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1248
1249	/*
1250	* Call the hardware specific method.
1251	*
1252	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1253	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1254	*/
1255	return g_HmR0.pfnTermVM(pVM);
1256	}
1257
1258
1259	/**
1260	* Sets up a VT-x or AMD-V session.
1261	*
1262	* This is mostly about setting up the hardware VM state.
1263	*
1264	* @returns VBox status code.
1265	* @param pVM Pointer to the VM.
1266	*/
1267	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1268	{
1269	Log(("HMR0SetupVM: %p\n", pVM));
1270	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1271
1272	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1273	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1274
1275	/* On first entry we'll sync everything. */
1276	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1277	HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1278
1279	/*
1280	* Call the hardware specific setup VM method. This requires the CPU to be
1281	* enabled for AMD-V/VT-x and preemption to be prevented.
1282	*/
1283	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1284	RTThreadPreemptDisable(&PreemptState);
1285	RTCPUID idCpu = RTMpCpuId();
1286
1287	/* Enable VT-x or AMD-V if local init is required. */
1288	int rc;
1289	if (!g_HmR0.fGlobalInit)
1290	{
1291	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1292	rc = hmR0EnableCpu(pVM, idCpu);
1293	if (RT_FAILURE(rc))
1294	{
1295	RTThreadPreemptRestore(&PreemptState);
1296	return rc;
1297	}
1298	}
1299
1300	/* Setup VT-x or AMD-V. */
1301	rc = g_HmR0.pfnSetupVM(pVM);
1302
1303	/* Disable VT-x or AMD-V if local init was done before. */
1304	if (!g_HmR0.fGlobalInit)
1305	{
1306	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1307	int rc2 = hmR0DisableCpu(idCpu);
1308	AssertRC(rc2);
1309	}
1310
1311	RTThreadPreemptRestore(&PreemptState);
1312	return rc;
1313	}
1314
1315
1316	/**
1317	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1318	* required for entering HM context.
1319	*
1320	* @returns VBox status code.
1321	* @param pvCpu Pointer to the VMCPU.
1322	*
1323	* @remarks No-long-jump zone!!!
1324	*/
1325	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1326	{
1327	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1328
1329	int rc = VINF_SUCCESS;
1330	RTCPUID idCpu = RTMpCpuId();
1331	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1332	AssertPtr(pCpu);
1333
1334	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1335	if (!pCpu->fConfigured)
1336	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1337
1338	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1339	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1340
1341	Assert(pCpu->idCpu == idCpu && pCpu->idCpu != NIL_RTCPUID);
1342	pVCpu->hm.s.idEnteredCpu = idCpu;
1343	return rc;
1344	}
1345
1346
1347	/**
1348	* Enters the VT-x or AMD-V session.
1349	*
1350	* @returns VBox status code.
1351	* @param pVM Pointer to the VM.
1352	* @param pVCpu Pointer to the VMCPU.
1353	*
1354	* @remarks This is called with preemption disabled.
1355	*/
1356	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1357	{
1358	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1359	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1360	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1361
1362	/* Load the bare minimum state required for entering HM. */
1363	int rc = HMR0EnterCpu(pVCpu);
1364	AssertRCReturn(rc, rc);
1365
1366	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1367	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1368	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1369	#endif
1370
1371	RTCPUID idCpu = RTMpCpuId();
1372	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1373	Assert(pCpu);
1374	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1375
1376	rc = g_HmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1377	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1378
1379	/* Load the host-state as we may be resuming code after a longjmp and quite
1380	possibly now be scheduled on a different CPU. */
1381	rc = g_HmR0.pfnSaveHostState(pVM, pVCpu);
1382	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1383
1384	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1385	if (fStartedSet)
1386	PGMRZDynMapReleaseAutoSet(pVCpu);
1387	#endif
1388
1389	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1390	if (RT_FAILURE(rc))
1391	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1392	return rc;
1393	}
1394
1395
1396	/**
1397	* Deinitializes the bare minimum state used for HM context and if necessary
1398	* disable HM on the CPU.
1399	*
1400	* @returns VBox status code.
1401	* @param pVCpu Pointer to the VMCPU.
1402	*
1403	* @remarks No-long-jump zone!!!
1404	*/
1405	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1406	{
1407	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1408	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1409
1410	RTCPUID idCpu = RTMpCpuId();
1411	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1412
1413	if ( !g_HmR0.fGlobalInit
1414	&& pCpu->fConfigured)
1415	{
1416	int rc = hmR0DisableCpu(idCpu);
1417	AssertRCReturn(rc, rc);
1418	Assert(!pCpu->fConfigured);
1419	Assert(pCpu->idCpu == NIL_RTCPUID);
1420
1421	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1422	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1423	}
1424
1425	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1426	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1427
1428	return VINF_SUCCESS;
1429	}
1430
1431
1432	/**
1433	* Thread-context hook for HM.
1434	*
1435	* @param enmEvent The thread-context event.
1436	* @param pvUser Opaque pointer to the VMCPU.
1437	*/
1438	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1439	{
1440	PVMCPU pVCpu = (PVMCPU)pvUser;
1441	Assert(pVCpu);
1442	Assert(g_HmR0.pfnThreadCtxCallback);
1443
1444	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1445	}
1446
1447
1448	/**
1449	* Runs guest code in a hardware accelerated VM.
1450	*
1451	* @returns VBox status code.
1452	* @param pVM Pointer to the VM.
1453	* @param pVCpu Pointer to the VMCPU.
1454	*
1455	* @remarks Can be called with preemption enabled if thread-context hooks are
1456	* used!!!
1457	*/
1458	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1459	{
1460	#ifdef VBOX_STRICT
1461	/* With thread-context hooks we would be running this code with preemption enabled. */
1462	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1463	{
1464	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1465	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1466	Assert(pCpu->fConfigured);
1467	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1468	}
1469	#endif
1470
1471	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1472	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1473	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1474	PGMRZDynMapStartAutoSet(pVCpu);
1475	#endif
1476
1477	int rc = g_HmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1478
1479	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1480	PGMRZDynMapReleaseAutoSet(pVCpu);
1481	#endif
1482	return rc;
1483	}
1484
1485	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1486
1487	/**
1488	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1489	*
1490	* @returns VBox status code.
1491	* @param pVM Pointer to the VM.
1492	* @param pVCpu Pointer to the VMCPU.
1493	* @param pCtx Pointer to the guest CPU context.
1494	*/
1495	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1496	{
1497	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1498	if (pVM->hm.s.vmx.fSupported)
1499	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1500	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1501	}
1502
1503
1504	/**
1505	* Save guest debug state (64 bits guest mode & 32 bits host only)
1506	*
1507	* @returns VBox status code.
1508	* @param pVM Pointer to the VM.
1509	* @param pVCpu Pointer to the VMCPU.
1510	* @param pCtx Pointer to the guest CPU context.
1511	*/
1512	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1513	{
1514	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1515	if (pVM->hm.s.vmx.fSupported)
1516	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1517	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1518	}
1519
1520
1521	/**
1522	* Test the 32->64 bits switcher.
1523	*
1524	* @returns VBox status code.
1525	* @param pVM Pointer to the VM.
1526	*/
1527	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1528	{
1529	PVMCPU pVCpu = &pVM->aCpus[0];
1530	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1531	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1532	int rc;
1533
1534	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1535	if (pVM->hm.s.vmx.fSupported)
1536	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1537	else
1538	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1539	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1540
1541	return rc;
1542	}
1543
1544	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1545
1546	/**
1547	* Returns suspend status of the host.
1548	*
1549	* @returns Suspend pending or not.
1550	*/
1551	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1552	{
1553	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1554	}
1555
1556
1557	/**
1558	* Returns the cpu structure for the current cpu.
1559	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1560	*
1561	* @returns The cpu structure pointer.
1562	*/
1563	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1564	{
1565	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1566	RTCPUID idCpu = RTMpCpuId();
1567	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1568	return &g_HmR0.aCpuInfo[idCpu];
1569	}
1570
1571
1572	/**
1573	* Returns the cpu structure for the current cpu.
1574	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1575	*
1576	* @returns The cpu structure pointer.
1577	* @param idCpu id of the VCPU.
1578	*/
1579	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1580	{
1581	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1582	return &g_HmR0.aCpuInfo[idCpu];
1583	}
1584
1585
1586	/**
1587	* Save a pending IO read.
1588	*
1589	* @param pVCpu Pointer to the VMCPU.
1590	* @param GCPtrRip Address of IO instruction.
1591	* @param GCPtrRipNext Address of the next instruction.
1592	* @param uPort Port address.
1593	* @param uAndVal AND mask for saving the result in eax.
1594	* @param cbSize Read size.
1595	*/
1596	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1597	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1598	{
1599	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1600	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1601	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1602	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1603	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1604	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1605	return;
1606	}
1607
1608
1609	/**
1610	* Save a pending IO write.
1611	*
1612	* @param pVCpu Pointer to the VMCPU.
1613	* @param GCPtrRIP Address of IO instruction.
1614	* @param uPort Port address.
1615	* @param uAndVal AND mask for fetching the result from eax.
1616	* @param cbSize Read size.
1617	*/
1618	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1619	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1620	{
1621	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1622	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1623	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1624	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1625	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1626	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1627	return;
1628	}
1629
1630	#ifdef VBOX_WITH_RAW_MODE
1631
1632	/**
1633	* Raw-mode switcher hook - disable VT-x if it's active and the current
1634	* switcher turns off paging.
1635	*
1636	* @returns VBox status code.
1637	* @param pVM Pointer to the VM.
1638	* @param enmSwitcher The switcher we're about to use.
1639	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1640	*/
1641	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1642	{
1643	NOREF(pVM);
1644
1645	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1646
1647	*pfVTxDisabled = false;
1648
1649	/* No such issues with AMD-V */
1650	if (!g_HmR0.vmx.fSupported)
1651	return VINF_SUCCESS;
1652
1653	/* Check if the switching we're up to is safe. */
1654	switch (enmSwitcher)
1655	{
1656	case VMMSWITCHER_32_TO_32:
1657	case VMMSWITCHER_PAE_TO_PAE:
1658	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1659
1660	case VMMSWITCHER_32_TO_PAE:
1661	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1662	case VMMSWITCHER_AMD64_TO_32:
1663	case VMMSWITCHER_AMD64_TO_PAE:
1664	break; /* unsafe switchers */
1665
1666	default:
1667	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1668	}
1669
1670	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1671	regardless of whether we're currently using VT-x or not. */
1672	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1673	{
1674	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1675	return VINF_SUCCESS;
1676	}
1677
1678	/** @todo Check if this code is presumptive wrt other VT-x users on the
1679	* system... */
1680
1681	/* Nothing to do if we haven't enabled VT-x. */
1682	if (!g_HmR0.fEnabled)
1683	return VINF_SUCCESS;
1684
1685	/* Local init implies the CPU is currently not in VMX root mode. */
1686	if (!g_HmR0.fGlobalInit)
1687	return VINF_SUCCESS;
1688
1689	/* Ok, disable VT-x. */
1690	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1691	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1692
1693	*pfVTxDisabled = true;
1694	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1695	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1696	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1697	}
1698
1699
1700	/**
1701	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1702	* switcher turned off paging.
1703	*
1704	* @param pVM Pointer to the VM.
1705	* @param fVTxDisabled Whether VT-x was disabled or not.
1706	*/
1707	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1708	{
1709	Assert(!ASMIntAreEnabled());
1710
1711	if (!fVTxDisabled)
1712	return; /* nothing to do */
1713
1714	Assert(g_HmR0.vmx.fSupported);
1715	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1716	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1717	else
1718	{
1719	Assert(g_HmR0.fEnabled);
1720	Assert(g_HmR0.fGlobalInit);
1721
1722	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1723	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1724
1725	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1726	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1727	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HmR0.vmx.Msrs);
1728	}
1729	}
1730
1731	#endif /* VBOX_WITH_RAW_MODE */
1732	#ifdef VBOX_STRICT
1733
1734	/**
1735	* Dumps a descriptor.
1736	*
1737	* @param pDesc Descriptor to dump.
1738	* @param Sel Selector number.
1739	* @param pszMsg Message to prepend the log entry with.
1740	*/
1741	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1742	{
1743	/*
1744	* Make variable description string.
1745	*/
1746	static struct
1747	{
1748	unsigned cch;
1749	const char *psz;
1750	} const s_aTypes[32] =
1751	{
1752	# define STRENTRY(str) { sizeof(str) - 1, str }
1753
1754	/* system */
1755	# if HC_ARCH_BITS == 64
1756	STRENTRY("Reserved0 "), /* 0x00 */
1757	STRENTRY("Reserved1 "), /* 0x01 */
1758	STRENTRY("LDT "), /* 0x02 */
1759	STRENTRY("Reserved3 "), /* 0x03 */
1760	STRENTRY("Reserved4 "), /* 0x04 */
1761	STRENTRY("Reserved5 "), /* 0x05 */
1762	STRENTRY("Reserved6 "), /* 0x06 */
1763	STRENTRY("Reserved7 "), /* 0x07 */
1764	STRENTRY("Reserved8 "), /* 0x08 */
1765	STRENTRY("TSS64Avail "), /* 0x09 */
1766	STRENTRY("ReservedA "), /* 0x0a */
1767	STRENTRY("TSS64Busy "), /* 0x0b */
1768	STRENTRY("Call64 "), /* 0x0c */
1769	STRENTRY("ReservedD "), /* 0x0d */
1770	STRENTRY("Int64 "), /* 0x0e */
1771	STRENTRY("Trap64 "), /* 0x0f */
1772	# else
1773	STRENTRY("Reserved0 "), /* 0x00 */
1774	STRENTRY("TSS16Avail "), /* 0x01 */
1775	STRENTRY("LDT "), /* 0x02 */
1776	STRENTRY("TSS16Busy "), /* 0x03 */
1777	STRENTRY("Call16 "), /* 0x04 */
1778	STRENTRY("Task "), /* 0x05 */
1779	STRENTRY("Int16 "), /* 0x06 */
1780	STRENTRY("Trap16 "), /* 0x07 */
1781	STRENTRY("Reserved8 "), /* 0x08 */
1782	STRENTRY("TSS32Avail "), /* 0x09 */
1783	STRENTRY("ReservedA "), /* 0x0a */
1784	STRENTRY("TSS32Busy "), /* 0x0b */
1785	STRENTRY("Call32 "), /* 0x0c */
1786	STRENTRY("ReservedD "), /* 0x0d */
1787	STRENTRY("Int32 "), /* 0x0e */
1788	STRENTRY("Trap32 "), /* 0x0f */
1789	# endif
1790	/* non system */
1791	STRENTRY("DataRO "), /* 0x10 */
1792	STRENTRY("DataRO Accessed "), /* 0x11 */
1793	STRENTRY("DataRW "), /* 0x12 */
1794	STRENTRY("DataRW Accessed "), /* 0x13 */
1795	STRENTRY("DataDownRO "), /* 0x14 */
1796	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1797	STRENTRY("DataDownRW "), /* 0x16 */
1798	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1799	STRENTRY("CodeEO "), /* 0x18 */
1800	STRENTRY("CodeEO Accessed "), /* 0x19 */
1801	STRENTRY("CodeER "), /* 0x1a */
1802	STRENTRY("CodeER Accessed "), /* 0x1b */
1803	STRENTRY("CodeConfEO "), /* 0x1c */
1804	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1805	STRENTRY("CodeConfER "), /* 0x1e */
1806	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1807	# undef SYSENTRY
1808	};
1809	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1810	char szMsg[128];
1811	char *psz = &szMsg[0];
1812	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1813	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1814	psz += s_aTypes[i].cch;
1815
1816	if (pDesc->Gen.u1Present)
1817	ADD_STR(psz, "Present ");
1818	else
1819	ADD_STR(psz, "Not-Present ");
1820	# if HC_ARCH_BITS == 64
1821	if (pDesc->Gen.u1Long)
1822	ADD_STR(psz, "64-bit ");
1823	else
1824	ADD_STR(psz, "Comp ");
1825	# else
1826	if (pDesc->Gen.u1Granularity)
1827	ADD_STR(psz, "Page ");
1828	if (pDesc->Gen.u1DefBig)
1829	ADD_STR(psz, "32-bit ");
1830	else
1831	ADD_STR(psz, "16-bit ");
1832	# endif
1833	# undef ADD_STR
1834	*psz = '\0';
1835
1836	/*
1837	* Limit and Base and format the output.
1838	*/
1839	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1840
1841	# if HC_ARCH_BITS == 64
1842	uint64_t u32Base = X86DESC64_BASE(pDesc);
1843	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1844	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1845	# else
1846	uint32_t u32Base = X86DESC_BASE(pDesc);
1847	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1848	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1849	# endif
1850	}
1851
1852
1853	/**
1854	* Formats a full register dump.
1855	*
1856	* @param pVM Pointer to the VM.
1857	* @param pVCpu Pointer to the VMCPU.
1858	* @param pCtx Pointer to the CPU context.
1859	*/
1860	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1861	{
1862	NOREF(pVM);
1863
1864	/*
1865	* Format the flags.
1866	*/
1867	static struct
1868	{
1869	const char pszSet; const char pszClear; uint32_t fFlag;
1870	} const s_aFlags[] =
1871	{
1872	{ "vip", NULL, X86_EFL_VIP },
1873	{ "vif", NULL, X86_EFL_VIF },
1874	{ "ac", NULL, X86_EFL_AC },
1875	{ "vm", NULL, X86_EFL_VM },
1876	{ "rf", NULL, X86_EFL_RF },
1877	{ "nt", NULL, X86_EFL_NT },
1878	{ "ov", "nv", X86_EFL_OF },
1879	{ "dn", "up", X86_EFL_DF },
1880	{ "ei", "di", X86_EFL_IF },
1881	{ "tf", NULL, X86_EFL_TF },
1882	{ "nt", "pl", X86_EFL_SF },
1883	{ "nz", "zr", X86_EFL_ZF },
1884	{ "ac", "na", X86_EFL_AF },
1885	{ "po", "pe", X86_EFL_PF },
1886	{ "cy", "nc", X86_EFL_CF },
1887	};
1888	char szEFlags[80];
1889	char *psz = szEFlags;
1890	uint32_t uEFlags = pCtx->eflags.u32;
1891	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1892	{
1893	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1894	if (pszAdd)
1895	{
1896	strcpy(psz, pszAdd);
1897	psz += strlen(pszAdd);
1898	*psz++ = ' ';
1899	}
1900	}
1901	psz[-1] = '\0';
1902
1903
1904	/*
1905	* Format the registers.
1906	*/
1907	if (CPUMIsGuestIn64BitCode(pVCpu))
1908	{
1909	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1910	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1911	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1912	"r14=%016RX64 r15=%016RX64\n"
1913	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1914	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1915	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1916	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1917	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1918	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1919	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1920	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1921	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1922	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1923	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1924	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1925	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1926	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1927	,
1928	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1929	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1930	pCtx->r14, pCtx->r15,
1931	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1932	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1933	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1934	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1935	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1936	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1937	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1938	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1939	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1940	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1941	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1942	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1943	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1944	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1945	}
1946	else
1947	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1948	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1949	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1950	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1951	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1952	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1953	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1954	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1955	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1956	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1957	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1958	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1959	,
1960	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1961	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1962	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1963	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1964	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1965	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1966	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1967	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1968	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1969	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1970	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1971	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1972
1973	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1974	Log(("FPU:\n"
1975	"FCW=%04x FSW=%04x FTW=%02x\n"
1976	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1977	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1978	,
1979	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1980	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1981	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1982	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1983
1984	Log(("MSR:\n"
1985	"EFER =%016RX64\n"
1986	"PAT =%016RX64\n"
1987	"STAR =%016RX64\n"
1988	"CSTAR =%016RX64\n"
1989	"LSTAR =%016RX64\n"
1990	"SFMASK =%016RX64\n"
1991	"KERNELGSBASE =%016RX64\n",
1992	pCtx->msrEFER,
1993	pCtx->msrPAT,
1994	pCtx->msrSTAR,
1995	pCtx->msrCSTAR,
1996	pCtx->msrLSTAR,
1997	pCtx->msrSFMASK,
1998	pCtx->msrKERNELGSBASE));
1999	}
2000
2001	#endif /* VBOX_STRICT */
2002

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 56619

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