HMR0.cpp@ 58156

Last change on this file since 58156 was 58126, checked in by vboxsync, 9 years ago
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1	/* $Id: HMR0.cpp 58126 2015-10-08 20:59:48Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/gim.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mem.h>
37	#include <iprt/memobj.h>
38	#include <iprt/once.h>
39	#include <iprt/param.h>
40	#include <iprt/power.h>
41	#include <iprt/string.h>
42	#include <iprt/thread.h>
43	#include <iprt/x86.h>
44	#include "HMVMXR0.h"
45	#include "HMSVMR0.h"
46
47
48	/*********************************************************************************************************************************
49	* Internal Functions *
50	*********************************************************************************************************************************/
51	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
56	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
57
58
59	/*********************************************************************************************************************************
60	* Structures and Typedefs *
61	*********************************************************************************************************************************/
62	/**
63	* This is used to manage the status code of a RTMpOnAll in HM.
64	*/
65	typedef struct HMR0FIRSTRC
66	{
67	/** The status code. */
68	int32_t volatile rc;
69	/** The ID of the CPU reporting the first failure. */
70	RTCPUID volatile idCpu;
71	} HMR0FIRSTRC;
72	/** Pointer to a first return code structure. */
73	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
74
75
76	/*********************************************************************************************************************************
77	* Global Variables *
78	*********************************************************************************************************************************/
79	/**
80	* Global data.
81	*/
82	static struct
83	{
84	/** Per CPU globals. */
85	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
86
87	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
88	* @{ */
89	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
90	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
91	DECLR0CALLBACKMEMBER(int, pfnSaveHostState, (PVM pVM, PVMCPU pVCpu));
92	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94	bool fEnabledByHost, void *pvArg));
95	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
96	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnSetupVM ,(PVM pVM));
99	/** @} */
100
101	/** Maximum ASID allowed. */
102	uint32_t uMaxAsid;
103
104	/** VT-x data. */
105	struct
106	{
107	/** Set to by us to indicate VMX is supported by the CPU. */
108	bool fSupported;
109	/** Whether we're using SUPR0EnableVTx or not. */
110	bool fUsingSUPR0EnableVTx;
111	/** Whether we're using the preemption timer or not. */
112	bool fUsePreemptTimer;
113	/** The shift mask employed by the VMX-Preemption timer. */
114	uint8_t cPreemptTimerShift;
115
116	/** Host CR4 value (set by ring-0 VMX init) */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** VMX MSR values */
123	VMXMSRS Msrs;
124
125	/** Last instruction error. */
126	uint32_t ulLastInstrError;
127
128	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
129	* module termination. */
130	bool fCalledSUPR0EnableVTx;
131	} vmx;
132
133	/** AMD-V information. */
134	struct
135	{
136	/* HWCR MSR (for diagnostics) */
137	uint64_t u64MsrHwcr;
138
139	/** SVM revision. */
140	uint32_t u32Rev;
141
142	/** SVM feature bits from cpuid 0x8000000a */
143	uint32_t u32Features;
144
145	/** Set by us to indicate SVM is supported by the CPU. */
146	bool fSupported;
147	} svm;
148	/** Saved error from detection */
149	int32_t lLastError;
150
151	/** CPUID 0x80000001 ecx:edx features */
152	struct
153	{
154	uint32_t u32AMDFeatureECX;
155	uint32_t u32AMDFeatureEDX;
156	} cpuid;
157
158	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
159	* enabled and disabled each time it's used to execute guest code. */
160	bool fGlobalInit;
161	/** Indicates whether the host is suspending or not. We'll refuse a few
162	* actions when the host is being suspended to speed up the suspending and
163	* avoid trouble. */
164	volatile bool fSuspended;
165
166	/** Whether we've already initialized all CPUs.
167	* @remarks We could check the EnableAllCpusOnce state, but this is
168	* simpler and hopefully easier to understand. */
169	bool fEnabled;
170	/** Serialize initialization in HMR0EnableAllCpus. */
171	RTONCE EnableAllCpusOnce;
172	} g_HmR0;
173
174
175
176	/**
177	* Initializes a first return code structure.
178	*
179	* @param pFirstRc The structure to init.
180	*/
181	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
182	{
183	pFirstRc->rc = VINF_SUCCESS;
184	pFirstRc->idCpu = NIL_RTCPUID;
185	}
186
187
188	/**
189	* Try set the status code (success ignored).
190	*
191	* @param pFirstRc The first return code structure.
192	* @param rc The status code.
193	*/
194	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
195	{
196	if ( RT_FAILURE(rc)
197	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
198	pFirstRc->idCpu = RTMpCpuId();
199	}
200
201
202	/**
203	* Get the status code of a first return code structure.
204	*
205	* @returns The status code; VINF_SUCCESS or error status, no informational or
206	* warning errors.
207	* @param pFirstRc The first return code structure.
208	*/
209	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
210	{
211	return pFirstRc->rc;
212	}
213
214
215	#ifdef VBOX_STRICT
216	/**
217	* Get the CPU ID on which the failure status code was reported.
218	*
219	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
220	* @param pFirstRc The first return code structure.
221	*/
222	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
223	{
224	return pFirstRc->idCpu;
225	}
226	#endif /* VBOX_STRICT */
227
228
229	/** @name Dummy callback handlers.
230	* @{ */
231
232	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
233	{
234	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
235	return VINF_SUCCESS;
236	}
237
238	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
239	{
240	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
241	}
242
243	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
244	bool fEnabledBySystem, void *pvArg)
245	{
246	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
247	return VINF_SUCCESS;
248	}
249
250	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
251	{
252	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
253	return VINF_SUCCESS;
254	}
255
256	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
257	{
258	NOREF(pVM);
259	return VINF_SUCCESS;
260	}
261
262	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
263	{
264	NOREF(pVM);
265	return VINF_SUCCESS;
266	}
267
268	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
269	{
270	NOREF(pVM);
271	return VINF_SUCCESS;
272	}
273
274	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
275	{
276	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
277	return VINF_SUCCESS;
278	}
279
280	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
281	{
282	NOREF(pVM); NOREF(pVCpu);
283	return VINF_SUCCESS;
284	}
285
286	/** @} */
287
288
289	/**
290	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
291	* Down at the Rate Specified" erratum.
292	*
293	* Errata names and related steppings:
294	* - BA86 - D0.
295	* - AAX65 - C2.
296	* - AAU65 - C2, K0.
297	* - AAO95 - B1.
298	* - AAT59 - C2.
299	* - AAK139 - D0.
300	* - AAM126 - C0, C1, D0.
301	* - AAN92 - B1.
302	* - AAJ124 - C0, D0.
303	*
304	* - AAP86 - B1.
305	*
306	* Steppings: B1, C0, C1, C2, D0, K0.
307	*
308	* @returns true if subject to it, false if not.
309	*/
310	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
311	{
312	uint32_t u = ASMCpuId_EAX(1);
313	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
314	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
315	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
316	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
317	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
318	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
319	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
320	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
321	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
322	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
323	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
324	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
325	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
326	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
327	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
328	)
329	return true;
330	return false;
331	}
332
333
334	/**
335	* Intel specific initialization code.
336	*
337	* @returns VBox status code (will only fail if out of memory).
338	*/
339	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
340	{
341	/*
342	* Check that all the required VT-x features are present.
343	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
344	*/
345	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
346	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
347	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
348	)
349	{
350	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
351	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
352
353	/*
354	* First try use native kernel API for controlling VT-x.
355	* (This is only supported by some Mac OS X kernels atm.)
356	*/
357	int rc = g_HmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
358	g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
359	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
360	{
361	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
362	if (RT_SUCCESS(rc))
363	{
364	g_HmR0.vmx.fSupported = true;
365	rc = SUPR0EnableVTx(false /* fEnable */);
366	AssertLogRelRC(rc);
367	}
368	}
369	else
370	{
371	HMR0FIRSTRC FirstRc;
372	hmR0FirstRcInit(&FirstRc);
373	g_HmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
374	if (RT_SUCCESS(g_HmR0.lLastError))
375	g_HmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
376	}
377	if (RT_SUCCESS(g_HmR0.lLastError))
378	{
379	/* Reread in case it was changed by SUPR0GetVmxUsability(). */
380	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
381
382	/*
383	* Read all relevant registers and MSRs.
384	*/
385	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
386	g_HmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
387	g_HmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
388	g_HmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
389	g_HmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
390	g_HmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
391	g_HmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
392	g_HmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
393	g_HmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
394	g_HmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
395	g_HmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
396	g_HmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
397	g_HmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
398	/* VPID 16 bits ASID. */
399	g_HmR0.uMaxAsid = 0x10000; /* exclusive */
400
401	if (g_HmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
402	{
403	g_HmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
404	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
405	g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
406
407	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
408	g_HmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
409	}
410
411	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
412	{
413	/*
414	* Enter root mode
415	*/
416	RTR0MEMOBJ hScatchMemObj;
417	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
418	if (RT_FAILURE(rc))
419	{
420	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
421	return rc;
422	}
423
424	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
425	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
426	ASMMemZeroPage(pvScatchPage);
427
428	/* Set revision dword at the beginning of the structure. */
429	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HmR0.vmx.Msrs.u64BasicInfo);
430
431	/* Make sure we don't get rescheduled to another cpu during this probe. */
432	RTCCUINTREG fFlags = ASMIntDisableFlags();
433
434	/*
435	* Check CR4.VMXE
436	*/
437	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
438	if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
439	{
440	/* In theory this bit could be cleared behind our back. Which would cause
441	#UD faults when we try to execute the VMX instructions... */
442	ASMSetCR4(g_HmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
443	}
444
445	/*
446	* The only way of checking if we're in VMX root mode or not is to try and enter it.
447	* There is no instruction or control bit that tells us if we're in VMX root mode.
448	* Therefore, try and enter VMX root mode here.
449	*/
450	rc = VMXEnable(HCPhysScratchPage);
451	if (RT_SUCCESS(rc))
452	{
453	g_HmR0.vmx.fSupported = true;
454	VMXDisable();
455	}
456	else
457	{
458	/*
459	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
460	* it will crash the host when we enter raw mode, because:
461	*
462	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
463	* this bit), and
464	* (b) turning off paging causes a #GP (unavoidable when switching
465	* from long to 32 bits mode or 32 bits to PAE).
466	*
467	* They should fix their code, but until they do we simply refuse to run.
468	*/
469	g_HmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
470	Assert(g_HmR0.vmx.fSupported == false);
471	}
472
473	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
474	if it wasn't so before (some software could incorrectly
475	think it's in VMX mode). */
476	ASMSetCR4(g_HmR0.vmx.u64HostCr4);
477	ASMSetFlags(fFlags);
478
479	RTR0MemObjFree(hScatchMemObj, false);
480	}
481
482	if (g_HmR0.vmx.fSupported)
483	{
484	rc = VMXR0GlobalInit();
485	if (RT_FAILURE(rc))
486	g_HmR0.lLastError = rc;
487
488	/*
489	* Install the VT-x methods.
490	*/
491	g_HmR0.pfnEnterSession = VMXR0Enter;
492	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
493	g_HmR0.pfnSaveHostState = VMXR0SaveHostState;
494	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
495	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
496	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
497	g_HmR0.pfnInitVM = VMXR0InitVM;
498	g_HmR0.pfnTermVM = VMXR0TermVM;
499	g_HmR0.pfnSetupVM = VMXR0SetupVM;
500
501	/*
502	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
503	* Timer Does Not Count Down at the Rate Specified" erratum.
504	*/
505	if (g_HmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
506	{
507	g_HmR0.vmx.fUsePreemptTimer = true;
508	g_HmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HmR0.vmx.Msrs.u64Misc);
509	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
510	g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
511	}
512	}
513	}
514	#ifdef LOG_ENABLED
515	else
516	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HmR0.lLastError);
517	#endif
518	}
519	else
520	g_HmR0.lLastError = VERR_VMX_NO_VMX;
521	return VINF_SUCCESS;
522	}
523
524
525	/**
526	* AMD-specific initialization code.
527	*
528	* @returns VBox status code.
529	*/
530	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
531	{
532	/*
533	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
534	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
535	*/
536	int rc;
537	if ( (g_HmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
538	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
539	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
540	&& ASMIsValidExtRange(uMaxExtLeaf)
541	&& uMaxExtLeaf >= 0x8000000a
542	)
543	{
544	/* Call the global AMD-V initialization routine. */
545	rc = SVMR0GlobalInit();
546	if (RT_FAILURE(rc))
547	{
548	g_HmR0.lLastError = rc;
549	return rc;
550	}
551
552	/*
553	* Install the AMD-V methods.
554	*/
555	g_HmR0.pfnEnterSession = SVMR0Enter;
556	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
557	g_HmR0.pfnSaveHostState = SVMR0SaveHostState;
558	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
559	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
560	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
561	g_HmR0.pfnInitVM = SVMR0InitVM;
562	g_HmR0.pfnTermVM = SVMR0TermVM;
563	g_HmR0.pfnSetupVM = SVMR0SetupVM;
564
565	/* Query AMD features. */
566	uint32_t u32Dummy;
567	ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
568
569	/*
570	* We need to check if AMD-V has been properly initialized on all CPUs.
571	* Some BIOSes might do a poor job.
572	*/
573	HMR0FIRSTRC FirstRc;
574	hmR0FirstRcInit(&FirstRc);
575	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
576	AssertRC(rc);
577	if (RT_SUCCESS(rc))
578	rc = hmR0FirstRcGetStatus(&FirstRc);
579	#ifndef DEBUG_bird
580	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
581	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
582	#endif
583	if (RT_SUCCESS(rc))
584	{
585	/* Read the HWCR MSR for diagnostics. */
586	g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
587	g_HmR0.svm.fSupported = true;
588	}
589	else
590	{
591	g_HmR0.lLastError = rc;
592	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
593	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
594	}
595	}
596	else
597	{
598	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
599	g_HmR0.lLastError = VERR_SVM_NO_SVM;
600	}
601	return rc;
602	}
603
604
605	/**
606	* Does global Ring-0 HM initialization (at module init).
607	*
608	* @returns VBox status code.
609	*/
610	VMMR0_INT_DECL(int) HMR0Init(void)
611	{
612	/*
613	* Initialize the globals.
614	*/
615	g_HmR0.fEnabled = false;
616	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
617	g_HmR0.EnableAllCpusOnce = s_OnceInit;
618	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
619	{
620	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
621	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
622	}
623
624	/* Fill in all callbacks with placeholders. */
625	g_HmR0.pfnEnterSession = hmR0DummyEnter;
626	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
627	g_HmR0.pfnSaveHostState = hmR0DummySaveHostState;
628	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
629	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
630	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
631	g_HmR0.pfnInitVM = hmR0DummyInitVM;
632	g_HmR0.pfnTermVM = hmR0DummyTermVM;
633	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
634
635	/* Default is global VT-x/AMD-V init. */
636	g_HmR0.fGlobalInit = true;
637
638	/*
639	* Make sure aCpuInfo is big enough for all the CPUs on this system.
640	*/
641	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
642	{
643	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
644	return VERR_TOO_MANY_CPUS;
645	}
646
647	/*
648	* Check for VT-x and AMD-V capabilities.
649	*/
650	int rc;
651	if (ASMHasCpuId())
652	{
653	/* Standard features. */
654	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
655	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
656	if (ASMIsValidStdRange(uMaxLeaf))
657	{
658	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
659	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
660
661	/* Query AMD features. */
662	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
663	if (ASMIsValidExtRange(uMaxExtLeaf))
664	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
665	&g_HmR0.cpuid.u32AMDFeatureECX,
666	&g_HmR0.cpuid.u32AMDFeatureEDX);
667	else
668	g_HmR0.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureEDX = 0;
669
670	/* Go to CPU specific initialization code. */
671	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
672	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
673	{
674	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
675	if (RT_FAILURE(rc))
676	return rc;
677	}
678	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
679	{
680	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
681	if (RT_FAILURE(rc))
682	return rc;
683	}
684	else
685	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
686	}
687	else
688	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
689	}
690	else
691	g_HmR0.lLastError = VERR_HM_NO_CPUID;
692
693	/*
694	* Register notification callbacks that we can use to disable/enable CPUs
695	* when brought offline/online or suspending/resuming.
696	*/
697	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
698	{
699	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
700	AssertRC(rc);
701
702	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
703	AssertRC(rc);
704	}
705
706	/* We return success here because module init shall not fail if HM
707	fails to initialize. */
708	return VINF_SUCCESS;
709	}
710
711
712	/**
713	* Does global Ring-0 HM termination (at module termination).
714	*
715	* @returns VBox status code.
716	*/
717	VMMR0_INT_DECL(int) HMR0Term(void)
718	{
719	int rc;
720	if ( g_HmR0.vmx.fSupported
721	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
722	{
723	/*
724	* Simple if the host OS manages VT-x.
725	*/
726	Assert(g_HmR0.fGlobalInit);
727
728	if (g_HmR0.vmx.fCalledSUPR0EnableVTx)
729	{
730	rc = SUPR0EnableVTx(false /* fEnable */);
731	g_HmR0.vmx.fCalledSUPR0EnableVTx = false;
732	}
733	else
734	rc = VINF_SUCCESS;
735
736	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
737	{
738	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
739	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
740	}
741	}
742	else
743	{
744	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
745
746	/* Doesn't really matter if this fails. */
747	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
748	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
749
750	/*
751	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
752	*/
753	if (g_HmR0.fGlobalInit)
754	{
755	HMR0FIRSTRC FirstRc;
756	hmR0FirstRcInit(&FirstRc);
757	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
758	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
759	if (RT_SUCCESS(rc))
760	rc = hmR0FirstRcGetStatus(&FirstRc);
761	}
762
763	/*
764	* Free the per-cpu pages used for VT-x and AMD-V.
765	*/
766	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
767	{
768	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
769	{
770	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
771	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
772	}
773	}
774	}
775
776	/** @todo This needs cleaning up. There's no matching
777	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
778	* should move into their respective modules. */
779	/* Finally, call global VT-x/AMD-V termination. */
780	if (g_HmR0.vmx.fSupported)
781	VMXR0GlobalTerm();
782	else if (g_HmR0.svm.fSupported)
783	SVMR0GlobalTerm();
784
785	return rc;
786	}
787
788
789	/**
790	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
791	* on a CPU.
792	*
793	* @param idCpu The identifier for the CPU the function is called on.
794	* @param pvUser1 Pointer to the first RC structure.
795	* @param pvUser2 Ignored.
796	*/
797	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
798	{
799	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
800	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
801	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
802	NOREF(idCpu); NOREF(pvUser2);
803
804	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
805	hmR0FirstRcSetStatus(pFirstRc, rc);
806	}
807
808
809	/**
810	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
811	* on a CPU.
812	*
813	* @param idCpu The identifier for the CPU the function is called on.
814	* @param pvUser1 Pointer to the first RC structure.
815	* @param pvUser2 Ignored.
816	*/
817	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
818	{
819	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
820	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
821	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
822	NOREF(idCpu); NOREF(pvUser2);
823
824	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
825	hmR0FirstRcSetStatus(pFirstRc, rc);
826	}
827
828
829	/**
830	* Enable VT-x or AMD-V on the current CPU
831	*
832	* @returns VBox status code.
833	* @param pVM The cross context VM structure. Can be NULL.
834	* @param idCpu The identifier for the CPU the function is called on.
835	*
836	* @remarks Maybe called with interrupts disabled!
837	*/
838	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
839	{
840	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
841
842	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
843	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
844	Assert(!pCpu->fConfigured);
845	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
846
847	pCpu->idCpu = idCpu;
848	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
849
850	int rc;
851	if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
852	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
853	else
854	{
855	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
856	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
857	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0 /* iPage */);
858
859	if (g_HmR0.vmx.fSupported)
860	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HmR0.vmx.Msrs);
861	else
862	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
863	}
864	if (RT_SUCCESS(rc))
865	pCpu->fConfigured = true;
866
867	return rc;
868	}
869
870
871	/**
872	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
873	*
874	* @param idCpu The identifier for the CPU the function is called on.
875	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
876	* @param pvUser2 The 2nd user argument.
877	*/
878	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
879	{
880	PVM pVM = (PVM)pvUser1; /* can be NULL! */
881	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
882	AssertReturnVoid(g_HmR0.fGlobalInit);
883	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
884	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
885	}
886
887
888	/**
889	* RTOnce callback employed by HMR0EnableAllCpus.
890	*
891	* @returns VBox status code.
892	* @param pvUser Pointer to the VM.
893	*/
894	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
895	{
896	PVM pVM = (PVM)pvUser;
897
898	/*
899	* Indicate that we've initialized.
900	*
901	* Note! There is a potential race between this function and the suspend
902	* notification. Kind of unlikely though, so ignored for now.
903	*/
904	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
905	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
906
907	/*
908	* The global init variable is set by the first VM.
909	*/
910	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
911
912	#ifdef VBOX_STRICT
913	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
914	{
915	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
916	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
917	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
918	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
919	}
920	#endif
921
922	int rc;
923	if ( g_HmR0.vmx.fSupported
924	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
925	{
926	/*
927	* Global VT-x initialization API (only darwin for now).
928	*/
929	rc = SUPR0EnableVTx(true /* fEnable */);
930	if (RT_SUCCESS(rc))
931	{
932	g_HmR0.vmx.fCalledSUPR0EnableVTx = true;
933	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
934	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
935	}
936	else
937	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
938	}
939	else
940	{
941	/*
942	* We're doing the job ourselves.
943	*/
944	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
945	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
946	{
947	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
948
949	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
950	{
951	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
952	AssertLogRelRCReturn(rc, rc);
953
954	void *pvR0 = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
955	ASMMemZeroPage(pvR0);
956	}
957	}
958
959	rc = VINF_SUCCESS;
960	}
961
962	if ( RT_SUCCESS(rc)
963	&& g_HmR0.fGlobalInit)
964	{
965	/* First time, so initialize each cpu/core. */
966	HMR0FIRSTRC FirstRc;
967	hmR0FirstRcInit(&FirstRc);
968	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
969	if (RT_SUCCESS(rc))
970	rc = hmR0FirstRcGetStatus(&FirstRc);
971	}
972
973	return rc;
974	}
975
976
977	/**
978	* Sets up HM on all cpus.
979	*
980	* @returns VBox status code.
981	* @param pVM The cross context VM structure.
982	*/
983	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
984	{
985	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
986	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
987	return VERR_HM_SUSPEND_PENDING;
988
989	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
990	}
991
992
993	/**
994	* Disable VT-x or AMD-V on the current CPU.
995	*
996	* @returns VBox status code.
997	* @param idCpu The identifier for the CPU this function is called on.
998	*
999	* @remarks Must be called with preemption disabled.
1000	*/
1001	static int hmR0DisableCpu(RTCPUID idCpu)
1002	{
1003	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1004
1005	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1006	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1007	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1008	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1009	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1010	AssertRelease(idCpu == RTMpCpuId());
1011
1012	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1013	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1014
1015	int rc;
1016	if (pCpu->fConfigured)
1017	{
1018	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1019	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1020
1021	rc = g_HmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1022	AssertRCReturn(rc, rc);
1023
1024	pCpu->fConfigured = false;
1025	pCpu->idCpu = NIL_RTCPUID;
1026	}
1027	else
1028	rc = VINF_SUCCESS; /* nothing to do */
1029	return rc;
1030	}
1031
1032
1033	/**
1034	* Worker function passed to RTMpOnAll() that is to be called on the target
1035	* CPUs.
1036	*
1037	* @param idCpu The identifier for the CPU the function is called on.
1038	* @param pvUser1 The 1st user argument.
1039	* @param pvUser2 Opaque pointer to the FirstRc.
1040	*/
1041	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1042	{
1043	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1044	AssertReturnVoid(g_HmR0.fGlobalInit);
1045	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1046	}
1047
1048
1049	/**
1050	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1051	* CPU.
1052	*
1053	* @param idCpu The identifier for the CPU the function is called on.
1054	* @param pvUser1 Null, not used.
1055	* @param pvUser2 Null, not used.
1056	*/
1057	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1058	{
1059	NOREF(pvUser1);
1060	NOREF(pvUser2);
1061	hmR0DisableCpu(idCpu);
1062	}
1063
1064
1065	/**
1066	* Callback function invoked when a cpu goes online or offline.
1067	*
1068	* @param enmEvent The Mp event.
1069	* @param idCpu The identifier for the CPU the function is called on.
1070	* @param pvData Opaque data (PVM pointer).
1071	*/
1072	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1073	{
1074	NOREF(pvData);
1075	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1076
1077	/*
1078	* We only care about uninitializing a CPU that is going offline. When a
1079	* CPU comes online, the initialization is done lazily in HMR0Enter().
1080	*/
1081	switch (enmEvent)
1082	{
1083	case RTMPEVENT_OFFLINE:
1084	{
1085	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1086	RTThreadPreemptDisable(&PreemptState);
1087	if (idCpu == RTMpCpuId())
1088	{
1089	int rc = hmR0DisableCpu(idCpu);
1090	AssertRC(rc);
1091	RTThreadPreemptRestore(&PreemptState);
1092	}
1093	else
1094	{
1095	RTThreadPreemptRestore(&PreemptState);
1096	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1097	}
1098	break;
1099	}
1100
1101	default:
1102	break;
1103	}
1104	}
1105
1106
1107	/**
1108	* Called whenever a system power state change occurs.
1109	*
1110	* @param enmEvent The Power event.
1111	* @param pvUser User argument.
1112	*/
1113	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1114	{
1115	NOREF(pvUser);
1116	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1117
1118	#ifdef LOG_ENABLED
1119	if (enmEvent == RTPOWEREVENT_SUSPEND)
1120	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1121	else
1122	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1123	#endif
1124
1125	if (enmEvent == RTPOWEREVENT_SUSPEND)
1126	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1127
1128	if (g_HmR0.fEnabled)
1129	{
1130	int rc;
1131	HMR0FIRSTRC FirstRc;
1132	hmR0FirstRcInit(&FirstRc);
1133
1134	if (enmEvent == RTPOWEREVENT_SUSPEND)
1135	{
1136	if (g_HmR0.fGlobalInit)
1137	{
1138	/* Turn off VT-x or AMD-V on all CPUs. */
1139	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1140	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1141	}
1142	/* else nothing to do here for the local init case */
1143	}
1144	else
1145	{
1146	/* Reinit the CPUs from scratch as the suspend state might have
1147	messed with the MSRs. (lousy BIOSes as usual) */
1148	if (g_HmR0.vmx.fSupported)
1149	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1150	else
1151	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1152	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1153	if (RT_SUCCESS(rc))
1154	rc = hmR0FirstRcGetStatus(&FirstRc);
1155	#ifdef LOG_ENABLED
1156	if (RT_FAILURE(rc))
1157	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1158	#endif
1159	if (g_HmR0.fGlobalInit)
1160	{
1161	/* Turn VT-x or AMD-V back on on all CPUs. */
1162	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1163	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1164	}
1165	/* else nothing to do here for the local init case */
1166	}
1167	}
1168
1169	if (enmEvent == RTPOWEREVENT_RESUME)
1170	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1171	}
1172
1173
1174	/**
1175	* Does ring-0 per-VM HM initialization.
1176	*
1177	* This will copy HM global into the VM structure and call the CPU specific
1178	* init routine which will allocate resources for each virtual CPU and such.
1179	*
1180	* @returns VBox status code.
1181	* @param pVM The cross context VM structure.
1182	*
1183	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1184	* vmR3InitRing3().
1185	*/
1186	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1187	{
1188	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1189
1190	#ifdef LOG_ENABLED
1191	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1192	#endif
1193
1194	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1195	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1196	return VERR_HM_SUSPEND_PENDING;
1197
1198	/*
1199	* Copy globals to the VM structure.
1200	*/
1201	pVM->hm.s.vmx.fSupported = g_HmR0.vmx.fSupported;
1202	pVM->hm.s.svm.fSupported = g_HmR0.svm.fSupported;
1203
1204	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1205	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.vmx.cPreemptTimerShift;
1206	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.vmx.u64HostCr4;
1207	pVM->hm.s.vmx.u64HostEfer = g_HmR0.vmx.u64HostEfer;
1208	pVM->hm.s.vmx.Msrs = g_HmR0.vmx.Msrs;
1209	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.svm.u64MsrHwcr;
1210	pVM->hm.s.svm.u32Rev = g_HmR0.svm.u32Rev;
1211	pVM->hm.s.svm.u32Features = g_HmR0.svm.u32Features;
1212	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureECX;
1213	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HmR0.cpuid.u32AMDFeatureEDX;
1214	pVM->hm.s.lLastError = g_HmR0.lLastError;
1215	pVM->hm.s.uMaxAsid = g_HmR0.uMaxAsid;
1216
1217	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1218	{
1219	pVM->hm.s.cMaxResumeLoops = 1024;
1220	if (RTThreadPreemptIsPendingTrusty())
1221	pVM->hm.s.cMaxResumeLoops = 8192;
1222	}
1223
1224	/*
1225	* Initialize some per-VCPU fields.
1226	*/
1227	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1228	{
1229	PVMCPU pVCpu = &pVM->aCpus[i];
1230	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1231	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1232	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1233
1234	/* We'll aways increment this the first time (host uses ASID 0). */
1235	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1236	}
1237
1238	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1239
1240	/*
1241	* Call the hardware specific initialization method.
1242	*/
1243	return g_HmR0.pfnInitVM(pVM);
1244	}
1245
1246
1247	/**
1248	* Does ring-0 per VM HM termination.
1249	*
1250	* @returns VBox status code.
1251	* @param pVM The cross context VM structure.
1252	*/
1253	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1254	{
1255	Log(("HMR0TermVM: %p\n", pVM));
1256	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1257
1258	/*
1259	* Call the hardware specific method.
1260	*
1261	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1262	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1263	*/
1264	return g_HmR0.pfnTermVM(pVM);
1265	}
1266
1267
1268	/**
1269	* Sets up a VT-x or AMD-V session.
1270	*
1271	* This is mostly about setting up the hardware VM state.
1272	*
1273	* @returns VBox status code.
1274	* @param pVM The cross context VM structure.
1275	*/
1276	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1277	{
1278	Log(("HMR0SetupVM: %p\n", pVM));
1279	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1280
1281	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1282	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1283
1284	/* On first entry we'll sync everything. */
1285	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1286	HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1287
1288	/*
1289	* Call the hardware specific setup VM method. This requires the CPU to be
1290	* enabled for AMD-V/VT-x and preemption to be prevented.
1291	*/
1292	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1293	RTThreadPreemptDisable(&PreemptState);
1294	RTCPUID idCpu = RTMpCpuId();
1295
1296	/* Enable VT-x or AMD-V if local init is required. */
1297	int rc;
1298	if (!g_HmR0.fGlobalInit)
1299	{
1300	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1301	rc = hmR0EnableCpu(pVM, idCpu);
1302	if (RT_FAILURE(rc))
1303	{
1304	RTThreadPreemptRestore(&PreemptState);
1305	return rc;
1306	}
1307	}
1308
1309	/* Setup VT-x or AMD-V. */
1310	rc = g_HmR0.pfnSetupVM(pVM);
1311
1312	/* Disable VT-x or AMD-V if local init was done before. */
1313	if (!g_HmR0.fGlobalInit)
1314	{
1315	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1316	int rc2 = hmR0DisableCpu(idCpu);
1317	AssertRC(rc2);
1318	}
1319
1320	RTThreadPreemptRestore(&PreemptState);
1321	return rc;
1322	}
1323
1324
1325	/**
1326	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1327	* required for entering HM context.
1328	*
1329	* @returns VBox status code.
1330	* @param pVCpu The cross context virtual CPU structure.
1331	*
1332	* @remarks No-long-jump zone!!!
1333	*/
1334	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1335	{
1336	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1337
1338	int rc = VINF_SUCCESS;
1339	RTCPUID idCpu = RTMpCpuId();
1340	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1341	AssertPtr(pCpu);
1342
1343	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1344	if (!pCpu->fConfigured)
1345	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1346
1347	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1348	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1349
1350	Assert(pCpu->idCpu == idCpu && pCpu->idCpu != NIL_RTCPUID);
1351	pVCpu->hm.s.idEnteredCpu = idCpu;
1352	return rc;
1353	}
1354
1355
1356	/**
1357	* Enters the VT-x or AMD-V session.
1358	*
1359	* @returns VBox status code.
1360	* @param pVM The cross context VM structure.
1361	* @param pVCpu The cross context virtual CPU structure.
1362	*
1363	* @remarks This is called with preemption disabled.
1364	*/
1365	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1366	{
1367	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1368	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1369	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1370
1371	/* Load the bare minimum state required for entering HM. */
1372	int rc = HMR0EnterCpu(pVCpu);
1373	AssertRCReturn(rc, rc);
1374
1375	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1376	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1377	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1378	#endif
1379
1380	RTCPUID idCpu = RTMpCpuId();
1381	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1382	Assert(pCpu);
1383	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1384
1385	rc = g_HmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1386	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1387
1388	/* Load the host-state as we may be resuming code after a longjmp and quite
1389	possibly now be scheduled on a different CPU. */
1390	rc = g_HmR0.pfnSaveHostState(pVM, pVCpu);
1391	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1392
1393	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1394	if (fStartedSet)
1395	PGMRZDynMapReleaseAutoSet(pVCpu);
1396	#endif
1397
1398	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1399	if (RT_FAILURE(rc))
1400	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1401	return rc;
1402	}
1403
1404
1405	/**
1406	* Deinitializes the bare minimum state used for HM context and if necessary
1407	* disable HM on the CPU.
1408	*
1409	* @returns VBox status code.
1410	* @param pVCpu The cross context virtual CPU structure.
1411	*
1412	* @remarks No-long-jump zone!!!
1413	*/
1414	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1415	{
1416	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1417	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1418
1419	RTCPUID idCpu = RTMpCpuId();
1420	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1421
1422	if ( !g_HmR0.fGlobalInit
1423	&& pCpu->fConfigured)
1424	{
1425	int rc = hmR0DisableCpu(idCpu);
1426	AssertRCReturn(rc, rc);
1427	Assert(!pCpu->fConfigured);
1428	Assert(pCpu->idCpu == NIL_RTCPUID);
1429
1430	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1431	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1432	}
1433
1434	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1435	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1436
1437	return VINF_SUCCESS;
1438	}
1439
1440
1441	/**
1442	* Thread-context hook for HM.
1443	*
1444	* @param enmEvent The thread-context event.
1445	* @param pvUser Opaque pointer to the VMCPU.
1446	*/
1447	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1448	{
1449	PVMCPU pVCpu = (PVMCPU)pvUser;
1450	Assert(pVCpu);
1451	Assert(g_HmR0.pfnThreadCtxCallback);
1452
1453	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1454	}
1455
1456
1457	/**
1458	* Runs guest code in a hardware accelerated VM.
1459	*
1460	* @returns VBox status code.
1461	* @param pVM The cross context VM structure.
1462	* @param pVCpu The cross context virtual CPU structure.
1463	*
1464	* @remarks Can be called with preemption enabled if thread-context hooks are
1465	* used!!!
1466	*/
1467	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1468	{
1469	#ifdef VBOX_STRICT
1470	/* With thread-context hooks we would be running this code with preemption enabled. */
1471	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1472	{
1473	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1474	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1475	Assert(pCpu->fConfigured);
1476	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1477	}
1478	#endif
1479
1480	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1481	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1482	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1483	PGMRZDynMapStartAutoSet(pVCpu);
1484	#endif
1485
1486	int rc = g_HmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1487
1488	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1489	PGMRZDynMapReleaseAutoSet(pVCpu);
1490	#endif
1491	return rc;
1492	}
1493
1494	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1495
1496	/**
1497	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1498	*
1499	* @returns VBox status code.
1500	* @param pVM The cross context VM structure.
1501	* @param pVCpu The cross context virtual CPU structure.
1502	* @param pCtx Pointer to the guest CPU context.
1503	*/
1504	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1505	{
1506	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1507	if (pVM->hm.s.vmx.fSupported)
1508	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1509	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1510	}
1511
1512
1513	/**
1514	* Save guest debug state (64 bits guest mode & 32 bits host only)
1515	*
1516	* @returns VBox status code.
1517	* @param pVM The cross context VM structure.
1518	* @param pVCpu The cross context virtual CPU structure.
1519	* @param pCtx Pointer to the guest CPU context.
1520	*/
1521	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1522	{
1523	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1524	if (pVM->hm.s.vmx.fSupported)
1525	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1526	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1527	}
1528
1529
1530	/**
1531	* Test the 32->64 bits switcher.
1532	*
1533	* @returns VBox status code.
1534	* @param pVM The cross context VM structure.
1535	*/
1536	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1537	{
1538	PVMCPU pVCpu = &pVM->aCpus[0];
1539	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1540	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1541	int rc;
1542
1543	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1544	if (pVM->hm.s.vmx.fSupported)
1545	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1546	else
1547	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1548	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1549
1550	return rc;
1551	}
1552
1553	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
1554
1555	/**
1556	* Returns suspend status of the host.
1557	*
1558	* @returns Suspend pending or not.
1559	*/
1560	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1561	{
1562	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1563	}
1564
1565
1566	/**
1567	* Returns the cpu structure for the current cpu.
1568	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1569	*
1570	* @returns The cpu structure pointer.
1571	*/
1572	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1573	{
1574	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1575	RTCPUID idCpu = RTMpCpuId();
1576	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1577	return &g_HmR0.aCpuInfo[idCpu];
1578	}
1579
1580
1581	/**
1582	* Returns the cpu structure for the current cpu.
1583	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1584	*
1585	* @returns The cpu structure pointer.
1586	* @param idCpu id of the VCPU.
1587	*/
1588	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1589	{
1590	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1591	return &g_HmR0.aCpuInfo[idCpu];
1592	}
1593
1594
1595	/**
1596	* Save a pending IO read.
1597	*
1598	* @param pVCpu The cross context virtual CPU structure.
1599	* @param GCPtrRip Address of IO instruction.
1600	* @param GCPtrRipNext Address of the next instruction.
1601	* @param uPort Port address.
1602	* @param uAndVal AND mask for saving the result in eax.
1603	* @param cbSize Read size.
1604	*/
1605	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1606	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1607	{
1608	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1609	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1610	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1611	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1612	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1613	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1614	return;
1615	}
1616
1617
1618	/**
1619	* Save a pending IO write.
1620	*
1621	* @param pVCpu The cross context virtual CPU structure.
1622	* @param GCPtrRip Address of IO instruction.
1623	* @param GCPtrRipNext Address of the next instruction.
1624	* @param uPort Port address.
1625	* @param uAndVal AND mask for fetching the result from eax.
1626	* @param cbSize Read size.
1627	*/
1628	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1629	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1630	{
1631	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1632	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1633	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1634	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1635	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1636	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1637	return;
1638	}
1639
1640	#ifdef VBOX_WITH_RAW_MODE
1641
1642	/**
1643	* Raw-mode switcher hook - disable VT-x if it's active and the current
1644	* switcher turns off paging.
1645	*
1646	* @returns VBox status code.
1647	* @param pVM The cross context VM structure.
1648	* @param enmSwitcher The switcher we're about to use.
1649	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1650	*/
1651	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1652	{
1653	NOREF(pVM);
1654
1655	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1656
1657	*pfVTxDisabled = false;
1658
1659	/* No such issues with AMD-V */
1660	if (!g_HmR0.vmx.fSupported)
1661	return VINF_SUCCESS;
1662
1663	/* Check if the switching we're up to is safe. */
1664	switch (enmSwitcher)
1665	{
1666	case VMMSWITCHER_32_TO_32:
1667	case VMMSWITCHER_PAE_TO_PAE:
1668	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1669
1670	case VMMSWITCHER_32_TO_PAE:
1671	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1672	case VMMSWITCHER_AMD64_TO_32:
1673	case VMMSWITCHER_AMD64_TO_PAE:
1674	break; /* unsafe switchers */
1675
1676	default:
1677	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1678	}
1679
1680	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1681	regardless of whether we're currently using VT-x or not. */
1682	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1683	{
1684	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1685	return VINF_SUCCESS;
1686	}
1687
1688	/** @todo Check if this code is presumptive wrt other VT-x users on the
1689	* system... */
1690
1691	/* Nothing to do if we haven't enabled VT-x. */
1692	if (!g_HmR0.fEnabled)
1693	return VINF_SUCCESS;
1694
1695	/* Local init implies the CPU is currently not in VMX root mode. */
1696	if (!g_HmR0.fGlobalInit)
1697	return VINF_SUCCESS;
1698
1699	/* Ok, disable VT-x. */
1700	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1701	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1702
1703	*pfVTxDisabled = true;
1704	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1705	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1706	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1707	}
1708
1709
1710	/**
1711	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1712	* switcher turned off paging.
1713	*
1714	* @param pVM The cross context VM structure.
1715	* @param fVTxDisabled Whether VT-x was disabled or not.
1716	*/
1717	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1718	{
1719	Assert(!ASMIntAreEnabled());
1720
1721	if (!fVTxDisabled)
1722	return; /* nothing to do */
1723
1724	Assert(g_HmR0.vmx.fSupported);
1725	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1726	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1727	else
1728	{
1729	Assert(g_HmR0.fEnabled);
1730	Assert(g_HmR0.fGlobalInit);
1731
1732	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1733	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1734
1735	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1736	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1737	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HmR0.vmx.Msrs);
1738	}
1739	}
1740
1741	#endif /* VBOX_WITH_RAW_MODE */
1742	#ifdef VBOX_STRICT
1743
1744	/**
1745	* Dumps a descriptor.
1746	*
1747	* @param pDesc Descriptor to dump.
1748	* @param Sel Selector number.
1749	* @param pszMsg Message to prepend the log entry with.
1750	*/
1751	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1752	{
1753	/*
1754	* Make variable description string.
1755	*/
1756	static struct
1757	{
1758	unsigned cch;
1759	const char *psz;
1760	} const s_aTypes[32] =
1761	{
1762	# define STRENTRY(str) { sizeof(str) - 1, str }
1763
1764	/* system */
1765	# if HC_ARCH_BITS == 64
1766	STRENTRY("Reserved0 "), /* 0x00 */
1767	STRENTRY("Reserved1 "), /* 0x01 */
1768	STRENTRY("LDT "), /* 0x02 */
1769	STRENTRY("Reserved3 "), /* 0x03 */
1770	STRENTRY("Reserved4 "), /* 0x04 */
1771	STRENTRY("Reserved5 "), /* 0x05 */
1772	STRENTRY("Reserved6 "), /* 0x06 */
1773	STRENTRY("Reserved7 "), /* 0x07 */
1774	STRENTRY("Reserved8 "), /* 0x08 */
1775	STRENTRY("TSS64Avail "), /* 0x09 */
1776	STRENTRY("ReservedA "), /* 0x0a */
1777	STRENTRY("TSS64Busy "), /* 0x0b */
1778	STRENTRY("Call64 "), /* 0x0c */
1779	STRENTRY("ReservedD "), /* 0x0d */
1780	STRENTRY("Int64 "), /* 0x0e */
1781	STRENTRY("Trap64 "), /* 0x0f */
1782	# else
1783	STRENTRY("Reserved0 "), /* 0x00 */
1784	STRENTRY("TSS16Avail "), /* 0x01 */
1785	STRENTRY("LDT "), /* 0x02 */
1786	STRENTRY("TSS16Busy "), /* 0x03 */
1787	STRENTRY("Call16 "), /* 0x04 */
1788	STRENTRY("Task "), /* 0x05 */
1789	STRENTRY("Int16 "), /* 0x06 */
1790	STRENTRY("Trap16 "), /* 0x07 */
1791	STRENTRY("Reserved8 "), /* 0x08 */
1792	STRENTRY("TSS32Avail "), /* 0x09 */
1793	STRENTRY("ReservedA "), /* 0x0a */
1794	STRENTRY("TSS32Busy "), /* 0x0b */
1795	STRENTRY("Call32 "), /* 0x0c */
1796	STRENTRY("ReservedD "), /* 0x0d */
1797	STRENTRY("Int32 "), /* 0x0e */
1798	STRENTRY("Trap32 "), /* 0x0f */
1799	# endif
1800	/* non system */
1801	STRENTRY("DataRO "), /* 0x10 */
1802	STRENTRY("DataRO Accessed "), /* 0x11 */
1803	STRENTRY("DataRW "), /* 0x12 */
1804	STRENTRY("DataRW Accessed "), /* 0x13 */
1805	STRENTRY("DataDownRO "), /* 0x14 */
1806	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1807	STRENTRY("DataDownRW "), /* 0x16 */
1808	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1809	STRENTRY("CodeEO "), /* 0x18 */
1810	STRENTRY("CodeEO Accessed "), /* 0x19 */
1811	STRENTRY("CodeER "), /* 0x1a */
1812	STRENTRY("CodeER Accessed "), /* 0x1b */
1813	STRENTRY("CodeConfEO "), /* 0x1c */
1814	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1815	STRENTRY("CodeConfER "), /* 0x1e */
1816	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1817	# undef SYSENTRY
1818	};
1819	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1820	char szMsg[128];
1821	char *psz = &szMsg[0];
1822	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1823	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1824	psz += s_aTypes[i].cch;
1825
1826	if (pDesc->Gen.u1Present)
1827	ADD_STR(psz, "Present ");
1828	else
1829	ADD_STR(psz, "Not-Present ");
1830	# if HC_ARCH_BITS == 64
1831	if (pDesc->Gen.u1Long)
1832	ADD_STR(psz, "64-bit ");
1833	else
1834	ADD_STR(psz, "Comp ");
1835	# else
1836	if (pDesc->Gen.u1Granularity)
1837	ADD_STR(psz, "Page ");
1838	if (pDesc->Gen.u1DefBig)
1839	ADD_STR(psz, "32-bit ");
1840	else
1841	ADD_STR(psz, "16-bit ");
1842	# endif
1843	# undef ADD_STR
1844	*psz = '\0';
1845
1846	/*
1847	* Limit and Base and format the output.
1848	*/
1849	#ifdef LOG_ENABLED
1850	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1851
1852	# if HC_ARCH_BITS == 64
1853	uint64_t u32Base = X86DESC64_BASE(pDesc);
1854	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1855	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1856	# else
1857	uint32_t u32Base = X86DESC_BASE(pDesc);
1858	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1859	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1860	# endif
1861	#else
1862	NOREF(Sel); NOREF(pszMsg);
1863	#endif
1864	}
1865
1866
1867	/**
1868	* Formats a full register dump.
1869	*
1870	* @param pVM The cross context VM structure.
1871	* @param pVCpu The cross context virtual CPU structure.
1872	* @param pCtx Pointer to the CPU context.
1873	*/
1874	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1875	{
1876	NOREF(pVM);
1877
1878	/*
1879	* Format the flags.
1880	*/
1881	static struct
1882	{
1883	const char pszSet; const char pszClear; uint32_t fFlag;
1884	} const s_aFlags[] =
1885	{
1886	{ "vip", NULL, X86_EFL_VIP },
1887	{ "vif", NULL, X86_EFL_VIF },
1888	{ "ac", NULL, X86_EFL_AC },
1889	{ "vm", NULL, X86_EFL_VM },
1890	{ "rf", NULL, X86_EFL_RF },
1891	{ "nt", NULL, X86_EFL_NT },
1892	{ "ov", "nv", X86_EFL_OF },
1893	{ "dn", "up", X86_EFL_DF },
1894	{ "ei", "di", X86_EFL_IF },
1895	{ "tf", NULL, X86_EFL_TF },
1896	{ "nt", "pl", X86_EFL_SF },
1897	{ "nz", "zr", X86_EFL_ZF },
1898	{ "ac", "na", X86_EFL_AF },
1899	{ "po", "pe", X86_EFL_PF },
1900	{ "cy", "nc", X86_EFL_CF },
1901	};
1902	char szEFlags[80];
1903	char *psz = szEFlags;
1904	uint32_t uEFlags = pCtx->eflags.u32;
1905	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1906	{
1907	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1908	if (pszAdd)
1909	{
1910	strcpy(psz, pszAdd);
1911	psz += strlen(pszAdd);
1912	*psz++ = ' ';
1913	}
1914	}
1915	psz[-1] = '\0';
1916
1917
1918	/*
1919	* Format the registers.
1920	*/
1921	if (CPUMIsGuestIn64BitCode(pVCpu))
1922	{
1923	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1924	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1925	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1926	"r14=%016RX64 r15=%016RX64\n"
1927	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1928	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1929	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1930	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1931	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1932	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1933	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1934	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1935	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1936	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1937	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1938	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1939	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1940	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1941	,
1942	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1943	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1944	pCtx->r14, pCtx->r15,
1945	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1946	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1947	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1948	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1949	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1950	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1951	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1952	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1953	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1954	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1955	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1956	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1957	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1958	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1959	}
1960	else
1961	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1962	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1963	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1964	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1965	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1966	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1967	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1968	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1969	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1970	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1971	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1972	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1973	,
1974	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1975	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1976	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1977	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1978	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1979	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1980	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1981	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1982	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1983	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1984	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1985	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1986
1987	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1988	Log(("FPU:\n"
1989	"FCW=%04x FSW=%04x FTW=%02x\n"
1990	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1991	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1992	,
1993	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1994	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1995	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1996	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1997
1998	Log(("MSR:\n"
1999	"EFER =%016RX64\n"
2000	"PAT =%016RX64\n"
2001	"STAR =%016RX64\n"
2002	"CSTAR =%016RX64\n"
2003	"LSTAR =%016RX64\n"
2004	"SFMASK =%016RX64\n"
2005	"KERNELGSBASE =%016RX64\n",
2006	pCtx->msrEFER,
2007	pCtx->msrPAT,
2008	pCtx->msrSTAR,
2009	pCtx->msrCSTAR,
2010	pCtx->msrLSTAR,
2011	pCtx->msrSFMASK,
2012	pCtx->msrKERNELGSBASE));
2013
2014	NOREF(pFpuCtx);
2015	}
2016
2017	#endif /* VBOX_STRICT */
2018

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 58156

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