HMR0.cpp@ 72747

Last change on this file since 72747 was 72744, checked in by vboxsync, 6 years ago
VMM: Extend HM changed flags. bugref:9193 [HM, CPUM]
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1	/* $Id: HMR0.cpp 72744 2018-06-29 07:36:19Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/gim.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mem.h>
37	#include <iprt/memobj.h>
38	#include <iprt/once.h>
39	#include <iprt/param.h>
40	#include <iprt/power.h>
41	#include <iprt/string.h>
42	#include <iprt/thread.h>
43	#include <iprt/x86.h>
44	#include "HMVMXR0.h"
45	#include "HMSVMR0.h"
46
47
48	/*********************************************************************************************************************************
49	* Internal Functions *
50	*********************************************************************************************************************************/
51	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
56	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
57
58
59	/*********************************************************************************************************************************
60	* Structures and Typedefs *
61	*********************************************************************************************************************************/
62	/**
63	* This is used to manage the status code of a RTMpOnAll in HM.
64	*/
65	typedef struct HMR0FIRSTRC
66	{
67	/** The status code. */
68	int32_t volatile rc;
69	/** The ID of the CPU reporting the first failure. */
70	RTCPUID volatile idCpu;
71	} HMR0FIRSTRC;
72	/** Pointer to a first return code structure. */
73	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
74
75
76	/*********************************************************************************************************************************
77	* Global Variables *
78	*********************************************************************************************************************************/
79	/**
80	* Global data.
81	*/
82	static struct
83	{
84	/** Per CPU globals. */
85	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
86
87	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
88	* @{ */
89	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
90	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
91	DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPU pVCpu));
92	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94	bool fEnabledByHost, void *pvArg));
95	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
96	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
99	/** @} */
100
101	/** Maximum ASID allowed. */
102	uint32_t uMaxAsid;
103
104	/** VT-x data. */
105	struct
106	{
107	/** Set to by us to indicate VMX is supported by the CPU. */
108	bool fSupported;
109	/** Whether we're using SUPR0EnableVTx or not. */
110	bool fUsingSUPR0EnableVTx;
111	/** Whether we're using the preemption timer or not. */
112	bool fUsePreemptTimer;
113	/** The shift mask employed by the VMX-Preemption timer. */
114	uint8_t cPreemptTimerShift;
115
116	/** Host CR4 value (set by ring-0 VMX init) */
117	uint64_t u64HostCr4;
118	/** Host EFER value (set by ring-0 VMX init) */
119	uint64_t u64HostEfer;
120	/** Host SMM monitor control (used for logging/diagnostics) */
121	uint64_t u64HostSmmMonitorCtl;
122
123	/** VMX MSR values */
124	VMXMSRS Msrs;
125
126	/** Last instruction error. */
127	uint32_t ulLastInstrError;
128
129	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
130	* module termination. */
131	bool fCalledSUPR0EnableVTx;
132	} vmx;
133
134	/** AMD-V information. */
135	struct
136	{
137	/* HWCR MSR (for diagnostics) */
138	uint64_t u64MsrHwcr;
139
140	/** SVM revision. */
141	uint32_t u32Rev;
142
143	/** SVM feature bits from cpuid 0x8000000a */
144	uint32_t u32Features;
145
146	/** Set by us to indicate SVM is supported by the CPU. */
147	bool fSupported;
148	} svm;
149
150	/** Saved error from detection */
151	int32_t lLastError;
152
153	/** CPUID 0x80000001 ecx:edx features */
154	struct
155	{
156	uint32_t u32AMDFeatureECX;
157	uint32_t u32AMDFeatureEDX;
158	} cpuid;
159
160	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
161	* enabled and disabled each time it's used to execute guest code. */
162	bool fGlobalInit;
163	/** Indicates whether the host is suspending or not. We'll refuse a few
164	* actions when the host is being suspended to speed up the suspending and
165	* avoid trouble. */
166	volatile bool fSuspended;
167
168	/** Whether we've already initialized all CPUs.
169	* @remarks We could check the EnableAllCpusOnce state, but this is
170	* simpler and hopefully easier to understand. */
171	bool fEnabled;
172	/** Serialize initialization in HMR0EnableAllCpus. */
173	RTONCE EnableAllCpusOnce;
174	} g_HmR0;
175
176
177	/**
178	* Initializes a first return code structure.
179	*
180	* @param pFirstRc The structure to init.
181	*/
182	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
183	{
184	pFirstRc->rc = VINF_SUCCESS;
185	pFirstRc->idCpu = NIL_RTCPUID;
186	}
187
188
189	/**
190	* Try set the status code (success ignored).
191	*
192	* @param pFirstRc The first return code structure.
193	* @param rc The status code.
194	*/
195	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
196	{
197	if ( RT_FAILURE(rc)
198	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
199	pFirstRc->idCpu = RTMpCpuId();
200	}
201
202
203	/**
204	* Get the status code of a first return code structure.
205	*
206	* @returns The status code; VINF_SUCCESS or error status, no informational or
207	* warning errors.
208	* @param pFirstRc The first return code structure.
209	*/
210	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
211	{
212	return pFirstRc->rc;
213	}
214
215
216	#ifdef VBOX_STRICT
217	# ifndef DEBUG_bird
218	/**
219	* Get the CPU ID on which the failure status code was reported.
220	*
221	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
222	* @param pFirstRc The first return code structure.
223	*/
224	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
225	{
226	return pFirstRc->idCpu;
227	}
228	# endif
229	#endif /* VBOX_STRICT */
230
231
232	/** @name Dummy callback handlers.
233	* @{ */
234
235	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
236	{
237	RT_NOREF3(pVM, pVCpu, pCpu);
238	return VINF_SUCCESS;
239	}
240
241	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
242	{
243	RT_NOREF3(enmEvent, pVCpu, fGlobalInit);
244	}
245
246	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
247	bool fEnabledBySystem, void *pvArg)
248	{
249	RT_NOREF6(pCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pvArg);
250	return VINF_SUCCESS;
251	}
252
253	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
254	{
255	RT_NOREF3(pCpu, pvCpuPage, HCPhysCpuPage);
256	return VINF_SUCCESS;
257	}
258
259	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
260	{
261	RT_NOREF1(pVM);
262	return VINF_SUCCESS;
263	}
264
265	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
266	{
267	RT_NOREF1(pVM);
268	return VINF_SUCCESS;
269	}
270
271	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
272	{
273	RT_NOREF1(pVM);
274	return VINF_SUCCESS;
275	}
276
277	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
278	{
279	RT_NOREF3(pVM, pVCpu, pCtx);
280	return VINF_SUCCESS;
281	}
282
283	static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPU pVCpu)
284	{
285	RT_NOREF1(pVCpu);
286	return VINF_SUCCESS;
287	}
288
289	/** @} */
290
291
292	/**
293	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
294	* Down at the Rate Specified" erratum.
295	*
296	* Errata names and related steppings:
297	* - BA86 - D0.
298	* - AAX65 - C2.
299	* - AAU65 - C2, K0.
300	* - AAO95 - B1.
301	* - AAT59 - C2.
302	* - AAK139 - D0.
303	* - AAM126 - C0, C1, D0.
304	* - AAN92 - B1.
305	* - AAJ124 - C0, D0.
306	*
307	* - AAP86 - B1.
308	*
309	* Steppings: B1, C0, C1, C2, D0, K0.
310	*
311	* @returns true if subject to it, false if not.
312	*/
313	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
314	{
315	uint32_t u = ASMCpuId_EAX(1);
316	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
317	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
318	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
319	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
320	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
321	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
322	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
323	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
324	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
325	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
326	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
327	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
328	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
329	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
330	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
331	)
332	return true;
333	return false;
334	}
335
336
337	/**
338	* Intel specific initialization code.
339	*
340	* @returns VBox status code (will only fail if out of memory).
341	*/
342	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
343	{
344	/*
345	* Check that all the required VT-x features are present.
346	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
347	*/
348	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
349	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
350	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
351	)
352	{
353	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
354	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
355
356	/*
357	* First try use native kernel API for controlling VT-x.
358	* (This is only supported by some Mac OS X kernels atm.)
359	*/
360	int rc = g_HmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
361	g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
362	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
363	{
364	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
365	if (RT_SUCCESS(rc))
366	{
367	g_HmR0.vmx.fSupported = true;
368	rc = SUPR0EnableVTx(false /* fEnable */);
369	AssertLogRelRC(rc);
370	}
371	}
372	else
373	{
374	HMR0FIRSTRC FirstRc;
375	hmR0FirstRcInit(&FirstRc);
376	g_HmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
377	if (RT_SUCCESS(g_HmR0.lLastError))
378	g_HmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
379	}
380	if (RT_SUCCESS(g_HmR0.lLastError))
381	{
382	/* Reread in case it was changed by SUPR0GetVmxUsability(). */
383	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
384
385	/*
386	* Read all relevant registers and MSRs.
387	*/
388	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
389	g_HmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
390	g_HmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
391	/* KVM workaround: Intel SDM section 34.15.5 describes that MSR_IA32_SMM_MONITOR_CTL
392	* depends on bit 49 of MSR_IA32_VMX_BASIC_INFO while table 35-2 says that this MSR
393	* is available if either VMX or SMX is supported. */
394	if (MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(g_HmR0.vmx.Msrs.u64BasicInfo))
395	g_HmR0.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
396	g_HmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
397	g_HmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
398	g_HmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
399	g_HmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
400	g_HmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
401	g_HmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
402	g_HmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
403	g_HmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
404	g_HmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
405	g_HmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
406	/* VPID 16 bits ASID. */
407	g_HmR0.uMaxAsid = 0x10000; /* exclusive */
408
409	if (g_HmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
410	{
411	g_HmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
412	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
413	g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
414
415	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
416	g_HmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
417	}
418
419	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
420	{
421	/*
422	* Enter root mode
423	*/
424	RTR0MEMOBJ hScatchMemObj;
425	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
426	if (RT_FAILURE(rc))
427	{
428	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
429	return rc;
430	}
431
432	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
433	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
434	ASMMemZeroPage(pvScatchPage);
435
436	/* Set revision dword at the beginning of the structure. */
437	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HmR0.vmx.Msrs.u64BasicInfo);
438
439	/* Make sure we don't get rescheduled to another cpu during this probe. */
440	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
441
442	/*
443	* Check CR4.VMXE.
444	*/
445	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
446	if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
447	{
448	/* In theory this bit could be cleared behind our back. Which would cause #UD
449	faults when we try to execute the VMX instructions... */
450	ASMSetCR4(g_HmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
451	}
452
453	/*
454	* The only way of checking if we're in VMX root mode or not is to try and enter it.
455	* There is no instruction or control bit that tells us if we're in VMX root mode.
456	* Therefore, try and enter VMX root mode here.
457	*/
458	rc = VMXEnable(HCPhysScratchPage);
459	if (RT_SUCCESS(rc))
460	{
461	g_HmR0.vmx.fSupported = true;
462	VMXDisable();
463	}
464	else
465	{
466	/*
467	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
468	* it will crash the host when we enter raw mode, because:
469	*
470	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
471	* this bit), and
472	* (b) turning off paging causes a #GP (unavoidable when switching
473	* from long to 32 bits mode or 32 bits to PAE).
474	*
475	* They should fix their code, but until they do we simply refuse to run.
476	*/
477	g_HmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
478	Assert(g_HmR0.vmx.fSupported == false);
479	}
480
481	/*
482	* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it was not
483	* set before (some software could incorrectly think it is in VMX mode).
484	*/
485	ASMSetCR4(g_HmR0.vmx.u64HostCr4);
486	ASMSetFlags(fEFlags);
487
488	RTR0MemObjFree(hScatchMemObj, false);
489	}
490
491	if (g_HmR0.vmx.fSupported)
492	{
493	rc = VMXR0GlobalInit();
494	if (RT_FAILURE(rc))
495	g_HmR0.lLastError = rc;
496
497	/*
498	* Install the VT-x methods.
499	*/
500	g_HmR0.pfnEnterSession = VMXR0Enter;
501	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
502	g_HmR0.pfnExportHostState = VMXR0ExportHostState;
503	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
504	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
505	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
506	g_HmR0.pfnInitVM = VMXR0InitVM;
507	g_HmR0.pfnTermVM = VMXR0TermVM;
508	g_HmR0.pfnSetupVM = VMXR0SetupVM;
509
510	/*
511	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
512	* Timer Does Not Count Down at the Rate Specified" erratum.
513	*/
514	if (g_HmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
515	{
516	g_HmR0.vmx.fUsePreemptTimer = true;
517	g_HmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HmR0.vmx.Msrs.u64Misc);
518	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
519	g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
520	}
521	}
522	}
523	#ifdef LOG_ENABLED
524	else
525	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HmR0.lLastError);
526	#endif
527	}
528	else
529	g_HmR0.lLastError = VERR_VMX_NO_VMX;
530	return VINF_SUCCESS;
531	}
532
533
534	/**
535	* AMD-specific initialization code.
536	*
537	* @returns VBox status code.
538	*/
539	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
540	{
541	/*
542	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
543	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
544	*/
545	int rc;
546	if ( (g_HmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
547	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
548	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
549	&& ASMIsValidExtRange(uMaxExtLeaf)
550	&& uMaxExtLeaf >= 0x8000000a
551	)
552	{
553	/* Call the global AMD-V initialization routine. */
554	rc = SVMR0GlobalInit();
555	if (RT_FAILURE(rc))
556	{
557	g_HmR0.lLastError = rc;
558	return rc;
559	}
560
561	/*
562	* Install the AMD-V methods.
563	*/
564	g_HmR0.pfnEnterSession = SVMR0Enter;
565	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
566	g_HmR0.pfnExportHostState = SVMR0ExportHostState;
567	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
568	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
569	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
570	g_HmR0.pfnInitVM = SVMR0InitVM;
571	g_HmR0.pfnTermVM = SVMR0TermVM;
572	g_HmR0.pfnSetupVM = SVMR0SetupVM;
573
574	/* Query AMD features. */
575	uint32_t u32Dummy;
576	ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
577
578	/*
579	* We need to check if AMD-V has been properly initialized on all CPUs.
580	* Some BIOSes might do a poor job.
581	*/
582	HMR0FIRSTRC FirstRc;
583	hmR0FirstRcInit(&FirstRc);
584	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
585	AssertRC(rc);
586	if (RT_SUCCESS(rc))
587	rc = hmR0FirstRcGetStatus(&FirstRc);
588	#ifndef DEBUG_bird
589	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
590	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
591	#endif
592	if (RT_SUCCESS(rc))
593	{
594	/* Read the HWCR MSR for diagnostics. */
595	g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
596	g_HmR0.svm.fSupported = true;
597	}
598	else
599	{
600	g_HmR0.lLastError = rc;
601	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
602	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
603	}
604	}
605	else
606	{
607	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
608	g_HmR0.lLastError = VERR_SVM_NO_SVM;
609	}
610	return rc;
611	}
612
613
614	/**
615	* Does global Ring-0 HM initialization (at module init).
616	*
617	* @returns VBox status code.
618	*/
619	VMMR0_INT_DECL(int) HMR0Init(void)
620	{
621	/*
622	* Initialize the globals.
623	*/
624	g_HmR0.fEnabled = false;
625	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
626	g_HmR0.EnableAllCpusOnce = s_OnceInit;
627	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
628	{
629	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
630	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
631	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
632	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
633	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
634	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
635	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
636	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
637	#endif
638	}
639
640	/* Fill in all callbacks with placeholders. */
641	g_HmR0.pfnEnterSession = hmR0DummyEnter;
642	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
643	g_HmR0.pfnExportHostState = hmR0DummyExportHostState;
644	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
645	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
646	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
647	g_HmR0.pfnInitVM = hmR0DummyInitVM;
648	g_HmR0.pfnTermVM = hmR0DummyTermVM;
649	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
650
651	/* Default is global VT-x/AMD-V init. */
652	g_HmR0.fGlobalInit = true;
653
654	/*
655	* Make sure aCpuInfo is big enough for all the CPUs on this system.
656	*/
657	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
658	{
659	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
660	return VERR_TOO_MANY_CPUS;
661	}
662
663	/*
664	* Check for VT-x and AMD-V capabilities.
665	*/
666	int rc;
667	if (ASMHasCpuId())
668	{
669	/* Standard features. */
670	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
671	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
672	if (ASMIsValidStdRange(uMaxLeaf))
673	{
674	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
675	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
676
677	/* Query AMD features. */
678	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
679	if (ASMIsValidExtRange(uMaxExtLeaf))
680	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
681	&g_HmR0.cpuid.u32AMDFeatureECX,
682	&g_HmR0.cpuid.u32AMDFeatureEDX);
683	else
684	g_HmR0.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureEDX = 0;
685
686	/* Go to CPU specific initialization code. */
687	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
688	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
689	{
690	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
691	if (RT_FAILURE(rc))
692	return rc;
693	}
694	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
695	{
696	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
697	if (RT_FAILURE(rc))
698	return rc;
699	}
700	else
701	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
702	}
703	else
704	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
705	}
706	else
707	g_HmR0.lLastError = VERR_HM_NO_CPUID;
708
709	/*
710	* Register notification callbacks that we can use to disable/enable CPUs
711	* when brought offline/online or suspending/resuming.
712	*/
713	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
714	{
715	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
716	AssertRC(rc);
717
718	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
719	AssertRC(rc);
720	}
721
722	/* We return success here because module init shall not fail if HM
723	fails to initialize. */
724	return VINF_SUCCESS;
725	}
726
727
728	/**
729	* Does global Ring-0 HM termination (at module termination).
730	*
731	* @returns VBox status code.
732	*/
733	VMMR0_INT_DECL(int) HMR0Term(void)
734	{
735	int rc;
736	if ( g_HmR0.vmx.fSupported
737	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
738	{
739	/*
740	* Simple if the host OS manages VT-x.
741	*/
742	Assert(g_HmR0.fGlobalInit);
743
744	if (g_HmR0.vmx.fCalledSUPR0EnableVTx)
745	{
746	rc = SUPR0EnableVTx(false /* fEnable */);
747	g_HmR0.vmx.fCalledSUPR0EnableVTx = false;
748	}
749	else
750	rc = VINF_SUCCESS;
751
752	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
753	{
754	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
755	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
756	}
757	}
758	else
759	{
760	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
761
762	/* Doesn't really matter if this fails. */
763	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
764	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
765
766	/*
767	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
768	*/
769	if (g_HmR0.fGlobalInit)
770	{
771	HMR0FIRSTRC FirstRc;
772	hmR0FirstRcInit(&FirstRc);
773	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
774	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
775	if (RT_SUCCESS(rc))
776	rc = hmR0FirstRcGetStatus(&FirstRc);
777	}
778
779	/*
780	* Free the per-cpu pages used for VT-x and AMD-V.
781	*/
782	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
783	{
784	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
785	{
786	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
787	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
788	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
789	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
790	}
791	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
792	if (g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
793	{
794	RTR0MemObjFree(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, false);
795	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
796	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
797	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
798	}
799	#endif
800	}
801	}
802
803	/** @todo This needs cleaning up. There's no matching
804	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
805	* should move into their respective modules. */
806	/* Finally, call global VT-x/AMD-V termination. */
807	if (g_HmR0.vmx.fSupported)
808	VMXR0GlobalTerm();
809	else if (g_HmR0.svm.fSupported)
810	SVMR0GlobalTerm();
811
812	return rc;
813	}
814
815
816	/**
817	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
818	* on a CPU.
819	*
820	* @param idCpu The identifier for the CPU the function is called on.
821	* @param pvUser1 Pointer to the first RC structure.
822	* @param pvUser2 Ignored.
823	*/
824	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
825	{
826	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
827	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
828	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
829	NOREF(idCpu); NOREF(pvUser2);
830
831	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
832	hmR0FirstRcSetStatus(pFirstRc, rc);
833	}
834
835
836	/**
837	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
838	* on a CPU.
839	*
840	* @param idCpu The identifier for the CPU the function is called on.
841	* @param pvUser1 Pointer to the first RC structure.
842	* @param pvUser2 Ignored.
843	*/
844	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
845	{
846	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
847	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
848	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
849	NOREF(idCpu); NOREF(pvUser2);
850
851	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
852	hmR0FirstRcSetStatus(pFirstRc, rc);
853	}
854
855
856	/**
857	* Enable VT-x or AMD-V on the current CPU
858	*
859	* @returns VBox status code.
860	* @param pVM The cross context VM structure. Can be NULL.
861	* @param idCpu The identifier for the CPU the function is called on.
862	*
863	* @remarks Maybe called with interrupts disabled!
864	*/
865	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
866	{
867	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
868
869	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
870	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
871	Assert(!pCpu->fConfigured);
872	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
873
874	pCpu->idCpu = idCpu;
875	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
876
877	int rc;
878	if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
879	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
880	else
881	{
882	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
883	if (g_HmR0.vmx.fSupported)
884	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pCpu->pvMemObj, pCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
885	else
886	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pCpu->pvMemObj, pCpu->HCPhysMemObj, false, NULL /* pvArg */);
887	}
888	if (RT_SUCCESS(rc))
889	pCpu->fConfigured = true;
890
891	return rc;
892	}
893
894
895	/**
896	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
897	*
898	* @param idCpu The identifier for the CPU the function is called on.
899	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
900	* @param pvUser2 The 2nd user argument.
901	*/
902	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
903	{
904	PVM pVM = (PVM)pvUser1; /* can be NULL! */
905	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
906	AssertReturnVoid(g_HmR0.fGlobalInit);
907	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
908	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
909	}
910
911
912	/**
913	* RTOnce callback employed by HMR0EnableAllCpus.
914	*
915	* @returns VBox status code.
916	* @param pvUser Pointer to the VM.
917	*/
918	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
919	{
920	PVM pVM = (PVM)pvUser;
921
922	/*
923	* Indicate that we've initialized.
924	*
925	* Note! There is a potential race between this function and the suspend
926	* notification. Kind of unlikely though, so ignored for now.
927	*/
928	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
929	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
930
931	/*
932	* The global init variable is set by the first VM.
933	*/
934	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
935
936	#ifdef VBOX_STRICT
937	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
938	{
939	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
940	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
941	Assert(g_HmR0.aCpuInfo[i].pvMemObj == NULL);
942	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
943	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
944	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
945	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
946	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
947	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
948	Assert(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
949	# endif
950	}
951	#endif
952
953	int rc;
954	if ( g_HmR0.vmx.fSupported
955	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
956	{
957	/*
958	* Global VT-x initialization API (only darwin for now).
959	*/
960	rc = SUPR0EnableVTx(true /* fEnable */);
961	if (RT_SUCCESS(rc))
962	{
963	g_HmR0.vmx.fCalledSUPR0EnableVTx = true;
964	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
965	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
966	}
967	else
968	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
969	}
970	else
971	{
972	/*
973	* We're doing the job ourselves.
974	*/
975	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
976	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
977	{
978	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
979	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
980	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
981	#endif
982	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
983	{
984	/** @todo NUMA */
985	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
986	AssertLogRelRCReturn(rc, rc);
987
988	g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
989	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
990	Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
991
992	g_HmR0.aCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
993	AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
994	ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
995
996	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
997	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
998	false /* executable R0 mapping */);
999	AssertLogRelRCReturn(rc, rc);
1000
1001	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, 0);
1002	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
1003	Assert(!(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
1004
1005	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm);
1006	AssertPtr(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm);
1007	ASMMemFill32(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
1008	#endif
1009	}
1010	}
1011
1012	rc = VINF_SUCCESS;
1013	}
1014
1015	if ( RT_SUCCESS(rc)
1016	&& g_HmR0.fGlobalInit)
1017	{
1018	/* First time, so initialize each cpu/core. */
1019	HMR0FIRSTRC FirstRc;
1020	hmR0FirstRcInit(&FirstRc);
1021	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1022	if (RT_SUCCESS(rc))
1023	rc = hmR0FirstRcGetStatus(&FirstRc);
1024	}
1025
1026	return rc;
1027	}
1028
1029
1030	/**
1031	* Sets up HM on all cpus.
1032	*
1033	* @returns VBox status code.
1034	* @param pVM The cross context VM structure.
1035	*/
1036	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1037	{
1038	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1039	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1040	return VERR_HM_SUSPEND_PENDING;
1041
1042	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1043	}
1044
1045
1046	/**
1047	* Disable VT-x or AMD-V on the current CPU.
1048	*
1049	* @returns VBox status code.
1050	* @param idCpu The identifier for the CPU this function is called on.
1051	*
1052	* @remarks Must be called with preemption disabled.
1053	*/
1054	static int hmR0DisableCpu(RTCPUID idCpu)
1055	{
1056	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1057
1058	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1059	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1060	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1061	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1062	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1063	AssertRelease(idCpu == RTMpCpuId());
1064
1065	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1066	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1067	AssertPtr(pCpu->pvMemObj);
1068	Assert(pCpu->HCPhysMemObj != NIL_RTHCPHYS);
1069
1070	int rc;
1071	if (pCpu->fConfigured)
1072	{
1073	rc = g_HmR0.pfnDisableCpu(pCpu, pCpu->pvMemObj, pCpu->HCPhysMemObj);
1074	AssertRCReturn(rc, rc);
1075
1076	pCpu->fConfigured = false;
1077	pCpu->idCpu = NIL_RTCPUID;
1078	}
1079	else
1080	rc = VINF_SUCCESS; /* nothing to do */
1081	return rc;
1082	}
1083
1084
1085	/**
1086	* Worker function passed to RTMpOnAll() that is to be called on the target
1087	* CPUs.
1088	*
1089	* @param idCpu The identifier for the CPU the function is called on.
1090	* @param pvUser1 The 1st user argument.
1091	* @param pvUser2 Opaque pointer to the FirstRc.
1092	*/
1093	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1094	{
1095	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1096	AssertReturnVoid(g_HmR0.fGlobalInit);
1097	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1098	}
1099
1100
1101	/**
1102	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1103	* CPU.
1104	*
1105	* @param idCpu The identifier for the CPU the function is called on.
1106	* @param pvUser1 Null, not used.
1107	* @param pvUser2 Null, not used.
1108	*/
1109	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1110	{
1111	NOREF(pvUser1);
1112	NOREF(pvUser2);
1113	hmR0DisableCpu(idCpu);
1114	}
1115
1116
1117	/**
1118	* Callback function invoked when a cpu goes online or offline.
1119	*
1120	* @param enmEvent The Mp event.
1121	* @param idCpu The identifier for the CPU the function is called on.
1122	* @param pvData Opaque data (PVM pointer).
1123	*/
1124	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1125	{
1126	NOREF(pvData);
1127	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1128
1129	/*
1130	* We only care about uninitializing a CPU that is going offline. When a
1131	* CPU comes online, the initialization is done lazily in HMR0Enter().
1132	*/
1133	switch (enmEvent)
1134	{
1135	case RTMPEVENT_OFFLINE:
1136	{
1137	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1138	RTThreadPreemptDisable(&PreemptState);
1139	if (idCpu == RTMpCpuId())
1140	{
1141	int rc = hmR0DisableCpu(idCpu);
1142	AssertRC(rc);
1143	RTThreadPreemptRestore(&PreemptState);
1144	}
1145	else
1146	{
1147	RTThreadPreemptRestore(&PreemptState);
1148	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1149	}
1150	break;
1151	}
1152
1153	default:
1154	break;
1155	}
1156	}
1157
1158
1159	/**
1160	* Called whenever a system power state change occurs.
1161	*
1162	* @param enmEvent The Power event.
1163	* @param pvUser User argument.
1164	*/
1165	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1166	{
1167	NOREF(pvUser);
1168	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1169
1170	#ifdef LOG_ENABLED
1171	if (enmEvent == RTPOWEREVENT_SUSPEND)
1172	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1173	else
1174	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1175	#endif
1176
1177	if (enmEvent == RTPOWEREVENT_SUSPEND)
1178	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1179
1180	if (g_HmR0.fEnabled)
1181	{
1182	int rc;
1183	HMR0FIRSTRC FirstRc;
1184	hmR0FirstRcInit(&FirstRc);
1185
1186	if (enmEvent == RTPOWEREVENT_SUSPEND)
1187	{
1188	if (g_HmR0.fGlobalInit)
1189	{
1190	/* Turn off VT-x or AMD-V on all CPUs. */
1191	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1192	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1193	}
1194	/* else nothing to do here for the local init case */
1195	}
1196	else
1197	{
1198	/* Reinit the CPUs from scratch as the suspend state might have
1199	messed with the MSRs. (lousy BIOSes as usual) */
1200	if (g_HmR0.vmx.fSupported)
1201	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1202	else
1203	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1204	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1205	if (RT_SUCCESS(rc))
1206	rc = hmR0FirstRcGetStatus(&FirstRc);
1207	#ifdef LOG_ENABLED
1208	if (RT_FAILURE(rc))
1209	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1210	#endif
1211	if (g_HmR0.fGlobalInit)
1212	{
1213	/* Turn VT-x or AMD-V back on on all CPUs. */
1214	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1215	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1216	}
1217	/* else nothing to do here for the local init case */
1218	}
1219	}
1220
1221	if (enmEvent == RTPOWEREVENT_RESUME)
1222	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1223	}
1224
1225
1226	/**
1227	* Does ring-0 per-VM HM initialization.
1228	*
1229	* This will copy HM global into the VM structure and call the CPU specific
1230	* init routine which will allocate resources for each virtual CPU and such.
1231	*
1232	* @returns VBox status code.
1233	* @param pVM The cross context VM structure.
1234	*
1235	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1236	* vmR3InitRing3().
1237	*/
1238	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1239	{
1240	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1241
1242	#ifdef LOG_ENABLED
1243	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1244	#endif
1245
1246	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1247	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1248	return VERR_HM_SUSPEND_PENDING;
1249
1250	/*
1251	* Copy globals to the VM structure.
1252	*/
1253	pVM->hm.s.vmx.fSupported = g_HmR0.vmx.fSupported;
1254	pVM->hm.s.svm.fSupported = g_HmR0.svm.fSupported;
1255
1256	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1257	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.vmx.cPreemptTimerShift;
1258	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.vmx.u64HostCr4;
1259	pVM->hm.s.vmx.u64HostEfer = g_HmR0.vmx.u64HostEfer;
1260	pVM->hm.s.vmx.u64HostSmmMonitorCtl = g_HmR0.vmx.u64HostSmmMonitorCtl;
1261	pVM->hm.s.vmx.Msrs = g_HmR0.vmx.Msrs;
1262	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.svm.u64MsrHwcr;
1263	pVM->hm.s.svm.u32Rev = g_HmR0.svm.u32Rev;
1264	pVM->hm.s.svm.u32Features = g_HmR0.svm.u32Features;
1265	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureECX;
1266	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HmR0.cpuid.u32AMDFeatureEDX;
1267	pVM->hm.s.lLastError = g_HmR0.lLastError;
1268	pVM->hm.s.uMaxAsid = g_HmR0.uMaxAsid;
1269
1270	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1271	{
1272	pVM->hm.s.cMaxResumeLoops = 1024;
1273	if (RTThreadPreemptIsPendingTrusty())
1274	pVM->hm.s.cMaxResumeLoops = 8192;
1275	}
1276
1277	/*
1278	* Initialize some per-VCPU fields.
1279	*/
1280	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1281	{
1282	PVMCPU pVCpu = &pVM->aCpus[i];
1283	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1284	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1285	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1286
1287	/* We'll aways increment this the first time (host uses ASID 0). */
1288	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1289	}
1290
1291	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1292
1293	/*
1294	* Call the hardware specific initialization method.
1295	*/
1296	return g_HmR0.pfnInitVM(pVM);
1297	}
1298
1299
1300	/**
1301	* Does ring-0 per VM HM termination.
1302	*
1303	* @returns VBox status code.
1304	* @param pVM The cross context VM structure.
1305	*/
1306	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1307	{
1308	Log(("HMR0TermVM: %p\n", pVM));
1309	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1310
1311	/*
1312	* Call the hardware specific method.
1313	*
1314	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1315	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1316	*/
1317	return g_HmR0.pfnTermVM(pVM);
1318	}
1319
1320
1321	/**
1322	* Sets up a VT-x or AMD-V session.
1323	*
1324	* This is mostly about setting up the hardware VM state.
1325	*
1326	* @returns VBox status code.
1327	* @param pVM The cross context VM structure.
1328	*/
1329	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1330	{
1331	Log(("HMR0SetupVM: %p\n", pVM));
1332	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1333
1334	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1335	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1336
1337	/* On first entry we'll sync everything. */
1338	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1339	{
1340	PVMCPU pVCpu = &pVM->aCpus[i];
1341	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1342	}
1343
1344	/*
1345	* Call the hardware specific setup VM method. This requires the CPU to be
1346	* enabled for AMD-V/VT-x and preemption to be prevented.
1347	*/
1348	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1349	RTThreadPreemptDisable(&PreemptState);
1350	RTCPUID idCpu = RTMpCpuId();
1351
1352	/* Enable VT-x or AMD-V if local init is required. */
1353	int rc;
1354	if (!g_HmR0.fGlobalInit)
1355	{
1356	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1357	rc = hmR0EnableCpu(pVM, idCpu);
1358	if (RT_FAILURE(rc))
1359	{
1360	RTThreadPreemptRestore(&PreemptState);
1361	return rc;
1362	}
1363	}
1364
1365	/* Setup VT-x or AMD-V. */
1366	rc = g_HmR0.pfnSetupVM(pVM);
1367
1368	/* Disable VT-x or AMD-V if local init was done before. */
1369	if (!g_HmR0.fGlobalInit)
1370	{
1371	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1372	int rc2 = hmR0DisableCpu(idCpu);
1373	AssertRC(rc2);
1374	}
1375
1376	RTThreadPreemptRestore(&PreemptState);
1377	return rc;
1378	}
1379
1380
1381	/**
1382	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1383	* required for entering HM context.
1384	*
1385	* @returns VBox status code.
1386	* @param pVCpu The cross context virtual CPU structure.
1387	*
1388	* @remarks No-long-jump zone!!!
1389	*/
1390	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1391	{
1392	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1393
1394	int rc = VINF_SUCCESS;
1395	RTCPUID idCpu = RTMpCpuId();
1396	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1397	AssertPtr(pCpu);
1398
1399	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1400	if (!pCpu->fConfigured)
1401	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1402
1403	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1404	if (g_HmR0.vmx.fSupported)
1405	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1406	else
1407	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1408
1409	Assert(pCpu->idCpu == idCpu && pCpu->idCpu != NIL_RTCPUID);
1410	pVCpu->hm.s.idEnteredCpu = idCpu;
1411	return rc;
1412	}
1413
1414
1415	/**
1416	* Enters the VT-x or AMD-V session.
1417	*
1418	* @returns VBox status code.
1419	* @param pVM The cross context VM structure.
1420	* @param pVCpu The cross context virtual CPU structure.
1421	*
1422	* @remarks This is called with preemption disabled.
1423	*/
1424	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1425	{
1426	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1427	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1428	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1429
1430	/* Load the bare minimum state required for entering HM. */
1431	int rc = HMR0EnterCpu(pVCpu);
1432	AssertRCReturn(rc, rc);
1433
1434	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1435	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1436	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1437	#endif
1438
1439	RTCPUID idCpu = RTMpCpuId();
1440	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1441	Assert(pCpu);
1442	if (g_HmR0.vmx.fSupported)
1443	{
1444	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1445	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1446	}
1447	else
1448	{
1449	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1450	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1451	}
1452
1453	rc = g_HmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1454	AssertMsgRCReturn(rc, ("rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1455
1456	/* Exports the host-state as we may be resuming code after a longjmp and quite
1457	possibly now be scheduled on a different CPU. */
1458	rc = g_HmR0.pfnExportHostState(pVCpu);
1459	AssertMsgRCReturn(rc, ("rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1460
1461	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1462	if (fStartedSet)
1463	PGMRZDynMapReleaseAutoSet(pVCpu);
1464	#endif
1465
1466	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1467	if (RT_FAILURE(rc))
1468	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1469	return rc;
1470	}
1471
1472
1473	/**
1474	* Deinitializes the bare minimum state used for HM context and if necessary
1475	* disable HM on the CPU.
1476	*
1477	* @returns VBox status code.
1478	* @param pVCpu The cross context virtual CPU structure.
1479	*
1480	* @remarks No-long-jump zone!!!
1481	*/
1482	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1483	{
1484	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1485	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1486
1487	RTCPUID idCpu = RTMpCpuId();
1488	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1489
1490	if ( !g_HmR0.fGlobalInit
1491	&& pCpu->fConfigured)
1492	{
1493	int rc = hmR0DisableCpu(idCpu);
1494	AssertRCReturn(rc, rc);
1495	Assert(!pCpu->fConfigured);
1496	Assert(pCpu->idCpu == NIL_RTCPUID);
1497
1498	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1499	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1500	}
1501
1502	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1503	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1504
1505	return VINF_SUCCESS;
1506	}
1507
1508
1509	/**
1510	* Thread-context hook for HM.
1511	*
1512	* @param enmEvent The thread-context event.
1513	* @param pvUser Opaque pointer to the VMCPU.
1514	*/
1515	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1516	{
1517	PVMCPU pVCpu = (PVMCPU)pvUser;
1518	Assert(pVCpu);
1519	Assert(g_HmR0.pfnThreadCtxCallback);
1520
1521	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1522	}
1523
1524
1525	/**
1526	* Runs guest code in a hardware accelerated VM.
1527	*
1528	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1529	* called from setjmp assembly.)
1530	* @param pVM The cross context VM structure.
1531	* @param pVCpu The cross context virtual CPU structure.
1532	*
1533	* @remarks Can be called with preemption enabled if thread-context hooks are
1534	* used!!!
1535	*/
1536	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1537	{
1538	#ifdef VBOX_STRICT
1539	/* With thread-context hooks we would be running this code with preemption enabled. */
1540	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1541	{
1542	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1543	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1544	Assert(pCpu->fConfigured);
1545	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1546	}
1547	#endif
1548
1549	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1550	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1551	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1552	PGMRZDynMapStartAutoSet(pVCpu);
1553	#endif
1554
1555	VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1556
1557	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1558	PGMRZDynMapReleaseAutoSet(pVCpu);
1559	#endif
1560	return VBOXSTRICTRC_VAL(rcStrict);
1561	}
1562
1563
1564	/**
1565	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1566	* the host CPU and that guest access to it must be intercepted.
1567	*
1568	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1569	*/
1570	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPU pVCpu)
1571	{
1572	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1573	}
1574
1575
1576	/**
1577	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1578	*
1579	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1580	*/
1581	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPU pVCpu)
1582	{
1583	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1584	}
1585
1586
1587	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1588
1589	/**
1590	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1591	*
1592	* @returns VBox status code.
1593	* @param pVM The cross context VM structure.
1594	* @param pVCpu The cross context virtual CPU structure.
1595	* @param pCtx Pointer to the guest CPU context.
1596	*/
1597	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1598	{
1599	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1600	if (pVM->hm.s.vmx.fSupported)
1601	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1602	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1603	}
1604
1605
1606	/**
1607	* Save guest debug state (64 bits guest mode & 32 bits host only)
1608	*
1609	* @returns VBox status code.
1610	* @param pVM The cross context VM structure.
1611	* @param pVCpu The cross context virtual CPU structure.
1612	* @param pCtx Pointer to the guest CPU context.
1613	*/
1614	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1615	{
1616	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1617	if (pVM->hm.s.vmx.fSupported)
1618	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1619	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1620	}
1621
1622
1623	/**
1624	* Test the 32->64 bits switcher.
1625	*
1626	* @returns VBox status code.
1627	* @param pVM The cross context VM structure.
1628	*/
1629	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1630	{
1631	PVMCPU pVCpu = &pVM->aCpus[0];
1632	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1633	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1634	int rc;
1635
1636	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1637	if (pVM->hm.s.vmx.fSupported)
1638	rc = VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1639	else
1640	rc = SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1641	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1642
1643	return rc;
1644	}
1645
1646	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
1647
1648	/**
1649	* Returns suspend status of the host.
1650	*
1651	* @returns Suspend pending or not.
1652	*/
1653	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1654	{
1655	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1656	}
1657
1658
1659	/**
1660	* Invalidates a guest page from the host TLB.
1661	*
1662	* @param pVCpu The cross context virtual CPU structure.
1663	* @param GCVirt Page to invalidate.
1664	*/
1665	VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1666	{
1667	PVM pVM = pVCpu->CTX_SUFF(pVM);
1668	if (pVM->hm.s.vmx.fSupported)
1669	return VMXR0InvalidatePage(pVM, pVCpu, GCVirt);
1670	return SVMR0InvalidatePage(pVM, pVCpu, GCVirt);
1671	}
1672
1673
1674	/**
1675	* Returns the cpu structure for the current cpu.
1676	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1677	*
1678	* @returns The cpu structure pointer.
1679	*/
1680	VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void)
1681	{
1682	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1683	RTCPUID idCpu = RTMpCpuId();
1684	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1685	return &g_HmR0.aCpuInfo[idCpu];
1686	}
1687
1688
1689	/**
1690	* Save a pending IO read.
1691	*
1692	* @param pVCpu The cross context virtual CPU structure.
1693	* @param GCPtrRip Address of IO instruction.
1694	* @param GCPtrRipNext Address of the next instruction.
1695	* @param uPort Port address.
1696	* @param uAndVal AND mask for saving the result in eax.
1697	* @param cbSize Read size.
1698	*/
1699	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1700	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1701	{
1702	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1703	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1704	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1705	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1706	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1707	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1708	return;
1709	}
1710
1711
1712	/**
1713	* Interface for importing state on demand (used by IEM).
1714	*
1715	* @returns VBox status code.
1716	* @param pVCpu The cross context CPU structure.
1717	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1718	*/
1719	VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
1720	{
1721	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1722	return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1723	return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1724	}
1725
1726
1727	#ifdef VBOX_WITH_RAW_MODE
1728
1729	/**
1730	* Raw-mode switcher hook - disable VT-x if it's active and the current
1731	* switcher turns off paging.
1732	*
1733	* @returns VBox status code.
1734	* @param pVM The cross context VM structure.
1735	* @param enmSwitcher The switcher we're about to use.
1736	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1737	*/
1738	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1739	{
1740	NOREF(pVM);
1741
1742	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1743
1744	*pfVTxDisabled = false;
1745
1746	/* No such issues with AMD-V */
1747	if (!g_HmR0.vmx.fSupported)
1748	return VINF_SUCCESS;
1749
1750	/* Check if the switching we're up to is safe. */
1751	switch (enmSwitcher)
1752	{
1753	case VMMSWITCHER_32_TO_32:
1754	case VMMSWITCHER_PAE_TO_PAE:
1755	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1756
1757	case VMMSWITCHER_32_TO_PAE:
1758	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1759	case VMMSWITCHER_AMD64_TO_32:
1760	case VMMSWITCHER_AMD64_TO_PAE:
1761	break; /* unsafe switchers */
1762
1763	default:
1764	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1765	}
1766
1767	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1768	regardless of whether we're currently using VT-x or not. */
1769	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1770	{
1771	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1772	return VINF_SUCCESS;
1773	}
1774
1775	/** @todo Check if this code is presumptive wrt other VT-x users on the
1776	* system... */
1777
1778	/* Nothing to do if we haven't enabled VT-x. */
1779	if (!g_HmR0.fEnabled)
1780	return VINF_SUCCESS;
1781
1782	/* Local init implies the CPU is currently not in VMX root mode. */
1783	if (!g_HmR0.fGlobalInit)
1784	return VINF_SUCCESS;
1785
1786	/* Ok, disable VT-x. */
1787	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
1788	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ && pCpu->pvMemObj && pCpu->HCPhysMemObj != NIL_RTHCPHYS, VERR_HM_IPE_2);
1789
1790	*pfVTxDisabled = true;
1791	return VMXR0DisableCpu(pCpu, pCpu->pvMemObj, pCpu->HCPhysMemObj);
1792	}
1793
1794
1795	/**
1796	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1797	* switcher turned off paging.
1798	*
1799	* @param pVM The cross context VM structure.
1800	* @param fVTxDisabled Whether VT-x was disabled or not.
1801	*/
1802	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1803	{
1804	Assert(!ASMIntAreEnabled());
1805
1806	if (!fVTxDisabled)
1807	return; /* nothing to do */
1808
1809	Assert(g_HmR0.vmx.fSupported);
1810	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1811	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1812	else
1813	{
1814	Assert(g_HmR0.fEnabled);
1815	Assert(g_HmR0.fGlobalInit);
1816
1817	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
1818	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ && pCpu->pvMemObj && pCpu->HCPhysMemObj != NIL_RTHCPHYS);
1819
1820	VMXR0EnableCpu(pCpu, pVM, pCpu->pvMemObj, pCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
1821	}
1822	}
1823
1824	#endif /* VBOX_WITH_RAW_MODE */
1825	#ifdef VBOX_STRICT
1826
1827	/**
1828	* Dumps a descriptor.
1829	*
1830	* @param pDesc Descriptor to dump.
1831	* @param Sel Selector number.
1832	* @param pszMsg Message to prepend the log entry with.
1833	*/
1834	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1835	{
1836	/*
1837	* Make variable description string.
1838	*/
1839	static struct
1840	{
1841	unsigned cch;
1842	const char *psz;
1843	} const s_aTypes[32] =
1844	{
1845	# define STRENTRY(str) { sizeof(str) - 1, str }
1846
1847	/* system */
1848	# if HC_ARCH_BITS == 64
1849	STRENTRY("Reserved0 "), /* 0x00 */
1850	STRENTRY("Reserved1 "), /* 0x01 */
1851	STRENTRY("LDT "), /* 0x02 */
1852	STRENTRY("Reserved3 "), /* 0x03 */
1853	STRENTRY("Reserved4 "), /* 0x04 */
1854	STRENTRY("Reserved5 "), /* 0x05 */
1855	STRENTRY("Reserved6 "), /* 0x06 */
1856	STRENTRY("Reserved7 "), /* 0x07 */
1857	STRENTRY("Reserved8 "), /* 0x08 */
1858	STRENTRY("TSS64Avail "), /* 0x09 */
1859	STRENTRY("ReservedA "), /* 0x0a */
1860	STRENTRY("TSS64Busy "), /* 0x0b */
1861	STRENTRY("Call64 "), /* 0x0c */
1862	STRENTRY("ReservedD "), /* 0x0d */
1863	STRENTRY("Int64 "), /* 0x0e */
1864	STRENTRY("Trap64 "), /* 0x0f */
1865	# else
1866	STRENTRY("Reserved0 "), /* 0x00 */
1867	STRENTRY("TSS16Avail "), /* 0x01 */
1868	STRENTRY("LDT "), /* 0x02 */
1869	STRENTRY("TSS16Busy "), /* 0x03 */
1870	STRENTRY("Call16 "), /* 0x04 */
1871	STRENTRY("Task "), /* 0x05 */
1872	STRENTRY("Int16 "), /* 0x06 */
1873	STRENTRY("Trap16 "), /* 0x07 */
1874	STRENTRY("Reserved8 "), /* 0x08 */
1875	STRENTRY("TSS32Avail "), /* 0x09 */
1876	STRENTRY("ReservedA "), /* 0x0a */
1877	STRENTRY("TSS32Busy "), /* 0x0b */
1878	STRENTRY("Call32 "), /* 0x0c */
1879	STRENTRY("ReservedD "), /* 0x0d */
1880	STRENTRY("Int32 "), /* 0x0e */
1881	STRENTRY("Trap32 "), /* 0x0f */
1882	# endif
1883	/* non system */
1884	STRENTRY("DataRO "), /* 0x10 */
1885	STRENTRY("DataRO Accessed "), /* 0x11 */
1886	STRENTRY("DataRW "), /* 0x12 */
1887	STRENTRY("DataRW Accessed "), /* 0x13 */
1888	STRENTRY("DataDownRO "), /* 0x14 */
1889	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1890	STRENTRY("DataDownRW "), /* 0x16 */
1891	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1892	STRENTRY("CodeEO "), /* 0x18 */
1893	STRENTRY("CodeEO Accessed "), /* 0x19 */
1894	STRENTRY("CodeER "), /* 0x1a */
1895	STRENTRY("CodeER Accessed "), /* 0x1b */
1896	STRENTRY("CodeConfEO "), /* 0x1c */
1897	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1898	STRENTRY("CodeConfER "), /* 0x1e */
1899	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1900	# undef SYSENTRY
1901	};
1902	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1903	char szMsg[128];
1904	char *psz = &szMsg[0];
1905	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1906	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1907	psz += s_aTypes[i].cch;
1908
1909	if (pDesc->Gen.u1Present)
1910	ADD_STR(psz, "Present ");
1911	else
1912	ADD_STR(psz, "Not-Present ");
1913	# if HC_ARCH_BITS == 64
1914	if (pDesc->Gen.u1Long)
1915	ADD_STR(psz, "64-bit ");
1916	else
1917	ADD_STR(psz, "Comp ");
1918	# else
1919	if (pDesc->Gen.u1Granularity)
1920	ADD_STR(psz, "Page ");
1921	if (pDesc->Gen.u1DefBig)
1922	ADD_STR(psz, "32-bit ");
1923	else
1924	ADD_STR(psz, "16-bit ");
1925	# endif
1926	# undef ADD_STR
1927	*psz = '\0';
1928
1929	/*
1930	* Limit and Base and format the output.
1931	*/
1932	#ifdef LOG_ENABLED
1933	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1934
1935	# if HC_ARCH_BITS == 64
1936	uint64_t u32Base = X86DESC64_BASE(pDesc);
1937	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1938	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1939	# else
1940	uint32_t u32Base = X86DESC_BASE(pDesc);
1941	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1942	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1943	# endif
1944	#else
1945	NOREF(Sel); NOREF(pszMsg);
1946	#endif
1947	}
1948
1949
1950	/**
1951	* Formats a full register dump.
1952	*
1953	* @param pVM The cross context VM structure.
1954	* @param pVCpu The cross context virtual CPU structure.
1955	* @param pCtx Pointer to the CPU context.
1956	*/
1957	VMMR0_INT_DECL(void) hmR0DumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1958	{
1959	NOREF(pVM);
1960
1961	/*
1962	* Format the flags.
1963	*/
1964	static struct
1965	{
1966	const char pszSet; const char pszClear; uint32_t fFlag;
1967	} const s_aFlags[] =
1968	{
1969	{ "vip", NULL, X86_EFL_VIP },
1970	{ "vif", NULL, X86_EFL_VIF },
1971	{ "ac", NULL, X86_EFL_AC },
1972	{ "vm", NULL, X86_EFL_VM },
1973	{ "rf", NULL, X86_EFL_RF },
1974	{ "nt", NULL, X86_EFL_NT },
1975	{ "ov", "nv", X86_EFL_OF },
1976	{ "dn", "up", X86_EFL_DF },
1977	{ "ei", "di", X86_EFL_IF },
1978	{ "tf", NULL, X86_EFL_TF },
1979	{ "nt", "pl", X86_EFL_SF },
1980	{ "nz", "zr", X86_EFL_ZF },
1981	{ "ac", "na", X86_EFL_AF },
1982	{ "po", "pe", X86_EFL_PF },
1983	{ "cy", "nc", X86_EFL_CF },
1984	};
1985	char szEFlags[80];
1986	char *psz = szEFlags;
1987	uint32_t uEFlags = pCtx->eflags.u32;
1988	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1989	{
1990	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1991	if (pszAdd)
1992	{
1993	strcpy(psz, pszAdd);
1994	psz += strlen(pszAdd);
1995	*psz++ = ' ';
1996	}
1997	}
1998	psz[-1] = '\0';
1999
2000	/*
2001	* Format the registers.
2002	*/
2003	if (CPUMIsGuestIn64BitCode(pVCpu))
2004	{
2005	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
2006	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
2007	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2008	"r14=%016RX64 r15=%016RX64\n"
2009	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
2010	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2011	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2012	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2013	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2014	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2015	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2016	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
2017	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
2018	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
2019	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2020	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2021	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2022	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2023	,
2024	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
2025	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
2026	pCtx->r14, pCtx->r15,
2027	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
2028	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2029	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2030	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2031	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2032	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2033	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2034	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
2035	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
2036	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2037	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
2038	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2039	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2040	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2041	}
2042	else
2043	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2044	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2045	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2046	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2047	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2048	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2049	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2050	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2051	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2052	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2053	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2054	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2055	,
2056	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2057	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
2058	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2059	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2060	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2061	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2062	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2063	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2064	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
2065	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2066	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2067	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2068
2069	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
2070	Log(("FPU:\n"
2071	"FCW=%04x FSW=%04x FTW=%02x\n"
2072	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2073	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2074	,
2075	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
2076	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
2077	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
2078	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
2079
2080	Log(("MSR:\n"
2081	"EFER =%016RX64\n"
2082	"PAT =%016RX64\n"
2083	"STAR =%016RX64\n"
2084	"CSTAR =%016RX64\n"
2085	"LSTAR =%016RX64\n"
2086	"SFMASK =%016RX64\n"
2087	"KERNELGSBASE =%016RX64\n",
2088	pCtx->msrEFER,
2089	pCtx->msrPAT,
2090	pCtx->msrSTAR,
2091	pCtx->msrCSTAR,
2092	pCtx->msrLSTAR,
2093	pCtx->msrSFMASK,
2094	pCtx->msrKERNELGSBASE));
2095
2096	NOREF(pFpuCtx);
2097	}
2098
2099	#endif /* VBOX_STRICT */
2100

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 72747

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