HMR0.cpp@ 72963

Last change on this file since 72963 was 72907, checked in by vboxsync, 6 years ago
VMM/HMR0: Naming, cleanup nits.
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1	/* $Id: HMR0.cpp 72907 2018-07-05 03:55:29Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/pgm.h>
26	#include "HMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/vmm/hm_vmx.h>
29	#include <VBox/vmm/hm_svm.h>
30	#include <VBox/vmm/gim.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <iprt/assert.h>
34	#include <iprt/asm.h>
35	#include <iprt/asm-amd64-x86.h>
36	#include <iprt/cpuset.h>
37	#include <iprt/mem.h>
38	#include <iprt/memobj.h>
39	#include <iprt/once.h>
40	#include <iprt/param.h>
41	#include <iprt/power.h>
42	#include <iprt/string.h>
43	#include <iprt/thread.h>
44	#include <iprt/x86.h>
45	#include "HMVMXR0.h"
46	#include "HMSVMR0.h"
47
48
49	/*********************************************************************************************************************************
50	* Internal Functions *
51	*********************************************************************************************************************************/
52	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
56	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
57	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
58
59
60	/*********************************************************************************************************************************
61	* Structures and Typedefs *
62	*********************************************************************************************************************************/
63	/**
64	* This is used to manage the status code of a RTMpOnAll in HM.
65	*/
66	typedef struct HMR0FIRSTRC
67	{
68	/** The status code. */
69	int32_t volatile rc;
70	/** The ID of the CPU reporting the first failure. */
71	RTCPUID volatile idCpu;
72	} HMR0FIRSTRC;
73	/** Pointer to a first return code structure. */
74	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
75
76
77	/*********************************************************************************************************************************
78	* Global Variables *
79	*********************************************************************************************************************************/
80	/**
81	* Global data.
82	*/
83	static struct
84	{
85	/** Per CPU globals. */
86	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
87
88	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
89	* @{ */
90	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu));
91	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
92	DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPU pVCpu));
93	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPU pVCpu, PCPUMCTX pCtx));
94	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
95	bool fEnabledByHost, void *pvArg));
96	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
97	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
99	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
100	/** @} */
101
102	/** Maximum ASID allowed. */
103	uint32_t uMaxAsid;
104
105	/** VT-x data. */
106	struct
107	{
108	/** Set to by us to indicate VMX is supported by the CPU. */
109	bool fSupported;
110	/** Whether we're using SUPR0EnableVTx or not. */
111	bool fUsingSUPR0EnableVTx;
112	/** Whether we're using the preemption timer or not. */
113	bool fUsePreemptTimer;
114	/** The shift mask employed by the VMX-Preemption timer. */
115	uint8_t cPreemptTimerShift;
116
117	/** Host CR4 value (set by ring-0 VMX init) */
118	uint64_t u64HostCr4;
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121	/** Host SMM monitor control (used for logging/diagnostics) */
122	uint64_t u64HostSmmMonitorCtl;
123
124	/** VMX MSR values */
125	VMXMSRS Msrs;
126
127	/** Last instruction error. */
128	uint32_t ulLastInstrError;
129
130	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
131	* module termination. */
132	bool fCalledSUPR0EnableVTx;
133	} vmx;
134
135	/** AMD-V information. */
136	struct
137	{
138	/* HWCR MSR (for diagnostics) */
139	uint64_t u64MsrHwcr;
140
141	/** SVM revision. */
142	uint32_t u32Rev;
143
144	/** SVM feature bits from cpuid 0x8000000a */
145	uint32_t u32Features;
146
147	/** Set by us to indicate SVM is supported by the CPU. */
148	bool fSupported;
149	} svm;
150
151	/** Last recorded error code during HM ring-0 init. */
152	int32_t rcInit;
153
154	/** CPUID 0x80000001 ecx:edx features */
155	struct
156	{
157	uint32_t u32AMDFeatureECX;
158	uint32_t u32AMDFeatureEDX;
159	} cpuid;
160
161	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
162	* enabled and disabled each time it's used to execute guest code. */
163	bool fGlobalInit;
164	/** Indicates whether the host is suspending or not. We'll refuse a few
165	* actions when the host is being suspended to speed up the suspending and
166	* avoid trouble. */
167	volatile bool fSuspended;
168
169	/** Whether we've already initialized all CPUs.
170	* @remarks We could check the EnableAllCpusOnce state, but this is
171	* simpler and hopefully easier to understand. */
172	bool fEnabled;
173	/** Serialize initialization in HMR0EnableAllCpus. */
174	RTONCE EnableAllCpusOnce;
175	} g_HmR0;
176
177
178	/**
179	* Initializes a first return code structure.
180	*
181	* @param pFirstRc The structure to init.
182	*/
183	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
184	{
185	pFirstRc->rc = VINF_SUCCESS;
186	pFirstRc->idCpu = NIL_RTCPUID;
187	}
188
189
190	/**
191	* Try set the status code (success ignored).
192	*
193	* @param pFirstRc The first return code structure.
194	* @param rc The status code.
195	*/
196	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
197	{
198	if ( RT_FAILURE(rc)
199	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
200	pFirstRc->idCpu = RTMpCpuId();
201	}
202
203
204	/**
205	* Get the status code of a first return code structure.
206	*
207	* @returns The status code; VINF_SUCCESS or error status, no informational or
208	* warning errors.
209	* @param pFirstRc The first return code structure.
210	*/
211	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
212	{
213	return pFirstRc->rc;
214	}
215
216
217	#ifdef VBOX_STRICT
218	# ifndef DEBUG_bird
219	/**
220	* Get the CPU ID on which the failure status code was reported.
221	*
222	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
223	* @param pFirstRc The first return code structure.
224	*/
225	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
226	{
227	return pFirstRc->idCpu;
228	}
229	# endif
230	#endif /* VBOX_STRICT */
231
232
233	/** @name Dummy callback handlers.
234	* @{ */
235
236	static DECLCALLBACK(int) hmR0DummyEnter(PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu)
237	{
238	RT_NOREF2(pVCpu, pHostCpu);
239	return VINF_SUCCESS;
240	}
241
242	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
243	{
244	RT_NOREF3(enmEvent, pVCpu, fGlobalInit);
245	}
246
247	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
248	bool fEnabledBySystem, void *pvArg)
249	{
250	RT_NOREF6(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pvArg);
251	return VINF_SUCCESS;
252	}
253
254	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
255	{
256	RT_NOREF3(pHostCpu, pvCpuPage, HCPhysCpuPage);
257	return VINF_SUCCESS;
258	}
259
260	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
261	{
262	RT_NOREF1(pVM);
263	return VINF_SUCCESS;
264	}
265
266	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
267	{
268	RT_NOREF1(pVM);
269	return VINF_SUCCESS;
270	}
271
272	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
273	{
274	RT_NOREF1(pVM);
275	return VINF_SUCCESS;
276	}
277
278	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPU pVCpu, PCPUMCTX pCtx)
279	{
280	RT_NOREF2(pVCpu, pCtx);
281	return VINF_SUCCESS;
282	}
283
284	static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPU pVCpu)
285	{
286	RT_NOREF1(pVCpu);
287	return VINF_SUCCESS;
288	}
289
290	/** @} */
291
292
293	/**
294	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
295	* Down at the Rate Specified" erratum.
296	*
297	* Errata names and related steppings:
298	* - BA86 - D0.
299	* - AAX65 - C2.
300	* - AAU65 - C2, K0.
301	* - AAO95 - B1.
302	* - AAT59 - C2.
303	* - AAK139 - D0.
304	* - AAM126 - C0, C1, D0.
305	* - AAN92 - B1.
306	* - AAJ124 - C0, D0.
307	*
308	* - AAP86 - B1.
309	*
310	* Steppings: B1, C0, C1, C2, D0, K0.
311	*
312	* @returns true if subject to it, false if not.
313	*/
314	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
315	{
316	uint32_t u = ASMCpuId_EAX(1);
317	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
318	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
319	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
320	/* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
321	/* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
322	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
323	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
324	/* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
325	/* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
326	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
327	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
328	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
329	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
330	/* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
331	/* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
332	)
333	return true;
334	return false;
335	}
336
337
338	/**
339	* Intel specific initialization code.
340	*
341	* @returns VBox status code (will only fail if out of memory).
342	*/
343	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
344	{
345	/*
346	* Check that all the required VT-x features are present.
347	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
348	*/
349	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
350	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
351	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
352	)
353	{
354	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
355	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
356
357	/*
358	* First try use native kernel API for controlling VT-x.
359	* (This is only supported by some Mac OS X kernels atm.)
360	*/
361	int rc = g_HmR0.rcInit = SUPR0EnableVTx(true /* fEnable */);
362	g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
363	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
364	{
365	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
366	if (RT_SUCCESS(rc))
367	{
368	g_HmR0.vmx.fSupported = true;
369	rc = SUPR0EnableVTx(false /* fEnable */);
370	AssertLogRelRC(rc);
371	}
372	}
373	else
374	{
375	HMR0FIRSTRC FirstRc;
376	hmR0FirstRcInit(&FirstRc);
377	g_HmR0.rcInit = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
378	if (RT_SUCCESS(g_HmR0.rcInit))
379	g_HmR0.rcInit = hmR0FirstRcGetStatus(&FirstRc);
380	}
381	if (RT_SUCCESS(g_HmR0.rcInit))
382	{
383	/* Reread in case it was changed by SUPR0GetVmxUsability(). */
384	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
385
386	/*
387	* Read all relevant registers and MSRs.
388	*/
389	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
390	g_HmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
391	g_HmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
392	/* KVM workaround: Intel SDM section 34.15.5 describes that MSR_IA32_SMM_MONITOR_CTL
393	* depends on bit 49 of MSR_IA32_VMX_BASIC_INFO while table 35-2 says that this MSR
394	* is available if either VMX or SMX is supported. */
395	if (MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(g_HmR0.vmx.Msrs.u64BasicInfo))
396	g_HmR0.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
397	g_HmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
398	g_HmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
399	g_HmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
400	g_HmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
401	g_HmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
402	g_HmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
403	g_HmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
404	g_HmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
405	g_HmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
406	g_HmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
407	/* VPID 16 bits ASID. */
408	g_HmR0.uMaxAsid = 0x10000; /* exclusive */
409
410	if (g_HmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
411	{
412	g_HmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
413	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
414	g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
415
416	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
417	g_HmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
418	}
419
420	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
421	{
422	/*
423	* Enter root mode
424	*/
425	RTR0MEMOBJ hScatchMemObj;
426	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
427	if (RT_FAILURE(rc))
428	{
429	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
430	return rc;
431	}
432
433	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
434	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
435	ASMMemZeroPage(pvScatchPage);
436
437	/* Set revision dword at the beginning of the structure. */
438	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HmR0.vmx.Msrs.u64BasicInfo);
439
440	/* Make sure we don't get rescheduled to another cpu during this probe. */
441	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
442
443	/*
444	* Check CR4.VMXE.
445	*/
446	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
447	if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
448	{
449	/* In theory this bit could be cleared behind our back. Which would cause #UD
450	faults when we try to execute the VMX instructions... */
451	ASMSetCR4(g_HmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
452	}
453
454	/*
455	* The only way of checking if we're in VMX root mode or not is to try and enter it.
456	* There is no instruction or control bit that tells us if we're in VMX root mode.
457	* Therefore, try and enter VMX root mode here.
458	*/
459	rc = VMXEnable(HCPhysScratchPage);
460	if (RT_SUCCESS(rc))
461	{
462	g_HmR0.vmx.fSupported = true;
463	VMXDisable();
464	}
465	else
466	{
467	/*
468	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
469	* it will crash the host when we enter raw mode, because:
470	*
471	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
472	* this bit), and
473	* (b) turning off paging causes a #GP (unavoidable when switching
474	* from long to 32 bits mode or 32 bits to PAE).
475	*
476	* They should fix their code, but until they do we simply refuse to run.
477	*/
478	g_HmR0.rcInit = VERR_VMX_IN_VMX_ROOT_MODE;
479	Assert(g_HmR0.vmx.fSupported == false);
480	}
481
482	/*
483	* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it was not
484	* set before (some software could incorrectly think it is in VMX mode).
485	*/
486	ASMSetCR4(g_HmR0.vmx.u64HostCr4);
487	ASMSetFlags(fEFlags);
488
489	RTR0MemObjFree(hScatchMemObj, false);
490	}
491
492	if (g_HmR0.vmx.fSupported)
493	{
494	rc = VMXR0GlobalInit();
495	if (RT_FAILURE(rc))
496	g_HmR0.rcInit = rc;
497
498	/*
499	* Install the VT-x methods.
500	*/
501	g_HmR0.pfnEnterSession = VMXR0Enter;
502	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
503	g_HmR0.pfnExportHostState = VMXR0ExportHostState;
504	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
505	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
506	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
507	g_HmR0.pfnInitVM = VMXR0InitVM;
508	g_HmR0.pfnTermVM = VMXR0TermVM;
509	g_HmR0.pfnSetupVM = VMXR0SetupVM;
510
511	/*
512	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
513	* Timer Does Not Count Down at the Rate Specified" erratum.
514	*/
515	if (g_HmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
516	{
517	g_HmR0.vmx.fUsePreemptTimer = true;
518	g_HmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HmR0.vmx.Msrs.u64Misc);
519	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
520	g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
521	}
522	}
523	}
524	#ifdef LOG_ENABLED
525	else
526	SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_HmR0.rcInit);
527	#endif
528	}
529	else
530	g_HmR0.rcInit = VERR_VMX_NO_VMX;
531	return VINF_SUCCESS;
532	}
533
534
535	/**
536	* AMD-specific initialization code.
537	*
538	* @returns VBox status code.
539	*/
540	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
541	{
542	/*
543	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
544	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
545	*/
546	int rc;
547	if ( (g_HmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
548	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
549	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
550	&& ASMIsValidExtRange(uMaxExtLeaf)
551	&& uMaxExtLeaf >= 0x8000000a
552	)
553	{
554	/* Call the global AMD-V initialization routine. */
555	rc = SVMR0GlobalInit();
556	if (RT_FAILURE(rc))
557	{
558	g_HmR0.rcInit = rc;
559	return rc;
560	}
561
562	/*
563	* Install the AMD-V methods.
564	*/
565	g_HmR0.pfnEnterSession = SVMR0Enter;
566	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
567	g_HmR0.pfnExportHostState = SVMR0ExportHostState;
568	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
569	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
570	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
571	g_HmR0.pfnInitVM = SVMR0InitVM;
572	g_HmR0.pfnTermVM = SVMR0TermVM;
573	g_HmR0.pfnSetupVM = SVMR0SetupVM;
574
575	/* Query AMD features. */
576	uint32_t u32Dummy;
577	ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
578
579	/*
580	* We need to check if AMD-V has been properly initialized on all CPUs.
581	* Some BIOSes might do a poor job.
582	*/
583	HMR0FIRSTRC FirstRc;
584	hmR0FirstRcInit(&FirstRc);
585	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
586	AssertRC(rc);
587	if (RT_SUCCESS(rc))
588	rc = hmR0FirstRcGetStatus(&FirstRc);
589	#ifndef DEBUG_bird
590	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
591	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
592	#endif
593	if (RT_SUCCESS(rc))
594	{
595	/* Read the HWCR MSR for diagnostics. */
596	g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
597	g_HmR0.svm.fSupported = true;
598	}
599	else
600	{
601	g_HmR0.rcInit = rc;
602	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
603	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
604	}
605	}
606	else
607	{
608	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
609	g_HmR0.rcInit = VERR_SVM_NO_SVM;
610	}
611	return rc;
612	}
613
614
615	/**
616	* Does global Ring-0 HM initialization (at module init).
617	*
618	* @returns VBox status code.
619	*/
620	VMMR0_INT_DECL(int) HMR0Init(void)
621	{
622	/*
623	* Initialize the globals.
624	*/
625	g_HmR0.fEnabled = false;
626	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
627	g_HmR0.EnableAllCpusOnce = s_OnceInit;
628	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
629	{
630	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
631	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
632	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
633	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
634	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
635	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
636	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
637	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
638	#endif
639	}
640
641	/* Fill in all callbacks with placeholders. */
642	g_HmR0.pfnEnterSession = hmR0DummyEnter;
643	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
644	g_HmR0.pfnExportHostState = hmR0DummyExportHostState;
645	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
646	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
647	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
648	g_HmR0.pfnInitVM = hmR0DummyInitVM;
649	g_HmR0.pfnTermVM = hmR0DummyTermVM;
650	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
651
652	/* Default is global VT-x/AMD-V init. */
653	g_HmR0.fGlobalInit = true;
654
655	/*
656	* Make sure aCpuInfo is big enough for all the CPUs on this system.
657	*/
658	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
659	{
660	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
661	return VERR_TOO_MANY_CPUS;
662	}
663
664	/*
665	* Check for VT-x and AMD-V capabilities.
666	*/
667	int rc;
668	if (ASMHasCpuId())
669	{
670	/* Standard features. */
671	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
672	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
673	if (ASMIsValidStdRange(uMaxLeaf))
674	{
675	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
676	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
677
678	/* Query AMD features. */
679	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
680	if (ASMIsValidExtRange(uMaxExtLeaf))
681	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
682	&g_HmR0.cpuid.u32AMDFeatureECX,
683	&g_HmR0.cpuid.u32AMDFeatureEDX);
684	else
685	g_HmR0.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureEDX = 0;
686
687	/* Go to CPU specific initialization code. */
688	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
689	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
690	{
691	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
692	if (RT_FAILURE(rc))
693	return rc;
694	}
695	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
696	{
697	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
698	if (RT_FAILURE(rc))
699	return rc;
700	}
701	else
702	g_HmR0.rcInit = VERR_HM_UNKNOWN_CPU;
703	}
704	else
705	g_HmR0.rcInit = VERR_HM_UNKNOWN_CPU;
706	}
707	else
708	g_HmR0.rcInit = VERR_HM_NO_CPUID;
709
710	/*
711	* Register notification callbacks that we can use to disable/enable CPUs
712	* when brought offline/online or suspending/resuming.
713	*/
714	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
715	{
716	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
717	AssertRC(rc);
718
719	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
720	AssertRC(rc);
721	}
722
723	/* We return success here because module init shall not fail if HM
724	fails to initialize. */
725	return VINF_SUCCESS;
726	}
727
728
729	/**
730	* Does global Ring-0 HM termination (at module termination).
731	*
732	* @returns VBox status code.
733	*/
734	VMMR0_INT_DECL(int) HMR0Term(void)
735	{
736	int rc;
737	if ( g_HmR0.vmx.fSupported
738	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
739	{
740	/*
741	* Simple if the host OS manages VT-x.
742	*/
743	Assert(g_HmR0.fGlobalInit);
744
745	if (g_HmR0.vmx.fCalledSUPR0EnableVTx)
746	{
747	rc = SUPR0EnableVTx(false /* fEnable */);
748	g_HmR0.vmx.fCalledSUPR0EnableVTx = false;
749	}
750	else
751	rc = VINF_SUCCESS;
752
753	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
754	{
755	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
756	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
757	}
758	}
759	else
760	{
761	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
762
763	/* Doesn't really matter if this fails. */
764	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
765	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
766
767	/*
768	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
769	*/
770	if (g_HmR0.fGlobalInit)
771	{
772	HMR0FIRSTRC FirstRc;
773	hmR0FirstRcInit(&FirstRc);
774	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
775	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
776	if (RT_SUCCESS(rc))
777	rc = hmR0FirstRcGetStatus(&FirstRc);
778	}
779
780	/*
781	* Free the per-cpu pages used for VT-x and AMD-V.
782	*/
783	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
784	{
785	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
786	{
787	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
788	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
789	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
790	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
791	}
792	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
793	if (g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
794	{
795	RTR0MemObjFree(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, false);
796	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
797	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
798	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
799	}
800	#endif
801	}
802	}
803
804	/** @todo This needs cleaning up. There's no matching
805	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
806	* should move into their respective modules. */
807	/* Finally, call global VT-x/AMD-V termination. */
808	if (g_HmR0.vmx.fSupported)
809	VMXR0GlobalTerm();
810	else if (g_HmR0.svm.fSupported)
811	SVMR0GlobalTerm();
812
813	return rc;
814	}
815
816
817	/**
818	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
819	* on a CPU.
820	*
821	* @param idCpu The identifier for the CPU the function is called on.
822	* @param pvUser1 Pointer to the first RC structure.
823	* @param pvUser2 Ignored.
824	*/
825	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
826	{
827	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
828	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
829	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
830	NOREF(idCpu); NOREF(pvUser2);
831
832	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
833	hmR0FirstRcSetStatus(pFirstRc, rc);
834	}
835
836
837	/**
838	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
839	* on a CPU.
840	*
841	* @param idCpu The identifier for the CPU the function is called on.
842	* @param pvUser1 Pointer to the first RC structure.
843	* @param pvUser2 Ignored.
844	*/
845	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
846	{
847	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
848	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
849	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
850	NOREF(idCpu); NOREF(pvUser2);
851
852	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
853	hmR0FirstRcSetStatus(pFirstRc, rc);
854	}
855
856
857	/**
858	* Enable VT-x or AMD-V on the current CPU
859	*
860	* @returns VBox status code.
861	* @param pVM The cross context VM structure. Can be NULL.
862	* @param idCpu The identifier for the CPU the function is called on.
863	*
864	* @remarks Maybe called with interrupts disabled!
865	*/
866	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
867	{
868	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
869
870	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
871	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
872	Assert(!pHostCpu->fConfigured);
873	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
874
875	pHostCpu->idCpu = idCpu;
876	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
877
878	int rc;
879	if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
880	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
881	else
882	{
883	AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
884	if (g_HmR0.vmx.fSupported)
885	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
886	else
887	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, NULL /* pvArg */);
888	}
889	if (RT_SUCCESS(rc))
890	pHostCpu->fConfigured = true;
891
892	return rc;
893	}
894
895
896	/**
897	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
898	*
899	* @param idCpu The identifier for the CPU the function is called on.
900	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
901	* @param pvUser2 The 2nd user argument.
902	*/
903	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
904	{
905	PVM pVM = (PVM)pvUser1; /* can be NULL! */
906	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
907	AssertReturnVoid(g_HmR0.fGlobalInit);
908	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
909	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
910	}
911
912
913	/**
914	* RTOnce callback employed by HMR0EnableAllCpus.
915	*
916	* @returns VBox status code.
917	* @param pvUser Pointer to the VM.
918	*/
919	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
920	{
921	PVM pVM = (PVM)pvUser;
922
923	/*
924	* Indicate that we've initialized.
925	*
926	* Note! There is a potential race between this function and the suspend
927	* notification. Kind of unlikely though, so ignored for now.
928	*/
929	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
930	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
931
932	/*
933	* The global init variable is set by the first VM.
934	*/
935	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
936
937	#ifdef VBOX_STRICT
938	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
939	{
940	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
941	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
942	Assert(g_HmR0.aCpuInfo[i].pvMemObj == NULL);
943	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
944	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
945	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
946	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
947	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
948	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
949	Assert(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
950	# endif
951	}
952	#endif
953
954	int rc;
955	if ( g_HmR0.vmx.fSupported
956	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
957	{
958	/*
959	* Global VT-x initialization API (only darwin for now).
960	*/
961	rc = SUPR0EnableVTx(true /* fEnable */);
962	if (RT_SUCCESS(rc))
963	{
964	g_HmR0.vmx.fCalledSUPR0EnableVTx = true;
965	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
966	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
967	}
968	else
969	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
970	}
971	else
972	{
973	/*
974	* We're doing the job ourselves.
975	*/
976	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
977	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
978	{
979	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
980	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
981	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
982	#endif
983	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
984	{
985	/** @todo NUMA */
986	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
987	AssertLogRelRCReturn(rc, rc);
988
989	g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
990	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
991	Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
992
993	g_HmR0.aCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
994	AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
995	ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
996
997	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
998	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
999	false /* executable R0 mapping */);
1000	AssertLogRelRCReturn(rc, rc);
1001
1002	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, 0);
1003	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
1004	Assert(!(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
1005
1006	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm);
1007	AssertPtr(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm);
1008	ASMMemFill32(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
1009	#endif
1010	}
1011	}
1012
1013	rc = VINF_SUCCESS;
1014	}
1015
1016	if ( RT_SUCCESS(rc)
1017	&& g_HmR0.fGlobalInit)
1018	{
1019	/* First time, so initialize each cpu/core. */
1020	HMR0FIRSTRC FirstRc;
1021	hmR0FirstRcInit(&FirstRc);
1022	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1023	if (RT_SUCCESS(rc))
1024	rc = hmR0FirstRcGetStatus(&FirstRc);
1025	}
1026
1027	return rc;
1028	}
1029
1030
1031	/**
1032	* Sets up HM on all cpus.
1033	*
1034	* @returns VBox status code.
1035	* @param pVM The cross context VM structure.
1036	*/
1037	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1038	{
1039	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1040	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1041	return VERR_HM_SUSPEND_PENDING;
1042
1043	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1044	}
1045
1046
1047	/**
1048	* Disable VT-x or AMD-V on the current CPU.
1049	*
1050	* @returns VBox status code.
1051	* @param idCpu The identifier for the CPU this function is called on.
1052	*
1053	* @remarks Must be called with preemption disabled.
1054	*/
1055	static int hmR0DisableCpu(RTCPUID idCpu)
1056	{
1057	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1058
1059	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1060	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1061	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1062	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1063	Assert(!pHostCpu->fConfigured \|\| pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
1064	AssertRelease(idCpu == RTMpCpuId());
1065
1066	if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
1067	return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1068	AssertPtr(pHostCpu->pvMemObj);
1069	Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
1070
1071	int rc;
1072	if (pHostCpu->fConfigured)
1073	{
1074	rc = g_HmR0.pfnDisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
1075	AssertRCReturn(rc, rc);
1076
1077	pHostCpu->fConfigured = false;
1078	pHostCpu->idCpu = NIL_RTCPUID;
1079	}
1080	else
1081	rc = VINF_SUCCESS; /* nothing to do */
1082	return rc;
1083	}
1084
1085
1086	/**
1087	* Worker function passed to RTMpOnAll() that is to be called on the target
1088	* CPUs.
1089	*
1090	* @param idCpu The identifier for the CPU the function is called on.
1091	* @param pvUser1 The 1st user argument.
1092	* @param pvUser2 Opaque pointer to the FirstRc.
1093	*/
1094	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1095	{
1096	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1097	AssertReturnVoid(g_HmR0.fGlobalInit);
1098	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1099	}
1100
1101
1102	/**
1103	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1104	* CPU.
1105	*
1106	* @param idCpu The identifier for the CPU the function is called on.
1107	* @param pvUser1 Null, not used.
1108	* @param pvUser2 Null, not used.
1109	*/
1110	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1111	{
1112	NOREF(pvUser1);
1113	NOREF(pvUser2);
1114	hmR0DisableCpu(idCpu);
1115	}
1116
1117
1118	/**
1119	* Callback function invoked when a cpu goes online or offline.
1120	*
1121	* @param enmEvent The Mp event.
1122	* @param idCpu The identifier for the CPU the function is called on.
1123	* @param pvData Opaque data (PVM pointer).
1124	*/
1125	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1126	{
1127	NOREF(pvData);
1128	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1129
1130	/*
1131	* We only care about uninitializing a CPU that is going offline. When a
1132	* CPU comes online, the initialization is done lazily in HMR0Enter().
1133	*/
1134	switch (enmEvent)
1135	{
1136	case RTMPEVENT_OFFLINE:
1137	{
1138	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1139	RTThreadPreemptDisable(&PreemptState);
1140	if (idCpu == RTMpCpuId())
1141	{
1142	int rc = hmR0DisableCpu(idCpu);
1143	AssertRC(rc);
1144	RTThreadPreemptRestore(&PreemptState);
1145	}
1146	else
1147	{
1148	RTThreadPreemptRestore(&PreemptState);
1149	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1150	}
1151	break;
1152	}
1153
1154	default:
1155	break;
1156	}
1157	}
1158
1159
1160	/**
1161	* Called whenever a system power state change occurs.
1162	*
1163	* @param enmEvent The Power event.
1164	* @param pvUser User argument.
1165	*/
1166	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1167	{
1168	NOREF(pvUser);
1169	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1170
1171	#ifdef LOG_ENABLED
1172	if (enmEvent == RTPOWEREVENT_SUSPEND)
1173	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1174	else
1175	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1176	#endif
1177
1178	if (enmEvent == RTPOWEREVENT_SUSPEND)
1179	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1180
1181	if (g_HmR0.fEnabled)
1182	{
1183	int rc;
1184	HMR0FIRSTRC FirstRc;
1185	hmR0FirstRcInit(&FirstRc);
1186
1187	if (enmEvent == RTPOWEREVENT_SUSPEND)
1188	{
1189	if (g_HmR0.fGlobalInit)
1190	{
1191	/* Turn off VT-x or AMD-V on all CPUs. */
1192	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1193	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1194	}
1195	/* else nothing to do here for the local init case */
1196	}
1197	else
1198	{
1199	/* Reinit the CPUs from scratch as the suspend state might have
1200	messed with the MSRs. (lousy BIOSes as usual) */
1201	if (g_HmR0.vmx.fSupported)
1202	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1203	else
1204	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1205	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1206	if (RT_SUCCESS(rc))
1207	rc = hmR0FirstRcGetStatus(&FirstRc);
1208	#ifdef LOG_ENABLED
1209	if (RT_FAILURE(rc))
1210	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1211	#endif
1212	if (g_HmR0.fGlobalInit)
1213	{
1214	/* Turn VT-x or AMD-V back on on all CPUs. */
1215	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1216	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1217	}
1218	/* else nothing to do here for the local init case */
1219	}
1220	}
1221
1222	if (enmEvent == RTPOWEREVENT_RESUME)
1223	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1224	}
1225
1226
1227	/**
1228	* Does ring-0 per-VM HM initialization.
1229	*
1230	* This will copy HM global into the VM structure and call the CPU specific
1231	* init routine which will allocate resources for each virtual CPU and such.
1232	*
1233	* @returns VBox status code.
1234	* @param pVM The cross context VM structure.
1235	*
1236	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1237	* vmR3InitRing3().
1238	*/
1239	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1240	{
1241	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1242
1243	#ifdef LOG_ENABLED
1244	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1245	#endif
1246
1247	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1248	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1249	return VERR_HM_SUSPEND_PENDING;
1250
1251	/*
1252	* Copy globals to the VM structure.
1253	*/
1254	pVM->hm.s.vmx.fSupported = g_HmR0.vmx.fSupported;
1255	pVM->hm.s.svm.fSupported = g_HmR0.svm.fSupported;
1256
1257	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1258	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.vmx.cPreemptTimerShift;
1259	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.vmx.u64HostCr4;
1260	pVM->hm.s.vmx.u64HostEfer = g_HmR0.vmx.u64HostEfer;
1261	pVM->hm.s.vmx.u64HostSmmMonitorCtl = g_HmR0.vmx.u64HostSmmMonitorCtl;
1262	pVM->hm.s.vmx.Msrs = g_HmR0.vmx.Msrs;
1263	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.svm.u64MsrHwcr;
1264	pVM->hm.s.svm.u32Rev = g_HmR0.svm.u32Rev;
1265	pVM->hm.s.svm.u32Features = g_HmR0.svm.u32Features;
1266	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureECX;
1267	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HmR0.cpuid.u32AMDFeatureEDX;
1268	pVM->hm.s.rcInit = g_HmR0.rcInit;
1269	pVM->hm.s.uMaxAsid = g_HmR0.uMaxAsid;
1270
1271	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1272	{
1273	pVM->hm.s.cMaxResumeLoops = 1024;
1274	if (RTThreadPreemptIsPendingTrusty())
1275	pVM->hm.s.cMaxResumeLoops = 8192;
1276	}
1277
1278	/*
1279	* Initialize some per-VCPU fields.
1280	*/
1281	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1282	{
1283	PVMCPU pVCpu = &pVM->aCpus[i];
1284	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1285	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1286	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1287
1288	/* We'll aways increment this the first time (host uses ASID 0). */
1289	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1290	}
1291
1292	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1293
1294	/*
1295	* Call the hardware specific initialization method.
1296	*/
1297	return g_HmR0.pfnInitVM(pVM);
1298	}
1299
1300
1301	/**
1302	* Does ring-0 per VM HM termination.
1303	*
1304	* @returns VBox status code.
1305	* @param pVM The cross context VM structure.
1306	*/
1307	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1308	{
1309	Log(("HMR0TermVM: %p\n", pVM));
1310	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1311
1312	/*
1313	* Call the hardware specific method.
1314	*
1315	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1316	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1317	*/
1318	return g_HmR0.pfnTermVM(pVM);
1319	}
1320
1321
1322	/**
1323	* Sets up a VT-x or AMD-V session.
1324	*
1325	* This is mostly about setting up the hardware VM state.
1326	*
1327	* @returns VBox status code.
1328	* @param pVM The cross context VM structure.
1329	*/
1330	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1331	{
1332	Log(("HMR0SetupVM: %p\n", pVM));
1333	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1334
1335	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1336	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1337
1338	/* On first entry we'll sync everything. */
1339	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1340	{
1341	PVMCPU pVCpu = &pVM->aCpus[i];
1342	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1343	}
1344
1345	/*
1346	* Call the hardware specific setup VM method. This requires the CPU to be
1347	* enabled for AMD-V/VT-x and preemption to be prevented.
1348	*/
1349	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1350	RTThreadPreemptDisable(&PreemptState);
1351	RTCPUID const idCpu = RTMpCpuId();
1352
1353	/* Enable VT-x or AMD-V if local init is required. */
1354	int rc;
1355	if (!g_HmR0.fGlobalInit)
1356	{
1357	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1358	rc = hmR0EnableCpu(pVM, idCpu);
1359	if (RT_FAILURE(rc))
1360	{
1361	RTThreadPreemptRestore(&PreemptState);
1362	return rc;
1363	}
1364	}
1365
1366	/* Setup VT-x or AMD-V. */
1367	rc = g_HmR0.pfnSetupVM(pVM);
1368
1369	/* Disable VT-x or AMD-V if local init was done before. */
1370	if (!g_HmR0.fGlobalInit)
1371	{
1372	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1373	int rc2 = hmR0DisableCpu(idCpu);
1374	AssertRC(rc2);
1375	}
1376
1377	RTThreadPreemptRestore(&PreemptState);
1378	return rc;
1379	}
1380
1381
1382	/**
1383	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1384	* required for entering HM context.
1385	*
1386	* @returns VBox status code.
1387	* @param pVCpu The cross context virtual CPU structure.
1388	*
1389	* @remarks No-long-jump zone!!!
1390	*/
1391	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu)
1392	{
1393	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1394
1395	int rc = VINF_SUCCESS;
1396	RTCPUID const idCpu = RTMpCpuId();
1397	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1398	AssertPtr(pHostCpu);
1399
1400	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1401	if (!pHostCpu->fConfigured)
1402	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1403
1404	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1405	if (g_HmR0.vmx.fSupported)
1406	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1407	else
1408	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1409
1410	Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
1411	pVCpu->hm.s.idEnteredCpu = idCpu;
1412	return rc;
1413	}
1414
1415
1416	/**
1417	* Enters the VT-x or AMD-V session.
1418	*
1419	* @returns VBox status code.
1420	* @param pVCpu The cross context virtual CPU structure.
1421	*
1422	* @remarks This is called with preemption disabled.
1423	*/
1424	VMMR0_INT_DECL(int) HMR0Enter(PVMCPU pVCpu)
1425	{
1426	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1427	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1428	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1429
1430	/* Load the bare minimum state required for entering HM. */
1431	int rc = hmR0EnterCpu(pVCpu);
1432	AssertRCReturn(rc, rc);
1433
1434	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1435	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1436	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1437	#endif
1438
1439	RTCPUID const idCpu = RTMpCpuId();
1440	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1441	Assert(pHostCpu);
1442	if (g_HmR0.vmx.fSupported)
1443	{
1444	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1445	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1446	}
1447	else
1448	{
1449	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1450	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1451	}
1452
1453	rc = g_HmR0.pfnEnterSession(pVCpu, pHostCpu);
1454	AssertMsgRCReturn(rc, ("rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1455
1456	/* Exports the host-state as we may be resuming code after a longjmp and quite
1457	possibly now be scheduled on a different CPU. */
1458	rc = g_HmR0.pfnExportHostState(pVCpu);
1459	AssertMsgRCReturn(rc, ("rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1460
1461	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1462	if (fStartedSet)
1463	PGMRZDynMapReleaseAutoSet(pVCpu);
1464	#endif
1465
1466	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1467	if (RT_FAILURE(rc))
1468	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1469	return rc;
1470	}
1471
1472
1473	/**
1474	* Deinitializes the bare minimum state used for HM context and if necessary
1475	* disable HM on the CPU.
1476	*
1477	* @returns VBox status code.
1478	* @param pVCpu The cross context virtual CPU structure.
1479	*
1480	* @remarks No-long-jump zone!!!
1481	*/
1482	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1483	{
1484	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1485	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1486
1487	RTCPUID const idCpu = RTMpCpuId();
1488	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1489
1490	if ( !g_HmR0.fGlobalInit
1491	&& pHostCpu->fConfigured)
1492	{
1493	int rc = hmR0DisableCpu(idCpu);
1494	AssertRCReturn(rc, rc);
1495	Assert(!pHostCpu->fConfigured);
1496	Assert(pHostCpu->idCpu == NIL_RTCPUID);
1497
1498	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1499	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1500	}
1501
1502	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1503	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1504
1505	return VINF_SUCCESS;
1506	}
1507
1508
1509	/**
1510	* Thread-context hook for HM.
1511	*
1512	* @param enmEvent The thread-context event.
1513	* @param pvUser Opaque pointer to the VMCPU.
1514	*/
1515	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1516	{
1517	PVMCPU pVCpu = (PVMCPU)pvUser;
1518	Assert(pVCpu);
1519	Assert(g_HmR0.pfnThreadCtxCallback);
1520
1521	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1522	}
1523
1524
1525	/**
1526	* Runs guest code in a hardware accelerated VM.
1527	*
1528	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1529	* called from setjmp assembly.)
1530	* @param pVM The cross context VM structure.
1531	* @param pVCpu The cross context virtual CPU structure.
1532	*
1533	* @remarks Can be called with preemption enabled if thread-context hooks are
1534	* used!!!
1535	*/
1536	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1537	{
1538	RT_NOREF(pVM);
1539
1540	#ifdef VBOX_STRICT
1541	/* With thread-context hooks we would be running this code with preemption enabled. */
1542	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1543	{
1544	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1545	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1546	Assert(pHostCpu->fConfigured);
1547	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1548	}
1549	#endif
1550
1551	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1552	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1553	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1554	PGMRZDynMapStartAutoSet(pVCpu);
1555	#endif
1556
1557	VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVCpu, &pVCpu->cpum.GstCtx);
1558
1559	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1560	PGMRZDynMapReleaseAutoSet(pVCpu);
1561	#endif
1562	return VBOXSTRICTRC_VAL(rcStrict);
1563	}
1564
1565
1566	/**
1567	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1568	* the host CPU and that guest access to it must be intercepted.
1569	*
1570	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1571	*/
1572	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPU pVCpu)
1573	{
1574	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1575	}
1576
1577
1578	/**
1579	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1580	*
1581	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1582	*/
1583	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPU pVCpu)
1584	{
1585	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1586	}
1587
1588
1589	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1590
1591	/**
1592	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1593	*
1594	* @returns VBox status code.
1595	* @param pVM The cross context VM structure.
1596	* @param pVCpu The cross context virtual CPU structure.
1597	* @param pCtx Pointer to the guest CPU context.
1598	*/
1599	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1600	{
1601	RT_NOREF(pCtx);
1602	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1603	if (pVM->hm.s.vmx.fSupported)
1604	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1605	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1606	}
1607
1608
1609	/**
1610	* Save guest debug state (64 bits guest mode & 32 bits host only)
1611	*
1612	* @returns VBox status code.
1613	* @param pVM The cross context VM structure.
1614	* @param pVCpu The cross context virtual CPU structure.
1615	* @param pCtx Pointer to the guest CPU context.
1616	*/
1617	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1618	{
1619	RT_NOREF(pCtx);
1620	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1621	if (pVM->hm.s.vmx.fSupported)
1622	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1623	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1624	}
1625
1626
1627	/**
1628	* Test the 32->64 bits switcher.
1629	*
1630	* @returns VBox status code.
1631	* @param pVM The cross context VM structure.
1632	*/
1633	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1634	{
1635	PVMCPU pVCpu = &pVM->aCpus[0];
1636	uint32_t aParam[5] = { 0, 1, 2, 3, 4 };
1637	int rc;
1638
1639	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1640	if (pVM->hm.s.vmx.fSupported)
1641	rc = VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1642	else
1643	rc = SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1644	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1645
1646	return rc;
1647	}
1648
1649	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
1650
1651	/**
1652	* Returns suspend status of the host.
1653	*
1654	* @returns Suspend pending or not.
1655	*/
1656	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1657	{
1658	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1659	}
1660
1661
1662	/**
1663	* Invalidates a guest page from the host TLB.
1664	*
1665	* @param pVCpu The cross context virtual CPU structure.
1666	* @param GCVirt Page to invalidate.
1667	*/
1668	VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1669	{
1670	PVM pVM = pVCpu->CTX_SUFF(pVM);
1671	if (pVM->hm.s.vmx.fSupported)
1672	return VMXR0InvalidatePage(pVCpu, GCVirt);
1673	return SVMR0InvalidatePage(pVCpu, GCVirt);
1674	}
1675
1676
1677	/**
1678	* Returns the cpu structure for the current cpu.
1679	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1680	*
1681	* @returns The cpu structure pointer.
1682	*/
1683	VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void)
1684	{
1685	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1686	RTCPUID const idCpu = RTMpCpuId();
1687	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1688	return &g_HmR0.aCpuInfo[idCpu];
1689	}
1690
1691
1692	/**
1693	* Save a pending IO read.
1694	*
1695	* @param pVCpu The cross context virtual CPU structure.
1696	* @param GCPtrRip Address of IO instruction.
1697	* @param GCPtrRipNext Address of the next instruction.
1698	* @param uPort Port address.
1699	* @param uAndVal AND mask for saving the result in eax.
1700	* @param cbSize Read size.
1701	*/
1702	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1703	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1704	{
1705	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1706	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1707	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1708	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1709	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1710	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1711	return;
1712	}
1713
1714
1715	/**
1716	* Interface for importing state on demand (used by IEM).
1717	*
1718	* @returns VBox status code.
1719	* @param pVCpu The cross context CPU structure.
1720	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1721	*/
1722	VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
1723	{
1724	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1725	return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1726	return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1727	}
1728
1729
1730	#ifdef VBOX_WITH_RAW_MODE
1731	/**
1732	* Raw-mode switcher hook - disable VT-x if it's active and the current
1733	* switcher turns off paging.
1734	*
1735	* @returns VBox status code.
1736	* @param pVM The cross context VM structure.
1737	* @param enmSwitcher The switcher we're about to use.
1738	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1739	*/
1740	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1741	{
1742	NOREF(pVM);
1743
1744	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1745
1746	*pfVTxDisabled = false;
1747
1748	/* No such issues with AMD-V */
1749	if (!g_HmR0.vmx.fSupported)
1750	return VINF_SUCCESS;
1751
1752	/* Check if the switching we're up to is safe. */
1753	switch (enmSwitcher)
1754	{
1755	case VMMSWITCHER_32_TO_32:
1756	case VMMSWITCHER_PAE_TO_PAE:
1757	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1758
1759	case VMMSWITCHER_32_TO_PAE:
1760	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1761	case VMMSWITCHER_AMD64_TO_32:
1762	case VMMSWITCHER_AMD64_TO_PAE:
1763	break; /* unsafe switchers */
1764
1765	default:
1766	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1767	}
1768
1769	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1770	regardless of whether we're currently using VT-x or not. */
1771	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1772	{
1773	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1774	return VINF_SUCCESS;
1775	}
1776
1777	/** @todo Check if this code is presumptive wrt other VT-x users on the
1778	* system... */
1779
1780	/* Nothing to do if we haven't enabled VT-x. */
1781	if (!g_HmR0.fEnabled)
1782	return VINF_SUCCESS;
1783
1784	/* Local init implies the CPU is currently not in VMX root mode. */
1785	if (!g_HmR0.fGlobalInit)
1786	return VINF_SUCCESS;
1787
1788	/* Ok, disable VT-x. */
1789	PHMGLOBALCPUINFO pHostCpu = hmR0GetCurrentCpu();
1790	AssertReturn( pHostCpu
1791	&& pHostCpu->hMemObj != NIL_RTR0MEMOBJ
1792	&& pHostCpu->pvMemObj
1793	&& pHostCpu->HCPhysMemObj != NIL_RTHCPHYS,
1794	VERR_HM_IPE_2);
1795
1796	*pfVTxDisabled = true;
1797	return VMXR0DisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
1798	}
1799
1800
1801	/**
1802	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1803	* switcher turned off paging.
1804	*
1805	* @param pVM The cross context VM structure.
1806	* @param fVTxDisabled Whether VT-x was disabled or not.
1807	*/
1808	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1809	{
1810	Assert(!ASMIntAreEnabled());
1811
1812	if (!fVTxDisabled)
1813	return; /* nothing to do */
1814
1815	Assert(g_HmR0.vmx.fSupported);
1816	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1817	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1818	else
1819	{
1820	Assert(g_HmR0.fEnabled);
1821	Assert(g_HmR0.fGlobalInit);
1822
1823	PHMGLOBALCPUINFO pHostCpu = hmR0GetCurrentCpu();
1824	AssertReturnVoid( pHostCpu
1825	&& pHostCpu->hMemObj != NIL_RTR0MEMOBJ
1826	&& pHostCpu->pvMemObj
1827	&& pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
1828
1829	VMXR0EnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
1830	}
1831	}
1832	#endif /* VBOX_WITH_RAW_MODE */
1833
1834
1835	#ifdef VBOX_STRICT
1836	/**
1837	* Dumps a descriptor.
1838	*
1839	* @param pDesc Descriptor to dump.
1840	* @param Sel Selector number.
1841	* @param pszMsg Message to prepend the log entry with.
1842	*/
1843	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1844	{
1845	/*
1846	* Make variable description string.
1847	*/
1848	static struct
1849	{
1850	unsigned cch;
1851	const char *psz;
1852	} const s_aTypes[32] =
1853	{
1854	# define STRENTRY(str) { sizeof(str) - 1, str }
1855
1856	/* system */
1857	# if HC_ARCH_BITS == 64
1858	STRENTRY("Reserved0 "), /* 0x00 */
1859	STRENTRY("Reserved1 "), /* 0x01 */
1860	STRENTRY("LDT "), /* 0x02 */
1861	STRENTRY("Reserved3 "), /* 0x03 */
1862	STRENTRY("Reserved4 "), /* 0x04 */
1863	STRENTRY("Reserved5 "), /* 0x05 */
1864	STRENTRY("Reserved6 "), /* 0x06 */
1865	STRENTRY("Reserved7 "), /* 0x07 */
1866	STRENTRY("Reserved8 "), /* 0x08 */
1867	STRENTRY("TSS64Avail "), /* 0x09 */
1868	STRENTRY("ReservedA "), /* 0x0a */
1869	STRENTRY("TSS64Busy "), /* 0x0b */
1870	STRENTRY("Call64 "), /* 0x0c */
1871	STRENTRY("ReservedD "), /* 0x0d */
1872	STRENTRY("Int64 "), /* 0x0e */
1873	STRENTRY("Trap64 "), /* 0x0f */
1874	# else
1875	STRENTRY("Reserved0 "), /* 0x00 */
1876	STRENTRY("TSS16Avail "), /* 0x01 */
1877	STRENTRY("LDT "), /* 0x02 */
1878	STRENTRY("TSS16Busy "), /* 0x03 */
1879	STRENTRY("Call16 "), /* 0x04 */
1880	STRENTRY("Task "), /* 0x05 */
1881	STRENTRY("Int16 "), /* 0x06 */
1882	STRENTRY("Trap16 "), /* 0x07 */
1883	STRENTRY("Reserved8 "), /* 0x08 */
1884	STRENTRY("TSS32Avail "), /* 0x09 */
1885	STRENTRY("ReservedA "), /* 0x0a */
1886	STRENTRY("TSS32Busy "), /* 0x0b */
1887	STRENTRY("Call32 "), /* 0x0c */
1888	STRENTRY("ReservedD "), /* 0x0d */
1889	STRENTRY("Int32 "), /* 0x0e */
1890	STRENTRY("Trap32 "), /* 0x0f */
1891	# endif
1892	/* non system */
1893	STRENTRY("DataRO "), /* 0x10 */
1894	STRENTRY("DataRO Accessed "), /* 0x11 */
1895	STRENTRY("DataRW "), /* 0x12 */
1896	STRENTRY("DataRW Accessed "), /* 0x13 */
1897	STRENTRY("DataDownRO "), /* 0x14 */
1898	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1899	STRENTRY("DataDownRW "), /* 0x16 */
1900	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1901	STRENTRY("CodeEO "), /* 0x18 */
1902	STRENTRY("CodeEO Accessed "), /* 0x19 */
1903	STRENTRY("CodeER "), /* 0x1a */
1904	STRENTRY("CodeER Accessed "), /* 0x1b */
1905	STRENTRY("CodeConfEO "), /* 0x1c */
1906	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1907	STRENTRY("CodeConfER "), /* 0x1e */
1908	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1909	# undef SYSENTRY
1910	};
1911	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1912	char szMsg[128];
1913	char *psz = &szMsg[0];
1914	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1915	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1916	psz += s_aTypes[i].cch;
1917
1918	if (pDesc->Gen.u1Present)
1919	ADD_STR(psz, "Present ");
1920	else
1921	ADD_STR(psz, "Not-Present ");
1922	# if HC_ARCH_BITS == 64
1923	if (pDesc->Gen.u1Long)
1924	ADD_STR(psz, "64-bit ");
1925	else
1926	ADD_STR(psz, "Comp ");
1927	# else
1928	if (pDesc->Gen.u1Granularity)
1929	ADD_STR(psz, "Page ");
1930	if (pDesc->Gen.u1DefBig)
1931	ADD_STR(psz, "32-bit ");
1932	else
1933	ADD_STR(psz, "16-bit ");
1934	# endif
1935	# undef ADD_STR
1936	*psz = '\0';
1937
1938	/*
1939	* Limit and Base and format the output.
1940	*/
1941	#ifdef LOG_ENABLED
1942	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1943
1944	# if HC_ARCH_BITS == 64
1945	uint64_t u32Base = X86DESC64_BASE(pDesc);
1946	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1947	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1948	# else
1949	uint32_t u32Base = X86DESC_BASE(pDesc);
1950	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1951	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1952	# endif
1953	#else
1954	NOREF(Sel); NOREF(pszMsg);
1955	#endif
1956	}
1957
1958
1959	/**
1960	* Formats a full register dump.
1961	*
1962	* @param pVCpu The cross context virtual CPU structure.
1963	* @param pCtx Pointer to the CPU context.
1964	*/
1965	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu, PCPUMCTX pCtx)
1966	{
1967	/*
1968	* Format the flags.
1969	*/
1970	static struct
1971	{
1972	const char pszSet; const char pszClear; uint32_t fFlag;
1973	} const s_aFlags[] =
1974	{
1975	{ "vip", NULL, X86_EFL_VIP },
1976	{ "vif", NULL, X86_EFL_VIF },
1977	{ "ac", NULL, X86_EFL_AC },
1978	{ "vm", NULL, X86_EFL_VM },
1979	{ "rf", NULL, X86_EFL_RF },
1980	{ "nt", NULL, X86_EFL_NT },
1981	{ "ov", "nv", X86_EFL_OF },
1982	{ "dn", "up", X86_EFL_DF },
1983	{ "ei", "di", X86_EFL_IF },
1984	{ "tf", NULL, X86_EFL_TF },
1985	{ "nt", "pl", X86_EFL_SF },
1986	{ "nz", "zr", X86_EFL_ZF },
1987	{ "ac", "na", X86_EFL_AF },
1988	{ "po", "pe", X86_EFL_PF },
1989	{ "cy", "nc", X86_EFL_CF },
1990	};
1991	char szEFlags[80];
1992	char *psz = szEFlags;
1993	uint32_t uEFlags = pCtx->eflags.u32;
1994	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1995	{
1996	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1997	if (pszAdd)
1998	{
1999	strcpy(psz, pszAdd);
2000	psz += strlen(pszAdd);
2001	*psz++ = ' ';
2002	}
2003	}
2004	psz[-1] = '\0';
2005
2006	/*
2007	* Format the registers.
2008	*/
2009	if (CPUMIsGuestIn64BitCode(pVCpu))
2010	{
2011	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
2012	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
2013	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2014	"r14=%016RX64 r15=%016RX64\n"
2015	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
2016	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2017	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2018	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2019	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2020	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2021	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2022	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
2023	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
2024	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
2025	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2026	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2027	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2028	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2029	,
2030	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
2031	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
2032	pCtx->r14, pCtx->r15,
2033	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
2034	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2035	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2036	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2037	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2038	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2039	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2040	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
2041	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
2042	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2043	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
2044	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2045	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2046	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2047	}
2048	else
2049	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2050	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2051	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2052	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2053	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2054	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2055	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2056	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2057	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2058	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2059	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2060	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2061	,
2062	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2063	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
2064	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2065	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2066	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2067	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2068	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2069	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2070	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
2071	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2072	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2073	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2074
2075	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
2076	Log(("FPU:\n"
2077	"FCW=%04x FSW=%04x FTW=%02x\n"
2078	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2079	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2080	,
2081	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
2082	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
2083	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
2084	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
2085
2086	Log(("MSR:\n"
2087	"EFER =%016RX64\n"
2088	"PAT =%016RX64\n"
2089	"STAR =%016RX64\n"
2090	"CSTAR =%016RX64\n"
2091	"LSTAR =%016RX64\n"
2092	"SFMASK =%016RX64\n"
2093	"KERNELGSBASE =%016RX64\n",
2094	pCtx->msrEFER,
2095	pCtx->msrPAT,
2096	pCtx->msrSTAR,
2097	pCtx->msrCSTAR,
2098	pCtx->msrLSTAR,
2099	pCtx->msrSFMASK,
2100	pCtx->msrKERNELGSBASE));
2101
2102	NOREF(pFpuCtx);
2103	}
2104	#endif /* VBOX_STRICT */
2105

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 72963

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